Commit | Line | Data |
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386c036b | 1 | /* Target-dependent code for SPARC. |
cda5a58a | 2 | |
ecd75fc8 | 3 | Copyright (C) 2003-2014 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 19 | |
c906108c | 20 | #include "defs.h" |
5af923b0 | 21 | #include "arch-utils.h" |
386c036b | 22 | #include "dis-asm.h" |
f5a9b87d | 23 | #include "dwarf2-frame.h" |
386c036b | 24 | #include "floatformat.h" |
c906108c | 25 | #include "frame.h" |
386c036b MK |
26 | #include "frame-base.h" |
27 | #include "frame-unwind.h" | |
28 | #include "gdbcore.h" | |
29 | #include "gdbtypes.h" | |
c906108c | 30 | #include "inferior.h" |
386c036b MK |
31 | #include "symtab.h" |
32 | #include "objfiles.h" | |
33 | #include "osabi.h" | |
34 | #include "regcache.h" | |
c906108c SS |
35 | #include "target.h" |
36 | #include "value.h" | |
c906108c | 37 | |
43bd9a9e | 38 | #include "gdb_assert.h" |
0e9f083f | 39 | #include <string.h> |
c906108c | 40 | |
386c036b | 41 | #include "sparc-tdep.h" |
e6f9c00b | 42 | #include "sparc-ravenscar-thread.h" |
c906108c | 43 | |
a54124c5 MK |
44 | struct regset; |
45 | ||
9eb42ed1 MK |
46 | /* This file implements the SPARC 32-bit ABI as defined by the section |
47 | "Low-Level System Information" of the SPARC Compliance Definition | |
48 | (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD | |
f2e7c15d | 49 | lists changes with respect to the original 32-bit psABI as defined |
9eb42ed1 | 50 | in the "System V ABI, SPARC Processor Supplement". |
386c036b MK |
51 | |
52 | Note that if we talk about SunOS, we mean SunOS 4.x, which was | |
53 | BSD-based, which is sometimes (retroactively?) referred to as | |
54 | Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and | |
55 | above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 | |
56 | suffering from severe version number inflation). Solaris 2.x is | |
57 | also known as SunOS 5.x, since that's what uname(1) says. Solaris | |
58 | 2.x is SVR4-based. */ | |
59 | ||
60 | /* Please use the sparc32_-prefix for 32-bit specific code, the | |
61 | sparc64_-prefix for 64-bit specific code and the sparc_-prefix for | |
62 | code that can handle both. The 64-bit specific code lives in | |
63 | sparc64-tdep.c; don't add any here. */ | |
64 | ||
65 | /* The SPARC Floating-Point Quad-Precision format is similar to | |
7a58cce8 | 66 | big-endian IA-64 Quad-Precision format. */ |
8da61cc4 | 67 | #define floatformats_sparc_quad floatformats_ia64_quad |
386c036b MK |
68 | |
69 | /* The stack pointer is offset from the stack frame by a BIAS of 2047 | |
70 | (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC | |
71 | hosts, so undefine it first. */ | |
72 | #undef BIAS | |
73 | #define BIAS 2047 | |
74 | ||
75 | /* Macros to extract fields from SPARC instructions. */ | |
c906108c SS |
76 | #define X_OP(i) (((i) >> 30) & 0x3) |
77 | #define X_RD(i) (((i) >> 25) & 0x1f) | |
78 | #define X_A(i) (((i) >> 29) & 1) | |
79 | #define X_COND(i) (((i) >> 25) & 0xf) | |
80 | #define X_OP2(i) (((i) >> 22) & 0x7) | |
81 | #define X_IMM22(i) ((i) & 0x3fffff) | |
82 | #define X_OP3(i) (((i) >> 19) & 0x3f) | |
075ccec8 | 83 | #define X_RS1(i) (((i) >> 14) & 0x1f) |
b0b92586 | 84 | #define X_RS2(i) ((i) & 0x1f) |
c906108c | 85 | #define X_I(i) (((i) >> 13) & 1) |
c906108c | 86 | /* Sign extension macros. */ |
c906108c | 87 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) |
c906108c | 88 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) |
8d1b3521 | 89 | #define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200) |
075ccec8 | 90 | #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000) |
961842b2 JM |
91 | /* Macros to identify some instructions. */ |
92 | /* RETURN (RETT in V8) */ | |
93 | #define X_RETTURN(i) ((X_OP (i) == 0x2) && (X_OP3 (i) == 0x39)) | |
c906108c | 94 | |
386c036b MK |
95 | /* Fetch the instruction at PC. Instructions are always big-endian |
96 | even if the processor operates in little-endian mode. */ | |
97 | ||
98 | unsigned long | |
99 | sparc_fetch_instruction (CORE_ADDR pc) | |
c906108c | 100 | { |
e1613aba | 101 | gdb_byte buf[4]; |
386c036b MK |
102 | unsigned long insn; |
103 | int i; | |
104 | ||
690668cc | 105 | /* If we can't read the instruction at PC, return zero. */ |
8defab1a | 106 | if (target_read_memory (pc, buf, sizeof (buf))) |
690668cc | 107 | return 0; |
c906108c | 108 | |
386c036b MK |
109 | insn = 0; |
110 | for (i = 0; i < sizeof (buf); i++) | |
111 | insn = (insn << 8) | buf[i]; | |
112 | return insn; | |
113 | } | |
42cdca6c MK |
114 | \f |
115 | ||
5465445a JB |
116 | /* Return non-zero if the instruction corresponding to PC is an "unimp" |
117 | instruction. */ | |
118 | ||
119 | static int | |
120 | sparc_is_unimp_insn (CORE_ADDR pc) | |
121 | { | |
122 | const unsigned long insn = sparc_fetch_instruction (pc); | |
123 | ||
124 | return ((insn & 0xc1c00000) == 0); | |
125 | } | |
126 | ||
d0b5971a JM |
127 | /* Return non-zero if the instruction corresponding to PC is an |
128 | "annulled" branch, i.e. the annul bit is set. */ | |
129 | ||
130 | int | |
131 | sparc_is_annulled_branch_insn (CORE_ADDR pc) | |
132 | { | |
133 | /* The branch instructions featuring an annul bit can be identified | |
134 | by the following bit patterns: | |
135 | ||
136 | OP=0 | |
137 | OP2=1: Branch on Integer Condition Codes with Prediction (BPcc). | |
138 | OP2=2: Branch on Integer Condition Codes (Bcc). | |
139 | OP2=5: Branch on FP Condition Codes with Prediction (FBfcc). | |
140 | OP2=6: Branch on FP Condition Codes (FBcc). | |
141 | OP2=3 && Bit28=0: | |
142 | Branch on Integer Register with Prediction (BPr). | |
143 | ||
144 | This leaves out ILLTRAP (OP2=0), SETHI/NOP (OP2=4) and the V8 | |
145 | coprocessor branch instructions (Op2=7). */ | |
146 | ||
147 | const unsigned long insn = sparc_fetch_instruction (pc); | |
148 | const unsigned op2 = X_OP2 (insn); | |
149 | ||
150 | if ((X_OP (insn) == 0) | |
151 | && ((op2 == 1) || (op2 == 2) || (op2 == 5) || (op2 == 6) | |
152 | || ((op2 == 3) && ((insn & 0x10000000) == 0)))) | |
153 | return X_A (insn); | |
154 | else | |
155 | return 0; | |
156 | } | |
157 | ||
42cdca6c MK |
158 | /* OpenBSD/sparc includes StackGhost, which according to the author's |
159 | website http://stackghost.cerias.purdue.edu "... transparently and | |
160 | automatically protects applications' stack frames; more | |
161 | specifically, it guards the return pointers. The protection | |
162 | mechanisms require no application source or binary modification and | |
163 | imposes only a negligible performance penalty." | |
164 | ||
165 | The same website provides the following description of how | |
166 | StackGhost works: | |
167 | ||
168 | "StackGhost interfaces with the kernel trap handler that would | |
169 | normally write out registers to the stack and the handler that | |
170 | would read them back in. By XORing a cookie into the | |
171 | return-address saved in the user stack when it is actually written | |
172 | to the stack, and then XOR it out when the return-address is pulled | |
173 | from the stack, StackGhost can cause attacker corrupted return | |
174 | pointers to behave in a manner the attacker cannot predict. | |
175 | StackGhost can also use several unused bits in the return pointer | |
176 | to detect a smashed return pointer and abort the process." | |
177 | ||
178 | For GDB this means that whenever we're reading %i7 from a stack | |
179 | frame's window save area, we'll have to XOR the cookie. | |
180 | ||
181 | More information on StackGuard can be found on in: | |
182 | ||
c378eb4e | 183 | Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated |
42cdca6c MK |
184 | Stack Protection." 2001. Published in USENIX Security Symposium |
185 | '01. */ | |
186 | ||
187 | /* Fetch StackGhost Per-Process XOR cookie. */ | |
188 | ||
189 | ULONGEST | |
e17a4113 | 190 | sparc_fetch_wcookie (struct gdbarch *gdbarch) |
42cdca6c | 191 | { |
e17a4113 | 192 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
baf92889 | 193 | struct target_ops *ops = ¤t_target; |
e1613aba | 194 | gdb_byte buf[8]; |
baf92889 MK |
195 | int len; |
196 | ||
13547ab6 | 197 | len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8); |
baf92889 MK |
198 | if (len == -1) |
199 | return 0; | |
42cdca6c | 200 | |
baf92889 MK |
201 | /* We should have either an 32-bit or an 64-bit cookie. */ |
202 | gdb_assert (len == 4 || len == 8); | |
203 | ||
e17a4113 | 204 | return extract_unsigned_integer (buf, len, byte_order); |
baf92889 | 205 | } |
386c036b | 206 | \f |
baf92889 | 207 | |
386c036b MK |
208 | /* The functions on this page are intended to be used to classify |
209 | function arguments. */ | |
c906108c | 210 | |
386c036b | 211 | /* Check whether TYPE is "Integral or Pointer". */ |
c906108c | 212 | |
386c036b MK |
213 | static int |
214 | sparc_integral_or_pointer_p (const struct type *type) | |
c906108c | 215 | { |
80ad1639 MK |
216 | int len = TYPE_LENGTH (type); |
217 | ||
386c036b | 218 | switch (TYPE_CODE (type)) |
c906108c | 219 | { |
386c036b MK |
220 | case TYPE_CODE_INT: |
221 | case TYPE_CODE_BOOL: | |
222 | case TYPE_CODE_CHAR: | |
223 | case TYPE_CODE_ENUM: | |
224 | case TYPE_CODE_RANGE: | |
80ad1639 MK |
225 | /* We have byte, half-word, word and extended-word/doubleword |
226 | integral types. The doubleword is an extension to the | |
227 | original 32-bit ABI by the SCD 2.4.x. */ | |
228 | return (len == 1 || len == 2 || len == 4 || len == 8); | |
386c036b MK |
229 | case TYPE_CODE_PTR: |
230 | case TYPE_CODE_REF: | |
80ad1639 MK |
231 | /* Allow either 32-bit or 64-bit pointers. */ |
232 | return (len == 4 || len == 8); | |
386c036b MK |
233 | default: |
234 | break; | |
235 | } | |
c906108c | 236 | |
386c036b MK |
237 | return 0; |
238 | } | |
c906108c | 239 | |
386c036b | 240 | /* Check whether TYPE is "Floating". */ |
c906108c | 241 | |
386c036b MK |
242 | static int |
243 | sparc_floating_p (const struct type *type) | |
244 | { | |
245 | switch (TYPE_CODE (type)) | |
c906108c | 246 | { |
386c036b MK |
247 | case TYPE_CODE_FLT: |
248 | { | |
249 | int len = TYPE_LENGTH (type); | |
250 | return (len == 4 || len == 8 || len == 16); | |
251 | } | |
252 | default: | |
253 | break; | |
254 | } | |
255 | ||
256 | return 0; | |
257 | } | |
c906108c | 258 | |
fe10a582 DM |
259 | /* Check whether TYPE is "Complex Floating". */ |
260 | ||
261 | static int | |
262 | sparc_complex_floating_p (const struct type *type) | |
263 | { | |
264 | switch (TYPE_CODE (type)) | |
265 | { | |
266 | case TYPE_CODE_COMPLEX: | |
267 | { | |
268 | int len = TYPE_LENGTH (type); | |
269 | return (len == 8 || len == 16 || len == 32); | |
270 | } | |
271 | default: | |
272 | break; | |
273 | } | |
274 | ||
275 | return 0; | |
276 | } | |
277 | ||
0497f5b0 JB |
278 | /* Check whether TYPE is "Structure or Union". |
279 | ||
280 | In terms of Ada subprogram calls, arrays are treated the same as | |
281 | struct and union types. So this function also returns non-zero | |
282 | for array types. */ | |
c906108c | 283 | |
386c036b MK |
284 | static int |
285 | sparc_structure_or_union_p (const struct type *type) | |
286 | { | |
287 | switch (TYPE_CODE (type)) | |
288 | { | |
289 | case TYPE_CODE_STRUCT: | |
290 | case TYPE_CODE_UNION: | |
0497f5b0 | 291 | case TYPE_CODE_ARRAY: |
386c036b MK |
292 | return 1; |
293 | default: | |
294 | break; | |
c906108c | 295 | } |
386c036b MK |
296 | |
297 | return 0; | |
c906108c | 298 | } |
386c036b MK |
299 | |
300 | /* Register information. */ | |
301 | ||
302 | static const char *sparc32_register_names[] = | |
5af923b0 | 303 | { |
386c036b MK |
304 | "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
305 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", | |
306 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", | |
307 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", | |
308 | ||
309 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
310 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
311 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
312 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
313 | ||
314 | "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" | |
5af923b0 MS |
315 | }; |
316 | ||
386c036b MK |
317 | /* Total number of registers. */ |
318 | #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) | |
c906108c | 319 | |
386c036b MK |
320 | /* We provide the aliases %d0..%d30 for the floating registers as |
321 | "psuedo" registers. */ | |
322 | ||
323 | static const char *sparc32_pseudo_register_names[] = | |
324 | { | |
325 | "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", | |
326 | "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" | |
327 | }; | |
328 | ||
329 | /* Total number of pseudo registers. */ | |
330 | #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) | |
331 | ||
332 | /* Return the name of register REGNUM. */ | |
333 | ||
334 | static const char * | |
d93859e2 | 335 | sparc32_register_name (struct gdbarch *gdbarch, int regnum) |
386c036b MK |
336 | { |
337 | if (regnum >= 0 && regnum < SPARC32_NUM_REGS) | |
338 | return sparc32_register_names[regnum]; | |
339 | ||
340 | if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS) | |
341 | return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS]; | |
342 | ||
343 | return NULL; | |
344 | } | |
2d457077 | 345 | \f |
209bd28e | 346 | /* Construct types for ISA-specific registers. */ |
2d457077 | 347 | |
209bd28e UW |
348 | static struct type * |
349 | sparc_psr_type (struct gdbarch *gdbarch) | |
350 | { | |
351 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2d457077 | 352 | |
209bd28e UW |
353 | if (!tdep->sparc_psr_type) |
354 | { | |
355 | struct type *type; | |
2d457077 | 356 | |
e9bb382b | 357 | type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 4); |
209bd28e UW |
358 | append_flags_type_flag (type, 5, "ET"); |
359 | append_flags_type_flag (type, 6, "PS"); | |
360 | append_flags_type_flag (type, 7, "S"); | |
361 | append_flags_type_flag (type, 12, "EF"); | |
362 | append_flags_type_flag (type, 13, "EC"); | |
2d457077 | 363 | |
209bd28e UW |
364 | tdep->sparc_psr_type = type; |
365 | } | |
366 | ||
367 | return tdep->sparc_psr_type; | |
368 | } | |
369 | ||
370 | static struct type * | |
371 | sparc_fsr_type (struct gdbarch *gdbarch) | |
2d457077 | 372 | { |
209bd28e UW |
373 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
374 | ||
375 | if (!tdep->sparc_fsr_type) | |
376 | { | |
377 | struct type *type; | |
378 | ||
e9bb382b | 379 | type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 4); |
209bd28e UW |
380 | append_flags_type_flag (type, 0, "NXA"); |
381 | append_flags_type_flag (type, 1, "DZA"); | |
382 | append_flags_type_flag (type, 2, "UFA"); | |
383 | append_flags_type_flag (type, 3, "OFA"); | |
384 | append_flags_type_flag (type, 4, "NVA"); | |
385 | append_flags_type_flag (type, 5, "NXC"); | |
386 | append_flags_type_flag (type, 6, "DZC"); | |
387 | append_flags_type_flag (type, 7, "UFC"); | |
388 | append_flags_type_flag (type, 8, "OFC"); | |
389 | append_flags_type_flag (type, 9, "NVC"); | |
390 | append_flags_type_flag (type, 22, "NS"); | |
391 | append_flags_type_flag (type, 23, "NXM"); | |
392 | append_flags_type_flag (type, 24, "DZM"); | |
393 | append_flags_type_flag (type, 25, "UFM"); | |
394 | append_flags_type_flag (type, 26, "OFM"); | |
395 | append_flags_type_flag (type, 27, "NVM"); | |
396 | ||
397 | tdep->sparc_fsr_type = type; | |
398 | } | |
399 | ||
400 | return tdep->sparc_fsr_type; | |
2d457077 | 401 | } |
386c036b MK |
402 | |
403 | /* Return the GDB type object for the "standard" data type of data in | |
c378eb4e | 404 | register REGNUM. */ |
386c036b MK |
405 | |
406 | static struct type * | |
407 | sparc32_register_type (struct gdbarch *gdbarch, int regnum) | |
408 | { | |
409 | if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) | |
0dfff4cb | 410 | return builtin_type (gdbarch)->builtin_float; |
386c036b MK |
411 | |
412 | if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) | |
0dfff4cb | 413 | return builtin_type (gdbarch)->builtin_double; |
386c036b MK |
414 | |
415 | if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) | |
0dfff4cb | 416 | return builtin_type (gdbarch)->builtin_data_ptr; |
386c036b MK |
417 | |
418 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) | |
0dfff4cb | 419 | return builtin_type (gdbarch)->builtin_func_ptr; |
386c036b | 420 | |
2d457077 | 421 | if (regnum == SPARC32_PSR_REGNUM) |
209bd28e | 422 | return sparc_psr_type (gdbarch); |
2d457077 MK |
423 | |
424 | if (regnum == SPARC32_FSR_REGNUM) | |
209bd28e | 425 | return sparc_fsr_type (gdbarch); |
2d457077 | 426 | |
df4df182 | 427 | return builtin_type (gdbarch)->builtin_int32; |
386c036b MK |
428 | } |
429 | ||
05d1431c | 430 | static enum register_status |
386c036b MK |
431 | sparc32_pseudo_register_read (struct gdbarch *gdbarch, |
432 | struct regcache *regcache, | |
e1613aba | 433 | int regnum, gdb_byte *buf) |
386c036b | 434 | { |
05d1431c PA |
435 | enum register_status status; |
436 | ||
386c036b MK |
437 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); |
438 | ||
439 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
05d1431c PA |
440 | status = regcache_raw_read (regcache, regnum, buf); |
441 | if (status == REG_VALID) | |
442 | status = regcache_raw_read (regcache, regnum + 1, buf + 4); | |
443 | return status; | |
386c036b MK |
444 | } |
445 | ||
446 | static void | |
447 | sparc32_pseudo_register_write (struct gdbarch *gdbarch, | |
448 | struct regcache *regcache, | |
e1613aba | 449 | int regnum, const gdb_byte *buf) |
386c036b MK |
450 | { |
451 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); | |
452 | ||
453 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
454 | regcache_raw_write (regcache, regnum, buf); | |
e1613aba | 455 | regcache_raw_write (regcache, regnum + 1, buf + 4); |
386c036b MK |
456 | } |
457 | \f | |
961842b2 JM |
458 | /* Implement "in_function_epilogue_p". */ |
459 | ||
460 | int | |
461 | sparc_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
462 | { | |
463 | /* This function must return true if we are one instruction after an | |
464 | instruction that destroyed the stack frame of the current | |
465 | function. The SPARC instructions used to restore the callers | |
466 | stack frame are RESTORE and RETURN/RETT. | |
467 | ||
468 | Of these RETURN/RETT is a branch instruction and thus we return | |
469 | true if we are in its delay slot. | |
470 | ||
471 | RESTORE is almost always found in the delay slot of a branch | |
472 | instruction that transfers control to the caller, such as JMPL. | |
473 | Thus the next instruction is in the caller frame and we don't | |
474 | need to do anything about it. */ | |
475 | ||
476 | unsigned int insn = sparc_fetch_instruction (pc - 4); | |
477 | ||
478 | return X_RETTURN (insn); | |
479 | } | |
480 | \f | |
386c036b | 481 | |
49a45ecf JB |
482 | static CORE_ADDR |
483 | sparc32_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) | |
484 | { | |
485 | /* The ABI requires double-word alignment. */ | |
486 | return address & ~0x7; | |
487 | } | |
488 | ||
386c036b MK |
489 | static CORE_ADDR |
490 | sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
82585c72 | 491 | CORE_ADDR funcaddr, |
386c036b MK |
492 | struct value **args, int nargs, |
493 | struct type *value_type, | |
e4fd649a UW |
494 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, |
495 | struct regcache *regcache) | |
c906108c | 496 | { |
e17a4113 UW |
497 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
498 | ||
386c036b MK |
499 | *bp_addr = sp - 4; |
500 | *real_pc = funcaddr; | |
501 | ||
d80b854b | 502 | if (using_struct_return (gdbarch, NULL, value_type)) |
c906108c | 503 | { |
e1613aba | 504 | gdb_byte buf[4]; |
386c036b MK |
505 | |
506 | /* This is an UNIMP instruction. */ | |
e17a4113 UW |
507 | store_unsigned_integer (buf, 4, byte_order, |
508 | TYPE_LENGTH (value_type) & 0x1fff); | |
386c036b MK |
509 | write_memory (sp - 8, buf, 4); |
510 | return sp - 8; | |
c906108c SS |
511 | } |
512 | ||
386c036b MK |
513 | return sp - 4; |
514 | } | |
515 | ||
516 | static CORE_ADDR | |
517 | sparc32_store_arguments (struct regcache *regcache, int nargs, | |
518 | struct value **args, CORE_ADDR sp, | |
519 | int struct_return, CORE_ADDR struct_addr) | |
520 | { | |
df4df182 | 521 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
e17a4113 | 522 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
386c036b MK |
523 | /* Number of words in the "parameter array". */ |
524 | int num_elements = 0; | |
525 | int element = 0; | |
526 | int i; | |
527 | ||
528 | for (i = 0; i < nargs; i++) | |
c906108c | 529 | { |
4991999e | 530 | struct type *type = value_type (args[i]); |
386c036b MK |
531 | int len = TYPE_LENGTH (type); |
532 | ||
533 | if (sparc_structure_or_union_p (type) | |
fe10a582 DM |
534 | || (sparc_floating_p (type) && len == 16) |
535 | || sparc_complex_floating_p (type)) | |
c906108c | 536 | { |
386c036b MK |
537 | /* Structure, Union and Quad-Precision Arguments. */ |
538 | sp -= len; | |
539 | ||
540 | /* Use doubleword alignment for these values. That's always | |
541 | correct, and wasting a few bytes shouldn't be a problem. */ | |
542 | sp &= ~0x7; | |
543 | ||
0fd88904 | 544 | write_memory (sp, value_contents (args[i]), len); |
386c036b MK |
545 | args[i] = value_from_pointer (lookup_pointer_type (type), sp); |
546 | num_elements++; | |
547 | } | |
548 | else if (sparc_floating_p (type)) | |
549 | { | |
550 | /* Floating arguments. */ | |
551 | gdb_assert (len == 4 || len == 8); | |
552 | num_elements += (len / 4); | |
c906108c | 553 | } |
c5aa993b JM |
554 | else |
555 | { | |
386c036b MK |
556 | /* Integral and pointer arguments. */ |
557 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
558 | ||
559 | if (len < 4) | |
df4df182 UW |
560 | args[i] = value_cast (builtin_type (gdbarch)->builtin_int32, |
561 | args[i]); | |
386c036b | 562 | num_elements += ((len + 3) / 4); |
c5aa993b | 563 | } |
c906108c | 564 | } |
c906108c | 565 | |
386c036b MK |
566 | /* Always allocate at least six words. */ |
567 | sp -= max (6, num_elements) * 4; | |
c906108c | 568 | |
386c036b MK |
569 | /* The psABI says that "Software convention requires space for the |
570 | struct/union return value pointer, even if the word is unused." */ | |
571 | sp -= 4; | |
c906108c | 572 | |
386c036b MK |
573 | /* The psABI says that "Although software convention and the |
574 | operating system require every stack frame to be doubleword | |
575 | aligned." */ | |
576 | sp &= ~0x7; | |
c906108c | 577 | |
386c036b | 578 | for (i = 0; i < nargs; i++) |
c906108c | 579 | { |
0fd88904 | 580 | const bfd_byte *valbuf = value_contents (args[i]); |
4991999e | 581 | struct type *type = value_type (args[i]); |
386c036b | 582 | int len = TYPE_LENGTH (type); |
c906108c | 583 | |
386c036b | 584 | gdb_assert (len == 4 || len == 8); |
c906108c | 585 | |
386c036b MK |
586 | if (element < 6) |
587 | { | |
588 | int regnum = SPARC_O0_REGNUM + element; | |
c906108c | 589 | |
386c036b MK |
590 | regcache_cooked_write (regcache, regnum, valbuf); |
591 | if (len > 4 && element < 5) | |
592 | regcache_cooked_write (regcache, regnum + 1, valbuf + 4); | |
593 | } | |
5af923b0 | 594 | |
386c036b MK |
595 | /* Always store the argument in memory. */ |
596 | write_memory (sp + 4 + element * 4, valbuf, len); | |
597 | element += len / 4; | |
598 | } | |
c906108c | 599 | |
386c036b | 600 | gdb_assert (element == num_elements); |
c906108c | 601 | |
386c036b | 602 | if (struct_return) |
c906108c | 603 | { |
e1613aba | 604 | gdb_byte buf[4]; |
c906108c | 605 | |
e17a4113 | 606 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
386c036b MK |
607 | write_memory (sp, buf, 4); |
608 | } | |
c906108c | 609 | |
386c036b | 610 | return sp; |
c906108c SS |
611 | } |
612 | ||
386c036b | 613 | static CORE_ADDR |
7d9b040b | 614 | sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
386c036b MK |
615 | struct regcache *regcache, CORE_ADDR bp_addr, |
616 | int nargs, struct value **args, CORE_ADDR sp, | |
617 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 618 | { |
386c036b MK |
619 | CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8)); |
620 | ||
621 | /* Set return address. */ | |
622 | regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); | |
623 | ||
624 | /* Set up function arguments. */ | |
625 | sp = sparc32_store_arguments (regcache, nargs, args, sp, | |
626 | struct_return, struct_addr); | |
627 | ||
628 | /* Allocate the 16-word window save area. */ | |
629 | sp -= 16 * 4; | |
c906108c | 630 | |
386c036b MK |
631 | /* Stack should be doubleword aligned at this point. */ |
632 | gdb_assert (sp % 8 == 0); | |
c906108c | 633 | |
386c036b MK |
634 | /* Finally, update the stack pointer. */ |
635 | regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); | |
636 | ||
637 | return sp; | |
638 | } | |
639 | \f | |
c906108c | 640 | |
386c036b MK |
641 | /* Use the program counter to determine the contents and size of a |
642 | breakpoint instruction. Return a pointer to a string of bytes that | |
643 | encode a breakpoint instruction, store the length of the string in | |
644 | *LEN and optionally adjust *PC to point to the correct memory | |
645 | location for inserting the breakpoint. */ | |
646 | ||
e1613aba | 647 | static const gdb_byte * |
67d57894 | 648 | sparc_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
386c036b | 649 | { |
864a1a37 | 650 | static const gdb_byte break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; |
c5aa993b | 651 | |
386c036b MK |
652 | *len = sizeof (break_insn); |
653 | return break_insn; | |
c906108c | 654 | } |
386c036b | 655 | \f |
c906108c | 656 | |
386c036b | 657 | /* Allocate and initialize a frame cache. */ |
c906108c | 658 | |
386c036b MK |
659 | static struct sparc_frame_cache * |
660 | sparc_alloc_frame_cache (void) | |
661 | { | |
662 | struct sparc_frame_cache *cache; | |
c906108c | 663 | |
386c036b | 664 | cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); |
c906108c | 665 | |
386c036b MK |
666 | /* Base address. */ |
667 | cache->base = 0; | |
668 | cache->pc = 0; | |
c906108c | 669 | |
386c036b MK |
670 | /* Frameless until proven otherwise. */ |
671 | cache->frameless_p = 1; | |
369c397b JB |
672 | cache->frame_offset = 0; |
673 | cache->saved_regs_mask = 0; | |
674 | cache->copied_regs_mask = 0; | |
386c036b MK |
675 | cache->struct_return_p = 0; |
676 | ||
677 | return cache; | |
678 | } | |
679 | ||
b0b92586 JB |
680 | /* GCC generates several well-known sequences of instructions at the begining |
681 | of each function prologue when compiling with -fstack-check. If one of | |
682 | such sequences starts at START_PC, then return the address of the | |
683 | instruction immediately past this sequence. Otherwise, return START_PC. */ | |
684 | ||
685 | static CORE_ADDR | |
686 | sparc_skip_stack_check (const CORE_ADDR start_pc) | |
687 | { | |
688 | CORE_ADDR pc = start_pc; | |
689 | unsigned long insn; | |
690 | int offset_stack_checking_sequence = 0; | |
2067c8d4 | 691 | int probing_loop = 0; |
b0b92586 JB |
692 | |
693 | /* With GCC, all stack checking sequences begin with the same two | |
2067c8d4 | 694 | instructions, plus an optional one in the case of a probing loop: |
b0b92586 | 695 | |
2067c8d4 JG |
696 | sethi <some immediate>, %g1 |
697 | sub %sp, %g1, %g1 | |
698 | ||
699 | or: | |
700 | ||
701 | sethi <some immediate>, %g1 | |
702 | sethi <some immediate>, %g4 | |
703 | sub %sp, %g1, %g1 | |
704 | ||
705 | or: | |
706 | ||
707 | sethi <some immediate>, %g1 | |
708 | sub %sp, %g1, %g1 | |
709 | sethi <some immediate>, %g4 | |
710 | ||
711 | If the optional instruction is found (setting g4), assume that a | |
712 | probing loop will follow. */ | |
713 | ||
714 | /* sethi <some immediate>, %g1 */ | |
b0b92586 JB |
715 | insn = sparc_fetch_instruction (pc); |
716 | pc = pc + 4; | |
717 | if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1)) | |
718 | return start_pc; | |
719 | ||
2067c8d4 | 720 | /* optional: sethi <some immediate>, %g4 */ |
b0b92586 JB |
721 | insn = sparc_fetch_instruction (pc); |
722 | pc = pc + 4; | |
2067c8d4 JG |
723 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) |
724 | { | |
725 | probing_loop = 1; | |
726 | insn = sparc_fetch_instruction (pc); | |
727 | pc = pc + 4; | |
728 | } | |
729 | ||
730 | /* sub %sp, %g1, %g1 */ | |
b0b92586 JB |
731 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) |
732 | && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1)) | |
733 | return start_pc; | |
734 | ||
735 | insn = sparc_fetch_instruction (pc); | |
736 | pc = pc + 4; | |
737 | ||
2067c8d4 JG |
738 | /* optional: sethi <some immediate>, %g4 */ |
739 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) | |
740 | { | |
741 | probing_loop = 1; | |
742 | insn = sparc_fetch_instruction (pc); | |
743 | pc = pc + 4; | |
744 | } | |
745 | ||
b0b92586 JB |
746 | /* First possible sequence: |
747 | [first two instructions above] | |
748 | clr [%g1 - some immediate] */ | |
749 | ||
750 | /* clr [%g1 - some immediate] */ | |
751 | if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
752 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
753 | { | |
754 | /* Valid stack-check sequence, return the new PC. */ | |
755 | return pc; | |
756 | } | |
757 | ||
758 | /* Second possible sequence: A small number of probes. | |
759 | [first two instructions above] | |
760 | clr [%g1] | |
761 | add %g1, -<some immediate>, %g1 | |
762 | clr [%g1] | |
763 | [repeat the two instructions above any (small) number of times] | |
764 | clr [%g1 - some immediate] */ | |
765 | ||
766 | /* clr [%g1] */ | |
767 | else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
768 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
769 | { | |
770 | while (1) | |
771 | { | |
772 | /* add %g1, -<some immediate>, %g1 */ | |
773 | insn = sparc_fetch_instruction (pc); | |
774 | pc = pc + 4; | |
775 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
776 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
777 | break; | |
778 | ||
779 | /* clr [%g1] */ | |
780 | insn = sparc_fetch_instruction (pc); | |
781 | pc = pc + 4; | |
782 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
783 | && X_RD (insn) == 0 && X_RS1 (insn) == 1)) | |
784 | return start_pc; | |
785 | } | |
786 | ||
787 | /* clr [%g1 - some immediate] */ | |
788 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
789 | && X_RS1 (insn) == 1 && X_RD (insn) == 0)) | |
790 | return start_pc; | |
791 | ||
792 | /* We found a valid stack-check sequence, return the new PC. */ | |
793 | return pc; | |
794 | } | |
795 | ||
796 | /* Third sequence: A probing loop. | |
2067c8d4 | 797 | [first three instructions above] |
b0b92586 JB |
798 | sub %g1, %g4, %g4 |
799 | cmp %g1, %g4 | |
800 | be <disp> | |
801 | add %g1, -<some immediate>, %g1 | |
802 | ba <disp> | |
803 | clr [%g1] | |
2067c8d4 JG |
804 | |
805 | And an optional last probe for the remainder: | |
806 | ||
b0b92586 JB |
807 | clr [%g4 - some immediate] */ |
808 | ||
2067c8d4 | 809 | if (probing_loop) |
b0b92586 JB |
810 | { |
811 | /* sub %g1, %g4, %g4 */ | |
b0b92586 JB |
812 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) |
813 | && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
814 | return start_pc; | |
815 | ||
816 | /* cmp %g1, %g4 */ | |
817 | insn = sparc_fetch_instruction (pc); | |
818 | pc = pc + 4; | |
819 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn) | |
820 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
821 | return start_pc; | |
822 | ||
823 | /* be <disp> */ | |
824 | insn = sparc_fetch_instruction (pc); | |
825 | pc = pc + 4; | |
826 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1)) | |
827 | return start_pc; | |
828 | ||
829 | /* add %g1, -<some immediate>, %g1 */ | |
830 | insn = sparc_fetch_instruction (pc); | |
831 | pc = pc + 4; | |
832 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
833 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
834 | return start_pc; | |
835 | ||
836 | /* ba <disp> */ | |
837 | insn = sparc_fetch_instruction (pc); | |
838 | pc = pc + 4; | |
839 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8)) | |
840 | return start_pc; | |
841 | ||
2067c8d4 | 842 | /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */ |
b0b92586 JB |
843 | insn = sparc_fetch_instruction (pc); |
844 | pc = pc + 4; | |
2067c8d4 JG |
845 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 |
846 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 | |
847 | && (!X_I(insn) || X_SIMM13 (insn) == 0))) | |
b0b92586 JB |
848 | return start_pc; |
849 | ||
2067c8d4 JG |
850 | /* We found a valid stack-check sequence, return the new PC. */ |
851 | ||
852 | /* optional: clr [%g4 - some immediate] */ | |
b0b92586 JB |
853 | insn = sparc_fetch_instruction (pc); |
854 | pc = pc + 4; | |
855 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
856 | && X_RS1 (insn) == 4 && X_RD (insn) == 0)) | |
2067c8d4 JG |
857 | return pc - 4; |
858 | else | |
859 | return pc; | |
b0b92586 JB |
860 | } |
861 | ||
862 | /* No stack check code in our prologue, return the start_pc. */ | |
863 | return start_pc; | |
864 | } | |
865 | ||
369c397b JB |
866 | /* Record the effect of a SAVE instruction on CACHE. */ |
867 | ||
868 | void | |
869 | sparc_record_save_insn (struct sparc_frame_cache *cache) | |
870 | { | |
871 | /* The frame is set up. */ | |
872 | cache->frameless_p = 0; | |
873 | ||
874 | /* The frame pointer contains the CFA. */ | |
875 | cache->frame_offset = 0; | |
876 | ||
877 | /* The `local' and `in' registers are all saved. */ | |
878 | cache->saved_regs_mask = 0xffff; | |
879 | ||
880 | /* The `out' registers are all renamed. */ | |
881 | cache->copied_regs_mask = 0xff; | |
882 | } | |
883 | ||
884 | /* Do a full analysis of the prologue at PC and update CACHE accordingly. | |
885 | Bail out early if CURRENT_PC is reached. Return the address where | |
886 | the analysis stopped. | |
887 | ||
888 | We handle both the traditional register window model and the single | |
889 | register window (aka flat) model. */ | |
890 | ||
386c036b | 891 | CORE_ADDR |
be8626e0 MD |
892 | sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, |
893 | CORE_ADDR current_pc, struct sparc_frame_cache *cache) | |
c906108c | 894 | { |
be8626e0 | 895 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
386c036b MK |
896 | unsigned long insn; |
897 | int offset = 0; | |
c906108c | 898 | int dest = -1; |
c906108c | 899 | |
b0b92586 JB |
900 | pc = sparc_skip_stack_check (pc); |
901 | ||
386c036b MK |
902 | if (current_pc <= pc) |
903 | return current_pc; | |
904 | ||
905 | /* We have to handle to "Procedure Linkage Table" (PLT) special. On | |
906 | SPARC the linker usually defines a symbol (typically | |
907 | _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. | |
908 | This symbol makes us end up here with PC pointing at the start of | |
909 | the PLT and CURRENT_PC probably pointing at a PLT entry. If we | |
910 | would do our normal prologue analysis, we would probably conclude | |
911 | that we've got a frame when in reality we don't, since the | |
912 | dynamic linker patches up the first PLT with some code that | |
913 | starts with a SAVE instruction. Patch up PC such that it points | |
914 | at the start of our PLT entry. */ | |
3e5d3a5a | 915 | if (tdep->plt_entry_size > 0 && in_plt_section (current_pc)) |
386c036b | 916 | pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); |
c906108c | 917 | |
386c036b MK |
918 | insn = sparc_fetch_instruction (pc); |
919 | ||
369c397b JB |
920 | /* Recognize store insns and record their sources. */ |
921 | while (X_OP (insn) == 3 | |
922 | && (X_OP3 (insn) == 0x4 /* stw */ | |
923 | || X_OP3 (insn) == 0x7 /* std */ | |
924 | || X_OP3 (insn) == 0xe) /* stx */ | |
925 | && X_RS1 (insn) == SPARC_SP_REGNUM) | |
926 | { | |
927 | int regnum = X_RD (insn); | |
928 | ||
929 | /* Recognize stores into the corresponding stack slots. */ | |
930 | if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM | |
931 | && ((X_I (insn) | |
932 | && X_SIMM13 (insn) == (X_OP3 (insn) == 0xe | |
933 | ? (regnum - SPARC_L0_REGNUM) * 8 + BIAS | |
934 | : (regnum - SPARC_L0_REGNUM) * 4)) | |
935 | || (!X_I (insn) && regnum == SPARC_L0_REGNUM))) | |
936 | { | |
937 | cache->saved_regs_mask |= (1 << (regnum - SPARC_L0_REGNUM)); | |
938 | if (X_OP3 (insn) == 0x7) | |
939 | cache->saved_regs_mask |= (1 << (regnum + 1 - SPARC_L0_REGNUM)); | |
940 | } | |
941 | ||
942 | offset += 4; | |
943 | ||
944 | insn = sparc_fetch_instruction (pc + offset); | |
945 | } | |
946 | ||
386c036b MK |
947 | /* Recognize a SETHI insn and record its destination. */ |
948 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) | |
c906108c SS |
949 | { |
950 | dest = X_RD (insn); | |
386c036b MK |
951 | offset += 4; |
952 | ||
369c397b | 953 | insn = sparc_fetch_instruction (pc + offset); |
c906108c SS |
954 | } |
955 | ||
386c036b MK |
956 | /* Allow for an arithmetic operation on DEST or %g1. */ |
957 | if (X_OP (insn) == 2 && X_I (insn) | |
c906108c SS |
958 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) |
959 | { | |
386c036b | 960 | offset += 4; |
c906108c | 961 | |
369c397b | 962 | insn = sparc_fetch_instruction (pc + offset); |
c906108c | 963 | } |
c906108c | 964 | |
386c036b MK |
965 | /* Check for the SAVE instruction that sets up the frame. */ |
966 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) | |
c906108c | 967 | { |
369c397b JB |
968 | sparc_record_save_insn (cache); |
969 | offset += 4; | |
970 | return pc + offset; | |
971 | } | |
972 | ||
973 | /* Check for an arithmetic operation on %sp. */ | |
974 | if (X_OP (insn) == 2 | |
975 | && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) | |
976 | && X_RS1 (insn) == SPARC_SP_REGNUM | |
977 | && X_RD (insn) == SPARC_SP_REGNUM) | |
978 | { | |
979 | if (X_I (insn)) | |
980 | { | |
981 | cache->frame_offset = X_SIMM13 (insn); | |
982 | if (X_OP3 (insn) == 0) | |
983 | cache->frame_offset = -cache->frame_offset; | |
984 | } | |
985 | offset += 4; | |
986 | ||
987 | insn = sparc_fetch_instruction (pc + offset); | |
988 | ||
989 | /* Check for an arithmetic operation that sets up the frame. */ | |
990 | if (X_OP (insn) == 2 | |
991 | && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) | |
992 | && X_RS1 (insn) == SPARC_SP_REGNUM | |
993 | && X_RD (insn) == SPARC_FP_REGNUM) | |
994 | { | |
995 | cache->frameless_p = 0; | |
996 | cache->frame_offset = 0; | |
997 | /* We could check that the amount subtracted to %sp above is the | |
998 | same as the one added here, but this seems superfluous. */ | |
999 | cache->copied_regs_mask |= 0x40; | |
1000 | offset += 4; | |
1001 | ||
1002 | insn = sparc_fetch_instruction (pc + offset); | |
1003 | } | |
1004 | ||
1005 | /* Check for a move (or) operation that copies the return register. */ | |
1006 | if (X_OP (insn) == 2 | |
1007 | && X_OP3 (insn) == 0x2 | |
1008 | && !X_I (insn) | |
1009 | && X_RS1 (insn) == SPARC_G0_REGNUM | |
1010 | && X_RS2 (insn) == SPARC_O7_REGNUM | |
1011 | && X_RD (insn) == SPARC_I7_REGNUM) | |
1012 | { | |
1013 | cache->copied_regs_mask |= 0x80; | |
1014 | offset += 4; | |
1015 | } | |
1016 | ||
1017 | return pc + offset; | |
c906108c SS |
1018 | } |
1019 | ||
1020 | return pc; | |
1021 | } | |
1022 | ||
386c036b | 1023 | static CORE_ADDR |
236369e7 | 1024 | sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) |
386c036b MK |
1025 | { |
1026 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
236369e7 | 1027 | return frame_unwind_register_unsigned (this_frame, tdep->pc_regnum); |
386c036b MK |
1028 | } |
1029 | ||
1030 | /* Return PC of first real instruction of the function starting at | |
1031 | START_PC. */ | |
f510d44e | 1032 | |
386c036b | 1033 | static CORE_ADDR |
6093d2eb | 1034 | sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1035 | { |
f510d44e DM |
1036 | struct symtab_and_line sal; |
1037 | CORE_ADDR func_start, func_end; | |
386c036b | 1038 | struct sparc_frame_cache cache; |
f510d44e DM |
1039 | |
1040 | /* This is the preferred method, find the end of the prologue by | |
1041 | using the debugging information. */ | |
1042 | if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) | |
1043 | { | |
1044 | sal = find_pc_line (func_start, 0); | |
1045 | ||
1046 | if (sal.end < func_end | |
1047 | && start_pc <= sal.end) | |
1048 | return sal.end; | |
1049 | } | |
1050 | ||
be8626e0 | 1051 | start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache); |
075ccec8 MK |
1052 | |
1053 | /* The psABI says that "Although the first 6 words of arguments | |
1054 | reside in registers, the standard stack frame reserves space for | |
1055 | them.". It also suggests that a function may use that space to | |
1056 | "write incoming arguments 0 to 5" into that space, and that's | |
1057 | indeed what GCC seems to be doing. In that case GCC will | |
1058 | generate debug information that points to the stack slots instead | |
1059 | of the registers, so we should consider the instructions that | |
369c397b | 1060 | write out these incoming arguments onto the stack. */ |
075ccec8 | 1061 | |
369c397b | 1062 | while (1) |
075ccec8 MK |
1063 | { |
1064 | unsigned long insn = sparc_fetch_instruction (start_pc); | |
1065 | ||
369c397b JB |
1066 | /* Recognize instructions that store incoming arguments into the |
1067 | corresponding stack slots. */ | |
1068 | if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 | |
1069 | && X_I (insn) && X_RS1 (insn) == SPARC_FP_REGNUM) | |
075ccec8 | 1070 | { |
369c397b JB |
1071 | int regnum = X_RD (insn); |
1072 | ||
1073 | /* Case of arguments still in %o[0..5]. */ | |
1074 | if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O5_REGNUM | |
1075 | && !(cache.copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM))) | |
1076 | && X_SIMM13 (insn) == 68 + (regnum - SPARC_O0_REGNUM) * 4) | |
1077 | { | |
1078 | start_pc += 4; | |
1079 | continue; | |
1080 | } | |
1081 | ||
1082 | /* Case of arguments copied into %i[0..5]. */ | |
1083 | if (regnum >= SPARC_I0_REGNUM && regnum <= SPARC_I5_REGNUM | |
1084 | && (cache.copied_regs_mask & (1 << (regnum - SPARC_I0_REGNUM))) | |
1085 | && X_SIMM13 (insn) == 68 + (regnum - SPARC_I0_REGNUM) * 4) | |
1086 | { | |
1087 | start_pc += 4; | |
1088 | continue; | |
1089 | } | |
075ccec8 MK |
1090 | } |
1091 | ||
1092 | break; | |
1093 | } | |
1094 | ||
1095 | return start_pc; | |
c906108c SS |
1096 | } |
1097 | ||
386c036b | 1098 | /* Normal frames. */ |
9319a2fe | 1099 | |
386c036b | 1100 | struct sparc_frame_cache * |
236369e7 | 1101 | sparc_frame_cache (struct frame_info *this_frame, void **this_cache) |
9319a2fe | 1102 | { |
386c036b | 1103 | struct sparc_frame_cache *cache; |
9319a2fe | 1104 | |
386c036b MK |
1105 | if (*this_cache) |
1106 | return *this_cache; | |
c906108c | 1107 | |
386c036b MK |
1108 | cache = sparc_alloc_frame_cache (); |
1109 | *this_cache = cache; | |
c906108c | 1110 | |
236369e7 | 1111 | cache->pc = get_frame_func (this_frame); |
386c036b | 1112 | if (cache->pc != 0) |
236369e7 JB |
1113 | sparc_analyze_prologue (get_frame_arch (this_frame), cache->pc, |
1114 | get_frame_pc (this_frame), cache); | |
386c036b MK |
1115 | |
1116 | if (cache->frameless_p) | |
c906108c | 1117 | { |
cbeae229 MK |
1118 | /* This function is frameless, so %fp (%i6) holds the frame |
1119 | pointer for our calling frame. Use %sp (%o6) as this frame's | |
1120 | base address. */ | |
1121 | cache->base = | |
236369e7 | 1122 | get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
cbeae229 MK |
1123 | } |
1124 | else | |
1125 | { | |
1126 | /* For normal frames, %fp (%i6) holds the frame pointer, the | |
1127 | base address for the current stack frame. */ | |
1128 | cache->base = | |
236369e7 | 1129 | get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM); |
c906108c | 1130 | } |
c906108c | 1131 | |
369c397b JB |
1132 | cache->base += cache->frame_offset; |
1133 | ||
5b2d44a0 MK |
1134 | if (cache->base & 1) |
1135 | cache->base += BIAS; | |
1136 | ||
386c036b | 1137 | return cache; |
c906108c | 1138 | } |
c906108c | 1139 | |
aff37fc1 DM |
1140 | static int |
1141 | sparc32_struct_return_from_sym (struct symbol *sym) | |
1142 | { | |
1143 | struct type *type = check_typedef (SYMBOL_TYPE (sym)); | |
1144 | enum type_code code = TYPE_CODE (type); | |
1145 | ||
1146 | if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) | |
1147 | { | |
1148 | type = check_typedef (TYPE_TARGET_TYPE (type)); | |
1149 | if (sparc_structure_or_union_p (type) | |
1150 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
1151 | return 1; | |
1152 | } | |
1153 | ||
1154 | return 0; | |
1155 | } | |
1156 | ||
386c036b | 1157 | struct sparc_frame_cache * |
236369e7 | 1158 | sparc32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 1159 | { |
386c036b MK |
1160 | struct sparc_frame_cache *cache; |
1161 | struct symbol *sym; | |
c906108c | 1162 | |
386c036b MK |
1163 | if (*this_cache) |
1164 | return *this_cache; | |
c906108c | 1165 | |
236369e7 | 1166 | cache = sparc_frame_cache (this_frame, this_cache); |
c906108c | 1167 | |
386c036b MK |
1168 | sym = find_pc_function (cache->pc); |
1169 | if (sym) | |
c906108c | 1170 | { |
aff37fc1 | 1171 | cache->struct_return_p = sparc32_struct_return_from_sym (sym); |
c906108c | 1172 | } |
5465445a JB |
1173 | else |
1174 | { | |
1175 | /* There is no debugging information for this function to | |
1176 | help us determine whether this function returns a struct | |
1177 | or not. So we rely on another heuristic which is to check | |
1178 | the instruction at the return address and see if this is | |
1179 | an "unimp" instruction. If it is, then it is a struct-return | |
1180 | function. */ | |
1181 | CORE_ADDR pc; | |
369c397b JB |
1182 | int regnum = |
1183 | (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; | |
5465445a | 1184 | |
236369e7 | 1185 | pc = get_frame_register_unsigned (this_frame, regnum) + 8; |
5465445a JB |
1186 | if (sparc_is_unimp_insn (pc)) |
1187 | cache->struct_return_p = 1; | |
1188 | } | |
c906108c | 1189 | |
386c036b MK |
1190 | return cache; |
1191 | } | |
1192 | ||
1193 | static void | |
236369e7 | 1194 | sparc32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
386c036b MK |
1195 | struct frame_id *this_id) |
1196 | { | |
1197 | struct sparc_frame_cache *cache = | |
236369e7 | 1198 | sparc32_frame_cache (this_frame, this_cache); |
386c036b MK |
1199 | |
1200 | /* This marks the outermost frame. */ | |
1201 | if (cache->base == 0) | |
1202 | return; | |
1203 | ||
1204 | (*this_id) = frame_id_build (cache->base, cache->pc); | |
1205 | } | |
c906108c | 1206 | |
236369e7 JB |
1207 | static struct value * |
1208 | sparc32_frame_prev_register (struct frame_info *this_frame, | |
1209 | void **this_cache, int regnum) | |
386c036b | 1210 | { |
e17a4113 | 1211 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
386c036b | 1212 | struct sparc_frame_cache *cache = |
236369e7 | 1213 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 1214 | |
386c036b | 1215 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) |
c906108c | 1216 | { |
236369e7 | 1217 | CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; |
386c036b | 1218 | |
236369e7 JB |
1219 | /* If this functions has a Structure, Union or Quad-Precision |
1220 | return value, we have to skip the UNIMP instruction that encodes | |
1221 | the size of the structure. */ | |
1222 | if (cache->struct_return_p) | |
1223 | pc += 4; | |
386c036b | 1224 | |
369c397b JB |
1225 | regnum = |
1226 | (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; | |
236369e7 JB |
1227 | pc += get_frame_register_unsigned (this_frame, regnum) + 8; |
1228 | return frame_unwind_got_constant (this_frame, regnum, pc); | |
c906108c SS |
1229 | } |
1230 | ||
42cdca6c MK |
1231 | /* Handle StackGhost. */ |
1232 | { | |
e17a4113 | 1233 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
42cdca6c MK |
1234 | |
1235 | if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM) | |
1236 | { | |
236369e7 JB |
1237 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
1238 | ULONGEST i7; | |
1239 | ||
1240 | /* Read the value in from memory. */ | |
1241 | i7 = get_frame_memory_unsigned (this_frame, addr, 4); | |
1242 | return frame_unwind_got_constant (this_frame, regnum, i7 ^ wcookie); | |
42cdca6c MK |
1243 | } |
1244 | } | |
1245 | ||
369c397b | 1246 | /* The previous frame's `local' and `in' registers may have been saved |
386c036b | 1247 | in the register save area. */ |
369c397b JB |
1248 | if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM |
1249 | && (cache->saved_regs_mask & (1 << (regnum - SPARC_L0_REGNUM)))) | |
c906108c | 1250 | { |
236369e7 | 1251 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
386c036b | 1252 | |
236369e7 | 1253 | return frame_unwind_got_memory (this_frame, regnum, addr); |
386c036b | 1254 | } |
c906108c | 1255 | |
369c397b JB |
1256 | /* The previous frame's `out' registers may be accessible as the current |
1257 | frame's `in' registers. */ | |
1258 | if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM | |
1259 | && (cache->copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM)))) | |
386c036b | 1260 | regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); |
5af923b0 | 1261 | |
236369e7 | 1262 | return frame_unwind_got_register (this_frame, regnum, regnum); |
386c036b | 1263 | } |
c906108c | 1264 | |
386c036b MK |
1265 | static const struct frame_unwind sparc32_frame_unwind = |
1266 | { | |
1267 | NORMAL_FRAME, | |
8fbca658 | 1268 | default_frame_unwind_stop_reason, |
386c036b | 1269 | sparc32_frame_this_id, |
236369e7 JB |
1270 | sparc32_frame_prev_register, |
1271 | NULL, | |
1272 | default_frame_sniffer | |
386c036b | 1273 | }; |
386c036b | 1274 | \f |
c906108c | 1275 | |
386c036b | 1276 | static CORE_ADDR |
236369e7 | 1277 | sparc32_frame_base_address (struct frame_info *this_frame, void **this_cache) |
386c036b MK |
1278 | { |
1279 | struct sparc_frame_cache *cache = | |
236369e7 | 1280 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 1281 | |
386c036b MK |
1282 | return cache->base; |
1283 | } | |
c906108c | 1284 | |
386c036b MK |
1285 | static const struct frame_base sparc32_frame_base = |
1286 | { | |
1287 | &sparc32_frame_unwind, | |
1288 | sparc32_frame_base_address, | |
1289 | sparc32_frame_base_address, | |
1290 | sparc32_frame_base_address | |
1291 | }; | |
c906108c | 1292 | |
386c036b | 1293 | static struct frame_id |
236369e7 | 1294 | sparc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
386c036b MK |
1295 | { |
1296 | CORE_ADDR sp; | |
5af923b0 | 1297 | |
236369e7 | 1298 | sp = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
5b2d44a0 MK |
1299 | if (sp & 1) |
1300 | sp += BIAS; | |
236369e7 | 1301 | return frame_id_build (sp, get_frame_pc (this_frame)); |
386c036b MK |
1302 | } |
1303 | \f | |
c906108c | 1304 | |
3923a2b2 MK |
1305 | /* Extract a function return value of TYPE from REGCACHE, and copy |
1306 | that into VALBUF. */ | |
5af923b0 | 1307 | |
386c036b MK |
1308 | static void |
1309 | sparc32_extract_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1310 | gdb_byte *valbuf) |
386c036b MK |
1311 | { |
1312 | int len = TYPE_LENGTH (type); | |
fe10a582 | 1313 | gdb_byte buf[32]; |
c906108c | 1314 | |
386c036b MK |
1315 | gdb_assert (!sparc_structure_or_union_p (type)); |
1316 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 1317 | |
fe10a582 | 1318 | if (sparc_floating_p (type) || sparc_complex_floating_p (type)) |
5af923b0 | 1319 | { |
386c036b MK |
1320 | /* Floating return values. */ |
1321 | regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf); | |
1322 | if (len > 4) | |
1323 | regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4); | |
fe10a582 DM |
1324 | if (len > 8) |
1325 | { | |
1326 | regcache_cooked_read (regcache, SPARC_F2_REGNUM, buf + 8); | |
1327 | regcache_cooked_read (regcache, SPARC_F3_REGNUM, buf + 12); | |
1328 | } | |
1329 | if (len > 16) | |
1330 | { | |
1331 | regcache_cooked_read (regcache, SPARC_F4_REGNUM, buf + 16); | |
1332 | regcache_cooked_read (regcache, SPARC_F5_REGNUM, buf + 20); | |
1333 | regcache_cooked_read (regcache, SPARC_F6_REGNUM, buf + 24); | |
1334 | regcache_cooked_read (regcache, SPARC_F7_REGNUM, buf + 28); | |
1335 | } | |
386c036b | 1336 | memcpy (valbuf, buf, len); |
5af923b0 MS |
1337 | } |
1338 | else | |
1339 | { | |
386c036b MK |
1340 | /* Integral and pointer return values. */ |
1341 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
c906108c | 1342 | |
386c036b MK |
1343 | regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); |
1344 | if (len > 4) | |
1345 | { | |
1346 | regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4); | |
1347 | gdb_assert (len == 8); | |
1348 | memcpy (valbuf, buf, 8); | |
1349 | } | |
1350 | else | |
1351 | { | |
1352 | /* Just stripping off any unused bytes should preserve the | |
1353 | signed-ness just fine. */ | |
1354 | memcpy (valbuf, buf + 4 - len, len); | |
1355 | } | |
1356 | } | |
1357 | } | |
c906108c | 1358 | |
3923a2b2 MK |
1359 | /* Store the function return value of type TYPE from VALBUF into |
1360 | REGCACHE. */ | |
c906108c | 1361 | |
386c036b MK |
1362 | static void |
1363 | sparc32_store_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1364 | const gdb_byte *valbuf) |
386c036b MK |
1365 | { |
1366 | int len = TYPE_LENGTH (type); | |
e1613aba | 1367 | gdb_byte buf[8]; |
c906108c | 1368 | |
386c036b MK |
1369 | gdb_assert (!sparc_structure_or_union_p (type)); |
1370 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
a9789a6b | 1371 | gdb_assert (len <= 8); |
c906108c | 1372 | |
fe10a582 | 1373 | if (sparc_floating_p (type) || sparc_complex_floating_p (type)) |
386c036b MK |
1374 | { |
1375 | /* Floating return values. */ | |
1376 | memcpy (buf, valbuf, len); | |
1377 | regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf); | |
1378 | if (len > 4) | |
1379 | regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4); | |
fe10a582 DM |
1380 | if (len > 8) |
1381 | { | |
1382 | regcache_cooked_write (regcache, SPARC_F2_REGNUM, buf + 8); | |
1383 | regcache_cooked_write (regcache, SPARC_F3_REGNUM, buf + 12); | |
1384 | } | |
1385 | if (len > 16) | |
1386 | { | |
1387 | regcache_cooked_write (regcache, SPARC_F4_REGNUM, buf + 16); | |
1388 | regcache_cooked_write (regcache, SPARC_F5_REGNUM, buf + 20); | |
1389 | regcache_cooked_write (regcache, SPARC_F6_REGNUM, buf + 24); | |
1390 | regcache_cooked_write (regcache, SPARC_F7_REGNUM, buf + 28); | |
1391 | } | |
386c036b MK |
1392 | } |
1393 | else | |
c906108c | 1394 | { |
386c036b MK |
1395 | /* Integral and pointer return values. */ |
1396 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
1397 | ||
1398 | if (len > 4) | |
2757dd86 | 1399 | { |
386c036b MK |
1400 | gdb_assert (len == 8); |
1401 | memcpy (buf, valbuf, 8); | |
1402 | regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4); | |
2757dd86 AC |
1403 | } |
1404 | else | |
1405 | { | |
386c036b MK |
1406 | /* ??? Do we need to do any sign-extension here? */ |
1407 | memcpy (buf + 4 - len, valbuf, len); | |
2757dd86 | 1408 | } |
386c036b | 1409 | regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); |
c906108c SS |
1410 | } |
1411 | } | |
1412 | ||
b9d4c5ed | 1413 | static enum return_value_convention |
6a3a010b | 1414 | sparc32_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
1415 | struct type *type, struct regcache *regcache, |
1416 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
b9d4c5ed | 1417 | { |
e17a4113 UW |
1418 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1419 | ||
0a8f48b9 MK |
1420 | /* The psABI says that "...every stack frame reserves the word at |
1421 | %fp+64. If a function returns a structure, union, or | |
1422 | quad-precision value, this word should hold the address of the | |
1423 | object into which the return value should be copied." This | |
1424 | guarantees that we can always find the return value, not just | |
1425 | before the function returns. */ | |
1426 | ||
b9d4c5ed MK |
1427 | if (sparc_structure_or_union_p (type) |
1428 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
0a8f48b9 | 1429 | { |
bbfdfe1c DM |
1430 | ULONGEST sp; |
1431 | CORE_ADDR addr; | |
1432 | ||
0a8f48b9 MK |
1433 | if (readbuf) |
1434 | { | |
0a8f48b9 | 1435 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); |
e17a4113 | 1436 | addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); |
0a8f48b9 MK |
1437 | read_memory (addr, readbuf, TYPE_LENGTH (type)); |
1438 | } | |
bbfdfe1c DM |
1439 | if (writebuf) |
1440 | { | |
1441 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1442 | addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); | |
1443 | write_memory (addr, writebuf, TYPE_LENGTH (type)); | |
1444 | } | |
0a8f48b9 MK |
1445 | |
1446 | return RETURN_VALUE_ABI_PRESERVES_ADDRESS; | |
1447 | } | |
b9d4c5ed MK |
1448 | |
1449 | if (readbuf) | |
1450 | sparc32_extract_return_value (type, regcache, readbuf); | |
1451 | if (writebuf) | |
1452 | sparc32_store_return_value (type, regcache, writebuf); | |
1453 | ||
1454 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1455 | } | |
1456 | ||
386c036b MK |
1457 | static int |
1458 | sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) | |
c906108c | 1459 | { |
386c036b | 1460 | return (sparc_structure_or_union_p (type) |
fe10a582 DM |
1461 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16) |
1462 | || sparc_complex_floating_p (type)); | |
386c036b | 1463 | } |
c906108c | 1464 | |
aff37fc1 | 1465 | static int |
4a4e5149 | 1466 | sparc32_dwarf2_struct_return_p (struct frame_info *this_frame) |
aff37fc1 | 1467 | { |
236369e7 | 1468 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
aff37fc1 DM |
1469 | struct symbol *sym = find_pc_function (pc); |
1470 | ||
1471 | if (sym) | |
1472 | return sparc32_struct_return_from_sym (sym); | |
1473 | return 0; | |
1474 | } | |
1475 | ||
f5a9b87d DM |
1476 | static void |
1477 | sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 | 1478 | struct dwarf2_frame_state_reg *reg, |
4a4e5149 | 1479 | struct frame_info *this_frame) |
f5a9b87d | 1480 | { |
aff37fc1 DM |
1481 | int off; |
1482 | ||
f5a9b87d DM |
1483 | switch (regnum) |
1484 | { | |
1485 | case SPARC_G0_REGNUM: | |
1486 | /* Since %g0 is always zero, there is no point in saving it, and | |
1487 | people will be inclined omit it from the CFI. Make sure we | |
1488 | don't warn about that. */ | |
1489 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
1490 | break; | |
1491 | case SPARC_SP_REGNUM: | |
1492 | reg->how = DWARF2_FRAME_REG_CFA; | |
1493 | break; | |
1494 | case SPARC32_PC_REGNUM: | |
f5a9b87d DM |
1495 | case SPARC32_NPC_REGNUM: |
1496 | reg->how = DWARF2_FRAME_REG_RA_OFFSET; | |
aff37fc1 | 1497 | off = 8; |
4a4e5149 | 1498 | if (sparc32_dwarf2_struct_return_p (this_frame)) |
aff37fc1 DM |
1499 | off += 4; |
1500 | if (regnum == SPARC32_NPC_REGNUM) | |
1501 | off += 4; | |
1502 | reg->loc.offset = off; | |
f5a9b87d DM |
1503 | break; |
1504 | } | |
1505 | } | |
1506 | ||
386c036b MK |
1507 | \f |
1508 | /* The SPARC Architecture doesn't have hardware single-step support, | |
1509 | and most operating systems don't implement it either, so we provide | |
1510 | software single-step mechanism. */ | |
c906108c | 1511 | |
386c036b | 1512 | static CORE_ADDR |
0b1b3e42 | 1513 | sparc_analyze_control_transfer (struct frame_info *frame, |
c893be75 | 1514 | CORE_ADDR pc, CORE_ADDR *npc) |
386c036b MK |
1515 | { |
1516 | unsigned long insn = sparc_fetch_instruction (pc); | |
1517 | int conditional_p = X_COND (insn) & 0x7; | |
8d1b3521 | 1518 | int branch_p = 0, fused_p = 0; |
386c036b | 1519 | long offset = 0; /* Must be signed for sign-extend. */ |
c906108c | 1520 | |
8d1b3521 | 1521 | if (X_OP (insn) == 0 && X_OP2 (insn) == 3) |
c906108c | 1522 | { |
8d1b3521 DM |
1523 | if ((insn & 0x10000000) == 0) |
1524 | { | |
1525 | /* Branch on Integer Register with Prediction (BPr). */ | |
1526 | branch_p = 1; | |
1527 | conditional_p = 1; | |
1528 | } | |
1529 | else | |
1530 | { | |
1531 | /* Compare and Branch */ | |
1532 | branch_p = 1; | |
1533 | fused_p = 1; | |
1534 | offset = 4 * X_DISP10 (insn); | |
1535 | } | |
c906108c | 1536 | } |
386c036b | 1537 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) |
c906108c | 1538 | { |
386c036b MK |
1539 | /* Branch on Floating-Point Condition Codes (FBfcc). */ |
1540 | branch_p = 1; | |
1541 | offset = 4 * X_DISP22 (insn); | |
c906108c | 1542 | } |
386c036b MK |
1543 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) |
1544 | { | |
1545 | /* Branch on Floating-Point Condition Codes with Prediction | |
1546 | (FBPfcc). */ | |
1547 | branch_p = 1; | |
1548 | offset = 4 * X_DISP19 (insn); | |
1549 | } | |
1550 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) | |
1551 | { | |
1552 | /* Branch on Integer Condition Codes (Bicc). */ | |
1553 | branch_p = 1; | |
1554 | offset = 4 * X_DISP22 (insn); | |
1555 | } | |
1556 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) | |
c906108c | 1557 | { |
386c036b MK |
1558 | /* Branch on Integer Condition Codes with Prediction (BPcc). */ |
1559 | branch_p = 1; | |
1560 | offset = 4 * X_DISP19 (insn); | |
c906108c | 1561 | } |
c893be75 MK |
1562 | else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a) |
1563 | { | |
1564 | /* Trap instruction (TRAP). */ | |
0b1b3e42 | 1565 | return gdbarch_tdep (get_frame_arch (frame))->step_trap (frame, insn); |
c893be75 | 1566 | } |
386c036b MK |
1567 | |
1568 | /* FIXME: Handle DONE and RETRY instructions. */ | |
1569 | ||
386c036b | 1570 | if (branch_p) |
c906108c | 1571 | { |
8d1b3521 DM |
1572 | if (fused_p) |
1573 | { | |
1574 | /* Fused compare-and-branch instructions are non-delayed, | |
1575 | and do not have an annuling capability. So we need to | |
1576 | always set a breakpoint on both the NPC and the branch | |
1577 | target address. */ | |
1578 | gdb_assert (offset != 0); | |
1579 | return pc + offset; | |
1580 | } | |
1581 | else if (conditional_p) | |
c906108c | 1582 | { |
386c036b MK |
1583 | /* For conditional branches, return nPC + 4 iff the annul |
1584 | bit is 1. */ | |
1585 | return (X_A (insn) ? *npc + 4 : 0); | |
c906108c SS |
1586 | } |
1587 | else | |
1588 | { | |
386c036b MK |
1589 | /* For unconditional branches, return the target if its |
1590 | specified condition is "always" and return nPC + 4 if the | |
1591 | condition is "never". If the annul bit is 1, set *NPC to | |
1592 | zero. */ | |
1593 | if (X_COND (insn) == 0x0) | |
1594 | pc = *npc, offset = 4; | |
1595 | if (X_A (insn)) | |
1596 | *npc = 0; | |
1597 | ||
386c036b | 1598 | return pc + offset; |
c906108c SS |
1599 | } |
1600 | } | |
386c036b MK |
1601 | |
1602 | return 0; | |
c906108c SS |
1603 | } |
1604 | ||
c893be75 | 1605 | static CORE_ADDR |
0b1b3e42 | 1606 | sparc_step_trap (struct frame_info *frame, unsigned long insn) |
c893be75 MK |
1607 | { |
1608 | return 0; | |
1609 | } | |
1610 | ||
e6590a1b | 1611 | int |
0b1b3e42 | 1612 | sparc_software_single_step (struct frame_info *frame) |
386c036b | 1613 | { |
0b1b3e42 | 1614 | struct gdbarch *arch = get_frame_arch (frame); |
c893be75 | 1615 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
6c95b8df | 1616 | struct address_space *aspace = get_frame_address_space (frame); |
8181d85f | 1617 | CORE_ADDR npc, nnpc; |
c906108c | 1618 | |
e0cd558a | 1619 | CORE_ADDR pc, orig_npc; |
c906108c | 1620 | |
0b1b3e42 UW |
1621 | pc = get_frame_register_unsigned (frame, tdep->pc_regnum); |
1622 | orig_npc = npc = get_frame_register_unsigned (frame, tdep->npc_regnum); | |
c906108c | 1623 | |
e0cd558a | 1624 | /* Analyze the instruction at PC. */ |
0b1b3e42 | 1625 | nnpc = sparc_analyze_control_transfer (frame, pc, &npc); |
e0cd558a | 1626 | if (npc != 0) |
6c95b8df | 1627 | insert_single_step_breakpoint (arch, aspace, npc); |
8181d85f | 1628 | |
e0cd558a | 1629 | if (nnpc != 0) |
6c95b8df | 1630 | insert_single_step_breakpoint (arch, aspace, nnpc); |
c906108c | 1631 | |
e0cd558a UW |
1632 | /* Assert that we have set at least one breakpoint, and that |
1633 | they're not set at the same spot - unless we're going | |
1634 | from here straight to NULL, i.e. a call or jump to 0. */ | |
1635 | gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0); | |
1636 | gdb_assert (nnpc != npc || orig_npc == 0); | |
e6590a1b UW |
1637 | |
1638 | return 1; | |
386c036b MK |
1639 | } |
1640 | ||
1641 | static void | |
61a1198a | 1642 | sparc_write_pc (struct regcache *regcache, CORE_ADDR pc) |
386c036b | 1643 | { |
61a1198a | 1644 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
386c036b | 1645 | |
61a1198a UW |
1646 | regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc); |
1647 | regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4); | |
386c036b MK |
1648 | } |
1649 | \f | |
5af923b0 | 1650 | |
a54124c5 MK |
1651 | /* Return the appropriate register set for the core section identified |
1652 | by SECT_NAME and SECT_SIZE. */ | |
1653 | ||
63807e1d | 1654 | static const struct regset * |
a54124c5 MK |
1655 | sparc_regset_from_core_section (struct gdbarch *gdbarch, |
1656 | const char *sect_name, size_t sect_size) | |
1657 | { | |
1658 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1659 | ||
c558d81a | 1660 | if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset) |
a54124c5 MK |
1661 | return tdep->gregset; |
1662 | ||
c558d81a | 1663 | if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset) |
a54124c5 MK |
1664 | return tdep->fpregset; |
1665 | ||
1666 | return NULL; | |
1667 | } | |
1668 | \f | |
1669 | ||
386c036b MK |
1670 | static struct gdbarch * |
1671 | sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1672 | { | |
1673 | struct gdbarch_tdep *tdep; | |
1674 | struct gdbarch *gdbarch; | |
c906108c | 1675 | |
386c036b MK |
1676 | /* If there is already a candidate, use it. */ |
1677 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1678 | if (arches != NULL) | |
1679 | return arches->gdbarch; | |
c906108c | 1680 | |
386c036b | 1681 | /* Allocate space for the new architecture. */ |
41bf6aca | 1682 | tdep = XCNEW (struct gdbarch_tdep); |
386c036b | 1683 | gdbarch = gdbarch_alloc (&info, tdep); |
5af923b0 | 1684 | |
386c036b MK |
1685 | tdep->pc_regnum = SPARC32_PC_REGNUM; |
1686 | tdep->npc_regnum = SPARC32_NPC_REGNUM; | |
c893be75 | 1687 | tdep->step_trap = sparc_step_trap; |
386c036b MK |
1688 | |
1689 | set_gdbarch_long_double_bit (gdbarch, 128); | |
8da61cc4 | 1690 | set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad); |
386c036b MK |
1691 | |
1692 | set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); | |
1693 | set_gdbarch_register_name (gdbarch, sparc32_register_name); | |
1694 | set_gdbarch_register_type (gdbarch, sparc32_register_type); | |
1695 | set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); | |
1696 | set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); | |
1697 | set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); | |
1698 | ||
1699 | /* Register numbers of various important registers. */ | |
1700 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ | |
1701 | set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ | |
1702 | set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ | |
1703 | ||
1704 | /* Call dummy code. */ | |
49a45ecf | 1705 | set_gdbarch_frame_align (gdbarch, sparc32_frame_align); |
386c036b MK |
1706 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
1707 | set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); | |
1708 | set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); | |
1709 | ||
b9d4c5ed | 1710 | set_gdbarch_return_value (gdbarch, sparc32_return_value); |
386c036b MK |
1711 | set_gdbarch_stabs_argument_has_addr |
1712 | (gdbarch, sparc32_stabs_argument_has_addr); | |
1713 | ||
1714 | set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); | |
1715 | ||
1716 | /* Stack grows downward. */ | |
1717 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
c906108c | 1718 | |
386c036b | 1719 | set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc); |
c906108c | 1720 | |
386c036b | 1721 | set_gdbarch_frame_args_skip (gdbarch, 8); |
5af923b0 | 1722 | |
386c036b | 1723 | set_gdbarch_print_insn (gdbarch, print_insn_sparc); |
c906108c | 1724 | |
386c036b MK |
1725 | set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); |
1726 | set_gdbarch_write_pc (gdbarch, sparc_write_pc); | |
c906108c | 1727 | |
236369e7 | 1728 | set_gdbarch_dummy_id (gdbarch, sparc_dummy_id); |
c906108c | 1729 | |
386c036b | 1730 | set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc); |
c906108c | 1731 | |
386c036b MK |
1732 | frame_base_set_default (gdbarch, &sparc32_frame_base); |
1733 | ||
f5a9b87d DM |
1734 | /* Hook in the DWARF CFI frame unwinder. */ |
1735 | dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg); | |
1736 | /* FIXME: kettenis/20050423: Don't enable the unwinder until the | |
1737 | StackGhost issues have been resolved. */ | |
1738 | ||
b2a0b9b2 DM |
1739 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1740 | gdbarch_init_osabi (info, gdbarch); | |
1741 | ||
236369e7 | 1742 | frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind); |
c906108c | 1743 | |
a54124c5 | 1744 | /* If we have register sets, enable the generic core file support. */ |
4c72d57a | 1745 | if (tdep->gregset) |
a54124c5 MK |
1746 | set_gdbarch_regset_from_core_section (gdbarch, |
1747 | sparc_regset_from_core_section); | |
1748 | ||
7e35103a JB |
1749 | register_sparc_ravenscar_ops (gdbarch); |
1750 | ||
386c036b MK |
1751 | return gdbarch; |
1752 | } | |
1753 | \f | |
1754 | /* Helper functions for dealing with register windows. */ | |
1755 | ||
1756 | void | |
1757 | sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) | |
c906108c | 1758 | { |
e17a4113 UW |
1759 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1760 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
386c036b | 1761 | int offset = 0; |
e1613aba | 1762 | gdb_byte buf[8]; |
386c036b MK |
1763 | int i; |
1764 | ||
1765 | if (sp & 1) | |
1766 | { | |
1767 | /* Registers are 64-bit. */ | |
1768 | sp += BIAS; | |
c906108c | 1769 | |
386c036b MK |
1770 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1771 | { | |
1772 | if (regnum == i || regnum == -1) | |
1773 | { | |
1774 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); | |
f700a364 MK |
1775 | |
1776 | /* Handle StackGhost. */ | |
1777 | if (i == SPARC_I7_REGNUM) | |
1778 | { | |
e17a4113 UW |
1779 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1780 | ULONGEST i7; | |
f700a364 | 1781 | |
e17a4113 UW |
1782 | i7 = extract_unsigned_integer (buf + offset, 8, byte_order); |
1783 | store_unsigned_integer (buf + offset, 8, byte_order, | |
1784 | i7 ^ wcookie); | |
f700a364 MK |
1785 | } |
1786 | ||
386c036b MK |
1787 | regcache_raw_supply (regcache, i, buf); |
1788 | } | |
1789 | } | |
1790 | } | |
1791 | else | |
c906108c | 1792 | { |
386c036b MK |
1793 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1794 | pointer. */ | |
1795 | sp &= 0xffffffffUL; | |
c906108c | 1796 | |
386c036b MK |
1797 | /* Clear out the top half of the temporary buffer, and put the |
1798 | register value in the bottom half if we're in 64-bit mode. */ | |
e6d4f032 | 1799 | if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) |
c906108c | 1800 | { |
386c036b MK |
1801 | memset (buf, 0, 4); |
1802 | offset = 4; | |
1803 | } | |
c906108c | 1804 | |
386c036b MK |
1805 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1806 | { | |
1807 | if (regnum == i || regnum == -1) | |
1808 | { | |
1809 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), | |
1810 | buf + offset, 4); | |
42cdca6c MK |
1811 | |
1812 | /* Handle StackGhost. */ | |
1813 | if (i == SPARC_I7_REGNUM) | |
1814 | { | |
e17a4113 UW |
1815 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1816 | ULONGEST i7; | |
42cdca6c | 1817 | |
e17a4113 UW |
1818 | i7 = extract_unsigned_integer (buf + offset, 4, byte_order); |
1819 | store_unsigned_integer (buf + offset, 4, byte_order, | |
1820 | i7 ^ wcookie); | |
42cdca6c MK |
1821 | } |
1822 | ||
386c036b MK |
1823 | regcache_raw_supply (regcache, i, buf); |
1824 | } | |
c906108c SS |
1825 | } |
1826 | } | |
c906108c | 1827 | } |
c906108c SS |
1828 | |
1829 | void | |
386c036b MK |
1830 | sparc_collect_rwindow (const struct regcache *regcache, |
1831 | CORE_ADDR sp, int regnum) | |
c906108c | 1832 | { |
e17a4113 UW |
1833 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1834 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
386c036b | 1835 | int offset = 0; |
e1613aba | 1836 | gdb_byte buf[8]; |
386c036b | 1837 | int i; |
5af923b0 | 1838 | |
386c036b | 1839 | if (sp & 1) |
5af923b0 | 1840 | { |
386c036b MK |
1841 | /* Registers are 64-bit. */ |
1842 | sp += BIAS; | |
c906108c | 1843 | |
386c036b MK |
1844 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1845 | { | |
1846 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1847 | { | |
1848 | regcache_raw_collect (regcache, i, buf); | |
f700a364 MK |
1849 | |
1850 | /* Handle StackGhost. */ | |
1851 | if (i == SPARC_I7_REGNUM) | |
1852 | { | |
e17a4113 UW |
1853 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1854 | ULONGEST i7; | |
f700a364 | 1855 | |
e17a4113 UW |
1856 | i7 = extract_unsigned_integer (buf + offset, 8, byte_order); |
1857 | store_unsigned_integer (buf, 8, byte_order, i7 ^ wcookie); | |
f700a364 MK |
1858 | } |
1859 | ||
386c036b MK |
1860 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); |
1861 | } | |
1862 | } | |
5af923b0 MS |
1863 | } |
1864 | else | |
1865 | { | |
386c036b MK |
1866 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1867 | pointer. */ | |
1868 | sp &= 0xffffffffUL; | |
1869 | ||
1870 | /* Only use the bottom half if we're in 64-bit mode. */ | |
e6d4f032 | 1871 | if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) |
386c036b MK |
1872 | offset = 4; |
1873 | ||
1874 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1875 | { | |
1876 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1877 | { | |
1878 | regcache_raw_collect (regcache, i, buf); | |
42cdca6c MK |
1879 | |
1880 | /* Handle StackGhost. */ | |
1881 | if (i == SPARC_I7_REGNUM) | |
1882 | { | |
e17a4113 UW |
1883 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1884 | ULONGEST i7; | |
42cdca6c | 1885 | |
e17a4113 UW |
1886 | i7 = extract_unsigned_integer (buf + offset, 4, byte_order); |
1887 | store_unsigned_integer (buf + offset, 4, byte_order, | |
1888 | i7 ^ wcookie); | |
42cdca6c MK |
1889 | } |
1890 | ||
386c036b MK |
1891 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), |
1892 | buf + offset, 4); | |
1893 | } | |
1894 | } | |
5af923b0 | 1895 | } |
c906108c SS |
1896 | } |
1897 | ||
386c036b MK |
1898 | /* Helper functions for dealing with register sets. */ |
1899 | ||
c906108c | 1900 | void |
386c036b MK |
1901 | sparc32_supply_gregset (const struct sparc_gregset *gregset, |
1902 | struct regcache *regcache, | |
1903 | int regnum, const void *gregs) | |
c906108c | 1904 | { |
e1613aba | 1905 | const gdb_byte *regs = gregs; |
22e74ef9 | 1906 | gdb_byte zero[4] = { 0 }; |
386c036b | 1907 | int i; |
5af923b0 | 1908 | |
386c036b MK |
1909 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1910 | regcache_raw_supply (regcache, SPARC32_PSR_REGNUM, | |
1911 | regs + gregset->r_psr_offset); | |
c906108c | 1912 | |
386c036b MK |
1913 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1914 | regcache_raw_supply (regcache, SPARC32_PC_REGNUM, | |
1915 | regs + gregset->r_pc_offset); | |
5af923b0 | 1916 | |
386c036b MK |
1917 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) |
1918 | regcache_raw_supply (regcache, SPARC32_NPC_REGNUM, | |
1919 | regs + gregset->r_npc_offset); | |
5af923b0 | 1920 | |
386c036b MK |
1921 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1922 | regcache_raw_supply (regcache, SPARC32_Y_REGNUM, | |
1923 | regs + gregset->r_y_offset); | |
5af923b0 | 1924 | |
386c036b | 1925 | if (regnum == SPARC_G0_REGNUM || regnum == -1) |
22e74ef9 | 1926 | regcache_raw_supply (regcache, SPARC_G0_REGNUM, &zero); |
5af923b0 | 1927 | |
386c036b | 1928 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) |
c906108c | 1929 | { |
386c036b MK |
1930 | int offset = gregset->r_g1_offset; |
1931 | ||
1932 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1933 | { | |
1934 | if (regnum == i || regnum == -1) | |
1935 | regcache_raw_supply (regcache, i, regs + offset); | |
1936 | offset += 4; | |
1937 | } | |
c906108c | 1938 | } |
386c036b MK |
1939 | |
1940 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
c906108c | 1941 | { |
386c036b MK |
1942 | /* Not all of the register set variants include Locals and |
1943 | Inputs. For those that don't, we read them off the stack. */ | |
1944 | if (gregset->r_l0_offset == -1) | |
1945 | { | |
1946 | ULONGEST sp; | |
1947 | ||
1948 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1949 | sparc_supply_rwindow (regcache, sp, regnum); | |
1950 | } | |
1951 | else | |
1952 | { | |
1953 | int offset = gregset->r_l0_offset; | |
1954 | ||
1955 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1956 | { | |
1957 | if (regnum == i || regnum == -1) | |
1958 | regcache_raw_supply (regcache, i, regs + offset); | |
1959 | offset += 4; | |
1960 | } | |
1961 | } | |
c906108c SS |
1962 | } |
1963 | } | |
1964 | ||
c5aa993b | 1965 | void |
386c036b MK |
1966 | sparc32_collect_gregset (const struct sparc_gregset *gregset, |
1967 | const struct regcache *regcache, | |
1968 | int regnum, void *gregs) | |
c906108c | 1969 | { |
e1613aba | 1970 | gdb_byte *regs = gregs; |
386c036b | 1971 | int i; |
c5aa993b | 1972 | |
386c036b MK |
1973 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1974 | regcache_raw_collect (regcache, SPARC32_PSR_REGNUM, | |
1975 | regs + gregset->r_psr_offset); | |
60054393 | 1976 | |
386c036b MK |
1977 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1978 | regcache_raw_collect (regcache, SPARC32_PC_REGNUM, | |
1979 | regs + gregset->r_pc_offset); | |
1980 | ||
1981 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) | |
1982 | regcache_raw_collect (regcache, SPARC32_NPC_REGNUM, | |
1983 | regs + gregset->r_npc_offset); | |
5af923b0 | 1984 | |
386c036b MK |
1985 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1986 | regcache_raw_collect (regcache, SPARC32_Y_REGNUM, | |
1987 | regs + gregset->r_y_offset); | |
1988 | ||
1989 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) | |
5af923b0 | 1990 | { |
386c036b MK |
1991 | int offset = gregset->r_g1_offset; |
1992 | ||
1993 | /* %g0 is always zero. */ | |
1994 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1995 | { | |
1996 | if (regnum == i || regnum == -1) | |
1997 | regcache_raw_collect (regcache, i, regs + offset); | |
1998 | offset += 4; | |
1999 | } | |
5af923b0 | 2000 | } |
386c036b MK |
2001 | |
2002 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
5af923b0 | 2003 | { |
386c036b MK |
2004 | /* Not all of the register set variants include Locals and |
2005 | Inputs. For those that don't, we read them off the stack. */ | |
2006 | if (gregset->r_l0_offset != -1) | |
2007 | { | |
2008 | int offset = gregset->r_l0_offset; | |
2009 | ||
2010 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
2011 | { | |
2012 | if (regnum == i || regnum == -1) | |
2013 | regcache_raw_collect (regcache, i, regs + offset); | |
2014 | offset += 4; | |
2015 | } | |
2016 | } | |
5af923b0 | 2017 | } |
c906108c SS |
2018 | } |
2019 | ||
c906108c | 2020 | void |
db75c717 DM |
2021 | sparc32_supply_fpregset (const struct sparc_fpregset *fpregset, |
2022 | struct regcache *regcache, | |
386c036b | 2023 | int regnum, const void *fpregs) |
c906108c | 2024 | { |
e1613aba | 2025 | const gdb_byte *regs = fpregs; |
386c036b | 2026 | int i; |
60054393 | 2027 | |
386c036b | 2028 | for (i = 0; i < 32; i++) |
c906108c | 2029 | { |
386c036b | 2030 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) |
db75c717 DM |
2031 | regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, |
2032 | regs + fpregset->r_f0_offset + (i * 4)); | |
c906108c | 2033 | } |
5af923b0 | 2034 | |
386c036b | 2035 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
db75c717 DM |
2036 | regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, |
2037 | regs + fpregset->r_fsr_offset); | |
c906108c SS |
2038 | } |
2039 | ||
386c036b | 2040 | void |
db75c717 DM |
2041 | sparc32_collect_fpregset (const struct sparc_fpregset *fpregset, |
2042 | const struct regcache *regcache, | |
386c036b | 2043 | int regnum, void *fpregs) |
c906108c | 2044 | { |
e1613aba | 2045 | gdb_byte *regs = fpregs; |
386c036b | 2046 | int i; |
c906108c | 2047 | |
386c036b MK |
2048 | for (i = 0; i < 32; i++) |
2049 | { | |
2050 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) | |
db75c717 DM |
2051 | regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, |
2052 | regs + fpregset->r_f0_offset + (i * 4)); | |
386c036b | 2053 | } |
c906108c | 2054 | |
386c036b | 2055 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
db75c717 DM |
2056 | regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, |
2057 | regs + fpregset->r_fsr_offset); | |
c906108c | 2058 | } |
c906108c | 2059 | \f |
c906108c | 2060 | |
386c036b | 2061 | /* SunOS 4. */ |
c906108c | 2062 | |
386c036b MK |
2063 | /* From <machine/reg.h>. */ |
2064 | const struct sparc_gregset sparc32_sunos4_gregset = | |
c906108c | 2065 | { |
386c036b MK |
2066 | 0 * 4, /* %psr */ |
2067 | 1 * 4, /* %pc */ | |
2068 | 2 * 4, /* %npc */ | |
2069 | 3 * 4, /* %y */ | |
2070 | -1, /* %wim */ | |
2071 | -1, /* %tbr */ | |
2072 | 4 * 4, /* %g1 */ | |
2073 | -1 /* %l0 */ | |
2074 | }; | |
db75c717 DM |
2075 | |
2076 | const struct sparc_fpregset sparc32_sunos4_fpregset = | |
2077 | { | |
2078 | 0 * 4, /* %f0 */ | |
2079 | 33 * 4, /* %fsr */ | |
2080 | }; | |
2081 | ||
2082 | const struct sparc_fpregset sparc32_bsd_fpregset = | |
2083 | { | |
2084 | 0 * 4, /* %f0 */ | |
2085 | 32 * 4, /* %fsr */ | |
2086 | }; | |
386c036b | 2087 | \f |
c906108c | 2088 | |
386c036b MK |
2089 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
2090 | void _initialize_sparc_tdep (void); | |
c906108c SS |
2091 | |
2092 | void | |
386c036b | 2093 | _initialize_sparc_tdep (void) |
c906108c | 2094 | { |
386c036b | 2095 | register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init); |
ef3cf062 | 2096 | } |