Commit | Line | Data |
---|---|---|
386c036b | 1 | /* Target-dependent code for SPARC. |
cda5a58a | 2 | |
28e7fd62 | 3 | Copyright (C) 2003-2013 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 19 | |
c906108c | 20 | #include "defs.h" |
5af923b0 | 21 | #include "arch-utils.h" |
386c036b | 22 | #include "dis-asm.h" |
f5a9b87d | 23 | #include "dwarf2-frame.h" |
386c036b | 24 | #include "floatformat.h" |
c906108c | 25 | #include "frame.h" |
386c036b MK |
26 | #include "frame-base.h" |
27 | #include "frame-unwind.h" | |
28 | #include "gdbcore.h" | |
29 | #include "gdbtypes.h" | |
c906108c | 30 | #include "inferior.h" |
386c036b MK |
31 | #include "symtab.h" |
32 | #include "objfiles.h" | |
33 | #include "osabi.h" | |
34 | #include "regcache.h" | |
c906108c SS |
35 | #include "target.h" |
36 | #include "value.h" | |
c906108c | 37 | |
43bd9a9e | 38 | #include "gdb_assert.h" |
386c036b | 39 | #include "gdb_string.h" |
c906108c | 40 | |
386c036b | 41 | #include "sparc-tdep.h" |
e6f9c00b | 42 | #include "sparc-ravenscar-thread.h" |
c906108c | 43 | |
a54124c5 MK |
44 | struct regset; |
45 | ||
9eb42ed1 MK |
46 | /* This file implements the SPARC 32-bit ABI as defined by the section |
47 | "Low-Level System Information" of the SPARC Compliance Definition | |
48 | (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD | |
f2e7c15d | 49 | lists changes with respect to the original 32-bit psABI as defined |
9eb42ed1 | 50 | in the "System V ABI, SPARC Processor Supplement". |
386c036b MK |
51 | |
52 | Note that if we talk about SunOS, we mean SunOS 4.x, which was | |
53 | BSD-based, which is sometimes (retroactively?) referred to as | |
54 | Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and | |
55 | above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 | |
56 | suffering from severe version number inflation). Solaris 2.x is | |
57 | also known as SunOS 5.x, since that's what uname(1) says. Solaris | |
58 | 2.x is SVR4-based. */ | |
59 | ||
60 | /* Please use the sparc32_-prefix for 32-bit specific code, the | |
61 | sparc64_-prefix for 64-bit specific code and the sparc_-prefix for | |
62 | code that can handle both. The 64-bit specific code lives in | |
63 | sparc64-tdep.c; don't add any here. */ | |
64 | ||
65 | /* The SPARC Floating-Point Quad-Precision format is similar to | |
7a58cce8 | 66 | big-endian IA-64 Quad-Precision format. */ |
8da61cc4 | 67 | #define floatformats_sparc_quad floatformats_ia64_quad |
386c036b MK |
68 | |
69 | /* The stack pointer is offset from the stack frame by a BIAS of 2047 | |
70 | (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC | |
71 | hosts, so undefine it first. */ | |
72 | #undef BIAS | |
73 | #define BIAS 2047 | |
74 | ||
75 | /* Macros to extract fields from SPARC instructions. */ | |
c906108c SS |
76 | #define X_OP(i) (((i) >> 30) & 0x3) |
77 | #define X_RD(i) (((i) >> 25) & 0x1f) | |
78 | #define X_A(i) (((i) >> 29) & 1) | |
79 | #define X_COND(i) (((i) >> 25) & 0xf) | |
80 | #define X_OP2(i) (((i) >> 22) & 0x7) | |
81 | #define X_IMM22(i) ((i) & 0x3fffff) | |
82 | #define X_OP3(i) (((i) >> 19) & 0x3f) | |
075ccec8 | 83 | #define X_RS1(i) (((i) >> 14) & 0x1f) |
b0b92586 | 84 | #define X_RS2(i) ((i) & 0x1f) |
c906108c | 85 | #define X_I(i) (((i) >> 13) & 1) |
c906108c | 86 | /* Sign extension macros. */ |
c906108c | 87 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) |
c906108c | 88 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) |
8d1b3521 | 89 | #define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200) |
075ccec8 | 90 | #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000) |
c906108c | 91 | |
386c036b MK |
92 | /* Fetch the instruction at PC. Instructions are always big-endian |
93 | even if the processor operates in little-endian mode. */ | |
94 | ||
95 | unsigned long | |
96 | sparc_fetch_instruction (CORE_ADDR pc) | |
c906108c | 97 | { |
e1613aba | 98 | gdb_byte buf[4]; |
386c036b MK |
99 | unsigned long insn; |
100 | int i; | |
101 | ||
690668cc | 102 | /* If we can't read the instruction at PC, return zero. */ |
8defab1a | 103 | if (target_read_memory (pc, buf, sizeof (buf))) |
690668cc | 104 | return 0; |
c906108c | 105 | |
386c036b MK |
106 | insn = 0; |
107 | for (i = 0; i < sizeof (buf); i++) | |
108 | insn = (insn << 8) | buf[i]; | |
109 | return insn; | |
110 | } | |
42cdca6c MK |
111 | \f |
112 | ||
5465445a JB |
113 | /* Return non-zero if the instruction corresponding to PC is an "unimp" |
114 | instruction. */ | |
115 | ||
116 | static int | |
117 | sparc_is_unimp_insn (CORE_ADDR pc) | |
118 | { | |
119 | const unsigned long insn = sparc_fetch_instruction (pc); | |
120 | ||
121 | return ((insn & 0xc1c00000) == 0); | |
122 | } | |
123 | ||
42cdca6c MK |
124 | /* OpenBSD/sparc includes StackGhost, which according to the author's |
125 | website http://stackghost.cerias.purdue.edu "... transparently and | |
126 | automatically protects applications' stack frames; more | |
127 | specifically, it guards the return pointers. The protection | |
128 | mechanisms require no application source or binary modification and | |
129 | imposes only a negligible performance penalty." | |
130 | ||
131 | The same website provides the following description of how | |
132 | StackGhost works: | |
133 | ||
134 | "StackGhost interfaces with the kernel trap handler that would | |
135 | normally write out registers to the stack and the handler that | |
136 | would read them back in. By XORing a cookie into the | |
137 | return-address saved in the user stack when it is actually written | |
138 | to the stack, and then XOR it out when the return-address is pulled | |
139 | from the stack, StackGhost can cause attacker corrupted return | |
140 | pointers to behave in a manner the attacker cannot predict. | |
141 | StackGhost can also use several unused bits in the return pointer | |
142 | to detect a smashed return pointer and abort the process." | |
143 | ||
144 | For GDB this means that whenever we're reading %i7 from a stack | |
145 | frame's window save area, we'll have to XOR the cookie. | |
146 | ||
147 | More information on StackGuard can be found on in: | |
148 | ||
c378eb4e | 149 | Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated |
42cdca6c MK |
150 | Stack Protection." 2001. Published in USENIX Security Symposium |
151 | '01. */ | |
152 | ||
153 | /* Fetch StackGhost Per-Process XOR cookie. */ | |
154 | ||
155 | ULONGEST | |
e17a4113 | 156 | sparc_fetch_wcookie (struct gdbarch *gdbarch) |
42cdca6c | 157 | { |
e17a4113 | 158 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
baf92889 | 159 | struct target_ops *ops = ¤t_target; |
e1613aba | 160 | gdb_byte buf[8]; |
baf92889 MK |
161 | int len; |
162 | ||
13547ab6 | 163 | len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8); |
baf92889 MK |
164 | if (len == -1) |
165 | return 0; | |
42cdca6c | 166 | |
baf92889 MK |
167 | /* We should have either an 32-bit or an 64-bit cookie. */ |
168 | gdb_assert (len == 4 || len == 8); | |
169 | ||
e17a4113 | 170 | return extract_unsigned_integer (buf, len, byte_order); |
baf92889 | 171 | } |
386c036b | 172 | \f |
baf92889 | 173 | |
386c036b MK |
174 | /* The functions on this page are intended to be used to classify |
175 | function arguments. */ | |
c906108c | 176 | |
386c036b | 177 | /* Check whether TYPE is "Integral or Pointer". */ |
c906108c | 178 | |
386c036b MK |
179 | static int |
180 | sparc_integral_or_pointer_p (const struct type *type) | |
c906108c | 181 | { |
80ad1639 MK |
182 | int len = TYPE_LENGTH (type); |
183 | ||
386c036b | 184 | switch (TYPE_CODE (type)) |
c906108c | 185 | { |
386c036b MK |
186 | case TYPE_CODE_INT: |
187 | case TYPE_CODE_BOOL: | |
188 | case TYPE_CODE_CHAR: | |
189 | case TYPE_CODE_ENUM: | |
190 | case TYPE_CODE_RANGE: | |
80ad1639 MK |
191 | /* We have byte, half-word, word and extended-word/doubleword |
192 | integral types. The doubleword is an extension to the | |
193 | original 32-bit ABI by the SCD 2.4.x. */ | |
194 | return (len == 1 || len == 2 || len == 4 || len == 8); | |
386c036b MK |
195 | case TYPE_CODE_PTR: |
196 | case TYPE_CODE_REF: | |
80ad1639 MK |
197 | /* Allow either 32-bit or 64-bit pointers. */ |
198 | return (len == 4 || len == 8); | |
386c036b MK |
199 | default: |
200 | break; | |
201 | } | |
c906108c | 202 | |
386c036b MK |
203 | return 0; |
204 | } | |
c906108c | 205 | |
386c036b | 206 | /* Check whether TYPE is "Floating". */ |
c906108c | 207 | |
386c036b MK |
208 | static int |
209 | sparc_floating_p (const struct type *type) | |
210 | { | |
211 | switch (TYPE_CODE (type)) | |
c906108c | 212 | { |
386c036b MK |
213 | case TYPE_CODE_FLT: |
214 | { | |
215 | int len = TYPE_LENGTH (type); | |
216 | return (len == 4 || len == 8 || len == 16); | |
217 | } | |
218 | default: | |
219 | break; | |
220 | } | |
221 | ||
222 | return 0; | |
223 | } | |
c906108c | 224 | |
fe10a582 DM |
225 | /* Check whether TYPE is "Complex Floating". */ |
226 | ||
227 | static int | |
228 | sparc_complex_floating_p (const struct type *type) | |
229 | { | |
230 | switch (TYPE_CODE (type)) | |
231 | { | |
232 | case TYPE_CODE_COMPLEX: | |
233 | { | |
234 | int len = TYPE_LENGTH (type); | |
235 | return (len == 8 || len == 16 || len == 32); | |
236 | } | |
237 | default: | |
238 | break; | |
239 | } | |
240 | ||
241 | return 0; | |
242 | } | |
243 | ||
0497f5b0 JB |
244 | /* Check whether TYPE is "Structure or Union". |
245 | ||
246 | In terms of Ada subprogram calls, arrays are treated the same as | |
247 | struct and union types. So this function also returns non-zero | |
248 | for array types. */ | |
c906108c | 249 | |
386c036b MK |
250 | static int |
251 | sparc_structure_or_union_p (const struct type *type) | |
252 | { | |
253 | switch (TYPE_CODE (type)) | |
254 | { | |
255 | case TYPE_CODE_STRUCT: | |
256 | case TYPE_CODE_UNION: | |
0497f5b0 | 257 | case TYPE_CODE_ARRAY: |
386c036b MK |
258 | return 1; |
259 | default: | |
260 | break; | |
c906108c | 261 | } |
386c036b MK |
262 | |
263 | return 0; | |
c906108c | 264 | } |
386c036b MK |
265 | |
266 | /* Register information. */ | |
267 | ||
268 | static const char *sparc32_register_names[] = | |
5af923b0 | 269 | { |
386c036b MK |
270 | "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
271 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", | |
272 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", | |
273 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", | |
274 | ||
275 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
276 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
277 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
278 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
279 | ||
280 | "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" | |
5af923b0 MS |
281 | }; |
282 | ||
386c036b MK |
283 | /* Total number of registers. */ |
284 | #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) | |
c906108c | 285 | |
386c036b MK |
286 | /* We provide the aliases %d0..%d30 for the floating registers as |
287 | "psuedo" registers. */ | |
288 | ||
289 | static const char *sparc32_pseudo_register_names[] = | |
290 | { | |
291 | "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", | |
292 | "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" | |
293 | }; | |
294 | ||
295 | /* Total number of pseudo registers. */ | |
296 | #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) | |
297 | ||
298 | /* Return the name of register REGNUM. */ | |
299 | ||
300 | static const char * | |
d93859e2 | 301 | sparc32_register_name (struct gdbarch *gdbarch, int regnum) |
386c036b MK |
302 | { |
303 | if (regnum >= 0 && regnum < SPARC32_NUM_REGS) | |
304 | return sparc32_register_names[regnum]; | |
305 | ||
306 | if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS) | |
307 | return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS]; | |
308 | ||
309 | return NULL; | |
310 | } | |
2d457077 | 311 | \f |
209bd28e | 312 | /* Construct types for ISA-specific registers. */ |
2d457077 | 313 | |
209bd28e UW |
314 | static struct type * |
315 | sparc_psr_type (struct gdbarch *gdbarch) | |
316 | { | |
317 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2d457077 | 318 | |
209bd28e UW |
319 | if (!tdep->sparc_psr_type) |
320 | { | |
321 | struct type *type; | |
2d457077 | 322 | |
e9bb382b | 323 | type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 4); |
209bd28e UW |
324 | append_flags_type_flag (type, 5, "ET"); |
325 | append_flags_type_flag (type, 6, "PS"); | |
326 | append_flags_type_flag (type, 7, "S"); | |
327 | append_flags_type_flag (type, 12, "EF"); | |
328 | append_flags_type_flag (type, 13, "EC"); | |
2d457077 | 329 | |
209bd28e UW |
330 | tdep->sparc_psr_type = type; |
331 | } | |
332 | ||
333 | return tdep->sparc_psr_type; | |
334 | } | |
335 | ||
336 | static struct type * | |
337 | sparc_fsr_type (struct gdbarch *gdbarch) | |
2d457077 | 338 | { |
209bd28e UW |
339 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
340 | ||
341 | if (!tdep->sparc_fsr_type) | |
342 | { | |
343 | struct type *type; | |
344 | ||
e9bb382b | 345 | type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 4); |
209bd28e UW |
346 | append_flags_type_flag (type, 0, "NXA"); |
347 | append_flags_type_flag (type, 1, "DZA"); | |
348 | append_flags_type_flag (type, 2, "UFA"); | |
349 | append_flags_type_flag (type, 3, "OFA"); | |
350 | append_flags_type_flag (type, 4, "NVA"); | |
351 | append_flags_type_flag (type, 5, "NXC"); | |
352 | append_flags_type_flag (type, 6, "DZC"); | |
353 | append_flags_type_flag (type, 7, "UFC"); | |
354 | append_flags_type_flag (type, 8, "OFC"); | |
355 | append_flags_type_flag (type, 9, "NVC"); | |
356 | append_flags_type_flag (type, 22, "NS"); | |
357 | append_flags_type_flag (type, 23, "NXM"); | |
358 | append_flags_type_flag (type, 24, "DZM"); | |
359 | append_flags_type_flag (type, 25, "UFM"); | |
360 | append_flags_type_flag (type, 26, "OFM"); | |
361 | append_flags_type_flag (type, 27, "NVM"); | |
362 | ||
363 | tdep->sparc_fsr_type = type; | |
364 | } | |
365 | ||
366 | return tdep->sparc_fsr_type; | |
2d457077 | 367 | } |
386c036b MK |
368 | |
369 | /* Return the GDB type object for the "standard" data type of data in | |
c378eb4e | 370 | register REGNUM. */ |
386c036b MK |
371 | |
372 | static struct type * | |
373 | sparc32_register_type (struct gdbarch *gdbarch, int regnum) | |
374 | { | |
375 | if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) | |
0dfff4cb | 376 | return builtin_type (gdbarch)->builtin_float; |
386c036b MK |
377 | |
378 | if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) | |
0dfff4cb | 379 | return builtin_type (gdbarch)->builtin_double; |
386c036b MK |
380 | |
381 | if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) | |
0dfff4cb | 382 | return builtin_type (gdbarch)->builtin_data_ptr; |
386c036b MK |
383 | |
384 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) | |
0dfff4cb | 385 | return builtin_type (gdbarch)->builtin_func_ptr; |
386c036b | 386 | |
2d457077 | 387 | if (regnum == SPARC32_PSR_REGNUM) |
209bd28e | 388 | return sparc_psr_type (gdbarch); |
2d457077 MK |
389 | |
390 | if (regnum == SPARC32_FSR_REGNUM) | |
209bd28e | 391 | return sparc_fsr_type (gdbarch); |
2d457077 | 392 | |
df4df182 | 393 | return builtin_type (gdbarch)->builtin_int32; |
386c036b MK |
394 | } |
395 | ||
05d1431c | 396 | static enum register_status |
386c036b MK |
397 | sparc32_pseudo_register_read (struct gdbarch *gdbarch, |
398 | struct regcache *regcache, | |
e1613aba | 399 | int regnum, gdb_byte *buf) |
386c036b | 400 | { |
05d1431c PA |
401 | enum register_status status; |
402 | ||
386c036b MK |
403 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); |
404 | ||
405 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
05d1431c PA |
406 | status = regcache_raw_read (regcache, regnum, buf); |
407 | if (status == REG_VALID) | |
408 | status = regcache_raw_read (regcache, regnum + 1, buf + 4); | |
409 | return status; | |
386c036b MK |
410 | } |
411 | ||
412 | static void | |
413 | sparc32_pseudo_register_write (struct gdbarch *gdbarch, | |
414 | struct regcache *regcache, | |
e1613aba | 415 | int regnum, const gdb_byte *buf) |
386c036b MK |
416 | { |
417 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); | |
418 | ||
419 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
420 | regcache_raw_write (regcache, regnum, buf); | |
e1613aba | 421 | regcache_raw_write (regcache, regnum + 1, buf + 4); |
386c036b MK |
422 | } |
423 | \f | |
424 | ||
49a45ecf JB |
425 | static CORE_ADDR |
426 | sparc32_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) | |
427 | { | |
428 | /* The ABI requires double-word alignment. */ | |
429 | return address & ~0x7; | |
430 | } | |
431 | ||
386c036b MK |
432 | static CORE_ADDR |
433 | sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
82585c72 | 434 | CORE_ADDR funcaddr, |
386c036b MK |
435 | struct value **args, int nargs, |
436 | struct type *value_type, | |
e4fd649a UW |
437 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, |
438 | struct regcache *regcache) | |
c906108c | 439 | { |
e17a4113 UW |
440 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
441 | ||
386c036b MK |
442 | *bp_addr = sp - 4; |
443 | *real_pc = funcaddr; | |
444 | ||
d80b854b | 445 | if (using_struct_return (gdbarch, NULL, value_type)) |
c906108c | 446 | { |
e1613aba | 447 | gdb_byte buf[4]; |
386c036b MK |
448 | |
449 | /* This is an UNIMP instruction. */ | |
e17a4113 UW |
450 | store_unsigned_integer (buf, 4, byte_order, |
451 | TYPE_LENGTH (value_type) & 0x1fff); | |
386c036b MK |
452 | write_memory (sp - 8, buf, 4); |
453 | return sp - 8; | |
c906108c SS |
454 | } |
455 | ||
386c036b MK |
456 | return sp - 4; |
457 | } | |
458 | ||
459 | static CORE_ADDR | |
460 | sparc32_store_arguments (struct regcache *regcache, int nargs, | |
461 | struct value **args, CORE_ADDR sp, | |
462 | int struct_return, CORE_ADDR struct_addr) | |
463 | { | |
df4df182 | 464 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
e17a4113 | 465 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
386c036b MK |
466 | /* Number of words in the "parameter array". */ |
467 | int num_elements = 0; | |
468 | int element = 0; | |
469 | int i; | |
470 | ||
471 | for (i = 0; i < nargs; i++) | |
c906108c | 472 | { |
4991999e | 473 | struct type *type = value_type (args[i]); |
386c036b MK |
474 | int len = TYPE_LENGTH (type); |
475 | ||
476 | if (sparc_structure_or_union_p (type) | |
fe10a582 DM |
477 | || (sparc_floating_p (type) && len == 16) |
478 | || sparc_complex_floating_p (type)) | |
c906108c | 479 | { |
386c036b MK |
480 | /* Structure, Union and Quad-Precision Arguments. */ |
481 | sp -= len; | |
482 | ||
483 | /* Use doubleword alignment for these values. That's always | |
484 | correct, and wasting a few bytes shouldn't be a problem. */ | |
485 | sp &= ~0x7; | |
486 | ||
0fd88904 | 487 | write_memory (sp, value_contents (args[i]), len); |
386c036b MK |
488 | args[i] = value_from_pointer (lookup_pointer_type (type), sp); |
489 | num_elements++; | |
490 | } | |
491 | else if (sparc_floating_p (type)) | |
492 | { | |
493 | /* Floating arguments. */ | |
494 | gdb_assert (len == 4 || len == 8); | |
495 | num_elements += (len / 4); | |
c906108c | 496 | } |
c5aa993b JM |
497 | else |
498 | { | |
386c036b MK |
499 | /* Integral and pointer arguments. */ |
500 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
501 | ||
502 | if (len < 4) | |
df4df182 UW |
503 | args[i] = value_cast (builtin_type (gdbarch)->builtin_int32, |
504 | args[i]); | |
386c036b | 505 | num_elements += ((len + 3) / 4); |
c5aa993b | 506 | } |
c906108c | 507 | } |
c906108c | 508 | |
386c036b MK |
509 | /* Always allocate at least six words. */ |
510 | sp -= max (6, num_elements) * 4; | |
c906108c | 511 | |
386c036b MK |
512 | /* The psABI says that "Software convention requires space for the |
513 | struct/union return value pointer, even if the word is unused." */ | |
514 | sp -= 4; | |
c906108c | 515 | |
386c036b MK |
516 | /* The psABI says that "Although software convention and the |
517 | operating system require every stack frame to be doubleword | |
518 | aligned." */ | |
519 | sp &= ~0x7; | |
c906108c | 520 | |
386c036b | 521 | for (i = 0; i < nargs; i++) |
c906108c | 522 | { |
0fd88904 | 523 | const bfd_byte *valbuf = value_contents (args[i]); |
4991999e | 524 | struct type *type = value_type (args[i]); |
386c036b | 525 | int len = TYPE_LENGTH (type); |
c906108c | 526 | |
386c036b | 527 | gdb_assert (len == 4 || len == 8); |
c906108c | 528 | |
386c036b MK |
529 | if (element < 6) |
530 | { | |
531 | int regnum = SPARC_O0_REGNUM + element; | |
c906108c | 532 | |
386c036b MK |
533 | regcache_cooked_write (regcache, regnum, valbuf); |
534 | if (len > 4 && element < 5) | |
535 | regcache_cooked_write (regcache, regnum + 1, valbuf + 4); | |
536 | } | |
5af923b0 | 537 | |
386c036b MK |
538 | /* Always store the argument in memory. */ |
539 | write_memory (sp + 4 + element * 4, valbuf, len); | |
540 | element += len / 4; | |
541 | } | |
c906108c | 542 | |
386c036b | 543 | gdb_assert (element == num_elements); |
c906108c | 544 | |
386c036b | 545 | if (struct_return) |
c906108c | 546 | { |
e1613aba | 547 | gdb_byte buf[4]; |
c906108c | 548 | |
e17a4113 | 549 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
386c036b MK |
550 | write_memory (sp, buf, 4); |
551 | } | |
c906108c | 552 | |
386c036b | 553 | return sp; |
c906108c SS |
554 | } |
555 | ||
386c036b | 556 | static CORE_ADDR |
7d9b040b | 557 | sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
386c036b MK |
558 | struct regcache *regcache, CORE_ADDR bp_addr, |
559 | int nargs, struct value **args, CORE_ADDR sp, | |
560 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 561 | { |
386c036b MK |
562 | CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8)); |
563 | ||
564 | /* Set return address. */ | |
565 | regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); | |
566 | ||
567 | /* Set up function arguments. */ | |
568 | sp = sparc32_store_arguments (regcache, nargs, args, sp, | |
569 | struct_return, struct_addr); | |
570 | ||
571 | /* Allocate the 16-word window save area. */ | |
572 | sp -= 16 * 4; | |
c906108c | 573 | |
386c036b MK |
574 | /* Stack should be doubleword aligned at this point. */ |
575 | gdb_assert (sp % 8 == 0); | |
c906108c | 576 | |
386c036b MK |
577 | /* Finally, update the stack pointer. */ |
578 | regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); | |
579 | ||
580 | return sp; | |
581 | } | |
582 | \f | |
c906108c | 583 | |
386c036b MK |
584 | /* Use the program counter to determine the contents and size of a |
585 | breakpoint instruction. Return a pointer to a string of bytes that | |
586 | encode a breakpoint instruction, store the length of the string in | |
587 | *LEN and optionally adjust *PC to point to the correct memory | |
588 | location for inserting the breakpoint. */ | |
589 | ||
e1613aba | 590 | static const gdb_byte * |
67d57894 | 591 | sparc_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
386c036b | 592 | { |
864a1a37 | 593 | static const gdb_byte break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; |
c5aa993b | 594 | |
386c036b MK |
595 | *len = sizeof (break_insn); |
596 | return break_insn; | |
c906108c | 597 | } |
386c036b | 598 | \f |
c906108c | 599 | |
386c036b | 600 | /* Allocate and initialize a frame cache. */ |
c906108c | 601 | |
386c036b MK |
602 | static struct sparc_frame_cache * |
603 | sparc_alloc_frame_cache (void) | |
604 | { | |
605 | struct sparc_frame_cache *cache; | |
c906108c | 606 | |
386c036b | 607 | cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); |
c906108c | 608 | |
386c036b MK |
609 | /* Base address. */ |
610 | cache->base = 0; | |
611 | cache->pc = 0; | |
c906108c | 612 | |
386c036b MK |
613 | /* Frameless until proven otherwise. */ |
614 | cache->frameless_p = 1; | |
369c397b JB |
615 | cache->frame_offset = 0; |
616 | cache->saved_regs_mask = 0; | |
617 | cache->copied_regs_mask = 0; | |
386c036b MK |
618 | cache->struct_return_p = 0; |
619 | ||
620 | return cache; | |
621 | } | |
622 | ||
b0b92586 JB |
623 | /* GCC generates several well-known sequences of instructions at the begining |
624 | of each function prologue when compiling with -fstack-check. If one of | |
625 | such sequences starts at START_PC, then return the address of the | |
626 | instruction immediately past this sequence. Otherwise, return START_PC. */ | |
627 | ||
628 | static CORE_ADDR | |
629 | sparc_skip_stack_check (const CORE_ADDR start_pc) | |
630 | { | |
631 | CORE_ADDR pc = start_pc; | |
632 | unsigned long insn; | |
633 | int offset_stack_checking_sequence = 0; | |
2067c8d4 | 634 | int probing_loop = 0; |
b0b92586 JB |
635 | |
636 | /* With GCC, all stack checking sequences begin with the same two | |
2067c8d4 | 637 | instructions, plus an optional one in the case of a probing loop: |
b0b92586 | 638 | |
2067c8d4 JG |
639 | sethi <some immediate>, %g1 |
640 | sub %sp, %g1, %g1 | |
641 | ||
642 | or: | |
643 | ||
644 | sethi <some immediate>, %g1 | |
645 | sethi <some immediate>, %g4 | |
646 | sub %sp, %g1, %g1 | |
647 | ||
648 | or: | |
649 | ||
650 | sethi <some immediate>, %g1 | |
651 | sub %sp, %g1, %g1 | |
652 | sethi <some immediate>, %g4 | |
653 | ||
654 | If the optional instruction is found (setting g4), assume that a | |
655 | probing loop will follow. */ | |
656 | ||
657 | /* sethi <some immediate>, %g1 */ | |
b0b92586 JB |
658 | insn = sparc_fetch_instruction (pc); |
659 | pc = pc + 4; | |
660 | if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1)) | |
661 | return start_pc; | |
662 | ||
2067c8d4 | 663 | /* optional: sethi <some immediate>, %g4 */ |
b0b92586 JB |
664 | insn = sparc_fetch_instruction (pc); |
665 | pc = pc + 4; | |
2067c8d4 JG |
666 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) |
667 | { | |
668 | probing_loop = 1; | |
669 | insn = sparc_fetch_instruction (pc); | |
670 | pc = pc + 4; | |
671 | } | |
672 | ||
673 | /* sub %sp, %g1, %g1 */ | |
b0b92586 JB |
674 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) |
675 | && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1)) | |
676 | return start_pc; | |
677 | ||
678 | insn = sparc_fetch_instruction (pc); | |
679 | pc = pc + 4; | |
680 | ||
2067c8d4 JG |
681 | /* optional: sethi <some immediate>, %g4 */ |
682 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) | |
683 | { | |
684 | probing_loop = 1; | |
685 | insn = sparc_fetch_instruction (pc); | |
686 | pc = pc + 4; | |
687 | } | |
688 | ||
b0b92586 JB |
689 | /* First possible sequence: |
690 | [first two instructions above] | |
691 | clr [%g1 - some immediate] */ | |
692 | ||
693 | /* clr [%g1 - some immediate] */ | |
694 | if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
695 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
696 | { | |
697 | /* Valid stack-check sequence, return the new PC. */ | |
698 | return pc; | |
699 | } | |
700 | ||
701 | /* Second possible sequence: A small number of probes. | |
702 | [first two instructions above] | |
703 | clr [%g1] | |
704 | add %g1, -<some immediate>, %g1 | |
705 | clr [%g1] | |
706 | [repeat the two instructions above any (small) number of times] | |
707 | clr [%g1 - some immediate] */ | |
708 | ||
709 | /* clr [%g1] */ | |
710 | else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
711 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
712 | { | |
713 | while (1) | |
714 | { | |
715 | /* add %g1, -<some immediate>, %g1 */ | |
716 | insn = sparc_fetch_instruction (pc); | |
717 | pc = pc + 4; | |
718 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
719 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
720 | break; | |
721 | ||
722 | /* clr [%g1] */ | |
723 | insn = sparc_fetch_instruction (pc); | |
724 | pc = pc + 4; | |
725 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
726 | && X_RD (insn) == 0 && X_RS1 (insn) == 1)) | |
727 | return start_pc; | |
728 | } | |
729 | ||
730 | /* clr [%g1 - some immediate] */ | |
731 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
732 | && X_RS1 (insn) == 1 && X_RD (insn) == 0)) | |
733 | return start_pc; | |
734 | ||
735 | /* We found a valid stack-check sequence, return the new PC. */ | |
736 | return pc; | |
737 | } | |
738 | ||
739 | /* Third sequence: A probing loop. | |
2067c8d4 | 740 | [first three instructions above] |
b0b92586 JB |
741 | sub %g1, %g4, %g4 |
742 | cmp %g1, %g4 | |
743 | be <disp> | |
744 | add %g1, -<some immediate>, %g1 | |
745 | ba <disp> | |
746 | clr [%g1] | |
2067c8d4 JG |
747 | |
748 | And an optional last probe for the remainder: | |
749 | ||
b0b92586 JB |
750 | clr [%g4 - some immediate] */ |
751 | ||
2067c8d4 | 752 | if (probing_loop) |
b0b92586 JB |
753 | { |
754 | /* sub %g1, %g4, %g4 */ | |
b0b92586 JB |
755 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) |
756 | && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
757 | return start_pc; | |
758 | ||
759 | /* cmp %g1, %g4 */ | |
760 | insn = sparc_fetch_instruction (pc); | |
761 | pc = pc + 4; | |
762 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn) | |
763 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
764 | return start_pc; | |
765 | ||
766 | /* be <disp> */ | |
767 | insn = sparc_fetch_instruction (pc); | |
768 | pc = pc + 4; | |
769 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1)) | |
770 | return start_pc; | |
771 | ||
772 | /* add %g1, -<some immediate>, %g1 */ | |
773 | insn = sparc_fetch_instruction (pc); | |
774 | pc = pc + 4; | |
775 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
776 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
777 | return start_pc; | |
778 | ||
779 | /* ba <disp> */ | |
780 | insn = sparc_fetch_instruction (pc); | |
781 | pc = pc + 4; | |
782 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8)) | |
783 | return start_pc; | |
784 | ||
2067c8d4 | 785 | /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */ |
b0b92586 JB |
786 | insn = sparc_fetch_instruction (pc); |
787 | pc = pc + 4; | |
2067c8d4 JG |
788 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 |
789 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 | |
790 | && (!X_I(insn) || X_SIMM13 (insn) == 0))) | |
b0b92586 JB |
791 | return start_pc; |
792 | ||
2067c8d4 JG |
793 | /* We found a valid stack-check sequence, return the new PC. */ |
794 | ||
795 | /* optional: clr [%g4 - some immediate] */ | |
b0b92586 JB |
796 | insn = sparc_fetch_instruction (pc); |
797 | pc = pc + 4; | |
798 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
799 | && X_RS1 (insn) == 4 && X_RD (insn) == 0)) | |
2067c8d4 JG |
800 | return pc - 4; |
801 | else | |
802 | return pc; | |
b0b92586 JB |
803 | } |
804 | ||
805 | /* No stack check code in our prologue, return the start_pc. */ | |
806 | return start_pc; | |
807 | } | |
808 | ||
369c397b JB |
809 | /* Record the effect of a SAVE instruction on CACHE. */ |
810 | ||
811 | void | |
812 | sparc_record_save_insn (struct sparc_frame_cache *cache) | |
813 | { | |
814 | /* The frame is set up. */ | |
815 | cache->frameless_p = 0; | |
816 | ||
817 | /* The frame pointer contains the CFA. */ | |
818 | cache->frame_offset = 0; | |
819 | ||
820 | /* The `local' and `in' registers are all saved. */ | |
821 | cache->saved_regs_mask = 0xffff; | |
822 | ||
823 | /* The `out' registers are all renamed. */ | |
824 | cache->copied_regs_mask = 0xff; | |
825 | } | |
826 | ||
827 | /* Do a full analysis of the prologue at PC and update CACHE accordingly. | |
828 | Bail out early if CURRENT_PC is reached. Return the address where | |
829 | the analysis stopped. | |
830 | ||
831 | We handle both the traditional register window model and the single | |
832 | register window (aka flat) model. */ | |
833 | ||
386c036b | 834 | CORE_ADDR |
be8626e0 MD |
835 | sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, |
836 | CORE_ADDR current_pc, struct sparc_frame_cache *cache) | |
c906108c | 837 | { |
be8626e0 | 838 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
386c036b MK |
839 | unsigned long insn; |
840 | int offset = 0; | |
c906108c | 841 | int dest = -1; |
c906108c | 842 | |
b0b92586 JB |
843 | pc = sparc_skip_stack_check (pc); |
844 | ||
386c036b MK |
845 | if (current_pc <= pc) |
846 | return current_pc; | |
847 | ||
848 | /* We have to handle to "Procedure Linkage Table" (PLT) special. On | |
849 | SPARC the linker usually defines a symbol (typically | |
850 | _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. | |
851 | This symbol makes us end up here with PC pointing at the start of | |
852 | the PLT and CURRENT_PC probably pointing at a PLT entry. If we | |
853 | would do our normal prologue analysis, we would probably conclude | |
854 | that we've got a frame when in reality we don't, since the | |
855 | dynamic linker patches up the first PLT with some code that | |
856 | starts with a SAVE instruction. Patch up PC such that it points | |
857 | at the start of our PLT entry. */ | |
858 | if (tdep->plt_entry_size > 0 && in_plt_section (current_pc, NULL)) | |
859 | pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); | |
c906108c | 860 | |
386c036b MK |
861 | insn = sparc_fetch_instruction (pc); |
862 | ||
369c397b JB |
863 | /* Recognize store insns and record their sources. */ |
864 | while (X_OP (insn) == 3 | |
865 | && (X_OP3 (insn) == 0x4 /* stw */ | |
866 | || X_OP3 (insn) == 0x7 /* std */ | |
867 | || X_OP3 (insn) == 0xe) /* stx */ | |
868 | && X_RS1 (insn) == SPARC_SP_REGNUM) | |
869 | { | |
870 | int regnum = X_RD (insn); | |
871 | ||
872 | /* Recognize stores into the corresponding stack slots. */ | |
873 | if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM | |
874 | && ((X_I (insn) | |
875 | && X_SIMM13 (insn) == (X_OP3 (insn) == 0xe | |
876 | ? (regnum - SPARC_L0_REGNUM) * 8 + BIAS | |
877 | : (regnum - SPARC_L0_REGNUM) * 4)) | |
878 | || (!X_I (insn) && regnum == SPARC_L0_REGNUM))) | |
879 | { | |
880 | cache->saved_regs_mask |= (1 << (regnum - SPARC_L0_REGNUM)); | |
881 | if (X_OP3 (insn) == 0x7) | |
882 | cache->saved_regs_mask |= (1 << (regnum + 1 - SPARC_L0_REGNUM)); | |
883 | } | |
884 | ||
885 | offset += 4; | |
886 | ||
887 | insn = sparc_fetch_instruction (pc + offset); | |
888 | } | |
889 | ||
386c036b MK |
890 | /* Recognize a SETHI insn and record its destination. */ |
891 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) | |
c906108c SS |
892 | { |
893 | dest = X_RD (insn); | |
386c036b MK |
894 | offset += 4; |
895 | ||
369c397b | 896 | insn = sparc_fetch_instruction (pc + offset); |
c906108c SS |
897 | } |
898 | ||
386c036b MK |
899 | /* Allow for an arithmetic operation on DEST or %g1. */ |
900 | if (X_OP (insn) == 2 && X_I (insn) | |
c906108c SS |
901 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) |
902 | { | |
386c036b | 903 | offset += 4; |
c906108c | 904 | |
369c397b | 905 | insn = sparc_fetch_instruction (pc + offset); |
c906108c | 906 | } |
c906108c | 907 | |
386c036b MK |
908 | /* Check for the SAVE instruction that sets up the frame. */ |
909 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) | |
c906108c | 910 | { |
369c397b JB |
911 | sparc_record_save_insn (cache); |
912 | offset += 4; | |
913 | return pc + offset; | |
914 | } | |
915 | ||
916 | /* Check for an arithmetic operation on %sp. */ | |
917 | if (X_OP (insn) == 2 | |
918 | && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) | |
919 | && X_RS1 (insn) == SPARC_SP_REGNUM | |
920 | && X_RD (insn) == SPARC_SP_REGNUM) | |
921 | { | |
922 | if (X_I (insn)) | |
923 | { | |
924 | cache->frame_offset = X_SIMM13 (insn); | |
925 | if (X_OP3 (insn) == 0) | |
926 | cache->frame_offset = -cache->frame_offset; | |
927 | } | |
928 | offset += 4; | |
929 | ||
930 | insn = sparc_fetch_instruction (pc + offset); | |
931 | ||
932 | /* Check for an arithmetic operation that sets up the frame. */ | |
933 | if (X_OP (insn) == 2 | |
934 | && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) | |
935 | && X_RS1 (insn) == SPARC_SP_REGNUM | |
936 | && X_RD (insn) == SPARC_FP_REGNUM) | |
937 | { | |
938 | cache->frameless_p = 0; | |
939 | cache->frame_offset = 0; | |
940 | /* We could check that the amount subtracted to %sp above is the | |
941 | same as the one added here, but this seems superfluous. */ | |
942 | cache->copied_regs_mask |= 0x40; | |
943 | offset += 4; | |
944 | ||
945 | insn = sparc_fetch_instruction (pc + offset); | |
946 | } | |
947 | ||
948 | /* Check for a move (or) operation that copies the return register. */ | |
949 | if (X_OP (insn) == 2 | |
950 | && X_OP3 (insn) == 0x2 | |
951 | && !X_I (insn) | |
952 | && X_RS1 (insn) == SPARC_G0_REGNUM | |
953 | && X_RS2 (insn) == SPARC_O7_REGNUM | |
954 | && X_RD (insn) == SPARC_I7_REGNUM) | |
955 | { | |
956 | cache->copied_regs_mask |= 0x80; | |
957 | offset += 4; | |
958 | } | |
959 | ||
960 | return pc + offset; | |
c906108c SS |
961 | } |
962 | ||
963 | return pc; | |
964 | } | |
965 | ||
386c036b | 966 | static CORE_ADDR |
236369e7 | 967 | sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) |
386c036b MK |
968 | { |
969 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
236369e7 | 970 | return frame_unwind_register_unsigned (this_frame, tdep->pc_regnum); |
386c036b MK |
971 | } |
972 | ||
973 | /* Return PC of first real instruction of the function starting at | |
974 | START_PC. */ | |
f510d44e | 975 | |
386c036b | 976 | static CORE_ADDR |
6093d2eb | 977 | sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 978 | { |
f510d44e DM |
979 | struct symtab_and_line sal; |
980 | CORE_ADDR func_start, func_end; | |
386c036b | 981 | struct sparc_frame_cache cache; |
f510d44e DM |
982 | |
983 | /* This is the preferred method, find the end of the prologue by | |
984 | using the debugging information. */ | |
985 | if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) | |
986 | { | |
987 | sal = find_pc_line (func_start, 0); | |
988 | ||
989 | if (sal.end < func_end | |
990 | && start_pc <= sal.end) | |
991 | return sal.end; | |
992 | } | |
993 | ||
be8626e0 | 994 | start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache); |
075ccec8 MK |
995 | |
996 | /* The psABI says that "Although the first 6 words of arguments | |
997 | reside in registers, the standard stack frame reserves space for | |
998 | them.". It also suggests that a function may use that space to | |
999 | "write incoming arguments 0 to 5" into that space, and that's | |
1000 | indeed what GCC seems to be doing. In that case GCC will | |
1001 | generate debug information that points to the stack slots instead | |
1002 | of the registers, so we should consider the instructions that | |
369c397b | 1003 | write out these incoming arguments onto the stack. */ |
075ccec8 | 1004 | |
369c397b | 1005 | while (1) |
075ccec8 MK |
1006 | { |
1007 | unsigned long insn = sparc_fetch_instruction (start_pc); | |
1008 | ||
369c397b JB |
1009 | /* Recognize instructions that store incoming arguments into the |
1010 | corresponding stack slots. */ | |
1011 | if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 | |
1012 | && X_I (insn) && X_RS1 (insn) == SPARC_FP_REGNUM) | |
075ccec8 | 1013 | { |
369c397b JB |
1014 | int regnum = X_RD (insn); |
1015 | ||
1016 | /* Case of arguments still in %o[0..5]. */ | |
1017 | if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O5_REGNUM | |
1018 | && !(cache.copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM))) | |
1019 | && X_SIMM13 (insn) == 68 + (regnum - SPARC_O0_REGNUM) * 4) | |
1020 | { | |
1021 | start_pc += 4; | |
1022 | continue; | |
1023 | } | |
1024 | ||
1025 | /* Case of arguments copied into %i[0..5]. */ | |
1026 | if (regnum >= SPARC_I0_REGNUM && regnum <= SPARC_I5_REGNUM | |
1027 | && (cache.copied_regs_mask & (1 << (regnum - SPARC_I0_REGNUM))) | |
1028 | && X_SIMM13 (insn) == 68 + (regnum - SPARC_I0_REGNUM) * 4) | |
1029 | { | |
1030 | start_pc += 4; | |
1031 | continue; | |
1032 | } | |
075ccec8 MK |
1033 | } |
1034 | ||
1035 | break; | |
1036 | } | |
1037 | ||
1038 | return start_pc; | |
c906108c SS |
1039 | } |
1040 | ||
386c036b | 1041 | /* Normal frames. */ |
9319a2fe | 1042 | |
386c036b | 1043 | struct sparc_frame_cache * |
236369e7 | 1044 | sparc_frame_cache (struct frame_info *this_frame, void **this_cache) |
9319a2fe | 1045 | { |
386c036b | 1046 | struct sparc_frame_cache *cache; |
9319a2fe | 1047 | |
386c036b MK |
1048 | if (*this_cache) |
1049 | return *this_cache; | |
c906108c | 1050 | |
386c036b MK |
1051 | cache = sparc_alloc_frame_cache (); |
1052 | *this_cache = cache; | |
c906108c | 1053 | |
236369e7 | 1054 | cache->pc = get_frame_func (this_frame); |
386c036b | 1055 | if (cache->pc != 0) |
236369e7 JB |
1056 | sparc_analyze_prologue (get_frame_arch (this_frame), cache->pc, |
1057 | get_frame_pc (this_frame), cache); | |
386c036b MK |
1058 | |
1059 | if (cache->frameless_p) | |
c906108c | 1060 | { |
cbeae229 MK |
1061 | /* This function is frameless, so %fp (%i6) holds the frame |
1062 | pointer for our calling frame. Use %sp (%o6) as this frame's | |
1063 | base address. */ | |
1064 | cache->base = | |
236369e7 | 1065 | get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
cbeae229 MK |
1066 | } |
1067 | else | |
1068 | { | |
1069 | /* For normal frames, %fp (%i6) holds the frame pointer, the | |
1070 | base address for the current stack frame. */ | |
1071 | cache->base = | |
236369e7 | 1072 | get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM); |
c906108c | 1073 | } |
c906108c | 1074 | |
369c397b JB |
1075 | cache->base += cache->frame_offset; |
1076 | ||
5b2d44a0 MK |
1077 | if (cache->base & 1) |
1078 | cache->base += BIAS; | |
1079 | ||
386c036b | 1080 | return cache; |
c906108c | 1081 | } |
c906108c | 1082 | |
aff37fc1 DM |
1083 | static int |
1084 | sparc32_struct_return_from_sym (struct symbol *sym) | |
1085 | { | |
1086 | struct type *type = check_typedef (SYMBOL_TYPE (sym)); | |
1087 | enum type_code code = TYPE_CODE (type); | |
1088 | ||
1089 | if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) | |
1090 | { | |
1091 | type = check_typedef (TYPE_TARGET_TYPE (type)); | |
1092 | if (sparc_structure_or_union_p (type) | |
1093 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
1094 | return 1; | |
1095 | } | |
1096 | ||
1097 | return 0; | |
1098 | } | |
1099 | ||
386c036b | 1100 | struct sparc_frame_cache * |
236369e7 | 1101 | sparc32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 1102 | { |
386c036b MK |
1103 | struct sparc_frame_cache *cache; |
1104 | struct symbol *sym; | |
c906108c | 1105 | |
386c036b MK |
1106 | if (*this_cache) |
1107 | return *this_cache; | |
c906108c | 1108 | |
236369e7 | 1109 | cache = sparc_frame_cache (this_frame, this_cache); |
c906108c | 1110 | |
386c036b MK |
1111 | sym = find_pc_function (cache->pc); |
1112 | if (sym) | |
c906108c | 1113 | { |
aff37fc1 | 1114 | cache->struct_return_p = sparc32_struct_return_from_sym (sym); |
c906108c | 1115 | } |
5465445a JB |
1116 | else |
1117 | { | |
1118 | /* There is no debugging information for this function to | |
1119 | help us determine whether this function returns a struct | |
1120 | or not. So we rely on another heuristic which is to check | |
1121 | the instruction at the return address and see if this is | |
1122 | an "unimp" instruction. If it is, then it is a struct-return | |
1123 | function. */ | |
1124 | CORE_ADDR pc; | |
369c397b JB |
1125 | int regnum = |
1126 | (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; | |
5465445a | 1127 | |
236369e7 | 1128 | pc = get_frame_register_unsigned (this_frame, regnum) + 8; |
5465445a JB |
1129 | if (sparc_is_unimp_insn (pc)) |
1130 | cache->struct_return_p = 1; | |
1131 | } | |
c906108c | 1132 | |
386c036b MK |
1133 | return cache; |
1134 | } | |
1135 | ||
1136 | static void | |
236369e7 | 1137 | sparc32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
386c036b MK |
1138 | struct frame_id *this_id) |
1139 | { | |
1140 | struct sparc_frame_cache *cache = | |
236369e7 | 1141 | sparc32_frame_cache (this_frame, this_cache); |
386c036b MK |
1142 | |
1143 | /* This marks the outermost frame. */ | |
1144 | if (cache->base == 0) | |
1145 | return; | |
1146 | ||
1147 | (*this_id) = frame_id_build (cache->base, cache->pc); | |
1148 | } | |
c906108c | 1149 | |
236369e7 JB |
1150 | static struct value * |
1151 | sparc32_frame_prev_register (struct frame_info *this_frame, | |
1152 | void **this_cache, int regnum) | |
386c036b | 1153 | { |
e17a4113 | 1154 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
386c036b | 1155 | struct sparc_frame_cache *cache = |
236369e7 | 1156 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 1157 | |
386c036b | 1158 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) |
c906108c | 1159 | { |
236369e7 | 1160 | CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; |
386c036b | 1161 | |
236369e7 JB |
1162 | /* If this functions has a Structure, Union or Quad-Precision |
1163 | return value, we have to skip the UNIMP instruction that encodes | |
1164 | the size of the structure. */ | |
1165 | if (cache->struct_return_p) | |
1166 | pc += 4; | |
386c036b | 1167 | |
369c397b JB |
1168 | regnum = |
1169 | (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; | |
236369e7 JB |
1170 | pc += get_frame_register_unsigned (this_frame, regnum) + 8; |
1171 | return frame_unwind_got_constant (this_frame, regnum, pc); | |
c906108c SS |
1172 | } |
1173 | ||
42cdca6c MK |
1174 | /* Handle StackGhost. */ |
1175 | { | |
e17a4113 | 1176 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
42cdca6c MK |
1177 | |
1178 | if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM) | |
1179 | { | |
236369e7 JB |
1180 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
1181 | ULONGEST i7; | |
1182 | ||
1183 | /* Read the value in from memory. */ | |
1184 | i7 = get_frame_memory_unsigned (this_frame, addr, 4); | |
1185 | return frame_unwind_got_constant (this_frame, regnum, i7 ^ wcookie); | |
42cdca6c MK |
1186 | } |
1187 | } | |
1188 | ||
369c397b | 1189 | /* The previous frame's `local' and `in' registers may have been saved |
386c036b | 1190 | in the register save area. */ |
369c397b JB |
1191 | if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM |
1192 | && (cache->saved_regs_mask & (1 << (regnum - SPARC_L0_REGNUM)))) | |
c906108c | 1193 | { |
236369e7 | 1194 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
386c036b | 1195 | |
236369e7 | 1196 | return frame_unwind_got_memory (this_frame, regnum, addr); |
386c036b | 1197 | } |
c906108c | 1198 | |
369c397b JB |
1199 | /* The previous frame's `out' registers may be accessible as the current |
1200 | frame's `in' registers. */ | |
1201 | if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM | |
1202 | && (cache->copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM)))) | |
386c036b | 1203 | regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); |
5af923b0 | 1204 | |
236369e7 | 1205 | return frame_unwind_got_register (this_frame, regnum, regnum); |
386c036b | 1206 | } |
c906108c | 1207 | |
386c036b MK |
1208 | static const struct frame_unwind sparc32_frame_unwind = |
1209 | { | |
1210 | NORMAL_FRAME, | |
8fbca658 | 1211 | default_frame_unwind_stop_reason, |
386c036b | 1212 | sparc32_frame_this_id, |
236369e7 JB |
1213 | sparc32_frame_prev_register, |
1214 | NULL, | |
1215 | default_frame_sniffer | |
386c036b | 1216 | }; |
386c036b | 1217 | \f |
c906108c | 1218 | |
386c036b | 1219 | static CORE_ADDR |
236369e7 | 1220 | sparc32_frame_base_address (struct frame_info *this_frame, void **this_cache) |
386c036b MK |
1221 | { |
1222 | struct sparc_frame_cache *cache = | |
236369e7 | 1223 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 1224 | |
386c036b MK |
1225 | return cache->base; |
1226 | } | |
c906108c | 1227 | |
386c036b MK |
1228 | static const struct frame_base sparc32_frame_base = |
1229 | { | |
1230 | &sparc32_frame_unwind, | |
1231 | sparc32_frame_base_address, | |
1232 | sparc32_frame_base_address, | |
1233 | sparc32_frame_base_address | |
1234 | }; | |
c906108c | 1235 | |
386c036b | 1236 | static struct frame_id |
236369e7 | 1237 | sparc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
386c036b MK |
1238 | { |
1239 | CORE_ADDR sp; | |
5af923b0 | 1240 | |
236369e7 | 1241 | sp = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
5b2d44a0 MK |
1242 | if (sp & 1) |
1243 | sp += BIAS; | |
236369e7 | 1244 | return frame_id_build (sp, get_frame_pc (this_frame)); |
386c036b MK |
1245 | } |
1246 | \f | |
c906108c | 1247 | |
3923a2b2 MK |
1248 | /* Extract a function return value of TYPE from REGCACHE, and copy |
1249 | that into VALBUF. */ | |
5af923b0 | 1250 | |
386c036b MK |
1251 | static void |
1252 | sparc32_extract_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1253 | gdb_byte *valbuf) |
386c036b MK |
1254 | { |
1255 | int len = TYPE_LENGTH (type); | |
fe10a582 | 1256 | gdb_byte buf[32]; |
c906108c | 1257 | |
386c036b MK |
1258 | gdb_assert (!sparc_structure_or_union_p (type)); |
1259 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 1260 | |
fe10a582 | 1261 | if (sparc_floating_p (type) || sparc_complex_floating_p (type)) |
5af923b0 | 1262 | { |
386c036b MK |
1263 | /* Floating return values. */ |
1264 | regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf); | |
1265 | if (len > 4) | |
1266 | regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4); | |
fe10a582 DM |
1267 | if (len > 8) |
1268 | { | |
1269 | regcache_cooked_read (regcache, SPARC_F2_REGNUM, buf + 8); | |
1270 | regcache_cooked_read (regcache, SPARC_F3_REGNUM, buf + 12); | |
1271 | } | |
1272 | if (len > 16) | |
1273 | { | |
1274 | regcache_cooked_read (regcache, SPARC_F4_REGNUM, buf + 16); | |
1275 | regcache_cooked_read (regcache, SPARC_F5_REGNUM, buf + 20); | |
1276 | regcache_cooked_read (regcache, SPARC_F6_REGNUM, buf + 24); | |
1277 | regcache_cooked_read (regcache, SPARC_F7_REGNUM, buf + 28); | |
1278 | } | |
386c036b | 1279 | memcpy (valbuf, buf, len); |
5af923b0 MS |
1280 | } |
1281 | else | |
1282 | { | |
386c036b MK |
1283 | /* Integral and pointer return values. */ |
1284 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
c906108c | 1285 | |
386c036b MK |
1286 | regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); |
1287 | if (len > 4) | |
1288 | { | |
1289 | regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4); | |
1290 | gdb_assert (len == 8); | |
1291 | memcpy (valbuf, buf, 8); | |
1292 | } | |
1293 | else | |
1294 | { | |
1295 | /* Just stripping off any unused bytes should preserve the | |
1296 | signed-ness just fine. */ | |
1297 | memcpy (valbuf, buf + 4 - len, len); | |
1298 | } | |
1299 | } | |
1300 | } | |
c906108c | 1301 | |
3923a2b2 MK |
1302 | /* Store the function return value of type TYPE from VALBUF into |
1303 | REGCACHE. */ | |
c906108c | 1304 | |
386c036b MK |
1305 | static void |
1306 | sparc32_store_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1307 | const gdb_byte *valbuf) |
386c036b MK |
1308 | { |
1309 | int len = TYPE_LENGTH (type); | |
e1613aba | 1310 | gdb_byte buf[8]; |
c906108c | 1311 | |
386c036b MK |
1312 | gdb_assert (!sparc_structure_or_union_p (type)); |
1313 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
a9789a6b | 1314 | gdb_assert (len <= 8); |
c906108c | 1315 | |
fe10a582 | 1316 | if (sparc_floating_p (type) || sparc_complex_floating_p (type)) |
386c036b MK |
1317 | { |
1318 | /* Floating return values. */ | |
1319 | memcpy (buf, valbuf, len); | |
1320 | regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf); | |
1321 | if (len > 4) | |
1322 | regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4); | |
fe10a582 DM |
1323 | if (len > 8) |
1324 | { | |
1325 | regcache_cooked_write (regcache, SPARC_F2_REGNUM, buf + 8); | |
1326 | regcache_cooked_write (regcache, SPARC_F3_REGNUM, buf + 12); | |
1327 | } | |
1328 | if (len > 16) | |
1329 | { | |
1330 | regcache_cooked_write (regcache, SPARC_F4_REGNUM, buf + 16); | |
1331 | regcache_cooked_write (regcache, SPARC_F5_REGNUM, buf + 20); | |
1332 | regcache_cooked_write (regcache, SPARC_F6_REGNUM, buf + 24); | |
1333 | regcache_cooked_write (regcache, SPARC_F7_REGNUM, buf + 28); | |
1334 | } | |
386c036b MK |
1335 | } |
1336 | else | |
c906108c | 1337 | { |
386c036b MK |
1338 | /* Integral and pointer return values. */ |
1339 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
1340 | ||
1341 | if (len > 4) | |
2757dd86 | 1342 | { |
386c036b MK |
1343 | gdb_assert (len == 8); |
1344 | memcpy (buf, valbuf, 8); | |
1345 | regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4); | |
2757dd86 AC |
1346 | } |
1347 | else | |
1348 | { | |
386c036b MK |
1349 | /* ??? Do we need to do any sign-extension here? */ |
1350 | memcpy (buf + 4 - len, valbuf, len); | |
2757dd86 | 1351 | } |
386c036b | 1352 | regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); |
c906108c SS |
1353 | } |
1354 | } | |
1355 | ||
b9d4c5ed | 1356 | static enum return_value_convention |
6a3a010b | 1357 | sparc32_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
1358 | struct type *type, struct regcache *regcache, |
1359 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
b9d4c5ed | 1360 | { |
e17a4113 UW |
1361 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1362 | ||
0a8f48b9 MK |
1363 | /* The psABI says that "...every stack frame reserves the word at |
1364 | %fp+64. If a function returns a structure, union, or | |
1365 | quad-precision value, this word should hold the address of the | |
1366 | object into which the return value should be copied." This | |
1367 | guarantees that we can always find the return value, not just | |
1368 | before the function returns. */ | |
1369 | ||
b9d4c5ed MK |
1370 | if (sparc_structure_or_union_p (type) |
1371 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
0a8f48b9 MK |
1372 | { |
1373 | if (readbuf) | |
1374 | { | |
1375 | ULONGEST sp; | |
1376 | CORE_ADDR addr; | |
1377 | ||
1378 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
e17a4113 | 1379 | addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); |
0a8f48b9 MK |
1380 | read_memory (addr, readbuf, TYPE_LENGTH (type)); |
1381 | } | |
1382 | ||
1383 | return RETURN_VALUE_ABI_PRESERVES_ADDRESS; | |
1384 | } | |
b9d4c5ed MK |
1385 | |
1386 | if (readbuf) | |
1387 | sparc32_extract_return_value (type, regcache, readbuf); | |
1388 | if (writebuf) | |
1389 | sparc32_store_return_value (type, regcache, writebuf); | |
1390 | ||
1391 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1392 | } | |
1393 | ||
386c036b MK |
1394 | static int |
1395 | sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) | |
c906108c | 1396 | { |
386c036b | 1397 | return (sparc_structure_or_union_p (type) |
fe10a582 DM |
1398 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16) |
1399 | || sparc_complex_floating_p (type)); | |
386c036b | 1400 | } |
c906108c | 1401 | |
aff37fc1 | 1402 | static int |
4a4e5149 | 1403 | sparc32_dwarf2_struct_return_p (struct frame_info *this_frame) |
aff37fc1 | 1404 | { |
236369e7 | 1405 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
aff37fc1 DM |
1406 | struct symbol *sym = find_pc_function (pc); |
1407 | ||
1408 | if (sym) | |
1409 | return sparc32_struct_return_from_sym (sym); | |
1410 | return 0; | |
1411 | } | |
1412 | ||
f5a9b87d DM |
1413 | static void |
1414 | sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 | 1415 | struct dwarf2_frame_state_reg *reg, |
4a4e5149 | 1416 | struct frame_info *this_frame) |
f5a9b87d | 1417 | { |
aff37fc1 DM |
1418 | int off; |
1419 | ||
f5a9b87d DM |
1420 | switch (regnum) |
1421 | { | |
1422 | case SPARC_G0_REGNUM: | |
1423 | /* Since %g0 is always zero, there is no point in saving it, and | |
1424 | people will be inclined omit it from the CFI. Make sure we | |
1425 | don't warn about that. */ | |
1426 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
1427 | break; | |
1428 | case SPARC_SP_REGNUM: | |
1429 | reg->how = DWARF2_FRAME_REG_CFA; | |
1430 | break; | |
1431 | case SPARC32_PC_REGNUM: | |
f5a9b87d DM |
1432 | case SPARC32_NPC_REGNUM: |
1433 | reg->how = DWARF2_FRAME_REG_RA_OFFSET; | |
aff37fc1 | 1434 | off = 8; |
4a4e5149 | 1435 | if (sparc32_dwarf2_struct_return_p (this_frame)) |
aff37fc1 DM |
1436 | off += 4; |
1437 | if (regnum == SPARC32_NPC_REGNUM) | |
1438 | off += 4; | |
1439 | reg->loc.offset = off; | |
f5a9b87d DM |
1440 | break; |
1441 | } | |
1442 | } | |
1443 | ||
386c036b MK |
1444 | \f |
1445 | /* The SPARC Architecture doesn't have hardware single-step support, | |
1446 | and most operating systems don't implement it either, so we provide | |
1447 | software single-step mechanism. */ | |
c906108c | 1448 | |
386c036b | 1449 | static CORE_ADDR |
0b1b3e42 | 1450 | sparc_analyze_control_transfer (struct frame_info *frame, |
c893be75 | 1451 | CORE_ADDR pc, CORE_ADDR *npc) |
386c036b MK |
1452 | { |
1453 | unsigned long insn = sparc_fetch_instruction (pc); | |
1454 | int conditional_p = X_COND (insn) & 0x7; | |
8d1b3521 | 1455 | int branch_p = 0, fused_p = 0; |
386c036b | 1456 | long offset = 0; /* Must be signed for sign-extend. */ |
c906108c | 1457 | |
8d1b3521 | 1458 | if (X_OP (insn) == 0 && X_OP2 (insn) == 3) |
c906108c | 1459 | { |
8d1b3521 DM |
1460 | if ((insn & 0x10000000) == 0) |
1461 | { | |
1462 | /* Branch on Integer Register with Prediction (BPr). */ | |
1463 | branch_p = 1; | |
1464 | conditional_p = 1; | |
1465 | } | |
1466 | else | |
1467 | { | |
1468 | /* Compare and Branch */ | |
1469 | branch_p = 1; | |
1470 | fused_p = 1; | |
1471 | offset = 4 * X_DISP10 (insn); | |
1472 | } | |
c906108c | 1473 | } |
386c036b | 1474 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) |
c906108c | 1475 | { |
386c036b MK |
1476 | /* Branch on Floating-Point Condition Codes (FBfcc). */ |
1477 | branch_p = 1; | |
1478 | offset = 4 * X_DISP22 (insn); | |
c906108c | 1479 | } |
386c036b MK |
1480 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) |
1481 | { | |
1482 | /* Branch on Floating-Point Condition Codes with Prediction | |
1483 | (FBPfcc). */ | |
1484 | branch_p = 1; | |
1485 | offset = 4 * X_DISP19 (insn); | |
1486 | } | |
1487 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) | |
1488 | { | |
1489 | /* Branch on Integer Condition Codes (Bicc). */ | |
1490 | branch_p = 1; | |
1491 | offset = 4 * X_DISP22 (insn); | |
1492 | } | |
1493 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) | |
c906108c | 1494 | { |
386c036b MK |
1495 | /* Branch on Integer Condition Codes with Prediction (BPcc). */ |
1496 | branch_p = 1; | |
1497 | offset = 4 * X_DISP19 (insn); | |
c906108c | 1498 | } |
c893be75 MK |
1499 | else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a) |
1500 | { | |
1501 | /* Trap instruction (TRAP). */ | |
0b1b3e42 | 1502 | return gdbarch_tdep (get_frame_arch (frame))->step_trap (frame, insn); |
c893be75 | 1503 | } |
386c036b MK |
1504 | |
1505 | /* FIXME: Handle DONE and RETRY instructions. */ | |
1506 | ||
386c036b | 1507 | if (branch_p) |
c906108c | 1508 | { |
8d1b3521 DM |
1509 | if (fused_p) |
1510 | { | |
1511 | /* Fused compare-and-branch instructions are non-delayed, | |
1512 | and do not have an annuling capability. So we need to | |
1513 | always set a breakpoint on both the NPC and the branch | |
1514 | target address. */ | |
1515 | gdb_assert (offset != 0); | |
1516 | return pc + offset; | |
1517 | } | |
1518 | else if (conditional_p) | |
c906108c | 1519 | { |
386c036b MK |
1520 | /* For conditional branches, return nPC + 4 iff the annul |
1521 | bit is 1. */ | |
1522 | return (X_A (insn) ? *npc + 4 : 0); | |
c906108c SS |
1523 | } |
1524 | else | |
1525 | { | |
386c036b MK |
1526 | /* For unconditional branches, return the target if its |
1527 | specified condition is "always" and return nPC + 4 if the | |
1528 | condition is "never". If the annul bit is 1, set *NPC to | |
1529 | zero. */ | |
1530 | if (X_COND (insn) == 0x0) | |
1531 | pc = *npc, offset = 4; | |
1532 | if (X_A (insn)) | |
1533 | *npc = 0; | |
1534 | ||
1535 | gdb_assert (offset != 0); | |
1536 | return pc + offset; | |
c906108c SS |
1537 | } |
1538 | } | |
386c036b MK |
1539 | |
1540 | return 0; | |
c906108c SS |
1541 | } |
1542 | ||
c893be75 | 1543 | static CORE_ADDR |
0b1b3e42 | 1544 | sparc_step_trap (struct frame_info *frame, unsigned long insn) |
c893be75 MK |
1545 | { |
1546 | return 0; | |
1547 | } | |
1548 | ||
e6590a1b | 1549 | int |
0b1b3e42 | 1550 | sparc_software_single_step (struct frame_info *frame) |
386c036b | 1551 | { |
0b1b3e42 | 1552 | struct gdbarch *arch = get_frame_arch (frame); |
c893be75 | 1553 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
6c95b8df | 1554 | struct address_space *aspace = get_frame_address_space (frame); |
8181d85f | 1555 | CORE_ADDR npc, nnpc; |
c906108c | 1556 | |
e0cd558a | 1557 | CORE_ADDR pc, orig_npc; |
c906108c | 1558 | |
0b1b3e42 UW |
1559 | pc = get_frame_register_unsigned (frame, tdep->pc_regnum); |
1560 | orig_npc = npc = get_frame_register_unsigned (frame, tdep->npc_regnum); | |
c906108c | 1561 | |
e0cd558a | 1562 | /* Analyze the instruction at PC. */ |
0b1b3e42 | 1563 | nnpc = sparc_analyze_control_transfer (frame, pc, &npc); |
e0cd558a | 1564 | if (npc != 0) |
6c95b8df | 1565 | insert_single_step_breakpoint (arch, aspace, npc); |
8181d85f | 1566 | |
e0cd558a | 1567 | if (nnpc != 0) |
6c95b8df | 1568 | insert_single_step_breakpoint (arch, aspace, nnpc); |
c906108c | 1569 | |
e0cd558a UW |
1570 | /* Assert that we have set at least one breakpoint, and that |
1571 | they're not set at the same spot - unless we're going | |
1572 | from here straight to NULL, i.e. a call or jump to 0. */ | |
1573 | gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0); | |
1574 | gdb_assert (nnpc != npc || orig_npc == 0); | |
e6590a1b UW |
1575 | |
1576 | return 1; | |
386c036b MK |
1577 | } |
1578 | ||
1579 | static void | |
61a1198a | 1580 | sparc_write_pc (struct regcache *regcache, CORE_ADDR pc) |
386c036b | 1581 | { |
61a1198a | 1582 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
386c036b | 1583 | |
61a1198a UW |
1584 | regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc); |
1585 | regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4); | |
386c036b MK |
1586 | } |
1587 | \f | |
5af923b0 | 1588 | |
a54124c5 MK |
1589 | /* Return the appropriate register set for the core section identified |
1590 | by SECT_NAME and SECT_SIZE. */ | |
1591 | ||
63807e1d | 1592 | static const struct regset * |
a54124c5 MK |
1593 | sparc_regset_from_core_section (struct gdbarch *gdbarch, |
1594 | const char *sect_name, size_t sect_size) | |
1595 | { | |
1596 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1597 | ||
c558d81a | 1598 | if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset) |
a54124c5 MK |
1599 | return tdep->gregset; |
1600 | ||
c558d81a | 1601 | if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset) |
a54124c5 MK |
1602 | return tdep->fpregset; |
1603 | ||
1604 | return NULL; | |
1605 | } | |
1606 | \f | |
1607 | ||
386c036b MK |
1608 | static struct gdbarch * |
1609 | sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1610 | { | |
1611 | struct gdbarch_tdep *tdep; | |
1612 | struct gdbarch *gdbarch; | |
c906108c | 1613 | |
386c036b MK |
1614 | /* If there is already a candidate, use it. */ |
1615 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1616 | if (arches != NULL) | |
1617 | return arches->gdbarch; | |
c906108c | 1618 | |
386c036b | 1619 | /* Allocate space for the new architecture. */ |
1390fcc2 | 1620 | tdep = XZALLOC (struct gdbarch_tdep); |
386c036b | 1621 | gdbarch = gdbarch_alloc (&info, tdep); |
5af923b0 | 1622 | |
386c036b MK |
1623 | tdep->pc_regnum = SPARC32_PC_REGNUM; |
1624 | tdep->npc_regnum = SPARC32_NPC_REGNUM; | |
c893be75 | 1625 | tdep->step_trap = sparc_step_trap; |
386c036b MK |
1626 | |
1627 | set_gdbarch_long_double_bit (gdbarch, 128); | |
8da61cc4 | 1628 | set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad); |
386c036b MK |
1629 | |
1630 | set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); | |
1631 | set_gdbarch_register_name (gdbarch, sparc32_register_name); | |
1632 | set_gdbarch_register_type (gdbarch, sparc32_register_type); | |
1633 | set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); | |
1634 | set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); | |
1635 | set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); | |
1636 | ||
1637 | /* Register numbers of various important registers. */ | |
1638 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ | |
1639 | set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ | |
1640 | set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ | |
1641 | ||
1642 | /* Call dummy code. */ | |
49a45ecf | 1643 | set_gdbarch_frame_align (gdbarch, sparc32_frame_align); |
386c036b MK |
1644 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
1645 | set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); | |
1646 | set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); | |
1647 | ||
b9d4c5ed | 1648 | set_gdbarch_return_value (gdbarch, sparc32_return_value); |
386c036b MK |
1649 | set_gdbarch_stabs_argument_has_addr |
1650 | (gdbarch, sparc32_stabs_argument_has_addr); | |
1651 | ||
1652 | set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); | |
1653 | ||
1654 | /* Stack grows downward. */ | |
1655 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
c906108c | 1656 | |
386c036b | 1657 | set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc); |
c906108c | 1658 | |
386c036b | 1659 | set_gdbarch_frame_args_skip (gdbarch, 8); |
5af923b0 | 1660 | |
386c036b | 1661 | set_gdbarch_print_insn (gdbarch, print_insn_sparc); |
c906108c | 1662 | |
386c036b MK |
1663 | set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); |
1664 | set_gdbarch_write_pc (gdbarch, sparc_write_pc); | |
c906108c | 1665 | |
236369e7 | 1666 | set_gdbarch_dummy_id (gdbarch, sparc_dummy_id); |
c906108c | 1667 | |
386c036b | 1668 | set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc); |
c906108c | 1669 | |
386c036b MK |
1670 | frame_base_set_default (gdbarch, &sparc32_frame_base); |
1671 | ||
f5a9b87d DM |
1672 | /* Hook in the DWARF CFI frame unwinder. */ |
1673 | dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg); | |
1674 | /* FIXME: kettenis/20050423: Don't enable the unwinder until the | |
1675 | StackGhost issues have been resolved. */ | |
1676 | ||
b2a0b9b2 DM |
1677 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1678 | gdbarch_init_osabi (info, gdbarch); | |
1679 | ||
236369e7 | 1680 | frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind); |
c906108c | 1681 | |
a54124c5 | 1682 | /* If we have register sets, enable the generic core file support. */ |
4c72d57a | 1683 | if (tdep->gregset) |
a54124c5 MK |
1684 | set_gdbarch_regset_from_core_section (gdbarch, |
1685 | sparc_regset_from_core_section); | |
1686 | ||
7e35103a JB |
1687 | register_sparc_ravenscar_ops (gdbarch); |
1688 | ||
386c036b MK |
1689 | return gdbarch; |
1690 | } | |
1691 | \f | |
1692 | /* Helper functions for dealing with register windows. */ | |
1693 | ||
1694 | void | |
1695 | sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) | |
c906108c | 1696 | { |
e17a4113 UW |
1697 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1698 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
386c036b | 1699 | int offset = 0; |
e1613aba | 1700 | gdb_byte buf[8]; |
386c036b MK |
1701 | int i; |
1702 | ||
1703 | if (sp & 1) | |
1704 | { | |
1705 | /* Registers are 64-bit. */ | |
1706 | sp += BIAS; | |
c906108c | 1707 | |
386c036b MK |
1708 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1709 | { | |
1710 | if (regnum == i || regnum == -1) | |
1711 | { | |
1712 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); | |
f700a364 MK |
1713 | |
1714 | /* Handle StackGhost. */ | |
1715 | if (i == SPARC_I7_REGNUM) | |
1716 | { | |
e17a4113 UW |
1717 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1718 | ULONGEST i7; | |
f700a364 | 1719 | |
e17a4113 UW |
1720 | i7 = extract_unsigned_integer (buf + offset, 8, byte_order); |
1721 | store_unsigned_integer (buf + offset, 8, byte_order, | |
1722 | i7 ^ wcookie); | |
f700a364 MK |
1723 | } |
1724 | ||
386c036b MK |
1725 | regcache_raw_supply (regcache, i, buf); |
1726 | } | |
1727 | } | |
1728 | } | |
1729 | else | |
c906108c | 1730 | { |
386c036b MK |
1731 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1732 | pointer. */ | |
1733 | sp &= 0xffffffffUL; | |
c906108c | 1734 | |
386c036b MK |
1735 | /* Clear out the top half of the temporary buffer, and put the |
1736 | register value in the bottom half if we're in 64-bit mode. */ | |
e6d4f032 | 1737 | if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) |
c906108c | 1738 | { |
386c036b MK |
1739 | memset (buf, 0, 4); |
1740 | offset = 4; | |
1741 | } | |
c906108c | 1742 | |
386c036b MK |
1743 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1744 | { | |
1745 | if (regnum == i || regnum == -1) | |
1746 | { | |
1747 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), | |
1748 | buf + offset, 4); | |
42cdca6c MK |
1749 | |
1750 | /* Handle StackGhost. */ | |
1751 | if (i == SPARC_I7_REGNUM) | |
1752 | { | |
e17a4113 UW |
1753 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1754 | ULONGEST i7; | |
42cdca6c | 1755 | |
e17a4113 UW |
1756 | i7 = extract_unsigned_integer (buf + offset, 4, byte_order); |
1757 | store_unsigned_integer (buf + offset, 4, byte_order, | |
1758 | i7 ^ wcookie); | |
42cdca6c MK |
1759 | } |
1760 | ||
386c036b MK |
1761 | regcache_raw_supply (regcache, i, buf); |
1762 | } | |
c906108c SS |
1763 | } |
1764 | } | |
c906108c | 1765 | } |
c906108c SS |
1766 | |
1767 | void | |
386c036b MK |
1768 | sparc_collect_rwindow (const struct regcache *regcache, |
1769 | CORE_ADDR sp, int regnum) | |
c906108c | 1770 | { |
e17a4113 UW |
1771 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1772 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
386c036b | 1773 | int offset = 0; |
e1613aba | 1774 | gdb_byte buf[8]; |
386c036b | 1775 | int i; |
5af923b0 | 1776 | |
386c036b | 1777 | if (sp & 1) |
5af923b0 | 1778 | { |
386c036b MK |
1779 | /* Registers are 64-bit. */ |
1780 | sp += BIAS; | |
c906108c | 1781 | |
386c036b MK |
1782 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1783 | { | |
1784 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1785 | { | |
1786 | regcache_raw_collect (regcache, i, buf); | |
f700a364 MK |
1787 | |
1788 | /* Handle StackGhost. */ | |
1789 | if (i == SPARC_I7_REGNUM) | |
1790 | { | |
e17a4113 UW |
1791 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1792 | ULONGEST i7; | |
f700a364 | 1793 | |
e17a4113 UW |
1794 | i7 = extract_unsigned_integer (buf + offset, 8, byte_order); |
1795 | store_unsigned_integer (buf, 8, byte_order, i7 ^ wcookie); | |
f700a364 MK |
1796 | } |
1797 | ||
386c036b MK |
1798 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); |
1799 | } | |
1800 | } | |
5af923b0 MS |
1801 | } |
1802 | else | |
1803 | { | |
386c036b MK |
1804 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1805 | pointer. */ | |
1806 | sp &= 0xffffffffUL; | |
1807 | ||
1808 | /* Only use the bottom half if we're in 64-bit mode. */ | |
e6d4f032 | 1809 | if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) |
386c036b MK |
1810 | offset = 4; |
1811 | ||
1812 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1813 | { | |
1814 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1815 | { | |
1816 | regcache_raw_collect (regcache, i, buf); | |
42cdca6c MK |
1817 | |
1818 | /* Handle StackGhost. */ | |
1819 | if (i == SPARC_I7_REGNUM) | |
1820 | { | |
e17a4113 UW |
1821 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1822 | ULONGEST i7; | |
42cdca6c | 1823 | |
e17a4113 UW |
1824 | i7 = extract_unsigned_integer (buf + offset, 4, byte_order); |
1825 | store_unsigned_integer (buf + offset, 4, byte_order, | |
1826 | i7 ^ wcookie); | |
42cdca6c MK |
1827 | } |
1828 | ||
386c036b MK |
1829 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), |
1830 | buf + offset, 4); | |
1831 | } | |
1832 | } | |
5af923b0 | 1833 | } |
c906108c SS |
1834 | } |
1835 | ||
386c036b MK |
1836 | /* Helper functions for dealing with register sets. */ |
1837 | ||
c906108c | 1838 | void |
386c036b MK |
1839 | sparc32_supply_gregset (const struct sparc_gregset *gregset, |
1840 | struct regcache *regcache, | |
1841 | int regnum, const void *gregs) | |
c906108c | 1842 | { |
e1613aba | 1843 | const gdb_byte *regs = gregs; |
22e74ef9 | 1844 | gdb_byte zero[4] = { 0 }; |
386c036b | 1845 | int i; |
5af923b0 | 1846 | |
386c036b MK |
1847 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1848 | regcache_raw_supply (regcache, SPARC32_PSR_REGNUM, | |
1849 | regs + gregset->r_psr_offset); | |
c906108c | 1850 | |
386c036b MK |
1851 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1852 | regcache_raw_supply (regcache, SPARC32_PC_REGNUM, | |
1853 | regs + gregset->r_pc_offset); | |
5af923b0 | 1854 | |
386c036b MK |
1855 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) |
1856 | regcache_raw_supply (regcache, SPARC32_NPC_REGNUM, | |
1857 | regs + gregset->r_npc_offset); | |
5af923b0 | 1858 | |
386c036b MK |
1859 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1860 | regcache_raw_supply (regcache, SPARC32_Y_REGNUM, | |
1861 | regs + gregset->r_y_offset); | |
5af923b0 | 1862 | |
386c036b | 1863 | if (regnum == SPARC_G0_REGNUM || regnum == -1) |
22e74ef9 | 1864 | regcache_raw_supply (regcache, SPARC_G0_REGNUM, &zero); |
5af923b0 | 1865 | |
386c036b | 1866 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) |
c906108c | 1867 | { |
386c036b MK |
1868 | int offset = gregset->r_g1_offset; |
1869 | ||
1870 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1871 | { | |
1872 | if (regnum == i || regnum == -1) | |
1873 | regcache_raw_supply (regcache, i, regs + offset); | |
1874 | offset += 4; | |
1875 | } | |
c906108c | 1876 | } |
386c036b MK |
1877 | |
1878 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
c906108c | 1879 | { |
386c036b MK |
1880 | /* Not all of the register set variants include Locals and |
1881 | Inputs. For those that don't, we read them off the stack. */ | |
1882 | if (gregset->r_l0_offset == -1) | |
1883 | { | |
1884 | ULONGEST sp; | |
1885 | ||
1886 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1887 | sparc_supply_rwindow (regcache, sp, regnum); | |
1888 | } | |
1889 | else | |
1890 | { | |
1891 | int offset = gregset->r_l0_offset; | |
1892 | ||
1893 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1894 | { | |
1895 | if (regnum == i || regnum == -1) | |
1896 | regcache_raw_supply (regcache, i, regs + offset); | |
1897 | offset += 4; | |
1898 | } | |
1899 | } | |
c906108c SS |
1900 | } |
1901 | } | |
1902 | ||
c5aa993b | 1903 | void |
386c036b MK |
1904 | sparc32_collect_gregset (const struct sparc_gregset *gregset, |
1905 | const struct regcache *regcache, | |
1906 | int regnum, void *gregs) | |
c906108c | 1907 | { |
e1613aba | 1908 | gdb_byte *regs = gregs; |
386c036b | 1909 | int i; |
c5aa993b | 1910 | |
386c036b MK |
1911 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1912 | regcache_raw_collect (regcache, SPARC32_PSR_REGNUM, | |
1913 | regs + gregset->r_psr_offset); | |
60054393 | 1914 | |
386c036b MK |
1915 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1916 | regcache_raw_collect (regcache, SPARC32_PC_REGNUM, | |
1917 | regs + gregset->r_pc_offset); | |
1918 | ||
1919 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) | |
1920 | regcache_raw_collect (regcache, SPARC32_NPC_REGNUM, | |
1921 | regs + gregset->r_npc_offset); | |
5af923b0 | 1922 | |
386c036b MK |
1923 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1924 | regcache_raw_collect (regcache, SPARC32_Y_REGNUM, | |
1925 | regs + gregset->r_y_offset); | |
1926 | ||
1927 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) | |
5af923b0 | 1928 | { |
386c036b MK |
1929 | int offset = gregset->r_g1_offset; |
1930 | ||
1931 | /* %g0 is always zero. */ | |
1932 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1933 | { | |
1934 | if (regnum == i || regnum == -1) | |
1935 | regcache_raw_collect (regcache, i, regs + offset); | |
1936 | offset += 4; | |
1937 | } | |
5af923b0 | 1938 | } |
386c036b MK |
1939 | |
1940 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
5af923b0 | 1941 | { |
386c036b MK |
1942 | /* Not all of the register set variants include Locals and |
1943 | Inputs. For those that don't, we read them off the stack. */ | |
1944 | if (gregset->r_l0_offset != -1) | |
1945 | { | |
1946 | int offset = gregset->r_l0_offset; | |
1947 | ||
1948 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1949 | { | |
1950 | if (regnum == i || regnum == -1) | |
1951 | regcache_raw_collect (regcache, i, regs + offset); | |
1952 | offset += 4; | |
1953 | } | |
1954 | } | |
5af923b0 | 1955 | } |
c906108c SS |
1956 | } |
1957 | ||
c906108c | 1958 | void |
db75c717 DM |
1959 | sparc32_supply_fpregset (const struct sparc_fpregset *fpregset, |
1960 | struct regcache *regcache, | |
386c036b | 1961 | int regnum, const void *fpregs) |
c906108c | 1962 | { |
e1613aba | 1963 | const gdb_byte *regs = fpregs; |
386c036b | 1964 | int i; |
60054393 | 1965 | |
386c036b | 1966 | for (i = 0; i < 32; i++) |
c906108c | 1967 | { |
386c036b | 1968 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) |
db75c717 DM |
1969 | regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, |
1970 | regs + fpregset->r_f0_offset + (i * 4)); | |
c906108c | 1971 | } |
5af923b0 | 1972 | |
386c036b | 1973 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
db75c717 DM |
1974 | regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, |
1975 | regs + fpregset->r_fsr_offset); | |
c906108c SS |
1976 | } |
1977 | ||
386c036b | 1978 | void |
db75c717 DM |
1979 | sparc32_collect_fpregset (const struct sparc_fpregset *fpregset, |
1980 | const struct regcache *regcache, | |
386c036b | 1981 | int regnum, void *fpregs) |
c906108c | 1982 | { |
e1613aba | 1983 | gdb_byte *regs = fpregs; |
386c036b | 1984 | int i; |
c906108c | 1985 | |
386c036b MK |
1986 | for (i = 0; i < 32; i++) |
1987 | { | |
1988 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) | |
db75c717 DM |
1989 | regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, |
1990 | regs + fpregset->r_f0_offset + (i * 4)); | |
386c036b | 1991 | } |
c906108c | 1992 | |
386c036b | 1993 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
db75c717 DM |
1994 | regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, |
1995 | regs + fpregset->r_fsr_offset); | |
c906108c | 1996 | } |
c906108c | 1997 | \f |
c906108c | 1998 | |
386c036b | 1999 | /* SunOS 4. */ |
c906108c | 2000 | |
386c036b MK |
2001 | /* From <machine/reg.h>. */ |
2002 | const struct sparc_gregset sparc32_sunos4_gregset = | |
c906108c | 2003 | { |
386c036b MK |
2004 | 0 * 4, /* %psr */ |
2005 | 1 * 4, /* %pc */ | |
2006 | 2 * 4, /* %npc */ | |
2007 | 3 * 4, /* %y */ | |
2008 | -1, /* %wim */ | |
2009 | -1, /* %tbr */ | |
2010 | 4 * 4, /* %g1 */ | |
2011 | -1 /* %l0 */ | |
2012 | }; | |
db75c717 DM |
2013 | |
2014 | const struct sparc_fpregset sparc32_sunos4_fpregset = | |
2015 | { | |
2016 | 0 * 4, /* %f0 */ | |
2017 | 33 * 4, /* %fsr */ | |
2018 | }; | |
2019 | ||
2020 | const struct sparc_fpregset sparc32_bsd_fpregset = | |
2021 | { | |
2022 | 0 * 4, /* %f0 */ | |
2023 | 32 * 4, /* %fsr */ | |
2024 | }; | |
386c036b | 2025 | \f |
c906108c | 2026 | |
386c036b MK |
2027 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
2028 | void _initialize_sparc_tdep (void); | |
c906108c SS |
2029 | |
2030 | void | |
386c036b | 2031 | _initialize_sparc_tdep (void) |
c906108c | 2032 | { |
386c036b | 2033 | register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init); |
ef3cf062 | 2034 | } |