Commit | Line | Data |
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386c036b | 1 | /* Target-dependent code for SPARC. |
cda5a58a | 2 | |
386c036b | 3 | Copyright 2003, 2004 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c | 21 | |
c906108c | 22 | #include "defs.h" |
5af923b0 | 23 | #include "arch-utils.h" |
386c036b MK |
24 | #include "dis-asm.h" |
25 | #include "floatformat.h" | |
c906108c | 26 | #include "frame.h" |
386c036b MK |
27 | #include "frame-base.h" |
28 | #include "frame-unwind.h" | |
29 | #include "gdbcore.h" | |
30 | #include "gdbtypes.h" | |
c906108c | 31 | #include "inferior.h" |
386c036b MK |
32 | #include "symtab.h" |
33 | #include "objfiles.h" | |
34 | #include "osabi.h" | |
35 | #include "regcache.h" | |
c906108c SS |
36 | #include "target.h" |
37 | #include "value.h" | |
c906108c | 38 | |
43bd9a9e | 39 | #include "gdb_assert.h" |
386c036b | 40 | #include "gdb_string.h" |
c906108c | 41 | |
386c036b | 42 | #include "sparc-tdep.h" |
c906108c | 43 | |
a54124c5 MK |
44 | struct regset; |
45 | ||
386c036b MK |
46 | /* This file implements the The SPARC 32-bit ABI as defined by the |
47 | section "Low-Level System Information" of the SPARC Compliance | |
48 | Definition (SCD) 2.4.1, which is the 32-bit System V psABI for | |
49 | SPARC. The SCD lists changes with respect to the origional 32-bit | |
50 | psABI as defined in the "System V ABI, SPARC Processor | |
51 | Supplement". | |
52 | ||
53 | Note that if we talk about SunOS, we mean SunOS 4.x, which was | |
54 | BSD-based, which is sometimes (retroactively?) referred to as | |
55 | Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and | |
56 | above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 | |
57 | suffering from severe version number inflation). Solaris 2.x is | |
58 | also known as SunOS 5.x, since that's what uname(1) says. Solaris | |
59 | 2.x is SVR4-based. */ | |
60 | ||
61 | /* Please use the sparc32_-prefix for 32-bit specific code, the | |
62 | sparc64_-prefix for 64-bit specific code and the sparc_-prefix for | |
63 | code that can handle both. The 64-bit specific code lives in | |
64 | sparc64-tdep.c; don't add any here. */ | |
65 | ||
66 | /* The SPARC Floating-Point Quad-Precision format is similar to | |
67 | big-endian IA-64 Quad-recision format. */ | |
68 | #define floatformat_sparc_quad floatformat_ia64_quad_big | |
69 | ||
70 | /* The stack pointer is offset from the stack frame by a BIAS of 2047 | |
71 | (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC | |
72 | hosts, so undefine it first. */ | |
73 | #undef BIAS | |
74 | #define BIAS 2047 | |
75 | ||
76 | /* Macros to extract fields from SPARC instructions. */ | |
c906108c SS |
77 | #define X_OP(i) (((i) >> 30) & 0x3) |
78 | #define X_RD(i) (((i) >> 25) & 0x1f) | |
79 | #define X_A(i) (((i) >> 29) & 1) | |
80 | #define X_COND(i) (((i) >> 25) & 0xf) | |
81 | #define X_OP2(i) (((i) >> 22) & 0x7) | |
82 | #define X_IMM22(i) ((i) & 0x3fffff) | |
83 | #define X_OP3(i) (((i) >> 19) & 0x3f) | |
c906108c | 84 | #define X_I(i) (((i) >> 13) & 1) |
c906108c | 85 | /* Sign extension macros. */ |
c906108c | 86 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) |
c906108c | 87 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) |
c906108c | 88 | |
386c036b MK |
89 | /* Fetch the instruction at PC. Instructions are always big-endian |
90 | even if the processor operates in little-endian mode. */ | |
91 | ||
92 | unsigned long | |
93 | sparc_fetch_instruction (CORE_ADDR pc) | |
c906108c | 94 | { |
386c036b MK |
95 | unsigned char buf[4]; |
96 | unsigned long insn; | |
97 | int i; | |
98 | ||
690668cc MK |
99 | /* If we can't read the instruction at PC, return zero. */ |
100 | if (target_read_memory (pc, buf, sizeof (buf))) | |
101 | return 0; | |
c906108c | 102 | |
386c036b MK |
103 | insn = 0; |
104 | for (i = 0; i < sizeof (buf); i++) | |
105 | insn = (insn << 8) | buf[i]; | |
106 | return insn; | |
107 | } | |
42cdca6c MK |
108 | \f |
109 | ||
110 | /* OpenBSD/sparc includes StackGhost, which according to the author's | |
111 | website http://stackghost.cerias.purdue.edu "... transparently and | |
112 | automatically protects applications' stack frames; more | |
113 | specifically, it guards the return pointers. The protection | |
114 | mechanisms require no application source or binary modification and | |
115 | imposes only a negligible performance penalty." | |
116 | ||
117 | The same website provides the following description of how | |
118 | StackGhost works: | |
119 | ||
120 | "StackGhost interfaces with the kernel trap handler that would | |
121 | normally write out registers to the stack and the handler that | |
122 | would read them back in. By XORing a cookie into the | |
123 | return-address saved in the user stack when it is actually written | |
124 | to the stack, and then XOR it out when the return-address is pulled | |
125 | from the stack, StackGhost can cause attacker corrupted return | |
126 | pointers to behave in a manner the attacker cannot predict. | |
127 | StackGhost can also use several unused bits in the return pointer | |
128 | to detect a smashed return pointer and abort the process." | |
129 | ||
130 | For GDB this means that whenever we're reading %i7 from a stack | |
131 | frame's window save area, we'll have to XOR the cookie. | |
132 | ||
133 | More information on StackGuard can be found on in: | |
134 | ||
135 | Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated | |
136 | Stack Protection." 2001. Published in USENIX Security Symposium | |
137 | '01. */ | |
138 | ||
139 | /* Fetch StackGhost Per-Process XOR cookie. */ | |
140 | ||
141 | ULONGEST | |
142 | sparc_fetch_wcookie (void) | |
143 | { | |
baf92889 MK |
144 | struct target_ops *ops = ¤t_target; |
145 | char buf[8]; | |
146 | int len; | |
147 | ||
148 | len = target_read_partial (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8); | |
149 | if (len == -1) | |
150 | return 0; | |
42cdca6c | 151 | |
baf92889 MK |
152 | /* We should have either an 32-bit or an 64-bit cookie. */ |
153 | gdb_assert (len == 4 || len == 8); | |
154 | ||
155 | return extract_unsigned_integer (buf, len); | |
156 | } | |
386c036b | 157 | \f |
baf92889 | 158 | |
386c036b | 159 | /* Return the contents if register REGNUM as an address. */ |
c906108c | 160 | |
386c036b MK |
161 | static CORE_ADDR |
162 | sparc_address_from_register (int regnum) | |
163 | { | |
164 | ULONGEST addr; | |
c906108c | 165 | |
386c036b MK |
166 | regcache_cooked_read_unsigned (current_regcache, regnum, &addr); |
167 | return addr; | |
168 | } | |
169 | \f | |
c906108c | 170 | |
386c036b MK |
171 | /* The functions on this page are intended to be used to classify |
172 | function arguments. */ | |
c906108c | 173 | |
386c036b | 174 | /* Check whether TYPE is "Integral or Pointer". */ |
c906108c | 175 | |
386c036b MK |
176 | static int |
177 | sparc_integral_or_pointer_p (const struct type *type) | |
c906108c | 178 | { |
386c036b | 179 | switch (TYPE_CODE (type)) |
c906108c | 180 | { |
386c036b MK |
181 | case TYPE_CODE_INT: |
182 | case TYPE_CODE_BOOL: | |
183 | case TYPE_CODE_CHAR: | |
184 | case TYPE_CODE_ENUM: | |
185 | case TYPE_CODE_RANGE: | |
186 | { | |
187 | /* We have byte, half-word, word and extended-word/doubleword | |
188 | integral types. The doubleword is an extension to the | |
189 | origional 32-bit ABI by the SCD 2.4.x. */ | |
190 | int len = TYPE_LENGTH (type); | |
191 | return (len == 1 || len == 2 || len == 4 || len == 8); | |
192 | } | |
193 | return 1; | |
194 | case TYPE_CODE_PTR: | |
195 | case TYPE_CODE_REF: | |
196 | { | |
197 | /* Allow either 32-bit or 64-bit pointers. */ | |
198 | int len = TYPE_LENGTH (type); | |
199 | return (len == 4 || len == 8); | |
200 | } | |
201 | return 1; | |
202 | default: | |
203 | break; | |
204 | } | |
c906108c | 205 | |
386c036b MK |
206 | return 0; |
207 | } | |
c906108c | 208 | |
386c036b | 209 | /* Check whether TYPE is "Floating". */ |
c906108c | 210 | |
386c036b MK |
211 | static int |
212 | sparc_floating_p (const struct type *type) | |
213 | { | |
214 | switch (TYPE_CODE (type)) | |
c906108c | 215 | { |
386c036b MK |
216 | case TYPE_CODE_FLT: |
217 | { | |
218 | int len = TYPE_LENGTH (type); | |
219 | return (len == 4 || len == 8 || len == 16); | |
220 | } | |
221 | default: | |
222 | break; | |
223 | } | |
224 | ||
225 | return 0; | |
226 | } | |
c906108c | 227 | |
386c036b | 228 | /* Check whether TYPE is "Structure or Union". */ |
c906108c | 229 | |
386c036b MK |
230 | static int |
231 | sparc_structure_or_union_p (const struct type *type) | |
232 | { | |
233 | switch (TYPE_CODE (type)) | |
234 | { | |
235 | case TYPE_CODE_STRUCT: | |
236 | case TYPE_CODE_UNION: | |
237 | return 1; | |
238 | default: | |
239 | break; | |
c906108c | 240 | } |
386c036b MK |
241 | |
242 | return 0; | |
c906108c | 243 | } |
386c036b MK |
244 | |
245 | /* Register information. */ | |
246 | ||
247 | static const char *sparc32_register_names[] = | |
5af923b0 | 248 | { |
386c036b MK |
249 | "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
250 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", | |
251 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", | |
252 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", | |
253 | ||
254 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
255 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
256 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
257 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
258 | ||
259 | "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" | |
5af923b0 MS |
260 | }; |
261 | ||
386c036b MK |
262 | /* Total number of registers. */ |
263 | #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) | |
c906108c | 264 | |
386c036b MK |
265 | /* We provide the aliases %d0..%d30 for the floating registers as |
266 | "psuedo" registers. */ | |
267 | ||
268 | static const char *sparc32_pseudo_register_names[] = | |
269 | { | |
270 | "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", | |
271 | "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" | |
272 | }; | |
273 | ||
274 | /* Total number of pseudo registers. */ | |
275 | #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) | |
276 | ||
277 | /* Return the name of register REGNUM. */ | |
278 | ||
279 | static const char * | |
280 | sparc32_register_name (int regnum) | |
281 | { | |
282 | if (regnum >= 0 && regnum < SPARC32_NUM_REGS) | |
283 | return sparc32_register_names[regnum]; | |
284 | ||
285 | if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS) | |
286 | return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS]; | |
287 | ||
288 | return NULL; | |
289 | } | |
290 | ||
291 | /* Return the GDB type object for the "standard" data type of data in | |
292 | register REGNUM. */ | |
293 | ||
294 | static struct type * | |
295 | sparc32_register_type (struct gdbarch *gdbarch, int regnum) | |
296 | { | |
297 | if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) | |
298 | return builtin_type_float; | |
299 | ||
300 | if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) | |
301 | return builtin_type_double; | |
302 | ||
303 | if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) | |
304 | return builtin_type_void_data_ptr; | |
305 | ||
306 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) | |
307 | return builtin_type_void_func_ptr; | |
308 | ||
309 | return builtin_type_int32; | |
310 | } | |
311 | ||
312 | static void | |
313 | sparc32_pseudo_register_read (struct gdbarch *gdbarch, | |
314 | struct regcache *regcache, | |
315 | int regnum, void *buf) | |
316 | { | |
317 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); | |
318 | ||
319 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
320 | regcache_raw_read (regcache, regnum, buf); | |
321 | regcache_raw_read (regcache, regnum + 1, ((char *)buf) + 4); | |
322 | } | |
323 | ||
324 | static void | |
325 | sparc32_pseudo_register_write (struct gdbarch *gdbarch, | |
326 | struct regcache *regcache, | |
327 | int regnum, const void *buf) | |
328 | { | |
329 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); | |
330 | ||
331 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
332 | regcache_raw_write (regcache, regnum, buf); | |
333 | regcache_raw_write (regcache, regnum + 1, ((const char *)buf) + 4); | |
334 | } | |
335 | \f | |
336 | ||
337 | static CORE_ADDR | |
338 | sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
339 | CORE_ADDR funcaddr, int using_gcc, | |
340 | struct value **args, int nargs, | |
341 | struct type *value_type, | |
342 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr) | |
c906108c | 343 | { |
386c036b MK |
344 | *bp_addr = sp - 4; |
345 | *real_pc = funcaddr; | |
346 | ||
347 | if (using_struct_return (value_type, using_gcc)) | |
c906108c | 348 | { |
386c036b MK |
349 | char buf[4]; |
350 | ||
351 | /* This is an UNIMP instruction. */ | |
352 | store_unsigned_integer (buf, 4, TYPE_LENGTH (value_type) & 0x1fff); | |
353 | write_memory (sp - 8, buf, 4); | |
354 | return sp - 8; | |
c906108c SS |
355 | } |
356 | ||
386c036b MK |
357 | return sp - 4; |
358 | } | |
359 | ||
360 | static CORE_ADDR | |
361 | sparc32_store_arguments (struct regcache *regcache, int nargs, | |
362 | struct value **args, CORE_ADDR sp, | |
363 | int struct_return, CORE_ADDR struct_addr) | |
364 | { | |
365 | /* Number of words in the "parameter array". */ | |
366 | int num_elements = 0; | |
367 | int element = 0; | |
368 | int i; | |
369 | ||
370 | for (i = 0; i < nargs; i++) | |
c906108c | 371 | { |
386c036b MK |
372 | struct type *type = VALUE_TYPE (args[i]); |
373 | int len = TYPE_LENGTH (type); | |
374 | ||
375 | if (sparc_structure_or_union_p (type) | |
376 | || (sparc_floating_p (type) && len == 16)) | |
c906108c | 377 | { |
386c036b MK |
378 | /* Structure, Union and Quad-Precision Arguments. */ |
379 | sp -= len; | |
380 | ||
381 | /* Use doubleword alignment for these values. That's always | |
382 | correct, and wasting a few bytes shouldn't be a problem. */ | |
383 | sp &= ~0x7; | |
384 | ||
385 | write_memory (sp, VALUE_CONTENTS (args[i]), len); | |
386 | args[i] = value_from_pointer (lookup_pointer_type (type), sp); | |
387 | num_elements++; | |
388 | } | |
389 | else if (sparc_floating_p (type)) | |
390 | { | |
391 | /* Floating arguments. */ | |
392 | gdb_assert (len == 4 || len == 8); | |
393 | num_elements += (len / 4); | |
c906108c | 394 | } |
c5aa993b JM |
395 | else |
396 | { | |
386c036b MK |
397 | /* Integral and pointer arguments. */ |
398 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
399 | ||
400 | if (len < 4) | |
401 | args[i] = value_cast (builtin_type_int32, args[i]); | |
402 | num_elements += ((len + 3) / 4); | |
c5aa993b | 403 | } |
c906108c | 404 | } |
c906108c | 405 | |
386c036b MK |
406 | /* Always allocate at least six words. */ |
407 | sp -= max (6, num_elements) * 4; | |
c906108c | 408 | |
386c036b MK |
409 | /* The psABI says that "Software convention requires space for the |
410 | struct/union return value pointer, even if the word is unused." */ | |
411 | sp -= 4; | |
c906108c | 412 | |
386c036b MK |
413 | /* The psABI says that "Although software convention and the |
414 | operating system require every stack frame to be doubleword | |
415 | aligned." */ | |
416 | sp &= ~0x7; | |
c906108c | 417 | |
386c036b | 418 | for (i = 0; i < nargs; i++) |
c906108c | 419 | { |
386c036b MK |
420 | char *valbuf = VALUE_CONTENTS (args[i]); |
421 | struct type *type = VALUE_TYPE (args[i]); | |
422 | int len = TYPE_LENGTH (type); | |
c906108c | 423 | |
386c036b | 424 | gdb_assert (len == 4 || len == 8); |
c906108c | 425 | |
386c036b MK |
426 | if (element < 6) |
427 | { | |
428 | int regnum = SPARC_O0_REGNUM + element; | |
c906108c | 429 | |
386c036b MK |
430 | regcache_cooked_write (regcache, regnum, valbuf); |
431 | if (len > 4 && element < 5) | |
432 | regcache_cooked_write (regcache, regnum + 1, valbuf + 4); | |
433 | } | |
5af923b0 | 434 | |
386c036b MK |
435 | /* Always store the argument in memory. */ |
436 | write_memory (sp + 4 + element * 4, valbuf, len); | |
437 | element += len / 4; | |
438 | } | |
c906108c | 439 | |
386c036b | 440 | gdb_assert (element == num_elements); |
c906108c | 441 | |
386c036b | 442 | if (struct_return) |
c906108c | 443 | { |
386c036b | 444 | char buf[4]; |
c906108c | 445 | |
386c036b MK |
446 | store_unsigned_integer (buf, 4, struct_addr); |
447 | write_memory (sp, buf, 4); | |
448 | } | |
c906108c | 449 | |
386c036b | 450 | return sp; |
c906108c SS |
451 | } |
452 | ||
386c036b MK |
453 | static CORE_ADDR |
454 | sparc32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, | |
455 | struct regcache *regcache, CORE_ADDR bp_addr, | |
456 | int nargs, struct value **args, CORE_ADDR sp, | |
457 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 458 | { |
386c036b MK |
459 | CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8)); |
460 | ||
461 | /* Set return address. */ | |
462 | regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); | |
463 | ||
464 | /* Set up function arguments. */ | |
465 | sp = sparc32_store_arguments (regcache, nargs, args, sp, | |
466 | struct_return, struct_addr); | |
467 | ||
468 | /* Allocate the 16-word window save area. */ | |
469 | sp -= 16 * 4; | |
c906108c | 470 | |
386c036b MK |
471 | /* Stack should be doubleword aligned at this point. */ |
472 | gdb_assert (sp % 8 == 0); | |
c906108c | 473 | |
386c036b MK |
474 | /* Finally, update the stack pointer. */ |
475 | regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); | |
476 | ||
477 | return sp; | |
478 | } | |
479 | \f | |
c906108c | 480 | |
386c036b MK |
481 | /* Use the program counter to determine the contents and size of a |
482 | breakpoint instruction. Return a pointer to a string of bytes that | |
483 | encode a breakpoint instruction, store the length of the string in | |
484 | *LEN and optionally adjust *PC to point to the correct memory | |
485 | location for inserting the breakpoint. */ | |
486 | ||
487 | static const unsigned char * | |
488 | sparc_breakpoint_from_pc (CORE_ADDR *pc, int *len) | |
489 | { | |
490 | static unsigned char break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; | |
c5aa993b | 491 | |
386c036b MK |
492 | *len = sizeof (break_insn); |
493 | return break_insn; | |
c906108c | 494 | } |
386c036b | 495 | \f |
c906108c | 496 | |
386c036b | 497 | /* Allocate and initialize a frame cache. */ |
c906108c | 498 | |
386c036b MK |
499 | static struct sparc_frame_cache * |
500 | sparc_alloc_frame_cache (void) | |
501 | { | |
502 | struct sparc_frame_cache *cache; | |
503 | int i; | |
c906108c | 504 | |
386c036b | 505 | cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); |
c906108c | 506 | |
386c036b MK |
507 | /* Base address. */ |
508 | cache->base = 0; | |
509 | cache->pc = 0; | |
c906108c | 510 | |
386c036b MK |
511 | /* Frameless until proven otherwise. */ |
512 | cache->frameless_p = 1; | |
513 | ||
514 | cache->struct_return_p = 0; | |
515 | ||
516 | return cache; | |
517 | } | |
518 | ||
519 | CORE_ADDR | |
520 | sparc_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, | |
521 | struct sparc_frame_cache *cache) | |
c906108c | 522 | { |
386c036b MK |
523 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
524 | unsigned long insn; | |
525 | int offset = 0; | |
c906108c | 526 | int dest = -1; |
c906108c | 527 | |
386c036b MK |
528 | if (current_pc <= pc) |
529 | return current_pc; | |
530 | ||
531 | /* We have to handle to "Procedure Linkage Table" (PLT) special. On | |
532 | SPARC the linker usually defines a symbol (typically | |
533 | _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. | |
534 | This symbol makes us end up here with PC pointing at the start of | |
535 | the PLT and CURRENT_PC probably pointing at a PLT entry. If we | |
536 | would do our normal prologue analysis, we would probably conclude | |
537 | that we've got a frame when in reality we don't, since the | |
538 | dynamic linker patches up the first PLT with some code that | |
539 | starts with a SAVE instruction. Patch up PC such that it points | |
540 | at the start of our PLT entry. */ | |
541 | if (tdep->plt_entry_size > 0 && in_plt_section (current_pc, NULL)) | |
542 | pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); | |
c906108c | 543 | |
386c036b MK |
544 | insn = sparc_fetch_instruction (pc); |
545 | ||
546 | /* Recognize a SETHI insn and record its destination. */ | |
547 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) | |
c906108c SS |
548 | { |
549 | dest = X_RD (insn); | |
386c036b MK |
550 | offset += 4; |
551 | ||
552 | insn = sparc_fetch_instruction (pc + 4); | |
c906108c SS |
553 | } |
554 | ||
386c036b MK |
555 | /* Allow for an arithmetic operation on DEST or %g1. */ |
556 | if (X_OP (insn) == 2 && X_I (insn) | |
c906108c SS |
557 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) |
558 | { | |
386c036b | 559 | offset += 4; |
c906108c | 560 | |
386c036b | 561 | insn = sparc_fetch_instruction (pc + 8); |
c906108c | 562 | } |
c906108c | 563 | |
386c036b MK |
564 | /* Check for the SAVE instruction that sets up the frame. */ |
565 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) | |
c906108c | 566 | { |
386c036b MK |
567 | cache->frameless_p = 0; |
568 | return pc + offset + 4; | |
c906108c SS |
569 | } |
570 | ||
571 | return pc; | |
572 | } | |
573 | ||
386c036b MK |
574 | static CORE_ADDR |
575 | sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
576 | { | |
577 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
578 | return frame_unwind_register_unsigned (next_frame, tdep->pc_regnum); | |
579 | } | |
580 | ||
581 | /* Return PC of first real instruction of the function starting at | |
582 | START_PC. */ | |
f510d44e | 583 | |
386c036b MK |
584 | static CORE_ADDR |
585 | sparc32_skip_prologue (CORE_ADDR start_pc) | |
c906108c | 586 | { |
f510d44e DM |
587 | struct symtab_and_line sal; |
588 | CORE_ADDR func_start, func_end; | |
386c036b | 589 | struct sparc_frame_cache cache; |
f510d44e DM |
590 | |
591 | /* This is the preferred method, find the end of the prologue by | |
592 | using the debugging information. */ | |
593 | if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) | |
594 | { | |
595 | sal = find_pc_line (func_start, 0); | |
596 | ||
597 | if (sal.end < func_end | |
598 | && start_pc <= sal.end) | |
599 | return sal.end; | |
600 | } | |
601 | ||
386c036b | 602 | return sparc_analyze_prologue (start_pc, 0xffffffffUL, &cache); |
c906108c SS |
603 | } |
604 | ||
386c036b | 605 | /* Normal frames. */ |
9319a2fe | 606 | |
386c036b MK |
607 | struct sparc_frame_cache * |
608 | sparc_frame_cache (struct frame_info *next_frame, void **this_cache) | |
9319a2fe | 609 | { |
386c036b | 610 | struct sparc_frame_cache *cache; |
9319a2fe | 611 | |
386c036b MK |
612 | if (*this_cache) |
613 | return *this_cache; | |
c906108c | 614 | |
386c036b MK |
615 | cache = sparc_alloc_frame_cache (); |
616 | *this_cache = cache; | |
c906108c | 617 | |
386c036b MK |
618 | /* In priciple, for normal frames, %fp (%i6) holds the frame |
619 | pointer, which holds the base address for the current stack | |
620 | frame. */ | |
621 | ||
622 | cache->base = frame_unwind_register_unsigned (next_frame, SPARC_FP_REGNUM); | |
623 | if (cache->base == 0) | |
624 | return cache; | |
625 | ||
626 | cache->pc = frame_func_unwind (next_frame); | |
627 | if (cache->pc != 0) | |
c906108c | 628 | { |
386c036b MK |
629 | CORE_ADDR addr_in_block = frame_unwind_address_in_block (next_frame); |
630 | sparc_analyze_prologue (cache->pc, addr_in_block, cache); | |
c906108c | 631 | } |
386c036b MK |
632 | |
633 | if (cache->frameless_p) | |
c906108c | 634 | { |
386c036b MK |
635 | /* We didn't find a valid frame, which means that CACHE->base |
636 | currently holds the frame pointer for our calling frame. */ | |
637 | cache->base = frame_unwind_register_unsigned (next_frame, | |
638 | SPARC_SP_REGNUM); | |
c906108c | 639 | } |
c906108c | 640 | |
386c036b | 641 | return cache; |
c906108c | 642 | } |
c906108c | 643 | |
386c036b MK |
644 | struct sparc_frame_cache * |
645 | sparc32_frame_cache (struct frame_info *next_frame, void **this_cache) | |
c906108c | 646 | { |
386c036b MK |
647 | struct sparc_frame_cache *cache; |
648 | struct symbol *sym; | |
c906108c | 649 | |
386c036b MK |
650 | if (*this_cache) |
651 | return *this_cache; | |
c906108c | 652 | |
386c036b | 653 | cache = sparc_frame_cache (next_frame, this_cache); |
c906108c | 654 | |
386c036b MK |
655 | sym = find_pc_function (cache->pc); |
656 | if (sym) | |
c906108c | 657 | { |
386c036b MK |
658 | struct type *type = check_typedef (SYMBOL_TYPE (sym)); |
659 | enum type_code code = TYPE_CODE (type); | |
660 | ||
661 | if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) | |
662 | { | |
663 | type = check_typedef (TYPE_TARGET_TYPE (type)); | |
664 | if (sparc_structure_or_union_p (type) | |
665 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
666 | cache->struct_return_p = 1; | |
667 | } | |
c906108c SS |
668 | } |
669 | ||
386c036b MK |
670 | return cache; |
671 | } | |
672 | ||
673 | static void | |
674 | sparc32_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
675 | struct frame_id *this_id) | |
676 | { | |
677 | struct sparc_frame_cache *cache = | |
678 | sparc32_frame_cache (next_frame, this_cache); | |
679 | ||
680 | /* This marks the outermost frame. */ | |
681 | if (cache->base == 0) | |
682 | return; | |
683 | ||
684 | (*this_id) = frame_id_build (cache->base, cache->pc); | |
685 | } | |
c906108c | 686 | |
386c036b MK |
687 | static void |
688 | sparc32_frame_prev_register (struct frame_info *next_frame, void **this_cache, | |
689 | int regnum, int *optimizedp, | |
690 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
691 | int *realnump, void *valuep) | |
692 | { | |
693 | struct sparc_frame_cache *cache = | |
694 | sparc32_frame_cache (next_frame, this_cache); | |
c906108c | 695 | |
386c036b | 696 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) |
c906108c | 697 | { |
386c036b MK |
698 | *optimizedp = 0; |
699 | *lvalp = not_lval; | |
700 | *addrp = 0; | |
701 | *realnump = -1; | |
702 | if (valuep) | |
c906108c | 703 | { |
386c036b MK |
704 | CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; |
705 | ||
706 | /* If this functions has a Structure, Union or | |
707 | Quad-Precision return value, we have to skip the UNIMP | |
708 | instruction that encodes the size of the structure. */ | |
709 | if (cache->struct_return_p) | |
710 | pc += 4; | |
711 | ||
712 | regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM; | |
713 | pc += frame_unwind_register_unsigned (next_frame, regnum) + 8; | |
714 | store_unsigned_integer (valuep, 4, pc); | |
c906108c | 715 | } |
c906108c SS |
716 | return; |
717 | } | |
718 | ||
42cdca6c MK |
719 | /* Handle StackGhost. */ |
720 | { | |
721 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
722 | ||
723 | if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM) | |
724 | { | |
725 | *optimizedp = 0; | |
726 | *lvalp = not_lval; | |
727 | *addrp = 0; | |
728 | *realnump = -1; | |
729 | if (valuep) | |
730 | { | |
731 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; | |
7d34766b | 732 | ULONGEST i7; |
42cdca6c MK |
733 | |
734 | /* Read the value in from memory. */ | |
7d34766b MK |
735 | i7 = get_frame_memory_unsigned (next_frame, addr, 4); |
736 | store_unsigned_integer (valuep, 4, i7 ^ wcookie); | |
42cdca6c MK |
737 | } |
738 | return; | |
739 | } | |
740 | } | |
741 | ||
386c036b MK |
742 | /* The previous frame's `local' and `in' registers have been saved |
743 | in the register save area. */ | |
744 | if (!cache->frameless_p | |
745 | && regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) | |
c906108c | 746 | { |
386c036b MK |
747 | *optimizedp = 0; |
748 | *lvalp = lval_memory; | |
749 | *addrp = cache->base + (regnum - SPARC_L0_REGNUM) * 4; | |
750 | *realnump = -1; | |
751 | if (valuep) | |
c906108c | 752 | { |
386c036b MK |
753 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
754 | ||
755 | /* Read the value in from memory. */ | |
756 | read_memory (*addrp, valuep, register_size (gdbarch, regnum)); | |
c906108c | 757 | } |
386c036b MK |
758 | return; |
759 | } | |
c906108c | 760 | |
386c036b MK |
761 | /* The previous frame's `out' registers are accessable as the |
762 | current frame's `in' registers. */ | |
763 | if (!cache->frameless_p | |
764 | && regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM) | |
765 | regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); | |
5af923b0 | 766 | |
386c036b MK |
767 | frame_register_unwind (next_frame, regnum, |
768 | optimizedp, lvalp, addrp, realnump, valuep); | |
769 | } | |
c906108c | 770 | |
386c036b MK |
771 | static const struct frame_unwind sparc32_frame_unwind = |
772 | { | |
773 | NORMAL_FRAME, | |
774 | sparc32_frame_this_id, | |
775 | sparc32_frame_prev_register | |
776 | }; | |
777 | ||
778 | static const struct frame_unwind * | |
779 | sparc32_frame_sniffer (struct frame_info *next_frame) | |
780 | { | |
781 | return &sparc32_frame_unwind; | |
c906108c | 782 | } |
386c036b | 783 | \f |
c906108c | 784 | |
386c036b MK |
785 | static CORE_ADDR |
786 | sparc32_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
787 | { | |
788 | struct sparc_frame_cache *cache = | |
789 | sparc32_frame_cache (next_frame, this_cache); | |
c906108c | 790 | |
386c036b MK |
791 | return cache->base; |
792 | } | |
c906108c | 793 | |
386c036b MK |
794 | static const struct frame_base sparc32_frame_base = |
795 | { | |
796 | &sparc32_frame_unwind, | |
797 | sparc32_frame_base_address, | |
798 | sparc32_frame_base_address, | |
799 | sparc32_frame_base_address | |
800 | }; | |
c906108c | 801 | |
386c036b MK |
802 | static struct frame_id |
803 | sparc_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
804 | { | |
805 | CORE_ADDR sp; | |
5af923b0 | 806 | |
386c036b MK |
807 | sp = frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM); |
808 | return frame_id_build (sp, frame_pc_unwind (next_frame)); | |
809 | } | |
810 | \f | |
c906108c | 811 | |
386c036b MK |
812 | /* Extract from an array REGBUF containing the (raw) register state, a |
813 | function return value of TYPE, and copy that into VALBUF. */ | |
5af923b0 | 814 | |
386c036b MK |
815 | static void |
816 | sparc32_extract_return_value (struct type *type, struct regcache *regcache, | |
817 | void *valbuf) | |
818 | { | |
819 | int len = TYPE_LENGTH (type); | |
820 | char buf[8]; | |
c906108c | 821 | |
386c036b MK |
822 | gdb_assert (!sparc_structure_or_union_p (type)); |
823 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 824 | |
386c036b | 825 | if (sparc_floating_p (type)) |
5af923b0 | 826 | { |
386c036b MK |
827 | /* Floating return values. */ |
828 | regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf); | |
829 | if (len > 4) | |
830 | regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4); | |
831 | memcpy (valbuf, buf, len); | |
5af923b0 MS |
832 | } |
833 | else | |
834 | { | |
386c036b MK |
835 | /* Integral and pointer return values. */ |
836 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
c906108c | 837 | |
386c036b MK |
838 | regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); |
839 | if (len > 4) | |
840 | { | |
841 | regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4); | |
842 | gdb_assert (len == 8); | |
843 | memcpy (valbuf, buf, 8); | |
844 | } | |
845 | else | |
846 | { | |
847 | /* Just stripping off any unused bytes should preserve the | |
848 | signed-ness just fine. */ | |
849 | memcpy (valbuf, buf + 4 - len, len); | |
850 | } | |
851 | } | |
852 | } | |
c906108c | 853 | |
386c036b MK |
854 | /* Write into the appropriate registers a function return value stored |
855 | in VALBUF of type TYPE. */ | |
c906108c | 856 | |
386c036b MK |
857 | static void |
858 | sparc32_store_return_value (struct type *type, struct regcache *regcache, | |
859 | const void *valbuf) | |
860 | { | |
861 | int len = TYPE_LENGTH (type); | |
862 | char buf[8]; | |
c906108c | 863 | |
386c036b MK |
864 | gdb_assert (!sparc_structure_or_union_p (type)); |
865 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 866 | |
386c036b MK |
867 | if (sparc_floating_p (type)) |
868 | { | |
869 | /* Floating return values. */ | |
870 | memcpy (buf, valbuf, len); | |
871 | regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf); | |
872 | if (len > 4) | |
873 | regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4); | |
874 | } | |
875 | else | |
c906108c | 876 | { |
386c036b MK |
877 | /* Integral and pointer return values. */ |
878 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
879 | ||
880 | if (len > 4) | |
2757dd86 | 881 | { |
386c036b MK |
882 | gdb_assert (len == 8); |
883 | memcpy (buf, valbuf, 8); | |
884 | regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4); | |
2757dd86 AC |
885 | } |
886 | else | |
887 | { | |
386c036b MK |
888 | /* ??? Do we need to do any sign-extension here? */ |
889 | memcpy (buf + 4 - len, valbuf, len); | |
2757dd86 | 890 | } |
386c036b | 891 | regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); |
c906108c SS |
892 | } |
893 | } | |
894 | ||
b9d4c5ed MK |
895 | static enum return_value_convention |
896 | sparc32_return_value (struct gdbarch *gdbarch, struct type *type, | |
897 | struct regcache *regcache, void *readbuf, | |
898 | const void *writebuf) | |
899 | { | |
900 | if (sparc_structure_or_union_p (type) | |
901 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
902 | return RETURN_VALUE_STRUCT_CONVENTION; | |
903 | ||
904 | if (readbuf) | |
905 | sparc32_extract_return_value (type, regcache, readbuf); | |
906 | if (writebuf) | |
907 | sparc32_store_return_value (type, regcache, writebuf); | |
908 | ||
909 | return RETURN_VALUE_REGISTER_CONVENTION; | |
910 | } | |
911 | ||
931aecf5 AC |
912 | #if 0 |
913 | /* NOTE: cagney/2004-01-17: For the moment disable this method. The | |
914 | architecture and CORE-gdb will need new code (and a replacement for | |
74055713 AC |
915 | DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS) before this can be made to |
916 | work robustly. Here is a possible function signature: */ | |
931aecf5 AC |
917 | /* NOTE: cagney/2004-01-17: So far only the 32-bit SPARC ABI has been |
918 | identifed as having a way to robustly recover the address of a | |
919 | struct-convention return-value (after the function has returned). | |
920 | For all other ABIs so far examined, the calling convention makes no | |
921 | guarenteed that the register containing the return-value will be | |
922 | preserved and hence that the return-value's address can be | |
923 | recovered. */ | |
386c036b MK |
924 | /* Extract from REGCACHE, which contains the (raw) register state, the |
925 | address in which a function should return its structure value, as a | |
926 | CORE_ADDR. */ | |
c906108c | 927 | |
386c036b | 928 | static CORE_ADDR |
ca9d58e9 | 929 | sparc32_extract_struct_value_address (struct regcache *regcache) |
386c036b | 930 | { |
9515395e | 931 | ULONGEST sp; |
c906108c | 932 | |
9515395e MK |
933 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); |
934 | return read_memory_unsigned_integer (sp + 64, 4); | |
386c036b | 935 | } |
931aecf5 | 936 | #endif |
c906108c | 937 | |
386c036b MK |
938 | static int |
939 | sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) | |
c906108c | 940 | { |
386c036b MK |
941 | return (sparc_structure_or_union_p (type) |
942 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)); | |
943 | } | |
c906108c | 944 | |
386c036b MK |
945 | \f |
946 | /* The SPARC Architecture doesn't have hardware single-step support, | |
947 | and most operating systems don't implement it either, so we provide | |
948 | software single-step mechanism. */ | |
c906108c | 949 | |
386c036b MK |
950 | static CORE_ADDR |
951 | sparc_analyze_control_transfer (CORE_ADDR pc, CORE_ADDR *npc) | |
952 | { | |
953 | unsigned long insn = sparc_fetch_instruction (pc); | |
954 | int conditional_p = X_COND (insn) & 0x7; | |
955 | int branch_p = 0; | |
956 | long offset = 0; /* Must be signed for sign-extend. */ | |
c906108c | 957 | |
386c036b | 958 | if (X_OP (insn) == 0 && X_OP2 (insn) == 3 && (insn & 0x1000000) == 0) |
c906108c | 959 | { |
386c036b MK |
960 | /* Branch on Integer Register with Prediction (BPr). */ |
961 | branch_p = 1; | |
962 | conditional_p = 1; | |
c906108c | 963 | } |
386c036b | 964 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) |
c906108c | 965 | { |
386c036b MK |
966 | /* Branch on Floating-Point Condition Codes (FBfcc). */ |
967 | branch_p = 1; | |
968 | offset = 4 * X_DISP22 (insn); | |
c906108c | 969 | } |
386c036b MK |
970 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) |
971 | { | |
972 | /* Branch on Floating-Point Condition Codes with Prediction | |
973 | (FBPfcc). */ | |
974 | branch_p = 1; | |
975 | offset = 4 * X_DISP19 (insn); | |
976 | } | |
977 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) | |
978 | { | |
979 | /* Branch on Integer Condition Codes (Bicc). */ | |
980 | branch_p = 1; | |
981 | offset = 4 * X_DISP22 (insn); | |
982 | } | |
983 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) | |
c906108c | 984 | { |
386c036b MK |
985 | /* Branch on Integer Condition Codes with Prediction (BPcc). */ |
986 | branch_p = 1; | |
987 | offset = 4 * X_DISP19 (insn); | |
c906108c | 988 | } |
386c036b MK |
989 | |
990 | /* FIXME: Handle DONE and RETRY instructions. */ | |
991 | ||
992 | /* FIXME: Handle the Trap instruction. */ | |
993 | ||
994 | if (branch_p) | |
c906108c | 995 | { |
386c036b | 996 | if (conditional_p) |
c906108c | 997 | { |
386c036b MK |
998 | /* For conditional branches, return nPC + 4 iff the annul |
999 | bit is 1. */ | |
1000 | return (X_A (insn) ? *npc + 4 : 0); | |
c906108c SS |
1001 | } |
1002 | else | |
1003 | { | |
386c036b MK |
1004 | /* For unconditional branches, return the target if its |
1005 | specified condition is "always" and return nPC + 4 if the | |
1006 | condition is "never". If the annul bit is 1, set *NPC to | |
1007 | zero. */ | |
1008 | if (X_COND (insn) == 0x0) | |
1009 | pc = *npc, offset = 4; | |
1010 | if (X_A (insn)) | |
1011 | *npc = 0; | |
1012 | ||
1013 | gdb_assert (offset != 0); | |
1014 | return pc + offset; | |
c906108c SS |
1015 | } |
1016 | } | |
386c036b MK |
1017 | |
1018 | return 0; | |
c906108c SS |
1019 | } |
1020 | ||
386c036b MK |
1021 | void |
1022 | sparc_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
1023 | { | |
1024 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1025 | static CORE_ADDR npc, nnpc; | |
1026 | static char npc_save[4], nnpc_save[4]; | |
c906108c | 1027 | |
386c036b MK |
1028 | if (insert_breakpoints_p) |
1029 | { | |
1030 | CORE_ADDR pc; | |
c906108c | 1031 | |
386c036b MK |
1032 | pc = sparc_address_from_register (tdep->pc_regnum); |
1033 | npc = sparc_address_from_register (tdep->npc_regnum); | |
c906108c | 1034 | |
386c036b MK |
1035 | /* Analyze the instruction at PC. */ |
1036 | nnpc = sparc_analyze_control_transfer (pc, &npc); | |
1037 | if (npc != 0) | |
1038 | target_insert_breakpoint (npc, npc_save); | |
1039 | if (nnpc != 0) | |
1040 | target_insert_breakpoint (nnpc, nnpc_save); | |
c906108c | 1041 | |
386c036b MK |
1042 | /* Assert that we have set at least one breakpoint, and that |
1043 | they're not set at the same spot. */ | |
1044 | gdb_assert (npc != 0 || nnpc != 0); | |
1045 | gdb_assert (nnpc != npc); | |
60054393 | 1046 | } |
386c036b | 1047 | else |
c906108c | 1048 | { |
386c036b MK |
1049 | if (npc != 0) |
1050 | target_remove_breakpoint (npc, npc_save); | |
1051 | if (nnpc != 0) | |
1052 | target_remove_breakpoint (nnpc, nnpc_save); | |
c906108c | 1053 | } |
386c036b MK |
1054 | } |
1055 | ||
1056 | static void | |
1057 | sparc_write_pc (CORE_ADDR pc, ptid_t ptid) | |
1058 | { | |
1059 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1060 | ||
1061 | write_register_pid (tdep->pc_regnum, pc, ptid); | |
1062 | write_register_pid (tdep->npc_regnum, pc + 4, ptid); | |
1063 | } | |
1064 | \f | |
1065 | /* Unglobalize NAME. */ | |
1066 | ||
1067 | char * | |
1068 | sparc_stabs_unglobalize_name (char *name) | |
1069 | { | |
1070 | /* The Sun compilers (Sun ONE Studio, Forte Developer, Sun WorkShop, | |
1071 | SunPRO) convert file static variables into global values, a | |
1072 | process known as globalization. In order to do this, the | |
1073 | compiler will create a unique prefix and prepend it to each file | |
1074 | static variable. For static variables within a function, this | |
1075 | globalization prefix is followed by the function name (nested | |
1076 | static variables within a function are supposed to generate a | |
1077 | warning message, and are left alone). The procedure is | |
1078 | documented in the Stabs Interface Manual, which is distrubuted | |
1079 | with the compilers, although version 4.0 of the manual seems to | |
1080 | be incorrect in some places, at least for SPARC. The | |
1081 | globalization prefix is encoded into an N_OPT stab, with the form | |
1082 | "G=<prefix>". The globalization prefix always seems to start | |
1083 | with a dollar sign '$'; a dot '.' is used as a seperator. So we | |
1084 | simply strip everything up until the last dot. */ | |
c906108c | 1085 | |
386c036b | 1086 | if (name[0] == '$') |
c906108c | 1087 | { |
386c036b MK |
1088 | char *p = strrchr (name, '.'); |
1089 | if (p) | |
1090 | return p + 1; | |
c906108c | 1091 | } |
c906108c | 1092 | |
386c036b MK |
1093 | return name; |
1094 | } | |
1095 | \f | |
5af923b0 | 1096 | |
a54124c5 MK |
1097 | /* Return the appropriate register set for the core section identified |
1098 | by SECT_NAME and SECT_SIZE. */ | |
1099 | ||
1100 | const struct regset * | |
1101 | sparc_regset_from_core_section (struct gdbarch *gdbarch, | |
1102 | const char *sect_name, size_t sect_size) | |
1103 | { | |
1104 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1105 | ||
c558d81a | 1106 | if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset) |
a54124c5 MK |
1107 | return tdep->gregset; |
1108 | ||
c558d81a | 1109 | if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset) |
a54124c5 MK |
1110 | return tdep->fpregset; |
1111 | ||
1112 | return NULL; | |
1113 | } | |
1114 | \f | |
1115 | ||
386c036b MK |
1116 | static struct gdbarch * |
1117 | sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1118 | { | |
1119 | struct gdbarch_tdep *tdep; | |
1120 | struct gdbarch *gdbarch; | |
c906108c | 1121 | |
386c036b MK |
1122 | /* If there is already a candidate, use it. */ |
1123 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1124 | if (arches != NULL) | |
1125 | return arches->gdbarch; | |
c906108c | 1126 | |
386c036b MK |
1127 | /* Allocate space for the new architecture. */ |
1128 | tdep = XMALLOC (struct gdbarch_tdep); | |
1129 | gdbarch = gdbarch_alloc (&info, tdep); | |
5af923b0 | 1130 | |
386c036b MK |
1131 | tdep->pc_regnum = SPARC32_PC_REGNUM; |
1132 | tdep->npc_regnum = SPARC32_NPC_REGNUM; | |
a54124c5 | 1133 | tdep->gregset = NULL; |
c558d81a | 1134 | tdep->sizeof_gregset = 0; |
a54124c5 | 1135 | tdep->fpregset = NULL; |
c558d81a | 1136 | tdep->sizeof_fpregset = 0; |
386c036b MK |
1137 | tdep->plt_entry_size = 0; |
1138 | ||
1139 | set_gdbarch_long_double_bit (gdbarch, 128); | |
1140 | set_gdbarch_long_double_format (gdbarch, &floatformat_sparc_quad); | |
1141 | ||
1142 | set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); | |
1143 | set_gdbarch_register_name (gdbarch, sparc32_register_name); | |
1144 | set_gdbarch_register_type (gdbarch, sparc32_register_type); | |
1145 | set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); | |
1146 | set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); | |
1147 | set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); | |
1148 | ||
1149 | /* Register numbers of various important registers. */ | |
1150 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ | |
1151 | set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ | |
1152 | set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ | |
1153 | ||
1154 | /* Call dummy code. */ | |
1155 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); | |
1156 | set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); | |
1157 | set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); | |
1158 | ||
b9d4c5ed | 1159 | set_gdbarch_return_value (gdbarch, sparc32_return_value); |
386c036b MK |
1160 | set_gdbarch_stabs_argument_has_addr |
1161 | (gdbarch, sparc32_stabs_argument_has_addr); | |
1162 | ||
1163 | set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); | |
1164 | ||
1165 | /* Stack grows downward. */ | |
1166 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
c906108c | 1167 | |
386c036b | 1168 | set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc); |
c906108c | 1169 | |
386c036b | 1170 | set_gdbarch_frame_args_skip (gdbarch, 8); |
5af923b0 | 1171 | |
386c036b | 1172 | set_gdbarch_print_insn (gdbarch, print_insn_sparc); |
c906108c | 1173 | |
386c036b MK |
1174 | set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); |
1175 | set_gdbarch_write_pc (gdbarch, sparc_write_pc); | |
c906108c | 1176 | |
386c036b | 1177 | set_gdbarch_unwind_dummy_id (gdbarch, sparc_unwind_dummy_id); |
c906108c | 1178 | |
386c036b | 1179 | set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc); |
c906108c | 1180 | |
386c036b MK |
1181 | frame_base_set_default (gdbarch, &sparc32_frame_base); |
1182 | ||
1183 | /* Hook in ABI-specific overrides, if they have been registered. */ | |
1184 | gdbarch_init_osabi (info, gdbarch); | |
c906108c | 1185 | |
386c036b | 1186 | frame_unwind_append_sniffer (gdbarch, sparc32_frame_sniffer); |
c906108c | 1187 | |
a54124c5 | 1188 | /* If we have register sets, enable the generic core file support. */ |
4c72d57a | 1189 | if (tdep->gregset) |
a54124c5 MK |
1190 | set_gdbarch_regset_from_core_section (gdbarch, |
1191 | sparc_regset_from_core_section); | |
1192 | ||
386c036b MK |
1193 | return gdbarch; |
1194 | } | |
1195 | \f | |
1196 | /* Helper functions for dealing with register windows. */ | |
1197 | ||
1198 | void | |
1199 | sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) | |
c906108c | 1200 | { |
386c036b MK |
1201 | int offset = 0; |
1202 | char buf[8]; | |
1203 | int i; | |
1204 | ||
1205 | if (sp & 1) | |
1206 | { | |
1207 | /* Registers are 64-bit. */ | |
1208 | sp += BIAS; | |
c906108c | 1209 | |
386c036b MK |
1210 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1211 | { | |
1212 | if (regnum == i || regnum == -1) | |
1213 | { | |
1214 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); | |
1215 | regcache_raw_supply (regcache, i, buf); | |
1216 | } | |
1217 | } | |
1218 | } | |
1219 | else | |
c906108c | 1220 | { |
386c036b MK |
1221 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1222 | pointer. */ | |
1223 | sp &= 0xffffffffUL; | |
c906108c | 1224 | |
386c036b MK |
1225 | /* Clear out the top half of the temporary buffer, and put the |
1226 | register value in the bottom half if we're in 64-bit mode. */ | |
1227 | if (gdbarch_ptr_bit (current_gdbarch) == 64) | |
c906108c | 1228 | { |
386c036b MK |
1229 | memset (buf, 0, 4); |
1230 | offset = 4; | |
1231 | } | |
c906108c | 1232 | |
386c036b MK |
1233 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1234 | { | |
1235 | if (regnum == i || regnum == -1) | |
1236 | { | |
1237 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), | |
1238 | buf + offset, 4); | |
42cdca6c MK |
1239 | |
1240 | /* Handle StackGhost. */ | |
1241 | if (i == SPARC_I7_REGNUM) | |
1242 | { | |
1243 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
7d34766b | 1244 | ULONGEST i7 = extract_unsigned_integer (buf + offset, 4); |
42cdca6c | 1245 | |
7d34766b | 1246 | store_unsigned_integer (buf + offset, 4, i7 ^ wcookie); |
42cdca6c MK |
1247 | } |
1248 | ||
386c036b MK |
1249 | regcache_raw_supply (regcache, i, buf); |
1250 | } | |
c906108c SS |
1251 | } |
1252 | } | |
c906108c | 1253 | } |
c906108c SS |
1254 | |
1255 | void | |
386c036b MK |
1256 | sparc_collect_rwindow (const struct regcache *regcache, |
1257 | CORE_ADDR sp, int regnum) | |
c906108c | 1258 | { |
386c036b MK |
1259 | int offset = 0; |
1260 | char buf[8]; | |
1261 | int i; | |
5af923b0 | 1262 | |
386c036b | 1263 | if (sp & 1) |
5af923b0 | 1264 | { |
386c036b MK |
1265 | /* Registers are 64-bit. */ |
1266 | sp += BIAS; | |
c906108c | 1267 | |
386c036b MK |
1268 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1269 | { | |
1270 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1271 | { | |
1272 | regcache_raw_collect (regcache, i, buf); | |
1273 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); | |
1274 | } | |
1275 | } | |
5af923b0 MS |
1276 | } |
1277 | else | |
1278 | { | |
386c036b MK |
1279 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1280 | pointer. */ | |
1281 | sp &= 0xffffffffUL; | |
1282 | ||
1283 | /* Only use the bottom half if we're in 64-bit mode. */ | |
1284 | if (gdbarch_ptr_bit (current_gdbarch) == 64) | |
1285 | offset = 4; | |
1286 | ||
1287 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1288 | { | |
1289 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1290 | { | |
1291 | regcache_raw_collect (regcache, i, buf); | |
42cdca6c MK |
1292 | |
1293 | /* Handle StackGhost. */ | |
1294 | if (i == SPARC_I7_REGNUM) | |
1295 | { | |
1296 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
7d34766b | 1297 | ULONGEST i7 = extract_unsigned_integer (buf + offset, 4); |
42cdca6c | 1298 | |
7d34766b | 1299 | store_unsigned_integer (buf + offset, 4, i7 ^ wcookie); |
42cdca6c MK |
1300 | } |
1301 | ||
386c036b MK |
1302 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), |
1303 | buf + offset, 4); | |
1304 | } | |
1305 | } | |
5af923b0 | 1306 | } |
c906108c SS |
1307 | } |
1308 | ||
386c036b MK |
1309 | /* Helper functions for dealing with register sets. */ |
1310 | ||
c906108c | 1311 | void |
386c036b MK |
1312 | sparc32_supply_gregset (const struct sparc_gregset *gregset, |
1313 | struct regcache *regcache, | |
1314 | int regnum, const void *gregs) | |
c906108c | 1315 | { |
386c036b MK |
1316 | const char *regs = gregs; |
1317 | int i; | |
5af923b0 | 1318 | |
386c036b MK |
1319 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1320 | regcache_raw_supply (regcache, SPARC32_PSR_REGNUM, | |
1321 | regs + gregset->r_psr_offset); | |
c906108c | 1322 | |
386c036b MK |
1323 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1324 | regcache_raw_supply (regcache, SPARC32_PC_REGNUM, | |
1325 | regs + gregset->r_pc_offset); | |
5af923b0 | 1326 | |
386c036b MK |
1327 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) |
1328 | regcache_raw_supply (regcache, SPARC32_NPC_REGNUM, | |
1329 | regs + gregset->r_npc_offset); | |
5af923b0 | 1330 | |
386c036b MK |
1331 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1332 | regcache_raw_supply (regcache, SPARC32_Y_REGNUM, | |
1333 | regs + gregset->r_y_offset); | |
5af923b0 | 1334 | |
386c036b MK |
1335 | if (regnum == SPARC_G0_REGNUM || regnum == -1) |
1336 | regcache_raw_supply (regcache, SPARC_G0_REGNUM, NULL); | |
5af923b0 | 1337 | |
386c036b | 1338 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) |
c906108c | 1339 | { |
386c036b MK |
1340 | int offset = gregset->r_g1_offset; |
1341 | ||
1342 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1343 | { | |
1344 | if (regnum == i || regnum == -1) | |
1345 | regcache_raw_supply (regcache, i, regs + offset); | |
1346 | offset += 4; | |
1347 | } | |
c906108c | 1348 | } |
386c036b MK |
1349 | |
1350 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
c906108c | 1351 | { |
386c036b MK |
1352 | /* Not all of the register set variants include Locals and |
1353 | Inputs. For those that don't, we read them off the stack. */ | |
1354 | if (gregset->r_l0_offset == -1) | |
1355 | { | |
1356 | ULONGEST sp; | |
1357 | ||
1358 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1359 | sparc_supply_rwindow (regcache, sp, regnum); | |
1360 | } | |
1361 | else | |
1362 | { | |
1363 | int offset = gregset->r_l0_offset; | |
1364 | ||
1365 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1366 | { | |
1367 | if (regnum == i || regnum == -1) | |
1368 | regcache_raw_supply (regcache, i, regs + offset); | |
1369 | offset += 4; | |
1370 | } | |
1371 | } | |
c906108c SS |
1372 | } |
1373 | } | |
1374 | ||
c5aa993b | 1375 | void |
386c036b MK |
1376 | sparc32_collect_gregset (const struct sparc_gregset *gregset, |
1377 | const struct regcache *regcache, | |
1378 | int regnum, void *gregs) | |
c906108c | 1379 | { |
386c036b MK |
1380 | char *regs = gregs; |
1381 | int i; | |
c5aa993b | 1382 | |
386c036b MK |
1383 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1384 | regcache_raw_collect (regcache, SPARC32_PSR_REGNUM, | |
1385 | regs + gregset->r_psr_offset); | |
60054393 | 1386 | |
386c036b MK |
1387 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1388 | regcache_raw_collect (regcache, SPARC32_PC_REGNUM, | |
1389 | regs + gregset->r_pc_offset); | |
1390 | ||
1391 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) | |
1392 | regcache_raw_collect (regcache, SPARC32_NPC_REGNUM, | |
1393 | regs + gregset->r_npc_offset); | |
5af923b0 | 1394 | |
386c036b MK |
1395 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1396 | regcache_raw_collect (regcache, SPARC32_Y_REGNUM, | |
1397 | regs + gregset->r_y_offset); | |
1398 | ||
1399 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) | |
5af923b0 | 1400 | { |
386c036b MK |
1401 | int offset = gregset->r_g1_offset; |
1402 | ||
1403 | /* %g0 is always zero. */ | |
1404 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1405 | { | |
1406 | if (regnum == i || regnum == -1) | |
1407 | regcache_raw_collect (regcache, i, regs + offset); | |
1408 | offset += 4; | |
1409 | } | |
5af923b0 | 1410 | } |
386c036b MK |
1411 | |
1412 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
5af923b0 | 1413 | { |
386c036b MK |
1414 | /* Not all of the register set variants include Locals and |
1415 | Inputs. For those that don't, we read them off the stack. */ | |
1416 | if (gregset->r_l0_offset != -1) | |
1417 | { | |
1418 | int offset = gregset->r_l0_offset; | |
1419 | ||
1420 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1421 | { | |
1422 | if (regnum == i || regnum == -1) | |
1423 | regcache_raw_collect (regcache, i, regs + offset); | |
1424 | offset += 4; | |
1425 | } | |
1426 | } | |
5af923b0 | 1427 | } |
c906108c SS |
1428 | } |
1429 | ||
c906108c | 1430 | void |
386c036b MK |
1431 | sparc32_supply_fpregset (struct regcache *regcache, |
1432 | int regnum, const void *fpregs) | |
c906108c | 1433 | { |
386c036b MK |
1434 | const char *regs = fpregs; |
1435 | int i; | |
60054393 | 1436 | |
386c036b | 1437 | for (i = 0; i < 32; i++) |
c906108c | 1438 | { |
386c036b MK |
1439 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) |
1440 | regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, regs + (i * 4)); | |
c906108c | 1441 | } |
5af923b0 | 1442 | |
386c036b MK |
1443 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
1444 | regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4); | |
c906108c SS |
1445 | } |
1446 | ||
386c036b MK |
1447 | void |
1448 | sparc32_collect_fpregset (const struct regcache *regcache, | |
1449 | int regnum, void *fpregs) | |
c906108c | 1450 | { |
386c036b MK |
1451 | char *regs = fpregs; |
1452 | int i; | |
c906108c | 1453 | |
386c036b MK |
1454 | for (i = 0; i < 32; i++) |
1455 | { | |
1456 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) | |
1457 | regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, regs + (i * 4)); | |
1458 | } | |
c906108c | 1459 | |
386c036b MK |
1460 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
1461 | regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4); | |
c906108c | 1462 | } |
c906108c | 1463 | \f |
c906108c | 1464 | |
386c036b | 1465 | /* SunOS 4. */ |
c906108c | 1466 | |
386c036b MK |
1467 | /* From <machine/reg.h>. */ |
1468 | const struct sparc_gregset sparc32_sunos4_gregset = | |
c906108c | 1469 | { |
386c036b MK |
1470 | 0 * 4, /* %psr */ |
1471 | 1 * 4, /* %pc */ | |
1472 | 2 * 4, /* %npc */ | |
1473 | 3 * 4, /* %y */ | |
1474 | -1, /* %wim */ | |
1475 | -1, /* %tbr */ | |
1476 | 4 * 4, /* %g1 */ | |
1477 | -1 /* %l0 */ | |
1478 | }; | |
1479 | \f | |
c906108c | 1480 | |
386c036b MK |
1481 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
1482 | void _initialize_sparc_tdep (void); | |
c906108c SS |
1483 | |
1484 | void | |
386c036b | 1485 | _initialize_sparc_tdep (void) |
c906108c | 1486 | { |
386c036b | 1487 | register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init); |
ef3cf062 | 1488 | } |