Commit | Line | Data |
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386c036b | 1 | /* Target-dependent code for SPARC. |
cda5a58a | 2 | |
61baf725 | 3 | Copyright (C) 2003-2017 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 19 | |
c906108c | 20 | #include "defs.h" |
5af923b0 | 21 | #include "arch-utils.h" |
386c036b | 22 | #include "dis-asm.h" |
f5a9b87d | 23 | #include "dwarf2-frame.h" |
386c036b | 24 | #include "floatformat.h" |
c906108c | 25 | #include "frame.h" |
386c036b MK |
26 | #include "frame-base.h" |
27 | #include "frame-unwind.h" | |
28 | #include "gdbcore.h" | |
29 | #include "gdbtypes.h" | |
c906108c | 30 | #include "inferior.h" |
386c036b MK |
31 | #include "symtab.h" |
32 | #include "objfiles.h" | |
33 | #include "osabi.h" | |
34 | #include "regcache.h" | |
c906108c SS |
35 | #include "target.h" |
36 | #include "value.h" | |
c906108c | 37 | |
386c036b | 38 | #include "sparc-tdep.h" |
e6f9c00b | 39 | #include "sparc-ravenscar-thread.h" |
325fac50 | 40 | #include <algorithm> |
c906108c | 41 | |
a54124c5 MK |
42 | struct regset; |
43 | ||
9eb42ed1 MK |
44 | /* This file implements the SPARC 32-bit ABI as defined by the section |
45 | "Low-Level System Information" of the SPARC Compliance Definition | |
46 | (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD | |
f2e7c15d | 47 | lists changes with respect to the original 32-bit psABI as defined |
9eb42ed1 | 48 | in the "System V ABI, SPARC Processor Supplement". |
386c036b MK |
49 | |
50 | Note that if we talk about SunOS, we mean SunOS 4.x, which was | |
51 | BSD-based, which is sometimes (retroactively?) referred to as | |
52 | Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and | |
53 | above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 | |
54 | suffering from severe version number inflation). Solaris 2.x is | |
55 | also known as SunOS 5.x, since that's what uname(1) says. Solaris | |
56 | 2.x is SVR4-based. */ | |
57 | ||
58 | /* Please use the sparc32_-prefix for 32-bit specific code, the | |
59 | sparc64_-prefix for 64-bit specific code and the sparc_-prefix for | |
60 | code that can handle both. The 64-bit specific code lives in | |
61 | sparc64-tdep.c; don't add any here. */ | |
62 | ||
63 | /* The SPARC Floating-Point Quad-Precision format is similar to | |
7a58cce8 | 64 | big-endian IA-64 Quad-Precision format. */ |
8da61cc4 | 65 | #define floatformats_sparc_quad floatformats_ia64_quad |
386c036b MK |
66 | |
67 | /* The stack pointer is offset from the stack frame by a BIAS of 2047 | |
68 | (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC | |
69 | hosts, so undefine it first. */ | |
70 | #undef BIAS | |
71 | #define BIAS 2047 | |
72 | ||
73 | /* Macros to extract fields from SPARC instructions. */ | |
c906108c SS |
74 | #define X_OP(i) (((i) >> 30) & 0x3) |
75 | #define X_RD(i) (((i) >> 25) & 0x1f) | |
76 | #define X_A(i) (((i) >> 29) & 1) | |
77 | #define X_COND(i) (((i) >> 25) & 0xf) | |
78 | #define X_OP2(i) (((i) >> 22) & 0x7) | |
79 | #define X_IMM22(i) ((i) & 0x3fffff) | |
80 | #define X_OP3(i) (((i) >> 19) & 0x3f) | |
075ccec8 | 81 | #define X_RS1(i) (((i) >> 14) & 0x1f) |
b0b92586 | 82 | #define X_RS2(i) ((i) & 0x1f) |
c906108c | 83 | #define X_I(i) (((i) >> 13) & 1) |
c906108c | 84 | /* Sign extension macros. */ |
c906108c | 85 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) |
c906108c | 86 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) |
8d1b3521 | 87 | #define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200) |
075ccec8 | 88 | #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000) |
961842b2 JM |
89 | /* Macros to identify some instructions. */ |
90 | /* RETURN (RETT in V8) */ | |
91 | #define X_RETTURN(i) ((X_OP (i) == 0x2) && (X_OP3 (i) == 0x39)) | |
c906108c | 92 | |
386c036b MK |
93 | /* Fetch the instruction at PC. Instructions are always big-endian |
94 | even if the processor operates in little-endian mode. */ | |
95 | ||
96 | unsigned long | |
97 | sparc_fetch_instruction (CORE_ADDR pc) | |
c906108c | 98 | { |
e1613aba | 99 | gdb_byte buf[4]; |
386c036b MK |
100 | unsigned long insn; |
101 | int i; | |
102 | ||
690668cc | 103 | /* If we can't read the instruction at PC, return zero. */ |
8defab1a | 104 | if (target_read_memory (pc, buf, sizeof (buf))) |
690668cc | 105 | return 0; |
c906108c | 106 | |
386c036b MK |
107 | insn = 0; |
108 | for (i = 0; i < sizeof (buf); i++) | |
109 | insn = (insn << 8) | buf[i]; | |
110 | return insn; | |
111 | } | |
42cdca6c MK |
112 | \f |
113 | ||
5465445a JB |
114 | /* Return non-zero if the instruction corresponding to PC is an "unimp" |
115 | instruction. */ | |
116 | ||
117 | static int | |
118 | sparc_is_unimp_insn (CORE_ADDR pc) | |
119 | { | |
120 | const unsigned long insn = sparc_fetch_instruction (pc); | |
121 | ||
122 | return ((insn & 0xc1c00000) == 0); | |
123 | } | |
124 | ||
d0b5971a JM |
125 | /* Return non-zero if the instruction corresponding to PC is an |
126 | "annulled" branch, i.e. the annul bit is set. */ | |
127 | ||
128 | int | |
129 | sparc_is_annulled_branch_insn (CORE_ADDR pc) | |
130 | { | |
131 | /* The branch instructions featuring an annul bit can be identified | |
132 | by the following bit patterns: | |
133 | ||
134 | OP=0 | |
135 | OP2=1: Branch on Integer Condition Codes with Prediction (BPcc). | |
136 | OP2=2: Branch on Integer Condition Codes (Bcc). | |
137 | OP2=5: Branch on FP Condition Codes with Prediction (FBfcc). | |
138 | OP2=6: Branch on FP Condition Codes (FBcc). | |
139 | OP2=3 && Bit28=0: | |
140 | Branch on Integer Register with Prediction (BPr). | |
141 | ||
142 | This leaves out ILLTRAP (OP2=0), SETHI/NOP (OP2=4) and the V8 | |
143 | coprocessor branch instructions (Op2=7). */ | |
144 | ||
145 | const unsigned long insn = sparc_fetch_instruction (pc); | |
146 | const unsigned op2 = X_OP2 (insn); | |
147 | ||
148 | if ((X_OP (insn) == 0) | |
149 | && ((op2 == 1) || (op2 == 2) || (op2 == 5) || (op2 == 6) | |
150 | || ((op2 == 3) && ((insn & 0x10000000) == 0)))) | |
151 | return X_A (insn); | |
152 | else | |
153 | return 0; | |
154 | } | |
155 | ||
42cdca6c MK |
156 | /* OpenBSD/sparc includes StackGhost, which according to the author's |
157 | website http://stackghost.cerias.purdue.edu "... transparently and | |
158 | automatically protects applications' stack frames; more | |
159 | specifically, it guards the return pointers. The protection | |
160 | mechanisms require no application source or binary modification and | |
161 | imposes only a negligible performance penalty." | |
162 | ||
163 | The same website provides the following description of how | |
164 | StackGhost works: | |
165 | ||
166 | "StackGhost interfaces with the kernel trap handler that would | |
167 | normally write out registers to the stack and the handler that | |
168 | would read them back in. By XORing a cookie into the | |
169 | return-address saved in the user stack when it is actually written | |
170 | to the stack, and then XOR it out when the return-address is pulled | |
171 | from the stack, StackGhost can cause attacker corrupted return | |
172 | pointers to behave in a manner the attacker cannot predict. | |
173 | StackGhost can also use several unused bits in the return pointer | |
174 | to detect a smashed return pointer and abort the process." | |
175 | ||
176 | For GDB this means that whenever we're reading %i7 from a stack | |
177 | frame's window save area, we'll have to XOR the cookie. | |
178 | ||
179 | More information on StackGuard can be found on in: | |
180 | ||
c378eb4e | 181 | Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated |
42cdca6c MK |
182 | Stack Protection." 2001. Published in USENIX Security Symposium |
183 | '01. */ | |
184 | ||
185 | /* Fetch StackGhost Per-Process XOR cookie. */ | |
186 | ||
187 | ULONGEST | |
e17a4113 | 188 | sparc_fetch_wcookie (struct gdbarch *gdbarch) |
42cdca6c | 189 | { |
e17a4113 | 190 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
baf92889 | 191 | struct target_ops *ops = ¤t_target; |
e1613aba | 192 | gdb_byte buf[8]; |
baf92889 MK |
193 | int len; |
194 | ||
13547ab6 | 195 | len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8); |
baf92889 MK |
196 | if (len == -1) |
197 | return 0; | |
42cdca6c | 198 | |
baf92889 MK |
199 | /* We should have either an 32-bit or an 64-bit cookie. */ |
200 | gdb_assert (len == 4 || len == 8); | |
201 | ||
e17a4113 | 202 | return extract_unsigned_integer (buf, len, byte_order); |
baf92889 | 203 | } |
386c036b | 204 | \f |
baf92889 | 205 | |
386c036b MK |
206 | /* The functions on this page are intended to be used to classify |
207 | function arguments. */ | |
c906108c | 208 | |
386c036b | 209 | /* Check whether TYPE is "Integral or Pointer". */ |
c906108c | 210 | |
386c036b MK |
211 | static int |
212 | sparc_integral_or_pointer_p (const struct type *type) | |
c906108c | 213 | { |
80ad1639 MK |
214 | int len = TYPE_LENGTH (type); |
215 | ||
386c036b | 216 | switch (TYPE_CODE (type)) |
c906108c | 217 | { |
386c036b MK |
218 | case TYPE_CODE_INT: |
219 | case TYPE_CODE_BOOL: | |
220 | case TYPE_CODE_CHAR: | |
221 | case TYPE_CODE_ENUM: | |
222 | case TYPE_CODE_RANGE: | |
80ad1639 MK |
223 | /* We have byte, half-word, word and extended-word/doubleword |
224 | integral types. The doubleword is an extension to the | |
225 | original 32-bit ABI by the SCD 2.4.x. */ | |
226 | return (len == 1 || len == 2 || len == 4 || len == 8); | |
386c036b MK |
227 | case TYPE_CODE_PTR: |
228 | case TYPE_CODE_REF: | |
80ad1639 MK |
229 | /* Allow either 32-bit or 64-bit pointers. */ |
230 | return (len == 4 || len == 8); | |
386c036b MK |
231 | default: |
232 | break; | |
233 | } | |
c906108c | 234 | |
386c036b MK |
235 | return 0; |
236 | } | |
c906108c | 237 | |
386c036b | 238 | /* Check whether TYPE is "Floating". */ |
c906108c | 239 | |
386c036b MK |
240 | static int |
241 | sparc_floating_p (const struct type *type) | |
242 | { | |
243 | switch (TYPE_CODE (type)) | |
c906108c | 244 | { |
386c036b MK |
245 | case TYPE_CODE_FLT: |
246 | { | |
247 | int len = TYPE_LENGTH (type); | |
248 | return (len == 4 || len == 8 || len == 16); | |
249 | } | |
250 | default: | |
251 | break; | |
252 | } | |
253 | ||
254 | return 0; | |
255 | } | |
c906108c | 256 | |
fe10a582 DM |
257 | /* Check whether TYPE is "Complex Floating". */ |
258 | ||
259 | static int | |
260 | sparc_complex_floating_p (const struct type *type) | |
261 | { | |
262 | switch (TYPE_CODE (type)) | |
263 | { | |
264 | case TYPE_CODE_COMPLEX: | |
265 | { | |
266 | int len = TYPE_LENGTH (type); | |
267 | return (len == 8 || len == 16 || len == 32); | |
268 | } | |
269 | default: | |
270 | break; | |
271 | } | |
272 | ||
273 | return 0; | |
274 | } | |
275 | ||
0497f5b0 JB |
276 | /* Check whether TYPE is "Structure or Union". |
277 | ||
278 | In terms of Ada subprogram calls, arrays are treated the same as | |
279 | struct and union types. So this function also returns non-zero | |
280 | for array types. */ | |
c906108c | 281 | |
386c036b MK |
282 | static int |
283 | sparc_structure_or_union_p (const struct type *type) | |
284 | { | |
285 | switch (TYPE_CODE (type)) | |
286 | { | |
287 | case TYPE_CODE_STRUCT: | |
288 | case TYPE_CODE_UNION: | |
0497f5b0 | 289 | case TYPE_CODE_ARRAY: |
386c036b MK |
290 | return 1; |
291 | default: | |
292 | break; | |
c906108c | 293 | } |
386c036b MK |
294 | |
295 | return 0; | |
c906108c | 296 | } |
386c036b MK |
297 | |
298 | /* Register information. */ | |
7a36499a IR |
299 | #define SPARC32_FPU_REGISTERS \ |
300 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ | |
301 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ | |
302 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \ | |
303 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" | |
304 | #define SPARC32_CP0_REGISTERS \ | |
305 | "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" | |
386c036b MK |
306 | |
307 | static const char *sparc32_register_names[] = | |
5af923b0 | 308 | { |
7a36499a IR |
309 | SPARC_CORE_REGISTERS, |
310 | SPARC32_FPU_REGISTERS, | |
311 | SPARC32_CP0_REGISTERS | |
5af923b0 MS |
312 | }; |
313 | ||
386c036b MK |
314 | /* Total number of registers. */ |
315 | #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) | |
c906108c | 316 | |
386c036b MK |
317 | /* We provide the aliases %d0..%d30 for the floating registers as |
318 | "psuedo" registers. */ | |
319 | ||
320 | static const char *sparc32_pseudo_register_names[] = | |
321 | { | |
322 | "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", | |
323 | "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" | |
324 | }; | |
325 | ||
326 | /* Total number of pseudo registers. */ | |
327 | #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) | |
328 | ||
7a36499a IR |
329 | /* Return the name of pseudo register REGNUM. */ |
330 | ||
331 | static const char * | |
332 | sparc32_pseudo_register_name (struct gdbarch *gdbarch, int regnum) | |
333 | { | |
334 | regnum -= gdbarch_num_regs (gdbarch); | |
335 | ||
336 | if (regnum < SPARC32_NUM_PSEUDO_REGS) | |
337 | return sparc32_pseudo_register_names[regnum]; | |
338 | ||
339 | internal_error (__FILE__, __LINE__, | |
340 | _("sparc32_pseudo_register_name: bad register number %d"), | |
341 | regnum); | |
342 | } | |
343 | ||
386c036b MK |
344 | /* Return the name of register REGNUM. */ |
345 | ||
346 | static const char * | |
d93859e2 | 347 | sparc32_register_name (struct gdbarch *gdbarch, int regnum) |
386c036b | 348 | { |
7a36499a | 349 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) |
386c036b MK |
350 | return sparc32_register_names[regnum]; |
351 | ||
7a36499a | 352 | return sparc32_pseudo_register_name (gdbarch, regnum); |
386c036b | 353 | } |
2d457077 | 354 | \f |
209bd28e | 355 | /* Construct types for ISA-specific registers. */ |
2d457077 | 356 | |
209bd28e UW |
357 | static struct type * |
358 | sparc_psr_type (struct gdbarch *gdbarch) | |
359 | { | |
360 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2d457077 | 361 | |
209bd28e UW |
362 | if (!tdep->sparc_psr_type) |
363 | { | |
364 | struct type *type; | |
2d457077 | 365 | |
e9bb382b | 366 | type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 4); |
209bd28e UW |
367 | append_flags_type_flag (type, 5, "ET"); |
368 | append_flags_type_flag (type, 6, "PS"); | |
369 | append_flags_type_flag (type, 7, "S"); | |
370 | append_flags_type_flag (type, 12, "EF"); | |
371 | append_flags_type_flag (type, 13, "EC"); | |
2d457077 | 372 | |
209bd28e UW |
373 | tdep->sparc_psr_type = type; |
374 | } | |
375 | ||
376 | return tdep->sparc_psr_type; | |
377 | } | |
378 | ||
379 | static struct type * | |
380 | sparc_fsr_type (struct gdbarch *gdbarch) | |
2d457077 | 381 | { |
209bd28e UW |
382 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
383 | ||
384 | if (!tdep->sparc_fsr_type) | |
385 | { | |
386 | struct type *type; | |
387 | ||
e9bb382b | 388 | type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 4); |
209bd28e UW |
389 | append_flags_type_flag (type, 0, "NXA"); |
390 | append_flags_type_flag (type, 1, "DZA"); | |
391 | append_flags_type_flag (type, 2, "UFA"); | |
392 | append_flags_type_flag (type, 3, "OFA"); | |
393 | append_flags_type_flag (type, 4, "NVA"); | |
394 | append_flags_type_flag (type, 5, "NXC"); | |
395 | append_flags_type_flag (type, 6, "DZC"); | |
396 | append_flags_type_flag (type, 7, "UFC"); | |
397 | append_flags_type_flag (type, 8, "OFC"); | |
398 | append_flags_type_flag (type, 9, "NVC"); | |
399 | append_flags_type_flag (type, 22, "NS"); | |
400 | append_flags_type_flag (type, 23, "NXM"); | |
401 | append_flags_type_flag (type, 24, "DZM"); | |
402 | append_flags_type_flag (type, 25, "UFM"); | |
403 | append_flags_type_flag (type, 26, "OFM"); | |
404 | append_flags_type_flag (type, 27, "NVM"); | |
405 | ||
406 | tdep->sparc_fsr_type = type; | |
407 | } | |
408 | ||
409 | return tdep->sparc_fsr_type; | |
2d457077 | 410 | } |
386c036b | 411 | |
7a36499a IR |
412 | /* Return the GDB type object for the "standard" data type of data in |
413 | pseudo register REGNUM. */ | |
414 | ||
415 | static struct type * | |
416 | sparc32_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
417 | { | |
418 | regnum -= gdbarch_num_regs (gdbarch); | |
419 | ||
420 | if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) | |
421 | return builtin_type (gdbarch)->builtin_double; | |
422 | ||
423 | internal_error (__FILE__, __LINE__, | |
424 | _("sparc32_pseudo_register_type: bad register number %d"), | |
425 | regnum); | |
426 | } | |
427 | ||
386c036b | 428 | /* Return the GDB type object for the "standard" data type of data in |
c378eb4e | 429 | register REGNUM. */ |
386c036b MK |
430 | |
431 | static struct type * | |
432 | sparc32_register_type (struct gdbarch *gdbarch, int regnum) | |
433 | { | |
434 | if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) | |
0dfff4cb | 435 | return builtin_type (gdbarch)->builtin_float; |
386c036b | 436 | |
386c036b | 437 | if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) |
0dfff4cb | 438 | return builtin_type (gdbarch)->builtin_data_ptr; |
386c036b MK |
439 | |
440 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) | |
0dfff4cb | 441 | return builtin_type (gdbarch)->builtin_func_ptr; |
386c036b | 442 | |
2d457077 | 443 | if (regnum == SPARC32_PSR_REGNUM) |
209bd28e | 444 | return sparc_psr_type (gdbarch); |
2d457077 MK |
445 | |
446 | if (regnum == SPARC32_FSR_REGNUM) | |
209bd28e | 447 | return sparc_fsr_type (gdbarch); |
2d457077 | 448 | |
7a36499a IR |
449 | if (regnum >= gdbarch_num_regs (gdbarch)) |
450 | return sparc32_pseudo_register_type (gdbarch, regnum); | |
451 | ||
df4df182 | 452 | return builtin_type (gdbarch)->builtin_int32; |
386c036b MK |
453 | } |
454 | ||
05d1431c | 455 | static enum register_status |
386c036b MK |
456 | sparc32_pseudo_register_read (struct gdbarch *gdbarch, |
457 | struct regcache *regcache, | |
e1613aba | 458 | int regnum, gdb_byte *buf) |
386c036b | 459 | { |
05d1431c PA |
460 | enum register_status status; |
461 | ||
7a36499a | 462 | regnum -= gdbarch_num_regs (gdbarch); |
386c036b MK |
463 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); |
464 | ||
465 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
05d1431c PA |
466 | status = regcache_raw_read (regcache, regnum, buf); |
467 | if (status == REG_VALID) | |
468 | status = regcache_raw_read (regcache, regnum + 1, buf + 4); | |
469 | return status; | |
386c036b MK |
470 | } |
471 | ||
472 | static void | |
473 | sparc32_pseudo_register_write (struct gdbarch *gdbarch, | |
474 | struct regcache *regcache, | |
e1613aba | 475 | int regnum, const gdb_byte *buf) |
386c036b | 476 | { |
7a36499a | 477 | regnum -= gdbarch_num_regs (gdbarch); |
386c036b MK |
478 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); |
479 | ||
480 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
481 | regcache_raw_write (regcache, regnum, buf); | |
e1613aba | 482 | regcache_raw_write (regcache, regnum + 1, buf + 4); |
386c036b MK |
483 | } |
484 | \f | |
c9cf6e20 | 485 | /* Implement the stack_frame_destroyed_p gdbarch method. */ |
961842b2 JM |
486 | |
487 | int | |
c9cf6e20 | 488 | sparc_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
961842b2 JM |
489 | { |
490 | /* This function must return true if we are one instruction after an | |
491 | instruction that destroyed the stack frame of the current | |
492 | function. The SPARC instructions used to restore the callers | |
493 | stack frame are RESTORE and RETURN/RETT. | |
494 | ||
495 | Of these RETURN/RETT is a branch instruction and thus we return | |
496 | true if we are in its delay slot. | |
497 | ||
498 | RESTORE is almost always found in the delay slot of a branch | |
499 | instruction that transfers control to the caller, such as JMPL. | |
500 | Thus the next instruction is in the caller frame and we don't | |
501 | need to do anything about it. */ | |
502 | ||
503 | unsigned int insn = sparc_fetch_instruction (pc - 4); | |
504 | ||
505 | return X_RETTURN (insn); | |
506 | } | |
507 | \f | |
386c036b | 508 | |
49a45ecf JB |
509 | static CORE_ADDR |
510 | sparc32_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) | |
511 | { | |
512 | /* The ABI requires double-word alignment. */ | |
513 | return address & ~0x7; | |
514 | } | |
515 | ||
386c036b MK |
516 | static CORE_ADDR |
517 | sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
82585c72 | 518 | CORE_ADDR funcaddr, |
386c036b MK |
519 | struct value **args, int nargs, |
520 | struct type *value_type, | |
e4fd649a UW |
521 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, |
522 | struct regcache *regcache) | |
c906108c | 523 | { |
e17a4113 UW |
524 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
525 | ||
386c036b MK |
526 | *bp_addr = sp - 4; |
527 | *real_pc = funcaddr; | |
528 | ||
d80b854b | 529 | if (using_struct_return (gdbarch, NULL, value_type)) |
c906108c | 530 | { |
e1613aba | 531 | gdb_byte buf[4]; |
386c036b MK |
532 | |
533 | /* This is an UNIMP instruction. */ | |
e17a4113 UW |
534 | store_unsigned_integer (buf, 4, byte_order, |
535 | TYPE_LENGTH (value_type) & 0x1fff); | |
386c036b MK |
536 | write_memory (sp - 8, buf, 4); |
537 | return sp - 8; | |
c906108c SS |
538 | } |
539 | ||
386c036b MK |
540 | return sp - 4; |
541 | } | |
542 | ||
543 | static CORE_ADDR | |
544 | sparc32_store_arguments (struct regcache *regcache, int nargs, | |
545 | struct value **args, CORE_ADDR sp, | |
546 | int struct_return, CORE_ADDR struct_addr) | |
547 | { | |
df4df182 | 548 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
e17a4113 | 549 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
386c036b MK |
550 | /* Number of words in the "parameter array". */ |
551 | int num_elements = 0; | |
552 | int element = 0; | |
553 | int i; | |
554 | ||
555 | for (i = 0; i < nargs; i++) | |
c906108c | 556 | { |
4991999e | 557 | struct type *type = value_type (args[i]); |
386c036b MK |
558 | int len = TYPE_LENGTH (type); |
559 | ||
560 | if (sparc_structure_or_union_p (type) | |
fe10a582 DM |
561 | || (sparc_floating_p (type) && len == 16) |
562 | || sparc_complex_floating_p (type)) | |
c906108c | 563 | { |
386c036b MK |
564 | /* Structure, Union and Quad-Precision Arguments. */ |
565 | sp -= len; | |
566 | ||
567 | /* Use doubleword alignment for these values. That's always | |
568 | correct, and wasting a few bytes shouldn't be a problem. */ | |
569 | sp &= ~0x7; | |
570 | ||
0fd88904 | 571 | write_memory (sp, value_contents (args[i]), len); |
386c036b MK |
572 | args[i] = value_from_pointer (lookup_pointer_type (type), sp); |
573 | num_elements++; | |
574 | } | |
575 | else if (sparc_floating_p (type)) | |
576 | { | |
577 | /* Floating arguments. */ | |
578 | gdb_assert (len == 4 || len == 8); | |
579 | num_elements += (len / 4); | |
c906108c | 580 | } |
c5aa993b JM |
581 | else |
582 | { | |
386c036b MK |
583 | /* Integral and pointer arguments. */ |
584 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
585 | ||
586 | if (len < 4) | |
df4df182 UW |
587 | args[i] = value_cast (builtin_type (gdbarch)->builtin_int32, |
588 | args[i]); | |
386c036b | 589 | num_elements += ((len + 3) / 4); |
c5aa993b | 590 | } |
c906108c | 591 | } |
c906108c | 592 | |
386c036b | 593 | /* Always allocate at least six words. */ |
325fac50 | 594 | sp -= std::max (6, num_elements) * 4; |
c906108c | 595 | |
386c036b MK |
596 | /* The psABI says that "Software convention requires space for the |
597 | struct/union return value pointer, even if the word is unused." */ | |
598 | sp -= 4; | |
c906108c | 599 | |
386c036b MK |
600 | /* The psABI says that "Although software convention and the |
601 | operating system require every stack frame to be doubleword | |
602 | aligned." */ | |
603 | sp &= ~0x7; | |
c906108c | 604 | |
386c036b | 605 | for (i = 0; i < nargs; i++) |
c906108c | 606 | { |
0fd88904 | 607 | const bfd_byte *valbuf = value_contents (args[i]); |
4991999e | 608 | struct type *type = value_type (args[i]); |
386c036b | 609 | int len = TYPE_LENGTH (type); |
c906108c | 610 | |
386c036b | 611 | gdb_assert (len == 4 || len == 8); |
c906108c | 612 | |
386c036b MK |
613 | if (element < 6) |
614 | { | |
615 | int regnum = SPARC_O0_REGNUM + element; | |
c906108c | 616 | |
386c036b MK |
617 | regcache_cooked_write (regcache, regnum, valbuf); |
618 | if (len > 4 && element < 5) | |
619 | regcache_cooked_write (regcache, regnum + 1, valbuf + 4); | |
620 | } | |
5af923b0 | 621 | |
386c036b MK |
622 | /* Always store the argument in memory. */ |
623 | write_memory (sp + 4 + element * 4, valbuf, len); | |
624 | element += len / 4; | |
625 | } | |
c906108c | 626 | |
386c036b | 627 | gdb_assert (element == num_elements); |
c906108c | 628 | |
386c036b | 629 | if (struct_return) |
c906108c | 630 | { |
e1613aba | 631 | gdb_byte buf[4]; |
c906108c | 632 | |
e17a4113 | 633 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
386c036b MK |
634 | write_memory (sp, buf, 4); |
635 | } | |
c906108c | 636 | |
386c036b | 637 | return sp; |
c906108c SS |
638 | } |
639 | ||
386c036b | 640 | static CORE_ADDR |
7d9b040b | 641 | sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
386c036b MK |
642 | struct regcache *regcache, CORE_ADDR bp_addr, |
643 | int nargs, struct value **args, CORE_ADDR sp, | |
644 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 645 | { |
386c036b MK |
646 | CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8)); |
647 | ||
648 | /* Set return address. */ | |
649 | regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); | |
650 | ||
651 | /* Set up function arguments. */ | |
652 | sp = sparc32_store_arguments (regcache, nargs, args, sp, | |
653 | struct_return, struct_addr); | |
654 | ||
655 | /* Allocate the 16-word window save area. */ | |
656 | sp -= 16 * 4; | |
c906108c | 657 | |
386c036b MK |
658 | /* Stack should be doubleword aligned at this point. */ |
659 | gdb_assert (sp % 8 == 0); | |
c906108c | 660 | |
386c036b MK |
661 | /* Finally, update the stack pointer. */ |
662 | regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); | |
663 | ||
664 | return sp; | |
665 | } | |
666 | \f | |
c906108c | 667 | |
386c036b MK |
668 | /* Use the program counter to determine the contents and size of a |
669 | breakpoint instruction. Return a pointer to a string of bytes that | |
670 | encode a breakpoint instruction, store the length of the string in | |
671 | *LEN and optionally adjust *PC to point to the correct memory | |
672 | location for inserting the breakpoint. */ | |
04180708 | 673 | constexpr gdb_byte sparc_break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; |
c5aa993b | 674 | |
04180708 | 675 | typedef BP_MANIPULATION (sparc_break_insn) sparc_breakpoint; |
386c036b | 676 | \f |
c906108c | 677 | |
386c036b | 678 | /* Allocate and initialize a frame cache. */ |
c906108c | 679 | |
386c036b MK |
680 | static struct sparc_frame_cache * |
681 | sparc_alloc_frame_cache (void) | |
682 | { | |
683 | struct sparc_frame_cache *cache; | |
c906108c | 684 | |
386c036b | 685 | cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); |
c906108c | 686 | |
386c036b MK |
687 | /* Base address. */ |
688 | cache->base = 0; | |
689 | cache->pc = 0; | |
c906108c | 690 | |
386c036b MK |
691 | /* Frameless until proven otherwise. */ |
692 | cache->frameless_p = 1; | |
369c397b JB |
693 | cache->frame_offset = 0; |
694 | cache->saved_regs_mask = 0; | |
695 | cache->copied_regs_mask = 0; | |
386c036b MK |
696 | cache->struct_return_p = 0; |
697 | ||
698 | return cache; | |
699 | } | |
700 | ||
b0b92586 JB |
701 | /* GCC generates several well-known sequences of instructions at the begining |
702 | of each function prologue when compiling with -fstack-check. If one of | |
703 | such sequences starts at START_PC, then return the address of the | |
704 | instruction immediately past this sequence. Otherwise, return START_PC. */ | |
705 | ||
706 | static CORE_ADDR | |
707 | sparc_skip_stack_check (const CORE_ADDR start_pc) | |
708 | { | |
709 | CORE_ADDR pc = start_pc; | |
710 | unsigned long insn; | |
2067c8d4 | 711 | int probing_loop = 0; |
b0b92586 JB |
712 | |
713 | /* With GCC, all stack checking sequences begin with the same two | |
2067c8d4 | 714 | instructions, plus an optional one in the case of a probing loop: |
b0b92586 | 715 | |
2067c8d4 JG |
716 | sethi <some immediate>, %g1 |
717 | sub %sp, %g1, %g1 | |
718 | ||
719 | or: | |
720 | ||
721 | sethi <some immediate>, %g1 | |
722 | sethi <some immediate>, %g4 | |
723 | sub %sp, %g1, %g1 | |
724 | ||
725 | or: | |
726 | ||
727 | sethi <some immediate>, %g1 | |
728 | sub %sp, %g1, %g1 | |
729 | sethi <some immediate>, %g4 | |
730 | ||
731 | If the optional instruction is found (setting g4), assume that a | |
732 | probing loop will follow. */ | |
733 | ||
734 | /* sethi <some immediate>, %g1 */ | |
b0b92586 JB |
735 | insn = sparc_fetch_instruction (pc); |
736 | pc = pc + 4; | |
737 | if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1)) | |
738 | return start_pc; | |
739 | ||
2067c8d4 | 740 | /* optional: sethi <some immediate>, %g4 */ |
b0b92586 JB |
741 | insn = sparc_fetch_instruction (pc); |
742 | pc = pc + 4; | |
2067c8d4 JG |
743 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) |
744 | { | |
745 | probing_loop = 1; | |
746 | insn = sparc_fetch_instruction (pc); | |
747 | pc = pc + 4; | |
748 | } | |
749 | ||
750 | /* sub %sp, %g1, %g1 */ | |
b0b92586 JB |
751 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) |
752 | && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1)) | |
753 | return start_pc; | |
754 | ||
755 | insn = sparc_fetch_instruction (pc); | |
756 | pc = pc + 4; | |
757 | ||
2067c8d4 JG |
758 | /* optional: sethi <some immediate>, %g4 */ |
759 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) | |
760 | { | |
761 | probing_loop = 1; | |
762 | insn = sparc_fetch_instruction (pc); | |
763 | pc = pc + 4; | |
764 | } | |
765 | ||
b0b92586 JB |
766 | /* First possible sequence: |
767 | [first two instructions above] | |
768 | clr [%g1 - some immediate] */ | |
769 | ||
770 | /* clr [%g1 - some immediate] */ | |
771 | if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
772 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
773 | { | |
774 | /* Valid stack-check sequence, return the new PC. */ | |
775 | return pc; | |
776 | } | |
777 | ||
778 | /* Second possible sequence: A small number of probes. | |
779 | [first two instructions above] | |
780 | clr [%g1] | |
781 | add %g1, -<some immediate>, %g1 | |
782 | clr [%g1] | |
783 | [repeat the two instructions above any (small) number of times] | |
784 | clr [%g1 - some immediate] */ | |
785 | ||
786 | /* clr [%g1] */ | |
787 | else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
788 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
789 | { | |
790 | while (1) | |
791 | { | |
792 | /* add %g1, -<some immediate>, %g1 */ | |
793 | insn = sparc_fetch_instruction (pc); | |
794 | pc = pc + 4; | |
795 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
796 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
797 | break; | |
798 | ||
799 | /* clr [%g1] */ | |
800 | insn = sparc_fetch_instruction (pc); | |
801 | pc = pc + 4; | |
802 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
803 | && X_RD (insn) == 0 && X_RS1 (insn) == 1)) | |
804 | return start_pc; | |
805 | } | |
806 | ||
807 | /* clr [%g1 - some immediate] */ | |
808 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
809 | && X_RS1 (insn) == 1 && X_RD (insn) == 0)) | |
810 | return start_pc; | |
811 | ||
812 | /* We found a valid stack-check sequence, return the new PC. */ | |
813 | return pc; | |
814 | } | |
815 | ||
816 | /* Third sequence: A probing loop. | |
2067c8d4 | 817 | [first three instructions above] |
b0b92586 JB |
818 | sub %g1, %g4, %g4 |
819 | cmp %g1, %g4 | |
820 | be <disp> | |
821 | add %g1, -<some immediate>, %g1 | |
822 | ba <disp> | |
823 | clr [%g1] | |
2067c8d4 JG |
824 | |
825 | And an optional last probe for the remainder: | |
826 | ||
b0b92586 JB |
827 | clr [%g4 - some immediate] */ |
828 | ||
2067c8d4 | 829 | if (probing_loop) |
b0b92586 JB |
830 | { |
831 | /* sub %g1, %g4, %g4 */ | |
b0b92586 JB |
832 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) |
833 | && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
834 | return start_pc; | |
835 | ||
836 | /* cmp %g1, %g4 */ | |
837 | insn = sparc_fetch_instruction (pc); | |
838 | pc = pc + 4; | |
839 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn) | |
840 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
841 | return start_pc; | |
842 | ||
843 | /* be <disp> */ | |
844 | insn = sparc_fetch_instruction (pc); | |
845 | pc = pc + 4; | |
846 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1)) | |
847 | return start_pc; | |
848 | ||
849 | /* add %g1, -<some immediate>, %g1 */ | |
850 | insn = sparc_fetch_instruction (pc); | |
851 | pc = pc + 4; | |
852 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
853 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
854 | return start_pc; | |
855 | ||
856 | /* ba <disp> */ | |
857 | insn = sparc_fetch_instruction (pc); | |
858 | pc = pc + 4; | |
859 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8)) | |
860 | return start_pc; | |
861 | ||
2067c8d4 | 862 | /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */ |
b0b92586 JB |
863 | insn = sparc_fetch_instruction (pc); |
864 | pc = pc + 4; | |
2067c8d4 JG |
865 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 |
866 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 | |
867 | && (!X_I(insn) || X_SIMM13 (insn) == 0))) | |
b0b92586 JB |
868 | return start_pc; |
869 | ||
2067c8d4 JG |
870 | /* We found a valid stack-check sequence, return the new PC. */ |
871 | ||
872 | /* optional: clr [%g4 - some immediate] */ | |
b0b92586 JB |
873 | insn = sparc_fetch_instruction (pc); |
874 | pc = pc + 4; | |
875 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
876 | && X_RS1 (insn) == 4 && X_RD (insn) == 0)) | |
2067c8d4 JG |
877 | return pc - 4; |
878 | else | |
879 | return pc; | |
b0b92586 JB |
880 | } |
881 | ||
882 | /* No stack check code in our prologue, return the start_pc. */ | |
883 | return start_pc; | |
884 | } | |
885 | ||
369c397b JB |
886 | /* Record the effect of a SAVE instruction on CACHE. */ |
887 | ||
888 | void | |
889 | sparc_record_save_insn (struct sparc_frame_cache *cache) | |
890 | { | |
891 | /* The frame is set up. */ | |
892 | cache->frameless_p = 0; | |
893 | ||
894 | /* The frame pointer contains the CFA. */ | |
895 | cache->frame_offset = 0; | |
896 | ||
897 | /* The `local' and `in' registers are all saved. */ | |
898 | cache->saved_regs_mask = 0xffff; | |
899 | ||
900 | /* The `out' registers are all renamed. */ | |
901 | cache->copied_regs_mask = 0xff; | |
902 | } | |
903 | ||
904 | /* Do a full analysis of the prologue at PC and update CACHE accordingly. | |
905 | Bail out early if CURRENT_PC is reached. Return the address where | |
906 | the analysis stopped. | |
907 | ||
908 | We handle both the traditional register window model and the single | |
909 | register window (aka flat) model. */ | |
910 | ||
386c036b | 911 | CORE_ADDR |
be8626e0 MD |
912 | sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, |
913 | CORE_ADDR current_pc, struct sparc_frame_cache *cache) | |
c906108c | 914 | { |
be8626e0 | 915 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
386c036b MK |
916 | unsigned long insn; |
917 | int offset = 0; | |
c906108c | 918 | int dest = -1; |
c906108c | 919 | |
b0b92586 JB |
920 | pc = sparc_skip_stack_check (pc); |
921 | ||
386c036b MK |
922 | if (current_pc <= pc) |
923 | return current_pc; | |
924 | ||
925 | /* We have to handle to "Procedure Linkage Table" (PLT) special. On | |
926 | SPARC the linker usually defines a symbol (typically | |
927 | _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. | |
928 | This symbol makes us end up here with PC pointing at the start of | |
929 | the PLT and CURRENT_PC probably pointing at a PLT entry. If we | |
930 | would do our normal prologue analysis, we would probably conclude | |
931 | that we've got a frame when in reality we don't, since the | |
932 | dynamic linker patches up the first PLT with some code that | |
933 | starts with a SAVE instruction. Patch up PC such that it points | |
934 | at the start of our PLT entry. */ | |
3e5d3a5a | 935 | if (tdep->plt_entry_size > 0 && in_plt_section (current_pc)) |
386c036b | 936 | pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); |
c906108c | 937 | |
386c036b MK |
938 | insn = sparc_fetch_instruction (pc); |
939 | ||
369c397b JB |
940 | /* Recognize store insns and record their sources. */ |
941 | while (X_OP (insn) == 3 | |
942 | && (X_OP3 (insn) == 0x4 /* stw */ | |
943 | || X_OP3 (insn) == 0x7 /* std */ | |
944 | || X_OP3 (insn) == 0xe) /* stx */ | |
945 | && X_RS1 (insn) == SPARC_SP_REGNUM) | |
946 | { | |
947 | int regnum = X_RD (insn); | |
948 | ||
949 | /* Recognize stores into the corresponding stack slots. */ | |
950 | if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM | |
951 | && ((X_I (insn) | |
952 | && X_SIMM13 (insn) == (X_OP3 (insn) == 0xe | |
953 | ? (regnum - SPARC_L0_REGNUM) * 8 + BIAS | |
954 | : (regnum - SPARC_L0_REGNUM) * 4)) | |
955 | || (!X_I (insn) && regnum == SPARC_L0_REGNUM))) | |
956 | { | |
957 | cache->saved_regs_mask |= (1 << (regnum - SPARC_L0_REGNUM)); | |
958 | if (X_OP3 (insn) == 0x7) | |
959 | cache->saved_regs_mask |= (1 << (regnum + 1 - SPARC_L0_REGNUM)); | |
960 | } | |
961 | ||
962 | offset += 4; | |
963 | ||
964 | insn = sparc_fetch_instruction (pc + offset); | |
965 | } | |
966 | ||
386c036b MK |
967 | /* Recognize a SETHI insn and record its destination. */ |
968 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) | |
c906108c SS |
969 | { |
970 | dest = X_RD (insn); | |
386c036b MK |
971 | offset += 4; |
972 | ||
369c397b | 973 | insn = sparc_fetch_instruction (pc + offset); |
c906108c SS |
974 | } |
975 | ||
386c036b MK |
976 | /* Allow for an arithmetic operation on DEST or %g1. */ |
977 | if (X_OP (insn) == 2 && X_I (insn) | |
c906108c SS |
978 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) |
979 | { | |
386c036b | 980 | offset += 4; |
c906108c | 981 | |
369c397b | 982 | insn = sparc_fetch_instruction (pc + offset); |
c906108c | 983 | } |
c906108c | 984 | |
386c036b MK |
985 | /* Check for the SAVE instruction that sets up the frame. */ |
986 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) | |
c906108c | 987 | { |
369c397b JB |
988 | sparc_record_save_insn (cache); |
989 | offset += 4; | |
990 | return pc + offset; | |
991 | } | |
992 | ||
993 | /* Check for an arithmetic operation on %sp. */ | |
994 | if (X_OP (insn) == 2 | |
995 | && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) | |
996 | && X_RS1 (insn) == SPARC_SP_REGNUM | |
997 | && X_RD (insn) == SPARC_SP_REGNUM) | |
998 | { | |
999 | if (X_I (insn)) | |
1000 | { | |
1001 | cache->frame_offset = X_SIMM13 (insn); | |
1002 | if (X_OP3 (insn) == 0) | |
1003 | cache->frame_offset = -cache->frame_offset; | |
1004 | } | |
1005 | offset += 4; | |
1006 | ||
1007 | insn = sparc_fetch_instruction (pc + offset); | |
1008 | ||
1009 | /* Check for an arithmetic operation that sets up the frame. */ | |
1010 | if (X_OP (insn) == 2 | |
1011 | && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) | |
1012 | && X_RS1 (insn) == SPARC_SP_REGNUM | |
1013 | && X_RD (insn) == SPARC_FP_REGNUM) | |
1014 | { | |
1015 | cache->frameless_p = 0; | |
1016 | cache->frame_offset = 0; | |
1017 | /* We could check that the amount subtracted to %sp above is the | |
1018 | same as the one added here, but this seems superfluous. */ | |
1019 | cache->copied_regs_mask |= 0x40; | |
1020 | offset += 4; | |
1021 | ||
1022 | insn = sparc_fetch_instruction (pc + offset); | |
1023 | } | |
1024 | ||
1025 | /* Check for a move (or) operation that copies the return register. */ | |
1026 | if (X_OP (insn) == 2 | |
1027 | && X_OP3 (insn) == 0x2 | |
1028 | && !X_I (insn) | |
1029 | && X_RS1 (insn) == SPARC_G0_REGNUM | |
1030 | && X_RS2 (insn) == SPARC_O7_REGNUM | |
1031 | && X_RD (insn) == SPARC_I7_REGNUM) | |
1032 | { | |
1033 | cache->copied_regs_mask |= 0x80; | |
1034 | offset += 4; | |
1035 | } | |
1036 | ||
1037 | return pc + offset; | |
c906108c SS |
1038 | } |
1039 | ||
1040 | return pc; | |
1041 | } | |
1042 | ||
386c036b | 1043 | static CORE_ADDR |
236369e7 | 1044 | sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) |
386c036b MK |
1045 | { |
1046 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
236369e7 | 1047 | return frame_unwind_register_unsigned (this_frame, tdep->pc_regnum); |
386c036b MK |
1048 | } |
1049 | ||
1050 | /* Return PC of first real instruction of the function starting at | |
1051 | START_PC. */ | |
f510d44e | 1052 | |
386c036b | 1053 | static CORE_ADDR |
6093d2eb | 1054 | sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1055 | { |
f510d44e DM |
1056 | struct symtab_and_line sal; |
1057 | CORE_ADDR func_start, func_end; | |
386c036b | 1058 | struct sparc_frame_cache cache; |
f510d44e DM |
1059 | |
1060 | /* This is the preferred method, find the end of the prologue by | |
1061 | using the debugging information. */ | |
1062 | if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) | |
1063 | { | |
1064 | sal = find_pc_line (func_start, 0); | |
1065 | ||
1066 | if (sal.end < func_end | |
1067 | && start_pc <= sal.end) | |
1068 | return sal.end; | |
1069 | } | |
1070 | ||
be8626e0 | 1071 | start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache); |
075ccec8 MK |
1072 | |
1073 | /* The psABI says that "Although the first 6 words of arguments | |
1074 | reside in registers, the standard stack frame reserves space for | |
1075 | them.". It also suggests that a function may use that space to | |
1076 | "write incoming arguments 0 to 5" into that space, and that's | |
1077 | indeed what GCC seems to be doing. In that case GCC will | |
1078 | generate debug information that points to the stack slots instead | |
1079 | of the registers, so we should consider the instructions that | |
369c397b | 1080 | write out these incoming arguments onto the stack. */ |
075ccec8 | 1081 | |
369c397b | 1082 | while (1) |
075ccec8 MK |
1083 | { |
1084 | unsigned long insn = sparc_fetch_instruction (start_pc); | |
1085 | ||
369c397b JB |
1086 | /* Recognize instructions that store incoming arguments into the |
1087 | corresponding stack slots. */ | |
1088 | if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 | |
1089 | && X_I (insn) && X_RS1 (insn) == SPARC_FP_REGNUM) | |
075ccec8 | 1090 | { |
369c397b JB |
1091 | int regnum = X_RD (insn); |
1092 | ||
1093 | /* Case of arguments still in %o[0..5]. */ | |
1094 | if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O5_REGNUM | |
1095 | && !(cache.copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM))) | |
1096 | && X_SIMM13 (insn) == 68 + (regnum - SPARC_O0_REGNUM) * 4) | |
1097 | { | |
1098 | start_pc += 4; | |
1099 | continue; | |
1100 | } | |
1101 | ||
1102 | /* Case of arguments copied into %i[0..5]. */ | |
1103 | if (regnum >= SPARC_I0_REGNUM && regnum <= SPARC_I5_REGNUM | |
1104 | && (cache.copied_regs_mask & (1 << (regnum - SPARC_I0_REGNUM))) | |
1105 | && X_SIMM13 (insn) == 68 + (regnum - SPARC_I0_REGNUM) * 4) | |
1106 | { | |
1107 | start_pc += 4; | |
1108 | continue; | |
1109 | } | |
075ccec8 MK |
1110 | } |
1111 | ||
1112 | break; | |
1113 | } | |
1114 | ||
1115 | return start_pc; | |
c906108c SS |
1116 | } |
1117 | ||
386c036b | 1118 | /* Normal frames. */ |
9319a2fe | 1119 | |
386c036b | 1120 | struct sparc_frame_cache * |
236369e7 | 1121 | sparc_frame_cache (struct frame_info *this_frame, void **this_cache) |
9319a2fe | 1122 | { |
386c036b | 1123 | struct sparc_frame_cache *cache; |
9319a2fe | 1124 | |
386c036b | 1125 | if (*this_cache) |
19ba03f4 | 1126 | return (struct sparc_frame_cache *) *this_cache; |
c906108c | 1127 | |
386c036b MK |
1128 | cache = sparc_alloc_frame_cache (); |
1129 | *this_cache = cache; | |
c906108c | 1130 | |
236369e7 | 1131 | cache->pc = get_frame_func (this_frame); |
386c036b | 1132 | if (cache->pc != 0) |
236369e7 JB |
1133 | sparc_analyze_prologue (get_frame_arch (this_frame), cache->pc, |
1134 | get_frame_pc (this_frame), cache); | |
386c036b MK |
1135 | |
1136 | if (cache->frameless_p) | |
c906108c | 1137 | { |
cbeae229 MK |
1138 | /* This function is frameless, so %fp (%i6) holds the frame |
1139 | pointer for our calling frame. Use %sp (%o6) as this frame's | |
1140 | base address. */ | |
1141 | cache->base = | |
236369e7 | 1142 | get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
cbeae229 MK |
1143 | } |
1144 | else | |
1145 | { | |
1146 | /* For normal frames, %fp (%i6) holds the frame pointer, the | |
1147 | base address for the current stack frame. */ | |
1148 | cache->base = | |
236369e7 | 1149 | get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM); |
c906108c | 1150 | } |
c906108c | 1151 | |
369c397b JB |
1152 | cache->base += cache->frame_offset; |
1153 | ||
5b2d44a0 MK |
1154 | if (cache->base & 1) |
1155 | cache->base += BIAS; | |
1156 | ||
386c036b | 1157 | return cache; |
c906108c | 1158 | } |
c906108c | 1159 | |
aff37fc1 DM |
1160 | static int |
1161 | sparc32_struct_return_from_sym (struct symbol *sym) | |
1162 | { | |
1163 | struct type *type = check_typedef (SYMBOL_TYPE (sym)); | |
1164 | enum type_code code = TYPE_CODE (type); | |
1165 | ||
1166 | if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) | |
1167 | { | |
1168 | type = check_typedef (TYPE_TARGET_TYPE (type)); | |
1169 | if (sparc_structure_or_union_p (type) | |
1170 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
1171 | return 1; | |
1172 | } | |
1173 | ||
1174 | return 0; | |
1175 | } | |
1176 | ||
386c036b | 1177 | struct sparc_frame_cache * |
236369e7 | 1178 | sparc32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 1179 | { |
386c036b MK |
1180 | struct sparc_frame_cache *cache; |
1181 | struct symbol *sym; | |
c906108c | 1182 | |
386c036b | 1183 | if (*this_cache) |
19ba03f4 | 1184 | return (struct sparc_frame_cache *) *this_cache; |
c906108c | 1185 | |
236369e7 | 1186 | cache = sparc_frame_cache (this_frame, this_cache); |
c906108c | 1187 | |
386c036b MK |
1188 | sym = find_pc_function (cache->pc); |
1189 | if (sym) | |
c906108c | 1190 | { |
aff37fc1 | 1191 | cache->struct_return_p = sparc32_struct_return_from_sym (sym); |
c906108c | 1192 | } |
5465445a JB |
1193 | else |
1194 | { | |
1195 | /* There is no debugging information for this function to | |
1196 | help us determine whether this function returns a struct | |
1197 | or not. So we rely on another heuristic which is to check | |
1198 | the instruction at the return address and see if this is | |
1199 | an "unimp" instruction. If it is, then it is a struct-return | |
1200 | function. */ | |
1201 | CORE_ADDR pc; | |
369c397b JB |
1202 | int regnum = |
1203 | (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; | |
5465445a | 1204 | |
236369e7 | 1205 | pc = get_frame_register_unsigned (this_frame, regnum) + 8; |
5465445a JB |
1206 | if (sparc_is_unimp_insn (pc)) |
1207 | cache->struct_return_p = 1; | |
1208 | } | |
c906108c | 1209 | |
386c036b MK |
1210 | return cache; |
1211 | } | |
1212 | ||
1213 | static void | |
236369e7 | 1214 | sparc32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
386c036b MK |
1215 | struct frame_id *this_id) |
1216 | { | |
1217 | struct sparc_frame_cache *cache = | |
236369e7 | 1218 | sparc32_frame_cache (this_frame, this_cache); |
386c036b MK |
1219 | |
1220 | /* This marks the outermost frame. */ | |
1221 | if (cache->base == 0) | |
1222 | return; | |
1223 | ||
1224 | (*this_id) = frame_id_build (cache->base, cache->pc); | |
1225 | } | |
c906108c | 1226 | |
236369e7 JB |
1227 | static struct value * |
1228 | sparc32_frame_prev_register (struct frame_info *this_frame, | |
1229 | void **this_cache, int regnum) | |
386c036b | 1230 | { |
e17a4113 | 1231 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
386c036b | 1232 | struct sparc_frame_cache *cache = |
236369e7 | 1233 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 1234 | |
386c036b | 1235 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) |
c906108c | 1236 | { |
236369e7 | 1237 | CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; |
386c036b | 1238 | |
236369e7 JB |
1239 | /* If this functions has a Structure, Union or Quad-Precision |
1240 | return value, we have to skip the UNIMP instruction that encodes | |
1241 | the size of the structure. */ | |
1242 | if (cache->struct_return_p) | |
1243 | pc += 4; | |
386c036b | 1244 | |
369c397b JB |
1245 | regnum = |
1246 | (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; | |
236369e7 JB |
1247 | pc += get_frame_register_unsigned (this_frame, regnum) + 8; |
1248 | return frame_unwind_got_constant (this_frame, regnum, pc); | |
c906108c SS |
1249 | } |
1250 | ||
42cdca6c MK |
1251 | /* Handle StackGhost. */ |
1252 | { | |
e17a4113 | 1253 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
42cdca6c MK |
1254 | |
1255 | if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM) | |
1256 | { | |
236369e7 JB |
1257 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
1258 | ULONGEST i7; | |
1259 | ||
1260 | /* Read the value in from memory. */ | |
1261 | i7 = get_frame_memory_unsigned (this_frame, addr, 4); | |
1262 | return frame_unwind_got_constant (this_frame, regnum, i7 ^ wcookie); | |
42cdca6c MK |
1263 | } |
1264 | } | |
1265 | ||
369c397b | 1266 | /* The previous frame's `local' and `in' registers may have been saved |
386c036b | 1267 | in the register save area. */ |
369c397b JB |
1268 | if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM |
1269 | && (cache->saved_regs_mask & (1 << (regnum - SPARC_L0_REGNUM)))) | |
c906108c | 1270 | { |
236369e7 | 1271 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
386c036b | 1272 | |
236369e7 | 1273 | return frame_unwind_got_memory (this_frame, regnum, addr); |
386c036b | 1274 | } |
c906108c | 1275 | |
369c397b JB |
1276 | /* The previous frame's `out' registers may be accessible as the current |
1277 | frame's `in' registers. */ | |
1278 | if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM | |
1279 | && (cache->copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM)))) | |
386c036b | 1280 | regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); |
5af923b0 | 1281 | |
236369e7 | 1282 | return frame_unwind_got_register (this_frame, regnum, regnum); |
386c036b | 1283 | } |
c906108c | 1284 | |
386c036b MK |
1285 | static const struct frame_unwind sparc32_frame_unwind = |
1286 | { | |
1287 | NORMAL_FRAME, | |
8fbca658 | 1288 | default_frame_unwind_stop_reason, |
386c036b | 1289 | sparc32_frame_this_id, |
236369e7 JB |
1290 | sparc32_frame_prev_register, |
1291 | NULL, | |
1292 | default_frame_sniffer | |
386c036b | 1293 | }; |
386c036b | 1294 | \f |
c906108c | 1295 | |
386c036b | 1296 | static CORE_ADDR |
236369e7 | 1297 | sparc32_frame_base_address (struct frame_info *this_frame, void **this_cache) |
386c036b MK |
1298 | { |
1299 | struct sparc_frame_cache *cache = | |
236369e7 | 1300 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 1301 | |
386c036b MK |
1302 | return cache->base; |
1303 | } | |
c906108c | 1304 | |
386c036b MK |
1305 | static const struct frame_base sparc32_frame_base = |
1306 | { | |
1307 | &sparc32_frame_unwind, | |
1308 | sparc32_frame_base_address, | |
1309 | sparc32_frame_base_address, | |
1310 | sparc32_frame_base_address | |
1311 | }; | |
c906108c | 1312 | |
386c036b | 1313 | static struct frame_id |
236369e7 | 1314 | sparc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
386c036b MK |
1315 | { |
1316 | CORE_ADDR sp; | |
5af923b0 | 1317 | |
236369e7 | 1318 | sp = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
5b2d44a0 MK |
1319 | if (sp & 1) |
1320 | sp += BIAS; | |
236369e7 | 1321 | return frame_id_build (sp, get_frame_pc (this_frame)); |
386c036b MK |
1322 | } |
1323 | \f | |
c906108c | 1324 | |
3923a2b2 MK |
1325 | /* Extract a function return value of TYPE from REGCACHE, and copy |
1326 | that into VALBUF. */ | |
5af923b0 | 1327 | |
386c036b MK |
1328 | static void |
1329 | sparc32_extract_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1330 | gdb_byte *valbuf) |
386c036b MK |
1331 | { |
1332 | int len = TYPE_LENGTH (type); | |
fe10a582 | 1333 | gdb_byte buf[32]; |
c906108c | 1334 | |
386c036b MK |
1335 | gdb_assert (!sparc_structure_or_union_p (type)); |
1336 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 1337 | |
fe10a582 | 1338 | if (sparc_floating_p (type) || sparc_complex_floating_p (type)) |
5af923b0 | 1339 | { |
386c036b MK |
1340 | /* Floating return values. */ |
1341 | regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf); | |
1342 | if (len > 4) | |
1343 | regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4); | |
fe10a582 DM |
1344 | if (len > 8) |
1345 | { | |
1346 | regcache_cooked_read (regcache, SPARC_F2_REGNUM, buf + 8); | |
1347 | regcache_cooked_read (regcache, SPARC_F3_REGNUM, buf + 12); | |
1348 | } | |
1349 | if (len > 16) | |
1350 | { | |
1351 | regcache_cooked_read (regcache, SPARC_F4_REGNUM, buf + 16); | |
1352 | regcache_cooked_read (regcache, SPARC_F5_REGNUM, buf + 20); | |
1353 | regcache_cooked_read (regcache, SPARC_F6_REGNUM, buf + 24); | |
1354 | regcache_cooked_read (regcache, SPARC_F7_REGNUM, buf + 28); | |
1355 | } | |
386c036b | 1356 | memcpy (valbuf, buf, len); |
5af923b0 MS |
1357 | } |
1358 | else | |
1359 | { | |
386c036b MK |
1360 | /* Integral and pointer return values. */ |
1361 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
c906108c | 1362 | |
386c036b MK |
1363 | regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); |
1364 | if (len > 4) | |
1365 | { | |
1366 | regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4); | |
1367 | gdb_assert (len == 8); | |
1368 | memcpy (valbuf, buf, 8); | |
1369 | } | |
1370 | else | |
1371 | { | |
1372 | /* Just stripping off any unused bytes should preserve the | |
1373 | signed-ness just fine. */ | |
1374 | memcpy (valbuf, buf + 4 - len, len); | |
1375 | } | |
1376 | } | |
1377 | } | |
c906108c | 1378 | |
3923a2b2 MK |
1379 | /* Store the function return value of type TYPE from VALBUF into |
1380 | REGCACHE. */ | |
c906108c | 1381 | |
386c036b MK |
1382 | static void |
1383 | sparc32_store_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1384 | const gdb_byte *valbuf) |
386c036b MK |
1385 | { |
1386 | int len = TYPE_LENGTH (type); | |
e1613aba | 1387 | gdb_byte buf[8]; |
c906108c | 1388 | |
386c036b MK |
1389 | gdb_assert (!sparc_structure_or_union_p (type)); |
1390 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
a9789a6b | 1391 | gdb_assert (len <= 8); |
c906108c | 1392 | |
fe10a582 | 1393 | if (sparc_floating_p (type) || sparc_complex_floating_p (type)) |
386c036b MK |
1394 | { |
1395 | /* Floating return values. */ | |
1396 | memcpy (buf, valbuf, len); | |
1397 | regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf); | |
1398 | if (len > 4) | |
1399 | regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4); | |
fe10a582 DM |
1400 | if (len > 8) |
1401 | { | |
1402 | regcache_cooked_write (regcache, SPARC_F2_REGNUM, buf + 8); | |
1403 | regcache_cooked_write (regcache, SPARC_F3_REGNUM, buf + 12); | |
1404 | } | |
1405 | if (len > 16) | |
1406 | { | |
1407 | regcache_cooked_write (regcache, SPARC_F4_REGNUM, buf + 16); | |
1408 | regcache_cooked_write (regcache, SPARC_F5_REGNUM, buf + 20); | |
1409 | regcache_cooked_write (regcache, SPARC_F6_REGNUM, buf + 24); | |
1410 | regcache_cooked_write (regcache, SPARC_F7_REGNUM, buf + 28); | |
1411 | } | |
386c036b MK |
1412 | } |
1413 | else | |
c906108c | 1414 | { |
386c036b MK |
1415 | /* Integral and pointer return values. */ |
1416 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
1417 | ||
1418 | if (len > 4) | |
2757dd86 | 1419 | { |
386c036b MK |
1420 | gdb_assert (len == 8); |
1421 | memcpy (buf, valbuf, 8); | |
1422 | regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4); | |
2757dd86 AC |
1423 | } |
1424 | else | |
1425 | { | |
386c036b MK |
1426 | /* ??? Do we need to do any sign-extension here? */ |
1427 | memcpy (buf + 4 - len, valbuf, len); | |
2757dd86 | 1428 | } |
386c036b | 1429 | regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); |
c906108c SS |
1430 | } |
1431 | } | |
1432 | ||
b9d4c5ed | 1433 | static enum return_value_convention |
6a3a010b | 1434 | sparc32_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
1435 | struct type *type, struct regcache *regcache, |
1436 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
b9d4c5ed | 1437 | { |
e17a4113 UW |
1438 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1439 | ||
0a8f48b9 MK |
1440 | /* The psABI says that "...every stack frame reserves the word at |
1441 | %fp+64. If a function returns a structure, union, or | |
1442 | quad-precision value, this word should hold the address of the | |
1443 | object into which the return value should be copied." This | |
1444 | guarantees that we can always find the return value, not just | |
1445 | before the function returns. */ | |
1446 | ||
b9d4c5ed MK |
1447 | if (sparc_structure_or_union_p (type) |
1448 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
0a8f48b9 | 1449 | { |
bbfdfe1c DM |
1450 | ULONGEST sp; |
1451 | CORE_ADDR addr; | |
1452 | ||
0a8f48b9 MK |
1453 | if (readbuf) |
1454 | { | |
0a8f48b9 | 1455 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); |
e17a4113 | 1456 | addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); |
0a8f48b9 MK |
1457 | read_memory (addr, readbuf, TYPE_LENGTH (type)); |
1458 | } | |
bbfdfe1c DM |
1459 | if (writebuf) |
1460 | { | |
1461 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1462 | addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); | |
1463 | write_memory (addr, writebuf, TYPE_LENGTH (type)); | |
1464 | } | |
0a8f48b9 MK |
1465 | |
1466 | return RETURN_VALUE_ABI_PRESERVES_ADDRESS; | |
1467 | } | |
b9d4c5ed MK |
1468 | |
1469 | if (readbuf) | |
1470 | sparc32_extract_return_value (type, regcache, readbuf); | |
1471 | if (writebuf) | |
1472 | sparc32_store_return_value (type, regcache, writebuf); | |
1473 | ||
1474 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1475 | } | |
1476 | ||
386c036b MK |
1477 | static int |
1478 | sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) | |
c906108c | 1479 | { |
386c036b | 1480 | return (sparc_structure_or_union_p (type) |
fe10a582 DM |
1481 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16) |
1482 | || sparc_complex_floating_p (type)); | |
386c036b | 1483 | } |
c906108c | 1484 | |
aff37fc1 | 1485 | static int |
4a4e5149 | 1486 | sparc32_dwarf2_struct_return_p (struct frame_info *this_frame) |
aff37fc1 | 1487 | { |
236369e7 | 1488 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
aff37fc1 DM |
1489 | struct symbol *sym = find_pc_function (pc); |
1490 | ||
1491 | if (sym) | |
1492 | return sparc32_struct_return_from_sym (sym); | |
1493 | return 0; | |
1494 | } | |
1495 | ||
f5a9b87d DM |
1496 | static void |
1497 | sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 | 1498 | struct dwarf2_frame_state_reg *reg, |
4a4e5149 | 1499 | struct frame_info *this_frame) |
f5a9b87d | 1500 | { |
aff37fc1 DM |
1501 | int off; |
1502 | ||
f5a9b87d DM |
1503 | switch (regnum) |
1504 | { | |
1505 | case SPARC_G0_REGNUM: | |
1506 | /* Since %g0 is always zero, there is no point in saving it, and | |
1507 | people will be inclined omit it from the CFI. Make sure we | |
1508 | don't warn about that. */ | |
1509 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
1510 | break; | |
1511 | case SPARC_SP_REGNUM: | |
1512 | reg->how = DWARF2_FRAME_REG_CFA; | |
1513 | break; | |
1514 | case SPARC32_PC_REGNUM: | |
f5a9b87d DM |
1515 | case SPARC32_NPC_REGNUM: |
1516 | reg->how = DWARF2_FRAME_REG_RA_OFFSET; | |
aff37fc1 | 1517 | off = 8; |
4a4e5149 | 1518 | if (sparc32_dwarf2_struct_return_p (this_frame)) |
aff37fc1 DM |
1519 | off += 4; |
1520 | if (regnum == SPARC32_NPC_REGNUM) | |
1521 | off += 4; | |
1522 | reg->loc.offset = off; | |
f5a9b87d DM |
1523 | break; |
1524 | } | |
1525 | } | |
1526 | ||
386c036b MK |
1527 | \f |
1528 | /* The SPARC Architecture doesn't have hardware single-step support, | |
1529 | and most operating systems don't implement it either, so we provide | |
1530 | software single-step mechanism. */ | |
c906108c | 1531 | |
386c036b | 1532 | static CORE_ADDR |
cd76b525 | 1533 | sparc_analyze_control_transfer (struct regcache *regcache, |
c893be75 | 1534 | CORE_ADDR pc, CORE_ADDR *npc) |
386c036b MK |
1535 | { |
1536 | unsigned long insn = sparc_fetch_instruction (pc); | |
1537 | int conditional_p = X_COND (insn) & 0x7; | |
8d1b3521 | 1538 | int branch_p = 0, fused_p = 0; |
386c036b | 1539 | long offset = 0; /* Must be signed for sign-extend. */ |
c906108c | 1540 | |
8d1b3521 | 1541 | if (X_OP (insn) == 0 && X_OP2 (insn) == 3) |
c906108c | 1542 | { |
8d1b3521 DM |
1543 | if ((insn & 0x10000000) == 0) |
1544 | { | |
1545 | /* Branch on Integer Register with Prediction (BPr). */ | |
1546 | branch_p = 1; | |
1547 | conditional_p = 1; | |
1548 | } | |
1549 | else | |
1550 | { | |
1551 | /* Compare and Branch */ | |
1552 | branch_p = 1; | |
1553 | fused_p = 1; | |
1554 | offset = 4 * X_DISP10 (insn); | |
1555 | } | |
c906108c | 1556 | } |
386c036b | 1557 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) |
c906108c | 1558 | { |
386c036b MK |
1559 | /* Branch on Floating-Point Condition Codes (FBfcc). */ |
1560 | branch_p = 1; | |
1561 | offset = 4 * X_DISP22 (insn); | |
c906108c | 1562 | } |
386c036b MK |
1563 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) |
1564 | { | |
1565 | /* Branch on Floating-Point Condition Codes with Prediction | |
1566 | (FBPfcc). */ | |
1567 | branch_p = 1; | |
1568 | offset = 4 * X_DISP19 (insn); | |
1569 | } | |
1570 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) | |
1571 | { | |
1572 | /* Branch on Integer Condition Codes (Bicc). */ | |
1573 | branch_p = 1; | |
1574 | offset = 4 * X_DISP22 (insn); | |
1575 | } | |
1576 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) | |
c906108c | 1577 | { |
386c036b MK |
1578 | /* Branch on Integer Condition Codes with Prediction (BPcc). */ |
1579 | branch_p = 1; | |
1580 | offset = 4 * X_DISP19 (insn); | |
c906108c | 1581 | } |
c893be75 MK |
1582 | else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a) |
1583 | { | |
cd76b525 YQ |
1584 | struct frame_info *frame = get_current_frame (); |
1585 | ||
c893be75 | 1586 | /* Trap instruction (TRAP). */ |
cd76b525 YQ |
1587 | return gdbarch_tdep (get_regcache_arch (regcache))->step_trap (frame, |
1588 | insn); | |
c893be75 | 1589 | } |
386c036b MK |
1590 | |
1591 | /* FIXME: Handle DONE and RETRY instructions. */ | |
1592 | ||
386c036b | 1593 | if (branch_p) |
c906108c | 1594 | { |
8d1b3521 DM |
1595 | if (fused_p) |
1596 | { | |
1597 | /* Fused compare-and-branch instructions are non-delayed, | |
1598 | and do not have an annuling capability. So we need to | |
1599 | always set a breakpoint on both the NPC and the branch | |
1600 | target address. */ | |
1601 | gdb_assert (offset != 0); | |
1602 | return pc + offset; | |
1603 | } | |
1604 | else if (conditional_p) | |
c906108c | 1605 | { |
386c036b MK |
1606 | /* For conditional branches, return nPC + 4 iff the annul |
1607 | bit is 1. */ | |
1608 | return (X_A (insn) ? *npc + 4 : 0); | |
c906108c SS |
1609 | } |
1610 | else | |
1611 | { | |
386c036b MK |
1612 | /* For unconditional branches, return the target if its |
1613 | specified condition is "always" and return nPC + 4 if the | |
1614 | condition is "never". If the annul bit is 1, set *NPC to | |
1615 | zero. */ | |
1616 | if (X_COND (insn) == 0x0) | |
1617 | pc = *npc, offset = 4; | |
1618 | if (X_A (insn)) | |
1619 | *npc = 0; | |
1620 | ||
386c036b | 1621 | return pc + offset; |
c906108c SS |
1622 | } |
1623 | } | |
386c036b MK |
1624 | |
1625 | return 0; | |
c906108c SS |
1626 | } |
1627 | ||
c893be75 | 1628 | static CORE_ADDR |
0b1b3e42 | 1629 | sparc_step_trap (struct frame_info *frame, unsigned long insn) |
c893be75 MK |
1630 | { |
1631 | return 0; | |
1632 | } | |
1633 | ||
93f9a11f | 1634 | static VEC (CORE_ADDR) * |
f5ea389a | 1635 | sparc_software_single_step (struct regcache *regcache) |
386c036b | 1636 | { |
cd76b525 | 1637 | struct gdbarch *arch = get_regcache_arch (regcache); |
c893be75 | 1638 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
8181d85f | 1639 | CORE_ADDR npc, nnpc; |
c906108c | 1640 | |
e0cd558a | 1641 | CORE_ADDR pc, orig_npc; |
93f9a11f | 1642 | VEC (CORE_ADDR) *next_pcs = NULL; |
c906108c | 1643 | |
cd76b525 YQ |
1644 | pc = regcache_raw_get_unsigned (regcache, tdep->pc_regnum); |
1645 | orig_npc = npc = regcache_raw_get_unsigned (regcache, tdep->npc_regnum); | |
c906108c | 1646 | |
e0cd558a | 1647 | /* Analyze the instruction at PC. */ |
cd76b525 | 1648 | nnpc = sparc_analyze_control_transfer (regcache, pc, &npc); |
e0cd558a | 1649 | if (npc != 0) |
93f9a11f | 1650 | VEC_safe_push (CORE_ADDR, next_pcs, npc); |
8181d85f | 1651 | |
e0cd558a | 1652 | if (nnpc != 0) |
93f9a11f | 1653 | VEC_safe_push (CORE_ADDR, next_pcs, nnpc); |
c906108c | 1654 | |
e0cd558a UW |
1655 | /* Assert that we have set at least one breakpoint, and that |
1656 | they're not set at the same spot - unless we're going | |
1657 | from here straight to NULL, i.e. a call or jump to 0. */ | |
1658 | gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0); | |
1659 | gdb_assert (nnpc != npc || orig_npc == 0); | |
e6590a1b | 1660 | |
93f9a11f | 1661 | return next_pcs; |
386c036b MK |
1662 | } |
1663 | ||
1664 | static void | |
61a1198a | 1665 | sparc_write_pc (struct regcache *regcache, CORE_ADDR pc) |
386c036b | 1666 | { |
61a1198a | 1667 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
386c036b | 1668 | |
61a1198a UW |
1669 | regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc); |
1670 | regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4); | |
386c036b MK |
1671 | } |
1672 | \f | |
5af923b0 | 1673 | |
e5139de8 | 1674 | /* Iterate over core file register note sections. */ |
a54124c5 | 1675 | |
e5139de8 AA |
1676 | static void |
1677 | sparc_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
1678 | iterate_over_regset_sections_cb *cb, | |
1679 | void *cb_data, | |
1680 | const struct regcache *regcache) | |
a54124c5 MK |
1681 | { |
1682 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1683 | ||
e5139de8 AA |
1684 | cb (".reg", tdep->sizeof_gregset, tdep->gregset, NULL, cb_data); |
1685 | cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data); | |
a54124c5 MK |
1686 | } |
1687 | \f | |
1688 | ||
386c036b MK |
1689 | static struct gdbarch * |
1690 | sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1691 | { | |
1692 | struct gdbarch_tdep *tdep; | |
1693 | struct gdbarch *gdbarch; | |
c906108c | 1694 | |
386c036b MK |
1695 | /* If there is already a candidate, use it. */ |
1696 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1697 | if (arches != NULL) | |
1698 | return arches->gdbarch; | |
c906108c | 1699 | |
386c036b | 1700 | /* Allocate space for the new architecture. */ |
41bf6aca | 1701 | tdep = XCNEW (struct gdbarch_tdep); |
386c036b | 1702 | gdbarch = gdbarch_alloc (&info, tdep); |
5af923b0 | 1703 | |
386c036b MK |
1704 | tdep->pc_regnum = SPARC32_PC_REGNUM; |
1705 | tdep->npc_regnum = SPARC32_NPC_REGNUM; | |
c893be75 | 1706 | tdep->step_trap = sparc_step_trap; |
386c036b MK |
1707 | |
1708 | set_gdbarch_long_double_bit (gdbarch, 128); | |
8da61cc4 | 1709 | set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad); |
386c036b MK |
1710 | |
1711 | set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); | |
1712 | set_gdbarch_register_name (gdbarch, sparc32_register_name); | |
1713 | set_gdbarch_register_type (gdbarch, sparc32_register_type); | |
1714 | set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); | |
1715 | set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); | |
1716 | set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); | |
1717 | ||
1718 | /* Register numbers of various important registers. */ | |
1719 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ | |
1720 | set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ | |
1721 | set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ | |
1722 | ||
1723 | /* Call dummy code. */ | |
49a45ecf | 1724 | set_gdbarch_frame_align (gdbarch, sparc32_frame_align); |
386c036b MK |
1725 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
1726 | set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); | |
1727 | set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); | |
1728 | ||
b9d4c5ed | 1729 | set_gdbarch_return_value (gdbarch, sparc32_return_value); |
386c036b MK |
1730 | set_gdbarch_stabs_argument_has_addr |
1731 | (gdbarch, sparc32_stabs_argument_has_addr); | |
1732 | ||
1733 | set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); | |
1734 | ||
1735 | /* Stack grows downward. */ | |
1736 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
c906108c | 1737 | |
04180708 YQ |
1738 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
1739 | sparc_breakpoint::kind_from_pc); | |
1740 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
1741 | sparc_breakpoint::bp_from_kind); | |
c906108c | 1742 | |
386c036b | 1743 | set_gdbarch_frame_args_skip (gdbarch, 8); |
5af923b0 | 1744 | |
386c036b | 1745 | set_gdbarch_print_insn (gdbarch, print_insn_sparc); |
c906108c | 1746 | |
386c036b MK |
1747 | set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); |
1748 | set_gdbarch_write_pc (gdbarch, sparc_write_pc); | |
c906108c | 1749 | |
236369e7 | 1750 | set_gdbarch_dummy_id (gdbarch, sparc_dummy_id); |
c906108c | 1751 | |
386c036b | 1752 | set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc); |
c906108c | 1753 | |
386c036b MK |
1754 | frame_base_set_default (gdbarch, &sparc32_frame_base); |
1755 | ||
f5a9b87d DM |
1756 | /* Hook in the DWARF CFI frame unwinder. */ |
1757 | dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg); | |
1758 | /* FIXME: kettenis/20050423: Don't enable the unwinder until the | |
1759 | StackGhost issues have been resolved. */ | |
1760 | ||
b2a0b9b2 DM |
1761 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1762 | gdbarch_init_osabi (info, gdbarch); | |
1763 | ||
236369e7 | 1764 | frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind); |
c906108c | 1765 | |
a54124c5 | 1766 | /* If we have register sets, enable the generic core file support. */ |
4c72d57a | 1767 | if (tdep->gregset) |
e5139de8 AA |
1768 | set_gdbarch_iterate_over_regset_sections |
1769 | (gdbarch, sparc_iterate_over_regset_sections); | |
a54124c5 | 1770 | |
7e35103a JB |
1771 | register_sparc_ravenscar_ops (gdbarch); |
1772 | ||
386c036b MK |
1773 | return gdbarch; |
1774 | } | |
1775 | \f | |
1776 | /* Helper functions for dealing with register windows. */ | |
1777 | ||
1778 | void | |
1779 | sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) | |
c906108c | 1780 | { |
e17a4113 UW |
1781 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1782 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
386c036b | 1783 | int offset = 0; |
e1613aba | 1784 | gdb_byte buf[8]; |
386c036b MK |
1785 | int i; |
1786 | ||
1787 | if (sp & 1) | |
1788 | { | |
1789 | /* Registers are 64-bit. */ | |
1790 | sp += BIAS; | |
c906108c | 1791 | |
386c036b MK |
1792 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1793 | { | |
1794 | if (regnum == i || regnum == -1) | |
1795 | { | |
1796 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); | |
f700a364 MK |
1797 | |
1798 | /* Handle StackGhost. */ | |
1799 | if (i == SPARC_I7_REGNUM) | |
1800 | { | |
e17a4113 UW |
1801 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1802 | ULONGEST i7; | |
f700a364 | 1803 | |
e17a4113 UW |
1804 | i7 = extract_unsigned_integer (buf + offset, 8, byte_order); |
1805 | store_unsigned_integer (buf + offset, 8, byte_order, | |
1806 | i7 ^ wcookie); | |
f700a364 MK |
1807 | } |
1808 | ||
386c036b MK |
1809 | regcache_raw_supply (regcache, i, buf); |
1810 | } | |
1811 | } | |
1812 | } | |
1813 | else | |
c906108c | 1814 | { |
386c036b MK |
1815 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1816 | pointer. */ | |
1817 | sp &= 0xffffffffUL; | |
c906108c | 1818 | |
386c036b MK |
1819 | /* Clear out the top half of the temporary buffer, and put the |
1820 | register value in the bottom half if we're in 64-bit mode. */ | |
e6d4f032 | 1821 | if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) |
c906108c | 1822 | { |
386c036b MK |
1823 | memset (buf, 0, 4); |
1824 | offset = 4; | |
1825 | } | |
c906108c | 1826 | |
386c036b MK |
1827 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1828 | { | |
1829 | if (regnum == i || regnum == -1) | |
1830 | { | |
1831 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), | |
1832 | buf + offset, 4); | |
42cdca6c MK |
1833 | |
1834 | /* Handle StackGhost. */ | |
1835 | if (i == SPARC_I7_REGNUM) | |
1836 | { | |
e17a4113 UW |
1837 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1838 | ULONGEST i7; | |
42cdca6c | 1839 | |
e17a4113 UW |
1840 | i7 = extract_unsigned_integer (buf + offset, 4, byte_order); |
1841 | store_unsigned_integer (buf + offset, 4, byte_order, | |
1842 | i7 ^ wcookie); | |
42cdca6c MK |
1843 | } |
1844 | ||
386c036b MK |
1845 | regcache_raw_supply (regcache, i, buf); |
1846 | } | |
c906108c SS |
1847 | } |
1848 | } | |
c906108c | 1849 | } |
c906108c SS |
1850 | |
1851 | void | |
386c036b MK |
1852 | sparc_collect_rwindow (const struct regcache *regcache, |
1853 | CORE_ADDR sp, int regnum) | |
c906108c | 1854 | { |
e17a4113 UW |
1855 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1856 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
386c036b | 1857 | int offset = 0; |
e1613aba | 1858 | gdb_byte buf[8]; |
386c036b | 1859 | int i; |
5af923b0 | 1860 | |
386c036b | 1861 | if (sp & 1) |
5af923b0 | 1862 | { |
386c036b MK |
1863 | /* Registers are 64-bit. */ |
1864 | sp += BIAS; | |
c906108c | 1865 | |
386c036b MK |
1866 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1867 | { | |
1868 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1869 | { | |
1870 | regcache_raw_collect (regcache, i, buf); | |
f700a364 MK |
1871 | |
1872 | /* Handle StackGhost. */ | |
1873 | if (i == SPARC_I7_REGNUM) | |
1874 | { | |
e17a4113 UW |
1875 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1876 | ULONGEST i7; | |
f700a364 | 1877 | |
e17a4113 UW |
1878 | i7 = extract_unsigned_integer (buf + offset, 8, byte_order); |
1879 | store_unsigned_integer (buf, 8, byte_order, i7 ^ wcookie); | |
f700a364 MK |
1880 | } |
1881 | ||
386c036b MK |
1882 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); |
1883 | } | |
1884 | } | |
5af923b0 MS |
1885 | } |
1886 | else | |
1887 | { | |
386c036b MK |
1888 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1889 | pointer. */ | |
1890 | sp &= 0xffffffffUL; | |
1891 | ||
1892 | /* Only use the bottom half if we're in 64-bit mode. */ | |
e6d4f032 | 1893 | if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) |
386c036b MK |
1894 | offset = 4; |
1895 | ||
1896 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1897 | { | |
1898 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1899 | { | |
1900 | regcache_raw_collect (regcache, i, buf); | |
42cdca6c MK |
1901 | |
1902 | /* Handle StackGhost. */ | |
1903 | if (i == SPARC_I7_REGNUM) | |
1904 | { | |
e17a4113 UW |
1905 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1906 | ULONGEST i7; | |
42cdca6c | 1907 | |
e17a4113 UW |
1908 | i7 = extract_unsigned_integer (buf + offset, 4, byte_order); |
1909 | store_unsigned_integer (buf + offset, 4, byte_order, | |
1910 | i7 ^ wcookie); | |
42cdca6c MK |
1911 | } |
1912 | ||
386c036b MK |
1913 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), |
1914 | buf + offset, 4); | |
1915 | } | |
1916 | } | |
5af923b0 | 1917 | } |
c906108c SS |
1918 | } |
1919 | ||
386c036b MK |
1920 | /* Helper functions for dealing with register sets. */ |
1921 | ||
c906108c | 1922 | void |
b4fd25c9 | 1923 | sparc32_supply_gregset (const struct sparc_gregmap *gregmap, |
386c036b MK |
1924 | struct regcache *regcache, |
1925 | int regnum, const void *gregs) | |
c906108c | 1926 | { |
19ba03f4 | 1927 | const gdb_byte *regs = (const gdb_byte *) gregs; |
22e74ef9 | 1928 | gdb_byte zero[4] = { 0 }; |
386c036b | 1929 | int i; |
5af923b0 | 1930 | |
386c036b MK |
1931 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1932 | regcache_raw_supply (regcache, SPARC32_PSR_REGNUM, | |
b4fd25c9 | 1933 | regs + gregmap->r_psr_offset); |
c906108c | 1934 | |
386c036b MK |
1935 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1936 | regcache_raw_supply (regcache, SPARC32_PC_REGNUM, | |
b4fd25c9 | 1937 | regs + gregmap->r_pc_offset); |
5af923b0 | 1938 | |
386c036b MK |
1939 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) |
1940 | regcache_raw_supply (regcache, SPARC32_NPC_REGNUM, | |
b4fd25c9 | 1941 | regs + gregmap->r_npc_offset); |
5af923b0 | 1942 | |
386c036b MK |
1943 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1944 | regcache_raw_supply (regcache, SPARC32_Y_REGNUM, | |
b4fd25c9 | 1945 | regs + gregmap->r_y_offset); |
5af923b0 | 1946 | |
386c036b | 1947 | if (regnum == SPARC_G0_REGNUM || regnum == -1) |
22e74ef9 | 1948 | regcache_raw_supply (regcache, SPARC_G0_REGNUM, &zero); |
5af923b0 | 1949 | |
386c036b | 1950 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) |
c906108c | 1951 | { |
b4fd25c9 | 1952 | int offset = gregmap->r_g1_offset; |
386c036b MK |
1953 | |
1954 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1955 | { | |
1956 | if (regnum == i || regnum == -1) | |
1957 | regcache_raw_supply (regcache, i, regs + offset); | |
1958 | offset += 4; | |
1959 | } | |
c906108c | 1960 | } |
386c036b MK |
1961 | |
1962 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
c906108c | 1963 | { |
386c036b MK |
1964 | /* Not all of the register set variants include Locals and |
1965 | Inputs. For those that don't, we read them off the stack. */ | |
b4fd25c9 | 1966 | if (gregmap->r_l0_offset == -1) |
386c036b MK |
1967 | { |
1968 | ULONGEST sp; | |
1969 | ||
1970 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1971 | sparc_supply_rwindow (regcache, sp, regnum); | |
1972 | } | |
1973 | else | |
1974 | { | |
b4fd25c9 | 1975 | int offset = gregmap->r_l0_offset; |
386c036b MK |
1976 | |
1977 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1978 | { | |
1979 | if (regnum == i || regnum == -1) | |
1980 | regcache_raw_supply (regcache, i, regs + offset); | |
1981 | offset += 4; | |
1982 | } | |
1983 | } | |
c906108c SS |
1984 | } |
1985 | } | |
1986 | ||
c5aa993b | 1987 | void |
b4fd25c9 | 1988 | sparc32_collect_gregset (const struct sparc_gregmap *gregmap, |
386c036b MK |
1989 | const struct regcache *regcache, |
1990 | int regnum, void *gregs) | |
c906108c | 1991 | { |
19ba03f4 | 1992 | gdb_byte *regs = (gdb_byte *) gregs; |
386c036b | 1993 | int i; |
c5aa993b | 1994 | |
386c036b MK |
1995 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1996 | regcache_raw_collect (regcache, SPARC32_PSR_REGNUM, | |
b4fd25c9 | 1997 | regs + gregmap->r_psr_offset); |
60054393 | 1998 | |
386c036b MK |
1999 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
2000 | regcache_raw_collect (regcache, SPARC32_PC_REGNUM, | |
b4fd25c9 | 2001 | regs + gregmap->r_pc_offset); |
386c036b MK |
2002 | |
2003 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) | |
2004 | regcache_raw_collect (regcache, SPARC32_NPC_REGNUM, | |
b4fd25c9 | 2005 | regs + gregmap->r_npc_offset); |
5af923b0 | 2006 | |
386c036b MK |
2007 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
2008 | regcache_raw_collect (regcache, SPARC32_Y_REGNUM, | |
b4fd25c9 | 2009 | regs + gregmap->r_y_offset); |
386c036b MK |
2010 | |
2011 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) | |
5af923b0 | 2012 | { |
b4fd25c9 | 2013 | int offset = gregmap->r_g1_offset; |
386c036b MK |
2014 | |
2015 | /* %g0 is always zero. */ | |
2016 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
2017 | { | |
2018 | if (regnum == i || regnum == -1) | |
2019 | regcache_raw_collect (regcache, i, regs + offset); | |
2020 | offset += 4; | |
2021 | } | |
5af923b0 | 2022 | } |
386c036b MK |
2023 | |
2024 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
5af923b0 | 2025 | { |
386c036b MK |
2026 | /* Not all of the register set variants include Locals and |
2027 | Inputs. For those that don't, we read them off the stack. */ | |
b4fd25c9 | 2028 | if (gregmap->r_l0_offset != -1) |
386c036b | 2029 | { |
b4fd25c9 | 2030 | int offset = gregmap->r_l0_offset; |
386c036b MK |
2031 | |
2032 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
2033 | { | |
2034 | if (regnum == i || regnum == -1) | |
2035 | regcache_raw_collect (regcache, i, regs + offset); | |
2036 | offset += 4; | |
2037 | } | |
2038 | } | |
5af923b0 | 2039 | } |
c906108c SS |
2040 | } |
2041 | ||
c906108c | 2042 | void |
b4fd25c9 | 2043 | sparc32_supply_fpregset (const struct sparc_fpregmap *fpregmap, |
db75c717 | 2044 | struct regcache *regcache, |
386c036b | 2045 | int regnum, const void *fpregs) |
c906108c | 2046 | { |
19ba03f4 | 2047 | const gdb_byte *regs = (const gdb_byte *) fpregs; |
386c036b | 2048 | int i; |
60054393 | 2049 | |
386c036b | 2050 | for (i = 0; i < 32; i++) |
c906108c | 2051 | { |
386c036b | 2052 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) |
db75c717 | 2053 | regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, |
b4fd25c9 | 2054 | regs + fpregmap->r_f0_offset + (i * 4)); |
c906108c | 2055 | } |
5af923b0 | 2056 | |
386c036b | 2057 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
db75c717 | 2058 | regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, |
b4fd25c9 | 2059 | regs + fpregmap->r_fsr_offset); |
c906108c SS |
2060 | } |
2061 | ||
386c036b | 2062 | void |
b4fd25c9 | 2063 | sparc32_collect_fpregset (const struct sparc_fpregmap *fpregmap, |
db75c717 | 2064 | const struct regcache *regcache, |
386c036b | 2065 | int regnum, void *fpregs) |
c906108c | 2066 | { |
19ba03f4 | 2067 | gdb_byte *regs = (gdb_byte *) fpregs; |
386c036b | 2068 | int i; |
c906108c | 2069 | |
386c036b MK |
2070 | for (i = 0; i < 32; i++) |
2071 | { | |
2072 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) | |
db75c717 | 2073 | regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, |
b4fd25c9 | 2074 | regs + fpregmap->r_f0_offset + (i * 4)); |
386c036b | 2075 | } |
c906108c | 2076 | |
386c036b | 2077 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
db75c717 | 2078 | regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, |
b4fd25c9 | 2079 | regs + fpregmap->r_fsr_offset); |
c906108c | 2080 | } |
c906108c | 2081 | \f |
c906108c | 2082 | |
386c036b | 2083 | /* SunOS 4. */ |
c906108c | 2084 | |
386c036b | 2085 | /* From <machine/reg.h>. */ |
b4fd25c9 | 2086 | const struct sparc_gregmap sparc32_sunos4_gregmap = |
c906108c | 2087 | { |
386c036b MK |
2088 | 0 * 4, /* %psr */ |
2089 | 1 * 4, /* %pc */ | |
2090 | 2 * 4, /* %npc */ | |
2091 | 3 * 4, /* %y */ | |
2092 | -1, /* %wim */ | |
2093 | -1, /* %tbr */ | |
2094 | 4 * 4, /* %g1 */ | |
2095 | -1 /* %l0 */ | |
2096 | }; | |
db75c717 | 2097 | |
b4fd25c9 | 2098 | const struct sparc_fpregmap sparc32_sunos4_fpregmap = |
db75c717 DM |
2099 | { |
2100 | 0 * 4, /* %f0 */ | |
2101 | 33 * 4, /* %fsr */ | |
2102 | }; | |
2103 | ||
b4fd25c9 | 2104 | const struct sparc_fpregmap sparc32_bsd_fpregmap = |
db75c717 DM |
2105 | { |
2106 | 0 * 4, /* %f0 */ | |
2107 | 32 * 4, /* %fsr */ | |
2108 | }; | |
386c036b | 2109 | \f |
c906108c | 2110 | |
386c036b MK |
2111 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
2112 | void _initialize_sparc_tdep (void); | |
c906108c SS |
2113 | |
2114 | void | |
386c036b | 2115 | _initialize_sparc_tdep (void) |
c906108c | 2116 | { |
386c036b | 2117 | register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init); |
ef3cf062 | 2118 | } |