Commit | Line | Data |
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386c036b | 1 | /* Target-dependent code for SPARC. |
cda5a58a | 2 | |
386c036b | 3 | Copyright 2003, 2004 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c | 21 | |
c906108c | 22 | #include "defs.h" |
5af923b0 | 23 | #include "arch-utils.h" |
386c036b MK |
24 | #include "dis-asm.h" |
25 | #include "floatformat.h" | |
c906108c | 26 | #include "frame.h" |
386c036b MK |
27 | #include "frame-base.h" |
28 | #include "frame-unwind.h" | |
29 | #include "gdbcore.h" | |
30 | #include "gdbtypes.h" | |
c906108c | 31 | #include "inferior.h" |
386c036b MK |
32 | #include "symtab.h" |
33 | #include "objfiles.h" | |
34 | #include "osabi.h" | |
35 | #include "regcache.h" | |
c906108c SS |
36 | #include "target.h" |
37 | #include "value.h" | |
c906108c | 38 | |
43bd9a9e | 39 | #include "gdb_assert.h" |
386c036b | 40 | #include "gdb_string.h" |
c906108c | 41 | |
386c036b | 42 | #include "sparc-tdep.h" |
c906108c | 43 | |
386c036b MK |
44 | /* This file implements the The SPARC 32-bit ABI as defined by the |
45 | section "Low-Level System Information" of the SPARC Compliance | |
46 | Definition (SCD) 2.4.1, which is the 32-bit System V psABI for | |
47 | SPARC. The SCD lists changes with respect to the origional 32-bit | |
48 | psABI as defined in the "System V ABI, SPARC Processor | |
49 | Supplement". | |
50 | ||
51 | Note that if we talk about SunOS, we mean SunOS 4.x, which was | |
52 | BSD-based, which is sometimes (retroactively?) referred to as | |
53 | Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and | |
54 | above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 | |
55 | suffering from severe version number inflation). Solaris 2.x is | |
56 | also known as SunOS 5.x, since that's what uname(1) says. Solaris | |
57 | 2.x is SVR4-based. */ | |
58 | ||
59 | /* Please use the sparc32_-prefix for 32-bit specific code, the | |
60 | sparc64_-prefix for 64-bit specific code and the sparc_-prefix for | |
61 | code that can handle both. The 64-bit specific code lives in | |
62 | sparc64-tdep.c; don't add any here. */ | |
63 | ||
64 | /* The SPARC Floating-Point Quad-Precision format is similar to | |
65 | big-endian IA-64 Quad-recision format. */ | |
66 | #define floatformat_sparc_quad floatformat_ia64_quad_big | |
67 | ||
68 | /* The stack pointer is offset from the stack frame by a BIAS of 2047 | |
69 | (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC | |
70 | hosts, so undefine it first. */ | |
71 | #undef BIAS | |
72 | #define BIAS 2047 | |
73 | ||
74 | /* Macros to extract fields from SPARC instructions. */ | |
c906108c SS |
75 | #define X_OP(i) (((i) >> 30) & 0x3) |
76 | #define X_RD(i) (((i) >> 25) & 0x1f) | |
77 | #define X_A(i) (((i) >> 29) & 1) | |
78 | #define X_COND(i) (((i) >> 25) & 0xf) | |
79 | #define X_OP2(i) (((i) >> 22) & 0x7) | |
80 | #define X_IMM22(i) ((i) & 0x3fffff) | |
81 | #define X_OP3(i) (((i) >> 19) & 0x3f) | |
c906108c | 82 | #define X_I(i) (((i) >> 13) & 1) |
c906108c | 83 | /* Sign extension macros. */ |
c906108c | 84 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) |
c906108c | 85 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) |
c906108c | 86 | |
386c036b MK |
87 | /* Fetch the instruction at PC. Instructions are always big-endian |
88 | even if the processor operates in little-endian mode. */ | |
89 | ||
90 | unsigned long | |
91 | sparc_fetch_instruction (CORE_ADDR pc) | |
c906108c | 92 | { |
386c036b MK |
93 | unsigned char buf[4]; |
94 | unsigned long insn; | |
95 | int i; | |
96 | ||
97 | read_memory (pc, buf, sizeof (buf)); | |
c906108c | 98 | |
386c036b MK |
99 | insn = 0; |
100 | for (i = 0; i < sizeof (buf); i++) | |
101 | insn = (insn << 8) | buf[i]; | |
102 | return insn; | |
103 | } | |
104 | \f | |
105 | /* Return the contents if register REGNUM as an address. */ | |
c906108c | 106 | |
386c036b MK |
107 | static CORE_ADDR |
108 | sparc_address_from_register (int regnum) | |
109 | { | |
110 | ULONGEST addr; | |
c906108c | 111 | |
386c036b MK |
112 | regcache_cooked_read_unsigned (current_regcache, regnum, &addr); |
113 | return addr; | |
114 | } | |
115 | \f | |
c906108c | 116 | |
386c036b MK |
117 | /* The functions on this page are intended to be used to classify |
118 | function arguments. */ | |
c906108c | 119 | |
386c036b | 120 | /* Check whether TYPE is "Integral or Pointer". */ |
c906108c | 121 | |
386c036b MK |
122 | static int |
123 | sparc_integral_or_pointer_p (const struct type *type) | |
c906108c | 124 | { |
386c036b | 125 | switch (TYPE_CODE (type)) |
c906108c | 126 | { |
386c036b MK |
127 | case TYPE_CODE_INT: |
128 | case TYPE_CODE_BOOL: | |
129 | case TYPE_CODE_CHAR: | |
130 | case TYPE_CODE_ENUM: | |
131 | case TYPE_CODE_RANGE: | |
132 | { | |
133 | /* We have byte, half-word, word and extended-word/doubleword | |
134 | integral types. The doubleword is an extension to the | |
135 | origional 32-bit ABI by the SCD 2.4.x. */ | |
136 | int len = TYPE_LENGTH (type); | |
137 | return (len == 1 || len == 2 || len == 4 || len == 8); | |
138 | } | |
139 | return 1; | |
140 | case TYPE_CODE_PTR: | |
141 | case TYPE_CODE_REF: | |
142 | { | |
143 | /* Allow either 32-bit or 64-bit pointers. */ | |
144 | int len = TYPE_LENGTH (type); | |
145 | return (len == 4 || len == 8); | |
146 | } | |
147 | return 1; | |
148 | default: | |
149 | break; | |
150 | } | |
c906108c | 151 | |
386c036b MK |
152 | return 0; |
153 | } | |
c906108c | 154 | |
386c036b | 155 | /* Check whether TYPE is "Floating". */ |
c906108c | 156 | |
386c036b MK |
157 | static int |
158 | sparc_floating_p (const struct type *type) | |
159 | { | |
160 | switch (TYPE_CODE (type)) | |
c906108c | 161 | { |
386c036b MK |
162 | case TYPE_CODE_FLT: |
163 | { | |
164 | int len = TYPE_LENGTH (type); | |
165 | return (len == 4 || len == 8 || len == 16); | |
166 | } | |
167 | default: | |
168 | break; | |
169 | } | |
170 | ||
171 | return 0; | |
172 | } | |
c906108c | 173 | |
386c036b | 174 | /* Check whether TYPE is "Structure or Union". */ |
c906108c | 175 | |
386c036b MK |
176 | static int |
177 | sparc_structure_or_union_p (const struct type *type) | |
178 | { | |
179 | switch (TYPE_CODE (type)) | |
180 | { | |
181 | case TYPE_CODE_STRUCT: | |
182 | case TYPE_CODE_UNION: | |
183 | return 1; | |
184 | default: | |
185 | break; | |
c906108c | 186 | } |
386c036b MK |
187 | |
188 | return 0; | |
c906108c | 189 | } |
386c036b MK |
190 | |
191 | /* Register information. */ | |
192 | ||
193 | static const char *sparc32_register_names[] = | |
5af923b0 | 194 | { |
386c036b MK |
195 | "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
196 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", | |
197 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", | |
198 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", | |
199 | ||
200 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
201 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
202 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
203 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
204 | ||
205 | "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" | |
5af923b0 MS |
206 | }; |
207 | ||
386c036b MK |
208 | /* Total number of registers. */ |
209 | #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) | |
c906108c | 210 | |
386c036b MK |
211 | /* We provide the aliases %d0..%d30 for the floating registers as |
212 | "psuedo" registers. */ | |
213 | ||
214 | static const char *sparc32_pseudo_register_names[] = | |
215 | { | |
216 | "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", | |
217 | "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" | |
218 | }; | |
219 | ||
220 | /* Total number of pseudo registers. */ | |
221 | #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) | |
222 | ||
223 | /* Return the name of register REGNUM. */ | |
224 | ||
225 | static const char * | |
226 | sparc32_register_name (int regnum) | |
227 | { | |
228 | if (regnum >= 0 && regnum < SPARC32_NUM_REGS) | |
229 | return sparc32_register_names[regnum]; | |
230 | ||
231 | if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS) | |
232 | return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS]; | |
233 | ||
234 | return NULL; | |
235 | } | |
236 | ||
237 | /* Return the GDB type object for the "standard" data type of data in | |
238 | register REGNUM. */ | |
239 | ||
240 | static struct type * | |
241 | sparc32_register_type (struct gdbarch *gdbarch, int regnum) | |
242 | { | |
243 | if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) | |
244 | return builtin_type_float; | |
245 | ||
246 | if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) | |
247 | return builtin_type_double; | |
248 | ||
249 | if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) | |
250 | return builtin_type_void_data_ptr; | |
251 | ||
252 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) | |
253 | return builtin_type_void_func_ptr; | |
254 | ||
255 | return builtin_type_int32; | |
256 | } | |
257 | ||
258 | static void | |
259 | sparc32_pseudo_register_read (struct gdbarch *gdbarch, | |
260 | struct regcache *regcache, | |
261 | int regnum, void *buf) | |
262 | { | |
263 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); | |
264 | ||
265 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
266 | regcache_raw_read (regcache, regnum, buf); | |
267 | regcache_raw_read (regcache, regnum + 1, ((char *)buf) + 4); | |
268 | } | |
269 | ||
270 | static void | |
271 | sparc32_pseudo_register_write (struct gdbarch *gdbarch, | |
272 | struct regcache *regcache, | |
273 | int regnum, const void *buf) | |
274 | { | |
275 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); | |
276 | ||
277 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
278 | regcache_raw_write (regcache, regnum, buf); | |
279 | regcache_raw_write (regcache, regnum + 1, ((const char *)buf) + 4); | |
280 | } | |
281 | \f | |
282 | ||
283 | static CORE_ADDR | |
284 | sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
285 | CORE_ADDR funcaddr, int using_gcc, | |
286 | struct value **args, int nargs, | |
287 | struct type *value_type, | |
288 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr) | |
c906108c | 289 | { |
386c036b MK |
290 | *bp_addr = sp - 4; |
291 | *real_pc = funcaddr; | |
292 | ||
293 | if (using_struct_return (value_type, using_gcc)) | |
c906108c | 294 | { |
386c036b MK |
295 | char buf[4]; |
296 | ||
297 | /* This is an UNIMP instruction. */ | |
298 | store_unsigned_integer (buf, 4, TYPE_LENGTH (value_type) & 0x1fff); | |
299 | write_memory (sp - 8, buf, 4); | |
300 | return sp - 8; | |
c906108c SS |
301 | } |
302 | ||
386c036b MK |
303 | return sp - 4; |
304 | } | |
305 | ||
306 | static CORE_ADDR | |
307 | sparc32_store_arguments (struct regcache *regcache, int nargs, | |
308 | struct value **args, CORE_ADDR sp, | |
309 | int struct_return, CORE_ADDR struct_addr) | |
310 | { | |
311 | /* Number of words in the "parameter array". */ | |
312 | int num_elements = 0; | |
313 | int element = 0; | |
314 | int i; | |
315 | ||
316 | for (i = 0; i < nargs; i++) | |
c906108c | 317 | { |
386c036b MK |
318 | struct type *type = VALUE_TYPE (args[i]); |
319 | int len = TYPE_LENGTH (type); | |
320 | ||
321 | if (sparc_structure_or_union_p (type) | |
322 | || (sparc_floating_p (type) && len == 16)) | |
c906108c | 323 | { |
386c036b MK |
324 | /* Structure, Union and Quad-Precision Arguments. */ |
325 | sp -= len; | |
326 | ||
327 | /* Use doubleword alignment for these values. That's always | |
328 | correct, and wasting a few bytes shouldn't be a problem. */ | |
329 | sp &= ~0x7; | |
330 | ||
331 | write_memory (sp, VALUE_CONTENTS (args[i]), len); | |
332 | args[i] = value_from_pointer (lookup_pointer_type (type), sp); | |
333 | num_elements++; | |
334 | } | |
335 | else if (sparc_floating_p (type)) | |
336 | { | |
337 | /* Floating arguments. */ | |
338 | gdb_assert (len == 4 || len == 8); | |
339 | num_elements += (len / 4); | |
c906108c | 340 | } |
c5aa993b JM |
341 | else |
342 | { | |
386c036b MK |
343 | /* Integral and pointer arguments. */ |
344 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
345 | ||
346 | if (len < 4) | |
347 | args[i] = value_cast (builtin_type_int32, args[i]); | |
348 | num_elements += ((len + 3) / 4); | |
c5aa993b | 349 | } |
c906108c | 350 | } |
c906108c | 351 | |
386c036b MK |
352 | /* Always allocate at least six words. */ |
353 | sp -= max (6, num_elements) * 4; | |
c906108c | 354 | |
386c036b MK |
355 | /* The psABI says that "Software convention requires space for the |
356 | struct/union return value pointer, even if the word is unused." */ | |
357 | sp -= 4; | |
c906108c | 358 | |
386c036b MK |
359 | /* The psABI says that "Although software convention and the |
360 | operating system require every stack frame to be doubleword | |
361 | aligned." */ | |
362 | sp &= ~0x7; | |
c906108c | 363 | |
386c036b | 364 | for (i = 0; i < nargs; i++) |
c906108c | 365 | { |
386c036b MK |
366 | char *valbuf = VALUE_CONTENTS (args[i]); |
367 | struct type *type = VALUE_TYPE (args[i]); | |
368 | int len = TYPE_LENGTH (type); | |
c906108c | 369 | |
386c036b | 370 | gdb_assert (len == 4 || len == 8); |
c906108c | 371 | |
386c036b MK |
372 | if (element < 6) |
373 | { | |
374 | int regnum = SPARC_O0_REGNUM + element; | |
c906108c | 375 | |
386c036b MK |
376 | regcache_cooked_write (regcache, regnum, valbuf); |
377 | if (len > 4 && element < 5) | |
378 | regcache_cooked_write (regcache, regnum + 1, valbuf + 4); | |
379 | } | |
5af923b0 | 380 | |
386c036b MK |
381 | /* Always store the argument in memory. */ |
382 | write_memory (sp + 4 + element * 4, valbuf, len); | |
383 | element += len / 4; | |
384 | } | |
c906108c | 385 | |
386c036b | 386 | gdb_assert (element == num_elements); |
c906108c | 387 | |
386c036b | 388 | if (struct_return) |
c906108c | 389 | { |
386c036b | 390 | char buf[4]; |
c906108c | 391 | |
386c036b MK |
392 | store_unsigned_integer (buf, 4, struct_addr); |
393 | write_memory (sp, buf, 4); | |
394 | } | |
c906108c | 395 | |
386c036b | 396 | return sp; |
c906108c SS |
397 | } |
398 | ||
386c036b MK |
399 | static CORE_ADDR |
400 | sparc32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, | |
401 | struct regcache *regcache, CORE_ADDR bp_addr, | |
402 | int nargs, struct value **args, CORE_ADDR sp, | |
403 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 404 | { |
386c036b MK |
405 | CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8)); |
406 | ||
407 | /* Set return address. */ | |
408 | regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); | |
409 | ||
410 | /* Set up function arguments. */ | |
411 | sp = sparc32_store_arguments (regcache, nargs, args, sp, | |
412 | struct_return, struct_addr); | |
413 | ||
414 | /* Allocate the 16-word window save area. */ | |
415 | sp -= 16 * 4; | |
c906108c | 416 | |
386c036b MK |
417 | /* Stack should be doubleword aligned at this point. */ |
418 | gdb_assert (sp % 8 == 0); | |
c906108c | 419 | |
386c036b MK |
420 | /* Finally, update the stack pointer. */ |
421 | regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); | |
422 | ||
423 | return sp; | |
424 | } | |
425 | \f | |
c906108c | 426 | |
386c036b MK |
427 | /* Use the program counter to determine the contents and size of a |
428 | breakpoint instruction. Return a pointer to a string of bytes that | |
429 | encode a breakpoint instruction, store the length of the string in | |
430 | *LEN and optionally adjust *PC to point to the correct memory | |
431 | location for inserting the breakpoint. */ | |
432 | ||
433 | static const unsigned char * | |
434 | sparc_breakpoint_from_pc (CORE_ADDR *pc, int *len) | |
435 | { | |
436 | static unsigned char break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; | |
c5aa993b | 437 | |
386c036b MK |
438 | *len = sizeof (break_insn); |
439 | return break_insn; | |
c906108c | 440 | } |
386c036b | 441 | \f |
c906108c | 442 | |
386c036b | 443 | /* Allocate and initialize a frame cache. */ |
c906108c | 444 | |
386c036b MK |
445 | static struct sparc_frame_cache * |
446 | sparc_alloc_frame_cache (void) | |
447 | { | |
448 | struct sparc_frame_cache *cache; | |
449 | int i; | |
c906108c | 450 | |
386c036b | 451 | cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); |
c906108c | 452 | |
386c036b MK |
453 | /* Base address. */ |
454 | cache->base = 0; | |
455 | cache->pc = 0; | |
c906108c | 456 | |
386c036b MK |
457 | /* Frameless until proven otherwise. */ |
458 | cache->frameless_p = 1; | |
459 | ||
460 | cache->struct_return_p = 0; | |
461 | ||
462 | return cache; | |
463 | } | |
464 | ||
465 | CORE_ADDR | |
466 | sparc_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, | |
467 | struct sparc_frame_cache *cache) | |
c906108c | 468 | { |
386c036b MK |
469 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
470 | unsigned long insn; | |
471 | int offset = 0; | |
c906108c | 472 | int dest = -1; |
c906108c | 473 | |
386c036b MK |
474 | if (current_pc <= pc) |
475 | return current_pc; | |
476 | ||
477 | /* We have to handle to "Procedure Linkage Table" (PLT) special. On | |
478 | SPARC the linker usually defines a symbol (typically | |
479 | _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. | |
480 | This symbol makes us end up here with PC pointing at the start of | |
481 | the PLT and CURRENT_PC probably pointing at a PLT entry. If we | |
482 | would do our normal prologue analysis, we would probably conclude | |
483 | that we've got a frame when in reality we don't, since the | |
484 | dynamic linker patches up the first PLT with some code that | |
485 | starts with a SAVE instruction. Patch up PC such that it points | |
486 | at the start of our PLT entry. */ | |
487 | if (tdep->plt_entry_size > 0 && in_plt_section (current_pc, NULL)) | |
488 | pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); | |
c906108c | 489 | |
386c036b MK |
490 | insn = sparc_fetch_instruction (pc); |
491 | ||
492 | /* Recognize a SETHI insn and record its destination. */ | |
493 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) | |
c906108c SS |
494 | { |
495 | dest = X_RD (insn); | |
386c036b MK |
496 | offset += 4; |
497 | ||
498 | insn = sparc_fetch_instruction (pc + 4); | |
c906108c SS |
499 | } |
500 | ||
386c036b MK |
501 | /* Allow for an arithmetic operation on DEST or %g1. */ |
502 | if (X_OP (insn) == 2 && X_I (insn) | |
c906108c SS |
503 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) |
504 | { | |
386c036b | 505 | offset += 4; |
c906108c | 506 | |
386c036b | 507 | insn = sparc_fetch_instruction (pc + 8); |
c906108c | 508 | } |
c906108c | 509 | |
386c036b MK |
510 | /* Check for the SAVE instruction that sets up the frame. */ |
511 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) | |
c906108c | 512 | { |
386c036b MK |
513 | cache->frameless_p = 0; |
514 | return pc + offset + 4; | |
c906108c SS |
515 | } |
516 | ||
517 | return pc; | |
518 | } | |
519 | ||
386c036b MK |
520 | static CORE_ADDR |
521 | sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
522 | { | |
523 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
524 | return frame_unwind_register_unsigned (next_frame, tdep->pc_regnum); | |
525 | } | |
526 | ||
527 | /* Return PC of first real instruction of the function starting at | |
528 | START_PC. */ | |
f510d44e | 529 | |
386c036b MK |
530 | static CORE_ADDR |
531 | sparc32_skip_prologue (CORE_ADDR start_pc) | |
c906108c | 532 | { |
f510d44e DM |
533 | struct symtab_and_line sal; |
534 | CORE_ADDR func_start, func_end; | |
386c036b | 535 | struct sparc_frame_cache cache; |
f510d44e DM |
536 | |
537 | /* This is the preferred method, find the end of the prologue by | |
538 | using the debugging information. */ | |
539 | if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) | |
540 | { | |
541 | sal = find_pc_line (func_start, 0); | |
542 | ||
543 | if (sal.end < func_end | |
544 | && start_pc <= sal.end) | |
545 | return sal.end; | |
546 | } | |
547 | ||
386c036b | 548 | return sparc_analyze_prologue (start_pc, 0xffffffffUL, &cache); |
c906108c SS |
549 | } |
550 | ||
386c036b | 551 | /* Normal frames. */ |
9319a2fe | 552 | |
386c036b MK |
553 | struct sparc_frame_cache * |
554 | sparc_frame_cache (struct frame_info *next_frame, void **this_cache) | |
9319a2fe | 555 | { |
386c036b | 556 | struct sparc_frame_cache *cache; |
9319a2fe | 557 | |
386c036b MK |
558 | if (*this_cache) |
559 | return *this_cache; | |
c906108c | 560 | |
386c036b MK |
561 | cache = sparc_alloc_frame_cache (); |
562 | *this_cache = cache; | |
c906108c | 563 | |
386c036b MK |
564 | /* In priciple, for normal frames, %fp (%i6) holds the frame |
565 | pointer, which holds the base address for the current stack | |
566 | frame. */ | |
567 | ||
568 | cache->base = frame_unwind_register_unsigned (next_frame, SPARC_FP_REGNUM); | |
569 | if (cache->base == 0) | |
570 | return cache; | |
571 | ||
572 | cache->pc = frame_func_unwind (next_frame); | |
573 | if (cache->pc != 0) | |
c906108c | 574 | { |
386c036b MK |
575 | CORE_ADDR addr_in_block = frame_unwind_address_in_block (next_frame); |
576 | sparc_analyze_prologue (cache->pc, addr_in_block, cache); | |
c906108c | 577 | } |
386c036b MK |
578 | |
579 | if (cache->frameless_p) | |
c906108c | 580 | { |
386c036b MK |
581 | /* We didn't find a valid frame, which means that CACHE->base |
582 | currently holds the frame pointer for our calling frame. */ | |
583 | cache->base = frame_unwind_register_unsigned (next_frame, | |
584 | SPARC_SP_REGNUM); | |
c906108c | 585 | } |
c906108c | 586 | |
386c036b | 587 | return cache; |
c906108c | 588 | } |
c906108c | 589 | |
386c036b MK |
590 | struct sparc_frame_cache * |
591 | sparc32_frame_cache (struct frame_info *next_frame, void **this_cache) | |
c906108c | 592 | { |
386c036b MK |
593 | struct sparc_frame_cache *cache; |
594 | struct symbol *sym; | |
c906108c | 595 | |
386c036b MK |
596 | if (*this_cache) |
597 | return *this_cache; | |
c906108c | 598 | |
386c036b | 599 | cache = sparc_frame_cache (next_frame, this_cache); |
c906108c | 600 | |
386c036b MK |
601 | sym = find_pc_function (cache->pc); |
602 | if (sym) | |
c906108c | 603 | { |
386c036b MK |
604 | struct type *type = check_typedef (SYMBOL_TYPE (sym)); |
605 | enum type_code code = TYPE_CODE (type); | |
606 | ||
607 | if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) | |
608 | { | |
609 | type = check_typedef (TYPE_TARGET_TYPE (type)); | |
610 | if (sparc_structure_or_union_p (type) | |
611 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
612 | cache->struct_return_p = 1; | |
613 | } | |
c906108c SS |
614 | } |
615 | ||
386c036b MK |
616 | return cache; |
617 | } | |
618 | ||
619 | static void | |
620 | sparc32_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
621 | struct frame_id *this_id) | |
622 | { | |
623 | struct sparc_frame_cache *cache = | |
624 | sparc32_frame_cache (next_frame, this_cache); | |
625 | ||
626 | /* This marks the outermost frame. */ | |
627 | if (cache->base == 0) | |
628 | return; | |
629 | ||
630 | (*this_id) = frame_id_build (cache->base, cache->pc); | |
631 | } | |
c906108c | 632 | |
386c036b MK |
633 | static void |
634 | sparc32_frame_prev_register (struct frame_info *next_frame, void **this_cache, | |
635 | int regnum, int *optimizedp, | |
636 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
637 | int *realnump, void *valuep) | |
638 | { | |
639 | struct sparc_frame_cache *cache = | |
640 | sparc32_frame_cache (next_frame, this_cache); | |
c906108c | 641 | |
386c036b | 642 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) |
c906108c | 643 | { |
386c036b MK |
644 | *optimizedp = 0; |
645 | *lvalp = not_lval; | |
646 | *addrp = 0; | |
647 | *realnump = -1; | |
648 | if (valuep) | |
c906108c | 649 | { |
386c036b MK |
650 | CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; |
651 | ||
652 | /* If this functions has a Structure, Union or | |
653 | Quad-Precision return value, we have to skip the UNIMP | |
654 | instruction that encodes the size of the structure. */ | |
655 | if (cache->struct_return_p) | |
656 | pc += 4; | |
657 | ||
658 | regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM; | |
659 | pc += frame_unwind_register_unsigned (next_frame, regnum) + 8; | |
660 | store_unsigned_integer (valuep, 4, pc); | |
c906108c | 661 | } |
c906108c SS |
662 | return; |
663 | } | |
664 | ||
386c036b MK |
665 | /* The previous frame's `local' and `in' registers have been saved |
666 | in the register save area. */ | |
667 | if (!cache->frameless_p | |
668 | && regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) | |
c906108c | 669 | { |
386c036b MK |
670 | *optimizedp = 0; |
671 | *lvalp = lval_memory; | |
672 | *addrp = cache->base + (regnum - SPARC_L0_REGNUM) * 4; | |
673 | *realnump = -1; | |
674 | if (valuep) | |
c906108c | 675 | { |
386c036b MK |
676 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
677 | ||
678 | /* Read the value in from memory. */ | |
679 | read_memory (*addrp, valuep, register_size (gdbarch, regnum)); | |
c906108c | 680 | } |
386c036b MK |
681 | return; |
682 | } | |
c906108c | 683 | |
386c036b MK |
684 | /* The previous frame's `out' registers are accessable as the |
685 | current frame's `in' registers. */ | |
686 | if (!cache->frameless_p | |
687 | && regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM) | |
688 | regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); | |
5af923b0 | 689 | |
386c036b MK |
690 | frame_register_unwind (next_frame, regnum, |
691 | optimizedp, lvalp, addrp, realnump, valuep); | |
692 | } | |
c906108c | 693 | |
386c036b MK |
694 | static const struct frame_unwind sparc32_frame_unwind = |
695 | { | |
696 | NORMAL_FRAME, | |
697 | sparc32_frame_this_id, | |
698 | sparc32_frame_prev_register | |
699 | }; | |
700 | ||
701 | static const struct frame_unwind * | |
702 | sparc32_frame_sniffer (struct frame_info *next_frame) | |
703 | { | |
704 | return &sparc32_frame_unwind; | |
c906108c | 705 | } |
386c036b | 706 | \f |
c906108c | 707 | |
386c036b MK |
708 | static CORE_ADDR |
709 | sparc32_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
710 | { | |
711 | struct sparc_frame_cache *cache = | |
712 | sparc32_frame_cache (next_frame, this_cache); | |
c906108c | 713 | |
386c036b MK |
714 | return cache->base; |
715 | } | |
c906108c | 716 | |
386c036b MK |
717 | static const struct frame_base sparc32_frame_base = |
718 | { | |
719 | &sparc32_frame_unwind, | |
720 | sparc32_frame_base_address, | |
721 | sparc32_frame_base_address, | |
722 | sparc32_frame_base_address | |
723 | }; | |
c906108c | 724 | |
386c036b MK |
725 | static struct frame_id |
726 | sparc_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
727 | { | |
728 | CORE_ADDR sp; | |
5af923b0 | 729 | |
386c036b MK |
730 | sp = frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM); |
731 | return frame_id_build (sp, frame_pc_unwind (next_frame)); | |
732 | } | |
733 | \f | |
c906108c | 734 | |
386c036b MK |
735 | /* Extract from an array REGBUF containing the (raw) register state, a |
736 | function return value of TYPE, and copy that into VALBUF. */ | |
5af923b0 | 737 | |
386c036b MK |
738 | static void |
739 | sparc32_extract_return_value (struct type *type, struct regcache *regcache, | |
740 | void *valbuf) | |
741 | { | |
742 | int len = TYPE_LENGTH (type); | |
743 | char buf[8]; | |
c906108c | 744 | |
386c036b MK |
745 | gdb_assert (!sparc_structure_or_union_p (type)); |
746 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 747 | |
386c036b | 748 | if (sparc_floating_p (type)) |
5af923b0 | 749 | { |
386c036b MK |
750 | /* Floating return values. */ |
751 | regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf); | |
752 | if (len > 4) | |
753 | regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4); | |
754 | memcpy (valbuf, buf, len); | |
5af923b0 MS |
755 | } |
756 | else | |
757 | { | |
386c036b MK |
758 | /* Integral and pointer return values. */ |
759 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
c906108c | 760 | |
386c036b MK |
761 | regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); |
762 | if (len > 4) | |
763 | { | |
764 | regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4); | |
765 | gdb_assert (len == 8); | |
766 | memcpy (valbuf, buf, 8); | |
767 | } | |
768 | else | |
769 | { | |
770 | /* Just stripping off any unused bytes should preserve the | |
771 | signed-ness just fine. */ | |
772 | memcpy (valbuf, buf + 4 - len, len); | |
773 | } | |
774 | } | |
775 | } | |
c906108c | 776 | |
386c036b MK |
777 | /* Write into the appropriate registers a function return value stored |
778 | in VALBUF of type TYPE. */ | |
c906108c | 779 | |
386c036b MK |
780 | static void |
781 | sparc32_store_return_value (struct type *type, struct regcache *regcache, | |
782 | const void *valbuf) | |
783 | { | |
784 | int len = TYPE_LENGTH (type); | |
785 | char buf[8]; | |
c906108c | 786 | |
386c036b MK |
787 | gdb_assert (!sparc_structure_or_union_p (type)); |
788 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 789 | |
386c036b MK |
790 | if (sparc_floating_p (type)) |
791 | { | |
792 | /* Floating return values. */ | |
793 | memcpy (buf, valbuf, len); | |
794 | regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf); | |
795 | if (len > 4) | |
796 | regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4); | |
797 | } | |
798 | else | |
c906108c | 799 | { |
386c036b MK |
800 | /* Integral and pointer return values. */ |
801 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
802 | ||
803 | if (len > 4) | |
2757dd86 | 804 | { |
386c036b MK |
805 | gdb_assert (len == 8); |
806 | memcpy (buf, valbuf, 8); | |
807 | regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4); | |
2757dd86 AC |
808 | } |
809 | else | |
810 | { | |
386c036b MK |
811 | /* ??? Do we need to do any sign-extension here? */ |
812 | memcpy (buf + 4 - len, valbuf, len); | |
2757dd86 | 813 | } |
386c036b | 814 | regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); |
c906108c SS |
815 | } |
816 | } | |
817 | ||
b9d4c5ed MK |
818 | static enum return_value_convention |
819 | sparc32_return_value (struct gdbarch *gdbarch, struct type *type, | |
820 | struct regcache *regcache, void *readbuf, | |
821 | const void *writebuf) | |
822 | { | |
823 | if (sparc_structure_or_union_p (type) | |
824 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
825 | return RETURN_VALUE_STRUCT_CONVENTION; | |
826 | ||
827 | if (readbuf) | |
828 | sparc32_extract_return_value (type, regcache, readbuf); | |
829 | if (writebuf) | |
830 | sparc32_store_return_value (type, regcache, writebuf); | |
831 | ||
832 | return RETURN_VALUE_REGISTER_CONVENTION; | |
833 | } | |
834 | ||
386c036b MK |
835 | /* Extract from REGCACHE, which contains the (raw) register state, the |
836 | address in which a function should return its structure value, as a | |
837 | CORE_ADDR. */ | |
c906108c | 838 | |
386c036b MK |
839 | static CORE_ADDR |
840 | sparc_extract_struct_value_address (struct regcache *regcache) | |
841 | { | |
9515395e | 842 | ULONGEST sp; |
c906108c | 843 | |
9515395e MK |
844 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); |
845 | return read_memory_unsigned_integer (sp + 64, 4); | |
386c036b | 846 | } |
c906108c | 847 | |
386c036b MK |
848 | static int |
849 | sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) | |
c906108c | 850 | { |
386c036b MK |
851 | return (sparc_structure_or_union_p (type) |
852 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)); | |
853 | } | |
c906108c | 854 | |
386c036b MK |
855 | \f |
856 | /* The SPARC Architecture doesn't have hardware single-step support, | |
857 | and most operating systems don't implement it either, so we provide | |
858 | software single-step mechanism. */ | |
c906108c | 859 | |
386c036b MK |
860 | static CORE_ADDR |
861 | sparc_analyze_control_transfer (CORE_ADDR pc, CORE_ADDR *npc) | |
862 | { | |
863 | unsigned long insn = sparc_fetch_instruction (pc); | |
864 | int conditional_p = X_COND (insn) & 0x7; | |
865 | int branch_p = 0; | |
866 | long offset = 0; /* Must be signed for sign-extend. */ | |
c906108c | 867 | |
386c036b | 868 | if (X_OP (insn) == 0 && X_OP2 (insn) == 3 && (insn & 0x1000000) == 0) |
c906108c | 869 | { |
386c036b MK |
870 | /* Branch on Integer Register with Prediction (BPr). */ |
871 | branch_p = 1; | |
872 | conditional_p = 1; | |
c906108c | 873 | } |
386c036b | 874 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) |
c906108c | 875 | { |
386c036b MK |
876 | /* Branch on Floating-Point Condition Codes (FBfcc). */ |
877 | branch_p = 1; | |
878 | offset = 4 * X_DISP22 (insn); | |
c906108c | 879 | } |
386c036b MK |
880 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) |
881 | { | |
882 | /* Branch on Floating-Point Condition Codes with Prediction | |
883 | (FBPfcc). */ | |
884 | branch_p = 1; | |
885 | offset = 4 * X_DISP19 (insn); | |
886 | } | |
887 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) | |
888 | { | |
889 | /* Branch on Integer Condition Codes (Bicc). */ | |
890 | branch_p = 1; | |
891 | offset = 4 * X_DISP22 (insn); | |
892 | } | |
893 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) | |
c906108c | 894 | { |
386c036b MK |
895 | /* Branch on Integer Condition Codes with Prediction (BPcc). */ |
896 | branch_p = 1; | |
897 | offset = 4 * X_DISP19 (insn); | |
c906108c | 898 | } |
386c036b MK |
899 | |
900 | /* FIXME: Handle DONE and RETRY instructions. */ | |
901 | ||
902 | /* FIXME: Handle the Trap instruction. */ | |
903 | ||
904 | if (branch_p) | |
c906108c | 905 | { |
386c036b | 906 | if (conditional_p) |
c906108c | 907 | { |
386c036b MK |
908 | /* For conditional branches, return nPC + 4 iff the annul |
909 | bit is 1. */ | |
910 | return (X_A (insn) ? *npc + 4 : 0); | |
c906108c SS |
911 | } |
912 | else | |
913 | { | |
386c036b MK |
914 | /* For unconditional branches, return the target if its |
915 | specified condition is "always" and return nPC + 4 if the | |
916 | condition is "never". If the annul bit is 1, set *NPC to | |
917 | zero. */ | |
918 | if (X_COND (insn) == 0x0) | |
919 | pc = *npc, offset = 4; | |
920 | if (X_A (insn)) | |
921 | *npc = 0; | |
922 | ||
923 | gdb_assert (offset != 0); | |
924 | return pc + offset; | |
c906108c SS |
925 | } |
926 | } | |
386c036b MK |
927 | |
928 | return 0; | |
c906108c SS |
929 | } |
930 | ||
386c036b MK |
931 | void |
932 | sparc_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
933 | { | |
934 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
935 | static CORE_ADDR npc, nnpc; | |
936 | static char npc_save[4], nnpc_save[4]; | |
c906108c | 937 | |
386c036b MK |
938 | if (insert_breakpoints_p) |
939 | { | |
940 | CORE_ADDR pc; | |
c906108c | 941 | |
386c036b MK |
942 | pc = sparc_address_from_register (tdep->pc_regnum); |
943 | npc = sparc_address_from_register (tdep->npc_regnum); | |
c906108c | 944 | |
386c036b MK |
945 | /* Analyze the instruction at PC. */ |
946 | nnpc = sparc_analyze_control_transfer (pc, &npc); | |
947 | if (npc != 0) | |
948 | target_insert_breakpoint (npc, npc_save); | |
949 | if (nnpc != 0) | |
950 | target_insert_breakpoint (nnpc, nnpc_save); | |
c906108c | 951 | |
386c036b MK |
952 | /* Assert that we have set at least one breakpoint, and that |
953 | they're not set at the same spot. */ | |
954 | gdb_assert (npc != 0 || nnpc != 0); | |
955 | gdb_assert (nnpc != npc); | |
60054393 | 956 | } |
386c036b | 957 | else |
c906108c | 958 | { |
386c036b MK |
959 | if (npc != 0) |
960 | target_remove_breakpoint (npc, npc_save); | |
961 | if (nnpc != 0) | |
962 | target_remove_breakpoint (nnpc, nnpc_save); | |
c906108c | 963 | } |
386c036b MK |
964 | } |
965 | ||
966 | static void | |
967 | sparc_write_pc (CORE_ADDR pc, ptid_t ptid) | |
968 | { | |
969 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
970 | ||
971 | write_register_pid (tdep->pc_regnum, pc, ptid); | |
972 | write_register_pid (tdep->npc_regnum, pc + 4, ptid); | |
973 | } | |
974 | \f | |
975 | /* Unglobalize NAME. */ | |
976 | ||
977 | char * | |
978 | sparc_stabs_unglobalize_name (char *name) | |
979 | { | |
980 | /* The Sun compilers (Sun ONE Studio, Forte Developer, Sun WorkShop, | |
981 | SunPRO) convert file static variables into global values, a | |
982 | process known as globalization. In order to do this, the | |
983 | compiler will create a unique prefix and prepend it to each file | |
984 | static variable. For static variables within a function, this | |
985 | globalization prefix is followed by the function name (nested | |
986 | static variables within a function are supposed to generate a | |
987 | warning message, and are left alone). The procedure is | |
988 | documented in the Stabs Interface Manual, which is distrubuted | |
989 | with the compilers, although version 4.0 of the manual seems to | |
990 | be incorrect in some places, at least for SPARC. The | |
991 | globalization prefix is encoded into an N_OPT stab, with the form | |
992 | "G=<prefix>". The globalization prefix always seems to start | |
993 | with a dollar sign '$'; a dot '.' is used as a seperator. So we | |
994 | simply strip everything up until the last dot. */ | |
c906108c | 995 | |
386c036b | 996 | if (name[0] == '$') |
c906108c | 997 | { |
386c036b MK |
998 | char *p = strrchr (name, '.'); |
999 | if (p) | |
1000 | return p + 1; | |
c906108c | 1001 | } |
c906108c | 1002 | |
386c036b MK |
1003 | return name; |
1004 | } | |
1005 | \f | |
5af923b0 | 1006 | |
386c036b MK |
1007 | static struct gdbarch * |
1008 | sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1009 | { | |
1010 | struct gdbarch_tdep *tdep; | |
1011 | struct gdbarch *gdbarch; | |
c906108c | 1012 | |
386c036b MK |
1013 | /* If there is already a candidate, use it. */ |
1014 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1015 | if (arches != NULL) | |
1016 | return arches->gdbarch; | |
c906108c | 1017 | |
386c036b MK |
1018 | /* Allocate space for the new architecture. */ |
1019 | tdep = XMALLOC (struct gdbarch_tdep); | |
1020 | gdbarch = gdbarch_alloc (&info, tdep); | |
5af923b0 | 1021 | |
386c036b MK |
1022 | tdep->pc_regnum = SPARC32_PC_REGNUM; |
1023 | tdep->npc_regnum = SPARC32_NPC_REGNUM; | |
1024 | tdep->plt_entry_size = 0; | |
1025 | ||
1026 | set_gdbarch_long_double_bit (gdbarch, 128); | |
1027 | set_gdbarch_long_double_format (gdbarch, &floatformat_sparc_quad); | |
1028 | ||
1029 | set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); | |
1030 | set_gdbarch_register_name (gdbarch, sparc32_register_name); | |
1031 | set_gdbarch_register_type (gdbarch, sparc32_register_type); | |
1032 | set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); | |
1033 | set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); | |
1034 | set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); | |
1035 | ||
1036 | /* Register numbers of various important registers. */ | |
1037 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ | |
1038 | set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ | |
1039 | set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ | |
1040 | ||
1041 | /* Call dummy code. */ | |
1042 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); | |
1043 | set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); | |
1044 | set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); | |
1045 | ||
b9d4c5ed | 1046 | set_gdbarch_return_value (gdbarch, sparc32_return_value); |
386c036b MK |
1047 | set_gdbarch_stabs_argument_has_addr |
1048 | (gdbarch, sparc32_stabs_argument_has_addr); | |
1049 | ||
1050 | set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); | |
1051 | ||
1052 | /* Stack grows downward. */ | |
1053 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
c906108c | 1054 | |
386c036b MK |
1055 | set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc); |
1056 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
1057 | set_gdbarch_function_start_offset (gdbarch, 0); | |
c906108c | 1058 | |
386c036b | 1059 | set_gdbarch_frame_args_skip (gdbarch, 8); |
5af923b0 | 1060 | |
386c036b | 1061 | set_gdbarch_print_insn (gdbarch, print_insn_sparc); |
c906108c | 1062 | |
386c036b MK |
1063 | set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); |
1064 | set_gdbarch_write_pc (gdbarch, sparc_write_pc); | |
c906108c | 1065 | |
386c036b | 1066 | set_gdbarch_unwind_dummy_id (gdbarch, sparc_unwind_dummy_id); |
c906108c | 1067 | |
386c036b | 1068 | set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc); |
c906108c | 1069 | |
386c036b MK |
1070 | frame_base_set_default (gdbarch, &sparc32_frame_base); |
1071 | ||
1072 | /* Hook in ABI-specific overrides, if they have been registered. */ | |
1073 | gdbarch_init_osabi (info, gdbarch); | |
c906108c | 1074 | |
386c036b | 1075 | frame_unwind_append_sniffer (gdbarch, sparc32_frame_sniffer); |
c906108c | 1076 | |
386c036b MK |
1077 | return gdbarch; |
1078 | } | |
1079 | \f | |
1080 | /* Helper functions for dealing with register windows. */ | |
1081 | ||
1082 | void | |
1083 | sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) | |
c906108c | 1084 | { |
386c036b MK |
1085 | int offset = 0; |
1086 | char buf[8]; | |
1087 | int i; | |
1088 | ||
1089 | if (sp & 1) | |
1090 | { | |
1091 | /* Registers are 64-bit. */ | |
1092 | sp += BIAS; | |
c906108c | 1093 | |
386c036b MK |
1094 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1095 | { | |
1096 | if (regnum == i || regnum == -1) | |
1097 | { | |
1098 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); | |
1099 | regcache_raw_supply (regcache, i, buf); | |
1100 | } | |
1101 | } | |
1102 | } | |
1103 | else | |
c906108c | 1104 | { |
386c036b MK |
1105 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1106 | pointer. */ | |
1107 | sp &= 0xffffffffUL; | |
c906108c | 1108 | |
386c036b MK |
1109 | /* Clear out the top half of the temporary buffer, and put the |
1110 | register value in the bottom half if we're in 64-bit mode. */ | |
1111 | if (gdbarch_ptr_bit (current_gdbarch) == 64) | |
c906108c | 1112 | { |
386c036b MK |
1113 | memset (buf, 0, 4); |
1114 | offset = 4; | |
1115 | } | |
c906108c | 1116 | |
386c036b MK |
1117 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1118 | { | |
1119 | if (regnum == i || regnum == -1) | |
1120 | { | |
1121 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), | |
1122 | buf + offset, 4); | |
1123 | regcache_raw_supply (regcache, i, buf); | |
1124 | } | |
c906108c SS |
1125 | } |
1126 | } | |
c906108c | 1127 | } |
c906108c SS |
1128 | |
1129 | void | |
386c036b MK |
1130 | sparc_collect_rwindow (const struct regcache *regcache, |
1131 | CORE_ADDR sp, int regnum) | |
c906108c | 1132 | { |
386c036b MK |
1133 | int offset = 0; |
1134 | char buf[8]; | |
1135 | int i; | |
5af923b0 | 1136 | |
386c036b | 1137 | if (sp & 1) |
5af923b0 | 1138 | { |
386c036b MK |
1139 | /* Registers are 64-bit. */ |
1140 | sp += BIAS; | |
c906108c | 1141 | |
386c036b MK |
1142 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1143 | { | |
1144 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1145 | { | |
1146 | regcache_raw_collect (regcache, i, buf); | |
1147 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); | |
1148 | } | |
1149 | } | |
5af923b0 MS |
1150 | } |
1151 | else | |
1152 | { | |
386c036b MK |
1153 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1154 | pointer. */ | |
1155 | sp &= 0xffffffffUL; | |
1156 | ||
1157 | /* Only use the bottom half if we're in 64-bit mode. */ | |
1158 | if (gdbarch_ptr_bit (current_gdbarch) == 64) | |
1159 | offset = 4; | |
1160 | ||
1161 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1162 | { | |
1163 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1164 | { | |
1165 | regcache_raw_collect (regcache, i, buf); | |
1166 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), | |
1167 | buf + offset, 4); | |
1168 | } | |
1169 | } | |
5af923b0 | 1170 | } |
c906108c SS |
1171 | } |
1172 | ||
386c036b MK |
1173 | /* Helper functions for dealing with register sets. */ |
1174 | ||
c906108c | 1175 | void |
386c036b MK |
1176 | sparc32_supply_gregset (const struct sparc_gregset *gregset, |
1177 | struct regcache *regcache, | |
1178 | int regnum, const void *gregs) | |
c906108c | 1179 | { |
386c036b MK |
1180 | const char *regs = gregs; |
1181 | int i; | |
5af923b0 | 1182 | |
386c036b MK |
1183 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1184 | regcache_raw_supply (regcache, SPARC32_PSR_REGNUM, | |
1185 | regs + gregset->r_psr_offset); | |
c906108c | 1186 | |
386c036b MK |
1187 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1188 | regcache_raw_supply (regcache, SPARC32_PC_REGNUM, | |
1189 | regs + gregset->r_pc_offset); | |
5af923b0 | 1190 | |
386c036b MK |
1191 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) |
1192 | regcache_raw_supply (regcache, SPARC32_NPC_REGNUM, | |
1193 | regs + gregset->r_npc_offset); | |
5af923b0 | 1194 | |
386c036b MK |
1195 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1196 | regcache_raw_supply (regcache, SPARC32_Y_REGNUM, | |
1197 | regs + gregset->r_y_offset); | |
5af923b0 | 1198 | |
386c036b MK |
1199 | if (regnum == SPARC_G0_REGNUM || regnum == -1) |
1200 | regcache_raw_supply (regcache, SPARC_G0_REGNUM, NULL); | |
5af923b0 | 1201 | |
386c036b | 1202 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) |
c906108c | 1203 | { |
386c036b MK |
1204 | int offset = gregset->r_g1_offset; |
1205 | ||
1206 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1207 | { | |
1208 | if (regnum == i || regnum == -1) | |
1209 | regcache_raw_supply (regcache, i, regs + offset); | |
1210 | offset += 4; | |
1211 | } | |
c906108c | 1212 | } |
386c036b MK |
1213 | |
1214 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
c906108c | 1215 | { |
386c036b MK |
1216 | /* Not all of the register set variants include Locals and |
1217 | Inputs. For those that don't, we read them off the stack. */ | |
1218 | if (gregset->r_l0_offset == -1) | |
1219 | { | |
1220 | ULONGEST sp; | |
1221 | ||
1222 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1223 | sparc_supply_rwindow (regcache, sp, regnum); | |
1224 | } | |
1225 | else | |
1226 | { | |
1227 | int offset = gregset->r_l0_offset; | |
1228 | ||
1229 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1230 | { | |
1231 | if (regnum == i || regnum == -1) | |
1232 | regcache_raw_supply (regcache, i, regs + offset); | |
1233 | offset += 4; | |
1234 | } | |
1235 | } | |
c906108c SS |
1236 | } |
1237 | } | |
1238 | ||
c5aa993b | 1239 | void |
386c036b MK |
1240 | sparc32_collect_gregset (const struct sparc_gregset *gregset, |
1241 | const struct regcache *regcache, | |
1242 | int regnum, void *gregs) | |
c906108c | 1243 | { |
386c036b MK |
1244 | char *regs = gregs; |
1245 | int i; | |
c5aa993b | 1246 | |
386c036b MK |
1247 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1248 | regcache_raw_collect (regcache, SPARC32_PSR_REGNUM, | |
1249 | regs + gregset->r_psr_offset); | |
60054393 | 1250 | |
386c036b MK |
1251 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1252 | regcache_raw_collect (regcache, SPARC32_PC_REGNUM, | |
1253 | regs + gregset->r_pc_offset); | |
1254 | ||
1255 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) | |
1256 | regcache_raw_collect (regcache, SPARC32_NPC_REGNUM, | |
1257 | regs + gregset->r_npc_offset); | |
5af923b0 | 1258 | |
386c036b MK |
1259 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1260 | regcache_raw_collect (regcache, SPARC32_Y_REGNUM, | |
1261 | regs + gregset->r_y_offset); | |
1262 | ||
1263 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) | |
5af923b0 | 1264 | { |
386c036b MK |
1265 | int offset = gregset->r_g1_offset; |
1266 | ||
1267 | /* %g0 is always zero. */ | |
1268 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1269 | { | |
1270 | if (regnum == i || regnum == -1) | |
1271 | regcache_raw_collect (regcache, i, regs + offset); | |
1272 | offset += 4; | |
1273 | } | |
5af923b0 | 1274 | } |
386c036b MK |
1275 | |
1276 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
5af923b0 | 1277 | { |
386c036b MK |
1278 | /* Not all of the register set variants include Locals and |
1279 | Inputs. For those that don't, we read them off the stack. */ | |
1280 | if (gregset->r_l0_offset != -1) | |
1281 | { | |
1282 | int offset = gregset->r_l0_offset; | |
1283 | ||
1284 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1285 | { | |
1286 | if (regnum == i || regnum == -1) | |
1287 | regcache_raw_collect (regcache, i, regs + offset); | |
1288 | offset += 4; | |
1289 | } | |
1290 | } | |
5af923b0 | 1291 | } |
c906108c SS |
1292 | } |
1293 | ||
c906108c | 1294 | void |
386c036b MK |
1295 | sparc32_supply_fpregset (struct regcache *regcache, |
1296 | int regnum, const void *fpregs) | |
c906108c | 1297 | { |
386c036b MK |
1298 | const char *regs = fpregs; |
1299 | int i; | |
60054393 | 1300 | |
386c036b | 1301 | for (i = 0; i < 32; i++) |
c906108c | 1302 | { |
386c036b MK |
1303 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) |
1304 | regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, regs + (i * 4)); | |
c906108c | 1305 | } |
5af923b0 | 1306 | |
386c036b MK |
1307 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
1308 | regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4); | |
c906108c SS |
1309 | } |
1310 | ||
386c036b MK |
1311 | void |
1312 | sparc32_collect_fpregset (const struct regcache *regcache, | |
1313 | int regnum, void *fpregs) | |
c906108c | 1314 | { |
386c036b MK |
1315 | char *regs = fpregs; |
1316 | int i; | |
c906108c | 1317 | |
386c036b MK |
1318 | for (i = 0; i < 32; i++) |
1319 | { | |
1320 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) | |
1321 | regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, regs + (i * 4)); | |
1322 | } | |
c906108c | 1323 | |
386c036b MK |
1324 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
1325 | regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4); | |
c906108c | 1326 | } |
c906108c | 1327 | \f |
c906108c | 1328 | |
386c036b | 1329 | /* SunOS 4. */ |
c906108c | 1330 | |
386c036b MK |
1331 | /* From <machine/reg.h>. */ |
1332 | const struct sparc_gregset sparc32_sunos4_gregset = | |
c906108c | 1333 | { |
386c036b MK |
1334 | 0 * 4, /* %psr */ |
1335 | 1 * 4, /* %pc */ | |
1336 | 2 * 4, /* %npc */ | |
1337 | 3 * 4, /* %y */ | |
1338 | -1, /* %wim */ | |
1339 | -1, /* %tbr */ | |
1340 | 4 * 4, /* %g1 */ | |
1341 | -1 /* %l0 */ | |
1342 | }; | |
1343 | \f | |
c906108c | 1344 | |
386c036b MK |
1345 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
1346 | void _initialize_sparc_tdep (void); | |
c906108c SS |
1347 | |
1348 | void | |
386c036b | 1349 | _initialize_sparc_tdep (void) |
c906108c | 1350 | { |
386c036b | 1351 | register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init); |
ef3cf062 | 1352 | } |