Commit | Line | Data |
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386c036b | 1 | /* Target-dependent code for SPARC. |
cda5a58a | 2 | |
28e7fd62 | 3 | Copyright (C) 2003-2013 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 19 | |
c906108c | 20 | #include "defs.h" |
5af923b0 | 21 | #include "arch-utils.h" |
386c036b | 22 | #include "dis-asm.h" |
f5a9b87d | 23 | #include "dwarf2-frame.h" |
386c036b | 24 | #include "floatformat.h" |
c906108c | 25 | #include "frame.h" |
386c036b MK |
26 | #include "frame-base.h" |
27 | #include "frame-unwind.h" | |
28 | #include "gdbcore.h" | |
29 | #include "gdbtypes.h" | |
c906108c | 30 | #include "inferior.h" |
386c036b MK |
31 | #include "symtab.h" |
32 | #include "objfiles.h" | |
33 | #include "osabi.h" | |
34 | #include "regcache.h" | |
c906108c SS |
35 | #include "target.h" |
36 | #include "value.h" | |
c906108c | 37 | |
43bd9a9e | 38 | #include "gdb_assert.h" |
0e9f083f | 39 | #include <string.h> |
c906108c | 40 | |
386c036b | 41 | #include "sparc-tdep.h" |
e6f9c00b | 42 | #include "sparc-ravenscar-thread.h" |
c906108c | 43 | |
a54124c5 MK |
44 | struct regset; |
45 | ||
9eb42ed1 MK |
46 | /* This file implements the SPARC 32-bit ABI as defined by the section |
47 | "Low-Level System Information" of the SPARC Compliance Definition | |
48 | (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD | |
f2e7c15d | 49 | lists changes with respect to the original 32-bit psABI as defined |
9eb42ed1 | 50 | in the "System V ABI, SPARC Processor Supplement". |
386c036b MK |
51 | |
52 | Note that if we talk about SunOS, we mean SunOS 4.x, which was | |
53 | BSD-based, which is sometimes (retroactively?) referred to as | |
54 | Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and | |
55 | above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 | |
56 | suffering from severe version number inflation). Solaris 2.x is | |
57 | also known as SunOS 5.x, since that's what uname(1) says. Solaris | |
58 | 2.x is SVR4-based. */ | |
59 | ||
60 | /* Please use the sparc32_-prefix for 32-bit specific code, the | |
61 | sparc64_-prefix for 64-bit specific code and the sparc_-prefix for | |
62 | code that can handle both. The 64-bit specific code lives in | |
63 | sparc64-tdep.c; don't add any here. */ | |
64 | ||
65 | /* The SPARC Floating-Point Quad-Precision format is similar to | |
7a58cce8 | 66 | big-endian IA-64 Quad-Precision format. */ |
8da61cc4 | 67 | #define floatformats_sparc_quad floatformats_ia64_quad |
386c036b MK |
68 | |
69 | /* The stack pointer is offset from the stack frame by a BIAS of 2047 | |
70 | (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC | |
71 | hosts, so undefine it first. */ | |
72 | #undef BIAS | |
73 | #define BIAS 2047 | |
74 | ||
75 | /* Macros to extract fields from SPARC instructions. */ | |
c906108c SS |
76 | #define X_OP(i) (((i) >> 30) & 0x3) |
77 | #define X_RD(i) (((i) >> 25) & 0x1f) | |
78 | #define X_A(i) (((i) >> 29) & 1) | |
79 | #define X_COND(i) (((i) >> 25) & 0xf) | |
80 | #define X_OP2(i) (((i) >> 22) & 0x7) | |
81 | #define X_IMM22(i) ((i) & 0x3fffff) | |
82 | #define X_OP3(i) (((i) >> 19) & 0x3f) | |
075ccec8 | 83 | #define X_RS1(i) (((i) >> 14) & 0x1f) |
b0b92586 | 84 | #define X_RS2(i) ((i) & 0x1f) |
c906108c | 85 | #define X_I(i) (((i) >> 13) & 1) |
c906108c | 86 | /* Sign extension macros. */ |
c906108c | 87 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) |
c906108c | 88 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) |
8d1b3521 | 89 | #define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200) |
075ccec8 | 90 | #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000) |
c906108c | 91 | |
386c036b MK |
92 | /* Fetch the instruction at PC. Instructions are always big-endian |
93 | even if the processor operates in little-endian mode. */ | |
94 | ||
95 | unsigned long | |
96 | sparc_fetch_instruction (CORE_ADDR pc) | |
c906108c | 97 | { |
e1613aba | 98 | gdb_byte buf[4]; |
386c036b MK |
99 | unsigned long insn; |
100 | int i; | |
101 | ||
690668cc | 102 | /* If we can't read the instruction at PC, return zero. */ |
8defab1a | 103 | if (target_read_memory (pc, buf, sizeof (buf))) |
690668cc | 104 | return 0; |
c906108c | 105 | |
386c036b MK |
106 | insn = 0; |
107 | for (i = 0; i < sizeof (buf); i++) | |
108 | insn = (insn << 8) | buf[i]; | |
109 | return insn; | |
110 | } | |
42cdca6c MK |
111 | \f |
112 | ||
5465445a JB |
113 | /* Return non-zero if the instruction corresponding to PC is an "unimp" |
114 | instruction. */ | |
115 | ||
116 | static int | |
117 | sparc_is_unimp_insn (CORE_ADDR pc) | |
118 | { | |
119 | const unsigned long insn = sparc_fetch_instruction (pc); | |
120 | ||
121 | return ((insn & 0xc1c00000) == 0); | |
122 | } | |
123 | ||
d0b5971a JM |
124 | /* Return non-zero if the instruction corresponding to PC is an |
125 | "annulled" branch, i.e. the annul bit is set. */ | |
126 | ||
127 | int | |
128 | sparc_is_annulled_branch_insn (CORE_ADDR pc) | |
129 | { | |
130 | /* The branch instructions featuring an annul bit can be identified | |
131 | by the following bit patterns: | |
132 | ||
133 | OP=0 | |
134 | OP2=1: Branch on Integer Condition Codes with Prediction (BPcc). | |
135 | OP2=2: Branch on Integer Condition Codes (Bcc). | |
136 | OP2=5: Branch on FP Condition Codes with Prediction (FBfcc). | |
137 | OP2=6: Branch on FP Condition Codes (FBcc). | |
138 | OP2=3 && Bit28=0: | |
139 | Branch on Integer Register with Prediction (BPr). | |
140 | ||
141 | This leaves out ILLTRAP (OP2=0), SETHI/NOP (OP2=4) and the V8 | |
142 | coprocessor branch instructions (Op2=7). */ | |
143 | ||
144 | const unsigned long insn = sparc_fetch_instruction (pc); | |
145 | const unsigned op2 = X_OP2 (insn); | |
146 | ||
147 | if ((X_OP (insn) == 0) | |
148 | && ((op2 == 1) || (op2 == 2) || (op2 == 5) || (op2 == 6) | |
149 | || ((op2 == 3) && ((insn & 0x10000000) == 0)))) | |
150 | return X_A (insn); | |
151 | else | |
152 | return 0; | |
153 | } | |
154 | ||
42cdca6c MK |
155 | /* OpenBSD/sparc includes StackGhost, which according to the author's |
156 | website http://stackghost.cerias.purdue.edu "... transparently and | |
157 | automatically protects applications' stack frames; more | |
158 | specifically, it guards the return pointers. The protection | |
159 | mechanisms require no application source or binary modification and | |
160 | imposes only a negligible performance penalty." | |
161 | ||
162 | The same website provides the following description of how | |
163 | StackGhost works: | |
164 | ||
165 | "StackGhost interfaces with the kernel trap handler that would | |
166 | normally write out registers to the stack and the handler that | |
167 | would read them back in. By XORing a cookie into the | |
168 | return-address saved in the user stack when it is actually written | |
169 | to the stack, and then XOR it out when the return-address is pulled | |
170 | from the stack, StackGhost can cause attacker corrupted return | |
171 | pointers to behave in a manner the attacker cannot predict. | |
172 | StackGhost can also use several unused bits in the return pointer | |
173 | to detect a smashed return pointer and abort the process." | |
174 | ||
175 | For GDB this means that whenever we're reading %i7 from a stack | |
176 | frame's window save area, we'll have to XOR the cookie. | |
177 | ||
178 | More information on StackGuard can be found on in: | |
179 | ||
c378eb4e | 180 | Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated |
42cdca6c MK |
181 | Stack Protection." 2001. Published in USENIX Security Symposium |
182 | '01. */ | |
183 | ||
184 | /* Fetch StackGhost Per-Process XOR cookie. */ | |
185 | ||
186 | ULONGEST | |
e17a4113 | 187 | sparc_fetch_wcookie (struct gdbarch *gdbarch) |
42cdca6c | 188 | { |
e17a4113 | 189 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
baf92889 | 190 | struct target_ops *ops = ¤t_target; |
e1613aba | 191 | gdb_byte buf[8]; |
baf92889 MK |
192 | int len; |
193 | ||
13547ab6 | 194 | len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8); |
baf92889 MK |
195 | if (len == -1) |
196 | return 0; | |
42cdca6c | 197 | |
baf92889 MK |
198 | /* We should have either an 32-bit or an 64-bit cookie. */ |
199 | gdb_assert (len == 4 || len == 8); | |
200 | ||
e17a4113 | 201 | return extract_unsigned_integer (buf, len, byte_order); |
baf92889 | 202 | } |
386c036b | 203 | \f |
baf92889 | 204 | |
386c036b MK |
205 | /* The functions on this page are intended to be used to classify |
206 | function arguments. */ | |
c906108c | 207 | |
386c036b | 208 | /* Check whether TYPE is "Integral or Pointer". */ |
c906108c | 209 | |
386c036b MK |
210 | static int |
211 | sparc_integral_or_pointer_p (const struct type *type) | |
c906108c | 212 | { |
80ad1639 MK |
213 | int len = TYPE_LENGTH (type); |
214 | ||
386c036b | 215 | switch (TYPE_CODE (type)) |
c906108c | 216 | { |
386c036b MK |
217 | case TYPE_CODE_INT: |
218 | case TYPE_CODE_BOOL: | |
219 | case TYPE_CODE_CHAR: | |
220 | case TYPE_CODE_ENUM: | |
221 | case TYPE_CODE_RANGE: | |
80ad1639 MK |
222 | /* We have byte, half-word, word and extended-word/doubleword |
223 | integral types. The doubleword is an extension to the | |
224 | original 32-bit ABI by the SCD 2.4.x. */ | |
225 | return (len == 1 || len == 2 || len == 4 || len == 8); | |
386c036b MK |
226 | case TYPE_CODE_PTR: |
227 | case TYPE_CODE_REF: | |
80ad1639 MK |
228 | /* Allow either 32-bit or 64-bit pointers. */ |
229 | return (len == 4 || len == 8); | |
386c036b MK |
230 | default: |
231 | break; | |
232 | } | |
c906108c | 233 | |
386c036b MK |
234 | return 0; |
235 | } | |
c906108c | 236 | |
386c036b | 237 | /* Check whether TYPE is "Floating". */ |
c906108c | 238 | |
386c036b MK |
239 | static int |
240 | sparc_floating_p (const struct type *type) | |
241 | { | |
242 | switch (TYPE_CODE (type)) | |
c906108c | 243 | { |
386c036b MK |
244 | case TYPE_CODE_FLT: |
245 | { | |
246 | int len = TYPE_LENGTH (type); | |
247 | return (len == 4 || len == 8 || len == 16); | |
248 | } | |
249 | default: | |
250 | break; | |
251 | } | |
252 | ||
253 | return 0; | |
254 | } | |
c906108c | 255 | |
fe10a582 DM |
256 | /* Check whether TYPE is "Complex Floating". */ |
257 | ||
258 | static int | |
259 | sparc_complex_floating_p (const struct type *type) | |
260 | { | |
261 | switch (TYPE_CODE (type)) | |
262 | { | |
263 | case TYPE_CODE_COMPLEX: | |
264 | { | |
265 | int len = TYPE_LENGTH (type); | |
266 | return (len == 8 || len == 16 || len == 32); | |
267 | } | |
268 | default: | |
269 | break; | |
270 | } | |
271 | ||
272 | return 0; | |
273 | } | |
274 | ||
0497f5b0 JB |
275 | /* Check whether TYPE is "Structure or Union". |
276 | ||
277 | In terms of Ada subprogram calls, arrays are treated the same as | |
278 | struct and union types. So this function also returns non-zero | |
279 | for array types. */ | |
c906108c | 280 | |
386c036b MK |
281 | static int |
282 | sparc_structure_or_union_p (const struct type *type) | |
283 | { | |
284 | switch (TYPE_CODE (type)) | |
285 | { | |
286 | case TYPE_CODE_STRUCT: | |
287 | case TYPE_CODE_UNION: | |
0497f5b0 | 288 | case TYPE_CODE_ARRAY: |
386c036b MK |
289 | return 1; |
290 | default: | |
291 | break; | |
c906108c | 292 | } |
386c036b MK |
293 | |
294 | return 0; | |
c906108c | 295 | } |
386c036b MK |
296 | |
297 | /* Register information. */ | |
298 | ||
299 | static const char *sparc32_register_names[] = | |
5af923b0 | 300 | { |
386c036b MK |
301 | "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
302 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", | |
303 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", | |
304 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", | |
305 | ||
306 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
307 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
308 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
309 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
310 | ||
311 | "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" | |
5af923b0 MS |
312 | }; |
313 | ||
386c036b MK |
314 | /* Total number of registers. */ |
315 | #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) | |
c906108c | 316 | |
386c036b MK |
317 | /* We provide the aliases %d0..%d30 for the floating registers as |
318 | "psuedo" registers. */ | |
319 | ||
320 | static const char *sparc32_pseudo_register_names[] = | |
321 | { | |
322 | "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", | |
323 | "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" | |
324 | }; | |
325 | ||
326 | /* Total number of pseudo registers. */ | |
327 | #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) | |
328 | ||
329 | /* Return the name of register REGNUM. */ | |
330 | ||
331 | static const char * | |
d93859e2 | 332 | sparc32_register_name (struct gdbarch *gdbarch, int regnum) |
386c036b MK |
333 | { |
334 | if (regnum >= 0 && regnum < SPARC32_NUM_REGS) | |
335 | return sparc32_register_names[regnum]; | |
336 | ||
337 | if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS) | |
338 | return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS]; | |
339 | ||
340 | return NULL; | |
341 | } | |
2d457077 | 342 | \f |
209bd28e | 343 | /* Construct types for ISA-specific registers. */ |
2d457077 | 344 | |
209bd28e UW |
345 | static struct type * |
346 | sparc_psr_type (struct gdbarch *gdbarch) | |
347 | { | |
348 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2d457077 | 349 | |
209bd28e UW |
350 | if (!tdep->sparc_psr_type) |
351 | { | |
352 | struct type *type; | |
2d457077 | 353 | |
e9bb382b | 354 | type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 4); |
209bd28e UW |
355 | append_flags_type_flag (type, 5, "ET"); |
356 | append_flags_type_flag (type, 6, "PS"); | |
357 | append_flags_type_flag (type, 7, "S"); | |
358 | append_flags_type_flag (type, 12, "EF"); | |
359 | append_flags_type_flag (type, 13, "EC"); | |
2d457077 | 360 | |
209bd28e UW |
361 | tdep->sparc_psr_type = type; |
362 | } | |
363 | ||
364 | return tdep->sparc_psr_type; | |
365 | } | |
366 | ||
367 | static struct type * | |
368 | sparc_fsr_type (struct gdbarch *gdbarch) | |
2d457077 | 369 | { |
209bd28e UW |
370 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
371 | ||
372 | if (!tdep->sparc_fsr_type) | |
373 | { | |
374 | struct type *type; | |
375 | ||
e9bb382b | 376 | type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 4); |
209bd28e UW |
377 | append_flags_type_flag (type, 0, "NXA"); |
378 | append_flags_type_flag (type, 1, "DZA"); | |
379 | append_flags_type_flag (type, 2, "UFA"); | |
380 | append_flags_type_flag (type, 3, "OFA"); | |
381 | append_flags_type_flag (type, 4, "NVA"); | |
382 | append_flags_type_flag (type, 5, "NXC"); | |
383 | append_flags_type_flag (type, 6, "DZC"); | |
384 | append_flags_type_flag (type, 7, "UFC"); | |
385 | append_flags_type_flag (type, 8, "OFC"); | |
386 | append_flags_type_flag (type, 9, "NVC"); | |
387 | append_flags_type_flag (type, 22, "NS"); | |
388 | append_flags_type_flag (type, 23, "NXM"); | |
389 | append_flags_type_flag (type, 24, "DZM"); | |
390 | append_flags_type_flag (type, 25, "UFM"); | |
391 | append_flags_type_flag (type, 26, "OFM"); | |
392 | append_flags_type_flag (type, 27, "NVM"); | |
393 | ||
394 | tdep->sparc_fsr_type = type; | |
395 | } | |
396 | ||
397 | return tdep->sparc_fsr_type; | |
2d457077 | 398 | } |
386c036b MK |
399 | |
400 | /* Return the GDB type object for the "standard" data type of data in | |
c378eb4e | 401 | register REGNUM. */ |
386c036b MK |
402 | |
403 | static struct type * | |
404 | sparc32_register_type (struct gdbarch *gdbarch, int regnum) | |
405 | { | |
406 | if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) | |
0dfff4cb | 407 | return builtin_type (gdbarch)->builtin_float; |
386c036b MK |
408 | |
409 | if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) | |
0dfff4cb | 410 | return builtin_type (gdbarch)->builtin_double; |
386c036b MK |
411 | |
412 | if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) | |
0dfff4cb | 413 | return builtin_type (gdbarch)->builtin_data_ptr; |
386c036b MK |
414 | |
415 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) | |
0dfff4cb | 416 | return builtin_type (gdbarch)->builtin_func_ptr; |
386c036b | 417 | |
2d457077 | 418 | if (regnum == SPARC32_PSR_REGNUM) |
209bd28e | 419 | return sparc_psr_type (gdbarch); |
2d457077 MK |
420 | |
421 | if (regnum == SPARC32_FSR_REGNUM) | |
209bd28e | 422 | return sparc_fsr_type (gdbarch); |
2d457077 | 423 | |
df4df182 | 424 | return builtin_type (gdbarch)->builtin_int32; |
386c036b MK |
425 | } |
426 | ||
05d1431c | 427 | static enum register_status |
386c036b MK |
428 | sparc32_pseudo_register_read (struct gdbarch *gdbarch, |
429 | struct regcache *regcache, | |
e1613aba | 430 | int regnum, gdb_byte *buf) |
386c036b | 431 | { |
05d1431c PA |
432 | enum register_status status; |
433 | ||
386c036b MK |
434 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); |
435 | ||
436 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
05d1431c PA |
437 | status = regcache_raw_read (regcache, regnum, buf); |
438 | if (status == REG_VALID) | |
439 | status = regcache_raw_read (regcache, regnum + 1, buf + 4); | |
440 | return status; | |
386c036b MK |
441 | } |
442 | ||
443 | static void | |
444 | sparc32_pseudo_register_write (struct gdbarch *gdbarch, | |
445 | struct regcache *regcache, | |
e1613aba | 446 | int regnum, const gdb_byte *buf) |
386c036b MK |
447 | { |
448 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); | |
449 | ||
450 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
451 | regcache_raw_write (regcache, regnum, buf); | |
e1613aba | 452 | regcache_raw_write (regcache, regnum + 1, buf + 4); |
386c036b MK |
453 | } |
454 | \f | |
455 | ||
49a45ecf JB |
456 | static CORE_ADDR |
457 | sparc32_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) | |
458 | { | |
459 | /* The ABI requires double-word alignment. */ | |
460 | return address & ~0x7; | |
461 | } | |
462 | ||
386c036b MK |
463 | static CORE_ADDR |
464 | sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
82585c72 | 465 | CORE_ADDR funcaddr, |
386c036b MK |
466 | struct value **args, int nargs, |
467 | struct type *value_type, | |
e4fd649a UW |
468 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, |
469 | struct regcache *regcache) | |
c906108c | 470 | { |
e17a4113 UW |
471 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
472 | ||
386c036b MK |
473 | *bp_addr = sp - 4; |
474 | *real_pc = funcaddr; | |
475 | ||
d80b854b | 476 | if (using_struct_return (gdbarch, NULL, value_type)) |
c906108c | 477 | { |
e1613aba | 478 | gdb_byte buf[4]; |
386c036b MK |
479 | |
480 | /* This is an UNIMP instruction. */ | |
e17a4113 UW |
481 | store_unsigned_integer (buf, 4, byte_order, |
482 | TYPE_LENGTH (value_type) & 0x1fff); | |
386c036b MK |
483 | write_memory (sp - 8, buf, 4); |
484 | return sp - 8; | |
c906108c SS |
485 | } |
486 | ||
386c036b MK |
487 | return sp - 4; |
488 | } | |
489 | ||
490 | static CORE_ADDR | |
491 | sparc32_store_arguments (struct regcache *regcache, int nargs, | |
492 | struct value **args, CORE_ADDR sp, | |
493 | int struct_return, CORE_ADDR struct_addr) | |
494 | { | |
df4df182 | 495 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
e17a4113 | 496 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
386c036b MK |
497 | /* Number of words in the "parameter array". */ |
498 | int num_elements = 0; | |
499 | int element = 0; | |
500 | int i; | |
501 | ||
502 | for (i = 0; i < nargs; i++) | |
c906108c | 503 | { |
4991999e | 504 | struct type *type = value_type (args[i]); |
386c036b MK |
505 | int len = TYPE_LENGTH (type); |
506 | ||
507 | if (sparc_structure_or_union_p (type) | |
fe10a582 DM |
508 | || (sparc_floating_p (type) && len == 16) |
509 | || sparc_complex_floating_p (type)) | |
c906108c | 510 | { |
386c036b MK |
511 | /* Structure, Union and Quad-Precision Arguments. */ |
512 | sp -= len; | |
513 | ||
514 | /* Use doubleword alignment for these values. That's always | |
515 | correct, and wasting a few bytes shouldn't be a problem. */ | |
516 | sp &= ~0x7; | |
517 | ||
0fd88904 | 518 | write_memory (sp, value_contents (args[i]), len); |
386c036b MK |
519 | args[i] = value_from_pointer (lookup_pointer_type (type), sp); |
520 | num_elements++; | |
521 | } | |
522 | else if (sparc_floating_p (type)) | |
523 | { | |
524 | /* Floating arguments. */ | |
525 | gdb_assert (len == 4 || len == 8); | |
526 | num_elements += (len / 4); | |
c906108c | 527 | } |
c5aa993b JM |
528 | else |
529 | { | |
386c036b MK |
530 | /* Integral and pointer arguments. */ |
531 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
532 | ||
533 | if (len < 4) | |
df4df182 UW |
534 | args[i] = value_cast (builtin_type (gdbarch)->builtin_int32, |
535 | args[i]); | |
386c036b | 536 | num_elements += ((len + 3) / 4); |
c5aa993b | 537 | } |
c906108c | 538 | } |
c906108c | 539 | |
386c036b MK |
540 | /* Always allocate at least six words. */ |
541 | sp -= max (6, num_elements) * 4; | |
c906108c | 542 | |
386c036b MK |
543 | /* The psABI says that "Software convention requires space for the |
544 | struct/union return value pointer, even if the word is unused." */ | |
545 | sp -= 4; | |
c906108c | 546 | |
386c036b MK |
547 | /* The psABI says that "Although software convention and the |
548 | operating system require every stack frame to be doubleword | |
549 | aligned." */ | |
550 | sp &= ~0x7; | |
c906108c | 551 | |
386c036b | 552 | for (i = 0; i < nargs; i++) |
c906108c | 553 | { |
0fd88904 | 554 | const bfd_byte *valbuf = value_contents (args[i]); |
4991999e | 555 | struct type *type = value_type (args[i]); |
386c036b | 556 | int len = TYPE_LENGTH (type); |
c906108c | 557 | |
386c036b | 558 | gdb_assert (len == 4 || len == 8); |
c906108c | 559 | |
386c036b MK |
560 | if (element < 6) |
561 | { | |
562 | int regnum = SPARC_O0_REGNUM + element; | |
c906108c | 563 | |
386c036b MK |
564 | regcache_cooked_write (regcache, regnum, valbuf); |
565 | if (len > 4 && element < 5) | |
566 | regcache_cooked_write (regcache, regnum + 1, valbuf + 4); | |
567 | } | |
5af923b0 | 568 | |
386c036b MK |
569 | /* Always store the argument in memory. */ |
570 | write_memory (sp + 4 + element * 4, valbuf, len); | |
571 | element += len / 4; | |
572 | } | |
c906108c | 573 | |
386c036b | 574 | gdb_assert (element == num_elements); |
c906108c | 575 | |
386c036b | 576 | if (struct_return) |
c906108c | 577 | { |
e1613aba | 578 | gdb_byte buf[4]; |
c906108c | 579 | |
e17a4113 | 580 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
386c036b MK |
581 | write_memory (sp, buf, 4); |
582 | } | |
c906108c | 583 | |
386c036b | 584 | return sp; |
c906108c SS |
585 | } |
586 | ||
386c036b | 587 | static CORE_ADDR |
7d9b040b | 588 | sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
386c036b MK |
589 | struct regcache *regcache, CORE_ADDR bp_addr, |
590 | int nargs, struct value **args, CORE_ADDR sp, | |
591 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 592 | { |
386c036b MK |
593 | CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8)); |
594 | ||
595 | /* Set return address. */ | |
596 | regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); | |
597 | ||
598 | /* Set up function arguments. */ | |
599 | sp = sparc32_store_arguments (regcache, nargs, args, sp, | |
600 | struct_return, struct_addr); | |
601 | ||
602 | /* Allocate the 16-word window save area. */ | |
603 | sp -= 16 * 4; | |
c906108c | 604 | |
386c036b MK |
605 | /* Stack should be doubleword aligned at this point. */ |
606 | gdb_assert (sp % 8 == 0); | |
c906108c | 607 | |
386c036b MK |
608 | /* Finally, update the stack pointer. */ |
609 | regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); | |
610 | ||
611 | return sp; | |
612 | } | |
613 | \f | |
c906108c | 614 | |
386c036b MK |
615 | /* Use the program counter to determine the contents and size of a |
616 | breakpoint instruction. Return a pointer to a string of bytes that | |
617 | encode a breakpoint instruction, store the length of the string in | |
618 | *LEN and optionally adjust *PC to point to the correct memory | |
619 | location for inserting the breakpoint. */ | |
620 | ||
e1613aba | 621 | static const gdb_byte * |
67d57894 | 622 | sparc_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
386c036b | 623 | { |
864a1a37 | 624 | static const gdb_byte break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; |
c5aa993b | 625 | |
386c036b MK |
626 | *len = sizeof (break_insn); |
627 | return break_insn; | |
c906108c | 628 | } |
386c036b | 629 | \f |
c906108c | 630 | |
386c036b | 631 | /* Allocate and initialize a frame cache. */ |
c906108c | 632 | |
386c036b MK |
633 | static struct sparc_frame_cache * |
634 | sparc_alloc_frame_cache (void) | |
635 | { | |
636 | struct sparc_frame_cache *cache; | |
c906108c | 637 | |
386c036b | 638 | cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); |
c906108c | 639 | |
386c036b MK |
640 | /* Base address. */ |
641 | cache->base = 0; | |
642 | cache->pc = 0; | |
c906108c | 643 | |
386c036b MK |
644 | /* Frameless until proven otherwise. */ |
645 | cache->frameless_p = 1; | |
369c397b JB |
646 | cache->frame_offset = 0; |
647 | cache->saved_regs_mask = 0; | |
648 | cache->copied_regs_mask = 0; | |
386c036b MK |
649 | cache->struct_return_p = 0; |
650 | ||
651 | return cache; | |
652 | } | |
653 | ||
b0b92586 JB |
654 | /* GCC generates several well-known sequences of instructions at the begining |
655 | of each function prologue when compiling with -fstack-check. If one of | |
656 | such sequences starts at START_PC, then return the address of the | |
657 | instruction immediately past this sequence. Otherwise, return START_PC. */ | |
658 | ||
659 | static CORE_ADDR | |
660 | sparc_skip_stack_check (const CORE_ADDR start_pc) | |
661 | { | |
662 | CORE_ADDR pc = start_pc; | |
663 | unsigned long insn; | |
664 | int offset_stack_checking_sequence = 0; | |
2067c8d4 | 665 | int probing_loop = 0; |
b0b92586 JB |
666 | |
667 | /* With GCC, all stack checking sequences begin with the same two | |
2067c8d4 | 668 | instructions, plus an optional one in the case of a probing loop: |
b0b92586 | 669 | |
2067c8d4 JG |
670 | sethi <some immediate>, %g1 |
671 | sub %sp, %g1, %g1 | |
672 | ||
673 | or: | |
674 | ||
675 | sethi <some immediate>, %g1 | |
676 | sethi <some immediate>, %g4 | |
677 | sub %sp, %g1, %g1 | |
678 | ||
679 | or: | |
680 | ||
681 | sethi <some immediate>, %g1 | |
682 | sub %sp, %g1, %g1 | |
683 | sethi <some immediate>, %g4 | |
684 | ||
685 | If the optional instruction is found (setting g4), assume that a | |
686 | probing loop will follow. */ | |
687 | ||
688 | /* sethi <some immediate>, %g1 */ | |
b0b92586 JB |
689 | insn = sparc_fetch_instruction (pc); |
690 | pc = pc + 4; | |
691 | if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1)) | |
692 | return start_pc; | |
693 | ||
2067c8d4 | 694 | /* optional: sethi <some immediate>, %g4 */ |
b0b92586 JB |
695 | insn = sparc_fetch_instruction (pc); |
696 | pc = pc + 4; | |
2067c8d4 JG |
697 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) |
698 | { | |
699 | probing_loop = 1; | |
700 | insn = sparc_fetch_instruction (pc); | |
701 | pc = pc + 4; | |
702 | } | |
703 | ||
704 | /* sub %sp, %g1, %g1 */ | |
b0b92586 JB |
705 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) |
706 | && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1)) | |
707 | return start_pc; | |
708 | ||
709 | insn = sparc_fetch_instruction (pc); | |
710 | pc = pc + 4; | |
711 | ||
2067c8d4 JG |
712 | /* optional: sethi <some immediate>, %g4 */ |
713 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) | |
714 | { | |
715 | probing_loop = 1; | |
716 | insn = sparc_fetch_instruction (pc); | |
717 | pc = pc + 4; | |
718 | } | |
719 | ||
b0b92586 JB |
720 | /* First possible sequence: |
721 | [first two instructions above] | |
722 | clr [%g1 - some immediate] */ | |
723 | ||
724 | /* clr [%g1 - some immediate] */ | |
725 | if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
726 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
727 | { | |
728 | /* Valid stack-check sequence, return the new PC. */ | |
729 | return pc; | |
730 | } | |
731 | ||
732 | /* Second possible sequence: A small number of probes. | |
733 | [first two instructions above] | |
734 | clr [%g1] | |
735 | add %g1, -<some immediate>, %g1 | |
736 | clr [%g1] | |
737 | [repeat the two instructions above any (small) number of times] | |
738 | clr [%g1 - some immediate] */ | |
739 | ||
740 | /* clr [%g1] */ | |
741 | else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
742 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
743 | { | |
744 | while (1) | |
745 | { | |
746 | /* add %g1, -<some immediate>, %g1 */ | |
747 | insn = sparc_fetch_instruction (pc); | |
748 | pc = pc + 4; | |
749 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
750 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
751 | break; | |
752 | ||
753 | /* clr [%g1] */ | |
754 | insn = sparc_fetch_instruction (pc); | |
755 | pc = pc + 4; | |
756 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
757 | && X_RD (insn) == 0 && X_RS1 (insn) == 1)) | |
758 | return start_pc; | |
759 | } | |
760 | ||
761 | /* clr [%g1 - some immediate] */ | |
762 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
763 | && X_RS1 (insn) == 1 && X_RD (insn) == 0)) | |
764 | return start_pc; | |
765 | ||
766 | /* We found a valid stack-check sequence, return the new PC. */ | |
767 | return pc; | |
768 | } | |
769 | ||
770 | /* Third sequence: A probing loop. | |
2067c8d4 | 771 | [first three instructions above] |
b0b92586 JB |
772 | sub %g1, %g4, %g4 |
773 | cmp %g1, %g4 | |
774 | be <disp> | |
775 | add %g1, -<some immediate>, %g1 | |
776 | ba <disp> | |
777 | clr [%g1] | |
2067c8d4 JG |
778 | |
779 | And an optional last probe for the remainder: | |
780 | ||
b0b92586 JB |
781 | clr [%g4 - some immediate] */ |
782 | ||
2067c8d4 | 783 | if (probing_loop) |
b0b92586 JB |
784 | { |
785 | /* sub %g1, %g4, %g4 */ | |
b0b92586 JB |
786 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) |
787 | && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
788 | return start_pc; | |
789 | ||
790 | /* cmp %g1, %g4 */ | |
791 | insn = sparc_fetch_instruction (pc); | |
792 | pc = pc + 4; | |
793 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn) | |
794 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
795 | return start_pc; | |
796 | ||
797 | /* be <disp> */ | |
798 | insn = sparc_fetch_instruction (pc); | |
799 | pc = pc + 4; | |
800 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1)) | |
801 | return start_pc; | |
802 | ||
803 | /* add %g1, -<some immediate>, %g1 */ | |
804 | insn = sparc_fetch_instruction (pc); | |
805 | pc = pc + 4; | |
806 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
807 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
808 | return start_pc; | |
809 | ||
810 | /* ba <disp> */ | |
811 | insn = sparc_fetch_instruction (pc); | |
812 | pc = pc + 4; | |
813 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8)) | |
814 | return start_pc; | |
815 | ||
2067c8d4 | 816 | /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */ |
b0b92586 JB |
817 | insn = sparc_fetch_instruction (pc); |
818 | pc = pc + 4; | |
2067c8d4 JG |
819 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 |
820 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 | |
821 | && (!X_I(insn) || X_SIMM13 (insn) == 0))) | |
b0b92586 JB |
822 | return start_pc; |
823 | ||
2067c8d4 JG |
824 | /* We found a valid stack-check sequence, return the new PC. */ |
825 | ||
826 | /* optional: clr [%g4 - some immediate] */ | |
b0b92586 JB |
827 | insn = sparc_fetch_instruction (pc); |
828 | pc = pc + 4; | |
829 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
830 | && X_RS1 (insn) == 4 && X_RD (insn) == 0)) | |
2067c8d4 JG |
831 | return pc - 4; |
832 | else | |
833 | return pc; | |
b0b92586 JB |
834 | } |
835 | ||
836 | /* No stack check code in our prologue, return the start_pc. */ | |
837 | return start_pc; | |
838 | } | |
839 | ||
369c397b JB |
840 | /* Record the effect of a SAVE instruction on CACHE. */ |
841 | ||
842 | void | |
843 | sparc_record_save_insn (struct sparc_frame_cache *cache) | |
844 | { | |
845 | /* The frame is set up. */ | |
846 | cache->frameless_p = 0; | |
847 | ||
848 | /* The frame pointer contains the CFA. */ | |
849 | cache->frame_offset = 0; | |
850 | ||
851 | /* The `local' and `in' registers are all saved. */ | |
852 | cache->saved_regs_mask = 0xffff; | |
853 | ||
854 | /* The `out' registers are all renamed. */ | |
855 | cache->copied_regs_mask = 0xff; | |
856 | } | |
857 | ||
858 | /* Do a full analysis of the prologue at PC and update CACHE accordingly. | |
859 | Bail out early if CURRENT_PC is reached. Return the address where | |
860 | the analysis stopped. | |
861 | ||
862 | We handle both the traditional register window model and the single | |
863 | register window (aka flat) model. */ | |
864 | ||
386c036b | 865 | CORE_ADDR |
be8626e0 MD |
866 | sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, |
867 | CORE_ADDR current_pc, struct sparc_frame_cache *cache) | |
c906108c | 868 | { |
be8626e0 | 869 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
386c036b MK |
870 | unsigned long insn; |
871 | int offset = 0; | |
c906108c | 872 | int dest = -1; |
c906108c | 873 | |
b0b92586 JB |
874 | pc = sparc_skip_stack_check (pc); |
875 | ||
386c036b MK |
876 | if (current_pc <= pc) |
877 | return current_pc; | |
878 | ||
879 | /* We have to handle to "Procedure Linkage Table" (PLT) special. On | |
880 | SPARC the linker usually defines a symbol (typically | |
881 | _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. | |
882 | This symbol makes us end up here with PC pointing at the start of | |
883 | the PLT and CURRENT_PC probably pointing at a PLT entry. If we | |
884 | would do our normal prologue analysis, we would probably conclude | |
885 | that we've got a frame when in reality we don't, since the | |
886 | dynamic linker patches up the first PLT with some code that | |
887 | starts with a SAVE instruction. Patch up PC such that it points | |
888 | at the start of our PLT entry. */ | |
3e5d3a5a | 889 | if (tdep->plt_entry_size > 0 && in_plt_section (current_pc)) |
386c036b | 890 | pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); |
c906108c | 891 | |
386c036b MK |
892 | insn = sparc_fetch_instruction (pc); |
893 | ||
369c397b JB |
894 | /* Recognize store insns and record their sources. */ |
895 | while (X_OP (insn) == 3 | |
896 | && (X_OP3 (insn) == 0x4 /* stw */ | |
897 | || X_OP3 (insn) == 0x7 /* std */ | |
898 | || X_OP3 (insn) == 0xe) /* stx */ | |
899 | && X_RS1 (insn) == SPARC_SP_REGNUM) | |
900 | { | |
901 | int regnum = X_RD (insn); | |
902 | ||
903 | /* Recognize stores into the corresponding stack slots. */ | |
904 | if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM | |
905 | && ((X_I (insn) | |
906 | && X_SIMM13 (insn) == (X_OP3 (insn) == 0xe | |
907 | ? (regnum - SPARC_L0_REGNUM) * 8 + BIAS | |
908 | : (regnum - SPARC_L0_REGNUM) * 4)) | |
909 | || (!X_I (insn) && regnum == SPARC_L0_REGNUM))) | |
910 | { | |
911 | cache->saved_regs_mask |= (1 << (regnum - SPARC_L0_REGNUM)); | |
912 | if (X_OP3 (insn) == 0x7) | |
913 | cache->saved_regs_mask |= (1 << (regnum + 1 - SPARC_L0_REGNUM)); | |
914 | } | |
915 | ||
916 | offset += 4; | |
917 | ||
918 | insn = sparc_fetch_instruction (pc + offset); | |
919 | } | |
920 | ||
386c036b MK |
921 | /* Recognize a SETHI insn and record its destination. */ |
922 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) | |
c906108c SS |
923 | { |
924 | dest = X_RD (insn); | |
386c036b MK |
925 | offset += 4; |
926 | ||
369c397b | 927 | insn = sparc_fetch_instruction (pc + offset); |
c906108c SS |
928 | } |
929 | ||
386c036b MK |
930 | /* Allow for an arithmetic operation on DEST or %g1. */ |
931 | if (X_OP (insn) == 2 && X_I (insn) | |
c906108c SS |
932 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) |
933 | { | |
386c036b | 934 | offset += 4; |
c906108c | 935 | |
369c397b | 936 | insn = sparc_fetch_instruction (pc + offset); |
c906108c | 937 | } |
c906108c | 938 | |
386c036b MK |
939 | /* Check for the SAVE instruction that sets up the frame. */ |
940 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) | |
c906108c | 941 | { |
369c397b JB |
942 | sparc_record_save_insn (cache); |
943 | offset += 4; | |
944 | return pc + offset; | |
945 | } | |
946 | ||
947 | /* Check for an arithmetic operation on %sp. */ | |
948 | if (X_OP (insn) == 2 | |
949 | && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) | |
950 | && X_RS1 (insn) == SPARC_SP_REGNUM | |
951 | && X_RD (insn) == SPARC_SP_REGNUM) | |
952 | { | |
953 | if (X_I (insn)) | |
954 | { | |
955 | cache->frame_offset = X_SIMM13 (insn); | |
956 | if (X_OP3 (insn) == 0) | |
957 | cache->frame_offset = -cache->frame_offset; | |
958 | } | |
959 | offset += 4; | |
960 | ||
961 | insn = sparc_fetch_instruction (pc + offset); | |
962 | ||
963 | /* Check for an arithmetic operation that sets up the frame. */ | |
964 | if (X_OP (insn) == 2 | |
965 | && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) | |
966 | && X_RS1 (insn) == SPARC_SP_REGNUM | |
967 | && X_RD (insn) == SPARC_FP_REGNUM) | |
968 | { | |
969 | cache->frameless_p = 0; | |
970 | cache->frame_offset = 0; | |
971 | /* We could check that the amount subtracted to %sp above is the | |
972 | same as the one added here, but this seems superfluous. */ | |
973 | cache->copied_regs_mask |= 0x40; | |
974 | offset += 4; | |
975 | ||
976 | insn = sparc_fetch_instruction (pc + offset); | |
977 | } | |
978 | ||
979 | /* Check for a move (or) operation that copies the return register. */ | |
980 | if (X_OP (insn) == 2 | |
981 | && X_OP3 (insn) == 0x2 | |
982 | && !X_I (insn) | |
983 | && X_RS1 (insn) == SPARC_G0_REGNUM | |
984 | && X_RS2 (insn) == SPARC_O7_REGNUM | |
985 | && X_RD (insn) == SPARC_I7_REGNUM) | |
986 | { | |
987 | cache->copied_regs_mask |= 0x80; | |
988 | offset += 4; | |
989 | } | |
990 | ||
991 | return pc + offset; | |
c906108c SS |
992 | } |
993 | ||
994 | return pc; | |
995 | } | |
996 | ||
386c036b | 997 | static CORE_ADDR |
236369e7 | 998 | sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) |
386c036b MK |
999 | { |
1000 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
236369e7 | 1001 | return frame_unwind_register_unsigned (this_frame, tdep->pc_regnum); |
386c036b MK |
1002 | } |
1003 | ||
1004 | /* Return PC of first real instruction of the function starting at | |
1005 | START_PC. */ | |
f510d44e | 1006 | |
386c036b | 1007 | static CORE_ADDR |
6093d2eb | 1008 | sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1009 | { |
f510d44e DM |
1010 | struct symtab_and_line sal; |
1011 | CORE_ADDR func_start, func_end; | |
386c036b | 1012 | struct sparc_frame_cache cache; |
f510d44e DM |
1013 | |
1014 | /* This is the preferred method, find the end of the prologue by | |
1015 | using the debugging information. */ | |
1016 | if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) | |
1017 | { | |
1018 | sal = find_pc_line (func_start, 0); | |
1019 | ||
1020 | if (sal.end < func_end | |
1021 | && start_pc <= sal.end) | |
1022 | return sal.end; | |
1023 | } | |
1024 | ||
be8626e0 | 1025 | start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache); |
075ccec8 MK |
1026 | |
1027 | /* The psABI says that "Although the first 6 words of arguments | |
1028 | reside in registers, the standard stack frame reserves space for | |
1029 | them.". It also suggests that a function may use that space to | |
1030 | "write incoming arguments 0 to 5" into that space, and that's | |
1031 | indeed what GCC seems to be doing. In that case GCC will | |
1032 | generate debug information that points to the stack slots instead | |
1033 | of the registers, so we should consider the instructions that | |
369c397b | 1034 | write out these incoming arguments onto the stack. */ |
075ccec8 | 1035 | |
369c397b | 1036 | while (1) |
075ccec8 MK |
1037 | { |
1038 | unsigned long insn = sparc_fetch_instruction (start_pc); | |
1039 | ||
369c397b JB |
1040 | /* Recognize instructions that store incoming arguments into the |
1041 | corresponding stack slots. */ | |
1042 | if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 | |
1043 | && X_I (insn) && X_RS1 (insn) == SPARC_FP_REGNUM) | |
075ccec8 | 1044 | { |
369c397b JB |
1045 | int regnum = X_RD (insn); |
1046 | ||
1047 | /* Case of arguments still in %o[0..5]. */ | |
1048 | if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O5_REGNUM | |
1049 | && !(cache.copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM))) | |
1050 | && X_SIMM13 (insn) == 68 + (regnum - SPARC_O0_REGNUM) * 4) | |
1051 | { | |
1052 | start_pc += 4; | |
1053 | continue; | |
1054 | } | |
1055 | ||
1056 | /* Case of arguments copied into %i[0..5]. */ | |
1057 | if (regnum >= SPARC_I0_REGNUM && regnum <= SPARC_I5_REGNUM | |
1058 | && (cache.copied_regs_mask & (1 << (regnum - SPARC_I0_REGNUM))) | |
1059 | && X_SIMM13 (insn) == 68 + (regnum - SPARC_I0_REGNUM) * 4) | |
1060 | { | |
1061 | start_pc += 4; | |
1062 | continue; | |
1063 | } | |
075ccec8 MK |
1064 | } |
1065 | ||
1066 | break; | |
1067 | } | |
1068 | ||
1069 | return start_pc; | |
c906108c SS |
1070 | } |
1071 | ||
386c036b | 1072 | /* Normal frames. */ |
9319a2fe | 1073 | |
386c036b | 1074 | struct sparc_frame_cache * |
236369e7 | 1075 | sparc_frame_cache (struct frame_info *this_frame, void **this_cache) |
9319a2fe | 1076 | { |
386c036b | 1077 | struct sparc_frame_cache *cache; |
9319a2fe | 1078 | |
386c036b MK |
1079 | if (*this_cache) |
1080 | return *this_cache; | |
c906108c | 1081 | |
386c036b MK |
1082 | cache = sparc_alloc_frame_cache (); |
1083 | *this_cache = cache; | |
c906108c | 1084 | |
236369e7 | 1085 | cache->pc = get_frame_func (this_frame); |
386c036b | 1086 | if (cache->pc != 0) |
236369e7 JB |
1087 | sparc_analyze_prologue (get_frame_arch (this_frame), cache->pc, |
1088 | get_frame_pc (this_frame), cache); | |
386c036b MK |
1089 | |
1090 | if (cache->frameless_p) | |
c906108c | 1091 | { |
cbeae229 MK |
1092 | /* This function is frameless, so %fp (%i6) holds the frame |
1093 | pointer for our calling frame. Use %sp (%o6) as this frame's | |
1094 | base address. */ | |
1095 | cache->base = | |
236369e7 | 1096 | get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
cbeae229 MK |
1097 | } |
1098 | else | |
1099 | { | |
1100 | /* For normal frames, %fp (%i6) holds the frame pointer, the | |
1101 | base address for the current stack frame. */ | |
1102 | cache->base = | |
236369e7 | 1103 | get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM); |
c906108c | 1104 | } |
c906108c | 1105 | |
369c397b JB |
1106 | cache->base += cache->frame_offset; |
1107 | ||
5b2d44a0 MK |
1108 | if (cache->base & 1) |
1109 | cache->base += BIAS; | |
1110 | ||
386c036b | 1111 | return cache; |
c906108c | 1112 | } |
c906108c | 1113 | |
aff37fc1 DM |
1114 | static int |
1115 | sparc32_struct_return_from_sym (struct symbol *sym) | |
1116 | { | |
1117 | struct type *type = check_typedef (SYMBOL_TYPE (sym)); | |
1118 | enum type_code code = TYPE_CODE (type); | |
1119 | ||
1120 | if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) | |
1121 | { | |
1122 | type = check_typedef (TYPE_TARGET_TYPE (type)); | |
1123 | if (sparc_structure_or_union_p (type) | |
1124 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
1125 | return 1; | |
1126 | } | |
1127 | ||
1128 | return 0; | |
1129 | } | |
1130 | ||
386c036b | 1131 | struct sparc_frame_cache * |
236369e7 | 1132 | sparc32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 1133 | { |
386c036b MK |
1134 | struct sparc_frame_cache *cache; |
1135 | struct symbol *sym; | |
c906108c | 1136 | |
386c036b MK |
1137 | if (*this_cache) |
1138 | return *this_cache; | |
c906108c | 1139 | |
236369e7 | 1140 | cache = sparc_frame_cache (this_frame, this_cache); |
c906108c | 1141 | |
386c036b MK |
1142 | sym = find_pc_function (cache->pc); |
1143 | if (sym) | |
c906108c | 1144 | { |
aff37fc1 | 1145 | cache->struct_return_p = sparc32_struct_return_from_sym (sym); |
c906108c | 1146 | } |
5465445a JB |
1147 | else |
1148 | { | |
1149 | /* There is no debugging information for this function to | |
1150 | help us determine whether this function returns a struct | |
1151 | or not. So we rely on another heuristic which is to check | |
1152 | the instruction at the return address and see if this is | |
1153 | an "unimp" instruction. If it is, then it is a struct-return | |
1154 | function. */ | |
1155 | CORE_ADDR pc; | |
369c397b JB |
1156 | int regnum = |
1157 | (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; | |
5465445a | 1158 | |
236369e7 | 1159 | pc = get_frame_register_unsigned (this_frame, regnum) + 8; |
5465445a JB |
1160 | if (sparc_is_unimp_insn (pc)) |
1161 | cache->struct_return_p = 1; | |
1162 | } | |
c906108c | 1163 | |
386c036b MK |
1164 | return cache; |
1165 | } | |
1166 | ||
1167 | static void | |
236369e7 | 1168 | sparc32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
386c036b MK |
1169 | struct frame_id *this_id) |
1170 | { | |
1171 | struct sparc_frame_cache *cache = | |
236369e7 | 1172 | sparc32_frame_cache (this_frame, this_cache); |
386c036b MK |
1173 | |
1174 | /* This marks the outermost frame. */ | |
1175 | if (cache->base == 0) | |
1176 | return; | |
1177 | ||
1178 | (*this_id) = frame_id_build (cache->base, cache->pc); | |
1179 | } | |
c906108c | 1180 | |
236369e7 JB |
1181 | static struct value * |
1182 | sparc32_frame_prev_register (struct frame_info *this_frame, | |
1183 | void **this_cache, int regnum) | |
386c036b | 1184 | { |
e17a4113 | 1185 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
386c036b | 1186 | struct sparc_frame_cache *cache = |
236369e7 | 1187 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 1188 | |
386c036b | 1189 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) |
c906108c | 1190 | { |
236369e7 | 1191 | CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; |
386c036b | 1192 | |
236369e7 JB |
1193 | /* If this functions has a Structure, Union or Quad-Precision |
1194 | return value, we have to skip the UNIMP instruction that encodes | |
1195 | the size of the structure. */ | |
1196 | if (cache->struct_return_p) | |
1197 | pc += 4; | |
386c036b | 1198 | |
369c397b JB |
1199 | regnum = |
1200 | (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; | |
236369e7 JB |
1201 | pc += get_frame_register_unsigned (this_frame, regnum) + 8; |
1202 | return frame_unwind_got_constant (this_frame, regnum, pc); | |
c906108c SS |
1203 | } |
1204 | ||
42cdca6c MK |
1205 | /* Handle StackGhost. */ |
1206 | { | |
e17a4113 | 1207 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
42cdca6c MK |
1208 | |
1209 | if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM) | |
1210 | { | |
236369e7 JB |
1211 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
1212 | ULONGEST i7; | |
1213 | ||
1214 | /* Read the value in from memory. */ | |
1215 | i7 = get_frame_memory_unsigned (this_frame, addr, 4); | |
1216 | return frame_unwind_got_constant (this_frame, regnum, i7 ^ wcookie); | |
42cdca6c MK |
1217 | } |
1218 | } | |
1219 | ||
369c397b | 1220 | /* The previous frame's `local' and `in' registers may have been saved |
386c036b | 1221 | in the register save area. */ |
369c397b JB |
1222 | if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM |
1223 | && (cache->saved_regs_mask & (1 << (regnum - SPARC_L0_REGNUM)))) | |
c906108c | 1224 | { |
236369e7 | 1225 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
386c036b | 1226 | |
236369e7 | 1227 | return frame_unwind_got_memory (this_frame, regnum, addr); |
386c036b | 1228 | } |
c906108c | 1229 | |
369c397b JB |
1230 | /* The previous frame's `out' registers may be accessible as the current |
1231 | frame's `in' registers. */ | |
1232 | if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM | |
1233 | && (cache->copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM)))) | |
386c036b | 1234 | regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); |
5af923b0 | 1235 | |
236369e7 | 1236 | return frame_unwind_got_register (this_frame, regnum, regnum); |
386c036b | 1237 | } |
c906108c | 1238 | |
386c036b MK |
1239 | static const struct frame_unwind sparc32_frame_unwind = |
1240 | { | |
1241 | NORMAL_FRAME, | |
8fbca658 | 1242 | default_frame_unwind_stop_reason, |
386c036b | 1243 | sparc32_frame_this_id, |
236369e7 JB |
1244 | sparc32_frame_prev_register, |
1245 | NULL, | |
1246 | default_frame_sniffer | |
386c036b | 1247 | }; |
386c036b | 1248 | \f |
c906108c | 1249 | |
386c036b | 1250 | static CORE_ADDR |
236369e7 | 1251 | sparc32_frame_base_address (struct frame_info *this_frame, void **this_cache) |
386c036b MK |
1252 | { |
1253 | struct sparc_frame_cache *cache = | |
236369e7 | 1254 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 1255 | |
386c036b MK |
1256 | return cache->base; |
1257 | } | |
c906108c | 1258 | |
386c036b MK |
1259 | static const struct frame_base sparc32_frame_base = |
1260 | { | |
1261 | &sparc32_frame_unwind, | |
1262 | sparc32_frame_base_address, | |
1263 | sparc32_frame_base_address, | |
1264 | sparc32_frame_base_address | |
1265 | }; | |
c906108c | 1266 | |
386c036b | 1267 | static struct frame_id |
236369e7 | 1268 | sparc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
386c036b MK |
1269 | { |
1270 | CORE_ADDR sp; | |
5af923b0 | 1271 | |
236369e7 | 1272 | sp = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
5b2d44a0 MK |
1273 | if (sp & 1) |
1274 | sp += BIAS; | |
236369e7 | 1275 | return frame_id_build (sp, get_frame_pc (this_frame)); |
386c036b MK |
1276 | } |
1277 | \f | |
c906108c | 1278 | |
3923a2b2 MK |
1279 | /* Extract a function return value of TYPE from REGCACHE, and copy |
1280 | that into VALBUF. */ | |
5af923b0 | 1281 | |
386c036b MK |
1282 | static void |
1283 | sparc32_extract_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1284 | gdb_byte *valbuf) |
386c036b MK |
1285 | { |
1286 | int len = TYPE_LENGTH (type); | |
fe10a582 | 1287 | gdb_byte buf[32]; |
c906108c | 1288 | |
386c036b MK |
1289 | gdb_assert (!sparc_structure_or_union_p (type)); |
1290 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 1291 | |
fe10a582 | 1292 | if (sparc_floating_p (type) || sparc_complex_floating_p (type)) |
5af923b0 | 1293 | { |
386c036b MK |
1294 | /* Floating return values. */ |
1295 | regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf); | |
1296 | if (len > 4) | |
1297 | regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4); | |
fe10a582 DM |
1298 | if (len > 8) |
1299 | { | |
1300 | regcache_cooked_read (regcache, SPARC_F2_REGNUM, buf + 8); | |
1301 | regcache_cooked_read (regcache, SPARC_F3_REGNUM, buf + 12); | |
1302 | } | |
1303 | if (len > 16) | |
1304 | { | |
1305 | regcache_cooked_read (regcache, SPARC_F4_REGNUM, buf + 16); | |
1306 | regcache_cooked_read (regcache, SPARC_F5_REGNUM, buf + 20); | |
1307 | regcache_cooked_read (regcache, SPARC_F6_REGNUM, buf + 24); | |
1308 | regcache_cooked_read (regcache, SPARC_F7_REGNUM, buf + 28); | |
1309 | } | |
386c036b | 1310 | memcpy (valbuf, buf, len); |
5af923b0 MS |
1311 | } |
1312 | else | |
1313 | { | |
386c036b MK |
1314 | /* Integral and pointer return values. */ |
1315 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
c906108c | 1316 | |
386c036b MK |
1317 | regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); |
1318 | if (len > 4) | |
1319 | { | |
1320 | regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4); | |
1321 | gdb_assert (len == 8); | |
1322 | memcpy (valbuf, buf, 8); | |
1323 | } | |
1324 | else | |
1325 | { | |
1326 | /* Just stripping off any unused bytes should preserve the | |
1327 | signed-ness just fine. */ | |
1328 | memcpy (valbuf, buf + 4 - len, len); | |
1329 | } | |
1330 | } | |
1331 | } | |
c906108c | 1332 | |
3923a2b2 MK |
1333 | /* Store the function return value of type TYPE from VALBUF into |
1334 | REGCACHE. */ | |
c906108c | 1335 | |
386c036b MK |
1336 | static void |
1337 | sparc32_store_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1338 | const gdb_byte *valbuf) |
386c036b MK |
1339 | { |
1340 | int len = TYPE_LENGTH (type); | |
e1613aba | 1341 | gdb_byte buf[8]; |
c906108c | 1342 | |
386c036b MK |
1343 | gdb_assert (!sparc_structure_or_union_p (type)); |
1344 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
a9789a6b | 1345 | gdb_assert (len <= 8); |
c906108c | 1346 | |
fe10a582 | 1347 | if (sparc_floating_p (type) || sparc_complex_floating_p (type)) |
386c036b MK |
1348 | { |
1349 | /* Floating return values. */ | |
1350 | memcpy (buf, valbuf, len); | |
1351 | regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf); | |
1352 | if (len > 4) | |
1353 | regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4); | |
fe10a582 DM |
1354 | if (len > 8) |
1355 | { | |
1356 | regcache_cooked_write (regcache, SPARC_F2_REGNUM, buf + 8); | |
1357 | regcache_cooked_write (regcache, SPARC_F3_REGNUM, buf + 12); | |
1358 | } | |
1359 | if (len > 16) | |
1360 | { | |
1361 | regcache_cooked_write (regcache, SPARC_F4_REGNUM, buf + 16); | |
1362 | regcache_cooked_write (regcache, SPARC_F5_REGNUM, buf + 20); | |
1363 | regcache_cooked_write (regcache, SPARC_F6_REGNUM, buf + 24); | |
1364 | regcache_cooked_write (regcache, SPARC_F7_REGNUM, buf + 28); | |
1365 | } | |
386c036b MK |
1366 | } |
1367 | else | |
c906108c | 1368 | { |
386c036b MK |
1369 | /* Integral and pointer return values. */ |
1370 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
1371 | ||
1372 | if (len > 4) | |
2757dd86 | 1373 | { |
386c036b MK |
1374 | gdb_assert (len == 8); |
1375 | memcpy (buf, valbuf, 8); | |
1376 | regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4); | |
2757dd86 AC |
1377 | } |
1378 | else | |
1379 | { | |
386c036b MK |
1380 | /* ??? Do we need to do any sign-extension here? */ |
1381 | memcpy (buf + 4 - len, valbuf, len); | |
2757dd86 | 1382 | } |
386c036b | 1383 | regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); |
c906108c SS |
1384 | } |
1385 | } | |
1386 | ||
b9d4c5ed | 1387 | static enum return_value_convention |
6a3a010b | 1388 | sparc32_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
1389 | struct type *type, struct regcache *regcache, |
1390 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
b9d4c5ed | 1391 | { |
e17a4113 UW |
1392 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1393 | ||
0a8f48b9 MK |
1394 | /* The psABI says that "...every stack frame reserves the word at |
1395 | %fp+64. If a function returns a structure, union, or | |
1396 | quad-precision value, this word should hold the address of the | |
1397 | object into which the return value should be copied." This | |
1398 | guarantees that we can always find the return value, not just | |
1399 | before the function returns. */ | |
1400 | ||
b9d4c5ed MK |
1401 | if (sparc_structure_or_union_p (type) |
1402 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
0a8f48b9 | 1403 | { |
bbfdfe1c DM |
1404 | ULONGEST sp; |
1405 | CORE_ADDR addr; | |
1406 | ||
0a8f48b9 MK |
1407 | if (readbuf) |
1408 | { | |
0a8f48b9 | 1409 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); |
e17a4113 | 1410 | addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); |
0a8f48b9 MK |
1411 | read_memory (addr, readbuf, TYPE_LENGTH (type)); |
1412 | } | |
bbfdfe1c DM |
1413 | if (writebuf) |
1414 | { | |
1415 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1416 | addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); | |
1417 | write_memory (addr, writebuf, TYPE_LENGTH (type)); | |
1418 | } | |
0a8f48b9 MK |
1419 | |
1420 | return RETURN_VALUE_ABI_PRESERVES_ADDRESS; | |
1421 | } | |
b9d4c5ed MK |
1422 | |
1423 | if (readbuf) | |
1424 | sparc32_extract_return_value (type, regcache, readbuf); | |
1425 | if (writebuf) | |
1426 | sparc32_store_return_value (type, regcache, writebuf); | |
1427 | ||
1428 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1429 | } | |
1430 | ||
386c036b MK |
1431 | static int |
1432 | sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) | |
c906108c | 1433 | { |
386c036b | 1434 | return (sparc_structure_or_union_p (type) |
fe10a582 DM |
1435 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16) |
1436 | || sparc_complex_floating_p (type)); | |
386c036b | 1437 | } |
c906108c | 1438 | |
aff37fc1 | 1439 | static int |
4a4e5149 | 1440 | sparc32_dwarf2_struct_return_p (struct frame_info *this_frame) |
aff37fc1 | 1441 | { |
236369e7 | 1442 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
aff37fc1 DM |
1443 | struct symbol *sym = find_pc_function (pc); |
1444 | ||
1445 | if (sym) | |
1446 | return sparc32_struct_return_from_sym (sym); | |
1447 | return 0; | |
1448 | } | |
1449 | ||
f5a9b87d DM |
1450 | static void |
1451 | sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 | 1452 | struct dwarf2_frame_state_reg *reg, |
4a4e5149 | 1453 | struct frame_info *this_frame) |
f5a9b87d | 1454 | { |
aff37fc1 DM |
1455 | int off; |
1456 | ||
f5a9b87d DM |
1457 | switch (regnum) |
1458 | { | |
1459 | case SPARC_G0_REGNUM: | |
1460 | /* Since %g0 is always zero, there is no point in saving it, and | |
1461 | people will be inclined omit it from the CFI. Make sure we | |
1462 | don't warn about that. */ | |
1463 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
1464 | break; | |
1465 | case SPARC_SP_REGNUM: | |
1466 | reg->how = DWARF2_FRAME_REG_CFA; | |
1467 | break; | |
1468 | case SPARC32_PC_REGNUM: | |
f5a9b87d DM |
1469 | case SPARC32_NPC_REGNUM: |
1470 | reg->how = DWARF2_FRAME_REG_RA_OFFSET; | |
aff37fc1 | 1471 | off = 8; |
4a4e5149 | 1472 | if (sparc32_dwarf2_struct_return_p (this_frame)) |
aff37fc1 DM |
1473 | off += 4; |
1474 | if (regnum == SPARC32_NPC_REGNUM) | |
1475 | off += 4; | |
1476 | reg->loc.offset = off; | |
f5a9b87d DM |
1477 | break; |
1478 | } | |
1479 | } | |
1480 | ||
386c036b MK |
1481 | \f |
1482 | /* The SPARC Architecture doesn't have hardware single-step support, | |
1483 | and most operating systems don't implement it either, so we provide | |
1484 | software single-step mechanism. */ | |
c906108c | 1485 | |
386c036b | 1486 | static CORE_ADDR |
0b1b3e42 | 1487 | sparc_analyze_control_transfer (struct frame_info *frame, |
c893be75 | 1488 | CORE_ADDR pc, CORE_ADDR *npc) |
386c036b MK |
1489 | { |
1490 | unsigned long insn = sparc_fetch_instruction (pc); | |
1491 | int conditional_p = X_COND (insn) & 0x7; | |
8d1b3521 | 1492 | int branch_p = 0, fused_p = 0; |
386c036b | 1493 | long offset = 0; /* Must be signed for sign-extend. */ |
c906108c | 1494 | |
8d1b3521 | 1495 | if (X_OP (insn) == 0 && X_OP2 (insn) == 3) |
c906108c | 1496 | { |
8d1b3521 DM |
1497 | if ((insn & 0x10000000) == 0) |
1498 | { | |
1499 | /* Branch on Integer Register with Prediction (BPr). */ | |
1500 | branch_p = 1; | |
1501 | conditional_p = 1; | |
1502 | } | |
1503 | else | |
1504 | { | |
1505 | /* Compare and Branch */ | |
1506 | branch_p = 1; | |
1507 | fused_p = 1; | |
1508 | offset = 4 * X_DISP10 (insn); | |
1509 | } | |
c906108c | 1510 | } |
386c036b | 1511 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) |
c906108c | 1512 | { |
386c036b MK |
1513 | /* Branch on Floating-Point Condition Codes (FBfcc). */ |
1514 | branch_p = 1; | |
1515 | offset = 4 * X_DISP22 (insn); | |
c906108c | 1516 | } |
386c036b MK |
1517 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) |
1518 | { | |
1519 | /* Branch on Floating-Point Condition Codes with Prediction | |
1520 | (FBPfcc). */ | |
1521 | branch_p = 1; | |
1522 | offset = 4 * X_DISP19 (insn); | |
1523 | } | |
1524 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) | |
1525 | { | |
1526 | /* Branch on Integer Condition Codes (Bicc). */ | |
1527 | branch_p = 1; | |
1528 | offset = 4 * X_DISP22 (insn); | |
1529 | } | |
1530 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) | |
c906108c | 1531 | { |
386c036b MK |
1532 | /* Branch on Integer Condition Codes with Prediction (BPcc). */ |
1533 | branch_p = 1; | |
1534 | offset = 4 * X_DISP19 (insn); | |
c906108c | 1535 | } |
c893be75 MK |
1536 | else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a) |
1537 | { | |
1538 | /* Trap instruction (TRAP). */ | |
0b1b3e42 | 1539 | return gdbarch_tdep (get_frame_arch (frame))->step_trap (frame, insn); |
c893be75 | 1540 | } |
386c036b MK |
1541 | |
1542 | /* FIXME: Handle DONE and RETRY instructions. */ | |
1543 | ||
386c036b | 1544 | if (branch_p) |
c906108c | 1545 | { |
8d1b3521 DM |
1546 | if (fused_p) |
1547 | { | |
1548 | /* Fused compare-and-branch instructions are non-delayed, | |
1549 | and do not have an annuling capability. So we need to | |
1550 | always set a breakpoint on both the NPC and the branch | |
1551 | target address. */ | |
1552 | gdb_assert (offset != 0); | |
1553 | return pc + offset; | |
1554 | } | |
1555 | else if (conditional_p) | |
c906108c | 1556 | { |
386c036b MK |
1557 | /* For conditional branches, return nPC + 4 iff the annul |
1558 | bit is 1. */ | |
1559 | return (X_A (insn) ? *npc + 4 : 0); | |
c906108c SS |
1560 | } |
1561 | else | |
1562 | { | |
386c036b MK |
1563 | /* For unconditional branches, return the target if its |
1564 | specified condition is "always" and return nPC + 4 if the | |
1565 | condition is "never". If the annul bit is 1, set *NPC to | |
1566 | zero. */ | |
1567 | if (X_COND (insn) == 0x0) | |
1568 | pc = *npc, offset = 4; | |
1569 | if (X_A (insn)) | |
1570 | *npc = 0; | |
1571 | ||
386c036b | 1572 | return pc + offset; |
c906108c SS |
1573 | } |
1574 | } | |
386c036b MK |
1575 | |
1576 | return 0; | |
c906108c SS |
1577 | } |
1578 | ||
c893be75 | 1579 | static CORE_ADDR |
0b1b3e42 | 1580 | sparc_step_trap (struct frame_info *frame, unsigned long insn) |
c893be75 MK |
1581 | { |
1582 | return 0; | |
1583 | } | |
1584 | ||
e6590a1b | 1585 | int |
0b1b3e42 | 1586 | sparc_software_single_step (struct frame_info *frame) |
386c036b | 1587 | { |
0b1b3e42 | 1588 | struct gdbarch *arch = get_frame_arch (frame); |
c893be75 | 1589 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
6c95b8df | 1590 | struct address_space *aspace = get_frame_address_space (frame); |
8181d85f | 1591 | CORE_ADDR npc, nnpc; |
c906108c | 1592 | |
e0cd558a | 1593 | CORE_ADDR pc, orig_npc; |
c906108c | 1594 | |
0b1b3e42 UW |
1595 | pc = get_frame_register_unsigned (frame, tdep->pc_regnum); |
1596 | orig_npc = npc = get_frame_register_unsigned (frame, tdep->npc_regnum); | |
c906108c | 1597 | |
e0cd558a | 1598 | /* Analyze the instruction at PC. */ |
0b1b3e42 | 1599 | nnpc = sparc_analyze_control_transfer (frame, pc, &npc); |
e0cd558a | 1600 | if (npc != 0) |
6c95b8df | 1601 | insert_single_step_breakpoint (arch, aspace, npc); |
8181d85f | 1602 | |
e0cd558a | 1603 | if (nnpc != 0) |
6c95b8df | 1604 | insert_single_step_breakpoint (arch, aspace, nnpc); |
c906108c | 1605 | |
e0cd558a UW |
1606 | /* Assert that we have set at least one breakpoint, and that |
1607 | they're not set at the same spot - unless we're going | |
1608 | from here straight to NULL, i.e. a call or jump to 0. */ | |
1609 | gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0); | |
1610 | gdb_assert (nnpc != npc || orig_npc == 0); | |
e6590a1b UW |
1611 | |
1612 | return 1; | |
386c036b MK |
1613 | } |
1614 | ||
1615 | static void | |
61a1198a | 1616 | sparc_write_pc (struct regcache *regcache, CORE_ADDR pc) |
386c036b | 1617 | { |
61a1198a | 1618 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
386c036b | 1619 | |
61a1198a UW |
1620 | regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc); |
1621 | regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4); | |
386c036b MK |
1622 | } |
1623 | \f | |
5af923b0 | 1624 | |
a54124c5 MK |
1625 | /* Return the appropriate register set for the core section identified |
1626 | by SECT_NAME and SECT_SIZE. */ | |
1627 | ||
63807e1d | 1628 | static const struct regset * |
a54124c5 MK |
1629 | sparc_regset_from_core_section (struct gdbarch *gdbarch, |
1630 | const char *sect_name, size_t sect_size) | |
1631 | { | |
1632 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1633 | ||
c558d81a | 1634 | if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset) |
a54124c5 MK |
1635 | return tdep->gregset; |
1636 | ||
c558d81a | 1637 | if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset) |
a54124c5 MK |
1638 | return tdep->fpregset; |
1639 | ||
1640 | return NULL; | |
1641 | } | |
1642 | \f | |
1643 | ||
386c036b MK |
1644 | static struct gdbarch * |
1645 | sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1646 | { | |
1647 | struct gdbarch_tdep *tdep; | |
1648 | struct gdbarch *gdbarch; | |
c906108c | 1649 | |
386c036b MK |
1650 | /* If there is already a candidate, use it. */ |
1651 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1652 | if (arches != NULL) | |
1653 | return arches->gdbarch; | |
c906108c | 1654 | |
386c036b | 1655 | /* Allocate space for the new architecture. */ |
1390fcc2 | 1656 | tdep = XZALLOC (struct gdbarch_tdep); |
386c036b | 1657 | gdbarch = gdbarch_alloc (&info, tdep); |
5af923b0 | 1658 | |
386c036b MK |
1659 | tdep->pc_regnum = SPARC32_PC_REGNUM; |
1660 | tdep->npc_regnum = SPARC32_NPC_REGNUM; | |
c893be75 | 1661 | tdep->step_trap = sparc_step_trap; |
386c036b MK |
1662 | |
1663 | set_gdbarch_long_double_bit (gdbarch, 128); | |
8da61cc4 | 1664 | set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad); |
386c036b MK |
1665 | |
1666 | set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); | |
1667 | set_gdbarch_register_name (gdbarch, sparc32_register_name); | |
1668 | set_gdbarch_register_type (gdbarch, sparc32_register_type); | |
1669 | set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); | |
1670 | set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); | |
1671 | set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); | |
1672 | ||
1673 | /* Register numbers of various important registers. */ | |
1674 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ | |
1675 | set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ | |
1676 | set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ | |
1677 | ||
1678 | /* Call dummy code. */ | |
49a45ecf | 1679 | set_gdbarch_frame_align (gdbarch, sparc32_frame_align); |
386c036b MK |
1680 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
1681 | set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); | |
1682 | set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); | |
1683 | ||
b9d4c5ed | 1684 | set_gdbarch_return_value (gdbarch, sparc32_return_value); |
386c036b MK |
1685 | set_gdbarch_stabs_argument_has_addr |
1686 | (gdbarch, sparc32_stabs_argument_has_addr); | |
1687 | ||
1688 | set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); | |
1689 | ||
1690 | /* Stack grows downward. */ | |
1691 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
c906108c | 1692 | |
386c036b | 1693 | set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc); |
c906108c | 1694 | |
386c036b | 1695 | set_gdbarch_frame_args_skip (gdbarch, 8); |
5af923b0 | 1696 | |
386c036b | 1697 | set_gdbarch_print_insn (gdbarch, print_insn_sparc); |
c906108c | 1698 | |
386c036b MK |
1699 | set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); |
1700 | set_gdbarch_write_pc (gdbarch, sparc_write_pc); | |
c906108c | 1701 | |
236369e7 | 1702 | set_gdbarch_dummy_id (gdbarch, sparc_dummy_id); |
c906108c | 1703 | |
386c036b | 1704 | set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc); |
c906108c | 1705 | |
386c036b MK |
1706 | frame_base_set_default (gdbarch, &sparc32_frame_base); |
1707 | ||
f5a9b87d DM |
1708 | /* Hook in the DWARF CFI frame unwinder. */ |
1709 | dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg); | |
1710 | /* FIXME: kettenis/20050423: Don't enable the unwinder until the | |
1711 | StackGhost issues have been resolved. */ | |
1712 | ||
b2a0b9b2 DM |
1713 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1714 | gdbarch_init_osabi (info, gdbarch); | |
1715 | ||
236369e7 | 1716 | frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind); |
c906108c | 1717 | |
a54124c5 | 1718 | /* If we have register sets, enable the generic core file support. */ |
4c72d57a | 1719 | if (tdep->gregset) |
a54124c5 MK |
1720 | set_gdbarch_regset_from_core_section (gdbarch, |
1721 | sparc_regset_from_core_section); | |
1722 | ||
7e35103a JB |
1723 | register_sparc_ravenscar_ops (gdbarch); |
1724 | ||
386c036b MK |
1725 | return gdbarch; |
1726 | } | |
1727 | \f | |
1728 | /* Helper functions for dealing with register windows. */ | |
1729 | ||
1730 | void | |
1731 | sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) | |
c906108c | 1732 | { |
e17a4113 UW |
1733 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1734 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
386c036b | 1735 | int offset = 0; |
e1613aba | 1736 | gdb_byte buf[8]; |
386c036b MK |
1737 | int i; |
1738 | ||
1739 | if (sp & 1) | |
1740 | { | |
1741 | /* Registers are 64-bit. */ | |
1742 | sp += BIAS; | |
c906108c | 1743 | |
386c036b MK |
1744 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1745 | { | |
1746 | if (regnum == i || regnum == -1) | |
1747 | { | |
1748 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); | |
f700a364 MK |
1749 | |
1750 | /* Handle StackGhost. */ | |
1751 | if (i == SPARC_I7_REGNUM) | |
1752 | { | |
e17a4113 UW |
1753 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1754 | ULONGEST i7; | |
f700a364 | 1755 | |
e17a4113 UW |
1756 | i7 = extract_unsigned_integer (buf + offset, 8, byte_order); |
1757 | store_unsigned_integer (buf + offset, 8, byte_order, | |
1758 | i7 ^ wcookie); | |
f700a364 MK |
1759 | } |
1760 | ||
386c036b MK |
1761 | regcache_raw_supply (regcache, i, buf); |
1762 | } | |
1763 | } | |
1764 | } | |
1765 | else | |
c906108c | 1766 | { |
386c036b MK |
1767 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1768 | pointer. */ | |
1769 | sp &= 0xffffffffUL; | |
c906108c | 1770 | |
386c036b MK |
1771 | /* Clear out the top half of the temporary buffer, and put the |
1772 | register value in the bottom half if we're in 64-bit mode. */ | |
e6d4f032 | 1773 | if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) |
c906108c | 1774 | { |
386c036b MK |
1775 | memset (buf, 0, 4); |
1776 | offset = 4; | |
1777 | } | |
c906108c | 1778 | |
386c036b MK |
1779 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1780 | { | |
1781 | if (regnum == i || regnum == -1) | |
1782 | { | |
1783 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), | |
1784 | buf + offset, 4); | |
42cdca6c MK |
1785 | |
1786 | /* Handle StackGhost. */ | |
1787 | if (i == SPARC_I7_REGNUM) | |
1788 | { | |
e17a4113 UW |
1789 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1790 | ULONGEST i7; | |
42cdca6c | 1791 | |
e17a4113 UW |
1792 | i7 = extract_unsigned_integer (buf + offset, 4, byte_order); |
1793 | store_unsigned_integer (buf + offset, 4, byte_order, | |
1794 | i7 ^ wcookie); | |
42cdca6c MK |
1795 | } |
1796 | ||
386c036b MK |
1797 | regcache_raw_supply (regcache, i, buf); |
1798 | } | |
c906108c SS |
1799 | } |
1800 | } | |
c906108c | 1801 | } |
c906108c SS |
1802 | |
1803 | void | |
386c036b MK |
1804 | sparc_collect_rwindow (const struct regcache *regcache, |
1805 | CORE_ADDR sp, int regnum) | |
c906108c | 1806 | { |
e17a4113 UW |
1807 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1808 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
386c036b | 1809 | int offset = 0; |
e1613aba | 1810 | gdb_byte buf[8]; |
386c036b | 1811 | int i; |
5af923b0 | 1812 | |
386c036b | 1813 | if (sp & 1) |
5af923b0 | 1814 | { |
386c036b MK |
1815 | /* Registers are 64-bit. */ |
1816 | sp += BIAS; | |
c906108c | 1817 | |
386c036b MK |
1818 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1819 | { | |
1820 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1821 | { | |
1822 | regcache_raw_collect (regcache, i, buf); | |
f700a364 MK |
1823 | |
1824 | /* Handle StackGhost. */ | |
1825 | if (i == SPARC_I7_REGNUM) | |
1826 | { | |
e17a4113 UW |
1827 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1828 | ULONGEST i7; | |
f700a364 | 1829 | |
e17a4113 UW |
1830 | i7 = extract_unsigned_integer (buf + offset, 8, byte_order); |
1831 | store_unsigned_integer (buf, 8, byte_order, i7 ^ wcookie); | |
f700a364 MK |
1832 | } |
1833 | ||
386c036b MK |
1834 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); |
1835 | } | |
1836 | } | |
5af923b0 MS |
1837 | } |
1838 | else | |
1839 | { | |
386c036b MK |
1840 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1841 | pointer. */ | |
1842 | sp &= 0xffffffffUL; | |
1843 | ||
1844 | /* Only use the bottom half if we're in 64-bit mode. */ | |
e6d4f032 | 1845 | if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) |
386c036b MK |
1846 | offset = 4; |
1847 | ||
1848 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1849 | { | |
1850 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1851 | { | |
1852 | regcache_raw_collect (regcache, i, buf); | |
42cdca6c MK |
1853 | |
1854 | /* Handle StackGhost. */ | |
1855 | if (i == SPARC_I7_REGNUM) | |
1856 | { | |
e17a4113 UW |
1857 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1858 | ULONGEST i7; | |
42cdca6c | 1859 | |
e17a4113 UW |
1860 | i7 = extract_unsigned_integer (buf + offset, 4, byte_order); |
1861 | store_unsigned_integer (buf + offset, 4, byte_order, | |
1862 | i7 ^ wcookie); | |
42cdca6c MK |
1863 | } |
1864 | ||
386c036b MK |
1865 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), |
1866 | buf + offset, 4); | |
1867 | } | |
1868 | } | |
5af923b0 | 1869 | } |
c906108c SS |
1870 | } |
1871 | ||
386c036b MK |
1872 | /* Helper functions for dealing with register sets. */ |
1873 | ||
c906108c | 1874 | void |
386c036b MK |
1875 | sparc32_supply_gregset (const struct sparc_gregset *gregset, |
1876 | struct regcache *regcache, | |
1877 | int regnum, const void *gregs) | |
c906108c | 1878 | { |
e1613aba | 1879 | const gdb_byte *regs = gregs; |
22e74ef9 | 1880 | gdb_byte zero[4] = { 0 }; |
386c036b | 1881 | int i; |
5af923b0 | 1882 | |
386c036b MK |
1883 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1884 | regcache_raw_supply (regcache, SPARC32_PSR_REGNUM, | |
1885 | regs + gregset->r_psr_offset); | |
c906108c | 1886 | |
386c036b MK |
1887 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1888 | regcache_raw_supply (regcache, SPARC32_PC_REGNUM, | |
1889 | regs + gregset->r_pc_offset); | |
5af923b0 | 1890 | |
386c036b MK |
1891 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) |
1892 | regcache_raw_supply (regcache, SPARC32_NPC_REGNUM, | |
1893 | regs + gregset->r_npc_offset); | |
5af923b0 | 1894 | |
386c036b MK |
1895 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1896 | regcache_raw_supply (regcache, SPARC32_Y_REGNUM, | |
1897 | regs + gregset->r_y_offset); | |
5af923b0 | 1898 | |
386c036b | 1899 | if (regnum == SPARC_G0_REGNUM || regnum == -1) |
22e74ef9 | 1900 | regcache_raw_supply (regcache, SPARC_G0_REGNUM, &zero); |
5af923b0 | 1901 | |
386c036b | 1902 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) |
c906108c | 1903 | { |
386c036b MK |
1904 | int offset = gregset->r_g1_offset; |
1905 | ||
1906 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1907 | { | |
1908 | if (regnum == i || regnum == -1) | |
1909 | regcache_raw_supply (regcache, i, regs + offset); | |
1910 | offset += 4; | |
1911 | } | |
c906108c | 1912 | } |
386c036b MK |
1913 | |
1914 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
c906108c | 1915 | { |
386c036b MK |
1916 | /* Not all of the register set variants include Locals and |
1917 | Inputs. For those that don't, we read them off the stack. */ | |
1918 | if (gregset->r_l0_offset == -1) | |
1919 | { | |
1920 | ULONGEST sp; | |
1921 | ||
1922 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1923 | sparc_supply_rwindow (regcache, sp, regnum); | |
1924 | } | |
1925 | else | |
1926 | { | |
1927 | int offset = gregset->r_l0_offset; | |
1928 | ||
1929 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1930 | { | |
1931 | if (regnum == i || regnum == -1) | |
1932 | regcache_raw_supply (regcache, i, regs + offset); | |
1933 | offset += 4; | |
1934 | } | |
1935 | } | |
c906108c SS |
1936 | } |
1937 | } | |
1938 | ||
c5aa993b | 1939 | void |
386c036b MK |
1940 | sparc32_collect_gregset (const struct sparc_gregset *gregset, |
1941 | const struct regcache *regcache, | |
1942 | int regnum, void *gregs) | |
c906108c | 1943 | { |
e1613aba | 1944 | gdb_byte *regs = gregs; |
386c036b | 1945 | int i; |
c5aa993b | 1946 | |
386c036b MK |
1947 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1948 | regcache_raw_collect (regcache, SPARC32_PSR_REGNUM, | |
1949 | regs + gregset->r_psr_offset); | |
60054393 | 1950 | |
386c036b MK |
1951 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1952 | regcache_raw_collect (regcache, SPARC32_PC_REGNUM, | |
1953 | regs + gregset->r_pc_offset); | |
1954 | ||
1955 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) | |
1956 | regcache_raw_collect (regcache, SPARC32_NPC_REGNUM, | |
1957 | regs + gregset->r_npc_offset); | |
5af923b0 | 1958 | |
386c036b MK |
1959 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1960 | regcache_raw_collect (regcache, SPARC32_Y_REGNUM, | |
1961 | regs + gregset->r_y_offset); | |
1962 | ||
1963 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) | |
5af923b0 | 1964 | { |
386c036b MK |
1965 | int offset = gregset->r_g1_offset; |
1966 | ||
1967 | /* %g0 is always zero. */ | |
1968 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1969 | { | |
1970 | if (regnum == i || regnum == -1) | |
1971 | regcache_raw_collect (regcache, i, regs + offset); | |
1972 | offset += 4; | |
1973 | } | |
5af923b0 | 1974 | } |
386c036b MK |
1975 | |
1976 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
5af923b0 | 1977 | { |
386c036b MK |
1978 | /* Not all of the register set variants include Locals and |
1979 | Inputs. For those that don't, we read them off the stack. */ | |
1980 | if (gregset->r_l0_offset != -1) | |
1981 | { | |
1982 | int offset = gregset->r_l0_offset; | |
1983 | ||
1984 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1985 | { | |
1986 | if (regnum == i || regnum == -1) | |
1987 | regcache_raw_collect (regcache, i, regs + offset); | |
1988 | offset += 4; | |
1989 | } | |
1990 | } | |
5af923b0 | 1991 | } |
c906108c SS |
1992 | } |
1993 | ||
c906108c | 1994 | void |
db75c717 DM |
1995 | sparc32_supply_fpregset (const struct sparc_fpregset *fpregset, |
1996 | struct regcache *regcache, | |
386c036b | 1997 | int regnum, const void *fpregs) |
c906108c | 1998 | { |
e1613aba | 1999 | const gdb_byte *regs = fpregs; |
386c036b | 2000 | int i; |
60054393 | 2001 | |
386c036b | 2002 | for (i = 0; i < 32; i++) |
c906108c | 2003 | { |
386c036b | 2004 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) |
db75c717 DM |
2005 | regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, |
2006 | regs + fpregset->r_f0_offset + (i * 4)); | |
c906108c | 2007 | } |
5af923b0 | 2008 | |
386c036b | 2009 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
db75c717 DM |
2010 | regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, |
2011 | regs + fpregset->r_fsr_offset); | |
c906108c SS |
2012 | } |
2013 | ||
386c036b | 2014 | void |
db75c717 DM |
2015 | sparc32_collect_fpregset (const struct sparc_fpregset *fpregset, |
2016 | const struct regcache *regcache, | |
386c036b | 2017 | int regnum, void *fpregs) |
c906108c | 2018 | { |
e1613aba | 2019 | gdb_byte *regs = fpregs; |
386c036b | 2020 | int i; |
c906108c | 2021 | |
386c036b MK |
2022 | for (i = 0; i < 32; i++) |
2023 | { | |
2024 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) | |
db75c717 DM |
2025 | regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, |
2026 | regs + fpregset->r_f0_offset + (i * 4)); | |
386c036b | 2027 | } |
c906108c | 2028 | |
386c036b | 2029 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
db75c717 DM |
2030 | regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, |
2031 | regs + fpregset->r_fsr_offset); | |
c906108c | 2032 | } |
c906108c | 2033 | \f |
c906108c | 2034 | |
386c036b | 2035 | /* SunOS 4. */ |
c906108c | 2036 | |
386c036b MK |
2037 | /* From <machine/reg.h>. */ |
2038 | const struct sparc_gregset sparc32_sunos4_gregset = | |
c906108c | 2039 | { |
386c036b MK |
2040 | 0 * 4, /* %psr */ |
2041 | 1 * 4, /* %pc */ | |
2042 | 2 * 4, /* %npc */ | |
2043 | 3 * 4, /* %y */ | |
2044 | -1, /* %wim */ | |
2045 | -1, /* %tbr */ | |
2046 | 4 * 4, /* %g1 */ | |
2047 | -1 /* %l0 */ | |
2048 | }; | |
db75c717 DM |
2049 | |
2050 | const struct sparc_fpregset sparc32_sunos4_fpregset = | |
2051 | { | |
2052 | 0 * 4, /* %f0 */ | |
2053 | 33 * 4, /* %fsr */ | |
2054 | }; | |
2055 | ||
2056 | const struct sparc_fpregset sparc32_bsd_fpregset = | |
2057 | { | |
2058 | 0 * 4, /* %f0 */ | |
2059 | 32 * 4, /* %fsr */ | |
2060 | }; | |
386c036b | 2061 | \f |
c906108c | 2062 | |
386c036b MK |
2063 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
2064 | void _initialize_sparc_tdep (void); | |
c906108c SS |
2065 | |
2066 | void | |
386c036b | 2067 | _initialize_sparc_tdep (void) |
c906108c | 2068 | { |
386c036b | 2069 | register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init); |
ef3cf062 | 2070 | } |