Commit | Line | Data |
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386c036b | 1 | /* Target-dependent code for SPARC. |
cda5a58a | 2 | |
b811d2c2 | 3 | Copyright (C) 2003-2020 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 19 | |
c906108c | 20 | #include "defs.h" |
5af923b0 | 21 | #include "arch-utils.h" |
386c036b | 22 | #include "dis-asm.h" |
b41c5a85 | 23 | #include "dwarf2.h" |
82ca8957 | 24 | #include "dwarf2/frame.h" |
c906108c | 25 | #include "frame.h" |
386c036b MK |
26 | #include "frame-base.h" |
27 | #include "frame-unwind.h" | |
28 | #include "gdbcore.h" | |
29 | #include "gdbtypes.h" | |
c906108c | 30 | #include "inferior.h" |
386c036b MK |
31 | #include "symtab.h" |
32 | #include "objfiles.h" | |
33 | #include "osabi.h" | |
34 | #include "regcache.h" | |
c906108c | 35 | #include "target.h" |
3f7b46f2 | 36 | #include "target-descriptions.h" |
c906108c | 37 | #include "value.h" |
c906108c | 38 | |
386c036b | 39 | #include "sparc-tdep.h" |
e6f9c00b | 40 | #include "sparc-ravenscar-thread.h" |
325fac50 | 41 | #include <algorithm> |
c906108c | 42 | |
a54124c5 MK |
43 | struct regset; |
44 | ||
9eb42ed1 MK |
45 | /* This file implements the SPARC 32-bit ABI as defined by the section |
46 | "Low-Level System Information" of the SPARC Compliance Definition | |
47 | (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD | |
f2e7c15d | 48 | lists changes with respect to the original 32-bit psABI as defined |
9eb42ed1 | 49 | in the "System V ABI, SPARC Processor Supplement". |
386c036b MK |
50 | |
51 | Note that if we talk about SunOS, we mean SunOS 4.x, which was | |
52 | BSD-based, which is sometimes (retroactively?) referred to as | |
53 | Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and | |
54 | above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 | |
55 | suffering from severe version number inflation). Solaris 2.x is | |
56 | also known as SunOS 5.x, since that's what uname(1) says. Solaris | |
57 | 2.x is SVR4-based. */ | |
58 | ||
59 | /* Please use the sparc32_-prefix for 32-bit specific code, the | |
60 | sparc64_-prefix for 64-bit specific code and the sparc_-prefix for | |
61 | code that can handle both. The 64-bit specific code lives in | |
62 | sparc64-tdep.c; don't add any here. */ | |
63 | ||
64 | /* The SPARC Floating-Point Quad-Precision format is similar to | |
7a58cce8 | 65 | big-endian IA-64 Quad-Precision format. */ |
8da61cc4 | 66 | #define floatformats_sparc_quad floatformats_ia64_quad |
386c036b MK |
67 | |
68 | /* The stack pointer is offset from the stack frame by a BIAS of 2047 | |
69 | (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC | |
70 | hosts, so undefine it first. */ | |
71 | #undef BIAS | |
72 | #define BIAS 2047 | |
73 | ||
74 | /* Macros to extract fields from SPARC instructions. */ | |
c906108c SS |
75 | #define X_OP(i) (((i) >> 30) & 0x3) |
76 | #define X_RD(i) (((i) >> 25) & 0x1f) | |
77 | #define X_A(i) (((i) >> 29) & 1) | |
78 | #define X_COND(i) (((i) >> 25) & 0xf) | |
79 | #define X_OP2(i) (((i) >> 22) & 0x7) | |
80 | #define X_IMM22(i) ((i) & 0x3fffff) | |
81 | #define X_OP3(i) (((i) >> 19) & 0x3f) | |
075ccec8 | 82 | #define X_RS1(i) (((i) >> 14) & 0x1f) |
b0b92586 | 83 | #define X_RS2(i) ((i) & 0x1f) |
c906108c | 84 | #define X_I(i) (((i) >> 13) & 1) |
c906108c | 85 | /* Sign extension macros. */ |
c906108c | 86 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) |
c906108c | 87 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) |
8d1b3521 | 88 | #define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200) |
075ccec8 | 89 | #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000) |
961842b2 JM |
90 | /* Macros to identify some instructions. */ |
91 | /* RETURN (RETT in V8) */ | |
92 | #define X_RETTURN(i) ((X_OP (i) == 0x2) && (X_OP3 (i) == 0x39)) | |
c906108c | 93 | |
386c036b MK |
94 | /* Fetch the instruction at PC. Instructions are always big-endian |
95 | even if the processor operates in little-endian mode. */ | |
96 | ||
97 | unsigned long | |
98 | sparc_fetch_instruction (CORE_ADDR pc) | |
c906108c | 99 | { |
e1613aba | 100 | gdb_byte buf[4]; |
386c036b MK |
101 | unsigned long insn; |
102 | int i; | |
103 | ||
690668cc | 104 | /* If we can't read the instruction at PC, return zero. */ |
8defab1a | 105 | if (target_read_memory (pc, buf, sizeof (buf))) |
690668cc | 106 | return 0; |
c906108c | 107 | |
386c036b MK |
108 | insn = 0; |
109 | for (i = 0; i < sizeof (buf); i++) | |
110 | insn = (insn << 8) | buf[i]; | |
111 | return insn; | |
112 | } | |
42cdca6c MK |
113 | \f |
114 | ||
5465445a JB |
115 | /* Return non-zero if the instruction corresponding to PC is an "unimp" |
116 | instruction. */ | |
117 | ||
118 | static int | |
119 | sparc_is_unimp_insn (CORE_ADDR pc) | |
120 | { | |
121 | const unsigned long insn = sparc_fetch_instruction (pc); | |
122 | ||
123 | return ((insn & 0xc1c00000) == 0); | |
124 | } | |
125 | ||
d0b5971a JM |
126 | /* Return non-zero if the instruction corresponding to PC is an |
127 | "annulled" branch, i.e. the annul bit is set. */ | |
128 | ||
129 | int | |
130 | sparc_is_annulled_branch_insn (CORE_ADDR pc) | |
131 | { | |
132 | /* The branch instructions featuring an annul bit can be identified | |
133 | by the following bit patterns: | |
134 | ||
135 | OP=0 | |
136 | OP2=1: Branch on Integer Condition Codes with Prediction (BPcc). | |
137 | OP2=2: Branch on Integer Condition Codes (Bcc). | |
138 | OP2=5: Branch on FP Condition Codes with Prediction (FBfcc). | |
139 | OP2=6: Branch on FP Condition Codes (FBcc). | |
140 | OP2=3 && Bit28=0: | |
141 | Branch on Integer Register with Prediction (BPr). | |
142 | ||
143 | This leaves out ILLTRAP (OP2=0), SETHI/NOP (OP2=4) and the V8 | |
144 | coprocessor branch instructions (Op2=7). */ | |
145 | ||
146 | const unsigned long insn = sparc_fetch_instruction (pc); | |
147 | const unsigned op2 = X_OP2 (insn); | |
148 | ||
149 | if ((X_OP (insn) == 0) | |
150 | && ((op2 == 1) || (op2 == 2) || (op2 == 5) || (op2 == 6) | |
151 | || ((op2 == 3) && ((insn & 0x10000000) == 0)))) | |
152 | return X_A (insn); | |
153 | else | |
154 | return 0; | |
155 | } | |
156 | ||
42cdca6c MK |
157 | /* OpenBSD/sparc includes StackGhost, which according to the author's |
158 | website http://stackghost.cerias.purdue.edu "... transparently and | |
159 | automatically protects applications' stack frames; more | |
160 | specifically, it guards the return pointers. The protection | |
161 | mechanisms require no application source or binary modification and | |
162 | imposes only a negligible performance penalty." | |
163 | ||
164 | The same website provides the following description of how | |
165 | StackGhost works: | |
166 | ||
167 | "StackGhost interfaces with the kernel trap handler that would | |
168 | normally write out registers to the stack and the handler that | |
169 | would read them back in. By XORing a cookie into the | |
170 | return-address saved in the user stack when it is actually written | |
171 | to the stack, and then XOR it out when the return-address is pulled | |
172 | from the stack, StackGhost can cause attacker corrupted return | |
173 | pointers to behave in a manner the attacker cannot predict. | |
174 | StackGhost can also use several unused bits in the return pointer | |
175 | to detect a smashed return pointer and abort the process." | |
176 | ||
177 | For GDB this means that whenever we're reading %i7 from a stack | |
178 | frame's window save area, we'll have to XOR the cookie. | |
179 | ||
180 | More information on StackGuard can be found on in: | |
181 | ||
c378eb4e | 182 | Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated |
42cdca6c MK |
183 | Stack Protection." 2001. Published in USENIX Security Symposium |
184 | '01. */ | |
185 | ||
186 | /* Fetch StackGhost Per-Process XOR cookie. */ | |
187 | ||
188 | ULONGEST | |
e17a4113 | 189 | sparc_fetch_wcookie (struct gdbarch *gdbarch) |
42cdca6c | 190 | { |
e17a4113 | 191 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
8b88a78e | 192 | struct target_ops *ops = current_top_target (); |
e1613aba | 193 | gdb_byte buf[8]; |
baf92889 MK |
194 | int len; |
195 | ||
13547ab6 | 196 | len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8); |
baf92889 MK |
197 | if (len == -1) |
198 | return 0; | |
42cdca6c | 199 | |
baf92889 MK |
200 | /* We should have either an 32-bit or an 64-bit cookie. */ |
201 | gdb_assert (len == 4 || len == 8); | |
202 | ||
e17a4113 | 203 | return extract_unsigned_integer (buf, len, byte_order); |
baf92889 | 204 | } |
386c036b | 205 | \f |
baf92889 | 206 | |
386c036b MK |
207 | /* The functions on this page are intended to be used to classify |
208 | function arguments. */ | |
c906108c | 209 | |
386c036b | 210 | /* Check whether TYPE is "Integral or Pointer". */ |
c906108c | 211 | |
386c036b MK |
212 | static int |
213 | sparc_integral_or_pointer_p (const struct type *type) | |
c906108c | 214 | { |
80ad1639 MK |
215 | int len = TYPE_LENGTH (type); |
216 | ||
78134374 | 217 | switch (type->code ()) |
c906108c | 218 | { |
386c036b MK |
219 | case TYPE_CODE_INT: |
220 | case TYPE_CODE_BOOL: | |
221 | case TYPE_CODE_CHAR: | |
222 | case TYPE_CODE_ENUM: | |
223 | case TYPE_CODE_RANGE: | |
80ad1639 MK |
224 | /* We have byte, half-word, word and extended-word/doubleword |
225 | integral types. The doubleword is an extension to the | |
226 | original 32-bit ABI by the SCD 2.4.x. */ | |
227 | return (len == 1 || len == 2 || len == 4 || len == 8); | |
386c036b MK |
228 | case TYPE_CODE_PTR: |
229 | case TYPE_CODE_REF: | |
aa006118 | 230 | case TYPE_CODE_RVALUE_REF: |
80ad1639 MK |
231 | /* Allow either 32-bit or 64-bit pointers. */ |
232 | return (len == 4 || len == 8); | |
386c036b MK |
233 | default: |
234 | break; | |
235 | } | |
c906108c | 236 | |
386c036b MK |
237 | return 0; |
238 | } | |
c906108c | 239 | |
386c036b | 240 | /* Check whether TYPE is "Floating". */ |
c906108c | 241 | |
386c036b MK |
242 | static int |
243 | sparc_floating_p (const struct type *type) | |
244 | { | |
78134374 | 245 | switch (type->code ()) |
c906108c | 246 | { |
386c036b MK |
247 | case TYPE_CODE_FLT: |
248 | { | |
249 | int len = TYPE_LENGTH (type); | |
250 | return (len == 4 || len == 8 || len == 16); | |
251 | } | |
252 | default: | |
253 | break; | |
254 | } | |
255 | ||
256 | return 0; | |
257 | } | |
c906108c | 258 | |
fe10a582 DM |
259 | /* Check whether TYPE is "Complex Floating". */ |
260 | ||
261 | static int | |
262 | sparc_complex_floating_p (const struct type *type) | |
263 | { | |
78134374 | 264 | switch (type->code ()) |
fe10a582 DM |
265 | { |
266 | case TYPE_CODE_COMPLEX: | |
267 | { | |
268 | int len = TYPE_LENGTH (type); | |
269 | return (len == 8 || len == 16 || len == 32); | |
270 | } | |
271 | default: | |
272 | break; | |
273 | } | |
274 | ||
275 | return 0; | |
276 | } | |
277 | ||
0497f5b0 JB |
278 | /* Check whether TYPE is "Structure or Union". |
279 | ||
280 | In terms of Ada subprogram calls, arrays are treated the same as | |
281 | struct and union types. So this function also returns non-zero | |
282 | for array types. */ | |
c906108c | 283 | |
386c036b MK |
284 | static int |
285 | sparc_structure_or_union_p (const struct type *type) | |
286 | { | |
78134374 | 287 | switch (type->code ()) |
386c036b MK |
288 | { |
289 | case TYPE_CODE_STRUCT: | |
290 | case TYPE_CODE_UNION: | |
0497f5b0 | 291 | case TYPE_CODE_ARRAY: |
386c036b MK |
292 | return 1; |
293 | default: | |
294 | break; | |
c906108c | 295 | } |
386c036b MK |
296 | |
297 | return 0; | |
c906108c | 298 | } |
386c036b | 299 | |
05bc7456 JB |
300 | /* Return true if TYPE is returned by memory, false if returned by |
301 | register. */ | |
1933fd8e VM |
302 | |
303 | static bool | |
304 | sparc_structure_return_p (const struct type *type) | |
305 | { | |
78134374 | 306 | if (type->code () == TYPE_CODE_ARRAY && TYPE_VECTOR (type)) |
1933fd8e | 307 | { |
05bc7456 JB |
308 | /* Float vectors are always returned by memory. */ |
309 | if (sparc_floating_p (check_typedef (TYPE_TARGET_TYPE (type)))) | |
310 | return true; | |
311 | /* Integer vectors are returned by memory if the vector size | |
312 | is greater than 8 bytes long. */ | |
313 | return (TYPE_LENGTH (type) > 8); | |
314 | } | |
1933fd8e | 315 | |
05bc7456 JB |
316 | if (sparc_floating_p (type)) |
317 | { | |
318 | /* Floating point types are passed by register for size 4 and | |
319 | 8 bytes, and by memory for size 16 bytes. */ | |
320 | return (TYPE_LENGTH (type) == 16); | |
1933fd8e | 321 | } |
05bc7456 JB |
322 | |
323 | /* Other than that, only aggregates of all sizes get returned by | |
324 | memory. */ | |
1933fd8e VM |
325 | return sparc_structure_or_union_p (type); |
326 | } | |
327 | ||
05bc7456 JB |
328 | /* Return true if arguments of the given TYPE are passed by |
329 | memory; false if returned by register. */ | |
1933fd8e VM |
330 | |
331 | static bool | |
05bc7456 | 332 | sparc_arg_by_memory_p (const struct type *type) |
1933fd8e | 333 | { |
78134374 | 334 | if (type->code () == TYPE_CODE_ARRAY && TYPE_VECTOR (type)) |
1933fd8e | 335 | { |
05bc7456 JB |
336 | /* Float vectors are always passed by memory. */ |
337 | if (sparc_floating_p (check_typedef (TYPE_TARGET_TYPE (type)))) | |
338 | return true; | |
339 | /* Integer vectors are passed by memory if the vector size | |
340 | is greater than 8 bytes long. */ | |
341 | return (TYPE_LENGTH (type) > 8); | |
1933fd8e | 342 | } |
05bc7456 JB |
343 | |
344 | /* Floats are passed by register for size 4 and 8 bytes, and by memory | |
345 | for size 16 bytes. */ | |
346 | if (sparc_floating_p (type)) | |
347 | return (TYPE_LENGTH (type) == 16); | |
348 | ||
349 | /* Complex floats and aggregates of all sizes are passed by memory. */ | |
350 | if (sparc_complex_floating_p (type) || sparc_structure_or_union_p (type)) | |
351 | return true; | |
352 | ||
353 | /* Everything else gets passed by register. */ | |
354 | return false; | |
1933fd8e VM |
355 | } |
356 | ||
386c036b | 357 | /* Register information. */ |
7a36499a IR |
358 | #define SPARC32_FPU_REGISTERS \ |
359 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ | |
360 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ | |
361 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \ | |
362 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" | |
363 | #define SPARC32_CP0_REGISTERS \ | |
364 | "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" | |
386c036b | 365 | |
3f7b46f2 IR |
366 | static const char *sparc_core_register_names[] = { SPARC_CORE_REGISTERS }; |
367 | static const char *sparc32_fpu_register_names[] = { SPARC32_FPU_REGISTERS }; | |
368 | static const char *sparc32_cp0_register_names[] = { SPARC32_CP0_REGISTERS }; | |
369 | ||
386c036b | 370 | static const char *sparc32_register_names[] = |
5af923b0 | 371 | { |
7a36499a IR |
372 | SPARC_CORE_REGISTERS, |
373 | SPARC32_FPU_REGISTERS, | |
374 | SPARC32_CP0_REGISTERS | |
5af923b0 MS |
375 | }; |
376 | ||
386c036b MK |
377 | /* Total number of registers. */ |
378 | #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) | |
c906108c | 379 | |
386c036b MK |
380 | /* We provide the aliases %d0..%d30 for the floating registers as |
381 | "psuedo" registers. */ | |
382 | ||
383 | static const char *sparc32_pseudo_register_names[] = | |
384 | { | |
385 | "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", | |
386 | "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" | |
387 | }; | |
388 | ||
389 | /* Total number of pseudo registers. */ | |
390 | #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) | |
391 | ||
7a36499a IR |
392 | /* Return the name of pseudo register REGNUM. */ |
393 | ||
394 | static const char * | |
395 | sparc32_pseudo_register_name (struct gdbarch *gdbarch, int regnum) | |
396 | { | |
397 | regnum -= gdbarch_num_regs (gdbarch); | |
398 | ||
399 | if (regnum < SPARC32_NUM_PSEUDO_REGS) | |
400 | return sparc32_pseudo_register_names[regnum]; | |
401 | ||
402 | internal_error (__FILE__, __LINE__, | |
403 | _("sparc32_pseudo_register_name: bad register number %d"), | |
404 | regnum); | |
405 | } | |
406 | ||
386c036b MK |
407 | /* Return the name of register REGNUM. */ |
408 | ||
409 | static const char * | |
d93859e2 | 410 | sparc32_register_name (struct gdbarch *gdbarch, int regnum) |
386c036b | 411 | { |
3f7b46f2 IR |
412 | if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
413 | return tdesc_register_name (gdbarch, regnum); | |
414 | ||
7a36499a | 415 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) |
386c036b MK |
416 | return sparc32_register_names[regnum]; |
417 | ||
7a36499a | 418 | return sparc32_pseudo_register_name (gdbarch, regnum); |
386c036b | 419 | } |
2d457077 | 420 | \f |
209bd28e | 421 | /* Construct types for ISA-specific registers. */ |
2d457077 | 422 | |
209bd28e UW |
423 | static struct type * |
424 | sparc_psr_type (struct gdbarch *gdbarch) | |
425 | { | |
426 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2d457077 | 427 | |
209bd28e UW |
428 | if (!tdep->sparc_psr_type) |
429 | { | |
430 | struct type *type; | |
2d457077 | 431 | |
77b7c781 | 432 | type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 32); |
209bd28e UW |
433 | append_flags_type_flag (type, 5, "ET"); |
434 | append_flags_type_flag (type, 6, "PS"); | |
435 | append_flags_type_flag (type, 7, "S"); | |
436 | append_flags_type_flag (type, 12, "EF"); | |
437 | append_flags_type_flag (type, 13, "EC"); | |
2d457077 | 438 | |
209bd28e UW |
439 | tdep->sparc_psr_type = type; |
440 | } | |
441 | ||
442 | return tdep->sparc_psr_type; | |
443 | } | |
444 | ||
445 | static struct type * | |
446 | sparc_fsr_type (struct gdbarch *gdbarch) | |
2d457077 | 447 | { |
209bd28e UW |
448 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
449 | ||
450 | if (!tdep->sparc_fsr_type) | |
451 | { | |
452 | struct type *type; | |
453 | ||
77b7c781 | 454 | type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 32); |
209bd28e UW |
455 | append_flags_type_flag (type, 0, "NXA"); |
456 | append_flags_type_flag (type, 1, "DZA"); | |
457 | append_flags_type_flag (type, 2, "UFA"); | |
458 | append_flags_type_flag (type, 3, "OFA"); | |
459 | append_flags_type_flag (type, 4, "NVA"); | |
460 | append_flags_type_flag (type, 5, "NXC"); | |
461 | append_flags_type_flag (type, 6, "DZC"); | |
462 | append_flags_type_flag (type, 7, "UFC"); | |
463 | append_flags_type_flag (type, 8, "OFC"); | |
464 | append_flags_type_flag (type, 9, "NVC"); | |
465 | append_flags_type_flag (type, 22, "NS"); | |
466 | append_flags_type_flag (type, 23, "NXM"); | |
467 | append_flags_type_flag (type, 24, "DZM"); | |
468 | append_flags_type_flag (type, 25, "UFM"); | |
469 | append_flags_type_flag (type, 26, "OFM"); | |
470 | append_flags_type_flag (type, 27, "NVM"); | |
471 | ||
472 | tdep->sparc_fsr_type = type; | |
473 | } | |
474 | ||
475 | return tdep->sparc_fsr_type; | |
2d457077 | 476 | } |
386c036b | 477 | |
7a36499a IR |
478 | /* Return the GDB type object for the "standard" data type of data in |
479 | pseudo register REGNUM. */ | |
480 | ||
481 | static struct type * | |
482 | sparc32_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
483 | { | |
484 | regnum -= gdbarch_num_regs (gdbarch); | |
485 | ||
486 | if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) | |
487 | return builtin_type (gdbarch)->builtin_double; | |
488 | ||
489 | internal_error (__FILE__, __LINE__, | |
490 | _("sparc32_pseudo_register_type: bad register number %d"), | |
491 | regnum); | |
492 | } | |
493 | ||
386c036b | 494 | /* Return the GDB type object for the "standard" data type of data in |
c378eb4e | 495 | register REGNUM. */ |
386c036b MK |
496 | |
497 | static struct type * | |
498 | sparc32_register_type (struct gdbarch *gdbarch, int regnum) | |
499 | { | |
3f7b46f2 IR |
500 | if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
501 | return tdesc_register_type (gdbarch, regnum); | |
502 | ||
386c036b | 503 | if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) |
0dfff4cb | 504 | return builtin_type (gdbarch)->builtin_float; |
386c036b | 505 | |
386c036b | 506 | if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) |
0dfff4cb | 507 | return builtin_type (gdbarch)->builtin_data_ptr; |
386c036b MK |
508 | |
509 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) | |
0dfff4cb | 510 | return builtin_type (gdbarch)->builtin_func_ptr; |
386c036b | 511 | |
2d457077 | 512 | if (regnum == SPARC32_PSR_REGNUM) |
209bd28e | 513 | return sparc_psr_type (gdbarch); |
2d457077 MK |
514 | |
515 | if (regnum == SPARC32_FSR_REGNUM) | |
209bd28e | 516 | return sparc_fsr_type (gdbarch); |
2d457077 | 517 | |
7a36499a IR |
518 | if (regnum >= gdbarch_num_regs (gdbarch)) |
519 | return sparc32_pseudo_register_type (gdbarch, regnum); | |
520 | ||
df4df182 | 521 | return builtin_type (gdbarch)->builtin_int32; |
386c036b MK |
522 | } |
523 | ||
05d1431c | 524 | static enum register_status |
386c036b | 525 | sparc32_pseudo_register_read (struct gdbarch *gdbarch, |
849d0ba8 | 526 | readable_regcache *regcache, |
e1613aba | 527 | int regnum, gdb_byte *buf) |
386c036b | 528 | { |
05d1431c PA |
529 | enum register_status status; |
530 | ||
7a36499a | 531 | regnum -= gdbarch_num_regs (gdbarch); |
386c036b MK |
532 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); |
533 | ||
534 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
03f50fc8 | 535 | status = regcache->raw_read (regnum, buf); |
05d1431c | 536 | if (status == REG_VALID) |
03f50fc8 | 537 | status = regcache->raw_read (regnum + 1, buf + 4); |
05d1431c | 538 | return status; |
386c036b MK |
539 | } |
540 | ||
541 | static void | |
542 | sparc32_pseudo_register_write (struct gdbarch *gdbarch, | |
543 | struct regcache *regcache, | |
e1613aba | 544 | int regnum, const gdb_byte *buf) |
386c036b | 545 | { |
7a36499a | 546 | regnum -= gdbarch_num_regs (gdbarch); |
386c036b MK |
547 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); |
548 | ||
549 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
10eaee5f SM |
550 | regcache->raw_write (regnum, buf); |
551 | regcache->raw_write (regnum + 1, buf + 4); | |
386c036b MK |
552 | } |
553 | \f | |
c9cf6e20 | 554 | /* Implement the stack_frame_destroyed_p gdbarch method. */ |
961842b2 JM |
555 | |
556 | int | |
c9cf6e20 | 557 | sparc_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
961842b2 JM |
558 | { |
559 | /* This function must return true if we are one instruction after an | |
560 | instruction that destroyed the stack frame of the current | |
561 | function. The SPARC instructions used to restore the callers | |
562 | stack frame are RESTORE and RETURN/RETT. | |
563 | ||
564 | Of these RETURN/RETT is a branch instruction and thus we return | |
565 | true if we are in its delay slot. | |
566 | ||
567 | RESTORE is almost always found in the delay slot of a branch | |
568 | instruction that transfers control to the caller, such as JMPL. | |
569 | Thus the next instruction is in the caller frame and we don't | |
570 | need to do anything about it. */ | |
571 | ||
572 | unsigned int insn = sparc_fetch_instruction (pc - 4); | |
573 | ||
574 | return X_RETTURN (insn); | |
575 | } | |
576 | \f | |
386c036b | 577 | |
49a45ecf JB |
578 | static CORE_ADDR |
579 | sparc32_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) | |
580 | { | |
581 | /* The ABI requires double-word alignment. */ | |
582 | return address & ~0x7; | |
583 | } | |
584 | ||
386c036b MK |
585 | static CORE_ADDR |
586 | sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
82585c72 | 587 | CORE_ADDR funcaddr, |
386c036b MK |
588 | struct value **args, int nargs, |
589 | struct type *value_type, | |
e4fd649a UW |
590 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, |
591 | struct regcache *regcache) | |
c906108c | 592 | { |
e17a4113 UW |
593 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
594 | ||
386c036b MK |
595 | *bp_addr = sp - 4; |
596 | *real_pc = funcaddr; | |
597 | ||
d80b854b | 598 | if (using_struct_return (gdbarch, NULL, value_type)) |
c906108c | 599 | { |
e1613aba | 600 | gdb_byte buf[4]; |
386c036b MK |
601 | |
602 | /* This is an UNIMP instruction. */ | |
e17a4113 UW |
603 | store_unsigned_integer (buf, 4, byte_order, |
604 | TYPE_LENGTH (value_type) & 0x1fff); | |
386c036b MK |
605 | write_memory (sp - 8, buf, 4); |
606 | return sp - 8; | |
c906108c SS |
607 | } |
608 | ||
386c036b MK |
609 | return sp - 4; |
610 | } | |
611 | ||
612 | static CORE_ADDR | |
613 | sparc32_store_arguments (struct regcache *regcache, int nargs, | |
614 | struct value **args, CORE_ADDR sp, | |
cf84fa6b AH |
615 | function_call_return_method return_method, |
616 | CORE_ADDR struct_addr) | |
386c036b | 617 | { |
ac7936df | 618 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 619 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
386c036b MK |
620 | /* Number of words in the "parameter array". */ |
621 | int num_elements = 0; | |
622 | int element = 0; | |
623 | int i; | |
624 | ||
625 | for (i = 0; i < nargs; i++) | |
c906108c | 626 | { |
4991999e | 627 | struct type *type = value_type (args[i]); |
386c036b MK |
628 | int len = TYPE_LENGTH (type); |
629 | ||
05bc7456 | 630 | if (sparc_arg_by_memory_p (type)) |
c906108c | 631 | { |
386c036b MK |
632 | /* Structure, Union and Quad-Precision Arguments. */ |
633 | sp -= len; | |
634 | ||
635 | /* Use doubleword alignment for these values. That's always | |
636 | correct, and wasting a few bytes shouldn't be a problem. */ | |
637 | sp &= ~0x7; | |
638 | ||
0fd88904 | 639 | write_memory (sp, value_contents (args[i]), len); |
386c036b MK |
640 | args[i] = value_from_pointer (lookup_pointer_type (type), sp); |
641 | num_elements++; | |
642 | } | |
643 | else if (sparc_floating_p (type)) | |
644 | { | |
645 | /* Floating arguments. */ | |
646 | gdb_assert (len == 4 || len == 8); | |
647 | num_elements += (len / 4); | |
c906108c | 648 | } |
c5aa993b JM |
649 | else |
650 | { | |
05bc7456 | 651 | /* Arguments passed via the General Purpose Registers. */ |
386c036b | 652 | num_elements += ((len + 3) / 4); |
c5aa993b | 653 | } |
c906108c | 654 | } |
c906108c | 655 | |
386c036b | 656 | /* Always allocate at least six words. */ |
325fac50 | 657 | sp -= std::max (6, num_elements) * 4; |
c906108c | 658 | |
386c036b MK |
659 | /* The psABI says that "Software convention requires space for the |
660 | struct/union return value pointer, even if the word is unused." */ | |
661 | sp -= 4; | |
c906108c | 662 | |
386c036b MK |
663 | /* The psABI says that "Although software convention and the |
664 | operating system require every stack frame to be doubleword | |
665 | aligned." */ | |
666 | sp &= ~0x7; | |
c906108c | 667 | |
386c036b | 668 | for (i = 0; i < nargs; i++) |
c906108c | 669 | { |
0fd88904 | 670 | const bfd_byte *valbuf = value_contents (args[i]); |
4991999e | 671 | struct type *type = value_type (args[i]); |
386c036b | 672 | int len = TYPE_LENGTH (type); |
1933fd8e VM |
673 | gdb_byte buf[4]; |
674 | ||
675 | if (len < 4) | |
676 | { | |
677 | memset (buf, 0, 4 - len); | |
678 | memcpy (buf + 4 - len, valbuf, len); | |
679 | valbuf = buf; | |
680 | len = 4; | |
681 | } | |
c906108c | 682 | |
386c036b | 683 | gdb_assert (len == 4 || len == 8); |
c906108c | 684 | |
386c036b MK |
685 | if (element < 6) |
686 | { | |
687 | int regnum = SPARC_O0_REGNUM + element; | |
c906108c | 688 | |
b66f5587 | 689 | regcache->cooked_write (regnum, valbuf); |
386c036b | 690 | if (len > 4 && element < 5) |
b66f5587 | 691 | regcache->cooked_write (regnum + 1, valbuf + 4); |
386c036b | 692 | } |
5af923b0 | 693 | |
386c036b MK |
694 | /* Always store the argument in memory. */ |
695 | write_memory (sp + 4 + element * 4, valbuf, len); | |
696 | element += len / 4; | |
697 | } | |
c906108c | 698 | |
386c036b | 699 | gdb_assert (element == num_elements); |
c906108c | 700 | |
cf84fa6b | 701 | if (return_method == return_method_struct) |
c906108c | 702 | { |
e1613aba | 703 | gdb_byte buf[4]; |
c906108c | 704 | |
e17a4113 | 705 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
386c036b MK |
706 | write_memory (sp, buf, 4); |
707 | } | |
c906108c | 708 | |
386c036b | 709 | return sp; |
c906108c SS |
710 | } |
711 | ||
386c036b | 712 | static CORE_ADDR |
7d9b040b | 713 | sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
386c036b MK |
714 | struct regcache *regcache, CORE_ADDR bp_addr, |
715 | int nargs, struct value **args, CORE_ADDR sp, | |
cf84fa6b AH |
716 | function_call_return_method return_method, |
717 | CORE_ADDR struct_addr) | |
c906108c | 718 | { |
cf84fa6b AH |
719 | CORE_ADDR call_pc = (return_method == return_method_struct |
720 | ? (bp_addr - 12) : (bp_addr - 8)); | |
386c036b MK |
721 | |
722 | /* Set return address. */ | |
723 | regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); | |
724 | ||
725 | /* Set up function arguments. */ | |
cf84fa6b AH |
726 | sp = sparc32_store_arguments (regcache, nargs, args, sp, return_method, |
727 | struct_addr); | |
386c036b MK |
728 | |
729 | /* Allocate the 16-word window save area. */ | |
730 | sp -= 16 * 4; | |
c906108c | 731 | |
386c036b MK |
732 | /* Stack should be doubleword aligned at this point. */ |
733 | gdb_assert (sp % 8 == 0); | |
c906108c | 734 | |
386c036b MK |
735 | /* Finally, update the stack pointer. */ |
736 | regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); | |
737 | ||
738 | return sp; | |
739 | } | |
740 | \f | |
c906108c | 741 | |
386c036b MK |
742 | /* Use the program counter to determine the contents and size of a |
743 | breakpoint instruction. Return a pointer to a string of bytes that | |
744 | encode a breakpoint instruction, store the length of the string in | |
745 | *LEN and optionally adjust *PC to point to the correct memory | |
746 | location for inserting the breakpoint. */ | |
04180708 | 747 | constexpr gdb_byte sparc_break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; |
c5aa993b | 748 | |
04180708 | 749 | typedef BP_MANIPULATION (sparc_break_insn) sparc_breakpoint; |
386c036b | 750 | \f |
c906108c | 751 | |
386c036b | 752 | /* Allocate and initialize a frame cache. */ |
c906108c | 753 | |
386c036b MK |
754 | static struct sparc_frame_cache * |
755 | sparc_alloc_frame_cache (void) | |
756 | { | |
757 | struct sparc_frame_cache *cache; | |
c906108c | 758 | |
386c036b | 759 | cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); |
c906108c | 760 | |
386c036b MK |
761 | /* Base address. */ |
762 | cache->base = 0; | |
763 | cache->pc = 0; | |
c906108c | 764 | |
386c036b MK |
765 | /* Frameless until proven otherwise. */ |
766 | cache->frameless_p = 1; | |
369c397b JB |
767 | cache->frame_offset = 0; |
768 | cache->saved_regs_mask = 0; | |
769 | cache->copied_regs_mask = 0; | |
386c036b MK |
770 | cache->struct_return_p = 0; |
771 | ||
772 | return cache; | |
773 | } | |
774 | ||
b0b92586 JB |
775 | /* GCC generates several well-known sequences of instructions at the begining |
776 | of each function prologue when compiling with -fstack-check. If one of | |
777 | such sequences starts at START_PC, then return the address of the | |
778 | instruction immediately past this sequence. Otherwise, return START_PC. */ | |
779 | ||
780 | static CORE_ADDR | |
781 | sparc_skip_stack_check (const CORE_ADDR start_pc) | |
782 | { | |
783 | CORE_ADDR pc = start_pc; | |
784 | unsigned long insn; | |
2067c8d4 | 785 | int probing_loop = 0; |
b0b92586 JB |
786 | |
787 | /* With GCC, all stack checking sequences begin with the same two | |
2067c8d4 | 788 | instructions, plus an optional one in the case of a probing loop: |
b0b92586 | 789 | |
2067c8d4 JG |
790 | sethi <some immediate>, %g1 |
791 | sub %sp, %g1, %g1 | |
792 | ||
793 | or: | |
794 | ||
795 | sethi <some immediate>, %g1 | |
796 | sethi <some immediate>, %g4 | |
797 | sub %sp, %g1, %g1 | |
798 | ||
799 | or: | |
800 | ||
801 | sethi <some immediate>, %g1 | |
802 | sub %sp, %g1, %g1 | |
803 | sethi <some immediate>, %g4 | |
804 | ||
805 | If the optional instruction is found (setting g4), assume that a | |
806 | probing loop will follow. */ | |
807 | ||
808 | /* sethi <some immediate>, %g1 */ | |
b0b92586 JB |
809 | insn = sparc_fetch_instruction (pc); |
810 | pc = pc + 4; | |
811 | if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1)) | |
812 | return start_pc; | |
813 | ||
2067c8d4 | 814 | /* optional: sethi <some immediate>, %g4 */ |
b0b92586 JB |
815 | insn = sparc_fetch_instruction (pc); |
816 | pc = pc + 4; | |
2067c8d4 JG |
817 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) |
818 | { | |
819 | probing_loop = 1; | |
820 | insn = sparc_fetch_instruction (pc); | |
821 | pc = pc + 4; | |
822 | } | |
823 | ||
824 | /* sub %sp, %g1, %g1 */ | |
b0b92586 JB |
825 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) |
826 | && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1)) | |
827 | return start_pc; | |
828 | ||
829 | insn = sparc_fetch_instruction (pc); | |
830 | pc = pc + 4; | |
831 | ||
2067c8d4 JG |
832 | /* optional: sethi <some immediate>, %g4 */ |
833 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) | |
834 | { | |
835 | probing_loop = 1; | |
836 | insn = sparc_fetch_instruction (pc); | |
837 | pc = pc + 4; | |
838 | } | |
839 | ||
b0b92586 JB |
840 | /* First possible sequence: |
841 | [first two instructions above] | |
842 | clr [%g1 - some immediate] */ | |
843 | ||
844 | /* clr [%g1 - some immediate] */ | |
845 | if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
846 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
847 | { | |
848 | /* Valid stack-check sequence, return the new PC. */ | |
849 | return pc; | |
850 | } | |
851 | ||
852 | /* Second possible sequence: A small number of probes. | |
853 | [first two instructions above] | |
854 | clr [%g1] | |
855 | add %g1, -<some immediate>, %g1 | |
856 | clr [%g1] | |
857 | [repeat the two instructions above any (small) number of times] | |
858 | clr [%g1 - some immediate] */ | |
859 | ||
860 | /* clr [%g1] */ | |
861 | else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
862 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
863 | { | |
864 | while (1) | |
865 | { | |
866 | /* add %g1, -<some immediate>, %g1 */ | |
867 | insn = sparc_fetch_instruction (pc); | |
868 | pc = pc + 4; | |
869 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
870 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
871 | break; | |
872 | ||
873 | /* clr [%g1] */ | |
874 | insn = sparc_fetch_instruction (pc); | |
875 | pc = pc + 4; | |
876 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
877 | && X_RD (insn) == 0 && X_RS1 (insn) == 1)) | |
878 | return start_pc; | |
879 | } | |
880 | ||
881 | /* clr [%g1 - some immediate] */ | |
882 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
883 | && X_RS1 (insn) == 1 && X_RD (insn) == 0)) | |
884 | return start_pc; | |
885 | ||
886 | /* We found a valid stack-check sequence, return the new PC. */ | |
887 | return pc; | |
888 | } | |
889 | ||
890 | /* Third sequence: A probing loop. | |
2067c8d4 | 891 | [first three instructions above] |
b0b92586 JB |
892 | sub %g1, %g4, %g4 |
893 | cmp %g1, %g4 | |
894 | be <disp> | |
895 | add %g1, -<some immediate>, %g1 | |
896 | ba <disp> | |
897 | clr [%g1] | |
2067c8d4 JG |
898 | |
899 | And an optional last probe for the remainder: | |
900 | ||
b0b92586 JB |
901 | clr [%g4 - some immediate] */ |
902 | ||
2067c8d4 | 903 | if (probing_loop) |
b0b92586 JB |
904 | { |
905 | /* sub %g1, %g4, %g4 */ | |
b0b92586 JB |
906 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) |
907 | && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
908 | return start_pc; | |
909 | ||
910 | /* cmp %g1, %g4 */ | |
911 | insn = sparc_fetch_instruction (pc); | |
912 | pc = pc + 4; | |
913 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn) | |
914 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
915 | return start_pc; | |
916 | ||
917 | /* be <disp> */ | |
918 | insn = sparc_fetch_instruction (pc); | |
919 | pc = pc + 4; | |
920 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1)) | |
921 | return start_pc; | |
922 | ||
923 | /* add %g1, -<some immediate>, %g1 */ | |
924 | insn = sparc_fetch_instruction (pc); | |
925 | pc = pc + 4; | |
926 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
927 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
928 | return start_pc; | |
929 | ||
930 | /* ba <disp> */ | |
931 | insn = sparc_fetch_instruction (pc); | |
932 | pc = pc + 4; | |
933 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8)) | |
934 | return start_pc; | |
935 | ||
2067c8d4 | 936 | /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */ |
b0b92586 JB |
937 | insn = sparc_fetch_instruction (pc); |
938 | pc = pc + 4; | |
2067c8d4 JG |
939 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 |
940 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 | |
941 | && (!X_I(insn) || X_SIMM13 (insn) == 0))) | |
b0b92586 JB |
942 | return start_pc; |
943 | ||
2067c8d4 JG |
944 | /* We found a valid stack-check sequence, return the new PC. */ |
945 | ||
946 | /* optional: clr [%g4 - some immediate] */ | |
b0b92586 JB |
947 | insn = sparc_fetch_instruction (pc); |
948 | pc = pc + 4; | |
949 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
950 | && X_RS1 (insn) == 4 && X_RD (insn) == 0)) | |
2067c8d4 JG |
951 | return pc - 4; |
952 | else | |
953 | return pc; | |
b0b92586 JB |
954 | } |
955 | ||
956 | /* No stack check code in our prologue, return the start_pc. */ | |
957 | return start_pc; | |
958 | } | |
959 | ||
369c397b JB |
960 | /* Record the effect of a SAVE instruction on CACHE. */ |
961 | ||
962 | void | |
963 | sparc_record_save_insn (struct sparc_frame_cache *cache) | |
964 | { | |
965 | /* The frame is set up. */ | |
966 | cache->frameless_p = 0; | |
967 | ||
968 | /* The frame pointer contains the CFA. */ | |
969 | cache->frame_offset = 0; | |
970 | ||
971 | /* The `local' and `in' registers are all saved. */ | |
972 | cache->saved_regs_mask = 0xffff; | |
973 | ||
974 | /* The `out' registers are all renamed. */ | |
975 | cache->copied_regs_mask = 0xff; | |
976 | } | |
977 | ||
978 | /* Do a full analysis of the prologue at PC and update CACHE accordingly. | |
979 | Bail out early if CURRENT_PC is reached. Return the address where | |
980 | the analysis stopped. | |
981 | ||
982 | We handle both the traditional register window model and the single | |
983 | register window (aka flat) model. */ | |
984 | ||
386c036b | 985 | CORE_ADDR |
be8626e0 MD |
986 | sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, |
987 | CORE_ADDR current_pc, struct sparc_frame_cache *cache) | |
c906108c | 988 | { |
be8626e0 | 989 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
386c036b MK |
990 | unsigned long insn; |
991 | int offset = 0; | |
c906108c | 992 | int dest = -1; |
c906108c | 993 | |
b0b92586 JB |
994 | pc = sparc_skip_stack_check (pc); |
995 | ||
386c036b MK |
996 | if (current_pc <= pc) |
997 | return current_pc; | |
998 | ||
999 | /* We have to handle to "Procedure Linkage Table" (PLT) special. On | |
1000 | SPARC the linker usually defines a symbol (typically | |
1001 | _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. | |
1002 | This symbol makes us end up here with PC pointing at the start of | |
1003 | the PLT and CURRENT_PC probably pointing at a PLT entry. If we | |
1004 | would do our normal prologue analysis, we would probably conclude | |
1005 | that we've got a frame when in reality we don't, since the | |
1006 | dynamic linker patches up the first PLT with some code that | |
1007 | starts with a SAVE instruction. Patch up PC such that it points | |
1008 | at the start of our PLT entry. */ | |
3e5d3a5a | 1009 | if (tdep->plt_entry_size > 0 && in_plt_section (current_pc)) |
386c036b | 1010 | pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); |
c906108c | 1011 | |
386c036b MK |
1012 | insn = sparc_fetch_instruction (pc); |
1013 | ||
369c397b JB |
1014 | /* Recognize store insns and record their sources. */ |
1015 | while (X_OP (insn) == 3 | |
1016 | && (X_OP3 (insn) == 0x4 /* stw */ | |
1017 | || X_OP3 (insn) == 0x7 /* std */ | |
1018 | || X_OP3 (insn) == 0xe) /* stx */ | |
1019 | && X_RS1 (insn) == SPARC_SP_REGNUM) | |
1020 | { | |
1021 | int regnum = X_RD (insn); | |
1022 | ||
1023 | /* Recognize stores into the corresponding stack slots. */ | |
1024 | if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM | |
1025 | && ((X_I (insn) | |
1026 | && X_SIMM13 (insn) == (X_OP3 (insn) == 0xe | |
1027 | ? (regnum - SPARC_L0_REGNUM) * 8 + BIAS | |
1028 | : (regnum - SPARC_L0_REGNUM) * 4)) | |
1029 | || (!X_I (insn) && regnum == SPARC_L0_REGNUM))) | |
1030 | { | |
1031 | cache->saved_regs_mask |= (1 << (regnum - SPARC_L0_REGNUM)); | |
1032 | if (X_OP3 (insn) == 0x7) | |
1033 | cache->saved_regs_mask |= (1 << (regnum + 1 - SPARC_L0_REGNUM)); | |
1034 | } | |
1035 | ||
1036 | offset += 4; | |
1037 | ||
1038 | insn = sparc_fetch_instruction (pc + offset); | |
1039 | } | |
1040 | ||
386c036b MK |
1041 | /* Recognize a SETHI insn and record its destination. */ |
1042 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) | |
c906108c SS |
1043 | { |
1044 | dest = X_RD (insn); | |
386c036b MK |
1045 | offset += 4; |
1046 | ||
369c397b | 1047 | insn = sparc_fetch_instruction (pc + offset); |
c906108c SS |
1048 | } |
1049 | ||
386c036b MK |
1050 | /* Allow for an arithmetic operation on DEST or %g1. */ |
1051 | if (X_OP (insn) == 2 && X_I (insn) | |
c906108c SS |
1052 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) |
1053 | { | |
386c036b | 1054 | offset += 4; |
c906108c | 1055 | |
369c397b | 1056 | insn = sparc_fetch_instruction (pc + offset); |
c906108c | 1057 | } |
c906108c | 1058 | |
386c036b MK |
1059 | /* Check for the SAVE instruction that sets up the frame. */ |
1060 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) | |
c906108c | 1061 | { |
369c397b JB |
1062 | sparc_record_save_insn (cache); |
1063 | offset += 4; | |
1064 | return pc + offset; | |
1065 | } | |
1066 | ||
1067 | /* Check for an arithmetic operation on %sp. */ | |
1068 | if (X_OP (insn) == 2 | |
1069 | && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) | |
1070 | && X_RS1 (insn) == SPARC_SP_REGNUM | |
1071 | && X_RD (insn) == SPARC_SP_REGNUM) | |
1072 | { | |
1073 | if (X_I (insn)) | |
1074 | { | |
1075 | cache->frame_offset = X_SIMM13 (insn); | |
1076 | if (X_OP3 (insn) == 0) | |
1077 | cache->frame_offset = -cache->frame_offset; | |
1078 | } | |
1079 | offset += 4; | |
1080 | ||
1081 | insn = sparc_fetch_instruction (pc + offset); | |
1082 | ||
1083 | /* Check for an arithmetic operation that sets up the frame. */ | |
1084 | if (X_OP (insn) == 2 | |
1085 | && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) | |
1086 | && X_RS1 (insn) == SPARC_SP_REGNUM | |
1087 | && X_RD (insn) == SPARC_FP_REGNUM) | |
1088 | { | |
1089 | cache->frameless_p = 0; | |
1090 | cache->frame_offset = 0; | |
1091 | /* We could check that the amount subtracted to %sp above is the | |
1092 | same as the one added here, but this seems superfluous. */ | |
1093 | cache->copied_regs_mask |= 0x40; | |
1094 | offset += 4; | |
1095 | ||
1096 | insn = sparc_fetch_instruction (pc + offset); | |
1097 | } | |
1098 | ||
1099 | /* Check for a move (or) operation that copies the return register. */ | |
1100 | if (X_OP (insn) == 2 | |
1101 | && X_OP3 (insn) == 0x2 | |
1102 | && !X_I (insn) | |
1103 | && X_RS1 (insn) == SPARC_G0_REGNUM | |
1104 | && X_RS2 (insn) == SPARC_O7_REGNUM | |
1105 | && X_RD (insn) == SPARC_I7_REGNUM) | |
1106 | { | |
1107 | cache->copied_regs_mask |= 0x80; | |
1108 | offset += 4; | |
1109 | } | |
1110 | ||
1111 | return pc + offset; | |
c906108c SS |
1112 | } |
1113 | ||
1114 | return pc; | |
1115 | } | |
1116 | ||
386c036b MK |
1117 | /* Return PC of first real instruction of the function starting at |
1118 | START_PC. */ | |
f510d44e | 1119 | |
386c036b | 1120 | static CORE_ADDR |
6093d2eb | 1121 | sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1122 | { |
f510d44e DM |
1123 | struct symtab_and_line sal; |
1124 | CORE_ADDR func_start, func_end; | |
386c036b | 1125 | struct sparc_frame_cache cache; |
f510d44e DM |
1126 | |
1127 | /* This is the preferred method, find the end of the prologue by | |
1128 | using the debugging information. */ | |
1129 | if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) | |
1130 | { | |
1131 | sal = find_pc_line (func_start, 0); | |
1132 | ||
1133 | if (sal.end < func_end | |
1134 | && start_pc <= sal.end) | |
1135 | return sal.end; | |
1136 | } | |
1137 | ||
be8626e0 | 1138 | start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache); |
075ccec8 MK |
1139 | |
1140 | /* The psABI says that "Although the first 6 words of arguments | |
1141 | reside in registers, the standard stack frame reserves space for | |
1142 | them.". It also suggests that a function may use that space to | |
1143 | "write incoming arguments 0 to 5" into that space, and that's | |
1144 | indeed what GCC seems to be doing. In that case GCC will | |
1145 | generate debug information that points to the stack slots instead | |
1146 | of the registers, so we should consider the instructions that | |
369c397b | 1147 | write out these incoming arguments onto the stack. */ |
075ccec8 | 1148 | |
369c397b | 1149 | while (1) |
075ccec8 MK |
1150 | { |
1151 | unsigned long insn = sparc_fetch_instruction (start_pc); | |
1152 | ||
369c397b JB |
1153 | /* Recognize instructions that store incoming arguments into the |
1154 | corresponding stack slots. */ | |
1155 | if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 | |
1156 | && X_I (insn) && X_RS1 (insn) == SPARC_FP_REGNUM) | |
075ccec8 | 1157 | { |
369c397b JB |
1158 | int regnum = X_RD (insn); |
1159 | ||
1160 | /* Case of arguments still in %o[0..5]. */ | |
1161 | if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O5_REGNUM | |
1162 | && !(cache.copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM))) | |
1163 | && X_SIMM13 (insn) == 68 + (regnum - SPARC_O0_REGNUM) * 4) | |
1164 | { | |
1165 | start_pc += 4; | |
1166 | continue; | |
1167 | } | |
1168 | ||
1169 | /* Case of arguments copied into %i[0..5]. */ | |
1170 | if (regnum >= SPARC_I0_REGNUM && regnum <= SPARC_I5_REGNUM | |
1171 | && (cache.copied_regs_mask & (1 << (regnum - SPARC_I0_REGNUM))) | |
1172 | && X_SIMM13 (insn) == 68 + (regnum - SPARC_I0_REGNUM) * 4) | |
1173 | { | |
1174 | start_pc += 4; | |
1175 | continue; | |
1176 | } | |
075ccec8 MK |
1177 | } |
1178 | ||
1179 | break; | |
1180 | } | |
1181 | ||
1182 | return start_pc; | |
c906108c SS |
1183 | } |
1184 | ||
386c036b | 1185 | /* Normal frames. */ |
9319a2fe | 1186 | |
386c036b | 1187 | struct sparc_frame_cache * |
236369e7 | 1188 | sparc_frame_cache (struct frame_info *this_frame, void **this_cache) |
9319a2fe | 1189 | { |
386c036b | 1190 | struct sparc_frame_cache *cache; |
9319a2fe | 1191 | |
386c036b | 1192 | if (*this_cache) |
19ba03f4 | 1193 | return (struct sparc_frame_cache *) *this_cache; |
c906108c | 1194 | |
386c036b MK |
1195 | cache = sparc_alloc_frame_cache (); |
1196 | *this_cache = cache; | |
c906108c | 1197 | |
236369e7 | 1198 | cache->pc = get_frame_func (this_frame); |
386c036b | 1199 | if (cache->pc != 0) |
236369e7 JB |
1200 | sparc_analyze_prologue (get_frame_arch (this_frame), cache->pc, |
1201 | get_frame_pc (this_frame), cache); | |
386c036b MK |
1202 | |
1203 | if (cache->frameless_p) | |
c906108c | 1204 | { |
cbeae229 MK |
1205 | /* This function is frameless, so %fp (%i6) holds the frame |
1206 | pointer for our calling frame. Use %sp (%o6) as this frame's | |
1207 | base address. */ | |
1208 | cache->base = | |
236369e7 | 1209 | get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
cbeae229 MK |
1210 | } |
1211 | else | |
1212 | { | |
1213 | /* For normal frames, %fp (%i6) holds the frame pointer, the | |
1214 | base address for the current stack frame. */ | |
1215 | cache->base = | |
236369e7 | 1216 | get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM); |
c906108c | 1217 | } |
c906108c | 1218 | |
369c397b JB |
1219 | cache->base += cache->frame_offset; |
1220 | ||
5b2d44a0 MK |
1221 | if (cache->base & 1) |
1222 | cache->base += BIAS; | |
1223 | ||
386c036b | 1224 | return cache; |
c906108c | 1225 | } |
c906108c | 1226 | |
aff37fc1 DM |
1227 | static int |
1228 | sparc32_struct_return_from_sym (struct symbol *sym) | |
1229 | { | |
1230 | struct type *type = check_typedef (SYMBOL_TYPE (sym)); | |
78134374 | 1231 | enum type_code code = type->code (); |
aff37fc1 DM |
1232 | |
1233 | if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) | |
1234 | { | |
1235 | type = check_typedef (TYPE_TARGET_TYPE (type)); | |
1236 | if (sparc_structure_or_union_p (type) | |
1237 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
1238 | return 1; | |
1239 | } | |
1240 | ||
1241 | return 0; | |
1242 | } | |
1243 | ||
386c036b | 1244 | struct sparc_frame_cache * |
236369e7 | 1245 | sparc32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 1246 | { |
386c036b MK |
1247 | struct sparc_frame_cache *cache; |
1248 | struct symbol *sym; | |
c906108c | 1249 | |
386c036b | 1250 | if (*this_cache) |
19ba03f4 | 1251 | return (struct sparc_frame_cache *) *this_cache; |
c906108c | 1252 | |
236369e7 | 1253 | cache = sparc_frame_cache (this_frame, this_cache); |
c906108c | 1254 | |
386c036b MK |
1255 | sym = find_pc_function (cache->pc); |
1256 | if (sym) | |
c906108c | 1257 | { |
aff37fc1 | 1258 | cache->struct_return_p = sparc32_struct_return_from_sym (sym); |
c906108c | 1259 | } |
5465445a JB |
1260 | else |
1261 | { | |
1262 | /* There is no debugging information for this function to | |
1263 | help us determine whether this function returns a struct | |
1264 | or not. So we rely on another heuristic which is to check | |
1265 | the instruction at the return address and see if this is | |
1266 | an "unimp" instruction. If it is, then it is a struct-return | |
1267 | function. */ | |
1268 | CORE_ADDR pc; | |
369c397b JB |
1269 | int regnum = |
1270 | (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; | |
5465445a | 1271 | |
236369e7 | 1272 | pc = get_frame_register_unsigned (this_frame, regnum) + 8; |
5465445a JB |
1273 | if (sparc_is_unimp_insn (pc)) |
1274 | cache->struct_return_p = 1; | |
1275 | } | |
c906108c | 1276 | |
386c036b MK |
1277 | return cache; |
1278 | } | |
1279 | ||
1280 | static void | |
236369e7 | 1281 | sparc32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
386c036b MK |
1282 | struct frame_id *this_id) |
1283 | { | |
1284 | struct sparc_frame_cache *cache = | |
236369e7 | 1285 | sparc32_frame_cache (this_frame, this_cache); |
386c036b MK |
1286 | |
1287 | /* This marks the outermost frame. */ | |
1288 | if (cache->base == 0) | |
1289 | return; | |
1290 | ||
1291 | (*this_id) = frame_id_build (cache->base, cache->pc); | |
1292 | } | |
c906108c | 1293 | |
236369e7 JB |
1294 | static struct value * |
1295 | sparc32_frame_prev_register (struct frame_info *this_frame, | |
1296 | void **this_cache, int regnum) | |
386c036b | 1297 | { |
e17a4113 | 1298 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
386c036b | 1299 | struct sparc_frame_cache *cache = |
236369e7 | 1300 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 1301 | |
386c036b | 1302 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) |
c906108c | 1303 | { |
236369e7 | 1304 | CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; |
386c036b | 1305 | |
236369e7 JB |
1306 | /* If this functions has a Structure, Union or Quad-Precision |
1307 | return value, we have to skip the UNIMP instruction that encodes | |
1308 | the size of the structure. */ | |
1309 | if (cache->struct_return_p) | |
1310 | pc += 4; | |
386c036b | 1311 | |
369c397b JB |
1312 | regnum = |
1313 | (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; | |
236369e7 JB |
1314 | pc += get_frame_register_unsigned (this_frame, regnum) + 8; |
1315 | return frame_unwind_got_constant (this_frame, regnum, pc); | |
c906108c SS |
1316 | } |
1317 | ||
42cdca6c MK |
1318 | /* Handle StackGhost. */ |
1319 | { | |
e17a4113 | 1320 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
42cdca6c MK |
1321 | |
1322 | if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM) | |
1323 | { | |
236369e7 JB |
1324 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
1325 | ULONGEST i7; | |
1326 | ||
1327 | /* Read the value in from memory. */ | |
1328 | i7 = get_frame_memory_unsigned (this_frame, addr, 4); | |
1329 | return frame_unwind_got_constant (this_frame, regnum, i7 ^ wcookie); | |
42cdca6c MK |
1330 | } |
1331 | } | |
1332 | ||
369c397b | 1333 | /* The previous frame's `local' and `in' registers may have been saved |
386c036b | 1334 | in the register save area. */ |
369c397b JB |
1335 | if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM |
1336 | && (cache->saved_regs_mask & (1 << (regnum - SPARC_L0_REGNUM)))) | |
c906108c | 1337 | { |
236369e7 | 1338 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
386c036b | 1339 | |
236369e7 | 1340 | return frame_unwind_got_memory (this_frame, regnum, addr); |
386c036b | 1341 | } |
c906108c | 1342 | |
369c397b JB |
1343 | /* The previous frame's `out' registers may be accessible as the current |
1344 | frame's `in' registers. */ | |
1345 | if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM | |
1346 | && (cache->copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM)))) | |
386c036b | 1347 | regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); |
5af923b0 | 1348 | |
236369e7 | 1349 | return frame_unwind_got_register (this_frame, regnum, regnum); |
386c036b | 1350 | } |
c906108c | 1351 | |
386c036b MK |
1352 | static const struct frame_unwind sparc32_frame_unwind = |
1353 | { | |
1354 | NORMAL_FRAME, | |
8fbca658 | 1355 | default_frame_unwind_stop_reason, |
386c036b | 1356 | sparc32_frame_this_id, |
236369e7 JB |
1357 | sparc32_frame_prev_register, |
1358 | NULL, | |
1359 | default_frame_sniffer | |
386c036b | 1360 | }; |
386c036b | 1361 | \f |
c906108c | 1362 | |
386c036b | 1363 | static CORE_ADDR |
236369e7 | 1364 | sparc32_frame_base_address (struct frame_info *this_frame, void **this_cache) |
386c036b MK |
1365 | { |
1366 | struct sparc_frame_cache *cache = | |
236369e7 | 1367 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 1368 | |
386c036b MK |
1369 | return cache->base; |
1370 | } | |
c906108c | 1371 | |
386c036b MK |
1372 | static const struct frame_base sparc32_frame_base = |
1373 | { | |
1374 | &sparc32_frame_unwind, | |
1375 | sparc32_frame_base_address, | |
1376 | sparc32_frame_base_address, | |
1377 | sparc32_frame_base_address | |
1378 | }; | |
c906108c | 1379 | |
386c036b | 1380 | static struct frame_id |
236369e7 | 1381 | sparc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
386c036b MK |
1382 | { |
1383 | CORE_ADDR sp; | |
5af923b0 | 1384 | |
236369e7 | 1385 | sp = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
5b2d44a0 MK |
1386 | if (sp & 1) |
1387 | sp += BIAS; | |
236369e7 | 1388 | return frame_id_build (sp, get_frame_pc (this_frame)); |
386c036b MK |
1389 | } |
1390 | \f | |
c906108c | 1391 | |
3923a2b2 MK |
1392 | /* Extract a function return value of TYPE from REGCACHE, and copy |
1393 | that into VALBUF. */ | |
5af923b0 | 1394 | |
386c036b MK |
1395 | static void |
1396 | sparc32_extract_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1397 | gdb_byte *valbuf) |
386c036b MK |
1398 | { |
1399 | int len = TYPE_LENGTH (type); | |
fe10a582 | 1400 | gdb_byte buf[32]; |
c906108c | 1401 | |
1933fd8e | 1402 | gdb_assert (!sparc_structure_return_p (type)); |
c906108c | 1403 | |
1933fd8e | 1404 | if (sparc_floating_p (type) || sparc_complex_floating_p (type) |
78134374 | 1405 | || type->code () == TYPE_CODE_ARRAY) |
5af923b0 | 1406 | { |
386c036b | 1407 | /* Floating return values. */ |
dca08e1f | 1408 | regcache->cooked_read (SPARC_F0_REGNUM, buf); |
386c036b | 1409 | if (len > 4) |
dca08e1f | 1410 | regcache->cooked_read (SPARC_F1_REGNUM, buf + 4); |
fe10a582 DM |
1411 | if (len > 8) |
1412 | { | |
dca08e1f SM |
1413 | regcache->cooked_read (SPARC_F2_REGNUM, buf + 8); |
1414 | regcache->cooked_read (SPARC_F3_REGNUM, buf + 12); | |
fe10a582 DM |
1415 | } |
1416 | if (len > 16) | |
1417 | { | |
dca08e1f SM |
1418 | regcache->cooked_read (SPARC_F4_REGNUM, buf + 16); |
1419 | regcache->cooked_read (SPARC_F5_REGNUM, buf + 20); | |
1420 | regcache->cooked_read (SPARC_F6_REGNUM, buf + 24); | |
1421 | regcache->cooked_read (SPARC_F7_REGNUM, buf + 28); | |
fe10a582 | 1422 | } |
386c036b | 1423 | memcpy (valbuf, buf, len); |
5af923b0 MS |
1424 | } |
1425 | else | |
1426 | { | |
386c036b MK |
1427 | /* Integral and pointer return values. */ |
1428 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
c906108c | 1429 | |
dca08e1f | 1430 | regcache->cooked_read (SPARC_O0_REGNUM, buf); |
386c036b MK |
1431 | if (len > 4) |
1432 | { | |
dca08e1f | 1433 | regcache->cooked_read (SPARC_O1_REGNUM, buf + 4); |
386c036b MK |
1434 | gdb_assert (len == 8); |
1435 | memcpy (valbuf, buf, 8); | |
1436 | } | |
1437 | else | |
1438 | { | |
1439 | /* Just stripping off any unused bytes should preserve the | |
1440 | signed-ness just fine. */ | |
1441 | memcpy (valbuf, buf + 4 - len, len); | |
1442 | } | |
1443 | } | |
1444 | } | |
c906108c | 1445 | |
3923a2b2 MK |
1446 | /* Store the function return value of type TYPE from VALBUF into |
1447 | REGCACHE. */ | |
c906108c | 1448 | |
386c036b MK |
1449 | static void |
1450 | sparc32_store_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1451 | const gdb_byte *valbuf) |
386c036b MK |
1452 | { |
1453 | int len = TYPE_LENGTH (type); | |
1933fd8e | 1454 | gdb_byte buf[32]; |
c906108c | 1455 | |
1933fd8e | 1456 | gdb_assert (!sparc_structure_return_p (type)); |
c906108c | 1457 | |
fe10a582 | 1458 | if (sparc_floating_p (type) || sparc_complex_floating_p (type)) |
386c036b MK |
1459 | { |
1460 | /* Floating return values. */ | |
1461 | memcpy (buf, valbuf, len); | |
b66f5587 | 1462 | regcache->cooked_write (SPARC_F0_REGNUM, buf); |
386c036b | 1463 | if (len > 4) |
b66f5587 | 1464 | regcache->cooked_write (SPARC_F1_REGNUM, buf + 4); |
fe10a582 DM |
1465 | if (len > 8) |
1466 | { | |
b66f5587 SM |
1467 | regcache->cooked_write (SPARC_F2_REGNUM, buf + 8); |
1468 | regcache->cooked_write (SPARC_F3_REGNUM, buf + 12); | |
fe10a582 DM |
1469 | } |
1470 | if (len > 16) | |
1471 | { | |
b66f5587 SM |
1472 | regcache->cooked_write (SPARC_F4_REGNUM, buf + 16); |
1473 | regcache->cooked_write (SPARC_F5_REGNUM, buf + 20); | |
1474 | regcache->cooked_write (SPARC_F6_REGNUM, buf + 24); | |
1475 | regcache->cooked_write (SPARC_F7_REGNUM, buf + 28); | |
fe10a582 | 1476 | } |
386c036b MK |
1477 | } |
1478 | else | |
c906108c | 1479 | { |
386c036b MK |
1480 | /* Integral and pointer return values. */ |
1481 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
1482 | ||
1483 | if (len > 4) | |
2757dd86 | 1484 | { |
386c036b MK |
1485 | gdb_assert (len == 8); |
1486 | memcpy (buf, valbuf, 8); | |
b66f5587 | 1487 | regcache->cooked_write (SPARC_O1_REGNUM, buf + 4); |
2757dd86 AC |
1488 | } |
1489 | else | |
1490 | { | |
386c036b MK |
1491 | /* ??? Do we need to do any sign-extension here? */ |
1492 | memcpy (buf + 4 - len, valbuf, len); | |
2757dd86 | 1493 | } |
b66f5587 | 1494 | regcache->cooked_write (SPARC_O0_REGNUM, buf); |
c906108c SS |
1495 | } |
1496 | } | |
1497 | ||
b9d4c5ed | 1498 | static enum return_value_convention |
6a3a010b | 1499 | sparc32_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
1500 | struct type *type, struct regcache *regcache, |
1501 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
b9d4c5ed | 1502 | { |
e17a4113 UW |
1503 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1504 | ||
0a8f48b9 MK |
1505 | /* The psABI says that "...every stack frame reserves the word at |
1506 | %fp+64. If a function returns a structure, union, or | |
1507 | quad-precision value, this word should hold the address of the | |
1508 | object into which the return value should be copied." This | |
1509 | guarantees that we can always find the return value, not just | |
1510 | before the function returns. */ | |
1511 | ||
1933fd8e | 1512 | if (sparc_structure_return_p (type)) |
0a8f48b9 | 1513 | { |
bbfdfe1c DM |
1514 | ULONGEST sp; |
1515 | CORE_ADDR addr; | |
1516 | ||
0a8f48b9 MK |
1517 | if (readbuf) |
1518 | { | |
0a8f48b9 | 1519 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); |
e17a4113 | 1520 | addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); |
0a8f48b9 MK |
1521 | read_memory (addr, readbuf, TYPE_LENGTH (type)); |
1522 | } | |
bbfdfe1c DM |
1523 | if (writebuf) |
1524 | { | |
1525 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1526 | addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); | |
1527 | write_memory (addr, writebuf, TYPE_LENGTH (type)); | |
1528 | } | |
0a8f48b9 MK |
1529 | |
1530 | return RETURN_VALUE_ABI_PRESERVES_ADDRESS; | |
1531 | } | |
b9d4c5ed MK |
1532 | |
1533 | if (readbuf) | |
1534 | sparc32_extract_return_value (type, regcache, readbuf); | |
1535 | if (writebuf) | |
1536 | sparc32_store_return_value (type, regcache, writebuf); | |
1537 | ||
1538 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1539 | } | |
1540 | ||
386c036b MK |
1541 | static int |
1542 | sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) | |
c906108c | 1543 | { |
386c036b | 1544 | return (sparc_structure_or_union_p (type) |
fe10a582 DM |
1545 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16) |
1546 | || sparc_complex_floating_p (type)); | |
386c036b | 1547 | } |
c906108c | 1548 | |
aff37fc1 | 1549 | static int |
4a4e5149 | 1550 | sparc32_dwarf2_struct_return_p (struct frame_info *this_frame) |
aff37fc1 | 1551 | { |
236369e7 | 1552 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
aff37fc1 DM |
1553 | struct symbol *sym = find_pc_function (pc); |
1554 | ||
1555 | if (sym) | |
1556 | return sparc32_struct_return_from_sym (sym); | |
1557 | return 0; | |
1558 | } | |
1559 | ||
f5a9b87d DM |
1560 | static void |
1561 | sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 | 1562 | struct dwarf2_frame_state_reg *reg, |
4a4e5149 | 1563 | struct frame_info *this_frame) |
f5a9b87d | 1564 | { |
aff37fc1 DM |
1565 | int off; |
1566 | ||
f5a9b87d DM |
1567 | switch (regnum) |
1568 | { | |
1569 | case SPARC_G0_REGNUM: | |
1570 | /* Since %g0 is always zero, there is no point in saving it, and | |
1571 | people will be inclined omit it from the CFI. Make sure we | |
1572 | don't warn about that. */ | |
1573 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
1574 | break; | |
1575 | case SPARC_SP_REGNUM: | |
1576 | reg->how = DWARF2_FRAME_REG_CFA; | |
1577 | break; | |
1578 | case SPARC32_PC_REGNUM: | |
f5a9b87d DM |
1579 | case SPARC32_NPC_REGNUM: |
1580 | reg->how = DWARF2_FRAME_REG_RA_OFFSET; | |
aff37fc1 | 1581 | off = 8; |
4a4e5149 | 1582 | if (sparc32_dwarf2_struct_return_p (this_frame)) |
aff37fc1 DM |
1583 | off += 4; |
1584 | if (regnum == SPARC32_NPC_REGNUM) | |
1585 | off += 4; | |
1586 | reg->loc.offset = off; | |
f5a9b87d DM |
1587 | break; |
1588 | } | |
1589 | } | |
1590 | ||
b41c5a85 JW |
1591 | /* Implement the execute_dwarf_cfa_vendor_op method. */ |
1592 | ||
1593 | static bool | |
1594 | sparc_execute_dwarf_cfa_vendor_op (struct gdbarch *gdbarch, gdb_byte op, | |
1595 | struct dwarf2_frame_state *fs) | |
1596 | { | |
1597 | /* Only DW_CFA_GNU_window_save is expected on SPARC. */ | |
1598 | if (op != DW_CFA_GNU_window_save) | |
1599 | return false; | |
1600 | ||
1601 | uint64_t reg; | |
1602 | int size = register_size (gdbarch, 0); | |
1603 | ||
1c90d9f0 | 1604 | fs->regs.alloc_regs (32); |
b41c5a85 JW |
1605 | for (reg = 8; reg < 16; reg++) |
1606 | { | |
1607 | fs->regs.reg[reg].how = DWARF2_FRAME_REG_SAVED_REG; | |
1608 | fs->regs.reg[reg].loc.reg = reg + 16; | |
1609 | } | |
1610 | for (reg = 16; reg < 32; reg++) | |
1611 | { | |
1612 | fs->regs.reg[reg].how = DWARF2_FRAME_REG_SAVED_OFFSET; | |
1613 | fs->regs.reg[reg].loc.offset = (reg - 16) * size; | |
1614 | } | |
1615 | ||
1616 | return true; | |
1617 | } | |
1618 | ||
386c036b MK |
1619 | \f |
1620 | /* The SPARC Architecture doesn't have hardware single-step support, | |
1621 | and most operating systems don't implement it either, so we provide | |
1622 | software single-step mechanism. */ | |
c906108c | 1623 | |
386c036b | 1624 | static CORE_ADDR |
cd76b525 | 1625 | sparc_analyze_control_transfer (struct regcache *regcache, |
c893be75 | 1626 | CORE_ADDR pc, CORE_ADDR *npc) |
386c036b MK |
1627 | { |
1628 | unsigned long insn = sparc_fetch_instruction (pc); | |
1629 | int conditional_p = X_COND (insn) & 0x7; | |
8d1b3521 | 1630 | int branch_p = 0, fused_p = 0; |
386c036b | 1631 | long offset = 0; /* Must be signed for sign-extend. */ |
c906108c | 1632 | |
8d1b3521 | 1633 | if (X_OP (insn) == 0 && X_OP2 (insn) == 3) |
c906108c | 1634 | { |
8d1b3521 DM |
1635 | if ((insn & 0x10000000) == 0) |
1636 | { | |
1637 | /* Branch on Integer Register with Prediction (BPr). */ | |
1638 | branch_p = 1; | |
1639 | conditional_p = 1; | |
1640 | } | |
1641 | else | |
1642 | { | |
1643 | /* Compare and Branch */ | |
1644 | branch_p = 1; | |
1645 | fused_p = 1; | |
1646 | offset = 4 * X_DISP10 (insn); | |
1647 | } | |
c906108c | 1648 | } |
386c036b | 1649 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) |
c906108c | 1650 | { |
386c036b MK |
1651 | /* Branch on Floating-Point Condition Codes (FBfcc). */ |
1652 | branch_p = 1; | |
1653 | offset = 4 * X_DISP22 (insn); | |
c906108c | 1654 | } |
386c036b MK |
1655 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) |
1656 | { | |
1657 | /* Branch on Floating-Point Condition Codes with Prediction | |
1658 | (FBPfcc). */ | |
1659 | branch_p = 1; | |
1660 | offset = 4 * X_DISP19 (insn); | |
1661 | } | |
1662 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) | |
1663 | { | |
1664 | /* Branch on Integer Condition Codes (Bicc). */ | |
1665 | branch_p = 1; | |
1666 | offset = 4 * X_DISP22 (insn); | |
1667 | } | |
1668 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) | |
c906108c | 1669 | { |
386c036b MK |
1670 | /* Branch on Integer Condition Codes with Prediction (BPcc). */ |
1671 | branch_p = 1; | |
1672 | offset = 4 * X_DISP19 (insn); | |
c906108c | 1673 | } |
c893be75 MK |
1674 | else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a) |
1675 | { | |
cd76b525 YQ |
1676 | struct frame_info *frame = get_current_frame (); |
1677 | ||
c893be75 | 1678 | /* Trap instruction (TRAP). */ |
ac7936df | 1679 | return gdbarch_tdep (regcache->arch ())->step_trap (frame, |
cd76b525 | 1680 | insn); |
c893be75 | 1681 | } |
386c036b MK |
1682 | |
1683 | /* FIXME: Handle DONE and RETRY instructions. */ | |
1684 | ||
386c036b | 1685 | if (branch_p) |
c906108c | 1686 | { |
8d1b3521 DM |
1687 | if (fused_p) |
1688 | { | |
1689 | /* Fused compare-and-branch instructions are non-delayed, | |
85102364 | 1690 | and do not have an annulling capability. So we need to |
8d1b3521 DM |
1691 | always set a breakpoint on both the NPC and the branch |
1692 | target address. */ | |
1693 | gdb_assert (offset != 0); | |
1694 | return pc + offset; | |
1695 | } | |
1696 | else if (conditional_p) | |
c906108c | 1697 | { |
386c036b MK |
1698 | /* For conditional branches, return nPC + 4 iff the annul |
1699 | bit is 1. */ | |
1700 | return (X_A (insn) ? *npc + 4 : 0); | |
c906108c SS |
1701 | } |
1702 | else | |
1703 | { | |
386c036b MK |
1704 | /* For unconditional branches, return the target if its |
1705 | specified condition is "always" and return nPC + 4 if the | |
1706 | condition is "never". If the annul bit is 1, set *NPC to | |
1707 | zero. */ | |
1708 | if (X_COND (insn) == 0x0) | |
1709 | pc = *npc, offset = 4; | |
1710 | if (X_A (insn)) | |
1711 | *npc = 0; | |
1712 | ||
386c036b | 1713 | return pc + offset; |
c906108c SS |
1714 | } |
1715 | } | |
386c036b MK |
1716 | |
1717 | return 0; | |
c906108c SS |
1718 | } |
1719 | ||
c893be75 | 1720 | static CORE_ADDR |
0b1b3e42 | 1721 | sparc_step_trap (struct frame_info *frame, unsigned long insn) |
c893be75 MK |
1722 | { |
1723 | return 0; | |
1724 | } | |
1725 | ||
a0ff9e1a | 1726 | static std::vector<CORE_ADDR> |
f5ea389a | 1727 | sparc_software_single_step (struct regcache *regcache) |
386c036b | 1728 | { |
ac7936df | 1729 | struct gdbarch *arch = regcache->arch (); |
c893be75 | 1730 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
8181d85f | 1731 | CORE_ADDR npc, nnpc; |
c906108c | 1732 | |
e0cd558a | 1733 | CORE_ADDR pc, orig_npc; |
a0ff9e1a | 1734 | std::vector<CORE_ADDR> next_pcs; |
c906108c | 1735 | |
cd76b525 YQ |
1736 | pc = regcache_raw_get_unsigned (regcache, tdep->pc_regnum); |
1737 | orig_npc = npc = regcache_raw_get_unsigned (regcache, tdep->npc_regnum); | |
c906108c | 1738 | |
e0cd558a | 1739 | /* Analyze the instruction at PC. */ |
cd76b525 | 1740 | nnpc = sparc_analyze_control_transfer (regcache, pc, &npc); |
e0cd558a | 1741 | if (npc != 0) |
a0ff9e1a | 1742 | next_pcs.push_back (npc); |
8181d85f | 1743 | |
e0cd558a | 1744 | if (nnpc != 0) |
a0ff9e1a | 1745 | next_pcs.push_back (nnpc); |
c906108c | 1746 | |
e0cd558a UW |
1747 | /* Assert that we have set at least one breakpoint, and that |
1748 | they're not set at the same spot - unless we're going | |
1749 | from here straight to NULL, i.e. a call or jump to 0. */ | |
1750 | gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0); | |
1751 | gdb_assert (nnpc != npc || orig_npc == 0); | |
e6590a1b | 1752 | |
93f9a11f | 1753 | return next_pcs; |
386c036b MK |
1754 | } |
1755 | ||
1756 | static void | |
61a1198a | 1757 | sparc_write_pc (struct regcache *regcache, CORE_ADDR pc) |
386c036b | 1758 | { |
ac7936df | 1759 | struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); |
386c036b | 1760 | |
61a1198a UW |
1761 | regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc); |
1762 | regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4); | |
386c036b MK |
1763 | } |
1764 | \f | |
5af923b0 | 1765 | |
e5139de8 | 1766 | /* Iterate over core file register note sections. */ |
a54124c5 | 1767 | |
e5139de8 AA |
1768 | static void |
1769 | sparc_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
1770 | iterate_over_regset_sections_cb *cb, | |
1771 | void *cb_data, | |
1772 | const struct regcache *regcache) | |
a54124c5 MK |
1773 | { |
1774 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1775 | ||
a616bb94 AH |
1776 | cb (".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL, |
1777 | cb_data); | |
1778 | cb (".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, | |
1779 | NULL, cb_data); | |
a54124c5 MK |
1780 | } |
1781 | \f | |
1782 | ||
3f7b46f2 IR |
1783 | static int |
1784 | validate_tdesc_registers (const struct target_desc *tdesc, | |
1785 | struct tdesc_arch_data *tdesc_data, | |
1786 | const char *feature_name, | |
1787 | const char *register_names[], | |
1788 | unsigned int registers_num, | |
1789 | unsigned int reg_start) | |
1790 | { | |
1791 | int valid_p = 1; | |
1792 | const struct tdesc_feature *feature; | |
1793 | ||
1794 | feature = tdesc_find_feature (tdesc, feature_name); | |
1795 | if (feature == NULL) | |
1796 | return 0; | |
1797 | ||
1798 | for (unsigned int i = 0; i < registers_num; i++) | |
1799 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1800 | reg_start + i, | |
1801 | register_names[i]); | |
1802 | ||
1803 | return valid_p; | |
1804 | } | |
1805 | ||
386c036b MK |
1806 | static struct gdbarch * |
1807 | sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1808 | { | |
1809 | struct gdbarch_tdep *tdep; | |
3f7b46f2 | 1810 | const struct target_desc *tdesc = info.target_desc; |
386c036b | 1811 | struct gdbarch *gdbarch; |
3f7b46f2 | 1812 | int valid_p = 1; |
c906108c | 1813 | |
386c036b MK |
1814 | /* If there is already a candidate, use it. */ |
1815 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1816 | if (arches != NULL) | |
1817 | return arches->gdbarch; | |
c906108c | 1818 | |
386c036b | 1819 | /* Allocate space for the new architecture. */ |
41bf6aca | 1820 | tdep = XCNEW (struct gdbarch_tdep); |
386c036b | 1821 | gdbarch = gdbarch_alloc (&info, tdep); |
5af923b0 | 1822 | |
386c036b MK |
1823 | tdep->pc_regnum = SPARC32_PC_REGNUM; |
1824 | tdep->npc_regnum = SPARC32_NPC_REGNUM; | |
c893be75 | 1825 | tdep->step_trap = sparc_step_trap; |
3f7b46f2 IR |
1826 | tdep->fpu_register_names = sparc32_fpu_register_names; |
1827 | tdep->fpu_registers_num = ARRAY_SIZE (sparc32_fpu_register_names); | |
1828 | tdep->cp0_register_names = sparc32_cp0_register_names; | |
1829 | tdep->cp0_registers_num = ARRAY_SIZE (sparc32_cp0_register_names); | |
386c036b MK |
1830 | |
1831 | set_gdbarch_long_double_bit (gdbarch, 128); | |
8da61cc4 | 1832 | set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad); |
386c036b | 1833 | |
53375380 PA |
1834 | set_gdbarch_wchar_bit (gdbarch, 16); |
1835 | set_gdbarch_wchar_signed (gdbarch, 1); | |
1836 | ||
386c036b MK |
1837 | set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); |
1838 | set_gdbarch_register_name (gdbarch, sparc32_register_name); | |
1839 | set_gdbarch_register_type (gdbarch, sparc32_register_type); | |
1840 | set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); | |
3f7b46f2 IR |
1841 | set_tdesc_pseudo_register_name (gdbarch, sparc32_pseudo_register_name); |
1842 | set_tdesc_pseudo_register_type (gdbarch, sparc32_pseudo_register_type); | |
386c036b MK |
1843 | set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); |
1844 | set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); | |
1845 | ||
1846 | /* Register numbers of various important registers. */ | |
1847 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ | |
1848 | set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ | |
1849 | set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ | |
1850 | ||
1851 | /* Call dummy code. */ | |
49a45ecf | 1852 | set_gdbarch_frame_align (gdbarch, sparc32_frame_align); |
386c036b MK |
1853 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
1854 | set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); | |
1855 | set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); | |
1856 | ||
b9d4c5ed | 1857 | set_gdbarch_return_value (gdbarch, sparc32_return_value); |
386c036b MK |
1858 | set_gdbarch_stabs_argument_has_addr |
1859 | (gdbarch, sparc32_stabs_argument_has_addr); | |
1860 | ||
1861 | set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); | |
1862 | ||
1863 | /* Stack grows downward. */ | |
1864 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
c906108c | 1865 | |
04180708 YQ |
1866 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
1867 | sparc_breakpoint::kind_from_pc); | |
1868 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
1869 | sparc_breakpoint::bp_from_kind); | |
c906108c | 1870 | |
386c036b | 1871 | set_gdbarch_frame_args_skip (gdbarch, 8); |
5af923b0 | 1872 | |
386c036b MK |
1873 | set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); |
1874 | set_gdbarch_write_pc (gdbarch, sparc_write_pc); | |
c906108c | 1875 | |
236369e7 | 1876 | set_gdbarch_dummy_id (gdbarch, sparc_dummy_id); |
c906108c | 1877 | |
386c036b MK |
1878 | frame_base_set_default (gdbarch, &sparc32_frame_base); |
1879 | ||
f5a9b87d DM |
1880 | /* Hook in the DWARF CFI frame unwinder. */ |
1881 | dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg); | |
b41c5a85 JW |
1882 | /* Register DWARF vendor CFI handler. */ |
1883 | set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch, | |
1884 | sparc_execute_dwarf_cfa_vendor_op); | |
f5a9b87d DM |
1885 | /* FIXME: kettenis/20050423: Don't enable the unwinder until the |
1886 | StackGhost issues have been resolved. */ | |
1887 | ||
b2a0b9b2 DM |
1888 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1889 | gdbarch_init_osabi (info, gdbarch); | |
1890 | ||
236369e7 | 1891 | frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind); |
c906108c | 1892 | |
3f7b46f2 IR |
1893 | if (tdesc_has_registers (tdesc)) |
1894 | { | |
1895 | struct tdesc_arch_data *tdesc_data = tdesc_data_alloc (); | |
1896 | ||
1897 | /* Validate that the descriptor provides the mandatory registers | |
1898 | and allocate their numbers. */ | |
1899 | valid_p &= validate_tdesc_registers (tdesc, tdesc_data, | |
1900 | "org.gnu.gdb.sparc.cpu", | |
1901 | sparc_core_register_names, | |
1902 | ARRAY_SIZE (sparc_core_register_names), | |
1903 | SPARC_G0_REGNUM); | |
1904 | valid_p &= validate_tdesc_registers (tdesc, tdesc_data, | |
1905 | "org.gnu.gdb.sparc.fpu", | |
1906 | tdep->fpu_register_names, | |
1907 | tdep->fpu_registers_num, | |
1908 | SPARC_F0_REGNUM); | |
1909 | valid_p &= validate_tdesc_registers (tdesc, tdesc_data, | |
1910 | "org.gnu.gdb.sparc.cp0", | |
1911 | tdep->cp0_register_names, | |
1912 | tdep->cp0_registers_num, | |
1291063d JM |
1913 | SPARC_F0_REGNUM |
1914 | + tdep->fpu_registers_num); | |
3f7b46f2 IR |
1915 | if (!valid_p) |
1916 | { | |
1917 | tdesc_data_cleanup (tdesc_data); | |
1918 | return NULL; | |
1919 | } | |
1920 | ||
1921 | /* Target description may have changed. */ | |
0dba2a6c | 1922 | info.tdesc_data = tdesc_data; |
3f7b46f2 IR |
1923 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
1924 | } | |
1925 | ||
a54124c5 | 1926 | /* If we have register sets, enable the generic core file support. */ |
4c72d57a | 1927 | if (tdep->gregset) |
e5139de8 AA |
1928 | set_gdbarch_iterate_over_regset_sections |
1929 | (gdbarch, sparc_iterate_over_regset_sections); | |
a54124c5 | 1930 | |
7e35103a JB |
1931 | register_sparc_ravenscar_ops (gdbarch); |
1932 | ||
386c036b MK |
1933 | return gdbarch; |
1934 | } | |
1935 | \f | |
1936 | /* Helper functions for dealing with register windows. */ | |
1937 | ||
1938 | void | |
1939 | sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) | |
c906108c | 1940 | { |
ac7936df | 1941 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 1942 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
386c036b | 1943 | int offset = 0; |
e1613aba | 1944 | gdb_byte buf[8]; |
386c036b MK |
1945 | int i; |
1946 | ||
1947 | if (sp & 1) | |
1948 | { | |
1949 | /* Registers are 64-bit. */ | |
1950 | sp += BIAS; | |
c906108c | 1951 | |
386c036b MK |
1952 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1953 | { | |
1954 | if (regnum == i || regnum == -1) | |
1955 | { | |
1956 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); | |
f700a364 MK |
1957 | |
1958 | /* Handle StackGhost. */ | |
1959 | if (i == SPARC_I7_REGNUM) | |
1960 | { | |
e17a4113 UW |
1961 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1962 | ULONGEST i7; | |
f700a364 | 1963 | |
e17a4113 UW |
1964 | i7 = extract_unsigned_integer (buf + offset, 8, byte_order); |
1965 | store_unsigned_integer (buf + offset, 8, byte_order, | |
1966 | i7 ^ wcookie); | |
f700a364 MK |
1967 | } |
1968 | ||
73e1c03f | 1969 | regcache->raw_supply (i, buf); |
386c036b MK |
1970 | } |
1971 | } | |
1972 | } | |
1973 | else | |
c906108c | 1974 | { |
386c036b MK |
1975 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1976 | pointer. */ | |
1977 | sp &= 0xffffffffUL; | |
c906108c | 1978 | |
386c036b MK |
1979 | /* Clear out the top half of the temporary buffer, and put the |
1980 | register value in the bottom half if we're in 64-bit mode. */ | |
ac7936df | 1981 | if (gdbarch_ptr_bit (regcache->arch ()) == 64) |
c906108c | 1982 | { |
386c036b MK |
1983 | memset (buf, 0, 4); |
1984 | offset = 4; | |
1985 | } | |
c906108c | 1986 | |
386c036b MK |
1987 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1988 | { | |
1989 | if (regnum == i || regnum == -1) | |
1990 | { | |
1991 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), | |
1992 | buf + offset, 4); | |
42cdca6c MK |
1993 | |
1994 | /* Handle StackGhost. */ | |
1995 | if (i == SPARC_I7_REGNUM) | |
1996 | { | |
e17a4113 UW |
1997 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1998 | ULONGEST i7; | |
42cdca6c | 1999 | |
e17a4113 UW |
2000 | i7 = extract_unsigned_integer (buf + offset, 4, byte_order); |
2001 | store_unsigned_integer (buf + offset, 4, byte_order, | |
2002 | i7 ^ wcookie); | |
42cdca6c MK |
2003 | } |
2004 | ||
73e1c03f | 2005 | regcache->raw_supply (i, buf); |
386c036b | 2006 | } |
c906108c SS |
2007 | } |
2008 | } | |
c906108c | 2009 | } |
c906108c SS |
2010 | |
2011 | void | |
386c036b MK |
2012 | sparc_collect_rwindow (const struct regcache *regcache, |
2013 | CORE_ADDR sp, int regnum) | |
c906108c | 2014 | { |
ac7936df | 2015 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 2016 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
386c036b | 2017 | int offset = 0; |
e1613aba | 2018 | gdb_byte buf[8]; |
386c036b | 2019 | int i; |
5af923b0 | 2020 | |
386c036b | 2021 | if (sp & 1) |
5af923b0 | 2022 | { |
386c036b MK |
2023 | /* Registers are 64-bit. */ |
2024 | sp += BIAS; | |
c906108c | 2025 | |
386c036b MK |
2026 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
2027 | { | |
2028 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
2029 | { | |
34a79281 | 2030 | regcache->raw_collect (i, buf); |
f700a364 MK |
2031 | |
2032 | /* Handle StackGhost. */ | |
2033 | if (i == SPARC_I7_REGNUM) | |
2034 | { | |
e17a4113 UW |
2035 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
2036 | ULONGEST i7; | |
f700a364 | 2037 | |
e17a4113 UW |
2038 | i7 = extract_unsigned_integer (buf + offset, 8, byte_order); |
2039 | store_unsigned_integer (buf, 8, byte_order, i7 ^ wcookie); | |
f700a364 MK |
2040 | } |
2041 | ||
386c036b MK |
2042 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); |
2043 | } | |
2044 | } | |
5af923b0 MS |
2045 | } |
2046 | else | |
2047 | { | |
386c036b MK |
2048 | /* Registers are 32-bit. Toss any sign-extension of the stack |
2049 | pointer. */ | |
2050 | sp &= 0xffffffffUL; | |
2051 | ||
2052 | /* Only use the bottom half if we're in 64-bit mode. */ | |
ac7936df | 2053 | if (gdbarch_ptr_bit (regcache->arch ()) == 64) |
386c036b MK |
2054 | offset = 4; |
2055 | ||
2056 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
2057 | { | |
2058 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
2059 | { | |
34a79281 | 2060 | regcache->raw_collect (i, buf); |
42cdca6c MK |
2061 | |
2062 | /* Handle StackGhost. */ | |
2063 | if (i == SPARC_I7_REGNUM) | |
2064 | { | |
e17a4113 UW |
2065 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
2066 | ULONGEST i7; | |
42cdca6c | 2067 | |
e17a4113 UW |
2068 | i7 = extract_unsigned_integer (buf + offset, 4, byte_order); |
2069 | store_unsigned_integer (buf + offset, 4, byte_order, | |
2070 | i7 ^ wcookie); | |
42cdca6c MK |
2071 | } |
2072 | ||
386c036b MK |
2073 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), |
2074 | buf + offset, 4); | |
2075 | } | |
2076 | } | |
5af923b0 | 2077 | } |
c906108c SS |
2078 | } |
2079 | ||
386c036b MK |
2080 | /* Helper functions for dealing with register sets. */ |
2081 | ||
c906108c | 2082 | void |
b4fd25c9 | 2083 | sparc32_supply_gregset (const struct sparc_gregmap *gregmap, |
386c036b MK |
2084 | struct regcache *regcache, |
2085 | int regnum, const void *gregs) | |
c906108c | 2086 | { |
19ba03f4 | 2087 | const gdb_byte *regs = (const gdb_byte *) gregs; |
22e74ef9 | 2088 | gdb_byte zero[4] = { 0 }; |
386c036b | 2089 | int i; |
5af923b0 | 2090 | |
386c036b | 2091 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
73e1c03f | 2092 | regcache->raw_supply (SPARC32_PSR_REGNUM, regs + gregmap->r_psr_offset); |
c906108c | 2093 | |
386c036b | 2094 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
73e1c03f | 2095 | regcache->raw_supply (SPARC32_PC_REGNUM, regs + gregmap->r_pc_offset); |
5af923b0 | 2096 | |
386c036b | 2097 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) |
73e1c03f | 2098 | regcache->raw_supply (SPARC32_NPC_REGNUM, regs + gregmap->r_npc_offset); |
5af923b0 | 2099 | |
386c036b | 2100 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
73e1c03f | 2101 | regcache->raw_supply (SPARC32_Y_REGNUM, regs + gregmap->r_y_offset); |
5af923b0 | 2102 | |
386c036b | 2103 | if (regnum == SPARC_G0_REGNUM || regnum == -1) |
73e1c03f | 2104 | regcache->raw_supply (SPARC_G0_REGNUM, &zero); |
5af923b0 | 2105 | |
386c036b | 2106 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) |
c906108c | 2107 | { |
b4fd25c9 | 2108 | int offset = gregmap->r_g1_offset; |
386c036b MK |
2109 | |
2110 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
2111 | { | |
2112 | if (regnum == i || regnum == -1) | |
73e1c03f | 2113 | regcache->raw_supply (i, regs + offset); |
386c036b MK |
2114 | offset += 4; |
2115 | } | |
c906108c | 2116 | } |
386c036b MK |
2117 | |
2118 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
c906108c | 2119 | { |
386c036b MK |
2120 | /* Not all of the register set variants include Locals and |
2121 | Inputs. For those that don't, we read them off the stack. */ | |
b4fd25c9 | 2122 | if (gregmap->r_l0_offset == -1) |
386c036b MK |
2123 | { |
2124 | ULONGEST sp; | |
2125 | ||
2126 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
2127 | sparc_supply_rwindow (regcache, sp, regnum); | |
2128 | } | |
2129 | else | |
2130 | { | |
b4fd25c9 | 2131 | int offset = gregmap->r_l0_offset; |
386c036b MK |
2132 | |
2133 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
2134 | { | |
2135 | if (regnum == i || regnum == -1) | |
73e1c03f | 2136 | regcache->raw_supply (i, regs + offset); |
386c036b MK |
2137 | offset += 4; |
2138 | } | |
2139 | } | |
c906108c SS |
2140 | } |
2141 | } | |
2142 | ||
c5aa993b | 2143 | void |
b4fd25c9 | 2144 | sparc32_collect_gregset (const struct sparc_gregmap *gregmap, |
386c036b MK |
2145 | const struct regcache *regcache, |
2146 | int regnum, void *gregs) | |
c906108c | 2147 | { |
19ba03f4 | 2148 | gdb_byte *regs = (gdb_byte *) gregs; |
386c036b | 2149 | int i; |
c5aa993b | 2150 | |
386c036b | 2151 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
34a79281 | 2152 | regcache->raw_collect (SPARC32_PSR_REGNUM, regs + gregmap->r_psr_offset); |
60054393 | 2153 | |
386c036b | 2154 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
34a79281 | 2155 | regcache->raw_collect (SPARC32_PC_REGNUM, regs + gregmap->r_pc_offset); |
386c036b MK |
2156 | |
2157 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) | |
34a79281 | 2158 | regcache->raw_collect (SPARC32_NPC_REGNUM, regs + gregmap->r_npc_offset); |
5af923b0 | 2159 | |
386c036b | 2160 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
34a79281 | 2161 | regcache->raw_collect (SPARC32_Y_REGNUM, regs + gregmap->r_y_offset); |
386c036b MK |
2162 | |
2163 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) | |
5af923b0 | 2164 | { |
b4fd25c9 | 2165 | int offset = gregmap->r_g1_offset; |
386c036b MK |
2166 | |
2167 | /* %g0 is always zero. */ | |
2168 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
2169 | { | |
2170 | if (regnum == i || regnum == -1) | |
34a79281 | 2171 | regcache->raw_collect (i, regs + offset); |
386c036b MK |
2172 | offset += 4; |
2173 | } | |
5af923b0 | 2174 | } |
386c036b MK |
2175 | |
2176 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
5af923b0 | 2177 | { |
386c036b MK |
2178 | /* Not all of the register set variants include Locals and |
2179 | Inputs. For those that don't, we read them off the stack. */ | |
b4fd25c9 | 2180 | if (gregmap->r_l0_offset != -1) |
386c036b | 2181 | { |
b4fd25c9 | 2182 | int offset = gregmap->r_l0_offset; |
386c036b MK |
2183 | |
2184 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
2185 | { | |
2186 | if (regnum == i || regnum == -1) | |
34a79281 | 2187 | regcache->raw_collect (i, regs + offset); |
386c036b MK |
2188 | offset += 4; |
2189 | } | |
2190 | } | |
5af923b0 | 2191 | } |
c906108c SS |
2192 | } |
2193 | ||
c906108c | 2194 | void |
b4fd25c9 | 2195 | sparc32_supply_fpregset (const struct sparc_fpregmap *fpregmap, |
db75c717 | 2196 | struct regcache *regcache, |
386c036b | 2197 | int regnum, const void *fpregs) |
c906108c | 2198 | { |
19ba03f4 | 2199 | const gdb_byte *regs = (const gdb_byte *) fpregs; |
386c036b | 2200 | int i; |
60054393 | 2201 | |
386c036b | 2202 | for (i = 0; i < 32; i++) |
c906108c | 2203 | { |
386c036b | 2204 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) |
73e1c03f SM |
2205 | regcache->raw_supply (SPARC_F0_REGNUM + i, |
2206 | regs + fpregmap->r_f0_offset + (i * 4)); | |
c906108c | 2207 | } |
5af923b0 | 2208 | |
386c036b | 2209 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
73e1c03f | 2210 | regcache->raw_supply (SPARC32_FSR_REGNUM, regs + fpregmap->r_fsr_offset); |
c906108c SS |
2211 | } |
2212 | ||
386c036b | 2213 | void |
b4fd25c9 | 2214 | sparc32_collect_fpregset (const struct sparc_fpregmap *fpregmap, |
db75c717 | 2215 | const struct regcache *regcache, |
386c036b | 2216 | int regnum, void *fpregs) |
c906108c | 2217 | { |
19ba03f4 | 2218 | gdb_byte *regs = (gdb_byte *) fpregs; |
386c036b | 2219 | int i; |
c906108c | 2220 | |
386c036b MK |
2221 | for (i = 0; i < 32; i++) |
2222 | { | |
2223 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) | |
34a79281 SM |
2224 | regcache->raw_collect (SPARC_F0_REGNUM + i, |
2225 | regs + fpregmap->r_f0_offset + (i * 4)); | |
386c036b | 2226 | } |
c906108c | 2227 | |
386c036b | 2228 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
34a79281 SM |
2229 | regcache->raw_collect (SPARC32_FSR_REGNUM, |
2230 | regs + fpregmap->r_fsr_offset); | |
c906108c | 2231 | } |
c906108c | 2232 | \f |
c906108c | 2233 | |
386c036b | 2234 | /* SunOS 4. */ |
c906108c | 2235 | |
386c036b | 2236 | /* From <machine/reg.h>. */ |
b4fd25c9 | 2237 | const struct sparc_gregmap sparc32_sunos4_gregmap = |
c906108c | 2238 | { |
386c036b MK |
2239 | 0 * 4, /* %psr */ |
2240 | 1 * 4, /* %pc */ | |
2241 | 2 * 4, /* %npc */ | |
2242 | 3 * 4, /* %y */ | |
2243 | -1, /* %wim */ | |
2244 | -1, /* %tbr */ | |
2245 | 4 * 4, /* %g1 */ | |
2246 | -1 /* %l0 */ | |
2247 | }; | |
db75c717 | 2248 | |
b4fd25c9 | 2249 | const struct sparc_fpregmap sparc32_sunos4_fpregmap = |
db75c717 DM |
2250 | { |
2251 | 0 * 4, /* %f0 */ | |
2252 | 33 * 4, /* %fsr */ | |
2253 | }; | |
2254 | ||
b4fd25c9 | 2255 | const struct sparc_fpregmap sparc32_bsd_fpregmap = |
db75c717 DM |
2256 | { |
2257 | 0 * 4, /* %f0 */ | |
2258 | 32 * 4, /* %fsr */ | |
2259 | }; | |
c906108c | 2260 | |
6c265988 | 2261 | void _initialize_sparc_tdep (); |
c906108c | 2262 | void |
6c265988 | 2263 | _initialize_sparc_tdep () |
c906108c | 2264 | { |
386c036b | 2265 | register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init); |
ef3cf062 | 2266 | } |