Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the SPARC for GDB, the GNU debugger. |
cda5a58a AC |
2 | |
3 | Copyright 1986, 1987, 1989, 1990, 1991, 1992, 1993, 1994, 1995, | |
1e698235 | 4 | 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, |
cda5a58a | 5 | Inc. |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b JM |
19 | You should have received a copy of the GNU General Public License |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 59 Temple Place - Suite 330, | |
22 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
23 | |
24 | /* ??? Support for calling functions from gdb in sparc64 is unfinished. */ | |
25 | ||
26 | #include "defs.h" | |
5af923b0 | 27 | #include "arch-utils.h" |
c906108c SS |
28 | #include "frame.h" |
29 | #include "inferior.h" | |
c906108c SS |
30 | #include "target.h" |
31 | #include "value.h" | |
32 | #include "bfd.h" | |
33 | #include "gdb_string.h" | |
4e052eda | 34 | #include "regcache.h" |
ef3cf062 | 35 | #include "osabi.h" |
c906108c SS |
36 | |
37 | #ifdef USE_PROC_FS | |
38 | #include <sys/procfs.h> | |
13437d4b KB |
39 | /* Prototypes for supply_gregset etc. */ |
40 | #include "gregset.h" | |
c906108c SS |
41 | #endif |
42 | ||
43 | #include "gdbcore.h" | |
43bd9a9e | 44 | #include "gdb_assert.h" |
c906108c | 45 | |
5af923b0 MS |
46 | #include "symfile.h" /* for 'entry_point_address' */ |
47 | ||
4eb8c7fc DM |
48 | /* |
49 | * Some local macros that have multi-arch and non-multi-arch versions: | |
50 | */ | |
51 | ||
52 | #if (GDB_MULTI_ARCH > 0) | |
53 | ||
07020390 AC |
54 | #if 0 |
55 | // OBSOLETE /* Does the target have Floating Point registers? */ | |
56 | // OBSOLETE #define SPARC_HAS_FPU (gdbarch_tdep (current_gdbarch)->has_fpu) | |
57 | #endif | |
58 | #define SPARC_HAS_FPU 1 | |
4eb8c7fc DM |
59 | /* Number of bytes devoted to Floating Point registers: */ |
60 | #define FP_REGISTER_BYTES (gdbarch_tdep (current_gdbarch)->fp_register_bytes) | |
61 | /* Highest numbered Floating Point register. */ | |
62 | #define FP_MAX_REGNUM (gdbarch_tdep (current_gdbarch)->fp_max_regnum) | |
63 | /* Size of a general (integer) register: */ | |
64 | #define SPARC_INTREG_SIZE (gdbarch_tdep (current_gdbarch)->intreg_size) | |
65 | /* Offset within the call dummy stack of the saved registers. */ | |
66 | #define DUMMY_REG_SAVE_OFFSET (gdbarch_tdep (current_gdbarch)->reg_save_offset) | |
67 | ||
68 | #else /* non-multi-arch */ | |
69 | ||
70 | ||
71 | /* Does the target have Floating Point registers? */ | |
f81824a9 AC |
72 | #if 0 |
73 | // OBSOLETE #if defined(TARGET_SPARCLET) || defined(TARGET_SPARCLITE) | |
74 | // OBSOLETE #define SPARC_HAS_FPU 0 | |
75 | // OBSOLETE #else | |
76 | // OBSOLETE #define SPARC_HAS_FPU 1 | |
77 | // OBSOLETE #endif | |
4eb8c7fc | 78 | #endif |
f81824a9 | 79 | #define SPARC_HAS_FPU 1 |
4eb8c7fc DM |
80 | |
81 | /* Number of bytes devoted to Floating Point registers: */ | |
82 | #if (GDB_TARGET_IS_SPARC64) | |
83 | #define FP_REGISTER_BYTES (64 * 4) | |
84 | #else | |
85 | #if (SPARC_HAS_FPU) | |
86 | #define FP_REGISTER_BYTES (32 * 4) | |
87 | #else | |
88 | #define FP_REGISTER_BYTES 0 | |
89 | #endif | |
90 | #endif | |
91 | ||
92 | /* Highest numbered Floating Point register. */ | |
93 | #if (GDB_TARGET_IS_SPARC64) | |
94 | #define FP_MAX_REGNUM (FP0_REGNUM + 48) | |
95 | #else | |
96 | #define FP_MAX_REGNUM (FP0_REGNUM + 32) | |
97 | #endif | |
98 | ||
99 | /* Size of a general (integer) register: */ | |
100 | #define SPARC_INTREG_SIZE (REGISTER_RAW_SIZE (G0_REGNUM)) | |
101 | ||
102 | /* Offset within the call dummy stack of the saved registers. */ | |
103 | #if (GDB_TARGET_IS_SPARC64) | |
104 | #define DUMMY_REG_SAVE_OFFSET (128 + 16) | |
105 | #else | |
106 | #define DUMMY_REG_SAVE_OFFSET 0x60 | |
107 | #endif | |
108 | ||
109 | #endif /* GDB_MULTI_ARCH */ | |
110 | ||
111 | struct gdbarch_tdep | |
112 | { | |
f81824a9 AC |
113 | #if 0 |
114 | // OBSOLETE int has_fpu; | |
115 | #endif | |
4eb8c7fc DM |
116 | int fp_register_bytes; |
117 | int y_regnum; | |
118 | int fp_max_regnum; | |
119 | int intreg_size; | |
120 | int reg_save_offset; | |
121 | int call_dummy_call_offset; | |
122 | int print_insn_mach; | |
123 | }; | |
5af923b0 MS |
124 | |
125 | /* Now make GDB_TARGET_IS_SPARC64 a runtime test. */ | |
126 | /* FIXME MVS: or try testing bfd_arch_info.arch and bfd_arch_info.mach ... | |
127 | * define GDB_TARGET_IS_SPARC64 \ | |
128 | * (TARGET_ARCHITECTURE->arch == bfd_arch_sparc && \ | |
129 | * (TARGET_ARCHITECTURE->mach == bfd_mach_sparc_v9 || \ | |
130 | * TARGET_ARCHITECTURE->mach == bfd_mach_sparc_v9a)) | |
131 | */ | |
132 | ||
c906108c SS |
133 | /* From infrun.c */ |
134 | extern int stop_after_trap; | |
135 | ||
136 | /* We don't store all registers immediately when requested, since they | |
137 | get sent over in large chunks anyway. Instead, we accumulate most | |
138 | of the changes and send them over once. "deferred_stores" keeps | |
139 | track of which sets of registers we have locally-changed copies of, | |
140 | so we only need send the groups that have changed. */ | |
141 | ||
5af923b0 | 142 | int deferred_stores = 0; /* Accumulated stores we want to do eventually. */ |
c906108c SS |
143 | |
144 | ||
f81824a9 AC |
145 | #if 0 |
146 | // OBSOLETE /* Some machines, such as Fujitsu SPARClite 86x, have a bi-endian mode | |
147 | // OBSOLETE where instructions are big-endian and data are little-endian. | |
148 | // OBSOLETE This flag is set when we detect that the target is of this type. */ | |
149 | // OBSOLETE | |
150 | // OBSOLETE int bi_endian = 0; | |
151 | #endif | |
c906108c SS |
152 | |
153 | ||
aaab4dba AC |
154 | const unsigned char * |
155 | sparc_breakpoint_from_pc (CORE_ADDR *pc, int *len) | |
156 | { | |
157 | static const char breakpoint[] = {0x91, 0xd0, 0x20, 0x01}; | |
158 | (*len) = sizeof (breakpoint); | |
159 | return breakpoint; | |
160 | } | |
161 | ||
c906108c SS |
162 | /* Fetch a single instruction. Even on bi-endian machines |
163 | such as sparc86x, instructions are always big-endian. */ | |
164 | ||
165 | static unsigned long | |
fba45db2 | 166 | fetch_instruction (CORE_ADDR pc) |
c906108c SS |
167 | { |
168 | unsigned long retval; | |
169 | int i; | |
170 | unsigned char buf[4]; | |
171 | ||
172 | read_memory (pc, buf, sizeof (buf)); | |
173 | ||
174 | /* Start at the most significant end of the integer, and work towards | |
175 | the least significant. */ | |
176 | retval = 0; | |
177 | for (i = 0; i < sizeof (buf); ++i) | |
178 | retval = (retval << 8) | buf[i]; | |
179 | return retval; | |
180 | } | |
181 | ||
182 | ||
183 | /* Branches with prediction are treated like their non-predicting cousins. */ | |
184 | /* FIXME: What about floating point branches? */ | |
185 | ||
186 | /* Macros to extract fields from sparc instructions. */ | |
187 | #define X_OP(i) (((i) >> 30) & 0x3) | |
188 | #define X_RD(i) (((i) >> 25) & 0x1f) | |
189 | #define X_A(i) (((i) >> 29) & 1) | |
190 | #define X_COND(i) (((i) >> 25) & 0xf) | |
191 | #define X_OP2(i) (((i) >> 22) & 0x7) | |
192 | #define X_IMM22(i) ((i) & 0x3fffff) | |
193 | #define X_OP3(i) (((i) >> 19) & 0x3f) | |
194 | #define X_RS1(i) (((i) >> 14) & 0x1f) | |
195 | #define X_I(i) (((i) >> 13) & 1) | |
196 | #define X_IMM13(i) ((i) & 0x1fff) | |
197 | /* Sign extension macros. */ | |
198 | #define X_SIMM13(i) ((X_IMM13 (i) ^ 0x1000) - 0x1000) | |
199 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) | |
200 | #define X_CC(i) (((i) >> 20) & 3) | |
201 | #define X_P(i) (((i) >> 19) & 1) | |
202 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) | |
203 | #define X_RCOND(i) (((i) >> 25) & 7) | |
204 | #define X_DISP16(i) ((((((i) >> 6) && 0xc000) | ((i) & 0x3fff)) ^ 0x8000) - 0x8000) | |
205 | #define X_FCN(i) (((i) >> 25) & 31) | |
206 | ||
207 | typedef enum | |
208 | { | |
5af923b0 MS |
209 | Error, not_branch, bicc, bicca, ba, baa, ticc, ta, done_retry |
210 | } branch_type; | |
c906108c SS |
211 | |
212 | /* Simulate single-step ptrace call for sun4. Code written by Gary | |
213 | Beihl (beihl@mcc.com). */ | |
214 | ||
215 | /* npc4 and next_pc describe the situation at the time that the | |
216 | step-breakpoint was set, not necessary the current value of NPC_REGNUM. */ | |
217 | static CORE_ADDR next_pc, npc4, target; | |
218 | static int brknpc4, brktrg; | |
219 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
220 | static binsn_quantum break_mem[3]; | |
221 | ||
5af923b0 | 222 | static branch_type isbranch (long, CORE_ADDR, CORE_ADDR *); |
c906108c SS |
223 | |
224 | /* single_step() is called just before we want to resume the inferior, | |
225 | if we want to single-step it but there is no hardware or kernel single-step | |
226 | support (as on all SPARCs). We find all the possible targets of the | |
227 | coming instruction and breakpoint them. | |
228 | ||
229 | single_step is also called just after the inferior stops. If we had | |
230 | set up a simulated single-step, we undo our damage. */ | |
231 | ||
232 | void | |
fba45db2 KB |
233 | sparc_software_single_step (enum target_signal ignore, /* pid, but we don't need it */ |
234 | int insert_breakpoints_p) | |
c906108c SS |
235 | { |
236 | branch_type br; | |
237 | CORE_ADDR pc; | |
238 | long pc_instruction; | |
239 | ||
240 | if (insert_breakpoints_p) | |
241 | { | |
242 | /* Always set breakpoint for NPC. */ | |
243 | next_pc = read_register (NPC_REGNUM); | |
c5aa993b | 244 | npc4 = next_pc + 4; /* branch not taken */ |
c906108c SS |
245 | |
246 | target_insert_breakpoint (next_pc, break_mem[0]); | |
247 | /* printf_unfiltered ("set break at %x\n",next_pc); */ | |
248 | ||
249 | pc = read_register (PC_REGNUM); | |
250 | pc_instruction = fetch_instruction (pc); | |
251 | br = isbranch (pc_instruction, pc, &target); | |
252 | brknpc4 = brktrg = 0; | |
253 | ||
254 | if (br == bicca) | |
255 | { | |
256 | /* Conditional annulled branch will either end up at | |
257 | npc (if taken) or at npc+4 (if not taken). | |
258 | Trap npc+4. */ | |
259 | brknpc4 = 1; | |
260 | target_insert_breakpoint (npc4, break_mem[1]); | |
261 | } | |
262 | else if (br == baa && target != next_pc) | |
263 | { | |
264 | /* Unconditional annulled branch will always end up at | |
265 | the target. */ | |
266 | brktrg = 1; | |
267 | target_insert_breakpoint (target, break_mem[2]); | |
268 | } | |
5af923b0 | 269 | else if (GDB_TARGET_IS_SPARC64 && br == done_retry) |
c906108c SS |
270 | { |
271 | brktrg = 1; | |
272 | target_insert_breakpoint (target, break_mem[2]); | |
273 | } | |
c906108c SS |
274 | } |
275 | else | |
276 | { | |
277 | /* Remove breakpoints */ | |
278 | target_remove_breakpoint (next_pc, break_mem[0]); | |
279 | ||
280 | if (brknpc4) | |
281 | target_remove_breakpoint (npc4, break_mem[1]); | |
282 | ||
283 | if (brktrg) | |
284 | target_remove_breakpoint (target, break_mem[2]); | |
285 | } | |
286 | } | |
287 | \f | |
5af923b0 MS |
288 | struct frame_extra_info |
289 | { | |
290 | CORE_ADDR bottom; | |
291 | int in_prologue; | |
292 | int flat; | |
293 | /* Following fields only relevant for flat frames. */ | |
294 | CORE_ADDR pc_addr; | |
295 | CORE_ADDR fp_addr; | |
296 | /* Add this to ->frame to get the value of the stack pointer at the | |
297 | time of the register saves. */ | |
298 | int sp_offset; | |
299 | }; | |
300 | ||
301 | /* Call this for each newly created frame. For SPARC, we need to | |
302 | calculate the bottom of the frame, and do some extra work if the | |
303 | prologue has been generated via the -mflat option to GCC. In | |
304 | particular, we need to know where the previous fp and the pc have | |
305 | been stashed, since their exact position within the frame may vary. */ | |
c906108c SS |
306 | |
307 | void | |
fba45db2 | 308 | sparc_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c SS |
309 | { |
310 | char *name; | |
311 | CORE_ADDR prologue_start, prologue_end; | |
312 | int insn; | |
313 | ||
a00a19e9 | 314 | frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info)); |
5af923b0 MS |
315 | frame_saved_regs_zalloc (fi); |
316 | ||
da50a4b7 | 317 | get_frame_extra_info (fi)->bottom = |
11c02a10 AC |
318 | (get_next_frame (fi) |
319 | ? (get_frame_base (fi) == get_frame_base (get_next_frame (fi)) | |
da50a4b7 | 320 | ? get_frame_extra_info (get_next_frame (fi))->bottom |
11c02a10 AC |
321 | : get_frame_base (get_next_frame (fi))) |
322 | : read_sp ()); | |
c906108c | 323 | |
0ba6dca9 AC |
324 | /* If fi->next is NULL, then we already set ->frame by passing |
325 | deprecated_read_fp() to create_new_frame. */ | |
11c02a10 | 326 | if (get_next_frame (fi)) |
c906108c | 327 | { |
d9d9c31f | 328 | char buf[MAX_REGISTER_SIZE]; |
c906108c SS |
329 | |
330 | /* Compute ->frame as if not flat. If it is flat, we'll change | |
c5aa993b | 331 | it later. */ |
11c02a10 AC |
332 | if (get_next_frame (get_next_frame (fi)) != NULL |
333 | && ((get_frame_type (get_next_frame (get_next_frame (fi))) == SIGTRAMP_FRAME) | |
334 | || deprecated_frame_in_dummy (get_next_frame (get_next_frame (fi)))) | |
335 | && frameless_look_for_prologue (get_next_frame (fi))) | |
c906108c SS |
336 | { |
337 | /* A frameless function interrupted by a signal did not change | |
338 | the frame pointer, fix up frame pointer accordingly. */ | |
11c02a10 | 339 | deprecated_update_frame_base_hack (fi, get_frame_base (get_next_frame (fi))); |
da50a4b7 AC |
340 | get_frame_extra_info (fi)->bottom = |
341 | get_frame_extra_info (get_next_frame (fi))->bottom; | |
c906108c SS |
342 | } |
343 | else | |
344 | { | |
345 | /* Should we adjust for stack bias here? */ | |
ac2adee5 | 346 | ULONGEST tmp; |
0ba6dca9 | 347 | frame_read_unsigned_register (fi, DEPRECATED_FP_REGNUM, &tmp); |
ac2adee5 | 348 | deprecated_update_frame_base_hack (fi, tmp); |
1e2330ba AC |
349 | if (GDB_TARGET_IS_SPARC64 && (get_frame_base (fi) & 1)) |
350 | deprecated_update_frame_base_hack (fi, get_frame_base (fi) + 2047); | |
c906108c SS |
351 | } |
352 | } | |
353 | ||
354 | /* Decide whether this is a function with a ``flat register window'' | |
355 | frame. For such functions, the frame pointer is actually in %i7. */ | |
da50a4b7 AC |
356 | get_frame_extra_info (fi)->flat = 0; |
357 | get_frame_extra_info (fi)->in_prologue = 0; | |
50abf9e5 | 358 | if (find_pc_partial_function (get_frame_pc (fi), &name, &prologue_start, &prologue_end)) |
c906108c SS |
359 | { |
360 | /* See if the function starts with an add (which will be of a | |
c5aa993b JM |
361 | negative number if a flat frame) to the sp. FIXME: Does not |
362 | handle large frames which will need more than one instruction | |
363 | to adjust the sp. */ | |
d0901120 | 364 | insn = fetch_instruction (prologue_start); |
c906108c SS |
365 | if (X_OP (insn) == 2 && X_RD (insn) == 14 && X_OP3 (insn) == 0 |
366 | && X_I (insn) && X_SIMM13 (insn) < 0) | |
367 | { | |
368 | int offset = X_SIMM13 (insn); | |
369 | ||
370 | /* Then look for a save of %i7 into the frame. */ | |
371 | insn = fetch_instruction (prologue_start + 4); | |
372 | if (X_OP (insn) == 3 | |
373 | && X_RD (insn) == 31 | |
374 | && X_OP3 (insn) == 4 | |
375 | && X_RS1 (insn) == 14) | |
376 | { | |
d9d9c31f | 377 | char buf[MAX_REGISTER_SIZE]; |
c906108c SS |
378 | |
379 | /* We definitely have a flat frame now. */ | |
da50a4b7 | 380 | get_frame_extra_info (fi)->flat = 1; |
c906108c | 381 | |
da50a4b7 | 382 | get_frame_extra_info (fi)->sp_offset = offset; |
c906108c SS |
383 | |
384 | /* Overwrite the frame's address with the value in %i7. */ | |
ac2adee5 AC |
385 | { |
386 | ULONGEST tmp; | |
387 | frame_read_unsigned_register (fi, I7_REGNUM, &tmp); | |
388 | deprecated_update_frame_base_hack (fi, tmp); | |
389 | } | |
5af923b0 | 390 | |
1e2330ba AC |
391 | if (GDB_TARGET_IS_SPARC64 && (get_frame_base (fi) & 1)) |
392 | deprecated_update_frame_base_hack (fi, get_frame_base (fi) + 2047); | |
5af923b0 | 393 | |
c906108c | 394 | /* Record where the fp got saved. */ |
da50a4b7 AC |
395 | get_frame_extra_info (fi)->fp_addr = |
396 | get_frame_base (fi) + get_frame_extra_info (fi)->sp_offset + X_SIMM13 (insn); | |
c906108c SS |
397 | |
398 | /* Also try to collect where the pc got saved to. */ | |
da50a4b7 | 399 | get_frame_extra_info (fi)->pc_addr = 0; |
c906108c SS |
400 | insn = fetch_instruction (prologue_start + 12); |
401 | if (X_OP (insn) == 3 | |
402 | && X_RD (insn) == 15 | |
403 | && X_OP3 (insn) == 4 | |
404 | && X_RS1 (insn) == 14) | |
da50a4b7 AC |
405 | get_frame_extra_info (fi)->pc_addr = |
406 | get_frame_base (fi) + get_frame_extra_info (fi)->sp_offset + X_SIMM13 (insn); | |
c906108c SS |
407 | } |
408 | } | |
c5aa993b JM |
409 | else |
410 | { | |
411 | /* Check if the PC is in the function prologue before a SAVE | |
412 | instruction has been executed yet. If so, set the frame | |
413 | to the current value of the stack pointer and set | |
414 | the in_prologue flag. */ | |
415 | CORE_ADDR addr; | |
416 | struct symtab_and_line sal; | |
417 | ||
418 | sal = find_pc_line (prologue_start, 0); | |
419 | if (sal.line == 0) /* no line info, use PC */ | |
50abf9e5 | 420 | prologue_end = get_frame_pc (fi); |
c5aa993b JM |
421 | else if (sal.end < prologue_end) |
422 | prologue_end = sal.end; | |
50abf9e5 | 423 | if (get_frame_pc (fi) < prologue_end) |
c5aa993b | 424 | { |
50abf9e5 | 425 | for (addr = prologue_start; addr < get_frame_pc (fi); addr += 4) |
c5aa993b JM |
426 | { |
427 | insn = read_memory_integer (addr, 4); | |
428 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) | |
429 | break; /* SAVE seen, stop searching */ | |
430 | } | |
50abf9e5 | 431 | if (addr >= get_frame_pc (fi)) |
c5aa993b | 432 | { |
da50a4b7 | 433 | get_frame_extra_info (fi)->in_prologue = 1; |
8ccd593b | 434 | deprecated_update_frame_base_hack (fi, read_register (SP_REGNUM)); |
c5aa993b JM |
435 | } |
436 | } | |
437 | } | |
c906108c | 438 | } |
11c02a10 | 439 | if (get_next_frame (fi) && get_frame_base (fi) == 0) |
c906108c SS |
440 | { |
441 | /* Kludge to cause init_prev_frame_info to destroy the new frame. */ | |
11c02a10 AC |
442 | deprecated_update_frame_base_hack (fi, get_frame_base (get_next_frame (fi))); |
443 | deprecated_update_frame_pc_hack (fi, get_frame_pc (get_next_frame (fi))); | |
c906108c SS |
444 | } |
445 | } | |
446 | ||
447 | CORE_ADDR | |
fba45db2 | 448 | sparc_frame_chain (struct frame_info *frame) |
c906108c | 449 | { |
618ce49f AC |
450 | /* Value that will cause DEPRECATED_FRAME_CHAIN_VALID to not worry |
451 | about the chain value. If it really is zero, we detect it later | |
452 | in sparc_init_prev_frame. | |
881324eb | 453 | |
e6ba3bc9 AC |
454 | Note: kevinb/2003-02-18: The constant 1 used to be returned here, |
455 | but, after some recent changes to legacy_frame_chain_valid(), | |
456 | this value is no longer suitable for causing | |
457 | legacy_frame_chain_valid() to "not worry about the chain value." | |
458 | The constant ~0 (i.e, 0xfff...) causes the failing test in | |
459 | legacy_frame_chain_valid() to succeed thus preserving the "not | |
460 | worry" property. I had considered using something like | |
461 | ``get_frame_base (frame) + 1''. However, I think a constant | |
462 | value is better, because when debugging this problem, I knew that | |
463 | something funny was going on as soon as I saw the constant 1 | |
464 | being used as the frame chain elsewhere in GDB. */ | |
881324eb KB |
465 | |
466 | return ~ (CORE_ADDR) 0; | |
c906108c SS |
467 | } |
468 | ||
c906108c SS |
469 | /* Find the pc saved in frame FRAME. */ |
470 | ||
471 | CORE_ADDR | |
fba45db2 | 472 | sparc_frame_saved_pc (struct frame_info *frame) |
c906108c | 473 | { |
d9d9c31f | 474 | char buf[MAX_REGISTER_SIZE]; |
c906108c SS |
475 | CORE_ADDR addr; |
476 | ||
5a203e44 | 477 | if ((get_frame_type (frame) == SIGTRAMP_FRAME)) |
c906108c SS |
478 | { |
479 | /* This is the signal trampoline frame. | |
c5aa993b | 480 | Get the saved PC from the sigcontext structure. */ |
c906108c SS |
481 | |
482 | #ifndef SIGCONTEXT_PC_OFFSET | |
483 | #define SIGCONTEXT_PC_OFFSET 12 | |
484 | #endif | |
485 | ||
486 | CORE_ADDR sigcontext_addr; | |
5af923b0 | 487 | char *scbuf; |
c906108c SS |
488 | int saved_pc_offset = SIGCONTEXT_PC_OFFSET; |
489 | char *name = NULL; | |
490 | ||
5af923b0 MS |
491 | scbuf = alloca (TARGET_PTR_BIT / HOST_CHAR_BIT); |
492 | ||
c906108c | 493 | /* Solaris2 ucbsigvechandler passes a pointer to a sigcontext |
c5aa993b | 494 | as the third parameter. The offset to the saved pc is 12. */ |
50abf9e5 | 495 | find_pc_partial_function (get_frame_pc (frame), &name, |
c5aa993b | 496 | (CORE_ADDR *) NULL, (CORE_ADDR *) NULL); |
c906108c SS |
497 | if (name && STREQ (name, "ucbsigvechandler")) |
498 | saved_pc_offset = 12; | |
499 | ||
500 | /* The sigcontext address is contained in register O2. */ | |
ac2adee5 AC |
501 | { |
502 | ULONGEST tmp; | |
503 | frame_read_unsigned_register (frame, O0_REGNUM + 2, &tmp); | |
504 | sigcontext_addr = tmp; | |
505 | } | |
c906108c SS |
506 | |
507 | /* Don't cause a memory_error when accessing sigcontext in case the | |
c5aa993b | 508 | stack layout has changed or the stack is corrupt. */ |
c906108c SS |
509 | target_read_memory (sigcontext_addr + saved_pc_offset, |
510 | scbuf, sizeof (scbuf)); | |
511 | return extract_address (scbuf, sizeof (scbuf)); | |
512 | } | |
da50a4b7 | 513 | else if (get_frame_extra_info (frame)->in_prologue || |
11c02a10 AC |
514 | (get_next_frame (frame) != NULL && |
515 | ((get_frame_type (get_next_frame (frame)) == SIGTRAMP_FRAME) || | |
516 | deprecated_frame_in_dummy (get_next_frame (frame))) && | |
5af923b0 | 517 | frameless_look_for_prologue (frame))) |
c906108c SS |
518 | { |
519 | /* A frameless function interrupted by a signal did not save | |
c5aa993b | 520 | the PC, it is still in %o7. */ |
ac2adee5 AC |
521 | ULONGEST tmp; |
522 | frame_read_unsigned_register (frame, O7_REGNUM, &tmp); | |
523 | return PC_ADJUST (tmp); | |
c906108c | 524 | } |
da50a4b7 AC |
525 | if (get_frame_extra_info (frame)->flat) |
526 | addr = get_frame_extra_info (frame)->pc_addr; | |
c906108c | 527 | else |
da50a4b7 | 528 | addr = get_frame_extra_info (frame)->bottom + FRAME_SAVED_I0 + |
c906108c SS |
529 | SPARC_INTREG_SIZE * (I7_REGNUM - I0_REGNUM); |
530 | ||
531 | if (addr == 0) | |
532 | /* A flat frame leaf function might not save the PC anywhere, | |
533 | just leave it in %o7. */ | |
534 | return PC_ADJUST (read_register (O7_REGNUM)); | |
535 | ||
536 | read_memory (addr, buf, SPARC_INTREG_SIZE); | |
537 | return PC_ADJUST (extract_address (buf, SPARC_INTREG_SIZE)); | |
538 | } | |
539 | ||
540 | /* Since an individual frame in the frame cache is defined by two | |
541 | arguments (a frame pointer and a stack pointer), we need two | |
542 | arguments to get info for an arbitrary stack frame. This routine | |
543 | takes two arguments and makes the cached frames look as if these | |
544 | two arguments defined a frame on the cache. This allows the rest | |
545 | of info frame to extract the important arguments without | |
546 | difficulty. */ | |
547 | ||
548 | struct frame_info * | |
fba45db2 | 549 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
c906108c SS |
550 | { |
551 | struct frame_info *frame; | |
552 | ||
553 | if (argc != 2) | |
554 | error ("Sparc frame specifications require two arguments: fp and sp"); | |
555 | ||
556 | frame = create_new_frame (argv[0], 0); | |
557 | ||
558 | if (!frame) | |
8e65ff28 AC |
559 | internal_error (__FILE__, __LINE__, |
560 | "create_new_frame returned invalid frame"); | |
c5aa993b | 561 | |
da50a4b7 | 562 | get_frame_extra_info (frame)->bottom = argv[1]; |
8bedc050 | 563 | deprecated_update_frame_pc_hack (frame, DEPRECATED_FRAME_SAVED_PC (frame)); |
c906108c SS |
564 | return frame; |
565 | } | |
566 | ||
567 | /* Given a pc value, skip it forward past the function prologue by | |
568 | disassembling instructions that appear to be a prologue. | |
569 | ||
570 | If FRAMELESS_P is set, we are only testing to see if the function | |
571 | is frameless. This allows a quicker answer. | |
572 | ||
573 | This routine should be more specific in its actions; making sure | |
574 | that it uses the same register in the initial prologue section. */ | |
575 | ||
5af923b0 MS |
576 | static CORE_ADDR examine_prologue (CORE_ADDR, int, struct frame_info *, |
577 | CORE_ADDR *); | |
c906108c | 578 | |
c5aa993b | 579 | static CORE_ADDR |
fba45db2 KB |
580 | examine_prologue (CORE_ADDR start_pc, int frameless_p, struct frame_info *fi, |
581 | CORE_ADDR *saved_regs) | |
c906108c SS |
582 | { |
583 | int insn; | |
584 | int dest = -1; | |
585 | CORE_ADDR pc = start_pc; | |
586 | int is_flat = 0; | |
587 | ||
588 | insn = fetch_instruction (pc); | |
589 | ||
590 | /* Recognize the `sethi' insn and record its destination. */ | |
591 | if (X_OP (insn) == 0 && X_OP2 (insn) == 4) | |
592 | { | |
593 | dest = X_RD (insn); | |
594 | pc += 4; | |
595 | insn = fetch_instruction (pc); | |
596 | } | |
597 | ||
598 | /* Recognize an add immediate value to register to either %g1 or | |
599 | the destination register recorded above. Actually, this might | |
600 | well recognize several different arithmetic operations. | |
601 | It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1" | |
602 | followed by "save %sp, %g1, %sp" is a valid prologue (Not that | |
603 | I imagine any compiler really does that, however). */ | |
604 | if (X_OP (insn) == 2 | |
605 | && X_I (insn) | |
606 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) | |
607 | { | |
608 | pc += 4; | |
609 | insn = fetch_instruction (pc); | |
610 | } | |
611 | ||
612 | /* Recognize any SAVE insn. */ | |
613 | if (X_OP (insn) == 2 && X_OP3 (insn) == 60) | |
614 | { | |
615 | pc += 4; | |
c5aa993b JM |
616 | if (frameless_p) /* If the save is all we care about, */ |
617 | return pc; /* return before doing more work */ | |
c906108c SS |
618 | insn = fetch_instruction (pc); |
619 | } | |
620 | /* Recognize add to %sp. */ | |
621 | else if (X_OP (insn) == 2 && X_RD (insn) == 14 && X_OP3 (insn) == 0) | |
622 | { | |
623 | pc += 4; | |
c5aa993b JM |
624 | if (frameless_p) /* If the add is all we care about, */ |
625 | return pc; /* return before doing more work */ | |
c906108c SS |
626 | is_flat = 1; |
627 | insn = fetch_instruction (pc); | |
628 | /* Recognize store of frame pointer (i7). */ | |
629 | if (X_OP (insn) == 3 | |
630 | && X_RD (insn) == 31 | |
631 | && X_OP3 (insn) == 4 | |
632 | && X_RS1 (insn) == 14) | |
633 | { | |
634 | pc += 4; | |
635 | insn = fetch_instruction (pc); | |
636 | ||
637 | /* Recognize sub %sp, <anything>, %i7. */ | |
c5aa993b | 638 | if (X_OP (insn) == 2 |
c906108c SS |
639 | && X_OP3 (insn) == 4 |
640 | && X_RS1 (insn) == 14 | |
641 | && X_RD (insn) == 31) | |
642 | { | |
643 | pc += 4; | |
644 | insn = fetch_instruction (pc); | |
645 | } | |
646 | else | |
647 | return pc; | |
648 | } | |
649 | else | |
650 | return pc; | |
651 | } | |
652 | else | |
653 | /* Without a save or add instruction, it's not a prologue. */ | |
654 | return start_pc; | |
655 | ||
656 | while (1) | |
657 | { | |
658 | /* Recognize stores into the frame from the input registers. | |
5af923b0 MS |
659 | This recognizes all non alternate stores of an input register, |
660 | into a location offset from the frame pointer between | |
661 | +68 and +92. */ | |
662 | ||
663 | /* The above will fail for arguments that are promoted | |
664 | (eg. shorts to ints or floats to doubles), because the compiler | |
665 | will pass them in positive-offset frame space, but the prologue | |
666 | will save them (after conversion) in negative frame space at an | |
667 | unpredictable offset. Therefore I am going to remove the | |
668 | restriction on the target-address of the save, on the theory | |
669 | that any unbroken sequence of saves from input registers must | |
670 | be part of the prologue. In un-optimized code (at least), I'm | |
671 | fairly sure that the compiler would emit SOME other instruction | |
672 | (eg. a move or add) before emitting another save that is actually | |
673 | a part of the function body. | |
674 | ||
675 | Besides, the reserved stack space is different for SPARC64 anyway. | |
676 | ||
677 | MVS 4/23/2000 */ | |
678 | ||
679 | if (X_OP (insn) == 3 | |
680 | && (X_OP3 (insn) & 0x3c) == 4 /* Store, non-alternate. */ | |
681 | && (X_RD (insn) & 0x18) == 0x18 /* Input register. */ | |
682 | && X_I (insn) /* Immediate mode. */ | |
683 | && X_RS1 (insn) == 30) /* Off of frame pointer. */ | |
684 | ; /* empty statement -- fall thru to end of loop */ | |
685 | else if (GDB_TARGET_IS_SPARC64 | |
686 | && X_OP (insn) == 3 | |
687 | && (X_OP3 (insn) & 0x3c) == 12 /* store, extended (64-bit) */ | |
688 | && (X_RD (insn) & 0x18) == 0x18 /* input register */ | |
689 | && X_I (insn) /* immediate mode */ | |
690 | && X_RS1 (insn) == 30) /* off of frame pointer */ | |
691 | ; /* empty statement -- fall thru to end of loop */ | |
692 | else if (X_OP (insn) == 3 | |
693 | && (X_OP3 (insn) & 0x3c) == 36 /* store, floating-point */ | |
694 | && X_I (insn) /* immediate mode */ | |
695 | && X_RS1 (insn) == 30) /* off of frame pointer */ | |
696 | ; /* empty statement -- fall thru to end of loop */ | |
c906108c SS |
697 | else if (is_flat |
698 | && X_OP (insn) == 3 | |
5af923b0 MS |
699 | && X_OP3 (insn) == 4 /* store? */ |
700 | && X_RS1 (insn) == 14) /* off of frame pointer */ | |
c906108c SS |
701 | { |
702 | if (saved_regs && X_I (insn)) | |
5af923b0 | 703 | saved_regs[X_RD (insn)] = |
da50a4b7 | 704 | get_frame_base (fi) + get_frame_extra_info (fi)->sp_offset + X_SIMM13 (insn); |
c906108c SS |
705 | } |
706 | else | |
707 | break; | |
708 | pc += 4; | |
709 | insn = fetch_instruction (pc); | |
710 | } | |
711 | ||
712 | return pc; | |
713 | } | |
714 | ||
f510d44e DM |
715 | /* Advance PC across any function entry prologue instructions to reach |
716 | some "real" code. */ | |
717 | ||
c5aa993b | 718 | CORE_ADDR |
f510d44e | 719 | sparc_skip_prologue (CORE_ADDR start_pc) |
c906108c | 720 | { |
f510d44e DM |
721 | struct symtab_and_line sal; |
722 | CORE_ADDR func_start, func_end; | |
723 | ||
724 | /* This is the preferred method, find the end of the prologue by | |
725 | using the debugging information. */ | |
726 | if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) | |
727 | { | |
728 | sal = find_pc_line (func_start, 0); | |
729 | ||
730 | if (sal.end < func_end | |
731 | && start_pc <= sal.end) | |
732 | return sal.end; | |
733 | } | |
734 | ||
735 | /* Oh well, examine the code by hand. */ | |
736 | return examine_prologue (start_pc, 0, NULL, NULL); | |
c906108c SS |
737 | } |
738 | ||
9319a2fe DM |
739 | /* Is the prologue at IP frameless? */ |
740 | ||
741 | int | |
742 | sparc_prologue_frameless_p (CORE_ADDR ip) | |
743 | { | |
f510d44e | 744 | return ip == examine_prologue (ip, 1, NULL, NULL); |
9319a2fe DM |
745 | } |
746 | ||
c906108c SS |
747 | /* Check instruction at ADDR to see if it is a branch. |
748 | All non-annulled instructions will go to NPC or will trap. | |
749 | Set *TARGET if we find a candidate branch; set to zero if not. | |
750 | ||
751 | This isn't static as it's used by remote-sa.sparc.c. */ | |
752 | ||
753 | static branch_type | |
fba45db2 | 754 | isbranch (long instruction, CORE_ADDR addr, CORE_ADDR *target) |
c906108c SS |
755 | { |
756 | branch_type val = not_branch; | |
757 | long int offset = 0; /* Must be signed for sign-extend. */ | |
758 | ||
759 | *target = 0; | |
760 | ||
761 | if (X_OP (instruction) == 0 | |
762 | && (X_OP2 (instruction) == 2 | |
763 | || X_OP2 (instruction) == 6 | |
764 | || X_OP2 (instruction) == 1 | |
765 | || X_OP2 (instruction) == 3 | |
766 | || X_OP2 (instruction) == 5 | |
5af923b0 | 767 | || (GDB_TARGET_IS_SPARC64 && X_OP2 (instruction) == 7))) |
c906108c SS |
768 | { |
769 | if (X_COND (instruction) == 8) | |
770 | val = X_A (instruction) ? baa : ba; | |
771 | else | |
772 | val = X_A (instruction) ? bicca : bicc; | |
773 | switch (X_OP2 (instruction)) | |
774 | { | |
5af923b0 MS |
775 | case 7: |
776 | if (!GDB_TARGET_IS_SPARC64) | |
777 | break; | |
778 | /* else fall thru */ | |
c906108c SS |
779 | case 2: |
780 | case 6: | |
c906108c SS |
781 | offset = 4 * X_DISP22 (instruction); |
782 | break; | |
783 | case 1: | |
784 | case 5: | |
785 | offset = 4 * X_DISP19 (instruction); | |
786 | break; | |
787 | case 3: | |
788 | offset = 4 * X_DISP16 (instruction); | |
789 | break; | |
790 | } | |
791 | *target = addr + offset; | |
792 | } | |
5af923b0 MS |
793 | else if (GDB_TARGET_IS_SPARC64 |
794 | && X_OP (instruction) == 2 | |
c906108c SS |
795 | && X_OP3 (instruction) == 62) |
796 | { | |
797 | if (X_FCN (instruction) == 0) | |
798 | { | |
799 | /* done */ | |
800 | *target = read_register (TNPC_REGNUM); | |
801 | val = done_retry; | |
802 | } | |
803 | else if (X_FCN (instruction) == 1) | |
804 | { | |
805 | /* retry */ | |
806 | *target = read_register (TPC_REGNUM); | |
807 | val = done_retry; | |
808 | } | |
809 | } | |
c906108c SS |
810 | |
811 | return val; | |
812 | } | |
813 | \f | |
814 | /* Find register number REGNUM relative to FRAME and put its | |
815 | (raw) contents in *RAW_BUFFER. Set *OPTIMIZED if the variable | |
816 | was optimized out (and thus can't be fetched). If the variable | |
817 | was fetched from memory, set *ADDRP to where it was fetched from, | |
818 | otherwise it was fetched from a register. | |
819 | ||
820 | The argument RAW_BUFFER must point to aligned memory. */ | |
821 | ||
822 | void | |
fba45db2 KB |
823 | sparc_get_saved_register (char *raw_buffer, int *optimized, CORE_ADDR *addrp, |
824 | struct frame_info *frame, int regnum, | |
825 | enum lval_type *lval) | |
c906108c SS |
826 | { |
827 | struct frame_info *frame1; | |
828 | CORE_ADDR addr; | |
829 | ||
830 | if (!target_has_registers) | |
831 | error ("No registers."); | |
832 | ||
833 | if (optimized) | |
834 | *optimized = 0; | |
835 | ||
836 | addr = 0; | |
837 | ||
838 | /* FIXME This code extracted from infcmd.c; should put elsewhere! */ | |
839 | if (frame == NULL) | |
840 | { | |
841 | /* error ("No selected frame."); */ | |
842 | if (!target_has_registers) | |
c5aa993b | 843 | error ("The program has no registers now."); |
6e7f8b9c | 844 | if (deprecated_selected_frame == NULL) |
c5aa993b | 845 | error ("No selected frame."); |
c906108c | 846 | /* Try to use selected frame */ |
6e7f8b9c | 847 | frame = get_prev_frame (deprecated_selected_frame); |
c906108c | 848 | if (frame == 0) |
c5aa993b | 849 | error ("Cmd not meaningful in the outermost frame."); |
c906108c SS |
850 | } |
851 | ||
852 | ||
11c02a10 | 853 | frame1 = get_next_frame (frame); |
c906108c SS |
854 | |
855 | /* Get saved PC from the frame info if not in innermost frame. */ | |
856 | if (regnum == PC_REGNUM && frame1 != NULL) | |
857 | { | |
858 | if (lval != NULL) | |
859 | *lval = not_lval; | |
860 | if (raw_buffer != NULL) | |
861 | { | |
862 | /* Put it back in target format. */ | |
fbd9dcd3 | 863 | store_unsigned_integer (raw_buffer, REGISTER_RAW_SIZE (regnum), get_frame_pc (frame)); |
c906108c SS |
864 | } |
865 | if (addrp != NULL) | |
866 | *addrp = 0; | |
867 | return; | |
868 | } | |
869 | ||
870 | while (frame1 != NULL) | |
871 | { | |
5af923b0 MS |
872 | /* FIXME MVS: wrong test for dummy frame at entry. */ |
873 | ||
da50a4b7 AC |
874 | if (get_frame_pc (frame1) >= (get_frame_extra_info (frame1)->bottom |
875 | ? get_frame_extra_info (frame1)->bottom | |
876 | : read_sp ()) | |
50abf9e5 | 877 | && get_frame_pc (frame1) <= get_frame_base (frame1)) |
c906108c SS |
878 | { |
879 | /* Dummy frame. All but the window regs are in there somewhere. | |
880 | The window registers are saved on the stack, just like in a | |
881 | normal frame. */ | |
882 | if (regnum >= G1_REGNUM && regnum < G1_REGNUM + 7) | |
1e2330ba | 883 | addr = get_frame_base (frame1) + (regnum - G0_REGNUM) * SPARC_INTREG_SIZE |
c906108c SS |
884 | - (FP_REGISTER_BYTES + 8 * SPARC_INTREG_SIZE); |
885 | else if (regnum >= I0_REGNUM && regnum < I0_REGNUM + 8) | |
f621c63e AC |
886 | /* NOTE: cagney/2002-05-04: The call to get_prev_frame() |
887 | is safe/cheap - there will always be a prev frame. | |
888 | This is because frame1 is initialized to frame->next | |
889 | (frame1->prev == frame) and is then advanced towards | |
890 | the innermost (next) frame. */ | |
da50a4b7 | 891 | addr = (get_frame_extra_info (get_prev_frame (frame1))->bottom |
c906108c SS |
892 | + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE |
893 | + FRAME_SAVED_I0); | |
894 | else if (regnum >= L0_REGNUM && regnum < L0_REGNUM + 8) | |
f621c63e AC |
895 | /* NOTE: cagney/2002-05-04: The call to get_prev_frame() |
896 | is safe/cheap - there will always be a prev frame. | |
897 | This is because frame1 is initialized to frame->next | |
898 | (frame1->prev == frame) and is then advanced towards | |
899 | the innermost (next) frame. */ | |
da50a4b7 | 900 | addr = (get_frame_extra_info (get_prev_frame (frame1))->bottom |
c906108c SS |
901 | + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE |
902 | + FRAME_SAVED_L0); | |
903 | else if (regnum >= O0_REGNUM && regnum < O0_REGNUM + 8) | |
1e2330ba | 904 | addr = get_frame_base (frame1) + (regnum - O0_REGNUM) * SPARC_INTREG_SIZE |
c906108c | 905 | - (FP_REGISTER_BYTES + 16 * SPARC_INTREG_SIZE); |
5af923b0 | 906 | else if (SPARC_HAS_FPU && |
60054393 | 907 | regnum >= FP0_REGNUM && regnum < FP0_REGNUM + 32) |
1e2330ba | 908 | addr = get_frame_base (frame1) + (regnum - FP0_REGNUM) * 4 |
c906108c | 909 | - (FP_REGISTER_BYTES); |
5af923b0 | 910 | else if (GDB_TARGET_IS_SPARC64 && SPARC_HAS_FPU && |
60054393 | 911 | regnum >= FP0_REGNUM + 32 && regnum < FP_MAX_REGNUM) |
1e2330ba | 912 | addr = get_frame_base (frame1) + 32 * 4 + (regnum - FP0_REGNUM - 32) * 8 |
c906108c | 913 | - (FP_REGISTER_BYTES); |
c906108c | 914 | else if (regnum >= Y_REGNUM && regnum < NUM_REGS) |
1e2330ba | 915 | addr = get_frame_base (frame1) + (regnum - Y_REGNUM) * SPARC_INTREG_SIZE |
c906108c SS |
916 | - (FP_REGISTER_BYTES + 24 * SPARC_INTREG_SIZE); |
917 | } | |
da50a4b7 | 918 | else if (get_frame_extra_info (frame1)->flat) |
c906108c SS |
919 | { |
920 | ||
921 | if (regnum == RP_REGNUM) | |
da50a4b7 | 922 | addr = get_frame_extra_info (frame1)->pc_addr; |
c906108c | 923 | else if (regnum == I7_REGNUM) |
da50a4b7 | 924 | addr = get_frame_extra_info (frame1)->fp_addr; |
c906108c SS |
925 | else |
926 | { | |
927 | CORE_ADDR func_start; | |
5af923b0 MS |
928 | CORE_ADDR *regs; |
929 | ||
930 | regs = alloca (NUM_REGS * sizeof (CORE_ADDR)); | |
931 | memset (regs, 0, NUM_REGS * sizeof (CORE_ADDR)); | |
c906108c | 932 | |
50abf9e5 | 933 | find_pc_partial_function (get_frame_pc (frame1), NULL, &func_start, NULL); |
5af923b0 MS |
934 | examine_prologue (func_start, 0, frame1, regs); |
935 | addr = regs[regnum]; | |
c906108c SS |
936 | } |
937 | } | |
938 | else | |
939 | { | |
940 | /* Normal frame. Local and In registers are saved on stack. */ | |
941 | if (regnum >= I0_REGNUM && regnum < I0_REGNUM + 8) | |
da50a4b7 | 942 | addr = (get_frame_extra_info (get_prev_frame (frame1))->bottom |
c906108c SS |
943 | + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE |
944 | + FRAME_SAVED_I0); | |
945 | else if (regnum >= L0_REGNUM && regnum < L0_REGNUM + 8) | |
da50a4b7 | 946 | addr = (get_frame_extra_info (get_prev_frame (frame1))->bottom |
c906108c SS |
947 | + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE |
948 | + FRAME_SAVED_L0); | |
949 | else if (regnum >= O0_REGNUM && regnum < O0_REGNUM + 8) | |
950 | { | |
951 | /* Outs become ins. */ | |
ac2adee5 AC |
952 | int realnum; |
953 | frame_register (frame1, (regnum - O0_REGNUM + I0_REGNUM), | |
954 | optimized, lval, addrp, &realnum, raw_buffer); | |
c906108c SS |
955 | return; |
956 | } | |
957 | } | |
958 | if (addr != 0) | |
959 | break; | |
11c02a10 | 960 | frame1 = get_next_frame (frame1); |
c906108c SS |
961 | } |
962 | if (addr != 0) | |
963 | { | |
964 | if (lval != NULL) | |
965 | *lval = lval_memory; | |
966 | if (regnum == SP_REGNUM) | |
967 | { | |
968 | if (raw_buffer != NULL) | |
969 | { | |
970 | /* Put it back in target format. */ | |
fbd9dcd3 | 971 | store_unsigned_integer (raw_buffer, REGISTER_RAW_SIZE (regnum), addr); |
c906108c SS |
972 | } |
973 | if (addrp != NULL) | |
974 | *addrp = 0; | |
975 | return; | |
976 | } | |
977 | if (raw_buffer != NULL) | |
978 | read_memory (addr, raw_buffer, REGISTER_RAW_SIZE (regnum)); | |
979 | } | |
980 | else | |
981 | { | |
982 | if (lval != NULL) | |
983 | *lval = lval_register; | |
984 | addr = REGISTER_BYTE (regnum); | |
985 | if (raw_buffer != NULL) | |
4caf0990 | 986 | deprecated_read_register_gen (regnum, raw_buffer); |
c906108c SS |
987 | } |
988 | if (addrp != NULL) | |
989 | *addrp = addr; | |
990 | } | |
991 | ||
992 | /* Push an empty stack frame, and record in it the current PC, regs, etc. | |
993 | ||
994 | We save the non-windowed registers and the ins. The locals and outs | |
995 | are new; they don't need to be saved. The i's and l's of | |
996 | the last frame were already saved on the stack. */ | |
997 | ||
998 | /* Definitely see tm-sparc.h for more doc of the frame format here. */ | |
999 | ||
c906108c | 1000 | /* See tm-sparc.h for how this is calculated. */ |
5af923b0 | 1001 | |
c906108c | 1002 | #define DUMMY_STACK_REG_BUF_SIZE \ |
60054393 | 1003 | (((8+8+8) * SPARC_INTREG_SIZE) + FP_REGISTER_BYTES) |
5af923b0 MS |
1004 | #define DUMMY_STACK_SIZE \ |
1005 | (DUMMY_STACK_REG_BUF_SIZE + DUMMY_REG_SAVE_OFFSET) | |
c906108c SS |
1006 | |
1007 | void | |
fba45db2 | 1008 | sparc_push_dummy_frame (void) |
c906108c SS |
1009 | { |
1010 | CORE_ADDR sp, old_sp; | |
5af923b0 MS |
1011 | char *register_temp; |
1012 | ||
1013 | register_temp = alloca (DUMMY_STACK_SIZE); | |
c906108c SS |
1014 | |
1015 | old_sp = sp = read_sp (); | |
1016 | ||
5af923b0 MS |
1017 | if (GDB_TARGET_IS_SPARC64) |
1018 | { | |
1019 | /* PC, NPC, CCR, FSR, FPRS, Y, ASI */ | |
73937e03 AC |
1020 | deprecated_read_register_bytes (REGISTER_BYTE (PC_REGNUM), |
1021 | ®ister_temp[0], | |
1022 | REGISTER_RAW_SIZE (PC_REGNUM) * 7); | |
1023 | deprecated_read_register_bytes (REGISTER_BYTE (PSTATE_REGNUM), | |
1024 | ®ister_temp[7 * SPARC_INTREG_SIZE], | |
1025 | REGISTER_RAW_SIZE (PSTATE_REGNUM)); | |
5af923b0 MS |
1026 | /* FIXME: not sure what needs to be saved here. */ |
1027 | } | |
1028 | else | |
1029 | { | |
1030 | /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */ | |
73937e03 AC |
1031 | deprecated_read_register_bytes (REGISTER_BYTE (Y_REGNUM), |
1032 | ®ister_temp[0], | |
1033 | REGISTER_RAW_SIZE (Y_REGNUM) * 8); | |
5af923b0 | 1034 | } |
c906108c | 1035 | |
73937e03 AC |
1036 | deprecated_read_register_bytes (REGISTER_BYTE (O0_REGNUM), |
1037 | ®ister_temp[8 * SPARC_INTREG_SIZE], | |
1038 | SPARC_INTREG_SIZE * 8); | |
c906108c | 1039 | |
73937e03 AC |
1040 | deprecated_read_register_bytes (REGISTER_BYTE (G0_REGNUM), |
1041 | ®ister_temp[16 * SPARC_INTREG_SIZE], | |
1042 | SPARC_INTREG_SIZE * 8); | |
c906108c | 1043 | |
5af923b0 | 1044 | if (SPARC_HAS_FPU) |
73937e03 AC |
1045 | deprecated_read_register_bytes (REGISTER_BYTE (FP0_REGNUM), |
1046 | ®ister_temp[24 * SPARC_INTREG_SIZE], | |
1047 | FP_REGISTER_BYTES); | |
c906108c SS |
1048 | |
1049 | sp -= DUMMY_STACK_SIZE; | |
1050 | ||
6c0e89ed | 1051 | DEPRECATED_DUMMY_WRITE_SP (sp); |
c906108c SS |
1052 | |
1053 | write_memory (sp + DUMMY_REG_SAVE_OFFSET, ®ister_temp[0], | |
1054 | DUMMY_STACK_REG_BUF_SIZE); | |
1055 | ||
1056 | if (strcmp (target_shortname, "sim") != 0) | |
1057 | { | |
2757dd86 AC |
1058 | /* NOTE: cagney/2002-04-04: The code below originally contained |
1059 | GDB's _only_ call to write_fp(). That call was eliminated by | |
1060 | inlining the corresponding code. For the 64 bit case, the | |
1061 | old function (sparc64_write_fp) did the below although I'm | |
1062 | not clear why. The same goes for why this is only done when | |
1063 | the underlying target is a simulator. */ | |
f32e7a74 | 1064 | if (GDB_TARGET_IS_SPARC64) |
2757dd86 AC |
1065 | { |
1066 | /* Target is a 64 bit SPARC. */ | |
0ba6dca9 | 1067 | CORE_ADDR oldfp = read_register (DEPRECATED_FP_REGNUM); |
2757dd86 | 1068 | if (oldfp & 1) |
0ba6dca9 | 1069 | write_register (DEPRECATED_FP_REGNUM, old_sp - 2047); |
2757dd86 | 1070 | else |
0ba6dca9 | 1071 | write_register (DEPRECATED_FP_REGNUM, old_sp); |
2757dd86 AC |
1072 | } |
1073 | else | |
1074 | { | |
1075 | /* Target is a 32 bit SPARC. */ | |
0ba6dca9 | 1076 | write_register (DEPRECATED_FP_REGNUM, old_sp); |
2757dd86 | 1077 | } |
c906108c | 1078 | /* Set return address register for the call dummy to the current PC. */ |
c5aa993b | 1079 | write_register (I7_REGNUM, read_pc () - 8); |
c906108c SS |
1080 | } |
1081 | else | |
1082 | { | |
1083 | /* The call dummy will write this value to FP before executing | |
1084 | the 'save'. This ensures that register window flushes work | |
c5aa993b | 1085 | correctly in the simulator. */ |
0ba6dca9 | 1086 | write_register (G0_REGNUM + 1, read_register (DEPRECATED_FP_REGNUM)); |
c5aa993b | 1087 | |
c906108c SS |
1088 | /* The call dummy will write this value to FP after executing |
1089 | the 'save'. */ | |
c5aa993b JM |
1090 | write_register (G0_REGNUM + 2, old_sp); |
1091 | ||
c906108c | 1092 | /* The call dummy will write this value to the return address (%i7) after |
c5aa993b JM |
1093 | executing the 'save'. */ |
1094 | write_register (G0_REGNUM + 3, read_pc () - 8); | |
1095 | ||
c906108c | 1096 | /* Set the FP that the call dummy will be using after the 'save'. |
c5aa993b | 1097 | This makes backtraces from an inferior function call work properly. */ |
0ba6dca9 | 1098 | write_register (DEPRECATED_FP_REGNUM, old_sp); |
c906108c SS |
1099 | } |
1100 | } | |
1101 | ||
1102 | /* sparc_frame_find_saved_regs (). This function is here only because | |
1103 | pop_frame uses it. Note there is an interesting corner case which | |
1104 | I think few ports of GDB get right--if you are popping a frame | |
1105 | which does not save some register that *is* saved by a more inner | |
1106 | frame (such a frame will never be a dummy frame because dummy | |
ac2adee5 AC |
1107 | frames save all registers). |
1108 | ||
1109 | NOTE: cagney/2003-03-12: Since pop_frame has been rewritten to use | |
1110 | frame_unwind_register() the need for this function is questionable. | |
c906108c | 1111 | |
5af923b0 | 1112 | Stores, into an array of CORE_ADDR, |
c906108c SS |
1113 | the addresses of the saved registers of frame described by FRAME_INFO. |
1114 | This includes special registers such as pc and fp saved in special | |
1115 | ways in the stack frame. sp is even more special: | |
1116 | the address we return for it IS the sp for the next frame. | |
1117 | ||
1118 | Note that on register window machines, we are currently making the | |
1119 | assumption that window registers are being saved somewhere in the | |
1120 | frame in which they are being used. If they are stored in an | |
1121 | inferior frame, find_saved_register will break. | |
1122 | ||
1123 | On the Sun 4, the only time all registers are saved is when | |
1124 | a dummy frame is involved. Otherwise, the only saved registers | |
1125 | are the LOCAL and IN registers which are saved as a result | |
1126 | of the "save/restore" opcodes. This condition is determined | |
1127 | by address rather than by value. | |
1128 | ||
1129 | The "pc" is not stored in a frame on the SPARC. (What is stored | |
1130 | is a return address minus 8.) sparc_pop_frame knows how to | |
1131 | deal with that. Other routines might or might not. | |
1132 | ||
1133 | See tm-sparc.h (PUSH_DUMMY_FRAME and friends) for CRITICAL information | |
1134 | about how this works. */ | |
1135 | ||
5af923b0 | 1136 | static void sparc_frame_find_saved_regs (struct frame_info *, CORE_ADDR *); |
c906108c SS |
1137 | |
1138 | static void | |
fba45db2 | 1139 | sparc_frame_find_saved_regs (struct frame_info *fi, CORE_ADDR *saved_regs_addr) |
c906108c SS |
1140 | { |
1141 | register int regnum; | |
c193f6ac | 1142 | CORE_ADDR frame_addr = get_frame_base (fi); |
c906108c | 1143 | |
43bd9a9e | 1144 | gdb_assert (fi != NULL); |
c906108c | 1145 | |
5af923b0 | 1146 | memset (saved_regs_addr, 0, NUM_REGS * sizeof (CORE_ADDR)); |
c906108c | 1147 | |
da50a4b7 AC |
1148 | if (get_frame_pc (fi) >= (get_frame_extra_info (fi)->bottom |
1149 | ? get_frame_extra_info (fi)->bottom | |
1150 | : read_sp ()) | |
50abf9e5 | 1151 | && get_frame_pc (fi) <= get_frame_base (fi)) |
c906108c SS |
1152 | { |
1153 | /* Dummy frame. All but the window regs are in there somewhere. */ | |
c5aa993b | 1154 | for (regnum = G1_REGNUM; regnum < G1_REGNUM + 7; regnum++) |
5af923b0 | 1155 | saved_regs_addr[regnum] = |
c906108c | 1156 | frame_addr + (regnum - G0_REGNUM) * SPARC_INTREG_SIZE |
c5aa993b | 1157 | - DUMMY_STACK_REG_BUF_SIZE + 16 * SPARC_INTREG_SIZE; |
5af923b0 | 1158 | |
c5aa993b | 1159 | for (regnum = I0_REGNUM; regnum < I0_REGNUM + 8; regnum++) |
5af923b0 | 1160 | saved_regs_addr[regnum] = |
c906108c | 1161 | frame_addr + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE |
c5aa993b | 1162 | - DUMMY_STACK_REG_BUF_SIZE + 8 * SPARC_INTREG_SIZE; |
60054393 | 1163 | |
5af923b0 MS |
1164 | if (SPARC_HAS_FPU) |
1165 | for (regnum = FP0_REGNUM; regnum < FP_MAX_REGNUM; regnum++) | |
1166 | saved_regs_addr[regnum] = frame_addr + (regnum - FP0_REGNUM) * 4 | |
1167 | - DUMMY_STACK_REG_BUF_SIZE + 24 * SPARC_INTREG_SIZE; | |
1168 | ||
1169 | if (GDB_TARGET_IS_SPARC64) | |
c906108c | 1170 | { |
5af923b0 MS |
1171 | for (regnum = PC_REGNUM; regnum < PC_REGNUM + 7; regnum++) |
1172 | { | |
1173 | saved_regs_addr[regnum] = | |
1174 | frame_addr + (regnum - PC_REGNUM) * SPARC_INTREG_SIZE | |
1175 | - DUMMY_STACK_REG_BUF_SIZE; | |
1176 | } | |
1177 | saved_regs_addr[PSTATE_REGNUM] = | |
1178 | frame_addr + 8 * SPARC_INTREG_SIZE - DUMMY_STACK_REG_BUF_SIZE; | |
c906108c | 1179 | } |
5af923b0 MS |
1180 | else |
1181 | for (regnum = Y_REGNUM; regnum < NUM_REGS; regnum++) | |
1182 | saved_regs_addr[regnum] = | |
1183 | frame_addr + (regnum - Y_REGNUM) * SPARC_INTREG_SIZE | |
1184 | - DUMMY_STACK_REG_BUF_SIZE; | |
1185 | ||
da50a4b7 AC |
1186 | frame_addr = (get_frame_extra_info (fi)->bottom |
1187 | ? get_frame_extra_info (fi)->bottom | |
1188 | : read_sp ()); | |
c906108c | 1189 | } |
da50a4b7 | 1190 | else if (get_frame_extra_info (fi)->flat) |
c906108c SS |
1191 | { |
1192 | CORE_ADDR func_start; | |
50abf9e5 | 1193 | find_pc_partial_function (get_frame_pc (fi), NULL, &func_start, NULL); |
c906108c SS |
1194 | examine_prologue (func_start, 0, fi, saved_regs_addr); |
1195 | ||
1196 | /* Flat register window frame. */ | |
da50a4b7 AC |
1197 | saved_regs_addr[RP_REGNUM] = get_frame_extra_info (fi)->pc_addr; |
1198 | saved_regs_addr[I7_REGNUM] = get_frame_extra_info (fi)->fp_addr; | |
c906108c SS |
1199 | } |
1200 | else | |
1201 | { | |
1202 | /* Normal frame. Just Local and In registers */ | |
da50a4b7 AC |
1203 | frame_addr = (get_frame_extra_info (fi)->bottom |
1204 | ? get_frame_extra_info (fi)->bottom | |
1205 | : read_sp ()); | |
c5aa993b | 1206 | for (regnum = L0_REGNUM; regnum < L0_REGNUM + 8; regnum++) |
5af923b0 | 1207 | saved_regs_addr[regnum] = |
c906108c SS |
1208 | (frame_addr + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE |
1209 | + FRAME_SAVED_L0); | |
c5aa993b | 1210 | for (regnum = I0_REGNUM; regnum < I0_REGNUM + 8; regnum++) |
5af923b0 | 1211 | saved_regs_addr[regnum] = |
c906108c SS |
1212 | (frame_addr + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE |
1213 | + FRAME_SAVED_I0); | |
1214 | } | |
11c02a10 | 1215 | if (get_next_frame (fi)) |
c906108c | 1216 | { |
da50a4b7 | 1217 | if (get_frame_extra_info (fi)->flat) |
c906108c | 1218 | { |
da50a4b7 | 1219 | saved_regs_addr[O7_REGNUM] = get_frame_extra_info (fi)->pc_addr; |
c906108c SS |
1220 | } |
1221 | else | |
1222 | { | |
1223 | /* Pull off either the next frame pointer or the stack pointer */ | |
1224 | CORE_ADDR next_next_frame_addr = | |
da50a4b7 AC |
1225 | (get_frame_extra_info (get_next_frame (fi))->bottom |
1226 | ? get_frame_extra_info (get_next_frame (fi))->bottom | |
1227 | : read_sp ()); | |
c5aa993b | 1228 | for (regnum = O0_REGNUM; regnum < O0_REGNUM + 8; regnum++) |
5af923b0 | 1229 | saved_regs_addr[regnum] = |
c906108c SS |
1230 | (next_next_frame_addr |
1231 | + (regnum - O0_REGNUM) * SPARC_INTREG_SIZE | |
1232 | + FRAME_SAVED_I0); | |
1233 | } | |
1234 | } | |
1235 | /* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */ | |
1236 | /* FIXME -- should this adjust for the sparc64 offset? */ | |
c193f6ac | 1237 | saved_regs_addr[SP_REGNUM] = get_frame_base (fi); |
c906108c SS |
1238 | } |
1239 | ||
1240 | /* Discard from the stack the innermost frame, restoring all saved registers. | |
1241 | ||
95486978 AC |
1242 | Note that the values stored in fsr by |
1243 | deprecated_get_frame_saved_regs are *in the context of the called | |
1244 | frame*. What this means is that the i regs of fsr must be restored | |
1245 | into the o regs of the (calling) frame that we pop into. We don't | |
1246 | care about the output regs of the calling frame, since unless it's | |
1247 | a dummy frame, it won't have any output regs in it. | |
c906108c SS |
1248 | |
1249 | We never have to bother with %l (local) regs, since the called routine's | |
1250 | locals get tossed, and the calling routine's locals are already saved | |
1251 | on its stack. */ | |
1252 | ||
1253 | /* Definitely see tm-sparc.h for more doc of the frame format here. */ | |
1254 | ||
1255 | void | |
fba45db2 | 1256 | sparc_pop_frame (void) |
c906108c SS |
1257 | { |
1258 | register struct frame_info *frame = get_current_frame (); | |
1259 | register CORE_ADDR pc; | |
5af923b0 MS |
1260 | CORE_ADDR *fsr; |
1261 | char *raw_buffer; | |
c906108c SS |
1262 | int regnum; |
1263 | ||
5af923b0 | 1264 | fsr = alloca (NUM_REGS * sizeof (CORE_ADDR)); |
b8b527c5 | 1265 | raw_buffer = alloca (DEPRECATED_REGISTER_BYTES); |
5af923b0 MS |
1266 | sparc_frame_find_saved_regs (frame, &fsr[0]); |
1267 | if (SPARC_HAS_FPU) | |
c906108c | 1268 | { |
5af923b0 | 1269 | if (fsr[FP0_REGNUM]) |
60054393 | 1270 | { |
5af923b0 | 1271 | read_memory (fsr[FP0_REGNUM], raw_buffer, FP_REGISTER_BYTES); |
73937e03 AC |
1272 | deprecated_write_register_bytes (REGISTER_BYTE (FP0_REGNUM), |
1273 | raw_buffer, FP_REGISTER_BYTES); | |
60054393 | 1274 | } |
5af923b0 | 1275 | if (!(GDB_TARGET_IS_SPARC64)) |
60054393 | 1276 | { |
5af923b0 MS |
1277 | if (fsr[FPS_REGNUM]) |
1278 | { | |
1279 | read_memory (fsr[FPS_REGNUM], raw_buffer, SPARC_INTREG_SIZE); | |
4caf0990 | 1280 | deprecated_write_register_gen (FPS_REGNUM, raw_buffer); |
5af923b0 MS |
1281 | } |
1282 | if (fsr[CPS_REGNUM]) | |
1283 | { | |
1284 | read_memory (fsr[CPS_REGNUM], raw_buffer, SPARC_INTREG_SIZE); | |
4caf0990 | 1285 | deprecated_write_register_gen (CPS_REGNUM, raw_buffer); |
5af923b0 | 1286 | } |
60054393 | 1287 | } |
60054393 | 1288 | } |
5af923b0 | 1289 | if (fsr[G1_REGNUM]) |
c906108c | 1290 | { |
5af923b0 | 1291 | read_memory (fsr[G1_REGNUM], raw_buffer, 7 * SPARC_INTREG_SIZE); |
73937e03 AC |
1292 | deprecated_write_register_bytes (REGISTER_BYTE (G1_REGNUM), raw_buffer, |
1293 | 7 * SPARC_INTREG_SIZE); | |
c906108c SS |
1294 | } |
1295 | ||
da50a4b7 | 1296 | if (get_frame_extra_info (frame)->flat) |
c906108c SS |
1297 | { |
1298 | /* Each register might or might not have been saved, need to test | |
c5aa993b | 1299 | individually. */ |
c906108c | 1300 | for (regnum = L0_REGNUM; regnum < L0_REGNUM + 8; ++regnum) |
5af923b0 MS |
1301 | if (fsr[regnum]) |
1302 | write_register (regnum, read_memory_integer (fsr[regnum], | |
c906108c SS |
1303 | SPARC_INTREG_SIZE)); |
1304 | for (regnum = I0_REGNUM; regnum < I0_REGNUM + 8; ++regnum) | |
5af923b0 MS |
1305 | if (fsr[regnum]) |
1306 | write_register (regnum, read_memory_integer (fsr[regnum], | |
c906108c SS |
1307 | SPARC_INTREG_SIZE)); |
1308 | ||
1309 | /* Handle all outs except stack pointer (o0-o5; o7). */ | |
1310 | for (regnum = O0_REGNUM; regnum < O0_REGNUM + 6; ++regnum) | |
5af923b0 MS |
1311 | if (fsr[regnum]) |
1312 | write_register (regnum, read_memory_integer (fsr[regnum], | |
c906108c | 1313 | SPARC_INTREG_SIZE)); |
5af923b0 | 1314 | if (fsr[O0_REGNUM + 7]) |
c906108c | 1315 | write_register (O0_REGNUM + 7, |
5af923b0 | 1316 | read_memory_integer (fsr[O0_REGNUM + 7], |
c906108c SS |
1317 | SPARC_INTREG_SIZE)); |
1318 | ||
6c0e89ed | 1319 | DEPRECATED_DUMMY_WRITE_SP (get_frame_base (frame)); |
c906108c | 1320 | } |
5af923b0 | 1321 | else if (fsr[I0_REGNUM]) |
c906108c SS |
1322 | { |
1323 | CORE_ADDR sp; | |
1324 | ||
5af923b0 MS |
1325 | char *reg_temp; |
1326 | ||
69cdf6a2 | 1327 | reg_temp = alloca (SPARC_INTREG_SIZE * 16); |
c906108c | 1328 | |
5af923b0 | 1329 | read_memory (fsr[I0_REGNUM], raw_buffer, 8 * SPARC_INTREG_SIZE); |
c906108c SS |
1330 | |
1331 | /* Get the ins and locals which we are about to restore. Just | |
c5aa993b JM |
1332 | moving the stack pointer is all that is really needed, except |
1333 | store_inferior_registers is then going to write the ins and | |
1334 | locals from the registers array, so we need to muck with the | |
1335 | registers array. */ | |
5af923b0 MS |
1336 | sp = fsr[SP_REGNUM]; |
1337 | ||
1338 | if (GDB_TARGET_IS_SPARC64 && (sp & 1)) | |
c906108c | 1339 | sp += 2047; |
5af923b0 | 1340 | |
c906108c SS |
1341 | read_memory (sp, reg_temp, SPARC_INTREG_SIZE * 16); |
1342 | ||
1343 | /* Restore the out registers. | |
c5aa993b | 1344 | Among other things this writes the new stack pointer. */ |
73937e03 AC |
1345 | deprecated_write_register_bytes (REGISTER_BYTE (O0_REGNUM), raw_buffer, |
1346 | SPARC_INTREG_SIZE * 8); | |
c906108c | 1347 | |
73937e03 AC |
1348 | deprecated_write_register_bytes (REGISTER_BYTE (L0_REGNUM), reg_temp, |
1349 | SPARC_INTREG_SIZE * 16); | |
c906108c | 1350 | } |
5af923b0 MS |
1351 | |
1352 | if (!(GDB_TARGET_IS_SPARC64)) | |
1353 | if (fsr[PS_REGNUM]) | |
1354 | write_register (PS_REGNUM, | |
1355 | read_memory_integer (fsr[PS_REGNUM], | |
1356 | REGISTER_RAW_SIZE (PS_REGNUM))); | |
1357 | ||
1358 | if (fsr[Y_REGNUM]) | |
1359 | write_register (Y_REGNUM, | |
1360 | read_memory_integer (fsr[Y_REGNUM], | |
1361 | REGISTER_RAW_SIZE (Y_REGNUM))); | |
1362 | if (fsr[PC_REGNUM]) | |
c906108c SS |
1363 | { |
1364 | /* Explicitly specified PC (and maybe NPC) -- just restore them. */ | |
5af923b0 MS |
1365 | write_register (PC_REGNUM, |
1366 | read_memory_integer (fsr[PC_REGNUM], | |
1367 | REGISTER_RAW_SIZE (PC_REGNUM))); | |
1368 | if (fsr[NPC_REGNUM]) | |
c906108c | 1369 | write_register (NPC_REGNUM, |
5af923b0 MS |
1370 | read_memory_integer (fsr[NPC_REGNUM], |
1371 | REGISTER_RAW_SIZE (NPC_REGNUM))); | |
c906108c | 1372 | } |
da50a4b7 | 1373 | else if (get_frame_extra_info (frame)->flat) |
c906108c | 1374 | { |
da50a4b7 | 1375 | if (get_frame_extra_info (frame)->pc_addr) |
c906108c | 1376 | pc = PC_ADJUST ((CORE_ADDR) |
da50a4b7 | 1377 | read_memory_integer (get_frame_extra_info (frame)->pc_addr, |
c906108c SS |
1378 | REGISTER_RAW_SIZE (PC_REGNUM))); |
1379 | else | |
1380 | { | |
1381 | /* I think this happens only in the innermost frame, if so then | |
1382 | it is a complicated way of saying | |
1383 | "pc = read_register (O7_REGNUM);". */ | |
ac2adee5 AC |
1384 | ULONGEST tmp; |
1385 | frame_read_unsigned_register (frame, O7_REGNUM, &tmp); | |
1386 | pc = PC_ADJUST (tmp); | |
c906108c SS |
1387 | } |
1388 | ||
c5aa993b | 1389 | write_register (PC_REGNUM, pc); |
c906108c SS |
1390 | write_register (NPC_REGNUM, pc + 4); |
1391 | } | |
5af923b0 | 1392 | else if (fsr[I7_REGNUM]) |
c906108c SS |
1393 | { |
1394 | /* Return address in %i7 -- adjust it, then restore PC and NPC from it */ | |
5af923b0 | 1395 | pc = PC_ADJUST ((CORE_ADDR) read_memory_integer (fsr[I7_REGNUM], |
c906108c | 1396 | SPARC_INTREG_SIZE)); |
c5aa993b | 1397 | write_register (PC_REGNUM, pc); |
c906108c SS |
1398 | write_register (NPC_REGNUM, pc + 4); |
1399 | } | |
1400 | flush_cached_frames (); | |
1401 | } | |
1402 | ||
1403 | /* On the Sun 4 under SunOS, the compile will leave a fake insn which | |
1404 | encodes the structure size being returned. If we detect such | |
1405 | a fake insn, step past it. */ | |
1406 | ||
1407 | CORE_ADDR | |
fba45db2 | 1408 | sparc_pc_adjust (CORE_ADDR pc) |
c906108c SS |
1409 | { |
1410 | unsigned long insn; | |
1411 | char buf[4]; | |
1412 | int err; | |
1413 | ||
1414 | err = target_read_memory (pc + 8, buf, 4); | |
1415 | insn = extract_unsigned_integer (buf, 4); | |
1416 | if ((err == 0) && (insn & 0xffc00000) == 0) | |
c5aa993b | 1417 | return pc + 12; |
c906108c | 1418 | else |
c5aa993b | 1419 | return pc + 8; |
c906108c SS |
1420 | } |
1421 | ||
1422 | /* If pc is in a shared library trampoline, return its target. | |
1423 | The SunOs 4.x linker rewrites the jump table entries for PIC | |
1424 | compiled modules in the main executable to bypass the dynamic linker | |
1425 | with jumps of the form | |
c5aa993b JM |
1426 | sethi %hi(addr),%g1 |
1427 | jmp %g1+%lo(addr) | |
c906108c SS |
1428 | and removes the corresponding jump table relocation entry in the |
1429 | dynamic relocations. | |
1430 | find_solib_trampoline_target relies on the presence of the jump | |
1431 | table relocation entry, so we have to detect these jump instructions | |
1432 | by hand. */ | |
1433 | ||
1434 | CORE_ADDR | |
fba45db2 | 1435 | sunos4_skip_trampoline_code (CORE_ADDR pc) |
c906108c SS |
1436 | { |
1437 | unsigned long insn1; | |
1438 | char buf[4]; | |
1439 | int err; | |
1440 | ||
1441 | err = target_read_memory (pc, buf, 4); | |
1442 | insn1 = extract_unsigned_integer (buf, 4); | |
1443 | if (err == 0 && (insn1 & 0xffc00000) == 0x03000000) | |
1444 | { | |
1445 | unsigned long insn2; | |
1446 | ||
1447 | err = target_read_memory (pc + 4, buf, 4); | |
1448 | insn2 = extract_unsigned_integer (buf, 4); | |
1449 | if (err == 0 && (insn2 & 0xffffe000) == 0x81c06000) | |
1450 | { | |
1451 | CORE_ADDR target_pc = (insn1 & 0x3fffff) << 10; | |
1452 | int delta = insn2 & 0x1fff; | |
1453 | ||
1454 | /* Sign extend the displacement. */ | |
1455 | if (delta & 0x1000) | |
1456 | delta |= ~0x1fff; | |
1457 | return target_pc + delta; | |
1458 | } | |
1459 | } | |
1460 | return find_solib_trampoline_target (pc); | |
1461 | } | |
1462 | \f | |
c5aa993b | 1463 | #ifdef USE_PROC_FS /* Target dependent support for /proc */ |
9846de1b | 1464 | /* *INDENT-OFF* */ |
c906108c SS |
1465 | /* The /proc interface divides the target machine's register set up into |
1466 | two different sets, the general register set (gregset) and the floating | |
1467 | point register set (fpregset). For each set, there is an ioctl to get | |
1468 | the current register set and another ioctl to set the current values. | |
1469 | ||
1470 | The actual structure passed through the ioctl interface is, of course, | |
1471 | naturally machine dependent, and is different for each set of registers. | |
1472 | For the sparc for example, the general register set is typically defined | |
1473 | by: | |
1474 | ||
1475 | typedef int gregset_t[38]; | |
1476 | ||
1477 | #define R_G0 0 | |
1478 | ... | |
1479 | #define R_TBR 37 | |
1480 | ||
1481 | and the floating point set by: | |
1482 | ||
1483 | typedef struct prfpregset { | |
1484 | union { | |
1485 | u_long pr_regs[32]; | |
1486 | double pr_dregs[16]; | |
1487 | } pr_fr; | |
1488 | void * pr_filler; | |
1489 | u_long pr_fsr; | |
1490 | u_char pr_qcnt; | |
1491 | u_char pr_q_entrysize; | |
1492 | u_char pr_en; | |
1493 | u_long pr_q[64]; | |
1494 | } prfpregset_t; | |
1495 | ||
1496 | These routines provide the packing and unpacking of gregset_t and | |
1497 | fpregset_t formatted data. | |
1498 | ||
1499 | */ | |
9846de1b | 1500 | /* *INDENT-ON* */ |
c906108c SS |
1501 | |
1502 | /* Given a pointer to a general register set in /proc format (gregset_t *), | |
1503 | unpack the register contents and supply them as gdb's idea of the current | |
1504 | register values. */ | |
1505 | ||
1506 | void | |
fba45db2 | 1507 | supply_gregset (gdb_gregset_t *gregsetp) |
c906108c | 1508 | { |
5af923b0 MS |
1509 | prgreg_t *regp = (prgreg_t *) gregsetp; |
1510 | int regi, offset = 0; | |
1511 | ||
1512 | /* If the host is 64-bit sparc, but the target is 32-bit sparc, | |
1513 | then the gregset may contain 64-bit ints while supply_register | |
1514 | is expecting 32-bit ints. Compensate. */ | |
1515 | if (sizeof (regp[0]) == 8 && SPARC_INTREG_SIZE == 4) | |
1516 | offset = 4; | |
c906108c SS |
1517 | |
1518 | /* GDB register numbers for Gn, On, Ln, In all match /proc reg numbers. */ | |
5af923b0 | 1519 | /* FIXME MVS: assumes the order of the first 32 elements... */ |
c5aa993b | 1520 | for (regi = G0_REGNUM; regi <= I7_REGNUM; regi++) |
c906108c | 1521 | { |
5af923b0 | 1522 | supply_register (regi, ((char *) (regp + regi)) + offset); |
c906108c SS |
1523 | } |
1524 | ||
1525 | /* These require a bit more care. */ | |
5af923b0 MS |
1526 | supply_register (PC_REGNUM, ((char *) (regp + R_PC)) + offset); |
1527 | supply_register (NPC_REGNUM, ((char *) (regp + R_nPC)) + offset); | |
1528 | supply_register (Y_REGNUM, ((char *) (regp + R_Y)) + offset); | |
1529 | ||
1530 | if (GDB_TARGET_IS_SPARC64) | |
1531 | { | |
1532 | #ifdef R_CCR | |
1533 | supply_register (CCR_REGNUM, ((char *) (regp + R_CCR)) + offset); | |
1534 | #else | |
1535 | supply_register (CCR_REGNUM, NULL); | |
1536 | #endif | |
1537 | #ifdef R_FPRS | |
1538 | supply_register (FPRS_REGNUM, ((char *) (regp + R_FPRS)) + offset); | |
1539 | #else | |
1540 | supply_register (FPRS_REGNUM, NULL); | |
1541 | #endif | |
1542 | #ifdef R_ASI | |
1543 | supply_register (ASI_REGNUM, ((char *) (regp + R_ASI)) + offset); | |
1544 | #else | |
1545 | supply_register (ASI_REGNUM, NULL); | |
1546 | #endif | |
1547 | } | |
1548 | else /* sparc32 */ | |
1549 | { | |
1550 | #ifdef R_PS | |
1551 | supply_register (PS_REGNUM, ((char *) (regp + R_PS)) + offset); | |
1552 | #else | |
1553 | supply_register (PS_REGNUM, NULL); | |
1554 | #endif | |
1555 | ||
1556 | /* For 64-bit hosts, R_WIM and R_TBR may not be defined. | |
1557 | Steal R_ASI and R_FPRS, and hope for the best! */ | |
1558 | ||
1559 | #if !defined (R_WIM) && defined (R_ASI) | |
1560 | #define R_WIM R_ASI | |
1561 | #endif | |
1562 | ||
1563 | #if !defined (R_TBR) && defined (R_FPRS) | |
1564 | #define R_TBR R_FPRS | |
1565 | #endif | |
1566 | ||
1567 | #if defined (R_WIM) | |
1568 | supply_register (WIM_REGNUM, ((char *) (regp + R_WIM)) + offset); | |
1569 | #else | |
1570 | supply_register (WIM_REGNUM, NULL); | |
1571 | #endif | |
1572 | ||
1573 | #if defined (R_TBR) | |
1574 | supply_register (TBR_REGNUM, ((char *) (regp + R_TBR)) + offset); | |
1575 | #else | |
1576 | supply_register (TBR_REGNUM, NULL); | |
1577 | #endif | |
1578 | } | |
c906108c SS |
1579 | |
1580 | /* Fill inaccessible registers with zero. */ | |
5af923b0 MS |
1581 | if (GDB_TARGET_IS_SPARC64) |
1582 | { | |
1583 | /* | |
1584 | * don't know how to get value of any of the following: | |
1585 | */ | |
1586 | supply_register (VER_REGNUM, NULL); | |
1587 | supply_register (TICK_REGNUM, NULL); | |
1588 | supply_register (PIL_REGNUM, NULL); | |
1589 | supply_register (PSTATE_REGNUM, NULL); | |
1590 | supply_register (TSTATE_REGNUM, NULL); | |
1591 | supply_register (TBA_REGNUM, NULL); | |
1592 | supply_register (TL_REGNUM, NULL); | |
1593 | supply_register (TT_REGNUM, NULL); | |
1594 | supply_register (TPC_REGNUM, NULL); | |
1595 | supply_register (TNPC_REGNUM, NULL); | |
1596 | supply_register (WSTATE_REGNUM, NULL); | |
1597 | supply_register (CWP_REGNUM, NULL); | |
1598 | supply_register (CANSAVE_REGNUM, NULL); | |
1599 | supply_register (CANRESTORE_REGNUM, NULL); | |
1600 | supply_register (CLEANWIN_REGNUM, NULL); | |
1601 | supply_register (OTHERWIN_REGNUM, NULL); | |
1602 | supply_register (ASR16_REGNUM, NULL); | |
1603 | supply_register (ASR17_REGNUM, NULL); | |
1604 | supply_register (ASR18_REGNUM, NULL); | |
1605 | supply_register (ASR19_REGNUM, NULL); | |
1606 | supply_register (ASR20_REGNUM, NULL); | |
1607 | supply_register (ASR21_REGNUM, NULL); | |
1608 | supply_register (ASR22_REGNUM, NULL); | |
1609 | supply_register (ASR23_REGNUM, NULL); | |
1610 | supply_register (ASR24_REGNUM, NULL); | |
1611 | supply_register (ASR25_REGNUM, NULL); | |
1612 | supply_register (ASR26_REGNUM, NULL); | |
1613 | supply_register (ASR27_REGNUM, NULL); | |
1614 | supply_register (ASR28_REGNUM, NULL); | |
1615 | supply_register (ASR29_REGNUM, NULL); | |
1616 | supply_register (ASR30_REGNUM, NULL); | |
1617 | supply_register (ASR31_REGNUM, NULL); | |
1618 | supply_register (ICC_REGNUM, NULL); | |
1619 | supply_register (XCC_REGNUM, NULL); | |
1620 | } | |
1621 | else | |
1622 | { | |
1623 | supply_register (CPS_REGNUM, NULL); | |
1624 | } | |
c906108c SS |
1625 | } |
1626 | ||
1627 | void | |
fba45db2 | 1628 | fill_gregset (gdb_gregset_t *gregsetp, int regno) |
c906108c | 1629 | { |
5af923b0 MS |
1630 | prgreg_t *regp = (prgreg_t *) gregsetp; |
1631 | int regi, offset = 0; | |
1632 | ||
1633 | /* If the host is 64-bit sparc, but the target is 32-bit sparc, | |
1634 | then the gregset may contain 64-bit ints while supply_register | |
1635 | is expecting 32-bit ints. Compensate. */ | |
1636 | if (sizeof (regp[0]) == 8 && SPARC_INTREG_SIZE == 4) | |
1637 | offset = 4; | |
c906108c | 1638 | |
c5aa993b | 1639 | for (regi = 0; regi <= R_I7; regi++) |
5af923b0 | 1640 | if ((regno == -1) || (regno == regi)) |
4caf0990 | 1641 | deprecated_read_register_gen (regi, (char *) (regp + regi) + offset); |
5af923b0 | 1642 | |
c906108c | 1643 | if ((regno == -1) || (regno == PC_REGNUM)) |
4caf0990 | 1644 | deprecated_read_register_gen (PC_REGNUM, (char *) (regp + R_PC) + offset); |
5af923b0 | 1645 | |
c906108c | 1646 | if ((regno == -1) || (regno == NPC_REGNUM)) |
4caf0990 | 1647 | deprecated_read_register_gen (NPC_REGNUM, (char *) (regp + R_nPC) + offset); |
5af923b0 MS |
1648 | |
1649 | if ((regno == -1) || (regno == Y_REGNUM)) | |
4caf0990 | 1650 | deprecated_read_register_gen (Y_REGNUM, (char *) (regp + R_Y) + offset); |
5af923b0 MS |
1651 | |
1652 | if (GDB_TARGET_IS_SPARC64) | |
c906108c | 1653 | { |
5af923b0 MS |
1654 | #ifdef R_CCR |
1655 | if (regno == -1 || regno == CCR_REGNUM) | |
4caf0990 | 1656 | deprecated_read_register_gen (CCR_REGNUM, ((char *) (regp + R_CCR)) + offset); |
5af923b0 MS |
1657 | #endif |
1658 | #ifdef R_FPRS | |
1659 | if (regno == -1 || regno == FPRS_REGNUM) | |
4caf0990 | 1660 | deprecated_read_register_gen (FPRS_REGNUM, ((char *) (regp + R_FPRS)) + offset); |
5af923b0 MS |
1661 | #endif |
1662 | #ifdef R_ASI | |
1663 | if (regno == -1 || regno == ASI_REGNUM) | |
4caf0990 | 1664 | deprecated_read_register_gen (ASI_REGNUM, ((char *) (regp + R_ASI)) + offset); |
5af923b0 | 1665 | #endif |
c906108c | 1666 | } |
5af923b0 | 1667 | else /* sparc32 */ |
c906108c | 1668 | { |
5af923b0 MS |
1669 | #ifdef R_PS |
1670 | if (regno == -1 || regno == PS_REGNUM) | |
4caf0990 | 1671 | deprecated_read_register_gen (PS_REGNUM, ((char *) (regp + R_PS)) + offset); |
5af923b0 MS |
1672 | #endif |
1673 | ||
1674 | /* For 64-bit hosts, R_WIM and R_TBR may not be defined. | |
1675 | Steal R_ASI and R_FPRS, and hope for the best! */ | |
1676 | ||
1677 | #if !defined (R_WIM) && defined (R_ASI) | |
1678 | #define R_WIM R_ASI | |
1679 | #endif | |
1680 | ||
1681 | #if !defined (R_TBR) && defined (R_FPRS) | |
1682 | #define R_TBR R_FPRS | |
1683 | #endif | |
1684 | ||
1685 | #if defined (R_WIM) | |
1686 | if (regno == -1 || regno == WIM_REGNUM) | |
4caf0990 | 1687 | deprecated_read_register_gen (WIM_REGNUM, ((char *) (regp + R_WIM)) + offset); |
5af923b0 MS |
1688 | #else |
1689 | if (regno == -1 || regno == WIM_REGNUM) | |
4caf0990 | 1690 | deprecated_read_register_gen (WIM_REGNUM, NULL); |
5af923b0 MS |
1691 | #endif |
1692 | ||
1693 | #if defined (R_TBR) | |
1694 | if (regno == -1 || regno == TBR_REGNUM) | |
4caf0990 | 1695 | deprecated_read_register_gen (TBR_REGNUM, ((char *) (regp + R_TBR)) + offset); |
5af923b0 MS |
1696 | #else |
1697 | if (regno == -1 || regno == TBR_REGNUM) | |
4caf0990 | 1698 | deprecated_read_register_gen (TBR_REGNUM, NULL); |
5af923b0 | 1699 | #endif |
c906108c SS |
1700 | } |
1701 | } | |
1702 | ||
c906108c | 1703 | /* Given a pointer to a floating point register set in /proc format |
c5aa993b JM |
1704 | (fpregset_t *), unpack the register contents and supply them as gdb's |
1705 | idea of the current floating point register values. */ | |
c906108c | 1706 | |
c5aa993b | 1707 | void |
fba45db2 | 1708 | supply_fpregset (gdb_fpregset_t *fpregsetp) |
c906108c SS |
1709 | { |
1710 | register int regi; | |
1711 | char *from; | |
c5aa993b | 1712 | |
5af923b0 | 1713 | if (!SPARC_HAS_FPU) |
60054393 MS |
1714 | return; |
1715 | ||
c5aa993b | 1716 | for (regi = FP0_REGNUM; regi < FP_MAX_REGNUM; regi++) |
c906108c | 1717 | { |
c5aa993b | 1718 | from = (char *) &fpregsetp->pr_fr.pr_regs[regi - FP0_REGNUM]; |
c906108c SS |
1719 | supply_register (regi, from); |
1720 | } | |
5af923b0 MS |
1721 | |
1722 | if (GDB_TARGET_IS_SPARC64) | |
1723 | { | |
1724 | /* | |
1725 | * don't know how to get value of the following. | |
1726 | */ | |
1727 | supply_register (FSR_REGNUM, NULL); /* zero it out for now */ | |
1728 | supply_register (FCC0_REGNUM, NULL); | |
1729 | supply_register (FCC1_REGNUM, NULL); /* don't know how to get value */ | |
1730 | supply_register (FCC2_REGNUM, NULL); /* don't know how to get value */ | |
1731 | supply_register (FCC3_REGNUM, NULL); /* don't know how to get value */ | |
1732 | } | |
1733 | else | |
1734 | { | |
1735 | supply_register (FPS_REGNUM, (char *) &(fpregsetp->pr_fsr)); | |
1736 | } | |
c906108c SS |
1737 | } |
1738 | ||
1739 | /* Given a pointer to a floating point register set in /proc format | |
c5aa993b JM |
1740 | (fpregset_t *), update the register specified by REGNO from gdb's idea |
1741 | of the current floating point register set. If REGNO is -1, update | |
1742 | them all. */ | |
5af923b0 | 1743 | /* This will probably need some changes for sparc64. */ |
c906108c SS |
1744 | |
1745 | void | |
fba45db2 | 1746 | fill_fpregset (gdb_fpregset_t *fpregsetp, int regno) |
c906108c SS |
1747 | { |
1748 | int regi; | |
1749 | char *to; | |
1750 | char *from; | |
1751 | ||
5af923b0 | 1752 | if (!SPARC_HAS_FPU) |
60054393 MS |
1753 | return; |
1754 | ||
c5aa993b | 1755 | for (regi = FP0_REGNUM; regi < FP_MAX_REGNUM; regi++) |
c906108c SS |
1756 | { |
1757 | if ((regno == -1) || (regno == regi)) | |
1758 | { | |
524d7c18 | 1759 | from = (char *) &deprecated_registers[REGISTER_BYTE (regi)]; |
c5aa993b | 1760 | to = (char *) &fpregsetp->pr_fr.pr_regs[regi - FP0_REGNUM]; |
c906108c SS |
1761 | memcpy (to, from, REGISTER_RAW_SIZE (regi)); |
1762 | } | |
1763 | } | |
5af923b0 MS |
1764 | |
1765 | if (!(GDB_TARGET_IS_SPARC64)) /* FIXME: does Sparc64 have this register? */ | |
1766 | if ((regno == -1) || (regno == FPS_REGNUM)) | |
1767 | { | |
524d7c18 | 1768 | from = (char *)&deprecated_registers[REGISTER_BYTE (FPS_REGNUM)]; |
5af923b0 MS |
1769 | to = (char *) &fpregsetp->pr_fsr; |
1770 | memcpy (to, from, REGISTER_RAW_SIZE (FPS_REGNUM)); | |
1771 | } | |
c906108c SS |
1772 | } |
1773 | ||
c5aa993b | 1774 | #endif /* USE_PROC_FS */ |
c906108c | 1775 | |
a48442a0 RE |
1776 | /* Because of Multi-arch, GET_LONGJMP_TARGET is always defined. So test |
1777 | for a definition of JB_PC. */ | |
1778 | #ifdef JB_PC | |
c906108c SS |
1779 | |
1780 | /* Figure out where the longjmp will land. We expect that we have just entered | |
1781 | longjmp and haven't yet setup the stack frame, so the args are still in the | |
1782 | output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we | |
1783 | extract the pc (JB_PC) that we will land at. The pc is copied into ADDR. | |
1784 | This routine returns true on success */ | |
1785 | ||
1786 | int | |
fba45db2 | 1787 | get_longjmp_target (CORE_ADDR *pc) |
c906108c SS |
1788 | { |
1789 | CORE_ADDR jb_addr; | |
1790 | #define LONGJMP_TARGET_SIZE 4 | |
1791 | char buf[LONGJMP_TARGET_SIZE]; | |
1792 | ||
1793 | jb_addr = read_register (O0_REGNUM); | |
1794 | ||
1795 | if (target_read_memory (jb_addr + JB_PC * JB_ELEMENT_SIZE, buf, | |
1796 | LONGJMP_TARGET_SIZE)) | |
1797 | return 0; | |
1798 | ||
1799 | *pc = extract_address (buf, LONGJMP_TARGET_SIZE); | |
1800 | ||
1801 | return 1; | |
1802 | } | |
1803 | #endif /* GET_LONGJMP_TARGET */ | |
1804 | \f | |
1805 | #ifdef STATIC_TRANSFORM_NAME | |
1806 | /* SunPRO (3.0 at least), encodes the static variables. This is not | |
1807 | related to C++ mangling, it is done for C too. */ | |
1808 | ||
1809 | char * | |
fba45db2 | 1810 | sunpro_static_transform_name (char *name) |
c906108c SS |
1811 | { |
1812 | char *p; | |
1813 | if (name[0] == '$') | |
1814 | { | |
1815 | /* For file-local statics there will be a dollar sign, a bunch | |
c5aa993b JM |
1816 | of junk (the contents of which match a string given in the |
1817 | N_OPT), a period and the name. For function-local statics | |
1818 | there will be a bunch of junk (which seems to change the | |
1819 | second character from 'A' to 'B'), a period, the name of the | |
1820 | function, and the name. So just skip everything before the | |
1821 | last period. */ | |
c906108c SS |
1822 | p = strrchr (name, '.'); |
1823 | if (p != NULL) | |
1824 | name = p + 1; | |
1825 | } | |
1826 | return name; | |
1827 | } | |
1828 | #endif /* STATIC_TRANSFORM_NAME */ | |
1829 | \f | |
1830 | ||
1831 | /* Utilities for printing registers. | |
1832 | Page numbers refer to the SPARC Architecture Manual. */ | |
1833 | ||
5af923b0 | 1834 | static void dump_ccreg (char *, int); |
c906108c SS |
1835 | |
1836 | static void | |
fba45db2 | 1837 | dump_ccreg (char *reg, int val) |
c906108c SS |
1838 | { |
1839 | /* page 41 */ | |
1840 | printf_unfiltered ("%s:%s,%s,%s,%s", reg, | |
c5aa993b JM |
1841 | val & 8 ? "N" : "NN", |
1842 | val & 4 ? "Z" : "NZ", | |
1843 | val & 2 ? "O" : "NO", | |
5af923b0 | 1844 | val & 1 ? "C" : "NC"); |
c906108c SS |
1845 | } |
1846 | ||
1847 | static char * | |
fba45db2 | 1848 | decode_asi (int val) |
c906108c SS |
1849 | { |
1850 | /* page 72 */ | |
1851 | switch (val) | |
1852 | { | |
c5aa993b JM |
1853 | case 4: |
1854 | return "ASI_NUCLEUS"; | |
1855 | case 0x0c: | |
1856 | return "ASI_NUCLEUS_LITTLE"; | |
1857 | case 0x10: | |
1858 | return "ASI_AS_IF_USER_PRIMARY"; | |
1859 | case 0x11: | |
1860 | return "ASI_AS_IF_USER_SECONDARY"; | |
1861 | case 0x18: | |
1862 | return "ASI_AS_IF_USER_PRIMARY_LITTLE"; | |
1863 | case 0x19: | |
1864 | return "ASI_AS_IF_USER_SECONDARY_LITTLE"; | |
1865 | case 0x80: | |
1866 | return "ASI_PRIMARY"; | |
1867 | case 0x81: | |
1868 | return "ASI_SECONDARY"; | |
1869 | case 0x82: | |
1870 | return "ASI_PRIMARY_NOFAULT"; | |
1871 | case 0x83: | |
1872 | return "ASI_SECONDARY_NOFAULT"; | |
1873 | case 0x88: | |
1874 | return "ASI_PRIMARY_LITTLE"; | |
1875 | case 0x89: | |
1876 | return "ASI_SECONDARY_LITTLE"; | |
1877 | case 0x8a: | |
1878 | return "ASI_PRIMARY_NOFAULT_LITTLE"; | |
1879 | case 0x8b: | |
1880 | return "ASI_SECONDARY_NOFAULT_LITTLE"; | |
1881 | default: | |
1882 | return NULL; | |
c906108c SS |
1883 | } |
1884 | } | |
1885 | ||
867f3898 | 1886 | /* Pretty print various registers. */ |
c906108c SS |
1887 | /* FIXME: Would be nice if this did some fancy things for 32 bit sparc. */ |
1888 | ||
87647bb0 | 1889 | static void |
fba45db2 | 1890 | sparc_print_register_hook (int regno) |
c906108c SS |
1891 | { |
1892 | ULONGEST val; | |
1893 | ||
1894 | /* Handle double/quad versions of lower 32 fp regs. */ | |
1895 | if (regno >= FP0_REGNUM && regno < FP0_REGNUM + 32 | |
1896 | && (regno & 1) == 0) | |
1897 | { | |
1898 | char value[16]; | |
1899 | ||
6e7f8b9c AC |
1900 | if (frame_register_read (deprecated_selected_frame, regno, value) |
1901 | && frame_register_read (deprecated_selected_frame, regno + 1, value + 4)) | |
c906108c SS |
1902 | { |
1903 | printf_unfiltered ("\t"); | |
1904 | print_floating (value, builtin_type_double, gdb_stdout); | |
1905 | } | |
c5aa993b | 1906 | #if 0 /* FIXME: gdb doesn't handle long doubles */ |
c906108c SS |
1907 | if ((regno & 3) == 0) |
1908 | { | |
6e7f8b9c AC |
1909 | if (frame_register_read (deprecated_selected_frame, regno + 2, value + 8) |
1910 | && frame_register_read (deprecated_selected_frame, regno + 3, value + 12)) | |
c906108c SS |
1911 | { |
1912 | printf_unfiltered ("\t"); | |
1913 | print_floating (value, builtin_type_long_double, gdb_stdout); | |
1914 | } | |
1915 | } | |
1916 | #endif | |
1917 | return; | |
1918 | } | |
1919 | ||
c5aa993b | 1920 | #if 0 /* FIXME: gdb doesn't handle long doubles */ |
c906108c SS |
1921 | /* Print upper fp regs as long double if appropriate. */ |
1922 | if (regno >= FP0_REGNUM + 32 && regno < FP_MAX_REGNUM | |
c5aa993b JM |
1923 | /* We test for even numbered regs and not a multiple of 4 because |
1924 | the upper fp regs are recorded as doubles. */ | |
c906108c SS |
1925 | && (regno & 1) == 0) |
1926 | { | |
1927 | char value[16]; | |
1928 | ||
6e7f8b9c AC |
1929 | if (frame_register_read (deprecated_selected_frame, regno, value) |
1930 | && frame_register_read (deprecated_selected_frame, regno + 1, value + 8)) | |
c906108c SS |
1931 | { |
1932 | printf_unfiltered ("\t"); | |
1933 | print_floating (value, builtin_type_long_double, gdb_stdout); | |
1934 | } | |
1935 | return; | |
1936 | } | |
1937 | #endif | |
1938 | ||
1939 | /* FIXME: Some of these are priviledged registers. | |
1940 | Not sure how they should be handled. */ | |
1941 | ||
1942 | #define BITS(n, mask) ((int) (((val) >> (n)) & (mask))) | |
1943 | ||
1944 | val = read_register (regno); | |
1945 | ||
1946 | /* pages 40 - 60 */ | |
5af923b0 MS |
1947 | if (GDB_TARGET_IS_SPARC64) |
1948 | switch (regno) | |
c906108c | 1949 | { |
5af923b0 MS |
1950 | case CCR_REGNUM: |
1951 | printf_unfiltered ("\t"); | |
1952 | dump_ccreg ("xcc", val >> 4); | |
1953 | printf_unfiltered (", "); | |
1954 | dump_ccreg ("icc", val & 15); | |
c906108c | 1955 | break; |
5af923b0 MS |
1956 | case FPRS_REGNUM: |
1957 | printf ("\tfef:%d, du:%d, dl:%d", | |
1958 | BITS (2, 1), BITS (1, 1), BITS (0, 1)); | |
c906108c | 1959 | break; |
5af923b0 MS |
1960 | case FSR_REGNUM: |
1961 | { | |
1962 | static char *fcc[4] = | |
1963 | {"=", "<", ">", "?"}; | |
1964 | static char *rd[4] = | |
1965 | {"N", "0", "+", "-"}; | |
1966 | /* Long, but I'd rather leave it as is and use a wide screen. */ | |
1967 | printf_filtered ("\t0:%s, 1:%s, 2:%s, 3:%s, rd:%s, tem:%d, ", | |
1968 | fcc[BITS (10, 3)], fcc[BITS (32, 3)], | |
1969 | fcc[BITS (34, 3)], fcc[BITS (36, 3)], | |
1970 | rd[BITS (30, 3)], BITS (23, 31)); | |
1971 | printf_filtered ("ns:%d, ver:%d, ftt:%d, qne:%d, aexc:%d, cexc:%d", | |
1972 | BITS (22, 1), BITS (17, 7), BITS (14, 7), | |
1973 | BITS (13, 1), BITS (5, 31), BITS (0, 31)); | |
1974 | break; | |
1975 | } | |
1976 | case ASI_REGNUM: | |
1977 | { | |
1978 | char *asi = decode_asi (val); | |
1979 | if (asi != NULL) | |
1980 | printf ("\t%s", asi); | |
1981 | break; | |
1982 | } | |
1983 | case VER_REGNUM: | |
1984 | printf ("\tmanuf:%d, impl:%d, mask:%d, maxtl:%d, maxwin:%d", | |
1985 | BITS (48, 0xffff), BITS (32, 0xffff), | |
1986 | BITS (24, 0xff), BITS (8, 0xff), BITS (0, 31)); | |
1987 | break; | |
1988 | case PSTATE_REGNUM: | |
1989 | { | |
1990 | static char *mm[4] = | |
1991 | {"tso", "pso", "rso", "?"}; | |
1992 | printf_filtered ("\tcle:%d, tle:%d, mm:%s, red:%d, ", | |
1993 | BITS (9, 1), BITS (8, 1), | |
1994 | mm[BITS (6, 3)], BITS (5, 1)); | |
1995 | printf_filtered ("pef:%d, am:%d, priv:%d, ie:%d, ag:%d", | |
1996 | BITS (4, 1), BITS (3, 1), BITS (2, 1), | |
1997 | BITS (1, 1), BITS (0, 1)); | |
1998 | break; | |
1999 | } | |
2000 | case TSTATE_REGNUM: | |
2001 | /* FIXME: print all 4? */ | |
2002 | break; | |
2003 | case TT_REGNUM: | |
2004 | /* FIXME: print all 4? */ | |
2005 | break; | |
2006 | case TPC_REGNUM: | |
2007 | /* FIXME: print all 4? */ | |
2008 | break; | |
2009 | case TNPC_REGNUM: | |
2010 | /* FIXME: print all 4? */ | |
2011 | break; | |
2012 | case WSTATE_REGNUM: | |
2013 | printf ("\tother:%d, normal:%d", BITS (3, 7), BITS (0, 7)); | |
2014 | break; | |
2015 | case CWP_REGNUM: | |
2016 | printf ("\t%d", BITS (0, 31)); | |
2017 | break; | |
2018 | case CANSAVE_REGNUM: | |
2019 | printf ("\t%-2d before spill", BITS (0, 31)); | |
2020 | break; | |
2021 | case CANRESTORE_REGNUM: | |
2022 | printf ("\t%-2d before fill", BITS (0, 31)); | |
2023 | break; | |
2024 | case CLEANWIN_REGNUM: | |
2025 | printf ("\t%-2d before clean", BITS (0, 31)); | |
2026 | break; | |
2027 | case OTHERWIN_REGNUM: | |
2028 | printf ("\t%d", BITS (0, 31)); | |
c906108c SS |
2029 | break; |
2030 | } | |
5af923b0 MS |
2031 | else /* Sparc32 */ |
2032 | switch (regno) | |
c906108c | 2033 | { |
5af923b0 MS |
2034 | case PS_REGNUM: |
2035 | printf ("\ticc:%c%c%c%c, pil:%d, s:%d, ps:%d, et:%d, cwp:%d", | |
2036 | BITS (23, 1) ? 'N' : '-', BITS (22, 1) ? 'Z' : '-', | |
2037 | BITS (21, 1) ? 'V' : '-', BITS (20, 1) ? 'C' : '-', | |
2038 | BITS (8, 15), BITS (7, 1), BITS (6, 1), BITS (5, 1), | |
c906108c SS |
2039 | BITS (0, 31)); |
2040 | break; | |
5af923b0 MS |
2041 | case FPS_REGNUM: |
2042 | { | |
2043 | static char *fcc[4] = | |
2044 | {"=", "<", ">", "?"}; | |
2045 | static char *rd[4] = | |
2046 | {"N", "0", "+", "-"}; | |
2047 | /* Long, but I'd rather leave it as is and use a wide screen. */ | |
2048 | printf ("\trd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, " | |
2049 | "fcc:%s, aexc:%d, cexc:%d", | |
2050 | rd[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7), | |
2051 | BITS (14, 7), BITS (13, 1), fcc[BITS (10, 3)], BITS (5, 31), | |
2052 | BITS (0, 31)); | |
2053 | break; | |
2054 | } | |
c906108c SS |
2055 | } |
2056 | ||
c906108c SS |
2057 | #undef BITS |
2058 | } | |
87647bb0 AC |
2059 | |
2060 | static void | |
2061 | sparc_print_registers (struct gdbarch *gdbarch, | |
2062 | struct ui_file *file, | |
2063 | struct frame_info *frame, | |
2064 | int regnum, int print_all, | |
2065 | void (*print_register_hook) (int)) | |
2066 | { | |
2067 | int i; | |
2068 | const int numregs = NUM_REGS + NUM_PSEUDO_REGS; | |
0c92afe8 AC |
2069 | char raw_buffer[MAX_REGISTER_SIZE]; |
2070 | char virtual_buffer[MAX_REGISTER_SIZE]; | |
87647bb0 AC |
2071 | |
2072 | for (i = 0; i < numregs; i++) | |
2073 | { | |
2074 | /* Decide between printing all regs, non-float / vector regs, or | |
2075 | specific reg. */ | |
2076 | if (regnum == -1) | |
2077 | { | |
2078 | if (!print_all) | |
2079 | { | |
2080 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (i)) == TYPE_CODE_FLT) | |
2081 | continue; | |
2082 | if (TYPE_VECTOR (REGISTER_VIRTUAL_TYPE (i))) | |
2083 | continue; | |
2084 | } | |
2085 | } | |
2086 | else | |
2087 | { | |
2088 | if (i != regnum) | |
2089 | continue; | |
2090 | } | |
2091 | ||
2092 | /* If the register name is empty, it is undefined for this | |
2093 | processor, so don't display anything. */ | |
2094 | if (REGISTER_NAME (i) == NULL || *(REGISTER_NAME (i)) == '\0') | |
2095 | continue; | |
2096 | ||
2097 | fputs_filtered (REGISTER_NAME (i), file); | |
2098 | print_spaces_filtered (15 - strlen (REGISTER_NAME (i)), file); | |
2099 | ||
2100 | /* Get the data in raw format. */ | |
2101 | if (! frame_register_read (frame, i, raw_buffer)) | |
2102 | { | |
2103 | fprintf_filtered (file, "*value not available*\n"); | |
2104 | continue; | |
2105 | } | |
2106 | ||
2107 | /* FIXME: cagney/2002-08-03: This code shouldn't be necessary. | |
2108 | The function frame_register_read() should have returned the | |
2109 | pre-cooked register so no conversion is necessary. */ | |
2110 | /* Convert raw data to virtual format if necessary. */ | |
2111 | if (REGISTER_CONVERTIBLE (i)) | |
2112 | { | |
2113 | REGISTER_CONVERT_TO_VIRTUAL (i, REGISTER_VIRTUAL_TYPE (i), | |
2114 | raw_buffer, virtual_buffer); | |
2115 | } | |
2116 | else | |
2117 | { | |
2118 | memcpy (virtual_buffer, raw_buffer, | |
2119 | REGISTER_VIRTUAL_SIZE (i)); | |
2120 | } | |
2121 | ||
2122 | /* If virtual format is floating, print it that way, and in raw | |
2123 | hex. */ | |
2124 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (i)) == TYPE_CODE_FLT) | |
2125 | { | |
2126 | int j; | |
2127 | ||
2128 | val_print (REGISTER_VIRTUAL_TYPE (i), virtual_buffer, 0, 0, | |
2129 | file, 0, 1, 0, Val_pretty_default); | |
2130 | ||
2131 | fprintf_filtered (file, "\t(raw 0x"); | |
2132 | for (j = 0; j < REGISTER_RAW_SIZE (i); j++) | |
2133 | { | |
2134 | int idx; | |
2135 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2136 | idx = j; | |
2137 | else | |
2138 | idx = REGISTER_RAW_SIZE (i) - 1 - j; | |
2139 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]); | |
2140 | } | |
2141 | fprintf_filtered (file, ")"); | |
2142 | } | |
2143 | else | |
2144 | { | |
2145 | /* Print the register in hex. */ | |
2146 | val_print (REGISTER_VIRTUAL_TYPE (i), virtual_buffer, 0, 0, | |
2147 | file, 'x', 1, 0, Val_pretty_default); | |
2148 | /* If not a vector register, print it also according to its | |
2149 | natural format. */ | |
2150 | if (TYPE_VECTOR (REGISTER_VIRTUAL_TYPE (i)) == 0) | |
2151 | { | |
2152 | fprintf_filtered (file, "\t"); | |
2153 | val_print (REGISTER_VIRTUAL_TYPE (i), virtual_buffer, 0, 0, | |
2154 | file, 0, 1, 0, Val_pretty_default); | |
2155 | } | |
2156 | } | |
2157 | ||
2158 | /* Some sparc specific info. */ | |
2159 | if (print_register_hook != NULL) | |
2160 | print_register_hook (i); | |
2161 | ||
2162 | fprintf_filtered (file, "\n"); | |
2163 | } | |
2164 | } | |
2165 | ||
2166 | static void | |
2167 | sparc_print_registers_info (struct gdbarch *gdbarch, | |
2168 | struct ui_file *file, | |
2169 | struct frame_info *frame, | |
2170 | int regnum, int print_all) | |
2171 | { | |
2172 | sparc_print_registers (gdbarch, file, frame, regnum, print_all, | |
2173 | sparc_print_register_hook); | |
2174 | } | |
2175 | ||
2176 | void | |
2177 | sparc_do_registers_info (int regnum, int all) | |
2178 | { | |
6e7f8b9c | 2179 | sparc_print_registers_info (current_gdbarch, gdb_stdout, deprecated_selected_frame, |
87647bb0 AC |
2180 | regnum, all); |
2181 | } | |
2182 | ||
f81824a9 AC |
2183 | #if 0 |
2184 | // OBSOLETE static void | |
2185 | // OBSOLETE sparclet_print_registers_info (struct gdbarch *gdbarch, | |
2186 | // OBSOLETE struct ui_file *file, | |
2187 | // OBSOLETE struct frame_info *frame, | |
2188 | // OBSOLETE int regnum, int print_all) | |
2189 | // OBSOLETE { | |
2190 | // OBSOLETE sparc_print_registers (gdbarch, file, frame, regnum, print_all, NULL); | |
2191 | // OBSOLETE } | |
2192 | // OBSOLETE | |
2193 | // OBSOLETE void | |
2194 | // OBSOLETE sparclet_do_registers_info (int regnum, int all) | |
2195 | // OBSOLETE { | |
2196 | // OBSOLETE sparclet_print_registers_info (current_gdbarch, gdb_stdout, | |
2197 | // OBSOLETE deprecated_selected_frame, regnum, all); | |
2198 | // OBSOLETE } | |
2199 | #endif | |
87647bb0 | 2200 | |
c906108c SS |
2201 | \f |
2202 | int | |
fba45db2 | 2203 | gdb_print_insn_sparc (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
2204 | { |
2205 | /* It's necessary to override mach again because print_insn messes it up. */ | |
96baa820 | 2206 | info->mach = TARGET_ARCHITECTURE->mach; |
c906108c SS |
2207 | return print_insn_sparc (memaddr, info); |
2208 | } | |
2209 | \f | |
c906108c | 2210 | |
eb2c22dc MK |
2211 | #define SPARC_F0_REGNUM FP0_REGNUM /* %f0 */ |
2212 | #define SPARC_F1_REGNUM (FP0_REGNUM + 1)/* %f1 */ | |
2213 | #define SPARC_O0_REGNUM O0_REGNUM /* %o0 */ | |
2214 | #define SPARC_O1_REGNUM O1_REGNUM /* %o1 */ | |
2215 | ||
2216 | /* Push the arguments onto the stack and into the appropriate registers. */ | |
2217 | ||
2218 | static CORE_ADDR | |
2219 | sparc32_do_push_arguments (struct regcache *regcache, int nargs, | |
2220 | struct value **args, CORE_ADDR sp) | |
c906108c | 2221 | { |
eb2c22dc MK |
2222 | CORE_ADDR *addr; |
2223 | int size = 0; | |
2224 | int i; | |
2225 | ||
2226 | /* Structure, union and quad-precision arguments are passed by | |
2227 | reference. We allocate space for these arguments on the stack | |
2228 | and record their addresses in an array. Array elements for | |
2229 | arguments that are passed by value will be set to zero.*/ | |
2230 | addr = alloca (nargs * sizeof (CORE_ADDR)); | |
2231 | ||
2232 | for (i = nargs - 1; i >= 0; i--) | |
c906108c | 2233 | { |
eb2c22dc MK |
2234 | struct type *type = VALUE_ENCLOSING_TYPE (args[i]); |
2235 | enum type_code code = TYPE_CODE (type); | |
2236 | int len = TYPE_LENGTH (type); | |
2237 | ||
2238 | /* Push the contents of structure, union and quad-precision | |
2239 | arguments on the stack. */ | |
2240 | if (code == TYPE_CODE_STRUCT || code == TYPE_CODE_UNION || len > 8) | |
2241 | { | |
2242 | /* Keep the stack doubleword aligned. */ | |
2243 | sp -= (len + 7) & ~7; | |
2244 | write_memory (sp, VALUE_CONTENTS_ALL (args[i]), len); | |
2245 | addr[i] = sp; | |
2246 | size += 4; | |
2247 | } | |
2248 | else | |
2249 | { | |
2250 | addr[i] = 0; | |
2251 | size += (len > 4) ? 8 : 4; | |
2252 | } | |
2253 | } | |
2254 | ||
2255 | /* The needed space for outgoing arguments should be a multiple of 4. */ | |
2256 | gdb_assert (size % 4 == 0); | |
2257 | ||
2258 | /* Make sure we reserve space for the first six words of arguments | |
2259 | in the stack frame, even if we don't need them. */ | |
2260 | if (size < 24) | |
2261 | sp -= (24 - size); | |
2262 | ||
2263 | /* Make sure we end up with a doubleword aligned stack in the end. | |
2264 | Reserve an extra word if necessary in order to accomplish this. */ | |
2265 | if ((sp - size) % 8 == 0) | |
2266 | sp -= 4; | |
2267 | ||
2268 | /* Now push the arguments onto the stack. */ | |
2269 | for (i = nargs - 1; i >=0; i--) | |
c906108c | 2270 | { |
eb2c22dc MK |
2271 | char buf[8]; |
2272 | int len; | |
2273 | ||
2274 | if (addr[i]) | |
c906108c | 2275 | { |
eb2c22dc MK |
2276 | store_unsigned_integer (buf, 4, addr[i]); |
2277 | len = 4; | |
2278 | } | |
2279 | else | |
2280 | { | |
2281 | struct value *arg = args[i]; | |
2282 | ||
2283 | len = TYPE_LENGTH (VALUE_ENCLOSING_TYPE (arg)); | |
2284 | ||
2285 | /* Expand signed and unsigned bytes and halfwords as needed. */ | |
2286 | if (len < 4) | |
c906108c | 2287 | { |
eb2c22dc MK |
2288 | arg = value_cast (builtin_type_long, arg); |
2289 | len = 4; | |
c906108c | 2290 | } |
eb2c22dc MK |
2291 | else if (len > 4 && len < 8) |
2292 | { | |
2293 | arg = value_cast (builtin_type_long_long, arg); | |
2294 | len = 4; | |
2295 | } | |
2296 | ||
2297 | gdb_assert (len == 4 || len == 8); | |
2298 | memcpy (buf, VALUE_CONTENTS_ALL (arg), len); | |
2299 | } | |
2300 | ||
2301 | /* We always write the argument word on the stack. */ | |
2302 | sp -= len; | |
2303 | write_memory (sp, buf, len); | |
2304 | ||
2305 | /* If this argument occupies one of the first 6 words, write it | |
2306 | into the appropriate register too. */ | |
2307 | size -= len; | |
2308 | if (size < 24) | |
2309 | { | |
2310 | int regnum = SPARC_O0_REGNUM + (size / 4); | |
2311 | ||
2312 | regcache_cooked_write (regcache, regnum, buf); | |
2313 | if (len == 8 && size < 20) | |
2314 | regcache_cooked_write (regcache, regnum + 1, buf + 4); | |
c906108c | 2315 | } |
c906108c SS |
2316 | } |
2317 | ||
eb2c22dc MK |
2318 | /* Reserve space for the struct/union return value pointer. */ |
2319 | sp -= 4; | |
2320 | ||
2321 | /* Stack should be doubleword aligned at this point. */ | |
2322 | gdb_assert (sp % 8 == 0); | |
2323 | ||
2324 | /* Return the adjusted stack pointer. */ | |
2325 | return sp; | |
2326 | } | |
c906108c | 2327 | |
eb2c22dc MK |
2328 | /* The SPARC passes the arguments on the stack; arguments smaller |
2329 | than an int are promoted to an int. The first 6 words worth of | |
2330 | args are also passed in registers o0 - o5. */ | |
2331 | ||
2332 | CORE_ADDR | |
2333 | sparc32_push_arguments (int nargs, struct value **args, CORE_ADDR sp, | |
2334 | int struct_return, CORE_ADDR struct_addr) | |
2335 | { | |
2336 | sp = sparc32_do_push_arguments (current_regcache, nargs, args, sp); | |
2337 | ||
2338 | /* FIXME: kettenis/20030525: We don't let this function set the | |
2339 | struct/union return pointer just yet. */ | |
2340 | #if 0 | |
2341 | if (struct_return) | |
5af923b0 | 2342 | { |
eb2c22dc MK |
2343 | char buf[4]; |
2344 | ||
2345 | /* The space for the struct/union return value pointer has | |
2346 | already been reserved. */ | |
2347 | store_unsigned_integer (buf, 4, struct_addr); | |
2348 | write (sp, buf, 4); | |
5af923b0 | 2349 | } |
c906108c SS |
2350 | |
2351 | return sp; | |
eb2c22dc MK |
2352 | #else |
2353 | return sp + 4; | |
2354 | #endif | |
c906108c SS |
2355 | } |
2356 | ||
44b7b84e MK |
2357 | /* Extract from REGCACHE a function return value of type TYPE and copy |
2358 | that into VALBUF. | |
2359 | ||
2360 | Note that REGCACHE specifies the register values for the frame of | |
2361 | the calling function. This means that we need to fetch the value | |
2362 | form %o0 and %o1, which correspond to %i0 and %i1 in the frame of | |
2363 | the called function. */ | |
c906108c SS |
2364 | |
2365 | void | |
44b7b84e MK |
2366 | sparc32_extract_return_value (struct type *type, struct regcache *regcache, |
2367 | void *valbuf) | |
c906108c | 2368 | { |
44b7b84e MK |
2369 | int len = TYPE_LENGTH (type); |
2370 | char buf[8]; | |
c906108c SS |
2371 | |
2372 | if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU) | |
44b7b84e MK |
2373 | { |
2374 | if (len == 4 || len == 8) | |
2375 | { | |
2376 | regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf); | |
2377 | regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4); | |
2378 | memcpy (valbuf, buf, len); | |
2379 | return; | |
2380 | } | |
2381 | else | |
2382 | internal_error (__FILE__, __LINE__, "\ | |
2383 | Cannot extract floating-point return value of %d bytes long.", len); | |
2384 | } | |
2385 | ||
2386 | if (len <= 4) | |
2387 | { | |
2388 | regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); | |
2389 | memcpy (valbuf, buf + 4 - len, len); | |
2390 | } | |
2391 | else if (len <= 8) | |
2392 | { | |
2393 | regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); | |
2394 | regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4); | |
2395 | memcpy (valbuf, buf + 8 - len, len); | |
2396 | } | |
c906108c | 2397 | else |
44b7b84e MK |
2398 | internal_error (__FILE__, __LINE__, |
2399 | "Cannot extract return value of %d bytes long.", len); | |
c906108c SS |
2400 | } |
2401 | ||
44b7b84e MK |
2402 | /* Write into REGBUF a function return value VALBUF of type TYPE. */ |
2403 | ||
2404 | void | |
2405 | sparc32_store_return_value (struct type *type, struct regcache *regcache, | |
2406 | const void *valbuf) | |
2407 | { | |
2408 | int len = TYPE_LENGTH (type); | |
2409 | char buf[8]; | |
2410 | ||
2411 | if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU) | |
2412 | { | |
2413 | const char *buf = valbuf; | |
2414 | ||
2415 | if (len == 4) | |
2416 | { | |
2417 | regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf); | |
2418 | return; | |
2419 | } | |
2420 | else if (len == 8) | |
2421 | { | |
2422 | regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf); | |
2423 | regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4); | |
2424 | return; | |
2425 | } | |
2426 | else | |
2427 | internal_error (__FILE__, __LINE__, "\ | |
2428 | Cannot extract floating-point return value of %d bytes long.", len); | |
2429 | } | |
2430 | ||
2431 | /* Add leading zeros to the value. */ | |
2432 | memset (buf, 0, sizeof buf); | |
2433 | ||
2434 | if (len <= 4) | |
2435 | { | |
2436 | memcpy (buf + 4 - len, valbuf, len); | |
2437 | regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); | |
2438 | } | |
2439 | else if (len <= 8) | |
2440 | { | |
2441 | memcpy (buf + 8 - len, valbuf, len); | |
2442 | regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); | |
2443 | regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf); | |
2444 | } | |
2445 | else | |
2446 | internal_error (__FILE__, __LINE__, | |
2447 | "Cannot extract return value of %d bytes long.", len); | |
2448 | } | |
2449 | ||
2450 | /* Extract from REGCACHE the address in which a function should return | |
2451 | its structure value. */ | |
2452 | ||
2453 | CORE_ADDR | |
2454 | sparc_extract_struct_value_address (struct regcache *regcache) | |
2455 | { | |
2456 | ULONGEST addr; | |
2457 | ||
2458 | regcache_cooked_read_unsigned (regcache, SPARC_O0_REGNUM, &addr); | |
2459 | return addr; | |
2460 | } | |
c906108c | 2461 | |
44b7b84e | 2462 | /* FIXME: kettenis/2003/05/24: Still used for sparc64. */ |
c906108c SS |
2463 | |
2464 | void | |
fba45db2 | 2465 | sparc_store_return_value (struct type *type, char *valbuf) |
c906108c SS |
2466 | { |
2467 | int regno; | |
d9d9c31f | 2468 | char buffer[MAX_REGISTER_SIZE]; |
c906108c SS |
2469 | |
2470 | if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU) | |
2471 | /* Floating-point values are returned in the register pair */ | |
2472 | /* formed by %f0 and %f1 (doubles are, anyway). */ | |
2473 | regno = FP0_REGNUM; | |
2474 | else | |
2475 | /* Other values are returned in register %o0. */ | |
2476 | regno = O0_REGNUM; | |
2477 | ||
2478 | /* Add leading zeros to the value. */ | |
c5aa993b | 2479 | if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (regno)) |
c906108c | 2480 | { |
5af923b0 | 2481 | memset (buffer, 0, REGISTER_RAW_SIZE (regno)); |
c5aa993b | 2482 | memcpy (buffer + REGISTER_RAW_SIZE (regno) - TYPE_LENGTH (type), valbuf, |
c906108c | 2483 | TYPE_LENGTH (type)); |
4caf0990 | 2484 | deprecated_write_register_gen (regno, buffer); |
c906108c SS |
2485 | } |
2486 | else | |
73937e03 AC |
2487 | deprecated_write_register_bytes (REGISTER_BYTE (regno), valbuf, |
2488 | TYPE_LENGTH (type)); | |
c906108c SS |
2489 | } |
2490 | ||
f81824a9 AC |
2491 | #if 0 |
2492 | // OBSOLETE extern void | |
2493 | // OBSOLETE sparclet_store_return_value (struct type *type, char *valbuf) | |
2494 | // OBSOLETE { | |
2495 | // OBSOLETE /* Other values are returned in register %o0. */ | |
2496 | // OBSOLETE deprecated_write_register_bytes (REGISTER_BYTE (O0_REGNUM), valbuf, | |
2497 | // OBSOLETE TYPE_LENGTH (type)); | |
2498 | // OBSOLETE } | |
2499 | #endif | |
5af923b0 MS |
2500 | |
2501 | ||
4eb8c7fc DM |
2502 | #ifndef CALL_DUMMY_CALL_OFFSET |
2503 | #define CALL_DUMMY_CALL_OFFSET \ | |
2504 | (gdbarch_tdep (current_gdbarch)->call_dummy_call_offset) | |
2505 | #endif /* CALL_DUMMY_CALL_OFFSET */ | |
2506 | ||
c906108c SS |
2507 | /* Insert the function address into a call dummy instruction sequence |
2508 | stored at DUMMY. | |
2509 | ||
2510 | For structs and unions, if the function was compiled with Sun cc, | |
2511 | it expects 'unimp' after the call. But gcc doesn't use that | |
b1e29e33 AC |
2512 | (twisted) convention. So leave a nop there for gcc |
2513 | (DEPRECATED_FIX_CALL_DUMMY can assume it is operating on a pristine | |
2514 | CALL_DUMMY, not one that has already been customized for a | |
2515 | different function). */ | |
c906108c SS |
2516 | |
2517 | void | |
fba45db2 KB |
2518 | sparc_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, |
2519 | struct type *value_type, int using_gcc) | |
c906108c SS |
2520 | { |
2521 | int i; | |
2522 | ||
2523 | /* Store the relative adddress of the target function into the | |
2524 | 'call' instruction. */ | |
2525 | store_unsigned_integer (dummy + CALL_DUMMY_CALL_OFFSET, 4, | |
2526 | (0x40000000 | |
2527 | | (((fun - (pc + CALL_DUMMY_CALL_OFFSET)) >> 2) | |
c5aa993b | 2528 | & 0x3fffffff))); |
c906108c | 2529 | |
9e36d949 PS |
2530 | /* If the called function returns an aggregate value, fill in the UNIMP |
2531 | instruction containing the size of the returned aggregate return value, | |
2532 | which follows the call instruction. | |
2533 | For details see the SPARC Architecture Manual Version 8, Appendix D.3. | |
2534 | ||
2535 | Adjust the call_dummy_breakpoint_offset for the bp_call_dummy breakpoint | |
2536 | to the proper address in the call dummy, so that `finish' after a stop | |
2537 | in a call dummy works. | |
04714b91 AC |
2538 | |
2539 | Tweeking current_gdbarch is not an optimal solution, but the call | |
2540 | to sparc_fix_call_dummy is immediately followed by a call to | |
2541 | call_function_by_hand, which is the only function where | |
2542 | dummy_breakpoint_offset is actually used, if it is non-zero. */ | |
9e36d949 PS |
2543 | if (TYPE_CODE (value_type) == TYPE_CODE_STRUCT |
2544 | || TYPE_CODE (value_type) == TYPE_CODE_UNION) | |
2545 | { | |
2546 | store_unsigned_integer (dummy + CALL_DUMMY_CALL_OFFSET + 8, 4, | |
2547 | TYPE_LENGTH (value_type) & 0x1fff); | |
b1e29e33 | 2548 | set_gdbarch_deprecated_call_dummy_breakpoint_offset (current_gdbarch, 0x30); |
9e36d949 PS |
2549 | } |
2550 | else | |
b1e29e33 | 2551 | set_gdbarch_deprecated_call_dummy_breakpoint_offset (current_gdbarch, 0x2c); |
c906108c | 2552 | |
5af923b0 | 2553 | if (!(GDB_TARGET_IS_SPARC64)) |
c906108c | 2554 | { |
5af923b0 MS |
2555 | /* If this is not a simulator target, change the first four |
2556 | instructions of the call dummy to NOPs. Those instructions | |
2557 | include a 'save' instruction and are designed to work around | |
2558 | problems with register window flushing in the simulator. */ | |
2559 | ||
2560 | if (strcmp (target_shortname, "sim") != 0) | |
2561 | { | |
2562 | for (i = 0; i < 4; i++) | |
2563 | store_unsigned_integer (dummy + (i * 4), 4, 0x01000000); | |
2564 | } | |
c906108c | 2565 | } |
c906108c | 2566 | |
f81824a9 AC |
2567 | #if 0 |
2568 | // OBSOLETE /* If this is a bi-endian target, GDB has written the call dummy | |
2569 | // OBSOLETE in little-endian order. We must byte-swap it back to big-endian. */ | |
2570 | // OBSOLETE if (bi_endian) | |
2571 | // OBSOLETE { | |
2572 | // OBSOLETE for (i = 0; i < CALL_DUMMY_LENGTH; i += 4) | |
2573 | // OBSOLETE { | |
2574 | // OBSOLETE char tmp = dummy[i]; | |
2575 | // OBSOLETE dummy[i] = dummy[i + 3]; | |
2576 | // OBSOLETE dummy[i + 3] = tmp; | |
2577 | // OBSOLETE tmp = dummy[i + 1]; | |
2578 | // OBSOLETE dummy[i + 1] = dummy[i + 2]; | |
2579 | // OBSOLETE dummy[i + 2] = tmp; | |
2580 | // OBSOLETE } | |
2581 | // OBSOLETE } | |
2582 | #endif | |
c906108c SS |
2583 | } |
2584 | ||
2585 | ||
f81824a9 AC |
2586 | #if 0 |
2587 | // OBSOLETE /* Set target byte order based on machine type. */ | |
2588 | // OBSOLETE | |
2589 | // OBSOLETE static int | |
2590 | // OBSOLETE sparc_target_architecture_hook (const bfd_arch_info_type *ap) | |
2591 | // OBSOLETE { | |
2592 | // OBSOLETE int i, j; | |
2593 | // OBSOLETE | |
2594 | // OBSOLETE if (ap->mach == bfd_mach_sparc_sparclite_le) | |
2595 | // OBSOLETE { | |
2596 | // OBSOLETE target_byte_order = BFD_ENDIAN_LITTLE; | |
2597 | // OBSOLETE bi_endian = 1; | |
2598 | // OBSOLETE } | |
2599 | // OBSOLETE else | |
2600 | // OBSOLETE bi_endian = 0; | |
2601 | // OBSOLETE return 1; | |
2602 | // OBSOLETE } | |
2603 | #endif | |
c5aa993b | 2604 | |
5af923b0 MS |
2605 | /* |
2606 | * Module "constructor" function. | |
2607 | */ | |
2608 | ||
2609 | static struct gdbarch * sparc_gdbarch_init (struct gdbarch_info info, | |
2610 | struct gdbarch_list *arches); | |
ef3cf062 | 2611 | static void sparc_dump_tdep (struct gdbarch *, struct ui_file *); |
5af923b0 | 2612 | |
c906108c | 2613 | void |
fba45db2 | 2614 | _initialize_sparc_tdep (void) |
c906108c | 2615 | { |
5af923b0 | 2616 | /* Hook us into the gdbarch mechanism. */ |
ef3cf062 | 2617 | gdbarch_register (bfd_arch_sparc, sparc_gdbarch_init, sparc_dump_tdep); |
5af923b0 | 2618 | |
d7a27068 | 2619 | deprecated_tm_print_insn = gdb_print_insn_sparc; |
810ecf9f | 2620 | deprecated_tm_print_insn_info.mach = TM_PRINT_INSN_MACH; /* Selects sparc/sparclite */ |
f81824a9 | 2621 | /* OBSOLETE target_architecture_hook = sparc_target_architecture_hook; */ |
c906108c SS |
2622 | } |
2623 | ||
5af923b0 MS |
2624 | /* Compensate for stack bias. Note that we currently don't handle |
2625 | mixed 32/64 bit code. */ | |
c906108c | 2626 | |
c906108c | 2627 | CORE_ADDR |
5af923b0 | 2628 | sparc64_read_sp (void) |
c906108c SS |
2629 | { |
2630 | CORE_ADDR sp = read_register (SP_REGNUM); | |
2631 | ||
2632 | if (sp & 1) | |
2633 | sp += 2047; | |
2634 | return sp; | |
2635 | } | |
2636 | ||
2637 | CORE_ADDR | |
5af923b0 | 2638 | sparc64_read_fp (void) |
c906108c | 2639 | { |
0ba6dca9 | 2640 | CORE_ADDR fp = read_register (DEPRECATED_FP_REGNUM); |
c906108c SS |
2641 | |
2642 | if (fp & 1) | |
2643 | fp += 2047; | |
2644 | return fp; | |
2645 | } | |
2646 | ||
2647 | void | |
fba45db2 | 2648 | sparc64_write_sp (CORE_ADDR val) |
c906108c SS |
2649 | { |
2650 | CORE_ADDR oldsp = read_register (SP_REGNUM); | |
2651 | if (oldsp & 1) | |
2652 | write_register (SP_REGNUM, val - 2047); | |
2653 | else | |
2654 | write_register (SP_REGNUM, val); | |
2655 | } | |
2656 | ||
5af923b0 MS |
2657 | /* The SPARC 64 ABI passes floating-point arguments in FP0 to FP31, |
2658 | and all other arguments in O0 to O5. They are also copied onto | |
2659 | the stack in the correct places. Apparently (empirically), | |
2660 | structs of less than 16 bytes are passed member-by-member in | |
2661 | separate registers, but I am unable to figure out the algorithm. | |
2662 | Some members go in floating point regs, but I don't know which. | |
2663 | ||
2664 | FIXME: Handle small structs (less than 16 bytes containing floats). | |
2665 | ||
2666 | The counting regimen for using both integer and FP registers | |
2667 | for argument passing is rather odd -- a single counter is used | |
2668 | for both; this means that if the arguments alternate between | |
2669 | int and float, we will waste every other register of both types. */ | |
c906108c SS |
2670 | |
2671 | CORE_ADDR | |
ea7c478f | 2672 | sparc64_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
fba45db2 | 2673 | int struct_return, CORE_ADDR struct_retaddr) |
c906108c | 2674 | { |
5af923b0 | 2675 | int i, j, register_counter = 0; |
c906108c | 2676 | CORE_ADDR tempsp; |
5af923b0 MS |
2677 | struct type *sparc_intreg_type = |
2678 | TYPE_LENGTH (builtin_type_long) == SPARC_INTREG_SIZE ? | |
2679 | builtin_type_long : builtin_type_long_long; | |
c5aa993b | 2680 | |
5af923b0 | 2681 | sp = (sp & ~(((unsigned long) SPARC_INTREG_SIZE) - 1UL)); |
c906108c SS |
2682 | |
2683 | /* Figure out how much space we'll need. */ | |
5af923b0 | 2684 | for (i = nargs - 1; i >= 0; i--) |
c906108c | 2685 | { |
5af923b0 | 2686 | int len = TYPE_LENGTH (check_typedef (VALUE_TYPE (args[i]))); |
ea7c478f | 2687 | struct value *copyarg = args[i]; |
c906108c SS |
2688 | int copylen = len; |
2689 | ||
5af923b0 | 2690 | if (copylen < SPARC_INTREG_SIZE) |
c906108c | 2691 | { |
5af923b0 MS |
2692 | copyarg = value_cast (sparc_intreg_type, copyarg); |
2693 | copylen = SPARC_INTREG_SIZE; | |
c5aa993b | 2694 | } |
c906108c SS |
2695 | sp -= copylen; |
2696 | } | |
2697 | ||
2698 | /* Round down. */ | |
2699 | sp = sp & ~7; | |
2700 | tempsp = sp; | |
2701 | ||
5af923b0 MS |
2702 | /* if STRUCT_RETURN, then first argument is the struct return location. */ |
2703 | if (struct_return) | |
2704 | write_register (O0_REGNUM + register_counter++, struct_retaddr); | |
2705 | ||
2706 | /* Now write the arguments onto the stack, while writing FP | |
2707 | arguments into the FP registers, and other arguments into the | |
2708 | first six 'O' registers. */ | |
2709 | ||
2710 | for (i = 0; i < nargs; i++) | |
c906108c | 2711 | { |
5af923b0 | 2712 | int len = TYPE_LENGTH (check_typedef (VALUE_TYPE (args[i]))); |
ea7c478f | 2713 | struct value *copyarg = args[i]; |
5af923b0 | 2714 | enum type_code typecode = TYPE_CODE (VALUE_TYPE (args[i])); |
c906108c SS |
2715 | int copylen = len; |
2716 | ||
5af923b0 MS |
2717 | if (typecode == TYPE_CODE_INT || |
2718 | typecode == TYPE_CODE_BOOL || | |
2719 | typecode == TYPE_CODE_CHAR || | |
2720 | typecode == TYPE_CODE_RANGE || | |
2721 | typecode == TYPE_CODE_ENUM) | |
2722 | if (len < SPARC_INTREG_SIZE) | |
2723 | { | |
2724 | /* Small ints will all take up the size of one intreg on | |
2725 | the stack. */ | |
2726 | copyarg = value_cast (sparc_intreg_type, copyarg); | |
2727 | copylen = SPARC_INTREG_SIZE; | |
2728 | } | |
2729 | ||
c906108c SS |
2730 | write_memory (tempsp, VALUE_CONTENTS (copyarg), copylen); |
2731 | tempsp += copylen; | |
5af923b0 MS |
2732 | |
2733 | /* Corner case: Structs consisting of a single float member are floats. | |
2734 | * FIXME! I don't know about structs containing multiple floats! | |
2735 | * Structs containing mixed floats and ints are even more weird. | |
2736 | */ | |
2737 | ||
2738 | ||
2739 | ||
2740 | /* Separate float args from all other args. */ | |
2741 | if (typecode == TYPE_CODE_FLT && SPARC_HAS_FPU) | |
c906108c | 2742 | { |
5af923b0 MS |
2743 | if (register_counter < 16) |
2744 | { | |
2745 | /* This arg gets copied into a FP register. */ | |
2746 | int fpreg; | |
2747 | ||
2748 | switch (len) { | |
2749 | case 4: /* Single-precision (float) */ | |
2750 | fpreg = FP0_REGNUM + 2 * register_counter + 1; | |
2751 | register_counter += 1; | |
2752 | break; | |
2753 | case 8: /* Double-precision (double) */ | |
2754 | fpreg = FP0_REGNUM + 2 * register_counter; | |
2755 | register_counter += 1; | |
2756 | break; | |
2757 | case 16: /* Quad-precision (long double) */ | |
2758 | fpreg = FP0_REGNUM + 2 * register_counter; | |
2759 | register_counter += 2; | |
2760 | break; | |
93d56215 AC |
2761 | default: |
2762 | internal_error (__FILE__, __LINE__, "bad switch"); | |
5af923b0 | 2763 | } |
73937e03 AC |
2764 | deprecated_write_register_bytes (REGISTER_BYTE (fpreg), |
2765 | VALUE_CONTENTS (args[i]), | |
2766 | len); | |
5af923b0 | 2767 | } |
c906108c | 2768 | } |
5af923b0 MS |
2769 | else /* all other args go into the first six 'o' registers */ |
2770 | { | |
2771 | for (j = 0; | |
2772 | j < len && register_counter < 6; | |
2773 | j += SPARC_INTREG_SIZE) | |
2774 | { | |
2775 | int oreg = O0_REGNUM + register_counter; | |
2776 | ||
4caf0990 | 2777 | deprecated_write_register_gen (oreg, VALUE_CONTENTS (copyarg) + j); |
5af923b0 MS |
2778 | register_counter += 1; |
2779 | } | |
2780 | } | |
c906108c SS |
2781 | } |
2782 | return sp; | |
2783 | } | |
2784 | ||
2785 | /* Values <= 32 bytes are returned in o0-o3 (floating-point values are | |
2786 | returned in f0-f3). */ | |
5af923b0 | 2787 | |
c906108c | 2788 | void |
fba45db2 KB |
2789 | sp64_extract_return_value (struct type *type, char *regbuf, char *valbuf, |
2790 | int bitoffset) | |
c906108c SS |
2791 | { |
2792 | int typelen = TYPE_LENGTH (type); | |
2793 | int regsize = REGISTER_RAW_SIZE (O0_REGNUM); | |
2794 | ||
2795 | if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU) | |
2796 | { | |
c5aa993b | 2797 | memcpy (valbuf, ®buf[REGISTER_BYTE (FP0_REGNUM)], typelen); |
c906108c SS |
2798 | return; |
2799 | } | |
2800 | ||
2801 | if (TYPE_CODE (type) != TYPE_CODE_STRUCT | |
2802 | || (TYPE_LENGTH (type) > 32)) | |
2803 | { | |
2804 | memcpy (valbuf, | |
c5aa993b | 2805 | ®buf[O0_REGNUM * regsize + |
c906108c SS |
2806 | (typelen >= regsize ? 0 : regsize - typelen)], |
2807 | typelen); | |
2808 | return; | |
2809 | } | |
2810 | else | |
2811 | { | |
2812 | char *o0 = ®buf[O0_REGNUM * regsize]; | |
2813 | char *f0 = ®buf[FP0_REGNUM * regsize]; | |
2814 | int x; | |
2815 | ||
2816 | for (x = 0; x < TYPE_NFIELDS (type); x++) | |
2817 | { | |
c5aa993b | 2818 | struct field *f = &TYPE_FIELDS (type)[x]; |
c906108c SS |
2819 | /* FIXME: We may need to handle static fields here. */ |
2820 | int whichreg = (f->loc.bitpos + bitoffset) / 32; | |
2821 | int remainder = ((f->loc.bitpos + bitoffset) % 32) / 8; | |
2822 | int where = (f->loc.bitpos + bitoffset) / 8; | |
2823 | int size = TYPE_LENGTH (f->type); | |
2824 | int typecode = TYPE_CODE (f->type); | |
2825 | ||
2826 | if (typecode == TYPE_CODE_STRUCT) | |
2827 | { | |
5af923b0 MS |
2828 | sp64_extract_return_value (f->type, |
2829 | regbuf, | |
2830 | valbuf, | |
2831 | bitoffset + f->loc.bitpos); | |
c906108c | 2832 | } |
5af923b0 | 2833 | else if (typecode == TYPE_CODE_FLT && SPARC_HAS_FPU) |
c906108c SS |
2834 | { |
2835 | memcpy (valbuf + where, &f0[whichreg * 4] + remainder, size); | |
2836 | } | |
2837 | else | |
2838 | { | |
2839 | memcpy (valbuf + where, &o0[whichreg * 4] + remainder, size); | |
2840 | } | |
2841 | } | |
2842 | } | |
2843 | } | |
2acceee2 | 2844 | |
5af923b0 MS |
2845 | extern void |
2846 | sparc64_extract_return_value (struct type *type, char *regbuf, char *valbuf) | |
2847 | { | |
2848 | sp64_extract_return_value (type, regbuf, valbuf, 0); | |
2849 | } | |
2850 | ||
f81824a9 AC |
2851 | #if 0 |
2852 | // OBSOLETE extern void | |
2853 | // OBSOLETE sparclet_extract_return_value (struct type *type, | |
2854 | // OBSOLETE char *regbuf, | |
2855 | // OBSOLETE char *valbuf) | |
2856 | // OBSOLETE { | |
2857 | // OBSOLETE regbuf += REGISTER_RAW_SIZE (O0_REGNUM) * 8; | |
2858 | // OBSOLETE if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (O0_REGNUM)) | |
2859 | // OBSOLETE regbuf += REGISTER_RAW_SIZE (O0_REGNUM) - TYPE_LENGTH (type); | |
2860 | // OBSOLETE | |
2861 | // OBSOLETE memcpy ((void *) valbuf, regbuf, TYPE_LENGTH (type)); | |
2862 | // OBSOLETE } | |
2863 | #endif | |
5af923b0 MS |
2864 | |
2865 | extern CORE_ADDR | |
2866 | sparc32_stack_align (CORE_ADDR addr) | |
2867 | { | |
2868 | return ((addr + 7) & -8); | |
2869 | } | |
2870 | ||
2871 | extern CORE_ADDR | |
2872 | sparc64_stack_align (CORE_ADDR addr) | |
2873 | { | |
2874 | return ((addr + 15) & -16); | |
2875 | } | |
2876 | ||
2877 | extern void | |
2878 | sparc_print_extra_frame_info (struct frame_info *fi) | |
2879 | { | |
da50a4b7 | 2880 | if (fi && get_frame_extra_info (fi) && get_frame_extra_info (fi)->flat) |
5af923b0 | 2881 | printf_filtered (" flat, pc saved at 0x%s, fp saved at 0x%s\n", |
da50a4b7 AC |
2882 | paddr_nz (get_frame_extra_info (fi)->pc_addr), |
2883 | paddr_nz (get_frame_extra_info (fi)->fp_addr)); | |
5af923b0 MS |
2884 | } |
2885 | ||
2886 | /* MULTI_ARCH support */ | |
2887 | ||
fa88f677 | 2888 | static const char * |
5af923b0 MS |
2889 | sparc32_register_name (int regno) |
2890 | { | |
2891 | static char *register_names[] = | |
2892 | { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", | |
2893 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", | |
2894 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", | |
2895 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", | |
2896 | ||
2897 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
2898 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
2899 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
2900 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
2901 | ||
2902 | "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr" | |
2903 | }; | |
2904 | ||
2905 | if (regno < 0 || | |
2906 | regno >= (sizeof (register_names) / sizeof (register_names[0]))) | |
2907 | return NULL; | |
2908 | else | |
2909 | return register_names[regno]; | |
2910 | } | |
2911 | ||
fa88f677 | 2912 | static const char * |
5af923b0 MS |
2913 | sparc64_register_name (int regno) |
2914 | { | |
2915 | static char *register_names[] = | |
2916 | { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", | |
2917 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", | |
2918 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", | |
2919 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", | |
2920 | ||
2921 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
2922 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
2923 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
2924 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
2925 | "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46", | |
2926 | "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62", | |
2927 | ||
2928 | "pc", "npc", "ccr", "fsr", "fprs", "y", "asi", "ver", | |
2929 | "tick", "pil", "pstate", "tstate", "tba", "tl", "tt", "tpc", | |
2930 | "tnpc", "wstate", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", | |
2931 | "asr16", "asr17", "asr18", "asr19", "asr20", "asr21", "asr22", "asr23", | |
2932 | "asr24", "asr25", "asr26", "asr27", "asr28", "asr29", "asr30", "asr31", | |
2933 | /* These are here at the end to simplify removing them if we have to. */ | |
2934 | "icc", "xcc", "fcc0", "fcc1", "fcc2", "fcc3" | |
2935 | }; | |
2936 | ||
2937 | if (regno < 0 || | |
2938 | regno >= (sizeof (register_names) / sizeof (register_names[0]))) | |
2939 | return NULL; | |
2940 | else | |
2941 | return register_names[regno]; | |
2942 | } | |
2943 | ||
5af923b0 | 2944 | #if 0 |
f81824a9 AC |
2945 | // OBSOLETE static const char * |
2946 | // OBSOLETE sparclite_register_name (int regno) | |
2947 | // OBSOLETE { | |
2948 | // OBSOLETE static char *register_names[] = | |
2949 | // OBSOLETE { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", | |
2950 | // OBSOLETE "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", | |
2951 | // OBSOLETE "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", | |
2952 | // OBSOLETE "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", | |
2953 | // OBSOLETE | |
2954 | // OBSOLETE "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
2955 | // OBSOLETE "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
2956 | // OBSOLETE "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
2957 | // OBSOLETE "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
2958 | // OBSOLETE | |
2959 | // OBSOLETE "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr", | |
2960 | // OBSOLETE "dia1", "dia2", "dda1", "dda2", "ddv1", "ddv2", "dcr", "dsr" | |
2961 | // OBSOLETE }; | |
2962 | // OBSOLETE | |
2963 | // OBSOLETE if (regno < 0 || | |
2964 | // OBSOLETE regno >= (sizeof (register_names) / sizeof (register_names[0]))) | |
2965 | // OBSOLETE return NULL; | |
2966 | // OBSOLETE else | |
2967 | // OBSOLETE return register_names[regno]; | |
2968 | // OBSOLETE } | |
2969 | #endif | |
5af923b0 | 2970 | |
f81824a9 AC |
2971 | #if 0 |
2972 | // OBSOLETE static const char * | |
2973 | // OBSOLETE sparclet_register_name (int regno) | |
2974 | // OBSOLETE { | |
2975 | // OBSOLETE static char *register_names[] = | |
2976 | // OBSOLETE { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", | |
2977 | // OBSOLETE "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", | |
2978 | // OBSOLETE "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", | |
2979 | // OBSOLETE "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", | |
2980 | // OBSOLETE | |
2981 | // OBSOLETE "", "", "", "", "", "", "", "", /* no floating point registers */ | |
2982 | // OBSOLETE "", "", "", "", "", "", "", "", | |
2983 | // OBSOLETE "", "", "", "", "", "", "", "", | |
2984 | // OBSOLETE "", "", "", "", "", "", "", "", | |
2985 | // OBSOLETE | |
2986 | // OBSOLETE "y", "psr", "wim", "tbr", "pc", "npc", "", "", /* no FPSR or CPSR */ | |
2987 | // OBSOLETE "ccsr", "ccpr", "cccrcr", "ccor", "ccobr", "ccibr", "ccir", "", | |
2988 | // OBSOLETE | |
2989 | // OBSOLETE /* ASR15 ASR19 (don't display them) */ | |
2990 | // OBSOLETE "asr1", "", "asr17", "asr18", "", "asr20", "asr21", "asr22" | |
2991 | // OBSOLETE /* None of the rest get displayed */ | |
2992 | // OBSOLETE #if 0 | |
2993 | // OBSOLETE "awr0", "awr1", "awr2", "awr3", "awr4", "awr5", "awr6", "awr7", | |
2994 | // OBSOLETE "awr8", "awr9", "awr10", "awr11", "awr12", "awr13", "awr14", "awr15", | |
2995 | // OBSOLETE "awr16", "awr17", "awr18", "awr19", "awr20", "awr21", "awr22", "awr23", | |
2996 | // OBSOLETE "awr24", "awr25", "awr26", "awr27", "awr28", "awr29", "awr30", "awr31", | |
2997 | // OBSOLETE "apsr" | |
2998 | // OBSOLETE #endif /* 0 */ | |
2999 | // OBSOLETE }; | |
3000 | // OBSOLETE | |
3001 | // OBSOLETE if (regno < 0 || | |
3002 | // OBSOLETE regno >= (sizeof (register_names) / sizeof (register_names[0]))) | |
3003 | // OBSOLETE return NULL; | |
3004 | // OBSOLETE else | |
3005 | // OBSOLETE return register_names[regno]; | |
3006 | // OBSOLETE } | |
3007 | #endif | |
5af923b0 MS |
3008 | |
3009 | CORE_ADDR | |
3010 | sparc_push_return_address (CORE_ADDR pc_unused, CORE_ADDR sp) | |
3011 | { | |
3012 | if (CALL_DUMMY_LOCATION == AT_ENTRY_POINT) | |
3013 | { | |
3014 | /* The return PC of the dummy_frame is the former 'current' PC | |
3015 | (where we were before we made the target function call). | |
3016 | This is saved in %i7 by push_dummy_frame. | |
3017 | ||
3018 | We will save the 'call dummy location' (ie. the address | |
3019 | to which the target function will return) in %o7. | |
3020 | This address will actually be the program's entry point. | |
3021 | There will be a special call_dummy breakpoint there. */ | |
3022 | ||
3023 | write_register (O7_REGNUM, | |
3024 | CALL_DUMMY_ADDRESS () - 8); | |
3025 | } | |
3026 | ||
3027 | return sp; | |
3028 | } | |
3029 | ||
3030 | /* Should call_function allocate stack space for a struct return? */ | |
3031 | ||
3032 | static int | |
3033 | sparc64_use_struct_convention (int gcc_p, struct type *type) | |
3034 | { | |
3035 | return (TYPE_LENGTH (type) > 32); | |
3036 | } | |
3037 | ||
3038 | /* Store the address of the place in which to copy the structure the | |
3039 | subroutine will return. This is called from call_function_by_hand. | |
3040 | The ultimate mystery is, tho, what is the value "16"? | |
3041 | ||
3042 | MVS: That's the offset from where the sp is now, to where the | |
3043 | subroutine is gonna expect to find the struct return address. */ | |
3044 | ||
3045 | static void | |
3046 | sparc32_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) | |
3047 | { | |
3048 | char *val; | |
3049 | CORE_ADDR o7; | |
3050 | ||
3051 | val = alloca (SPARC_INTREG_SIZE); | |
3052 | store_unsigned_integer (val, SPARC_INTREG_SIZE, addr); | |
3053 | write_memory (sp + (16 * SPARC_INTREG_SIZE), val, SPARC_INTREG_SIZE); | |
3054 | ||
3055 | if (CALL_DUMMY_LOCATION == AT_ENTRY_POINT) | |
3056 | { | |
3057 | /* Now adjust the value of the link register, which was previously | |
3058 | stored by push_return_address. Functions that return structs are | |
3059 | peculiar in that they return to link register + 12, rather than | |
3060 | link register + 8. */ | |
3061 | ||
3062 | o7 = read_register (O7_REGNUM); | |
3063 | write_register (O7_REGNUM, o7 - 4); | |
3064 | } | |
3065 | } | |
3066 | ||
3067 | static void | |
3068 | sparc64_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) | |
3069 | { | |
3070 | /* FIXME: V9 uses %o0 for this. */ | |
3071 | /* FIXME MVS: Only for small enough structs!!! */ | |
2acceee2 | 3072 | |
5af923b0 MS |
3073 | target_write_memory (sp + (16 * SPARC_INTREG_SIZE), |
3074 | (char *) &addr, SPARC_INTREG_SIZE); | |
3075 | #if 0 | |
3076 | if (CALL_DUMMY_LOCATION == AT_ENTRY_POINT) | |
3077 | { | |
3078 | /* Now adjust the value of the link register, which was previously | |
3079 | stored by push_return_address. Functions that return structs are | |
3080 | peculiar in that they return to link register + 12, rather than | |
3081 | link register + 8. */ | |
3082 | ||
3083 | write_register (O7_REGNUM, read_register (O7_REGNUM) - 4); | |
3084 | } | |
c906108c | 3085 | #endif |
5af923b0 MS |
3086 | } |
3087 | ||
3088 | /* Default target data type for register REGNO. */ | |
3089 | ||
3090 | static struct type * | |
3091 | sparc32_register_virtual_type (int regno) | |
3092 | { | |
3093 | if (regno == PC_REGNUM || | |
0ba6dca9 | 3094 | regno == DEPRECATED_FP_REGNUM || |
5af923b0 MS |
3095 | regno == SP_REGNUM) |
3096 | return builtin_type_unsigned_int; | |
3097 | if (regno < 32) | |
3098 | return builtin_type_int; | |
3099 | if (regno < 64) | |
3100 | return builtin_type_float; | |
3101 | return builtin_type_int; | |
3102 | } | |
3103 | ||
3104 | static struct type * | |
3105 | sparc64_register_virtual_type (int regno) | |
3106 | { | |
3107 | if (regno == PC_REGNUM || | |
0ba6dca9 | 3108 | regno == DEPRECATED_FP_REGNUM || |
5af923b0 MS |
3109 | regno == SP_REGNUM) |
3110 | return builtin_type_unsigned_long_long; | |
3111 | if (regno < 32) | |
3112 | return builtin_type_long_long; | |
3113 | if (regno < 64) | |
3114 | return builtin_type_float; | |
3115 | if (regno < 80) | |
3116 | return builtin_type_double; | |
3117 | return builtin_type_long_long; | |
3118 | } | |
3119 | ||
3120 | /* Number of bytes of storage in the actual machine representation for | |
3121 | register REGNO. */ | |
3122 | ||
3123 | static int | |
3124 | sparc32_register_size (int regno) | |
3125 | { | |
3126 | return 4; | |
3127 | } | |
3128 | ||
3129 | static int | |
3130 | sparc64_register_size (int regno) | |
3131 | { | |
3132 | return (regno < 32 ? 8 : regno < 64 ? 4 : 8); | |
3133 | } | |
3134 | ||
3135 | /* Index within the `registers' buffer of the first byte of the space | |
3136 | for register REGNO. */ | |
3137 | ||
3138 | static int | |
3139 | sparc32_register_byte (int regno) | |
3140 | { | |
3141 | return (regno * 4); | |
3142 | } | |
3143 | ||
3144 | static int | |
3145 | sparc64_register_byte (int regno) | |
3146 | { | |
3147 | if (regno < 32) | |
3148 | return regno * 8; | |
3149 | else if (regno < 64) | |
3150 | return 32 * 8 + (regno - 32) * 4; | |
3151 | else if (regno < 80) | |
3152 | return 32 * 8 + 32 * 4 + (regno - 64) * 8; | |
3153 | else | |
3154 | return 64 * 8 + (regno - 80) * 8; | |
3155 | } | |
3156 | ||
5af923b0 MS |
3157 | /* Immediately after a function call, return the saved pc. |
3158 | Can't go through the frames for this because on some machines | |
3159 | the new frame is not set up until the new function executes | |
3160 | some instructions. */ | |
3161 | ||
3162 | static CORE_ADDR | |
3163 | sparc_saved_pc_after_call (struct frame_info *fi) | |
3164 | { | |
3165 | return sparc_pc_adjust (read_register (RP_REGNUM)); | |
3166 | } | |
3167 | ||
3168 | /* Convert registers between 'raw' and 'virtual' formats. | |
3169 | They are the same on sparc, so there's nothing to do. */ | |
3170 | ||
3171 | static void | |
3172 | sparc_convert_to_virtual (int regnum, struct type *type, char *from, char *to) | |
3173 | { /* do nothing (should never be called) */ | |
3174 | } | |
3175 | ||
3176 | static void | |
3177 | sparc_convert_to_raw (struct type *type, int regnum, char *from, char *to) | |
3178 | { /* do nothing (should never be called) */ | |
3179 | } | |
3180 | ||
3181 | /* Init saved regs: nothing to do, just a place-holder function. */ | |
3182 | ||
3183 | static void | |
3184 | sparc_frame_init_saved_regs (struct frame_info *fi_ignored) | |
3185 | { /* no-op */ | |
3186 | } | |
3187 | ||
5af923b0 MS |
3188 | /* gdbarch fix call dummy: |
3189 | All this function does is rearrange the arguments before calling | |
3190 | sparc_fix_call_dummy (which does the real work). */ | |
3191 | ||
3192 | static void | |
3193 | sparc_gdbarch_fix_call_dummy (char *dummy, | |
3194 | CORE_ADDR pc, | |
3195 | CORE_ADDR fun, | |
3196 | int nargs, | |
3197 | struct value **args, | |
3198 | struct type *type, | |
3199 | int gcc_p) | |
3200 | { | |
3201 | if (CALL_DUMMY_LOCATION == ON_STACK) | |
3202 | sparc_fix_call_dummy (dummy, pc, fun, type, gcc_p); | |
3203 | } | |
3204 | ||
5af923b0 MS |
3205 | /* CALL_DUMMY_ADDRESS: fetch the breakpoint address for a call dummy. */ |
3206 | ||
3207 | static CORE_ADDR | |
3208 | sparc_call_dummy_address (void) | |
3209 | { | |
b1e29e33 | 3210 | return (DEPRECATED_CALL_DUMMY_START_OFFSET) + DEPRECATED_CALL_DUMMY_BREAKPOINT_OFFSET; |
5af923b0 MS |
3211 | } |
3212 | ||
3213 | /* Supply the Y register number to those that need it. */ | |
3214 | ||
3215 | int | |
3216 | sparc_y_regnum (void) | |
3217 | { | |
3218 | return gdbarch_tdep (current_gdbarch)->y_regnum; | |
3219 | } | |
3220 | ||
3221 | int | |
3222 | sparc_reg_struct_has_addr (int gcc_p, struct type *type) | |
3223 | { | |
3224 | if (GDB_TARGET_IS_SPARC64) | |
3225 | return (TYPE_LENGTH (type) > 32); | |
3226 | else | |
3227 | return (gcc_p != 1); | |
3228 | } | |
3229 | ||
3230 | int | |
3231 | sparc_intreg_size (void) | |
3232 | { | |
3233 | return SPARC_INTREG_SIZE; | |
3234 | } | |
3235 | ||
3236 | static int | |
3237 | sparc_return_value_on_stack (struct type *type) | |
3238 | { | |
3239 | if (TYPE_CODE (type) == TYPE_CODE_FLT && | |
3240 | TYPE_LENGTH (type) > 8) | |
3241 | return 1; | |
3242 | else | |
3243 | return 0; | |
3244 | } | |
3245 | ||
3246 | /* | |
3247 | * Gdbarch "constructor" function. | |
3248 | */ | |
3249 | ||
3250 | #define SPARC32_CALL_DUMMY_ON_STACK | |
3251 | ||
3252 | #define SPARC_SP_REGNUM 14 | |
3253 | #define SPARC_FP_REGNUM 30 | |
3254 | #define SPARC_FP0_REGNUM 32 | |
3255 | #define SPARC32_NPC_REGNUM 69 | |
3256 | #define SPARC32_PC_REGNUM 68 | |
3257 | #define SPARC32_Y_REGNUM 64 | |
3258 | #define SPARC64_PC_REGNUM 80 | |
3259 | #define SPARC64_NPC_REGNUM 81 | |
3260 | #define SPARC64_Y_REGNUM 85 | |
3261 | ||
3262 | static struct gdbarch * | |
3263 | sparc_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
3264 | { | |
3265 | struct gdbarch *gdbarch; | |
3266 | struct gdbarch_tdep *tdep; | |
3267 | ||
3268 | static LONGEST call_dummy_32[] = | |
3269 | { 0xbc100001, 0x9de38000, 0xbc100002, 0xbe100003, | |
3270 | 0xda03a058, 0xd803a054, 0xd603a050, 0xd403a04c, | |
3271 | 0xd203a048, 0x40000000, 0xd003a044, 0x01000000, | |
3272 | 0x91d02001, 0x01000000 | |
3273 | }; | |
3274 | static LONGEST call_dummy_64[] = | |
3275 | { 0x9de3bec0fd3fa7f7LL, 0xf93fa7eff53fa7e7LL, | |
3276 | 0xf13fa7dfed3fa7d7LL, 0xe93fa7cfe53fa7c7LL, | |
3277 | 0xe13fa7bfdd3fa7b7LL, 0xd93fa7afd53fa7a7LL, | |
3278 | 0xd13fa79fcd3fa797LL, 0xc93fa78fc53fa787LL, | |
3279 | 0xc13fa77fcc3fa777LL, 0xc83fa76fc43fa767LL, | |
3280 | 0xc03fa75ffc3fa757LL, 0xf83fa74ff43fa747LL, | |
3281 | 0xf03fa73f01000000LL, 0x0100000001000000LL, | |
3282 | 0x0100000091580000LL, 0xd027a72b93500000LL, | |
3283 | 0xd027a72791480000LL, 0xd027a72391400000LL, | |
3284 | 0xd027a71fda5ba8a7LL, 0xd85ba89fd65ba897LL, | |
3285 | 0xd45ba88fd25ba887LL, 0x9fc02000d05ba87fLL, | |
3286 | 0x0100000091d02001LL, 0x0100000001000000LL | |
3287 | }; | |
3288 | static LONGEST call_dummy_nil[] = {0}; | |
3289 | ||
ef3cf062 JT |
3290 | /* Try to determine the OS ABI of the object we are loading. */ |
3291 | ||
4be87837 DJ |
3292 | if (info.abfd != NULL |
3293 | && info.osabi == GDB_OSABI_UNKNOWN) | |
ef3cf062 | 3294 | { |
4be87837 DJ |
3295 | /* If it's an ELF file, assume it's Solaris. */ |
3296 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
3297 | info.osabi = GDB_OSABI_SOLARIS; | |
ef3cf062 JT |
3298 | } |
3299 | ||
5af923b0 | 3300 | /* First see if there is already a gdbarch that can satisfy the request. */ |
4be87837 DJ |
3301 | arches = gdbarch_list_lookup_by_info (arches, &info); |
3302 | if (arches != NULL) | |
3303 | return arches->gdbarch; | |
5af923b0 MS |
3304 | |
3305 | /* None found: is the request for a sparc architecture? */ | |
aca21d9a | 3306 | if (info.bfd_arch_info->arch != bfd_arch_sparc) |
5af923b0 MS |
3307 | return NULL; /* No; then it's not for us. */ |
3308 | ||
3309 | /* Yes: create a new gdbarch for the specified machine type. */ | |
3310 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); | |
3311 | gdbarch = gdbarch_alloc (&info, tdep); | |
3312 | ||
3313 | /* First set settings that are common for all sparc architectures. */ | |
3314 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); | |
aaab4dba | 3315 | set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc); |
5af923b0 MS |
3316 | set_gdbarch_decr_pc_after_break (gdbarch, 0); |
3317 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
44b7b84e MK |
3318 | set_gdbarch_extract_struct_value_address (gdbarch, |
3319 | sparc_extract_struct_value_address); | |
b1e29e33 | 3320 | set_gdbarch_deprecated_fix_call_dummy (gdbarch, sparc_gdbarch_fix_call_dummy); |
5af923b0 | 3321 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
0ba6dca9 | 3322 | set_gdbarch_deprecated_fp_regnum (gdbarch, SPARC_FP_REGNUM); |
5af923b0 | 3323 | set_gdbarch_fp0_regnum (gdbarch, SPARC_FP0_REGNUM); |
618ce49f | 3324 | set_gdbarch_deprecated_frame_chain (gdbarch, sparc_frame_chain); |
f30ee0bc | 3325 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sparc_frame_init_saved_regs); |
5af923b0 | 3326 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); |
8bedc050 | 3327 | set_gdbarch_deprecated_frame_saved_pc (gdbarch, sparc_frame_saved_pc); |
5af923b0 MS |
3328 | set_gdbarch_frameless_function_invocation (gdbarch, |
3329 | frameless_look_for_prologue); | |
129c1cd6 | 3330 | set_gdbarch_deprecated_get_saved_register (gdbarch, sparc_get_saved_register); |
e9582e71 | 3331 | set_gdbarch_deprecated_init_extra_frame_info (gdbarch, sparc_init_extra_frame_info); |
5af923b0 MS |
3332 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
3333 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
3334 | set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT); | |
3335 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
a0ed5532 AC |
3336 | set_gdbarch_deprecated_max_register_raw_size (gdbarch, 8); |
3337 | set_gdbarch_deprecated_max_register_virtual_size (gdbarch, 8); | |
749b82f6 | 3338 | set_gdbarch_deprecated_pop_frame (gdbarch, sparc_pop_frame); |
28f617b3 | 3339 | set_gdbarch_deprecated_push_return_address (gdbarch, sparc_push_return_address); |
f3824013 | 3340 | set_gdbarch_deprecated_push_dummy_frame (gdbarch, sparc_push_dummy_frame); |
5af923b0 MS |
3341 | set_gdbarch_read_pc (gdbarch, generic_target_read_pc); |
3342 | set_gdbarch_register_convert_to_raw (gdbarch, sparc_convert_to_raw); | |
3343 | set_gdbarch_register_convert_to_virtual (gdbarch, | |
3344 | sparc_convert_to_virtual); | |
3345 | set_gdbarch_register_convertible (gdbarch, | |
3346 | generic_register_convertible_not); | |
3347 | set_gdbarch_reg_struct_has_addr (gdbarch, sparc_reg_struct_has_addr); | |
3348 | set_gdbarch_return_value_on_stack (gdbarch, sparc_return_value_on_stack); | |
6913c89a | 3349 | set_gdbarch_deprecated_saved_pc_after_call (gdbarch, sparc_saved_pc_after_call); |
9319a2fe | 3350 | set_gdbarch_prologue_frameless_p (gdbarch, sparc_prologue_frameless_p); |
5af923b0 | 3351 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
f510d44e | 3352 | set_gdbarch_skip_prologue (gdbarch, sparc_skip_prologue); |
5af923b0 | 3353 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); |
07555a72 | 3354 | set_gdbarch_deprecated_use_generic_dummy_frames (gdbarch, 0); |
5af923b0 MS |
3355 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
3356 | ||
3357 | /* | |
3358 | * Settings that depend only on 32/64 bit word size | |
3359 | */ | |
3360 | ||
3361 | switch (info.bfd_arch_info->mach) | |
3362 | { | |
3363 | case bfd_mach_sparc: | |
f81824a9 AC |
3364 | #if 0 |
3365 | // OBSOLETE case bfd_mach_sparc_sparclet: | |
3366 | // OBSOLETE case bfd_mach_sparc_sparclite: | |
3367 | #endif | |
5af923b0 MS |
3368 | case bfd_mach_sparc_v8plus: |
3369 | case bfd_mach_sparc_v8plusa: | |
f81824a9 AC |
3370 | #if 0 |
3371 | // OBSOLETE case bfd_mach_sparc_sparclite_le: | |
3372 | #endif | |
5af923b0 MS |
3373 | /* 32-bit machine types: */ |
3374 | ||
3375 | #ifdef SPARC32_CALL_DUMMY_ON_STACK | |
ae45cd16 | 3376 | set_gdbarch_deprecated_pc_in_call_dummy (gdbarch, deprecated_pc_in_call_dummy_on_stack); |
5af923b0 | 3377 | set_gdbarch_call_dummy_address (gdbarch, sparc_call_dummy_address); |
b1e29e33 AC |
3378 | set_gdbarch_deprecated_call_dummy_breakpoint_offset (gdbarch, 0x30); |
3379 | set_gdbarch_deprecated_call_dummy_length (gdbarch, 0x38); | |
7e57f5f4 | 3380 | |
7043d8dc AC |
3381 | /* NOTE: cagney/2003-05-01: Using the just added push_dummy_code |
3382 | architecture method, it is now possible to implement a | |
3383 | generic dummy frames based inferior function call that stores | |
3384 | the breakpoint (and struct info) on the stack. Further, by | |
3385 | treating a SIGSEG at a breakpoint as equivalent to a SIGTRAP | |
3386 | it is even possible to make this work when the stack is | |
3387 | no-execute. | |
3388 | ||
3389 | NOTE: cagney/2002-04-26: Based from info posted by Peter | |
7e57f5f4 AC |
3390 | Schauer around Oct '99. Briefly, due to aspects of the SPARC |
3391 | ABI, it isn't possible to use ON_STACK with a strictly | |
3392 | compliant compiler. | |
3393 | ||
3394 | Peter Schauer writes ... | |
3395 | ||
3396 | No, any call from GDB to a user function returning a | |
3397 | struct/union will fail miserably. Try this: | |
3398 | ||
3399 | *NOINDENT* | |
3400 | struct x | |
3401 | { | |
3402 | int a[4]; | |
3403 | }; | |
3404 | ||
3405 | struct x gx; | |
3406 | ||
3407 | struct x | |
3408 | sret () | |
3409 | { | |
3410 | return gx; | |
3411 | } | |
3412 | ||
3413 | main () | |
3414 | { | |
3415 | int i; | |
3416 | for (i = 0; i < 4; i++) | |
3417 | gx.a[i] = i + 1; | |
3418 | gx = sret (); | |
3419 | } | |
3420 | *INDENT* | |
3421 | ||
3422 | Set a breakpoint at the gx = sret () statement, run to it and | |
3423 | issue a `print sret()'. It will not succed with your | |
3424 | approach, and I doubt that continuing the program will work | |
3425 | as well. | |
3426 | ||
3427 | For details of the ABI see the Sparc Architecture Manual. I | |
3428 | have Version 8 (Prentice Hall ISBN 0-13-825001-4) and the | |
3429 | calling conventions for functions returning aggregate values | |
3430 | are explained in Appendix D.3. */ | |
3431 | ||
5af923b0 | 3432 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
b1e29e33 | 3433 | set_gdbarch_deprecated_call_dummy_words (gdbarch, call_dummy_32); |
5af923b0 | 3434 | #else |
ae45cd16 | 3435 | set_gdbarch_deprecated_pc_in_call_dummy (gdbarch, deprecated_pc_in_call_dummy_at_entry_point); |
b1e29e33 | 3436 | set_gdbarch_deprecated_call_dummy_words (gdbarch, call_dummy_nil); |
5af923b0 | 3437 | #endif |
1bf6d5cc | 3438 | set_gdbarch_deprecated_call_dummy_stack_adjust (gdbarch, 68); |
5af923b0 MS |
3439 | set_gdbarch_frame_args_skip (gdbarch, 68); |
3440 | set_gdbarch_function_start_offset (gdbarch, 0); | |
3441 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
3442 | set_gdbarch_npc_regnum (gdbarch, SPARC32_NPC_REGNUM); | |
3443 | set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); | |
3444 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
b81774d8 | 3445 | set_gdbarch_deprecated_push_arguments (gdbarch, sparc32_push_arguments); |
5af923b0 MS |
3446 | set_gdbarch_read_sp (gdbarch, generic_target_read_sp); |
3447 | ||
3448 | set_gdbarch_register_byte (gdbarch, sparc32_register_byte); | |
3449 | set_gdbarch_register_raw_size (gdbarch, sparc32_register_size); | |
b1e29e33 | 3450 | set_gdbarch_deprecated_register_size (gdbarch, 4); |
5af923b0 MS |
3451 | set_gdbarch_register_virtual_size (gdbarch, sparc32_register_size); |
3452 | set_gdbarch_register_virtual_type (gdbarch, | |
3453 | sparc32_register_virtual_type); | |
3454 | #ifdef SPARC32_CALL_DUMMY_ON_STACK | |
b1e29e33 | 3455 | set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, sizeof (call_dummy_32)); |
5af923b0 | 3456 | #else |
b1e29e33 | 3457 | set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, 0); |
5af923b0 MS |
3458 | #endif |
3459 | set_gdbarch_stack_align (gdbarch, sparc32_stack_align); | |
f933a9c5 | 3460 | set_gdbarch_deprecated_extra_stack_alignment_needed (gdbarch, 1); |
4183d812 | 3461 | set_gdbarch_deprecated_store_struct_return (gdbarch, sparc32_store_struct_return); |
5af923b0 MS |
3462 | set_gdbarch_use_struct_convention (gdbarch, |
3463 | generic_use_struct_convention); | |
6c0e89ed | 3464 | set_gdbarch_deprecated_dummy_write_sp (gdbarch, generic_target_write_sp); |
5af923b0 MS |
3465 | tdep->y_regnum = SPARC32_Y_REGNUM; |
3466 | tdep->fp_max_regnum = SPARC_FP0_REGNUM + 32; | |
3467 | tdep->intreg_size = 4; | |
3468 | tdep->reg_save_offset = 0x60; | |
3469 | tdep->call_dummy_call_offset = 0x24; | |
3470 | break; | |
3471 | ||
3472 | case bfd_mach_sparc_v9: | |
3473 | case bfd_mach_sparc_v9a: | |
3474 | /* 64-bit machine types: */ | |
3475 | default: /* Any new machine type is likely to be 64-bit. */ | |
3476 | ||
3477 | #ifdef SPARC64_CALL_DUMMY_ON_STACK | |
ae45cd16 | 3478 | set_gdbarch_deprecated_pc_in_call_dummy (gdbarch, deprecated_pc_in_call_dummy_on_stack); |
5af923b0 | 3479 | set_gdbarch_call_dummy_address (gdbarch, sparc_call_dummy_address); |
b1e29e33 AC |
3480 | set_gdbarch_deprecated_call_dummy_breakpoint_offset (gdbarch, 8 * 4); |
3481 | set_gdbarch_deprecated_call_dummy_length (gdbarch, 192); | |
5af923b0 | 3482 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
b1e29e33 AC |
3483 | set_gdbarch_deprecated_call_dummy_start_offset (gdbarch, 148); |
3484 | set_gdbarch_deprecated_call_dummy_words (gdbarch, call_dummy_64); | |
5af923b0 | 3485 | #else |
ae45cd16 | 3486 | set_gdbarch_deprecated_pc_in_call_dummy (gdbarch, deprecated_pc_in_call_dummy_at_entry_point); |
b1e29e33 | 3487 | set_gdbarch_deprecated_call_dummy_words (gdbarch, call_dummy_nil); |
5af923b0 | 3488 | #endif |
1bf6d5cc | 3489 | set_gdbarch_deprecated_call_dummy_stack_adjust (gdbarch, 128); |
5af923b0 MS |
3490 | set_gdbarch_frame_args_skip (gdbarch, 136); |
3491 | set_gdbarch_function_start_offset (gdbarch, 0); | |
3492 | set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
3493 | set_gdbarch_npc_regnum (gdbarch, SPARC64_NPC_REGNUM); | |
3494 | set_gdbarch_pc_regnum (gdbarch, SPARC64_PC_REGNUM); | |
3495 | set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
b81774d8 | 3496 | set_gdbarch_deprecated_push_arguments (gdbarch, sparc64_push_arguments); |
5af923b0 | 3497 | /* NOTE different for at_entry */ |
0ba6dca9 | 3498 | set_gdbarch_deprecated_target_read_fp (gdbarch, sparc64_read_fp); |
5af923b0 MS |
3499 | set_gdbarch_read_sp (gdbarch, sparc64_read_sp); |
3500 | /* Some of the registers aren't 64 bits, but it's a lot simpler just | |
3501 | to assume they all are (since most of them are). */ | |
3502 | set_gdbarch_register_byte (gdbarch, sparc64_register_byte); | |
3503 | set_gdbarch_register_raw_size (gdbarch, sparc64_register_size); | |
b1e29e33 | 3504 | set_gdbarch_deprecated_register_size (gdbarch, 8); |
5af923b0 MS |
3505 | set_gdbarch_register_virtual_size (gdbarch, sparc64_register_size); |
3506 | set_gdbarch_register_virtual_type (gdbarch, | |
3507 | sparc64_register_virtual_type); | |
3508 | #ifdef SPARC64_CALL_DUMMY_ON_STACK | |
b1e29e33 | 3509 | set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, sizeof (call_dummy_64)); |
5af923b0 | 3510 | #else |
b1e29e33 | 3511 | set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, 0); |
5af923b0 MS |
3512 | #endif |
3513 | set_gdbarch_stack_align (gdbarch, sparc64_stack_align); | |
f933a9c5 | 3514 | set_gdbarch_deprecated_extra_stack_alignment_needed (gdbarch, 1); |
4183d812 | 3515 | set_gdbarch_deprecated_store_struct_return (gdbarch, sparc64_store_struct_return); |
5af923b0 MS |
3516 | set_gdbarch_use_struct_convention (gdbarch, |
3517 | sparc64_use_struct_convention); | |
6c0e89ed | 3518 | set_gdbarch_deprecated_dummy_write_sp (gdbarch, sparc64_write_sp); |
5af923b0 MS |
3519 | tdep->y_regnum = SPARC64_Y_REGNUM; |
3520 | tdep->fp_max_regnum = SPARC_FP0_REGNUM + 48; | |
3521 | tdep->intreg_size = 8; | |
3522 | tdep->reg_save_offset = 0x90; | |
3523 | tdep->call_dummy_call_offset = 148 + 4 * 5; | |
3524 | break; | |
3525 | } | |
3526 | ||
3527 | /* | |
3528 | * Settings that vary per-architecture: | |
3529 | */ | |
3530 | ||
3531 | switch (info.bfd_arch_info->mach) | |
3532 | { | |
3533 | case bfd_mach_sparc: | |
44b7b84e MK |
3534 | set_gdbarch_extract_return_value (gdbarch, sparc32_extract_return_value); |
3535 | set_gdbarch_store_return_value (gdbarch, sparc32_store_return_value); | |
5af923b0 | 3536 | set_gdbarch_num_regs (gdbarch, 72); |
b8b527c5 | 3537 | set_gdbarch_deprecated_register_bytes (gdbarch, 32*4 + 32*4 + 8*4); |
5af923b0 | 3538 | set_gdbarch_register_name (gdbarch, sparc32_register_name); |
f81824a9 AC |
3539 | #if 0 |
3540 | // OBSOLETE tdep->has_fpu = 1; /* (all but sparclet and sparclite) */ | |
3541 | #endif | |
5af923b0 MS |
3542 | tdep->fp_register_bytes = 32 * 4; |
3543 | tdep->print_insn_mach = bfd_mach_sparc; | |
3544 | break; | |
f81824a9 AC |
3545 | #if 0 |
3546 | // OBSOLETE case bfd_mach_sparc_sparclet: | |
3547 | // OBSOLETE set_gdbarch_deprecated_extract_return_value (gdbarch, sparclet_extract_return_value); | |
3548 | // OBSOLETE set_gdbarch_num_regs (gdbarch, 32 + 32 + 8 + 8 + 8); | |
3549 | // OBSOLETE set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4 + 8*4 + 8*4); | |
3550 | // OBSOLETE set_gdbarch_register_name (gdbarch, sparclet_register_name); | |
3551 | // OBSOLETE set_gdbarch_deprecated_store_return_value (gdbarch, sparclet_store_return_value); | |
3552 | // OBSOLETE tdep->has_fpu = 0; /* (all but sparclet and sparclite) */ | |
3553 | // OBSOLETE tdep->fp_register_bytes = 0; | |
3554 | // OBSOLETE tdep->print_insn_mach = bfd_mach_sparc_sparclet; | |
3555 | // OBSOLETE break; | |
3556 | #endif | |
3557 | #if 0 | |
3558 | // OBSOLETE case bfd_mach_sparc_sparclite: | |
3559 | // OBSOLETE set_gdbarch_deprecated_extract_return_value (gdbarch, sparc32_extract_return_value); | |
3560 | // OBSOLETE set_gdbarch_num_regs (gdbarch, 80); | |
3561 | // OBSOLETE set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4 + 8*4); | |
3562 | // OBSOLETE set_gdbarch_register_name (gdbarch, sparclite_register_name); | |
3563 | // OBSOLETE set_gdbarch_deprecated_store_return_value (gdbarch, sparc_store_return_value); | |
3564 | // OBSOLETE tdep->has_fpu = 0; /* (all but sparclet and sparclite) */ | |
3565 | // OBSOLETE tdep->fp_register_bytes = 0; | |
3566 | // OBSOLETE tdep->print_insn_mach = bfd_mach_sparc_sparclite; | |
3567 | // OBSOLETE break; | |
3568 | #endif | |
5af923b0 | 3569 | case bfd_mach_sparc_v8plus: |
44b7b84e MK |
3570 | set_gdbarch_extract_return_value (gdbarch, sparc32_extract_return_value); |
3571 | set_gdbarch_store_return_value (gdbarch, sparc32_store_return_value); | |
5af923b0 | 3572 | set_gdbarch_num_regs (gdbarch, 72); |
b8b527c5 | 3573 | set_gdbarch_deprecated_register_bytes (gdbarch, 32*4 + 32*4 + 8*4); |
5af923b0 | 3574 | set_gdbarch_register_name (gdbarch, sparc32_register_name); |
5af923b0 MS |
3575 | tdep->print_insn_mach = bfd_mach_sparc; |
3576 | tdep->fp_register_bytes = 32 * 4; | |
f81824a9 AC |
3577 | #if 0 |
3578 | // OBSOLETE tdep->has_fpu = 1; /* (all but sparclet and sparclite) */ | |
3579 | #endif | |
5af923b0 MS |
3580 | break; |
3581 | case bfd_mach_sparc_v8plusa: | |
44b7b84e MK |
3582 | set_gdbarch_extract_return_value (gdbarch, sparc32_extract_return_value); |
3583 | set_gdbarch_store_return_value (gdbarch, sparc32_store_return_value); | |
5af923b0 | 3584 | set_gdbarch_num_regs (gdbarch, 72); |
b8b527c5 | 3585 | set_gdbarch_deprecated_register_bytes (gdbarch, 32*4 + 32*4 + 8*4); |
5af923b0 | 3586 | set_gdbarch_register_name (gdbarch, sparc32_register_name); |
f81824a9 AC |
3587 | #if 0 |
3588 | // OBSOLETE tdep->has_fpu = 1; /* (all but sparclet and sparclite) */ | |
3589 | #endif | |
5af923b0 MS |
3590 | tdep->fp_register_bytes = 32 * 4; |
3591 | tdep->print_insn_mach = bfd_mach_sparc; | |
3592 | break; | |
f81824a9 AC |
3593 | #if 0 |
3594 | // OBSOLETE case bfd_mach_sparc_sparclite_le: | |
3595 | // OBSOLETE set_gdbarch_deprecated_extract_return_value (gdbarch, sparc32_extract_return_value); | |
3596 | // OBSOLETE set_gdbarch_num_regs (gdbarch, 80); | |
3597 | // OBSOLETE set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4 + 8*4); | |
3598 | // OBSOLETE set_gdbarch_register_name (gdbarch, sparclite_register_name); | |
3599 | // OBSOLETE set_gdbarch_deprecated_store_return_value (gdbarch, sparc_store_return_value); | |
3600 | // OBSOLETE tdep->has_fpu = 0; /* (all but sparclet and sparclite) */ | |
3601 | // OBSOLETE tdep->fp_register_bytes = 0; | |
3602 | // OBSOLETE tdep->print_insn_mach = bfd_mach_sparc_sparclite; | |
3603 | // OBSOLETE break; | |
3604 | #endif | |
5af923b0 | 3605 | case bfd_mach_sparc_v9: |
26e9b323 | 3606 | set_gdbarch_deprecated_extract_return_value (gdbarch, sparc64_extract_return_value); |
5af923b0 | 3607 | set_gdbarch_num_regs (gdbarch, 125); |
b8b527c5 | 3608 | set_gdbarch_deprecated_register_bytes (gdbarch, 32*8 + 32*8 + 45*8); |
5af923b0 | 3609 | set_gdbarch_register_name (gdbarch, sparc64_register_name); |
ebba8386 | 3610 | set_gdbarch_deprecated_store_return_value (gdbarch, sparc_store_return_value); |
f81824a9 AC |
3611 | #if 0 |
3612 | // OBSOLETE tdep->has_fpu = 1; /* (all but sparclet and sparclite) */ | |
3613 | #endif | |
5af923b0 MS |
3614 | tdep->fp_register_bytes = 64 * 4; |
3615 | tdep->print_insn_mach = bfd_mach_sparc_v9a; | |
3616 | break; | |
3617 | case bfd_mach_sparc_v9a: | |
26e9b323 | 3618 | set_gdbarch_deprecated_extract_return_value (gdbarch, sparc64_extract_return_value); |
5af923b0 | 3619 | set_gdbarch_num_regs (gdbarch, 125); |
b8b527c5 | 3620 | set_gdbarch_deprecated_register_bytes (gdbarch, 32*8 + 32*8 + 45*8); |
5af923b0 | 3621 | set_gdbarch_register_name (gdbarch, sparc64_register_name); |
ebba8386 | 3622 | set_gdbarch_deprecated_store_return_value (gdbarch, sparc_store_return_value); |
f81824a9 AC |
3623 | #if 0 |
3624 | // OBSOLETE tdep->has_fpu = 1; /* (all but sparclet and sparclite) */ | |
3625 | #endif | |
5af923b0 MS |
3626 | tdep->fp_register_bytes = 64 * 4; |
3627 | tdep->print_insn_mach = bfd_mach_sparc_v9a; | |
3628 | break; | |
3629 | } | |
3630 | ||
ef3cf062 | 3631 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
4be87837 | 3632 | gdbarch_init_osabi (info, gdbarch); |
ef3cf062 | 3633 | |
5af923b0 MS |
3634 | return gdbarch; |
3635 | } | |
3636 | ||
ef3cf062 JT |
3637 | static void |
3638 | sparc_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
3639 | { | |
3640 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3641 | ||
3642 | if (tdep == NULL) | |
3643 | return; | |
3644 | ||
f81824a9 AC |
3645 | #if 0 |
3646 | // OBSOLETE fprintf_unfiltered (file, "sparc_dump_tdep: has_fpu = %d\n", | |
3647 | // OBSOLETE tdep->has_fpu); | |
3648 | #endif | |
4be87837 DJ |
3649 | fprintf_unfiltered (file, "sparc_dump_tdep: fp_register_bytes = %d\n", |
3650 | tdep->fp_register_bytes); | |
3651 | fprintf_unfiltered (file, "sparc_dump_tdep: y_regnum = %d\n", | |
3652 | tdep->y_regnum); | |
3653 | fprintf_unfiltered (file, "sparc_dump_tdep: fp_max_regnum = %d\n", | |
3654 | tdep->fp_max_regnum); | |
3655 | fprintf_unfiltered (file, "sparc_dump_tdep: intreg_size = %d\n", | |
3656 | tdep->intreg_size); | |
3657 | fprintf_unfiltered (file, "sparc_dump_tdep: reg_save_offset = %d\n", | |
3658 | tdep->reg_save_offset); | |
3659 | fprintf_unfiltered (file, "sparc_dump_tdep: call_dummy_call_offset = %d\n", | |
3660 | tdep->call_dummy_call_offset); | |
3661 | fprintf_unfiltered (file, "sparc_dump_tdep: print_insn_match = %d\n", | |
d995ff4b | 3662 | tdep->print_insn_mach); |
ef3cf062 | 3663 | } |