Commit | Line | Data |
---|---|---|
f9e3b3cc JG |
1 | /* Target-dependent code for the SPARC for GDB, the GNU debugger. |
2 | Copyright 1986, 1987, 1989, 1991, 1992 Free Software Foundation, Inc. | |
bd5635a1 RP |
3 | |
4 | This file is part of GDB. | |
5 | ||
5259796b | 6 | This program is free software; you can redistribute it and/or modify |
bd5635a1 | 7 | it under the terms of the GNU General Public License as published by |
5259796b JG |
8 | the Free Software Foundation; either version 2 of the License, or |
9 | (at your option) any later version. | |
bd5635a1 | 10 | |
5259796b | 11 | This program is distributed in the hope that it will be useful, |
bd5635a1 RP |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
5259796b JG |
17 | along with this program; if not, write to the Free Software |
18 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
bd5635a1 | 19 | |
bd5635a1 | 20 | #include "defs.h" |
bd5635a1 RP |
21 | #include "frame.h" |
22 | #include "inferior.h" | |
23 | #include "obstack.h" | |
bd5635a1 RP |
24 | #include "target.h" |
25 | #include "ieee-float.h" | |
26 | ||
8f86a4e4 JG |
27 | #ifdef USE_PROC_FS |
28 | #include <sys/procfs.h> | |
29 | #else | |
bd5635a1 | 30 | #include <sys/ptrace.h> |
8f86a4e4 | 31 | #endif |
bd5635a1 | 32 | |
bd5635a1 RP |
33 | #include "gdbcore.h" |
34 | ||
35 | /* From infrun.c */ | |
36 | extern int stop_after_trap; | |
37 | ||
b38f304c JG |
38 | /* We don't store all registers immediately when requested, since they |
39 | get sent over in large chunks anyway. Instead, we accumulate most | |
40 | of the changes and send them over once. "deferred_stores" keeps | |
41 | track of which sets of registers we have locally-changed copies of, | |
42 | so we only need send the groups that have changed. */ | |
43 | ||
44 | int deferred_stores = 0; /* Cumulates stores we want to do eventually. */ | |
45 | ||
bd5635a1 RP |
46 | typedef enum |
47 | { | |
f9e3b3cc | 48 | Error, not_branch, bicc, bicca, ba, baa, ticc, ta |
bd5635a1 RP |
49 | } branch_type; |
50 | ||
51 | /* Simulate single-step ptrace call for sun4. Code written by Gary | |
52 | Beihl (beihl@mcc.com). */ | |
53 | ||
54 | /* npc4 and next_pc describe the situation at the time that the | |
55 | step-breakpoint was set, not necessary the current value of NPC_REGNUM. */ | |
56 | static CORE_ADDR next_pc, npc4, target; | |
57 | static int brknpc4, brktrg; | |
58 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
59 | static binsn_quantum break_mem[3]; | |
60 | ||
61 | /* Non-zero if we just simulated a single-step ptrace call. This is | |
62 | needed because we cannot remove the breakpoints in the inferior | |
63 | process until after the `wait' in `wait_for_inferior'. Used for | |
64 | sun4. */ | |
65 | ||
66 | int one_stepped; | |
67 | ||
d11c44f1 JG |
68 | /* single_step() is called just before we want to resume the inferior, |
69 | if we want to single-step it but there is no hardware or kernel single-step | |
70 | support (as on all SPARCs). We find all the possible targets of the | |
71 | coming instruction and breakpoint them. | |
72 | ||
73 | single_step is also called just after the inferior stops. If we had | |
74 | set up a simulated single-step, we undo our damage. */ | |
75 | ||
bd5635a1 | 76 | void |
8f86a4e4 JG |
77 | single_step (ignore) |
78 | int ignore; /* pid, but we don't need it */ | |
bd5635a1 RP |
79 | { |
80 | branch_type br, isannulled(); | |
81 | CORE_ADDR pc; | |
82 | long pc_instruction; | |
83 | ||
84 | if (!one_stepped) | |
85 | { | |
86 | /* Always set breakpoint for NPC. */ | |
87 | next_pc = read_register (NPC_REGNUM); | |
88 | npc4 = next_pc + 4; /* branch not taken */ | |
89 | ||
90 | target_insert_breakpoint (next_pc, break_mem[0]); | |
91 | /* printf ("set break at %x\n",next_pc); */ | |
92 | ||
93 | pc = read_register (PC_REGNUM); | |
94 | pc_instruction = read_memory_integer (pc, sizeof(pc_instruction)); | |
95 | br = isannulled (pc_instruction, pc, &target); | |
96 | brknpc4 = brktrg = 0; | |
97 | ||
98 | if (br == bicca) | |
99 | { | |
100 | /* Conditional annulled branch will either end up at | |
101 | npc (if taken) or at npc+4 (if not taken). | |
102 | Trap npc+4. */ | |
103 | brknpc4 = 1; | |
104 | target_insert_breakpoint (npc4, break_mem[1]); | |
105 | } | |
106 | else if (br == baa && target != next_pc) | |
107 | { | |
108 | /* Unconditional annulled branch will always end up at | |
109 | the target. */ | |
110 | brktrg = 1; | |
111 | target_insert_breakpoint (target, break_mem[2]); | |
112 | } | |
113 | ||
d11c44f1 | 114 | /* We are ready to let it go */ |
bd5635a1 RP |
115 | one_stepped = 1; |
116 | return; | |
117 | } | |
118 | else | |
119 | { | |
120 | /* Remove breakpoints */ | |
121 | target_remove_breakpoint (next_pc, break_mem[0]); | |
122 | ||
123 | if (brknpc4) | |
124 | target_remove_breakpoint (npc4, break_mem[1]); | |
125 | ||
126 | if (brktrg) | |
127 | target_remove_breakpoint (target, break_mem[2]); | |
128 | ||
129 | one_stepped = 0; | |
130 | } | |
131 | } | |
132 | \f | |
f9e3b3cc JG |
133 | #define FRAME_SAVED_L0 0 /* Byte offset from SP */ |
134 | #define FRAME_SAVED_I0 32 /* Byte offset from SP */ | |
135 | ||
d11c44f1 JG |
136 | CORE_ADDR |
137 | sparc_frame_chain (thisframe) | |
138 | FRAME thisframe; | |
139 | { | |
140 | CORE_ADDR retval; | |
5259796b | 141 | int err; |
f9e3b3cc JG |
142 | CORE_ADDR addr; |
143 | ||
144 | addr = thisframe->frame + FRAME_SAVED_I0 + | |
145 | REGISTER_RAW_SIZE(FP_REGNUM) * (FP_REGNUM - I0_REGNUM); | |
146 | err = target_read_memory (addr, (char *) &retval, sizeof (CORE_ADDR)); | |
5259796b JG |
147 | if (err) |
148 | return 0; | |
f9e3b3cc | 149 | SWAP_TARGET_AND_HOST (&retval, sizeof (retval)); |
d11c44f1 JG |
150 | return retval; |
151 | } | |
152 | ||
153 | CORE_ADDR | |
154 | sparc_extract_struct_value_address (regbuf) | |
155 | char regbuf[REGISTER_BYTES]; | |
156 | { | |
f9e3b3cc JG |
157 | /* FIXME, handle byte swapping */ |
158 | return read_memory_integer (((int *)(regbuf))[SP_REGNUM]+(16*4), | |
159 | sizeof (CORE_ADDR)); | |
d11c44f1 JG |
160 | } |
161 | ||
f9e3b3cc JG |
162 | /* Find the pc saved in frame FRAME. */ |
163 | ||
bd5635a1 RP |
164 | CORE_ADDR |
165 | frame_saved_pc (frame) | |
166 | FRAME frame; | |
167 | { | |
168 | CORE_ADDR prev_pc; | |
169 | ||
f9e3b3cc JG |
170 | if (get_current_frame () == frame) /* FIXME, debug check. Remove >=gdb-4.6 */ |
171 | { | |
172 | if (read_register (SP_REGNUM) != frame->bottom) abort(); | |
173 | } | |
174 | ||
175 | read_memory ((CORE_ADDR) (frame->bottom + FRAME_SAVED_I0 + | |
176 | REGISTER_RAW_SIZE(I7_REGNUM) * (I7_REGNUM - I0_REGNUM)), | |
177 | (char *) &prev_pc, | |
178 | sizeof (CORE_ADDR)); | |
179 | ||
180 | SWAP_TARGET_AND_HOST (&prev_pc, sizeof (prev_pc)); | |
bd5635a1 RP |
181 | return PC_ADJUST (prev_pc); |
182 | } | |
183 | ||
184 | /* | |
185 | * Since an individual frame in the frame cache is defined by two | |
186 | * arguments (a frame pointer and a stack pointer), we need two | |
187 | * arguments to get info for an arbitrary stack frame. This routine | |
188 | * takes two arguments and makes the cached frames look as if these | |
189 | * two arguments defined a frame on the cache. This allows the rest | |
190 | * of info frame to extract the important arguments without | |
191 | * difficulty. | |
192 | */ | |
193 | FRAME | |
194 | setup_arbitrary_frame (frame, stack) | |
195 | FRAME_ADDR frame, stack; | |
196 | { | |
197 | FRAME fid = create_new_frame (frame, 0); | |
198 | ||
199 | if (!fid) | |
200 | fatal ("internal: create_new_frame returned invalid frame id"); | |
201 | ||
202 | fid->bottom = stack; | |
5259796b | 203 | fid->pc = FRAME_SAVED_PC (fid); |
bd5635a1 RP |
204 | return fid; |
205 | } | |
206 | ||
207 | /* This code was written by Gary Beihl (beihl@mcc.com). | |
208 | It was modified by Michael Tiemann (tiemann@corto.inria.fr). */ | |
209 | ||
210 | /* | |
211 | * This routine appears to be passed a size by which to increase the | |
212 | * stack. It then executes a save instruction in the inferior to | |
213 | * increase the stack by this amount. Only the register window system | |
214 | * should be affected by this; the program counter & etc. will not be. | |
215 | * | |
216 | * This instructions used for this purpose are: | |
217 | * | |
218 | * sethi %hi(0x0),g1 * | |
219 | * add g1,0x1ee0,g1 * | |
220 | * save sp,g1,sp | |
221 | * sethi %hi(0x0),g1 * | |
222 | * add g1,0x1ee0,g1 * | |
223 | * t g0,0x1,o0 | |
224 | * sethi %hi(0x0),g0 (nop) | |
225 | * | |
226 | * I presume that these set g1 to be the negative of the size, do a | |
227 | * save (putting the stack pointer at sp - size) and restore the | |
228 | * original contents of g1. A * indicates that the actual value of | |
229 | * the instruction is modified below. | |
230 | */ | |
231 | static int save_insn_opcodes[] = { | |
232 | 0x03000000, 0x82007ee0, 0x9de38001, 0x03000000, | |
233 | 0x82007ee0, 0x91d02001, 0x01000000 }; | |
234 | ||
235 | /* Neither do_save_insn or do_restore_insn save stack configuration | |
236 | (current_frame, etc), | |
237 | since the stack is in an indeterminate state through the call to | |
b38f304c | 238 | each of them. That is the responsibility of the routine which calls them. */ |
bd5635a1 RP |
239 | |
240 | static void | |
241 | do_save_insn (size) | |
242 | int size; | |
243 | { | |
244 | int g1 = read_register (G1_REGNUM); | |
245 | CORE_ADDR sp = read_register (SP_REGNUM); | |
246 | CORE_ADDR pc = read_register (PC_REGNUM); | |
247 | CORE_ADDR npc = read_register (NPC_REGNUM); | |
248 | CORE_ADDR fake_pc = sp - sizeof (save_insn_opcodes); | |
249 | struct inferior_status inf_status; | |
250 | ||
251 | save_inferior_status (&inf_status, 0); /* Don't restore stack info */ | |
252 | /* | |
253 | * See above. | |
254 | */ | |
255 | save_insn_opcodes[0] = 0x03000000 | ((-size >> 10) & 0x3fffff); | |
256 | save_insn_opcodes[1] = 0x82006000 | (-size & 0x3ff); | |
257 | save_insn_opcodes[3] = 0x03000000 | ((g1 >> 10) & 0x3fffff); | |
258 | save_insn_opcodes[4] = 0x82006000 | (g1 & 0x3ff); | |
259 | write_memory (fake_pc, (char *)save_insn_opcodes, sizeof (save_insn_opcodes)); | |
260 | ||
261 | clear_proceed_status (); | |
262 | stop_after_trap = 1; | |
263 | proceed (fake_pc, 0, 0); | |
264 | ||
265 | write_register (PC_REGNUM, pc); | |
266 | write_register (NPC_REGNUM, npc); | |
267 | restore_inferior_status (&inf_status); | |
268 | } | |
269 | ||
270 | /* | |
271 | * This routine takes a program counter value. It restores the | |
272 | * register window system to the frame above the current one. | |
273 | * THIS ROUTINE CLOBBERS PC AND NPC IN THE TARGET! | |
274 | */ | |
275 | ||
276 | /* The following insns translate to: | |
277 | ||
278 | restore %g0,%g0,%g0 | |
279 | t %g0,1 | |
280 | sethi %hi(0),%g0 */ | |
281 | ||
282 | static int restore_insn_opcodes[] = { 0x81e80000, 0x91d02001, 0x01000000 }; | |
283 | ||
284 | static void | |
285 | do_restore_insn () | |
286 | { | |
287 | CORE_ADDR sp = read_register (SP_REGNUM); | |
288 | CORE_ADDR fake_pc = sp - sizeof (restore_insn_opcodes); | |
289 | struct inferior_status inf_status; | |
290 | ||
291 | save_inferior_status (&inf_status, 0); /* Don't restore stack info */ | |
292 | ||
293 | write_memory (fake_pc, (char *)restore_insn_opcodes, | |
294 | sizeof (restore_insn_opcodes)); | |
295 | ||
296 | clear_proceed_status (); | |
297 | stop_after_trap = 1; | |
298 | proceed (fake_pc, 0, 0); | |
299 | ||
300 | restore_inferior_status (&inf_status); | |
301 | } | |
302 | ||
5259796b JG |
303 | /* Given a pc value, skip it forward past the function prologue by |
304 | disassembling instructions that appear to be a prologue. | |
305 | ||
306 | If FRAMELESS_P is set, we are only testing to see if the function | |
307 | is frameless. This allows a quicker answer. | |
308 | ||
309 | This routine should be more specific in its actions; making sure | |
192cbba9 | 310 | that it uses the same register in the initial prologue section. */ |
bd5635a1 | 311 | CORE_ADDR |
5259796b | 312 | skip_prologue (start_pc, frameless_p) |
192cbba9 | 313 | CORE_ADDR start_pc; |
5259796b | 314 | int frameless_p; |
bd5635a1 RP |
315 | { |
316 | union | |
317 | { | |
318 | unsigned long int code; | |
319 | struct | |
320 | { | |
321 | unsigned int op:2; | |
322 | unsigned int rd:5; | |
323 | unsigned int op2:3; | |
324 | unsigned int imm22:22; | |
325 | } sethi; | |
326 | struct | |
327 | { | |
328 | unsigned int op:2; | |
329 | unsigned int rd:5; | |
330 | unsigned int op3:6; | |
331 | unsigned int rs1:5; | |
332 | unsigned int i:1; | |
333 | unsigned int simm13:13; | |
334 | } add; | |
335 | int i; | |
336 | } x; | |
337 | int dest = -1; | |
192cbba9 | 338 | CORE_ADDR pc = start_pc; |
bd5635a1 RP |
339 | |
340 | x.i = read_memory_integer (pc, 4); | |
341 | ||
342 | /* Recognize the `sethi' insn and record its destination. */ | |
343 | if (x.sethi.op == 0 && x.sethi.op2 == 4) | |
344 | { | |
345 | dest = x.sethi.rd; | |
346 | pc += 4; | |
347 | x.i = read_memory_integer (pc, 4); | |
348 | } | |
349 | ||
350 | /* Recognize an add immediate value to register to either %g1 or | |
351 | the destination register recorded above. Actually, this might | |
192cbba9 JK |
352 | well recognize several different arithmetic operations. |
353 | It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1" | |
354 | followed by "save %sp, %g1, %sp" is a valid prologue (Not that | |
355 | I imagine any compiler really does that, however). */ | |
bd5635a1 RP |
356 | if (x.add.op == 2 && x.add.i && (x.add.rd == 1 || x.add.rd == dest)) |
357 | { | |
358 | pc += 4; | |
359 | x.i = read_memory_integer (pc, 4); | |
360 | } | |
361 | ||
362 | /* This recognizes any SAVE insn. But why do the XOR and then | |
363 | the compare? That's identical to comparing against 60 (as long | |
364 | as there isn't any sign extension). */ | |
365 | if (x.add.op == 2 && (x.add.op3 ^ 32) == 28) | |
366 | { | |
367 | pc += 4; | |
5259796b JG |
368 | if (frameless_p) /* If the save is all we care about, */ |
369 | return pc; /* return before doing more work */ | |
bd5635a1 RP |
370 | x.i = read_memory_integer (pc, 4); |
371 | } | |
5259796b JG |
372 | else |
373 | { | |
374 | /* Without a save instruction, it's not a prologue. */ | |
375 | return start_pc; | |
376 | } | |
bd5635a1 RP |
377 | |
378 | /* Now we need to recognize stores into the frame from the input | |
379 | registers. This recognizes all non alternate stores of input | |
380 | register, into a location offset from the frame pointer. */ | |
381 | while (x.add.op == 3 | |
382 | && (x.add.op3 & 0x3c) == 4 /* Store, non-alternate. */ | |
383 | && (x.add.rd & 0x18) == 0x18 /* Input register. */ | |
384 | && x.add.i /* Immediate mode. */ | |
385 | && x.add.rs1 == 30 /* Off of frame pointer. */ | |
386 | /* Into reserved stack space. */ | |
387 | && x.add.simm13 >= 0x44 | |
388 | && x.add.simm13 < 0x5b) | |
389 | { | |
390 | pc += 4; | |
391 | x.i = read_memory_integer (pc, 4); | |
392 | } | |
5259796b | 393 | return pc; |
bd5635a1 RP |
394 | } |
395 | ||
396 | /* Check instruction at ADDR to see if it is an annulled branch. | |
397 | All other instructions will go to NPC or will trap. | |
398 | Set *TARGET if we find a canidate branch; set to zero if not. */ | |
399 | ||
400 | branch_type | |
401 | isannulled (instruction, addr, target) | |
402 | long instruction; | |
403 | CORE_ADDR addr, *target; | |
404 | { | |
405 | branch_type val = not_branch; | |
406 | long int offset; /* Must be signed for sign-extend. */ | |
407 | union | |
408 | { | |
409 | unsigned long int code; | |
410 | struct | |
411 | { | |
412 | unsigned int op:2; | |
413 | unsigned int a:1; | |
414 | unsigned int cond:4; | |
415 | unsigned int op2:3; | |
416 | unsigned int disp22:22; | |
417 | } b; | |
418 | } insn; | |
419 | ||
420 | *target = 0; | |
421 | insn.code = instruction; | |
422 | ||
423 | if (insn.b.op == 0 | |
424 | && (insn.b.op2 == 2 || insn.b.op2 == 6 || insn.b.op2 == 7)) | |
425 | { | |
426 | if (insn.b.cond == 8) | |
427 | val = insn.b.a ? baa : ba; | |
428 | else | |
429 | val = insn.b.a ? bicca : bicc; | |
430 | offset = 4 * ((int) (insn.b.disp22 << 10) >> 10); | |
431 | *target = addr + offset; | |
432 | } | |
433 | ||
434 | return val; | |
435 | } | |
436 | ||
437 | /* sparc_frame_find_saved_regs () | |
438 | ||
439 | Stores, into a struct frame_saved_regs, | |
440 | the addresses of the saved registers of frame described by FRAME_INFO. | |
441 | This includes special registers such as pc and fp saved in special | |
442 | ways in the stack frame. sp is even more special: | |
443 | the address we return for it IS the sp for the next frame. | |
444 | ||
445 | Note that on register window machines, we are currently making the | |
446 | assumption that window registers are being saved somewhere in the | |
447 | frame in which they are being used. If they are stored in an | |
448 | inferior frame, find_saved_register will break. | |
449 | ||
450 | On the Sun 4, the only time all registers are saved is when | |
451 | a dummy frame is involved. Otherwise, the only saved registers | |
452 | are the LOCAL and IN registers which are saved as a result | |
453 | of the "save/restore" opcodes. This condition is determined | |
454 | by address rather than by value. | |
455 | ||
456 | The "pc" is not stored in a frame on the SPARC. (What is stored | |
457 | is a return address minus 8.) sparc_pop_frame knows how to | |
458 | deal with that. Other routines might or might not. | |
459 | ||
460 | See tm-sparc.h (PUSH_FRAME and friends) for CRITICAL information | |
461 | about how this works. */ | |
462 | ||
463 | void | |
464 | sparc_frame_find_saved_regs (fi, saved_regs_addr) | |
465 | struct frame_info *fi; | |
466 | struct frame_saved_regs *saved_regs_addr; | |
467 | { | |
468 | register int regnum; | |
469 | FRAME_ADDR frame = read_register (FP_REGNUM); | |
470 | FRAME fid = FRAME_INFO_ID (fi); | |
471 | ||
472 | if (!fid) | |
473 | fatal ("Bad frame info struct in FRAME_FIND_SAVED_REGS"); | |
474 | ||
b38f304c | 475 | memset (saved_regs_addr, 0, sizeof (*saved_regs_addr)); |
bd5635a1 RP |
476 | |
477 | /* Old test. | |
478 | if (fi->pc >= frame - CALL_DUMMY_LENGTH - 0x140 | |
479 | && fi->pc <= frame) */ | |
480 | ||
481 | if (fi->pc >= (fi->bottom ? fi->bottom : | |
482 | read_register (SP_REGNUM)) | |
483 | && fi->pc <= FRAME_FP(fi)) | |
484 | { | |
485 | /* Dummy frame. All but the window regs are in there somewhere. */ | |
486 | for (regnum = G1_REGNUM; regnum < G1_REGNUM+7; regnum++) | |
487 | saved_regs_addr->regs[regnum] = | |
488 | frame + (regnum - G0_REGNUM) * 4 - 0xa0; | |
489 | for (regnum = I0_REGNUM; regnum < I0_REGNUM+8; regnum++) | |
490 | saved_regs_addr->regs[regnum] = | |
491 | frame + (regnum - I0_REGNUM) * 4 - 0xc0; | |
492 | for (regnum = FP0_REGNUM; regnum < FP0_REGNUM + 32; regnum++) | |
493 | saved_regs_addr->regs[regnum] = | |
494 | frame + (regnum - FP0_REGNUM) * 4 - 0x80; | |
495 | for (regnum = Y_REGNUM; regnum < NUM_REGS; regnum++) | |
496 | saved_regs_addr->regs[regnum] = | |
497 | frame + (regnum - Y_REGNUM) * 4 - 0xe0; | |
498 | frame = fi->bottom ? | |
499 | fi->bottom : read_register (SP_REGNUM); | |
500 | } | |
501 | else | |
502 | { | |
503 | /* Normal frame. Just Local and In registers */ | |
504 | frame = fi->bottom ? | |
505 | fi->bottom : read_register (SP_REGNUM); | |
506 | for (regnum = L0_REGNUM; regnum < L0_REGNUM+16; regnum++) | |
507 | saved_regs_addr->regs[regnum] = frame + (regnum-L0_REGNUM) * 4; | |
508 | } | |
509 | if (fi->next) | |
510 | { | |
511 | /* Pull off either the next frame pointer or the stack pointer */ | |
512 | FRAME_ADDR next_next_frame = | |
513 | (fi->next->bottom ? | |
514 | fi->next->bottom : | |
515 | read_register (SP_REGNUM)); | |
516 | for (regnum = O0_REGNUM; regnum < O0_REGNUM+8; regnum++) | |
517 | saved_regs_addr->regs[regnum] = next_next_frame + regnum * 4; | |
518 | } | |
519 | /* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */ | |
520 | saved_regs_addr->regs[SP_REGNUM] = FRAME_FP (fi); | |
521 | } | |
522 | ||
523 | /* Push an empty stack frame, and record in it the current PC, regs, etc. | |
524 | ||
525 | Note that the write's are of registers in the context of the newly | |
526 | pushed frame. Thus the the fp*'s, the g*'s, the i*'s, and | |
527 | the randoms, of the new frame, are being saved. The locals and outs | |
528 | are new; they don't need to be saved. The i's and l's of | |
529 | the last frame were saved by the do_save_insn in the register | |
530 | file (now on the stack, since a context switch happended imm after). | |
531 | ||
532 | The return pointer register %i7 does not have | |
533 | the pc saved into it (return from this frame will be accomplished | |
534 | by a POP_FRAME). In fact, we must leave it unclobbered, since we | |
535 | must preserve it in the calling routine except across call instructions. */ | |
536 | ||
537 | /* Definitely see tm-sparc.h for more doc of the frame format here. */ | |
538 | ||
539 | void | |
540 | sparc_push_dummy_frame () | |
541 | { | |
542 | CORE_ADDR fp; | |
543 | char register_temp[REGISTER_BYTES]; | |
544 | ||
545 | do_save_insn (0x140); /* FIXME where does this value come from? */ | |
546 | fp = read_register (FP_REGNUM); | |
547 | ||
548 | read_register_bytes (REGISTER_BYTE (FP0_REGNUM), register_temp, 32 * 4); | |
549 | write_memory (fp - 0x80, register_temp, 32 * 4); | |
550 | ||
551 | read_register_bytes (REGISTER_BYTE (G0_REGNUM), register_temp, 8 * 4); | |
552 | write_memory (fp - 0xa0, register_temp, 8 * 4); | |
553 | ||
554 | read_register_bytes (REGISTER_BYTE (I0_REGNUM), register_temp, 8 * 4); | |
555 | write_memory (fp - 0xc0, register_temp, 8 * 4); | |
556 | ||
557 | /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */ | |
558 | read_register_bytes (REGISTER_BYTE (Y_REGNUM), register_temp, 8 * 4); | |
559 | write_memory (fp - 0xe0, register_temp, 8 * 4); | |
560 | } | |
561 | ||
562 | /* Discard from the stack the innermost frame, restoring all saved registers. | |
563 | ||
564 | Note that the values stored in fsr by get_frame_saved_regs are *in | |
565 | the context of the called frame*. What this means is that the i | |
566 | regs of fsr must be restored into the o regs of the (calling) frame that | |
567 | we pop into. We don't care about the output regs of the calling frame, | |
568 | since unless it's a dummy frame, it won't have any output regs in it. | |
569 | ||
570 | We never have to bother with %l (local) regs, since the called routine's | |
571 | locals get tossed, and the calling routine's locals are already saved | |
572 | on its stack. */ | |
573 | ||
574 | /* Definitely see tm-sparc.h for more doc of the frame format here. */ | |
575 | ||
576 | void | |
577 | sparc_pop_frame () | |
578 | { | |
579 | register FRAME frame = get_current_frame (); | |
580 | register CORE_ADDR pc; | |
581 | struct frame_saved_regs fsr; | |
582 | struct frame_info *fi; | |
583 | char raw_buffer[REGISTER_BYTES]; | |
584 | ||
585 | fi = get_frame_info (frame); | |
586 | get_frame_saved_regs (fi, &fsr); | |
587 | do_restore_insn (); | |
588 | if (fsr.regs[FP0_REGNUM]) | |
589 | { | |
590 | read_memory (fsr.regs[FP0_REGNUM], raw_buffer, 32 * 4); | |
591 | write_register_bytes (REGISTER_BYTE (FP0_REGNUM), raw_buffer, 32 * 4); | |
592 | } | |
593 | if (fsr.regs[G1_REGNUM]) | |
594 | { | |
595 | read_memory (fsr.regs[G1_REGNUM], raw_buffer, 7 * 4); | |
596 | write_register_bytes (REGISTER_BYTE (G1_REGNUM), raw_buffer, 7 * 4); | |
597 | } | |
598 | if (fsr.regs[I0_REGNUM]) | |
599 | { | |
600 | read_memory (fsr.regs[I0_REGNUM], raw_buffer, 8 * 4); | |
601 | write_register_bytes (REGISTER_BYTE (O0_REGNUM), raw_buffer, 8 * 4); | |
602 | } | |
603 | if (fsr.regs[PS_REGNUM]) | |
604 | write_register (PS_REGNUM, read_memory_integer (fsr.regs[PS_REGNUM], 4)); | |
605 | if (fsr.regs[Y_REGNUM]) | |
606 | write_register (Y_REGNUM, read_memory_integer (fsr.regs[Y_REGNUM], 4)); | |
607 | if (fsr.regs[PC_REGNUM]) | |
608 | { | |
609 | /* Explicitly specified PC (and maybe NPC) -- just restore them. */ | |
610 | write_register (PC_REGNUM, read_memory_integer (fsr.regs[PC_REGNUM], 4)); | |
611 | if (fsr.regs[NPC_REGNUM]) | |
612 | write_register (NPC_REGNUM, | |
613 | read_memory_integer (fsr.regs[NPC_REGNUM], 4)); | |
614 | } | |
615 | else if (fsr.regs[I7_REGNUM]) | |
616 | { | |
617 | /* Return address in %i7 -- adjust it, then restore PC and NPC from it */ | |
618 | pc = PC_ADJUST (read_memory_integer (fsr.regs[I7_REGNUM], 4)); | |
619 | write_register (PC_REGNUM, pc); | |
620 | write_register (NPC_REGNUM, pc + 4); | |
621 | } | |
622 | flush_cached_frames (); | |
623 | set_current_frame ( create_new_frame (read_register (FP_REGNUM), | |
624 | read_pc ())); | |
625 | } | |
626 | ||
5e5215eb JG |
627 | /* On the Sun 4 under SunOS, the compile will leave a fake insn which |
628 | encodes the structure size being returned. If we detect such | |
629 | a fake insn, step past it. */ | |
630 | ||
631 | CORE_ADDR | |
632 | sparc_pc_adjust(pc) | |
633 | CORE_ADDR pc; | |
634 | { | |
635 | long insn; | |
636 | int err; | |
637 | ||
638 | err = target_read_memory (pc + 8, (char *)&insn, sizeof(long)); | |
639 | SWAP_TARGET_AND_HOST (&insn, sizeof(long)); | |
640 | if ((err == 0) && (insn & 0xfffffe00) == 0) | |
641 | return pc+12; | |
642 | else | |
643 | return pc+8; | |
644 | } | |
645 | ||
646 | ||
bd5635a1 RP |
647 | /* Structure of SPARC extended floating point numbers. |
648 | This information is not currently used by GDB, since no current SPARC | |
649 | implementations support extended float. */ | |
650 | ||
f9e3b3cc | 651 | const struct ext_format ext_format_sparc = { |
bd5635a1 | 652 | /* tot sbyte smask expbyte manbyte */ |
f9e3b3cc | 653 | 16, 0, 0x80, 0,1, 4,8, /* sparc */ |
bd5635a1 | 654 | }; |
8f86a4e4 JG |
655 | \f |
656 | #ifdef USE_PROC_FS /* Target dependent support for /proc */ | |
657 | ||
658 | /* The /proc interface divides the target machine's register set up into | |
659 | two different sets, the general register set (gregset) and the floating | |
660 | point register set (fpregset). For each set, there is an ioctl to get | |
661 | the current register set and another ioctl to set the current values. | |
662 | ||
663 | The actual structure passed through the ioctl interface is, of course, | |
664 | naturally machine dependent, and is different for each set of registers. | |
665 | For the sparc for example, the general register set is typically defined | |
666 | by: | |
667 | ||
668 | typedef int gregset_t[38]; | |
669 | ||
670 | #define R_G0 0 | |
671 | ... | |
672 | #define R_TBR 37 | |
673 | ||
674 | and the floating point set by: | |
675 | ||
676 | typedef struct prfpregset { | |
677 | union { | |
678 | u_long pr_regs[32]; | |
679 | double pr_dregs[16]; | |
680 | } pr_fr; | |
681 | void * pr_filler; | |
682 | u_long pr_fsr; | |
683 | u_char pr_qcnt; | |
684 | u_char pr_q_entrysize; | |
685 | u_char pr_en; | |
686 | u_long pr_q[64]; | |
687 | } prfpregset_t; | |
688 | ||
689 | These routines provide the packing and unpacking of gregset_t and | |
690 | fpregset_t formatted data. | |
691 | ||
692 | */ | |
693 | ||
694 | ||
695 | /* Given a pointer to a general register set in /proc format (gregset_t *), | |
696 | unpack the register contents and supply them as gdb's idea of the current | |
697 | register values. */ | |
698 | ||
699 | void | |
700 | supply_gregset (gregsetp) | |
701 | prgregset_t *gregsetp; | |
702 | { | |
b38f304c | 703 | register int regi; |
8f86a4e4 JG |
704 | register prgreg_t *regp = (prgreg_t *) gregsetp; |
705 | ||
706 | /* GDB register numbers for Gn, On, Ln, In all match /proc reg numbers. */ | |
b38f304c | 707 | for (regi = G0_REGNUM ; regi <= I7_REGNUM ; regi++) |
8f86a4e4 | 708 | { |
b38f304c | 709 | supply_register (regi, (char *) (regp + regi)); |
8f86a4e4 JG |
710 | } |
711 | ||
712 | /* These require a bit more care. */ | |
713 | supply_register (PS_REGNUM, (char *) (regp + R_PS)); | |
714 | supply_register (PC_REGNUM, (char *) (regp + R_PC)); | |
715 | supply_register (NPC_REGNUM,(char *) (regp + R_nPC)); | |
716 | supply_register (Y_REGNUM, (char *) (regp + R_Y)); | |
717 | } | |
718 | ||
719 | void | |
720 | fill_gregset (gregsetp, regno) | |
721 | prgregset_t *gregsetp; | |
722 | int regno; | |
723 | { | |
724 | int regi; | |
725 | register prgreg_t *regp = (prgreg_t *) gregsetp; | |
726 | extern char registers[]; | |
727 | ||
728 | for (regi = 0 ; regi <= R_I7 ; regi++) | |
729 | { | |
730 | if ((regno == -1) || (regno == regi)) | |
731 | { | |
b38f304c | 732 | *(regp + regi) = *(int *) ®isters[REGISTER_BYTE (regi)]; |
8f86a4e4 JG |
733 | } |
734 | } | |
735 | if ((regno == -1) || (regno == PS_REGNUM)) | |
736 | { | |
737 | *(regp + R_PS) = *(int *) ®isters[REGISTER_BYTE (PS_REGNUM)]; | |
738 | } | |
739 | if ((regno == -1) || (regno == PC_REGNUM)) | |
740 | { | |
741 | *(regp + R_PC) = *(int *) ®isters[REGISTER_BYTE (PC_REGNUM)]; | |
742 | } | |
743 | if ((regno == -1) || (regno == NPC_REGNUM)) | |
744 | { | |
745 | *(regp + R_nPC) = *(int *) ®isters[REGISTER_BYTE (NPC_REGNUM)]; | |
746 | } | |
747 | if ((regno == -1) || (regno == Y_REGNUM)) | |
748 | { | |
749 | *(regp + R_Y) = *(int *) ®isters[REGISTER_BYTE (Y_REGNUM)]; | |
750 | } | |
751 | } | |
752 | ||
753 | #if defined (FP0_REGNUM) | |
754 | ||
755 | /* Given a pointer to a floating point register set in /proc format | |
756 | (fpregset_t *), unpack the register contents and supply them as gdb's | |
757 | idea of the current floating point register values. */ | |
758 | ||
759 | void | |
760 | supply_fpregset (fpregsetp) | |
761 | prfpregset_t *fpregsetp; | |
762 | { | |
763 | register int regi; | |
764 | char *from; | |
765 | ||
766 | for (regi = FP0_REGNUM ; regi < FP0_REGNUM+32 ; regi++) | |
767 | { | |
768 | from = (char *) &fpregsetp->pr_fr.pr_regs[regi-FP0_REGNUM]; | |
769 | supply_register (regi, from); | |
770 | } | |
771 | supply_register (FPS_REGNUM, (char *) &(fpregsetp->pr_fsr)); | |
772 | } | |
773 | ||
774 | /* Given a pointer to a floating point register set in /proc format | |
775 | (fpregset_t *), update the register specified by REGNO from gdb's idea | |
776 | of the current floating point register set. If REGNO is -1, update | |
777 | them all. */ | |
778 | ||
779 | void | |
780 | fill_fpregset (fpregsetp, regno) | |
781 | prfpregset_t *fpregsetp; | |
782 | int regno; | |
783 | { | |
784 | int regi; | |
785 | char *to; | |
786 | char *from; | |
787 | extern char registers[]; | |
788 | ||
789 | for (regi = FP0_REGNUM ; regi < FP0_REGNUM+32 ; regi++) | |
790 | { | |
791 | if ((regno == -1) || (regno == regi)) | |
792 | { | |
793 | from = (char *) ®isters[REGISTER_BYTE (regi)]; | |
794 | to = (char *) &fpregsetp->pr_fr.pr_regs[regi-FP0_REGNUM]; | |
b38f304c | 795 | memcpy (to, from, REGISTER_RAW_SIZE (regi)); |
8f86a4e4 JG |
796 | } |
797 | } | |
798 | if ((regno == -1) || (regno == FPS_REGNUM)) | |
799 | { | |
800 | fpregsetp->pr_fsr = *(int *) ®isters[REGISTER_BYTE (FPS_REGNUM)]; | |
801 | } | |
802 | } | |
803 | ||
804 | #endif /* defined (FP0_REGNUM) */ | |
805 | ||
806 | #endif /* USE_PROC_FS */ | |
807 | ||
808 | ||
809 | #ifdef GET_LONGJMP_TARGET | |
f9e3b3cc JG |
810 | |
811 | /* Figure out where the longjmp will land. We expect that we have just entered | |
812 | longjmp and haven't yet setup the stack frame, so the args are still in the | |
813 | output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we | |
814 | extract the pc (JB_PC) that we will land at. The pc is copied into ADDR. | |
815 | This routine returns true on success */ | |
816 | ||
817 | int | |
818 | get_longjmp_target(pc) | |
819 | CORE_ADDR *pc; | |
820 | { | |
821 | CORE_ADDR jb_addr; | |
822 | ||
823 | jb_addr = read_register(O0_REGNUM); | |
824 | ||
825 | if (target_read_memory(jb_addr + JB_PC * JB_ELEMENT_SIZE, (char *) pc, | |
826 | sizeof(CORE_ADDR))) | |
827 | return 0; | |
828 | ||
829 | SWAP_TARGET_AND_HOST(pc, sizeof(CORE_ADDR)); | |
830 | ||
831 | return 1; | |
832 | } | |
8f86a4e4 | 833 | #endif /* GET_LONGJMP_TARGET */ |