Commit | Line | Data |
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386c036b | 1 | /* Target-dependent code for SPARC. |
cda5a58a | 2 | |
ecd75fc8 | 3 | Copyright (C) 2003-2014 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 19 | |
c906108c | 20 | #include "defs.h" |
5af923b0 | 21 | #include "arch-utils.h" |
386c036b | 22 | #include "dis-asm.h" |
f5a9b87d | 23 | #include "dwarf2-frame.h" |
386c036b | 24 | #include "floatformat.h" |
c906108c | 25 | #include "frame.h" |
386c036b MK |
26 | #include "frame-base.h" |
27 | #include "frame-unwind.h" | |
28 | #include "gdbcore.h" | |
29 | #include "gdbtypes.h" | |
c906108c | 30 | #include "inferior.h" |
386c036b MK |
31 | #include "symtab.h" |
32 | #include "objfiles.h" | |
33 | #include "osabi.h" | |
34 | #include "regcache.h" | |
c906108c SS |
35 | #include "target.h" |
36 | #include "value.h" | |
c906108c | 37 | |
386c036b | 38 | #include "sparc-tdep.h" |
e6f9c00b | 39 | #include "sparc-ravenscar-thread.h" |
c906108c | 40 | |
a54124c5 MK |
41 | struct regset; |
42 | ||
9eb42ed1 MK |
43 | /* This file implements the SPARC 32-bit ABI as defined by the section |
44 | "Low-Level System Information" of the SPARC Compliance Definition | |
45 | (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD | |
f2e7c15d | 46 | lists changes with respect to the original 32-bit psABI as defined |
9eb42ed1 | 47 | in the "System V ABI, SPARC Processor Supplement". |
386c036b MK |
48 | |
49 | Note that if we talk about SunOS, we mean SunOS 4.x, which was | |
50 | BSD-based, which is sometimes (retroactively?) referred to as | |
51 | Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and | |
52 | above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 | |
53 | suffering from severe version number inflation). Solaris 2.x is | |
54 | also known as SunOS 5.x, since that's what uname(1) says. Solaris | |
55 | 2.x is SVR4-based. */ | |
56 | ||
57 | /* Please use the sparc32_-prefix for 32-bit specific code, the | |
58 | sparc64_-prefix for 64-bit specific code and the sparc_-prefix for | |
59 | code that can handle both. The 64-bit specific code lives in | |
60 | sparc64-tdep.c; don't add any here. */ | |
61 | ||
62 | /* The SPARC Floating-Point Quad-Precision format is similar to | |
7a58cce8 | 63 | big-endian IA-64 Quad-Precision format. */ |
8da61cc4 | 64 | #define floatformats_sparc_quad floatformats_ia64_quad |
386c036b MK |
65 | |
66 | /* The stack pointer is offset from the stack frame by a BIAS of 2047 | |
67 | (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC | |
68 | hosts, so undefine it first. */ | |
69 | #undef BIAS | |
70 | #define BIAS 2047 | |
71 | ||
72 | /* Macros to extract fields from SPARC instructions. */ | |
c906108c SS |
73 | #define X_OP(i) (((i) >> 30) & 0x3) |
74 | #define X_RD(i) (((i) >> 25) & 0x1f) | |
75 | #define X_A(i) (((i) >> 29) & 1) | |
76 | #define X_COND(i) (((i) >> 25) & 0xf) | |
77 | #define X_OP2(i) (((i) >> 22) & 0x7) | |
78 | #define X_IMM22(i) ((i) & 0x3fffff) | |
79 | #define X_OP3(i) (((i) >> 19) & 0x3f) | |
075ccec8 | 80 | #define X_RS1(i) (((i) >> 14) & 0x1f) |
b0b92586 | 81 | #define X_RS2(i) ((i) & 0x1f) |
c906108c | 82 | #define X_I(i) (((i) >> 13) & 1) |
c906108c | 83 | /* Sign extension macros. */ |
c906108c | 84 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) |
c906108c | 85 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) |
8d1b3521 | 86 | #define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200) |
075ccec8 | 87 | #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000) |
961842b2 JM |
88 | /* Macros to identify some instructions. */ |
89 | /* RETURN (RETT in V8) */ | |
90 | #define X_RETTURN(i) ((X_OP (i) == 0x2) && (X_OP3 (i) == 0x39)) | |
c906108c | 91 | |
386c036b MK |
92 | /* Fetch the instruction at PC. Instructions are always big-endian |
93 | even if the processor operates in little-endian mode. */ | |
94 | ||
95 | unsigned long | |
96 | sparc_fetch_instruction (CORE_ADDR pc) | |
c906108c | 97 | { |
e1613aba | 98 | gdb_byte buf[4]; |
386c036b MK |
99 | unsigned long insn; |
100 | int i; | |
101 | ||
690668cc | 102 | /* If we can't read the instruction at PC, return zero. */ |
8defab1a | 103 | if (target_read_memory (pc, buf, sizeof (buf))) |
690668cc | 104 | return 0; |
c906108c | 105 | |
386c036b MK |
106 | insn = 0; |
107 | for (i = 0; i < sizeof (buf); i++) | |
108 | insn = (insn << 8) | buf[i]; | |
109 | return insn; | |
110 | } | |
42cdca6c MK |
111 | \f |
112 | ||
5465445a JB |
113 | /* Return non-zero if the instruction corresponding to PC is an "unimp" |
114 | instruction. */ | |
115 | ||
116 | static int | |
117 | sparc_is_unimp_insn (CORE_ADDR pc) | |
118 | { | |
119 | const unsigned long insn = sparc_fetch_instruction (pc); | |
120 | ||
121 | return ((insn & 0xc1c00000) == 0); | |
122 | } | |
123 | ||
d0b5971a JM |
124 | /* Return non-zero if the instruction corresponding to PC is an |
125 | "annulled" branch, i.e. the annul bit is set. */ | |
126 | ||
127 | int | |
128 | sparc_is_annulled_branch_insn (CORE_ADDR pc) | |
129 | { | |
130 | /* The branch instructions featuring an annul bit can be identified | |
131 | by the following bit patterns: | |
132 | ||
133 | OP=0 | |
134 | OP2=1: Branch on Integer Condition Codes with Prediction (BPcc). | |
135 | OP2=2: Branch on Integer Condition Codes (Bcc). | |
136 | OP2=5: Branch on FP Condition Codes with Prediction (FBfcc). | |
137 | OP2=6: Branch on FP Condition Codes (FBcc). | |
138 | OP2=3 && Bit28=0: | |
139 | Branch on Integer Register with Prediction (BPr). | |
140 | ||
141 | This leaves out ILLTRAP (OP2=0), SETHI/NOP (OP2=4) and the V8 | |
142 | coprocessor branch instructions (Op2=7). */ | |
143 | ||
144 | const unsigned long insn = sparc_fetch_instruction (pc); | |
145 | const unsigned op2 = X_OP2 (insn); | |
146 | ||
147 | if ((X_OP (insn) == 0) | |
148 | && ((op2 == 1) || (op2 == 2) || (op2 == 5) || (op2 == 6) | |
149 | || ((op2 == 3) && ((insn & 0x10000000) == 0)))) | |
150 | return X_A (insn); | |
151 | else | |
152 | return 0; | |
153 | } | |
154 | ||
42cdca6c MK |
155 | /* OpenBSD/sparc includes StackGhost, which according to the author's |
156 | website http://stackghost.cerias.purdue.edu "... transparently and | |
157 | automatically protects applications' stack frames; more | |
158 | specifically, it guards the return pointers. The protection | |
159 | mechanisms require no application source or binary modification and | |
160 | imposes only a negligible performance penalty." | |
161 | ||
162 | The same website provides the following description of how | |
163 | StackGhost works: | |
164 | ||
165 | "StackGhost interfaces with the kernel trap handler that would | |
166 | normally write out registers to the stack and the handler that | |
167 | would read them back in. By XORing a cookie into the | |
168 | return-address saved in the user stack when it is actually written | |
169 | to the stack, and then XOR it out when the return-address is pulled | |
170 | from the stack, StackGhost can cause attacker corrupted return | |
171 | pointers to behave in a manner the attacker cannot predict. | |
172 | StackGhost can also use several unused bits in the return pointer | |
173 | to detect a smashed return pointer and abort the process." | |
174 | ||
175 | For GDB this means that whenever we're reading %i7 from a stack | |
176 | frame's window save area, we'll have to XOR the cookie. | |
177 | ||
178 | More information on StackGuard can be found on in: | |
179 | ||
c378eb4e | 180 | Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated |
42cdca6c MK |
181 | Stack Protection." 2001. Published in USENIX Security Symposium |
182 | '01. */ | |
183 | ||
184 | /* Fetch StackGhost Per-Process XOR cookie. */ | |
185 | ||
186 | ULONGEST | |
e17a4113 | 187 | sparc_fetch_wcookie (struct gdbarch *gdbarch) |
42cdca6c | 188 | { |
e17a4113 | 189 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
baf92889 | 190 | struct target_ops *ops = ¤t_target; |
e1613aba | 191 | gdb_byte buf[8]; |
baf92889 MK |
192 | int len; |
193 | ||
13547ab6 | 194 | len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8); |
baf92889 MK |
195 | if (len == -1) |
196 | return 0; | |
42cdca6c | 197 | |
baf92889 MK |
198 | /* We should have either an 32-bit or an 64-bit cookie. */ |
199 | gdb_assert (len == 4 || len == 8); | |
200 | ||
e17a4113 | 201 | return extract_unsigned_integer (buf, len, byte_order); |
baf92889 | 202 | } |
386c036b | 203 | \f |
baf92889 | 204 | |
386c036b MK |
205 | /* The functions on this page are intended to be used to classify |
206 | function arguments. */ | |
c906108c | 207 | |
386c036b | 208 | /* Check whether TYPE is "Integral or Pointer". */ |
c906108c | 209 | |
386c036b MK |
210 | static int |
211 | sparc_integral_or_pointer_p (const struct type *type) | |
c906108c | 212 | { |
80ad1639 MK |
213 | int len = TYPE_LENGTH (type); |
214 | ||
386c036b | 215 | switch (TYPE_CODE (type)) |
c906108c | 216 | { |
386c036b MK |
217 | case TYPE_CODE_INT: |
218 | case TYPE_CODE_BOOL: | |
219 | case TYPE_CODE_CHAR: | |
220 | case TYPE_CODE_ENUM: | |
221 | case TYPE_CODE_RANGE: | |
80ad1639 MK |
222 | /* We have byte, half-word, word and extended-word/doubleword |
223 | integral types. The doubleword is an extension to the | |
224 | original 32-bit ABI by the SCD 2.4.x. */ | |
225 | return (len == 1 || len == 2 || len == 4 || len == 8); | |
386c036b MK |
226 | case TYPE_CODE_PTR: |
227 | case TYPE_CODE_REF: | |
80ad1639 MK |
228 | /* Allow either 32-bit or 64-bit pointers. */ |
229 | return (len == 4 || len == 8); | |
386c036b MK |
230 | default: |
231 | break; | |
232 | } | |
c906108c | 233 | |
386c036b MK |
234 | return 0; |
235 | } | |
c906108c | 236 | |
386c036b | 237 | /* Check whether TYPE is "Floating". */ |
c906108c | 238 | |
386c036b MK |
239 | static int |
240 | sparc_floating_p (const struct type *type) | |
241 | { | |
242 | switch (TYPE_CODE (type)) | |
c906108c | 243 | { |
386c036b MK |
244 | case TYPE_CODE_FLT: |
245 | { | |
246 | int len = TYPE_LENGTH (type); | |
247 | return (len == 4 || len == 8 || len == 16); | |
248 | } | |
249 | default: | |
250 | break; | |
251 | } | |
252 | ||
253 | return 0; | |
254 | } | |
c906108c | 255 | |
fe10a582 DM |
256 | /* Check whether TYPE is "Complex Floating". */ |
257 | ||
258 | static int | |
259 | sparc_complex_floating_p (const struct type *type) | |
260 | { | |
261 | switch (TYPE_CODE (type)) | |
262 | { | |
263 | case TYPE_CODE_COMPLEX: | |
264 | { | |
265 | int len = TYPE_LENGTH (type); | |
266 | return (len == 8 || len == 16 || len == 32); | |
267 | } | |
268 | default: | |
269 | break; | |
270 | } | |
271 | ||
272 | return 0; | |
273 | } | |
274 | ||
0497f5b0 JB |
275 | /* Check whether TYPE is "Structure or Union". |
276 | ||
277 | In terms of Ada subprogram calls, arrays are treated the same as | |
278 | struct and union types. So this function also returns non-zero | |
279 | for array types. */ | |
c906108c | 280 | |
386c036b MK |
281 | static int |
282 | sparc_structure_or_union_p (const struct type *type) | |
283 | { | |
284 | switch (TYPE_CODE (type)) | |
285 | { | |
286 | case TYPE_CODE_STRUCT: | |
287 | case TYPE_CODE_UNION: | |
0497f5b0 | 288 | case TYPE_CODE_ARRAY: |
386c036b MK |
289 | return 1; |
290 | default: | |
291 | break; | |
c906108c | 292 | } |
386c036b MK |
293 | |
294 | return 0; | |
c906108c | 295 | } |
386c036b MK |
296 | |
297 | /* Register information. */ | |
298 | ||
299 | static const char *sparc32_register_names[] = | |
5af923b0 | 300 | { |
386c036b MK |
301 | "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
302 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", | |
303 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", | |
304 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", | |
305 | ||
306 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
307 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
308 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
309 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
310 | ||
311 | "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" | |
5af923b0 MS |
312 | }; |
313 | ||
386c036b MK |
314 | /* Total number of registers. */ |
315 | #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) | |
c906108c | 316 | |
386c036b MK |
317 | /* We provide the aliases %d0..%d30 for the floating registers as |
318 | "psuedo" registers. */ | |
319 | ||
320 | static const char *sparc32_pseudo_register_names[] = | |
321 | { | |
322 | "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", | |
323 | "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" | |
324 | }; | |
325 | ||
326 | /* Total number of pseudo registers. */ | |
327 | #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) | |
328 | ||
329 | /* Return the name of register REGNUM. */ | |
330 | ||
331 | static const char * | |
d93859e2 | 332 | sparc32_register_name (struct gdbarch *gdbarch, int regnum) |
386c036b MK |
333 | { |
334 | if (regnum >= 0 && regnum < SPARC32_NUM_REGS) | |
335 | return sparc32_register_names[regnum]; | |
336 | ||
337 | if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS) | |
338 | return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS]; | |
339 | ||
340 | return NULL; | |
341 | } | |
2d457077 | 342 | \f |
209bd28e | 343 | /* Construct types for ISA-specific registers. */ |
2d457077 | 344 | |
209bd28e UW |
345 | static struct type * |
346 | sparc_psr_type (struct gdbarch *gdbarch) | |
347 | { | |
348 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2d457077 | 349 | |
209bd28e UW |
350 | if (!tdep->sparc_psr_type) |
351 | { | |
352 | struct type *type; | |
2d457077 | 353 | |
e9bb382b | 354 | type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 4); |
209bd28e UW |
355 | append_flags_type_flag (type, 5, "ET"); |
356 | append_flags_type_flag (type, 6, "PS"); | |
357 | append_flags_type_flag (type, 7, "S"); | |
358 | append_flags_type_flag (type, 12, "EF"); | |
359 | append_flags_type_flag (type, 13, "EC"); | |
2d457077 | 360 | |
209bd28e UW |
361 | tdep->sparc_psr_type = type; |
362 | } | |
363 | ||
364 | return tdep->sparc_psr_type; | |
365 | } | |
366 | ||
367 | static struct type * | |
368 | sparc_fsr_type (struct gdbarch *gdbarch) | |
2d457077 | 369 | { |
209bd28e UW |
370 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
371 | ||
372 | if (!tdep->sparc_fsr_type) | |
373 | { | |
374 | struct type *type; | |
375 | ||
e9bb382b | 376 | type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 4); |
209bd28e UW |
377 | append_flags_type_flag (type, 0, "NXA"); |
378 | append_flags_type_flag (type, 1, "DZA"); | |
379 | append_flags_type_flag (type, 2, "UFA"); | |
380 | append_flags_type_flag (type, 3, "OFA"); | |
381 | append_flags_type_flag (type, 4, "NVA"); | |
382 | append_flags_type_flag (type, 5, "NXC"); | |
383 | append_flags_type_flag (type, 6, "DZC"); | |
384 | append_flags_type_flag (type, 7, "UFC"); | |
385 | append_flags_type_flag (type, 8, "OFC"); | |
386 | append_flags_type_flag (type, 9, "NVC"); | |
387 | append_flags_type_flag (type, 22, "NS"); | |
388 | append_flags_type_flag (type, 23, "NXM"); | |
389 | append_flags_type_flag (type, 24, "DZM"); | |
390 | append_flags_type_flag (type, 25, "UFM"); | |
391 | append_flags_type_flag (type, 26, "OFM"); | |
392 | append_flags_type_flag (type, 27, "NVM"); | |
393 | ||
394 | tdep->sparc_fsr_type = type; | |
395 | } | |
396 | ||
397 | return tdep->sparc_fsr_type; | |
2d457077 | 398 | } |
386c036b MK |
399 | |
400 | /* Return the GDB type object for the "standard" data type of data in | |
c378eb4e | 401 | register REGNUM. */ |
386c036b MK |
402 | |
403 | static struct type * | |
404 | sparc32_register_type (struct gdbarch *gdbarch, int regnum) | |
405 | { | |
406 | if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) | |
0dfff4cb | 407 | return builtin_type (gdbarch)->builtin_float; |
386c036b MK |
408 | |
409 | if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) | |
0dfff4cb | 410 | return builtin_type (gdbarch)->builtin_double; |
386c036b MK |
411 | |
412 | if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) | |
0dfff4cb | 413 | return builtin_type (gdbarch)->builtin_data_ptr; |
386c036b MK |
414 | |
415 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) | |
0dfff4cb | 416 | return builtin_type (gdbarch)->builtin_func_ptr; |
386c036b | 417 | |
2d457077 | 418 | if (regnum == SPARC32_PSR_REGNUM) |
209bd28e | 419 | return sparc_psr_type (gdbarch); |
2d457077 MK |
420 | |
421 | if (regnum == SPARC32_FSR_REGNUM) | |
209bd28e | 422 | return sparc_fsr_type (gdbarch); |
2d457077 | 423 | |
df4df182 | 424 | return builtin_type (gdbarch)->builtin_int32; |
386c036b MK |
425 | } |
426 | ||
05d1431c | 427 | static enum register_status |
386c036b MK |
428 | sparc32_pseudo_register_read (struct gdbarch *gdbarch, |
429 | struct regcache *regcache, | |
e1613aba | 430 | int regnum, gdb_byte *buf) |
386c036b | 431 | { |
05d1431c PA |
432 | enum register_status status; |
433 | ||
386c036b MK |
434 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); |
435 | ||
436 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
05d1431c PA |
437 | status = regcache_raw_read (regcache, regnum, buf); |
438 | if (status == REG_VALID) | |
439 | status = regcache_raw_read (regcache, regnum + 1, buf + 4); | |
440 | return status; | |
386c036b MK |
441 | } |
442 | ||
443 | static void | |
444 | sparc32_pseudo_register_write (struct gdbarch *gdbarch, | |
445 | struct regcache *regcache, | |
e1613aba | 446 | int regnum, const gdb_byte *buf) |
386c036b MK |
447 | { |
448 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); | |
449 | ||
450 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
451 | regcache_raw_write (regcache, regnum, buf); | |
e1613aba | 452 | regcache_raw_write (regcache, regnum + 1, buf + 4); |
386c036b MK |
453 | } |
454 | \f | |
961842b2 JM |
455 | /* Implement "in_function_epilogue_p". */ |
456 | ||
457 | int | |
458 | sparc_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
459 | { | |
460 | /* This function must return true if we are one instruction after an | |
461 | instruction that destroyed the stack frame of the current | |
462 | function. The SPARC instructions used to restore the callers | |
463 | stack frame are RESTORE and RETURN/RETT. | |
464 | ||
465 | Of these RETURN/RETT is a branch instruction and thus we return | |
466 | true if we are in its delay slot. | |
467 | ||
468 | RESTORE is almost always found in the delay slot of a branch | |
469 | instruction that transfers control to the caller, such as JMPL. | |
470 | Thus the next instruction is in the caller frame and we don't | |
471 | need to do anything about it. */ | |
472 | ||
473 | unsigned int insn = sparc_fetch_instruction (pc - 4); | |
474 | ||
475 | return X_RETTURN (insn); | |
476 | } | |
477 | \f | |
386c036b | 478 | |
49a45ecf JB |
479 | static CORE_ADDR |
480 | sparc32_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) | |
481 | { | |
482 | /* The ABI requires double-word alignment. */ | |
483 | return address & ~0x7; | |
484 | } | |
485 | ||
386c036b MK |
486 | static CORE_ADDR |
487 | sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
82585c72 | 488 | CORE_ADDR funcaddr, |
386c036b MK |
489 | struct value **args, int nargs, |
490 | struct type *value_type, | |
e4fd649a UW |
491 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, |
492 | struct regcache *regcache) | |
c906108c | 493 | { |
e17a4113 UW |
494 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
495 | ||
386c036b MK |
496 | *bp_addr = sp - 4; |
497 | *real_pc = funcaddr; | |
498 | ||
d80b854b | 499 | if (using_struct_return (gdbarch, NULL, value_type)) |
c906108c | 500 | { |
e1613aba | 501 | gdb_byte buf[4]; |
386c036b MK |
502 | |
503 | /* This is an UNIMP instruction. */ | |
e17a4113 UW |
504 | store_unsigned_integer (buf, 4, byte_order, |
505 | TYPE_LENGTH (value_type) & 0x1fff); | |
386c036b MK |
506 | write_memory (sp - 8, buf, 4); |
507 | return sp - 8; | |
c906108c SS |
508 | } |
509 | ||
386c036b MK |
510 | return sp - 4; |
511 | } | |
512 | ||
513 | static CORE_ADDR | |
514 | sparc32_store_arguments (struct regcache *regcache, int nargs, | |
515 | struct value **args, CORE_ADDR sp, | |
516 | int struct_return, CORE_ADDR struct_addr) | |
517 | { | |
df4df182 | 518 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
e17a4113 | 519 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
386c036b MK |
520 | /* Number of words in the "parameter array". */ |
521 | int num_elements = 0; | |
522 | int element = 0; | |
523 | int i; | |
524 | ||
525 | for (i = 0; i < nargs; i++) | |
c906108c | 526 | { |
4991999e | 527 | struct type *type = value_type (args[i]); |
386c036b MK |
528 | int len = TYPE_LENGTH (type); |
529 | ||
530 | if (sparc_structure_or_union_p (type) | |
fe10a582 DM |
531 | || (sparc_floating_p (type) && len == 16) |
532 | || sparc_complex_floating_p (type)) | |
c906108c | 533 | { |
386c036b MK |
534 | /* Structure, Union and Quad-Precision Arguments. */ |
535 | sp -= len; | |
536 | ||
537 | /* Use doubleword alignment for these values. That's always | |
538 | correct, and wasting a few bytes shouldn't be a problem. */ | |
539 | sp &= ~0x7; | |
540 | ||
0fd88904 | 541 | write_memory (sp, value_contents (args[i]), len); |
386c036b MK |
542 | args[i] = value_from_pointer (lookup_pointer_type (type), sp); |
543 | num_elements++; | |
544 | } | |
545 | else if (sparc_floating_p (type)) | |
546 | { | |
547 | /* Floating arguments. */ | |
548 | gdb_assert (len == 4 || len == 8); | |
549 | num_elements += (len / 4); | |
c906108c | 550 | } |
c5aa993b JM |
551 | else |
552 | { | |
386c036b MK |
553 | /* Integral and pointer arguments. */ |
554 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
555 | ||
556 | if (len < 4) | |
df4df182 UW |
557 | args[i] = value_cast (builtin_type (gdbarch)->builtin_int32, |
558 | args[i]); | |
386c036b | 559 | num_elements += ((len + 3) / 4); |
c5aa993b | 560 | } |
c906108c | 561 | } |
c906108c | 562 | |
386c036b MK |
563 | /* Always allocate at least six words. */ |
564 | sp -= max (6, num_elements) * 4; | |
c906108c | 565 | |
386c036b MK |
566 | /* The psABI says that "Software convention requires space for the |
567 | struct/union return value pointer, even if the word is unused." */ | |
568 | sp -= 4; | |
c906108c | 569 | |
386c036b MK |
570 | /* The psABI says that "Although software convention and the |
571 | operating system require every stack frame to be doubleword | |
572 | aligned." */ | |
573 | sp &= ~0x7; | |
c906108c | 574 | |
386c036b | 575 | for (i = 0; i < nargs; i++) |
c906108c | 576 | { |
0fd88904 | 577 | const bfd_byte *valbuf = value_contents (args[i]); |
4991999e | 578 | struct type *type = value_type (args[i]); |
386c036b | 579 | int len = TYPE_LENGTH (type); |
c906108c | 580 | |
386c036b | 581 | gdb_assert (len == 4 || len == 8); |
c906108c | 582 | |
386c036b MK |
583 | if (element < 6) |
584 | { | |
585 | int regnum = SPARC_O0_REGNUM + element; | |
c906108c | 586 | |
386c036b MK |
587 | regcache_cooked_write (regcache, regnum, valbuf); |
588 | if (len > 4 && element < 5) | |
589 | regcache_cooked_write (regcache, regnum + 1, valbuf + 4); | |
590 | } | |
5af923b0 | 591 | |
386c036b MK |
592 | /* Always store the argument in memory. */ |
593 | write_memory (sp + 4 + element * 4, valbuf, len); | |
594 | element += len / 4; | |
595 | } | |
c906108c | 596 | |
386c036b | 597 | gdb_assert (element == num_elements); |
c906108c | 598 | |
386c036b | 599 | if (struct_return) |
c906108c | 600 | { |
e1613aba | 601 | gdb_byte buf[4]; |
c906108c | 602 | |
e17a4113 | 603 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
386c036b MK |
604 | write_memory (sp, buf, 4); |
605 | } | |
c906108c | 606 | |
386c036b | 607 | return sp; |
c906108c SS |
608 | } |
609 | ||
386c036b | 610 | static CORE_ADDR |
7d9b040b | 611 | sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
386c036b MK |
612 | struct regcache *regcache, CORE_ADDR bp_addr, |
613 | int nargs, struct value **args, CORE_ADDR sp, | |
614 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 615 | { |
386c036b MK |
616 | CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8)); |
617 | ||
618 | /* Set return address. */ | |
619 | regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); | |
620 | ||
621 | /* Set up function arguments. */ | |
622 | sp = sparc32_store_arguments (regcache, nargs, args, sp, | |
623 | struct_return, struct_addr); | |
624 | ||
625 | /* Allocate the 16-word window save area. */ | |
626 | sp -= 16 * 4; | |
c906108c | 627 | |
386c036b MK |
628 | /* Stack should be doubleword aligned at this point. */ |
629 | gdb_assert (sp % 8 == 0); | |
c906108c | 630 | |
386c036b MK |
631 | /* Finally, update the stack pointer. */ |
632 | regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); | |
633 | ||
634 | return sp; | |
635 | } | |
636 | \f | |
c906108c | 637 | |
386c036b MK |
638 | /* Use the program counter to determine the contents and size of a |
639 | breakpoint instruction. Return a pointer to a string of bytes that | |
640 | encode a breakpoint instruction, store the length of the string in | |
641 | *LEN and optionally adjust *PC to point to the correct memory | |
642 | location for inserting the breakpoint. */ | |
643 | ||
e1613aba | 644 | static const gdb_byte * |
67d57894 | 645 | sparc_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
386c036b | 646 | { |
864a1a37 | 647 | static const gdb_byte break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; |
c5aa993b | 648 | |
386c036b MK |
649 | *len = sizeof (break_insn); |
650 | return break_insn; | |
c906108c | 651 | } |
386c036b | 652 | \f |
c906108c | 653 | |
386c036b | 654 | /* Allocate and initialize a frame cache. */ |
c906108c | 655 | |
386c036b MK |
656 | static struct sparc_frame_cache * |
657 | sparc_alloc_frame_cache (void) | |
658 | { | |
659 | struct sparc_frame_cache *cache; | |
c906108c | 660 | |
386c036b | 661 | cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); |
c906108c | 662 | |
386c036b MK |
663 | /* Base address. */ |
664 | cache->base = 0; | |
665 | cache->pc = 0; | |
c906108c | 666 | |
386c036b MK |
667 | /* Frameless until proven otherwise. */ |
668 | cache->frameless_p = 1; | |
369c397b JB |
669 | cache->frame_offset = 0; |
670 | cache->saved_regs_mask = 0; | |
671 | cache->copied_regs_mask = 0; | |
386c036b MK |
672 | cache->struct_return_p = 0; |
673 | ||
674 | return cache; | |
675 | } | |
676 | ||
b0b92586 JB |
677 | /* GCC generates several well-known sequences of instructions at the begining |
678 | of each function prologue when compiling with -fstack-check. If one of | |
679 | such sequences starts at START_PC, then return the address of the | |
680 | instruction immediately past this sequence. Otherwise, return START_PC. */ | |
681 | ||
682 | static CORE_ADDR | |
683 | sparc_skip_stack_check (const CORE_ADDR start_pc) | |
684 | { | |
685 | CORE_ADDR pc = start_pc; | |
686 | unsigned long insn; | |
687 | int offset_stack_checking_sequence = 0; | |
2067c8d4 | 688 | int probing_loop = 0; |
b0b92586 JB |
689 | |
690 | /* With GCC, all stack checking sequences begin with the same two | |
2067c8d4 | 691 | instructions, plus an optional one in the case of a probing loop: |
b0b92586 | 692 | |
2067c8d4 JG |
693 | sethi <some immediate>, %g1 |
694 | sub %sp, %g1, %g1 | |
695 | ||
696 | or: | |
697 | ||
698 | sethi <some immediate>, %g1 | |
699 | sethi <some immediate>, %g4 | |
700 | sub %sp, %g1, %g1 | |
701 | ||
702 | or: | |
703 | ||
704 | sethi <some immediate>, %g1 | |
705 | sub %sp, %g1, %g1 | |
706 | sethi <some immediate>, %g4 | |
707 | ||
708 | If the optional instruction is found (setting g4), assume that a | |
709 | probing loop will follow. */ | |
710 | ||
711 | /* sethi <some immediate>, %g1 */ | |
b0b92586 JB |
712 | insn = sparc_fetch_instruction (pc); |
713 | pc = pc + 4; | |
714 | if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1)) | |
715 | return start_pc; | |
716 | ||
2067c8d4 | 717 | /* optional: sethi <some immediate>, %g4 */ |
b0b92586 JB |
718 | insn = sparc_fetch_instruction (pc); |
719 | pc = pc + 4; | |
2067c8d4 JG |
720 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) |
721 | { | |
722 | probing_loop = 1; | |
723 | insn = sparc_fetch_instruction (pc); | |
724 | pc = pc + 4; | |
725 | } | |
726 | ||
727 | /* sub %sp, %g1, %g1 */ | |
b0b92586 JB |
728 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) |
729 | && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1)) | |
730 | return start_pc; | |
731 | ||
732 | insn = sparc_fetch_instruction (pc); | |
733 | pc = pc + 4; | |
734 | ||
2067c8d4 JG |
735 | /* optional: sethi <some immediate>, %g4 */ |
736 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) | |
737 | { | |
738 | probing_loop = 1; | |
739 | insn = sparc_fetch_instruction (pc); | |
740 | pc = pc + 4; | |
741 | } | |
742 | ||
b0b92586 JB |
743 | /* First possible sequence: |
744 | [first two instructions above] | |
745 | clr [%g1 - some immediate] */ | |
746 | ||
747 | /* clr [%g1 - some immediate] */ | |
748 | if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
749 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
750 | { | |
751 | /* Valid stack-check sequence, return the new PC. */ | |
752 | return pc; | |
753 | } | |
754 | ||
755 | /* Second possible sequence: A small number of probes. | |
756 | [first two instructions above] | |
757 | clr [%g1] | |
758 | add %g1, -<some immediate>, %g1 | |
759 | clr [%g1] | |
760 | [repeat the two instructions above any (small) number of times] | |
761 | clr [%g1 - some immediate] */ | |
762 | ||
763 | /* clr [%g1] */ | |
764 | else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
765 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
766 | { | |
767 | while (1) | |
768 | { | |
769 | /* add %g1, -<some immediate>, %g1 */ | |
770 | insn = sparc_fetch_instruction (pc); | |
771 | pc = pc + 4; | |
772 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
773 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
774 | break; | |
775 | ||
776 | /* clr [%g1] */ | |
777 | insn = sparc_fetch_instruction (pc); | |
778 | pc = pc + 4; | |
779 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
780 | && X_RD (insn) == 0 && X_RS1 (insn) == 1)) | |
781 | return start_pc; | |
782 | } | |
783 | ||
784 | /* clr [%g1 - some immediate] */ | |
785 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
786 | && X_RS1 (insn) == 1 && X_RD (insn) == 0)) | |
787 | return start_pc; | |
788 | ||
789 | /* We found a valid stack-check sequence, return the new PC. */ | |
790 | return pc; | |
791 | } | |
792 | ||
793 | /* Third sequence: A probing loop. | |
2067c8d4 | 794 | [first three instructions above] |
b0b92586 JB |
795 | sub %g1, %g4, %g4 |
796 | cmp %g1, %g4 | |
797 | be <disp> | |
798 | add %g1, -<some immediate>, %g1 | |
799 | ba <disp> | |
800 | clr [%g1] | |
2067c8d4 JG |
801 | |
802 | And an optional last probe for the remainder: | |
803 | ||
b0b92586 JB |
804 | clr [%g4 - some immediate] */ |
805 | ||
2067c8d4 | 806 | if (probing_loop) |
b0b92586 JB |
807 | { |
808 | /* sub %g1, %g4, %g4 */ | |
b0b92586 JB |
809 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) |
810 | && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
811 | return start_pc; | |
812 | ||
813 | /* cmp %g1, %g4 */ | |
814 | insn = sparc_fetch_instruction (pc); | |
815 | pc = pc + 4; | |
816 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn) | |
817 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
818 | return start_pc; | |
819 | ||
820 | /* be <disp> */ | |
821 | insn = sparc_fetch_instruction (pc); | |
822 | pc = pc + 4; | |
823 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1)) | |
824 | return start_pc; | |
825 | ||
826 | /* add %g1, -<some immediate>, %g1 */ | |
827 | insn = sparc_fetch_instruction (pc); | |
828 | pc = pc + 4; | |
829 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
830 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
831 | return start_pc; | |
832 | ||
833 | /* ba <disp> */ | |
834 | insn = sparc_fetch_instruction (pc); | |
835 | pc = pc + 4; | |
836 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8)) | |
837 | return start_pc; | |
838 | ||
2067c8d4 | 839 | /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */ |
b0b92586 JB |
840 | insn = sparc_fetch_instruction (pc); |
841 | pc = pc + 4; | |
2067c8d4 JG |
842 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 |
843 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 | |
844 | && (!X_I(insn) || X_SIMM13 (insn) == 0))) | |
b0b92586 JB |
845 | return start_pc; |
846 | ||
2067c8d4 JG |
847 | /* We found a valid stack-check sequence, return the new PC. */ |
848 | ||
849 | /* optional: clr [%g4 - some immediate] */ | |
b0b92586 JB |
850 | insn = sparc_fetch_instruction (pc); |
851 | pc = pc + 4; | |
852 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
853 | && X_RS1 (insn) == 4 && X_RD (insn) == 0)) | |
2067c8d4 JG |
854 | return pc - 4; |
855 | else | |
856 | return pc; | |
b0b92586 JB |
857 | } |
858 | ||
859 | /* No stack check code in our prologue, return the start_pc. */ | |
860 | return start_pc; | |
861 | } | |
862 | ||
369c397b JB |
863 | /* Record the effect of a SAVE instruction on CACHE. */ |
864 | ||
865 | void | |
866 | sparc_record_save_insn (struct sparc_frame_cache *cache) | |
867 | { | |
868 | /* The frame is set up. */ | |
869 | cache->frameless_p = 0; | |
870 | ||
871 | /* The frame pointer contains the CFA. */ | |
872 | cache->frame_offset = 0; | |
873 | ||
874 | /* The `local' and `in' registers are all saved. */ | |
875 | cache->saved_regs_mask = 0xffff; | |
876 | ||
877 | /* The `out' registers are all renamed. */ | |
878 | cache->copied_regs_mask = 0xff; | |
879 | } | |
880 | ||
881 | /* Do a full analysis of the prologue at PC and update CACHE accordingly. | |
882 | Bail out early if CURRENT_PC is reached. Return the address where | |
883 | the analysis stopped. | |
884 | ||
885 | We handle both the traditional register window model and the single | |
886 | register window (aka flat) model. */ | |
887 | ||
386c036b | 888 | CORE_ADDR |
be8626e0 MD |
889 | sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, |
890 | CORE_ADDR current_pc, struct sparc_frame_cache *cache) | |
c906108c | 891 | { |
be8626e0 | 892 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
386c036b MK |
893 | unsigned long insn; |
894 | int offset = 0; | |
c906108c | 895 | int dest = -1; |
c906108c | 896 | |
b0b92586 JB |
897 | pc = sparc_skip_stack_check (pc); |
898 | ||
386c036b MK |
899 | if (current_pc <= pc) |
900 | return current_pc; | |
901 | ||
902 | /* We have to handle to "Procedure Linkage Table" (PLT) special. On | |
903 | SPARC the linker usually defines a symbol (typically | |
904 | _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. | |
905 | This symbol makes us end up here with PC pointing at the start of | |
906 | the PLT and CURRENT_PC probably pointing at a PLT entry. If we | |
907 | would do our normal prologue analysis, we would probably conclude | |
908 | that we've got a frame when in reality we don't, since the | |
909 | dynamic linker patches up the first PLT with some code that | |
910 | starts with a SAVE instruction. Patch up PC such that it points | |
911 | at the start of our PLT entry. */ | |
3e5d3a5a | 912 | if (tdep->plt_entry_size > 0 && in_plt_section (current_pc)) |
386c036b | 913 | pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); |
c906108c | 914 | |
386c036b MK |
915 | insn = sparc_fetch_instruction (pc); |
916 | ||
369c397b JB |
917 | /* Recognize store insns and record their sources. */ |
918 | while (X_OP (insn) == 3 | |
919 | && (X_OP3 (insn) == 0x4 /* stw */ | |
920 | || X_OP3 (insn) == 0x7 /* std */ | |
921 | || X_OP3 (insn) == 0xe) /* stx */ | |
922 | && X_RS1 (insn) == SPARC_SP_REGNUM) | |
923 | { | |
924 | int regnum = X_RD (insn); | |
925 | ||
926 | /* Recognize stores into the corresponding stack slots. */ | |
927 | if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM | |
928 | && ((X_I (insn) | |
929 | && X_SIMM13 (insn) == (X_OP3 (insn) == 0xe | |
930 | ? (regnum - SPARC_L0_REGNUM) * 8 + BIAS | |
931 | : (regnum - SPARC_L0_REGNUM) * 4)) | |
932 | || (!X_I (insn) && regnum == SPARC_L0_REGNUM))) | |
933 | { | |
934 | cache->saved_regs_mask |= (1 << (regnum - SPARC_L0_REGNUM)); | |
935 | if (X_OP3 (insn) == 0x7) | |
936 | cache->saved_regs_mask |= (1 << (regnum + 1 - SPARC_L0_REGNUM)); | |
937 | } | |
938 | ||
939 | offset += 4; | |
940 | ||
941 | insn = sparc_fetch_instruction (pc + offset); | |
942 | } | |
943 | ||
386c036b MK |
944 | /* Recognize a SETHI insn and record its destination. */ |
945 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) | |
c906108c SS |
946 | { |
947 | dest = X_RD (insn); | |
386c036b MK |
948 | offset += 4; |
949 | ||
369c397b | 950 | insn = sparc_fetch_instruction (pc + offset); |
c906108c SS |
951 | } |
952 | ||
386c036b MK |
953 | /* Allow for an arithmetic operation on DEST or %g1. */ |
954 | if (X_OP (insn) == 2 && X_I (insn) | |
c906108c SS |
955 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) |
956 | { | |
386c036b | 957 | offset += 4; |
c906108c | 958 | |
369c397b | 959 | insn = sparc_fetch_instruction (pc + offset); |
c906108c | 960 | } |
c906108c | 961 | |
386c036b MK |
962 | /* Check for the SAVE instruction that sets up the frame. */ |
963 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) | |
c906108c | 964 | { |
369c397b JB |
965 | sparc_record_save_insn (cache); |
966 | offset += 4; | |
967 | return pc + offset; | |
968 | } | |
969 | ||
970 | /* Check for an arithmetic operation on %sp. */ | |
971 | if (X_OP (insn) == 2 | |
972 | && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) | |
973 | && X_RS1 (insn) == SPARC_SP_REGNUM | |
974 | && X_RD (insn) == SPARC_SP_REGNUM) | |
975 | { | |
976 | if (X_I (insn)) | |
977 | { | |
978 | cache->frame_offset = X_SIMM13 (insn); | |
979 | if (X_OP3 (insn) == 0) | |
980 | cache->frame_offset = -cache->frame_offset; | |
981 | } | |
982 | offset += 4; | |
983 | ||
984 | insn = sparc_fetch_instruction (pc + offset); | |
985 | ||
986 | /* Check for an arithmetic operation that sets up the frame. */ | |
987 | if (X_OP (insn) == 2 | |
988 | && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) | |
989 | && X_RS1 (insn) == SPARC_SP_REGNUM | |
990 | && X_RD (insn) == SPARC_FP_REGNUM) | |
991 | { | |
992 | cache->frameless_p = 0; | |
993 | cache->frame_offset = 0; | |
994 | /* We could check that the amount subtracted to %sp above is the | |
995 | same as the one added here, but this seems superfluous. */ | |
996 | cache->copied_regs_mask |= 0x40; | |
997 | offset += 4; | |
998 | ||
999 | insn = sparc_fetch_instruction (pc + offset); | |
1000 | } | |
1001 | ||
1002 | /* Check for a move (or) operation that copies the return register. */ | |
1003 | if (X_OP (insn) == 2 | |
1004 | && X_OP3 (insn) == 0x2 | |
1005 | && !X_I (insn) | |
1006 | && X_RS1 (insn) == SPARC_G0_REGNUM | |
1007 | && X_RS2 (insn) == SPARC_O7_REGNUM | |
1008 | && X_RD (insn) == SPARC_I7_REGNUM) | |
1009 | { | |
1010 | cache->copied_regs_mask |= 0x80; | |
1011 | offset += 4; | |
1012 | } | |
1013 | ||
1014 | return pc + offset; | |
c906108c SS |
1015 | } |
1016 | ||
1017 | return pc; | |
1018 | } | |
1019 | ||
386c036b | 1020 | static CORE_ADDR |
236369e7 | 1021 | sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) |
386c036b MK |
1022 | { |
1023 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
236369e7 | 1024 | return frame_unwind_register_unsigned (this_frame, tdep->pc_regnum); |
386c036b MK |
1025 | } |
1026 | ||
1027 | /* Return PC of first real instruction of the function starting at | |
1028 | START_PC. */ | |
f510d44e | 1029 | |
386c036b | 1030 | static CORE_ADDR |
6093d2eb | 1031 | sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1032 | { |
f510d44e DM |
1033 | struct symtab_and_line sal; |
1034 | CORE_ADDR func_start, func_end; | |
386c036b | 1035 | struct sparc_frame_cache cache; |
f510d44e DM |
1036 | |
1037 | /* This is the preferred method, find the end of the prologue by | |
1038 | using the debugging information. */ | |
1039 | if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) | |
1040 | { | |
1041 | sal = find_pc_line (func_start, 0); | |
1042 | ||
1043 | if (sal.end < func_end | |
1044 | && start_pc <= sal.end) | |
1045 | return sal.end; | |
1046 | } | |
1047 | ||
be8626e0 | 1048 | start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache); |
075ccec8 MK |
1049 | |
1050 | /* The psABI says that "Although the first 6 words of arguments | |
1051 | reside in registers, the standard stack frame reserves space for | |
1052 | them.". It also suggests that a function may use that space to | |
1053 | "write incoming arguments 0 to 5" into that space, and that's | |
1054 | indeed what GCC seems to be doing. In that case GCC will | |
1055 | generate debug information that points to the stack slots instead | |
1056 | of the registers, so we should consider the instructions that | |
369c397b | 1057 | write out these incoming arguments onto the stack. */ |
075ccec8 | 1058 | |
369c397b | 1059 | while (1) |
075ccec8 MK |
1060 | { |
1061 | unsigned long insn = sparc_fetch_instruction (start_pc); | |
1062 | ||
369c397b JB |
1063 | /* Recognize instructions that store incoming arguments into the |
1064 | corresponding stack slots. */ | |
1065 | if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 | |
1066 | && X_I (insn) && X_RS1 (insn) == SPARC_FP_REGNUM) | |
075ccec8 | 1067 | { |
369c397b JB |
1068 | int regnum = X_RD (insn); |
1069 | ||
1070 | /* Case of arguments still in %o[0..5]. */ | |
1071 | if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O5_REGNUM | |
1072 | && !(cache.copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM))) | |
1073 | && X_SIMM13 (insn) == 68 + (regnum - SPARC_O0_REGNUM) * 4) | |
1074 | { | |
1075 | start_pc += 4; | |
1076 | continue; | |
1077 | } | |
1078 | ||
1079 | /* Case of arguments copied into %i[0..5]. */ | |
1080 | if (regnum >= SPARC_I0_REGNUM && regnum <= SPARC_I5_REGNUM | |
1081 | && (cache.copied_regs_mask & (1 << (regnum - SPARC_I0_REGNUM))) | |
1082 | && X_SIMM13 (insn) == 68 + (regnum - SPARC_I0_REGNUM) * 4) | |
1083 | { | |
1084 | start_pc += 4; | |
1085 | continue; | |
1086 | } | |
075ccec8 MK |
1087 | } |
1088 | ||
1089 | break; | |
1090 | } | |
1091 | ||
1092 | return start_pc; | |
c906108c SS |
1093 | } |
1094 | ||
386c036b | 1095 | /* Normal frames. */ |
9319a2fe | 1096 | |
386c036b | 1097 | struct sparc_frame_cache * |
236369e7 | 1098 | sparc_frame_cache (struct frame_info *this_frame, void **this_cache) |
9319a2fe | 1099 | { |
386c036b | 1100 | struct sparc_frame_cache *cache; |
9319a2fe | 1101 | |
386c036b MK |
1102 | if (*this_cache) |
1103 | return *this_cache; | |
c906108c | 1104 | |
386c036b MK |
1105 | cache = sparc_alloc_frame_cache (); |
1106 | *this_cache = cache; | |
c906108c | 1107 | |
236369e7 | 1108 | cache->pc = get_frame_func (this_frame); |
386c036b | 1109 | if (cache->pc != 0) |
236369e7 JB |
1110 | sparc_analyze_prologue (get_frame_arch (this_frame), cache->pc, |
1111 | get_frame_pc (this_frame), cache); | |
386c036b MK |
1112 | |
1113 | if (cache->frameless_p) | |
c906108c | 1114 | { |
cbeae229 MK |
1115 | /* This function is frameless, so %fp (%i6) holds the frame |
1116 | pointer for our calling frame. Use %sp (%o6) as this frame's | |
1117 | base address. */ | |
1118 | cache->base = | |
236369e7 | 1119 | get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
cbeae229 MK |
1120 | } |
1121 | else | |
1122 | { | |
1123 | /* For normal frames, %fp (%i6) holds the frame pointer, the | |
1124 | base address for the current stack frame. */ | |
1125 | cache->base = | |
236369e7 | 1126 | get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM); |
c906108c | 1127 | } |
c906108c | 1128 | |
369c397b JB |
1129 | cache->base += cache->frame_offset; |
1130 | ||
5b2d44a0 MK |
1131 | if (cache->base & 1) |
1132 | cache->base += BIAS; | |
1133 | ||
386c036b | 1134 | return cache; |
c906108c | 1135 | } |
c906108c | 1136 | |
aff37fc1 DM |
1137 | static int |
1138 | sparc32_struct_return_from_sym (struct symbol *sym) | |
1139 | { | |
1140 | struct type *type = check_typedef (SYMBOL_TYPE (sym)); | |
1141 | enum type_code code = TYPE_CODE (type); | |
1142 | ||
1143 | if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) | |
1144 | { | |
1145 | type = check_typedef (TYPE_TARGET_TYPE (type)); | |
1146 | if (sparc_structure_or_union_p (type) | |
1147 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
1148 | return 1; | |
1149 | } | |
1150 | ||
1151 | return 0; | |
1152 | } | |
1153 | ||
386c036b | 1154 | struct sparc_frame_cache * |
236369e7 | 1155 | sparc32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 1156 | { |
386c036b MK |
1157 | struct sparc_frame_cache *cache; |
1158 | struct symbol *sym; | |
c906108c | 1159 | |
386c036b MK |
1160 | if (*this_cache) |
1161 | return *this_cache; | |
c906108c | 1162 | |
236369e7 | 1163 | cache = sparc_frame_cache (this_frame, this_cache); |
c906108c | 1164 | |
386c036b MK |
1165 | sym = find_pc_function (cache->pc); |
1166 | if (sym) | |
c906108c | 1167 | { |
aff37fc1 | 1168 | cache->struct_return_p = sparc32_struct_return_from_sym (sym); |
c906108c | 1169 | } |
5465445a JB |
1170 | else |
1171 | { | |
1172 | /* There is no debugging information for this function to | |
1173 | help us determine whether this function returns a struct | |
1174 | or not. So we rely on another heuristic which is to check | |
1175 | the instruction at the return address and see if this is | |
1176 | an "unimp" instruction. If it is, then it is a struct-return | |
1177 | function. */ | |
1178 | CORE_ADDR pc; | |
369c397b JB |
1179 | int regnum = |
1180 | (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; | |
5465445a | 1181 | |
236369e7 | 1182 | pc = get_frame_register_unsigned (this_frame, regnum) + 8; |
5465445a JB |
1183 | if (sparc_is_unimp_insn (pc)) |
1184 | cache->struct_return_p = 1; | |
1185 | } | |
c906108c | 1186 | |
386c036b MK |
1187 | return cache; |
1188 | } | |
1189 | ||
1190 | static void | |
236369e7 | 1191 | sparc32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
386c036b MK |
1192 | struct frame_id *this_id) |
1193 | { | |
1194 | struct sparc_frame_cache *cache = | |
236369e7 | 1195 | sparc32_frame_cache (this_frame, this_cache); |
386c036b MK |
1196 | |
1197 | /* This marks the outermost frame. */ | |
1198 | if (cache->base == 0) | |
1199 | return; | |
1200 | ||
1201 | (*this_id) = frame_id_build (cache->base, cache->pc); | |
1202 | } | |
c906108c | 1203 | |
236369e7 JB |
1204 | static struct value * |
1205 | sparc32_frame_prev_register (struct frame_info *this_frame, | |
1206 | void **this_cache, int regnum) | |
386c036b | 1207 | { |
e17a4113 | 1208 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
386c036b | 1209 | struct sparc_frame_cache *cache = |
236369e7 | 1210 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 1211 | |
386c036b | 1212 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) |
c906108c | 1213 | { |
236369e7 | 1214 | CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; |
386c036b | 1215 | |
236369e7 JB |
1216 | /* If this functions has a Structure, Union or Quad-Precision |
1217 | return value, we have to skip the UNIMP instruction that encodes | |
1218 | the size of the structure. */ | |
1219 | if (cache->struct_return_p) | |
1220 | pc += 4; | |
386c036b | 1221 | |
369c397b JB |
1222 | regnum = |
1223 | (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; | |
236369e7 JB |
1224 | pc += get_frame_register_unsigned (this_frame, regnum) + 8; |
1225 | return frame_unwind_got_constant (this_frame, regnum, pc); | |
c906108c SS |
1226 | } |
1227 | ||
42cdca6c MK |
1228 | /* Handle StackGhost. */ |
1229 | { | |
e17a4113 | 1230 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
42cdca6c MK |
1231 | |
1232 | if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM) | |
1233 | { | |
236369e7 JB |
1234 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
1235 | ULONGEST i7; | |
1236 | ||
1237 | /* Read the value in from memory. */ | |
1238 | i7 = get_frame_memory_unsigned (this_frame, addr, 4); | |
1239 | return frame_unwind_got_constant (this_frame, regnum, i7 ^ wcookie); | |
42cdca6c MK |
1240 | } |
1241 | } | |
1242 | ||
369c397b | 1243 | /* The previous frame's `local' and `in' registers may have been saved |
386c036b | 1244 | in the register save area. */ |
369c397b JB |
1245 | if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM |
1246 | && (cache->saved_regs_mask & (1 << (regnum - SPARC_L0_REGNUM)))) | |
c906108c | 1247 | { |
236369e7 | 1248 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
386c036b | 1249 | |
236369e7 | 1250 | return frame_unwind_got_memory (this_frame, regnum, addr); |
386c036b | 1251 | } |
c906108c | 1252 | |
369c397b JB |
1253 | /* The previous frame's `out' registers may be accessible as the current |
1254 | frame's `in' registers. */ | |
1255 | if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM | |
1256 | && (cache->copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM)))) | |
386c036b | 1257 | regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); |
5af923b0 | 1258 | |
236369e7 | 1259 | return frame_unwind_got_register (this_frame, regnum, regnum); |
386c036b | 1260 | } |
c906108c | 1261 | |
386c036b MK |
1262 | static const struct frame_unwind sparc32_frame_unwind = |
1263 | { | |
1264 | NORMAL_FRAME, | |
8fbca658 | 1265 | default_frame_unwind_stop_reason, |
386c036b | 1266 | sparc32_frame_this_id, |
236369e7 JB |
1267 | sparc32_frame_prev_register, |
1268 | NULL, | |
1269 | default_frame_sniffer | |
386c036b | 1270 | }; |
386c036b | 1271 | \f |
c906108c | 1272 | |
386c036b | 1273 | static CORE_ADDR |
236369e7 | 1274 | sparc32_frame_base_address (struct frame_info *this_frame, void **this_cache) |
386c036b MK |
1275 | { |
1276 | struct sparc_frame_cache *cache = | |
236369e7 | 1277 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 1278 | |
386c036b MK |
1279 | return cache->base; |
1280 | } | |
c906108c | 1281 | |
386c036b MK |
1282 | static const struct frame_base sparc32_frame_base = |
1283 | { | |
1284 | &sparc32_frame_unwind, | |
1285 | sparc32_frame_base_address, | |
1286 | sparc32_frame_base_address, | |
1287 | sparc32_frame_base_address | |
1288 | }; | |
c906108c | 1289 | |
386c036b | 1290 | static struct frame_id |
236369e7 | 1291 | sparc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
386c036b MK |
1292 | { |
1293 | CORE_ADDR sp; | |
5af923b0 | 1294 | |
236369e7 | 1295 | sp = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
5b2d44a0 MK |
1296 | if (sp & 1) |
1297 | sp += BIAS; | |
236369e7 | 1298 | return frame_id_build (sp, get_frame_pc (this_frame)); |
386c036b MK |
1299 | } |
1300 | \f | |
c906108c | 1301 | |
3923a2b2 MK |
1302 | /* Extract a function return value of TYPE from REGCACHE, and copy |
1303 | that into VALBUF. */ | |
5af923b0 | 1304 | |
386c036b MK |
1305 | static void |
1306 | sparc32_extract_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1307 | gdb_byte *valbuf) |
386c036b MK |
1308 | { |
1309 | int len = TYPE_LENGTH (type); | |
fe10a582 | 1310 | gdb_byte buf[32]; |
c906108c | 1311 | |
386c036b MK |
1312 | gdb_assert (!sparc_structure_or_union_p (type)); |
1313 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 1314 | |
fe10a582 | 1315 | if (sparc_floating_p (type) || sparc_complex_floating_p (type)) |
5af923b0 | 1316 | { |
386c036b MK |
1317 | /* Floating return values. */ |
1318 | regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf); | |
1319 | if (len > 4) | |
1320 | regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4); | |
fe10a582 DM |
1321 | if (len > 8) |
1322 | { | |
1323 | regcache_cooked_read (regcache, SPARC_F2_REGNUM, buf + 8); | |
1324 | regcache_cooked_read (regcache, SPARC_F3_REGNUM, buf + 12); | |
1325 | } | |
1326 | if (len > 16) | |
1327 | { | |
1328 | regcache_cooked_read (regcache, SPARC_F4_REGNUM, buf + 16); | |
1329 | regcache_cooked_read (regcache, SPARC_F5_REGNUM, buf + 20); | |
1330 | regcache_cooked_read (regcache, SPARC_F6_REGNUM, buf + 24); | |
1331 | regcache_cooked_read (regcache, SPARC_F7_REGNUM, buf + 28); | |
1332 | } | |
386c036b | 1333 | memcpy (valbuf, buf, len); |
5af923b0 MS |
1334 | } |
1335 | else | |
1336 | { | |
386c036b MK |
1337 | /* Integral and pointer return values. */ |
1338 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
c906108c | 1339 | |
386c036b MK |
1340 | regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); |
1341 | if (len > 4) | |
1342 | { | |
1343 | regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4); | |
1344 | gdb_assert (len == 8); | |
1345 | memcpy (valbuf, buf, 8); | |
1346 | } | |
1347 | else | |
1348 | { | |
1349 | /* Just stripping off any unused bytes should preserve the | |
1350 | signed-ness just fine. */ | |
1351 | memcpy (valbuf, buf + 4 - len, len); | |
1352 | } | |
1353 | } | |
1354 | } | |
c906108c | 1355 | |
3923a2b2 MK |
1356 | /* Store the function return value of type TYPE from VALBUF into |
1357 | REGCACHE. */ | |
c906108c | 1358 | |
386c036b MK |
1359 | static void |
1360 | sparc32_store_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1361 | const gdb_byte *valbuf) |
386c036b MK |
1362 | { |
1363 | int len = TYPE_LENGTH (type); | |
e1613aba | 1364 | gdb_byte buf[8]; |
c906108c | 1365 | |
386c036b MK |
1366 | gdb_assert (!sparc_structure_or_union_p (type)); |
1367 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
a9789a6b | 1368 | gdb_assert (len <= 8); |
c906108c | 1369 | |
fe10a582 | 1370 | if (sparc_floating_p (type) || sparc_complex_floating_p (type)) |
386c036b MK |
1371 | { |
1372 | /* Floating return values. */ | |
1373 | memcpy (buf, valbuf, len); | |
1374 | regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf); | |
1375 | if (len > 4) | |
1376 | regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4); | |
fe10a582 DM |
1377 | if (len > 8) |
1378 | { | |
1379 | regcache_cooked_write (regcache, SPARC_F2_REGNUM, buf + 8); | |
1380 | regcache_cooked_write (regcache, SPARC_F3_REGNUM, buf + 12); | |
1381 | } | |
1382 | if (len > 16) | |
1383 | { | |
1384 | regcache_cooked_write (regcache, SPARC_F4_REGNUM, buf + 16); | |
1385 | regcache_cooked_write (regcache, SPARC_F5_REGNUM, buf + 20); | |
1386 | regcache_cooked_write (regcache, SPARC_F6_REGNUM, buf + 24); | |
1387 | regcache_cooked_write (regcache, SPARC_F7_REGNUM, buf + 28); | |
1388 | } | |
386c036b MK |
1389 | } |
1390 | else | |
c906108c | 1391 | { |
386c036b MK |
1392 | /* Integral and pointer return values. */ |
1393 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
1394 | ||
1395 | if (len > 4) | |
2757dd86 | 1396 | { |
386c036b MK |
1397 | gdb_assert (len == 8); |
1398 | memcpy (buf, valbuf, 8); | |
1399 | regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4); | |
2757dd86 AC |
1400 | } |
1401 | else | |
1402 | { | |
386c036b MK |
1403 | /* ??? Do we need to do any sign-extension here? */ |
1404 | memcpy (buf + 4 - len, valbuf, len); | |
2757dd86 | 1405 | } |
386c036b | 1406 | regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); |
c906108c SS |
1407 | } |
1408 | } | |
1409 | ||
b9d4c5ed | 1410 | static enum return_value_convention |
6a3a010b | 1411 | sparc32_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
1412 | struct type *type, struct regcache *regcache, |
1413 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
b9d4c5ed | 1414 | { |
e17a4113 UW |
1415 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1416 | ||
0a8f48b9 MK |
1417 | /* The psABI says that "...every stack frame reserves the word at |
1418 | %fp+64. If a function returns a structure, union, or | |
1419 | quad-precision value, this word should hold the address of the | |
1420 | object into which the return value should be copied." This | |
1421 | guarantees that we can always find the return value, not just | |
1422 | before the function returns. */ | |
1423 | ||
b9d4c5ed MK |
1424 | if (sparc_structure_or_union_p (type) |
1425 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
0a8f48b9 | 1426 | { |
bbfdfe1c DM |
1427 | ULONGEST sp; |
1428 | CORE_ADDR addr; | |
1429 | ||
0a8f48b9 MK |
1430 | if (readbuf) |
1431 | { | |
0a8f48b9 | 1432 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); |
e17a4113 | 1433 | addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); |
0a8f48b9 MK |
1434 | read_memory (addr, readbuf, TYPE_LENGTH (type)); |
1435 | } | |
bbfdfe1c DM |
1436 | if (writebuf) |
1437 | { | |
1438 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1439 | addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); | |
1440 | write_memory (addr, writebuf, TYPE_LENGTH (type)); | |
1441 | } | |
0a8f48b9 MK |
1442 | |
1443 | return RETURN_VALUE_ABI_PRESERVES_ADDRESS; | |
1444 | } | |
b9d4c5ed MK |
1445 | |
1446 | if (readbuf) | |
1447 | sparc32_extract_return_value (type, regcache, readbuf); | |
1448 | if (writebuf) | |
1449 | sparc32_store_return_value (type, regcache, writebuf); | |
1450 | ||
1451 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1452 | } | |
1453 | ||
386c036b MK |
1454 | static int |
1455 | sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) | |
c906108c | 1456 | { |
386c036b | 1457 | return (sparc_structure_or_union_p (type) |
fe10a582 DM |
1458 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16) |
1459 | || sparc_complex_floating_p (type)); | |
386c036b | 1460 | } |
c906108c | 1461 | |
aff37fc1 | 1462 | static int |
4a4e5149 | 1463 | sparc32_dwarf2_struct_return_p (struct frame_info *this_frame) |
aff37fc1 | 1464 | { |
236369e7 | 1465 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
aff37fc1 DM |
1466 | struct symbol *sym = find_pc_function (pc); |
1467 | ||
1468 | if (sym) | |
1469 | return sparc32_struct_return_from_sym (sym); | |
1470 | return 0; | |
1471 | } | |
1472 | ||
f5a9b87d DM |
1473 | static void |
1474 | sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 | 1475 | struct dwarf2_frame_state_reg *reg, |
4a4e5149 | 1476 | struct frame_info *this_frame) |
f5a9b87d | 1477 | { |
aff37fc1 DM |
1478 | int off; |
1479 | ||
f5a9b87d DM |
1480 | switch (regnum) |
1481 | { | |
1482 | case SPARC_G0_REGNUM: | |
1483 | /* Since %g0 is always zero, there is no point in saving it, and | |
1484 | people will be inclined omit it from the CFI. Make sure we | |
1485 | don't warn about that. */ | |
1486 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
1487 | break; | |
1488 | case SPARC_SP_REGNUM: | |
1489 | reg->how = DWARF2_FRAME_REG_CFA; | |
1490 | break; | |
1491 | case SPARC32_PC_REGNUM: | |
f5a9b87d DM |
1492 | case SPARC32_NPC_REGNUM: |
1493 | reg->how = DWARF2_FRAME_REG_RA_OFFSET; | |
aff37fc1 | 1494 | off = 8; |
4a4e5149 | 1495 | if (sparc32_dwarf2_struct_return_p (this_frame)) |
aff37fc1 DM |
1496 | off += 4; |
1497 | if (regnum == SPARC32_NPC_REGNUM) | |
1498 | off += 4; | |
1499 | reg->loc.offset = off; | |
f5a9b87d DM |
1500 | break; |
1501 | } | |
1502 | } | |
1503 | ||
386c036b MK |
1504 | \f |
1505 | /* The SPARC Architecture doesn't have hardware single-step support, | |
1506 | and most operating systems don't implement it either, so we provide | |
1507 | software single-step mechanism. */ | |
c906108c | 1508 | |
386c036b | 1509 | static CORE_ADDR |
0b1b3e42 | 1510 | sparc_analyze_control_transfer (struct frame_info *frame, |
c893be75 | 1511 | CORE_ADDR pc, CORE_ADDR *npc) |
386c036b MK |
1512 | { |
1513 | unsigned long insn = sparc_fetch_instruction (pc); | |
1514 | int conditional_p = X_COND (insn) & 0x7; | |
8d1b3521 | 1515 | int branch_p = 0, fused_p = 0; |
386c036b | 1516 | long offset = 0; /* Must be signed for sign-extend. */ |
c906108c | 1517 | |
8d1b3521 | 1518 | if (X_OP (insn) == 0 && X_OP2 (insn) == 3) |
c906108c | 1519 | { |
8d1b3521 DM |
1520 | if ((insn & 0x10000000) == 0) |
1521 | { | |
1522 | /* Branch on Integer Register with Prediction (BPr). */ | |
1523 | branch_p = 1; | |
1524 | conditional_p = 1; | |
1525 | } | |
1526 | else | |
1527 | { | |
1528 | /* Compare and Branch */ | |
1529 | branch_p = 1; | |
1530 | fused_p = 1; | |
1531 | offset = 4 * X_DISP10 (insn); | |
1532 | } | |
c906108c | 1533 | } |
386c036b | 1534 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) |
c906108c | 1535 | { |
386c036b MK |
1536 | /* Branch on Floating-Point Condition Codes (FBfcc). */ |
1537 | branch_p = 1; | |
1538 | offset = 4 * X_DISP22 (insn); | |
c906108c | 1539 | } |
386c036b MK |
1540 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) |
1541 | { | |
1542 | /* Branch on Floating-Point Condition Codes with Prediction | |
1543 | (FBPfcc). */ | |
1544 | branch_p = 1; | |
1545 | offset = 4 * X_DISP19 (insn); | |
1546 | } | |
1547 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) | |
1548 | { | |
1549 | /* Branch on Integer Condition Codes (Bicc). */ | |
1550 | branch_p = 1; | |
1551 | offset = 4 * X_DISP22 (insn); | |
1552 | } | |
1553 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) | |
c906108c | 1554 | { |
386c036b MK |
1555 | /* Branch on Integer Condition Codes with Prediction (BPcc). */ |
1556 | branch_p = 1; | |
1557 | offset = 4 * X_DISP19 (insn); | |
c906108c | 1558 | } |
c893be75 MK |
1559 | else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a) |
1560 | { | |
1561 | /* Trap instruction (TRAP). */ | |
0b1b3e42 | 1562 | return gdbarch_tdep (get_frame_arch (frame))->step_trap (frame, insn); |
c893be75 | 1563 | } |
386c036b MK |
1564 | |
1565 | /* FIXME: Handle DONE and RETRY instructions. */ | |
1566 | ||
386c036b | 1567 | if (branch_p) |
c906108c | 1568 | { |
8d1b3521 DM |
1569 | if (fused_p) |
1570 | { | |
1571 | /* Fused compare-and-branch instructions are non-delayed, | |
1572 | and do not have an annuling capability. So we need to | |
1573 | always set a breakpoint on both the NPC and the branch | |
1574 | target address. */ | |
1575 | gdb_assert (offset != 0); | |
1576 | return pc + offset; | |
1577 | } | |
1578 | else if (conditional_p) | |
c906108c | 1579 | { |
386c036b MK |
1580 | /* For conditional branches, return nPC + 4 iff the annul |
1581 | bit is 1. */ | |
1582 | return (X_A (insn) ? *npc + 4 : 0); | |
c906108c SS |
1583 | } |
1584 | else | |
1585 | { | |
386c036b MK |
1586 | /* For unconditional branches, return the target if its |
1587 | specified condition is "always" and return nPC + 4 if the | |
1588 | condition is "never". If the annul bit is 1, set *NPC to | |
1589 | zero. */ | |
1590 | if (X_COND (insn) == 0x0) | |
1591 | pc = *npc, offset = 4; | |
1592 | if (X_A (insn)) | |
1593 | *npc = 0; | |
1594 | ||
386c036b | 1595 | return pc + offset; |
c906108c SS |
1596 | } |
1597 | } | |
386c036b MK |
1598 | |
1599 | return 0; | |
c906108c SS |
1600 | } |
1601 | ||
c893be75 | 1602 | static CORE_ADDR |
0b1b3e42 | 1603 | sparc_step_trap (struct frame_info *frame, unsigned long insn) |
c893be75 MK |
1604 | { |
1605 | return 0; | |
1606 | } | |
1607 | ||
e6590a1b | 1608 | int |
0b1b3e42 | 1609 | sparc_software_single_step (struct frame_info *frame) |
386c036b | 1610 | { |
0b1b3e42 | 1611 | struct gdbarch *arch = get_frame_arch (frame); |
c893be75 | 1612 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
6c95b8df | 1613 | struct address_space *aspace = get_frame_address_space (frame); |
8181d85f | 1614 | CORE_ADDR npc, nnpc; |
c906108c | 1615 | |
e0cd558a | 1616 | CORE_ADDR pc, orig_npc; |
c906108c | 1617 | |
0b1b3e42 UW |
1618 | pc = get_frame_register_unsigned (frame, tdep->pc_regnum); |
1619 | orig_npc = npc = get_frame_register_unsigned (frame, tdep->npc_regnum); | |
c906108c | 1620 | |
e0cd558a | 1621 | /* Analyze the instruction at PC. */ |
0b1b3e42 | 1622 | nnpc = sparc_analyze_control_transfer (frame, pc, &npc); |
e0cd558a | 1623 | if (npc != 0) |
6c95b8df | 1624 | insert_single_step_breakpoint (arch, aspace, npc); |
8181d85f | 1625 | |
e0cd558a | 1626 | if (nnpc != 0) |
6c95b8df | 1627 | insert_single_step_breakpoint (arch, aspace, nnpc); |
c906108c | 1628 | |
e0cd558a UW |
1629 | /* Assert that we have set at least one breakpoint, and that |
1630 | they're not set at the same spot - unless we're going | |
1631 | from here straight to NULL, i.e. a call or jump to 0. */ | |
1632 | gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0); | |
1633 | gdb_assert (nnpc != npc || orig_npc == 0); | |
e6590a1b UW |
1634 | |
1635 | return 1; | |
386c036b MK |
1636 | } |
1637 | ||
1638 | static void | |
61a1198a | 1639 | sparc_write_pc (struct regcache *regcache, CORE_ADDR pc) |
386c036b | 1640 | { |
61a1198a | 1641 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
386c036b | 1642 | |
61a1198a UW |
1643 | regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc); |
1644 | regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4); | |
386c036b MK |
1645 | } |
1646 | \f | |
5af923b0 | 1647 | |
a54124c5 MK |
1648 | /* Return the appropriate register set for the core section identified |
1649 | by SECT_NAME and SECT_SIZE. */ | |
1650 | ||
63807e1d | 1651 | static const struct regset * |
a54124c5 MK |
1652 | sparc_regset_from_core_section (struct gdbarch *gdbarch, |
1653 | const char *sect_name, size_t sect_size) | |
1654 | { | |
1655 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1656 | ||
c558d81a | 1657 | if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset) |
a54124c5 MK |
1658 | return tdep->gregset; |
1659 | ||
c558d81a | 1660 | if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset) |
a54124c5 MK |
1661 | return tdep->fpregset; |
1662 | ||
1663 | return NULL; | |
1664 | } | |
1665 | \f | |
1666 | ||
386c036b MK |
1667 | static struct gdbarch * |
1668 | sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1669 | { | |
1670 | struct gdbarch_tdep *tdep; | |
1671 | struct gdbarch *gdbarch; | |
c906108c | 1672 | |
386c036b MK |
1673 | /* If there is already a candidate, use it. */ |
1674 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1675 | if (arches != NULL) | |
1676 | return arches->gdbarch; | |
c906108c | 1677 | |
386c036b | 1678 | /* Allocate space for the new architecture. */ |
41bf6aca | 1679 | tdep = XCNEW (struct gdbarch_tdep); |
386c036b | 1680 | gdbarch = gdbarch_alloc (&info, tdep); |
5af923b0 | 1681 | |
386c036b MK |
1682 | tdep->pc_regnum = SPARC32_PC_REGNUM; |
1683 | tdep->npc_regnum = SPARC32_NPC_REGNUM; | |
c893be75 | 1684 | tdep->step_trap = sparc_step_trap; |
386c036b MK |
1685 | |
1686 | set_gdbarch_long_double_bit (gdbarch, 128); | |
8da61cc4 | 1687 | set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad); |
386c036b MK |
1688 | |
1689 | set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); | |
1690 | set_gdbarch_register_name (gdbarch, sparc32_register_name); | |
1691 | set_gdbarch_register_type (gdbarch, sparc32_register_type); | |
1692 | set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); | |
1693 | set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); | |
1694 | set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); | |
1695 | ||
1696 | /* Register numbers of various important registers. */ | |
1697 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ | |
1698 | set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ | |
1699 | set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ | |
1700 | ||
1701 | /* Call dummy code. */ | |
49a45ecf | 1702 | set_gdbarch_frame_align (gdbarch, sparc32_frame_align); |
386c036b MK |
1703 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
1704 | set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); | |
1705 | set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); | |
1706 | ||
b9d4c5ed | 1707 | set_gdbarch_return_value (gdbarch, sparc32_return_value); |
386c036b MK |
1708 | set_gdbarch_stabs_argument_has_addr |
1709 | (gdbarch, sparc32_stabs_argument_has_addr); | |
1710 | ||
1711 | set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); | |
1712 | ||
1713 | /* Stack grows downward. */ | |
1714 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
c906108c | 1715 | |
386c036b | 1716 | set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc); |
c906108c | 1717 | |
386c036b | 1718 | set_gdbarch_frame_args_skip (gdbarch, 8); |
5af923b0 | 1719 | |
386c036b | 1720 | set_gdbarch_print_insn (gdbarch, print_insn_sparc); |
c906108c | 1721 | |
386c036b MK |
1722 | set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); |
1723 | set_gdbarch_write_pc (gdbarch, sparc_write_pc); | |
c906108c | 1724 | |
236369e7 | 1725 | set_gdbarch_dummy_id (gdbarch, sparc_dummy_id); |
c906108c | 1726 | |
386c036b | 1727 | set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc); |
c906108c | 1728 | |
386c036b MK |
1729 | frame_base_set_default (gdbarch, &sparc32_frame_base); |
1730 | ||
f5a9b87d DM |
1731 | /* Hook in the DWARF CFI frame unwinder. */ |
1732 | dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg); | |
1733 | /* FIXME: kettenis/20050423: Don't enable the unwinder until the | |
1734 | StackGhost issues have been resolved. */ | |
1735 | ||
b2a0b9b2 DM |
1736 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1737 | gdbarch_init_osabi (info, gdbarch); | |
1738 | ||
236369e7 | 1739 | frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind); |
c906108c | 1740 | |
a54124c5 | 1741 | /* If we have register sets, enable the generic core file support. */ |
4c72d57a | 1742 | if (tdep->gregset) |
a54124c5 MK |
1743 | set_gdbarch_regset_from_core_section (gdbarch, |
1744 | sparc_regset_from_core_section); | |
1745 | ||
7e35103a JB |
1746 | register_sparc_ravenscar_ops (gdbarch); |
1747 | ||
386c036b MK |
1748 | return gdbarch; |
1749 | } | |
1750 | \f | |
1751 | /* Helper functions for dealing with register windows. */ | |
1752 | ||
1753 | void | |
1754 | sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) | |
c906108c | 1755 | { |
e17a4113 UW |
1756 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1757 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
386c036b | 1758 | int offset = 0; |
e1613aba | 1759 | gdb_byte buf[8]; |
386c036b MK |
1760 | int i; |
1761 | ||
1762 | if (sp & 1) | |
1763 | { | |
1764 | /* Registers are 64-bit. */ | |
1765 | sp += BIAS; | |
c906108c | 1766 | |
386c036b MK |
1767 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1768 | { | |
1769 | if (regnum == i || regnum == -1) | |
1770 | { | |
1771 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); | |
f700a364 MK |
1772 | |
1773 | /* Handle StackGhost. */ | |
1774 | if (i == SPARC_I7_REGNUM) | |
1775 | { | |
e17a4113 UW |
1776 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1777 | ULONGEST i7; | |
f700a364 | 1778 | |
e17a4113 UW |
1779 | i7 = extract_unsigned_integer (buf + offset, 8, byte_order); |
1780 | store_unsigned_integer (buf + offset, 8, byte_order, | |
1781 | i7 ^ wcookie); | |
f700a364 MK |
1782 | } |
1783 | ||
386c036b MK |
1784 | regcache_raw_supply (regcache, i, buf); |
1785 | } | |
1786 | } | |
1787 | } | |
1788 | else | |
c906108c | 1789 | { |
386c036b MK |
1790 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1791 | pointer. */ | |
1792 | sp &= 0xffffffffUL; | |
c906108c | 1793 | |
386c036b MK |
1794 | /* Clear out the top half of the temporary buffer, and put the |
1795 | register value in the bottom half if we're in 64-bit mode. */ | |
e6d4f032 | 1796 | if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) |
c906108c | 1797 | { |
386c036b MK |
1798 | memset (buf, 0, 4); |
1799 | offset = 4; | |
1800 | } | |
c906108c | 1801 | |
386c036b MK |
1802 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1803 | { | |
1804 | if (regnum == i || regnum == -1) | |
1805 | { | |
1806 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), | |
1807 | buf + offset, 4); | |
42cdca6c MK |
1808 | |
1809 | /* Handle StackGhost. */ | |
1810 | if (i == SPARC_I7_REGNUM) | |
1811 | { | |
e17a4113 UW |
1812 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1813 | ULONGEST i7; | |
42cdca6c | 1814 | |
e17a4113 UW |
1815 | i7 = extract_unsigned_integer (buf + offset, 4, byte_order); |
1816 | store_unsigned_integer (buf + offset, 4, byte_order, | |
1817 | i7 ^ wcookie); | |
42cdca6c MK |
1818 | } |
1819 | ||
386c036b MK |
1820 | regcache_raw_supply (regcache, i, buf); |
1821 | } | |
c906108c SS |
1822 | } |
1823 | } | |
c906108c | 1824 | } |
c906108c SS |
1825 | |
1826 | void | |
386c036b MK |
1827 | sparc_collect_rwindow (const struct regcache *regcache, |
1828 | CORE_ADDR sp, int regnum) | |
c906108c | 1829 | { |
e17a4113 UW |
1830 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1831 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
386c036b | 1832 | int offset = 0; |
e1613aba | 1833 | gdb_byte buf[8]; |
386c036b | 1834 | int i; |
5af923b0 | 1835 | |
386c036b | 1836 | if (sp & 1) |
5af923b0 | 1837 | { |
386c036b MK |
1838 | /* Registers are 64-bit. */ |
1839 | sp += BIAS; | |
c906108c | 1840 | |
386c036b MK |
1841 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1842 | { | |
1843 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1844 | { | |
1845 | regcache_raw_collect (regcache, i, buf); | |
f700a364 MK |
1846 | |
1847 | /* Handle StackGhost. */ | |
1848 | if (i == SPARC_I7_REGNUM) | |
1849 | { | |
e17a4113 UW |
1850 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1851 | ULONGEST i7; | |
f700a364 | 1852 | |
e17a4113 UW |
1853 | i7 = extract_unsigned_integer (buf + offset, 8, byte_order); |
1854 | store_unsigned_integer (buf, 8, byte_order, i7 ^ wcookie); | |
f700a364 MK |
1855 | } |
1856 | ||
386c036b MK |
1857 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); |
1858 | } | |
1859 | } | |
5af923b0 MS |
1860 | } |
1861 | else | |
1862 | { | |
386c036b MK |
1863 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1864 | pointer. */ | |
1865 | sp &= 0xffffffffUL; | |
1866 | ||
1867 | /* Only use the bottom half if we're in 64-bit mode. */ | |
e6d4f032 | 1868 | if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) |
386c036b MK |
1869 | offset = 4; |
1870 | ||
1871 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1872 | { | |
1873 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1874 | { | |
1875 | regcache_raw_collect (regcache, i, buf); | |
42cdca6c MK |
1876 | |
1877 | /* Handle StackGhost. */ | |
1878 | if (i == SPARC_I7_REGNUM) | |
1879 | { | |
e17a4113 UW |
1880 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1881 | ULONGEST i7; | |
42cdca6c | 1882 | |
e17a4113 UW |
1883 | i7 = extract_unsigned_integer (buf + offset, 4, byte_order); |
1884 | store_unsigned_integer (buf + offset, 4, byte_order, | |
1885 | i7 ^ wcookie); | |
42cdca6c MK |
1886 | } |
1887 | ||
386c036b MK |
1888 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), |
1889 | buf + offset, 4); | |
1890 | } | |
1891 | } | |
5af923b0 | 1892 | } |
c906108c SS |
1893 | } |
1894 | ||
386c036b MK |
1895 | /* Helper functions for dealing with register sets. */ |
1896 | ||
c906108c | 1897 | void |
b4fd25c9 | 1898 | sparc32_supply_gregset (const struct sparc_gregmap *gregmap, |
386c036b MK |
1899 | struct regcache *regcache, |
1900 | int regnum, const void *gregs) | |
c906108c | 1901 | { |
e1613aba | 1902 | const gdb_byte *regs = gregs; |
22e74ef9 | 1903 | gdb_byte zero[4] = { 0 }; |
386c036b | 1904 | int i; |
5af923b0 | 1905 | |
386c036b MK |
1906 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1907 | regcache_raw_supply (regcache, SPARC32_PSR_REGNUM, | |
b4fd25c9 | 1908 | regs + gregmap->r_psr_offset); |
c906108c | 1909 | |
386c036b MK |
1910 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1911 | regcache_raw_supply (regcache, SPARC32_PC_REGNUM, | |
b4fd25c9 | 1912 | regs + gregmap->r_pc_offset); |
5af923b0 | 1913 | |
386c036b MK |
1914 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) |
1915 | regcache_raw_supply (regcache, SPARC32_NPC_REGNUM, | |
b4fd25c9 | 1916 | regs + gregmap->r_npc_offset); |
5af923b0 | 1917 | |
386c036b MK |
1918 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1919 | regcache_raw_supply (regcache, SPARC32_Y_REGNUM, | |
b4fd25c9 | 1920 | regs + gregmap->r_y_offset); |
5af923b0 | 1921 | |
386c036b | 1922 | if (regnum == SPARC_G0_REGNUM || regnum == -1) |
22e74ef9 | 1923 | regcache_raw_supply (regcache, SPARC_G0_REGNUM, &zero); |
5af923b0 | 1924 | |
386c036b | 1925 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) |
c906108c | 1926 | { |
b4fd25c9 | 1927 | int offset = gregmap->r_g1_offset; |
386c036b MK |
1928 | |
1929 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1930 | { | |
1931 | if (regnum == i || regnum == -1) | |
1932 | regcache_raw_supply (regcache, i, regs + offset); | |
1933 | offset += 4; | |
1934 | } | |
c906108c | 1935 | } |
386c036b MK |
1936 | |
1937 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
c906108c | 1938 | { |
386c036b MK |
1939 | /* Not all of the register set variants include Locals and |
1940 | Inputs. For those that don't, we read them off the stack. */ | |
b4fd25c9 | 1941 | if (gregmap->r_l0_offset == -1) |
386c036b MK |
1942 | { |
1943 | ULONGEST sp; | |
1944 | ||
1945 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1946 | sparc_supply_rwindow (regcache, sp, regnum); | |
1947 | } | |
1948 | else | |
1949 | { | |
b4fd25c9 | 1950 | int offset = gregmap->r_l0_offset; |
386c036b MK |
1951 | |
1952 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1953 | { | |
1954 | if (regnum == i || regnum == -1) | |
1955 | regcache_raw_supply (regcache, i, regs + offset); | |
1956 | offset += 4; | |
1957 | } | |
1958 | } | |
c906108c SS |
1959 | } |
1960 | } | |
1961 | ||
c5aa993b | 1962 | void |
b4fd25c9 | 1963 | sparc32_collect_gregset (const struct sparc_gregmap *gregmap, |
386c036b MK |
1964 | const struct regcache *regcache, |
1965 | int regnum, void *gregs) | |
c906108c | 1966 | { |
e1613aba | 1967 | gdb_byte *regs = gregs; |
386c036b | 1968 | int i; |
c5aa993b | 1969 | |
386c036b MK |
1970 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1971 | regcache_raw_collect (regcache, SPARC32_PSR_REGNUM, | |
b4fd25c9 | 1972 | regs + gregmap->r_psr_offset); |
60054393 | 1973 | |
386c036b MK |
1974 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1975 | regcache_raw_collect (regcache, SPARC32_PC_REGNUM, | |
b4fd25c9 | 1976 | regs + gregmap->r_pc_offset); |
386c036b MK |
1977 | |
1978 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) | |
1979 | regcache_raw_collect (regcache, SPARC32_NPC_REGNUM, | |
b4fd25c9 | 1980 | regs + gregmap->r_npc_offset); |
5af923b0 | 1981 | |
386c036b MK |
1982 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1983 | regcache_raw_collect (regcache, SPARC32_Y_REGNUM, | |
b4fd25c9 | 1984 | regs + gregmap->r_y_offset); |
386c036b MK |
1985 | |
1986 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) | |
5af923b0 | 1987 | { |
b4fd25c9 | 1988 | int offset = gregmap->r_g1_offset; |
386c036b MK |
1989 | |
1990 | /* %g0 is always zero. */ | |
1991 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1992 | { | |
1993 | if (regnum == i || regnum == -1) | |
1994 | regcache_raw_collect (regcache, i, regs + offset); | |
1995 | offset += 4; | |
1996 | } | |
5af923b0 | 1997 | } |
386c036b MK |
1998 | |
1999 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
5af923b0 | 2000 | { |
386c036b MK |
2001 | /* Not all of the register set variants include Locals and |
2002 | Inputs. For those that don't, we read them off the stack. */ | |
b4fd25c9 | 2003 | if (gregmap->r_l0_offset != -1) |
386c036b | 2004 | { |
b4fd25c9 | 2005 | int offset = gregmap->r_l0_offset; |
386c036b MK |
2006 | |
2007 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
2008 | { | |
2009 | if (regnum == i || regnum == -1) | |
2010 | regcache_raw_collect (regcache, i, regs + offset); | |
2011 | offset += 4; | |
2012 | } | |
2013 | } | |
5af923b0 | 2014 | } |
c906108c SS |
2015 | } |
2016 | ||
c906108c | 2017 | void |
b4fd25c9 | 2018 | sparc32_supply_fpregset (const struct sparc_fpregmap *fpregmap, |
db75c717 | 2019 | struct regcache *regcache, |
386c036b | 2020 | int regnum, const void *fpregs) |
c906108c | 2021 | { |
e1613aba | 2022 | const gdb_byte *regs = fpregs; |
386c036b | 2023 | int i; |
60054393 | 2024 | |
386c036b | 2025 | for (i = 0; i < 32; i++) |
c906108c | 2026 | { |
386c036b | 2027 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) |
db75c717 | 2028 | regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, |
b4fd25c9 | 2029 | regs + fpregmap->r_f0_offset + (i * 4)); |
c906108c | 2030 | } |
5af923b0 | 2031 | |
386c036b | 2032 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
db75c717 | 2033 | regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, |
b4fd25c9 | 2034 | regs + fpregmap->r_fsr_offset); |
c906108c SS |
2035 | } |
2036 | ||
386c036b | 2037 | void |
b4fd25c9 | 2038 | sparc32_collect_fpregset (const struct sparc_fpregmap *fpregmap, |
db75c717 | 2039 | const struct regcache *regcache, |
386c036b | 2040 | int regnum, void *fpregs) |
c906108c | 2041 | { |
e1613aba | 2042 | gdb_byte *regs = fpregs; |
386c036b | 2043 | int i; |
c906108c | 2044 | |
386c036b MK |
2045 | for (i = 0; i < 32; i++) |
2046 | { | |
2047 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) | |
db75c717 | 2048 | regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, |
b4fd25c9 | 2049 | regs + fpregmap->r_f0_offset + (i * 4)); |
386c036b | 2050 | } |
c906108c | 2051 | |
386c036b | 2052 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
db75c717 | 2053 | regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, |
b4fd25c9 | 2054 | regs + fpregmap->r_fsr_offset); |
c906108c | 2055 | } |
c906108c | 2056 | \f |
c906108c | 2057 | |
386c036b | 2058 | /* SunOS 4. */ |
c906108c | 2059 | |
386c036b | 2060 | /* From <machine/reg.h>. */ |
b4fd25c9 | 2061 | const struct sparc_gregmap sparc32_sunos4_gregmap = |
c906108c | 2062 | { |
386c036b MK |
2063 | 0 * 4, /* %psr */ |
2064 | 1 * 4, /* %pc */ | |
2065 | 2 * 4, /* %npc */ | |
2066 | 3 * 4, /* %y */ | |
2067 | -1, /* %wim */ | |
2068 | -1, /* %tbr */ | |
2069 | 4 * 4, /* %g1 */ | |
2070 | -1 /* %l0 */ | |
2071 | }; | |
db75c717 | 2072 | |
b4fd25c9 | 2073 | const struct sparc_fpregmap sparc32_sunos4_fpregmap = |
db75c717 DM |
2074 | { |
2075 | 0 * 4, /* %f0 */ | |
2076 | 33 * 4, /* %fsr */ | |
2077 | }; | |
2078 | ||
b4fd25c9 | 2079 | const struct sparc_fpregmap sparc32_bsd_fpregmap = |
db75c717 DM |
2080 | { |
2081 | 0 * 4, /* %f0 */ | |
2082 | 32 * 4, /* %fsr */ | |
2083 | }; | |
386c036b | 2084 | \f |
c906108c | 2085 | |
386c036b MK |
2086 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
2087 | void _initialize_sparc_tdep (void); | |
c906108c SS |
2088 | |
2089 | void | |
386c036b | 2090 | _initialize_sparc_tdep (void) |
c906108c | 2091 | { |
386c036b | 2092 | register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init); |
ef3cf062 | 2093 | } |