Commit | Line | Data |
---|---|---|
386c036b | 1 | /* Target-dependent code for SPARC. |
cda5a58a | 2 | |
61baf725 | 3 | Copyright (C) 2003-2017 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 19 | |
c906108c | 20 | #include "defs.h" |
5af923b0 | 21 | #include "arch-utils.h" |
386c036b | 22 | #include "dis-asm.h" |
f5a9b87d | 23 | #include "dwarf2-frame.h" |
386c036b | 24 | #include "floatformat.h" |
c906108c | 25 | #include "frame.h" |
386c036b MK |
26 | #include "frame-base.h" |
27 | #include "frame-unwind.h" | |
28 | #include "gdbcore.h" | |
29 | #include "gdbtypes.h" | |
c906108c | 30 | #include "inferior.h" |
386c036b MK |
31 | #include "symtab.h" |
32 | #include "objfiles.h" | |
33 | #include "osabi.h" | |
34 | #include "regcache.h" | |
c906108c | 35 | #include "target.h" |
3f7b46f2 | 36 | #include "target-descriptions.h" |
c906108c | 37 | #include "value.h" |
c906108c | 38 | |
386c036b | 39 | #include "sparc-tdep.h" |
e6f9c00b | 40 | #include "sparc-ravenscar-thread.h" |
325fac50 | 41 | #include <algorithm> |
c906108c | 42 | |
a54124c5 MK |
43 | struct regset; |
44 | ||
9eb42ed1 MK |
45 | /* This file implements the SPARC 32-bit ABI as defined by the section |
46 | "Low-Level System Information" of the SPARC Compliance Definition | |
47 | (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD | |
f2e7c15d | 48 | lists changes with respect to the original 32-bit psABI as defined |
9eb42ed1 | 49 | in the "System V ABI, SPARC Processor Supplement". |
386c036b MK |
50 | |
51 | Note that if we talk about SunOS, we mean SunOS 4.x, which was | |
52 | BSD-based, which is sometimes (retroactively?) referred to as | |
53 | Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and | |
54 | above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 | |
55 | suffering from severe version number inflation). Solaris 2.x is | |
56 | also known as SunOS 5.x, since that's what uname(1) says. Solaris | |
57 | 2.x is SVR4-based. */ | |
58 | ||
59 | /* Please use the sparc32_-prefix for 32-bit specific code, the | |
60 | sparc64_-prefix for 64-bit specific code and the sparc_-prefix for | |
61 | code that can handle both. The 64-bit specific code lives in | |
62 | sparc64-tdep.c; don't add any here. */ | |
63 | ||
64 | /* The SPARC Floating-Point Quad-Precision format is similar to | |
7a58cce8 | 65 | big-endian IA-64 Quad-Precision format. */ |
8da61cc4 | 66 | #define floatformats_sparc_quad floatformats_ia64_quad |
386c036b MK |
67 | |
68 | /* The stack pointer is offset from the stack frame by a BIAS of 2047 | |
69 | (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC | |
70 | hosts, so undefine it first. */ | |
71 | #undef BIAS | |
72 | #define BIAS 2047 | |
73 | ||
74 | /* Macros to extract fields from SPARC instructions. */ | |
c906108c SS |
75 | #define X_OP(i) (((i) >> 30) & 0x3) |
76 | #define X_RD(i) (((i) >> 25) & 0x1f) | |
77 | #define X_A(i) (((i) >> 29) & 1) | |
78 | #define X_COND(i) (((i) >> 25) & 0xf) | |
79 | #define X_OP2(i) (((i) >> 22) & 0x7) | |
80 | #define X_IMM22(i) ((i) & 0x3fffff) | |
81 | #define X_OP3(i) (((i) >> 19) & 0x3f) | |
075ccec8 | 82 | #define X_RS1(i) (((i) >> 14) & 0x1f) |
b0b92586 | 83 | #define X_RS2(i) ((i) & 0x1f) |
c906108c | 84 | #define X_I(i) (((i) >> 13) & 1) |
c906108c | 85 | /* Sign extension macros. */ |
c906108c | 86 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) |
c906108c | 87 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) |
8d1b3521 | 88 | #define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200) |
075ccec8 | 89 | #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000) |
961842b2 JM |
90 | /* Macros to identify some instructions. */ |
91 | /* RETURN (RETT in V8) */ | |
92 | #define X_RETTURN(i) ((X_OP (i) == 0x2) && (X_OP3 (i) == 0x39)) | |
c906108c | 93 | |
386c036b MK |
94 | /* Fetch the instruction at PC. Instructions are always big-endian |
95 | even if the processor operates in little-endian mode. */ | |
96 | ||
97 | unsigned long | |
98 | sparc_fetch_instruction (CORE_ADDR pc) | |
c906108c | 99 | { |
e1613aba | 100 | gdb_byte buf[4]; |
386c036b MK |
101 | unsigned long insn; |
102 | int i; | |
103 | ||
690668cc | 104 | /* If we can't read the instruction at PC, return zero. */ |
8defab1a | 105 | if (target_read_memory (pc, buf, sizeof (buf))) |
690668cc | 106 | return 0; |
c906108c | 107 | |
386c036b MK |
108 | insn = 0; |
109 | for (i = 0; i < sizeof (buf); i++) | |
110 | insn = (insn << 8) | buf[i]; | |
111 | return insn; | |
112 | } | |
42cdca6c MK |
113 | \f |
114 | ||
5465445a JB |
115 | /* Return non-zero if the instruction corresponding to PC is an "unimp" |
116 | instruction. */ | |
117 | ||
118 | static int | |
119 | sparc_is_unimp_insn (CORE_ADDR pc) | |
120 | { | |
121 | const unsigned long insn = sparc_fetch_instruction (pc); | |
122 | ||
123 | return ((insn & 0xc1c00000) == 0); | |
124 | } | |
125 | ||
d0b5971a JM |
126 | /* Return non-zero if the instruction corresponding to PC is an |
127 | "annulled" branch, i.e. the annul bit is set. */ | |
128 | ||
129 | int | |
130 | sparc_is_annulled_branch_insn (CORE_ADDR pc) | |
131 | { | |
132 | /* The branch instructions featuring an annul bit can be identified | |
133 | by the following bit patterns: | |
134 | ||
135 | OP=0 | |
136 | OP2=1: Branch on Integer Condition Codes with Prediction (BPcc). | |
137 | OP2=2: Branch on Integer Condition Codes (Bcc). | |
138 | OP2=5: Branch on FP Condition Codes with Prediction (FBfcc). | |
139 | OP2=6: Branch on FP Condition Codes (FBcc). | |
140 | OP2=3 && Bit28=0: | |
141 | Branch on Integer Register with Prediction (BPr). | |
142 | ||
143 | This leaves out ILLTRAP (OP2=0), SETHI/NOP (OP2=4) and the V8 | |
144 | coprocessor branch instructions (Op2=7). */ | |
145 | ||
146 | const unsigned long insn = sparc_fetch_instruction (pc); | |
147 | const unsigned op2 = X_OP2 (insn); | |
148 | ||
149 | if ((X_OP (insn) == 0) | |
150 | && ((op2 == 1) || (op2 == 2) || (op2 == 5) || (op2 == 6) | |
151 | || ((op2 == 3) && ((insn & 0x10000000) == 0)))) | |
152 | return X_A (insn); | |
153 | else | |
154 | return 0; | |
155 | } | |
156 | ||
42cdca6c MK |
157 | /* OpenBSD/sparc includes StackGhost, which according to the author's |
158 | website http://stackghost.cerias.purdue.edu "... transparently and | |
159 | automatically protects applications' stack frames; more | |
160 | specifically, it guards the return pointers. The protection | |
161 | mechanisms require no application source or binary modification and | |
162 | imposes only a negligible performance penalty." | |
163 | ||
164 | The same website provides the following description of how | |
165 | StackGhost works: | |
166 | ||
167 | "StackGhost interfaces with the kernel trap handler that would | |
168 | normally write out registers to the stack and the handler that | |
169 | would read them back in. By XORing a cookie into the | |
170 | return-address saved in the user stack when it is actually written | |
171 | to the stack, and then XOR it out when the return-address is pulled | |
172 | from the stack, StackGhost can cause attacker corrupted return | |
173 | pointers to behave in a manner the attacker cannot predict. | |
174 | StackGhost can also use several unused bits in the return pointer | |
175 | to detect a smashed return pointer and abort the process." | |
176 | ||
177 | For GDB this means that whenever we're reading %i7 from a stack | |
178 | frame's window save area, we'll have to XOR the cookie. | |
179 | ||
180 | More information on StackGuard can be found on in: | |
181 | ||
c378eb4e | 182 | Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated |
42cdca6c MK |
183 | Stack Protection." 2001. Published in USENIX Security Symposium |
184 | '01. */ | |
185 | ||
186 | /* Fetch StackGhost Per-Process XOR cookie. */ | |
187 | ||
188 | ULONGEST | |
e17a4113 | 189 | sparc_fetch_wcookie (struct gdbarch *gdbarch) |
42cdca6c | 190 | { |
e17a4113 | 191 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
baf92889 | 192 | struct target_ops *ops = ¤t_target; |
e1613aba | 193 | gdb_byte buf[8]; |
baf92889 MK |
194 | int len; |
195 | ||
13547ab6 | 196 | len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8); |
baf92889 MK |
197 | if (len == -1) |
198 | return 0; | |
42cdca6c | 199 | |
baf92889 MK |
200 | /* We should have either an 32-bit or an 64-bit cookie. */ |
201 | gdb_assert (len == 4 || len == 8); | |
202 | ||
e17a4113 | 203 | return extract_unsigned_integer (buf, len, byte_order); |
baf92889 | 204 | } |
386c036b | 205 | \f |
baf92889 | 206 | |
386c036b MK |
207 | /* The functions on this page are intended to be used to classify |
208 | function arguments. */ | |
c906108c | 209 | |
386c036b | 210 | /* Check whether TYPE is "Integral or Pointer". */ |
c906108c | 211 | |
386c036b MK |
212 | static int |
213 | sparc_integral_or_pointer_p (const struct type *type) | |
c906108c | 214 | { |
80ad1639 MK |
215 | int len = TYPE_LENGTH (type); |
216 | ||
386c036b | 217 | switch (TYPE_CODE (type)) |
c906108c | 218 | { |
386c036b MK |
219 | case TYPE_CODE_INT: |
220 | case TYPE_CODE_BOOL: | |
221 | case TYPE_CODE_CHAR: | |
222 | case TYPE_CODE_ENUM: | |
223 | case TYPE_CODE_RANGE: | |
80ad1639 MK |
224 | /* We have byte, half-word, word and extended-word/doubleword |
225 | integral types. The doubleword is an extension to the | |
226 | original 32-bit ABI by the SCD 2.4.x. */ | |
227 | return (len == 1 || len == 2 || len == 4 || len == 8); | |
386c036b MK |
228 | case TYPE_CODE_PTR: |
229 | case TYPE_CODE_REF: | |
aa006118 | 230 | case TYPE_CODE_RVALUE_REF: |
80ad1639 MK |
231 | /* Allow either 32-bit or 64-bit pointers. */ |
232 | return (len == 4 || len == 8); | |
386c036b MK |
233 | default: |
234 | break; | |
235 | } | |
c906108c | 236 | |
386c036b MK |
237 | return 0; |
238 | } | |
c906108c | 239 | |
386c036b | 240 | /* Check whether TYPE is "Floating". */ |
c906108c | 241 | |
386c036b MK |
242 | static int |
243 | sparc_floating_p (const struct type *type) | |
244 | { | |
245 | switch (TYPE_CODE (type)) | |
c906108c | 246 | { |
386c036b MK |
247 | case TYPE_CODE_FLT: |
248 | { | |
249 | int len = TYPE_LENGTH (type); | |
250 | return (len == 4 || len == 8 || len == 16); | |
251 | } | |
252 | default: | |
253 | break; | |
254 | } | |
255 | ||
256 | return 0; | |
257 | } | |
c906108c | 258 | |
fe10a582 DM |
259 | /* Check whether TYPE is "Complex Floating". */ |
260 | ||
261 | static int | |
262 | sparc_complex_floating_p (const struct type *type) | |
263 | { | |
264 | switch (TYPE_CODE (type)) | |
265 | { | |
266 | case TYPE_CODE_COMPLEX: | |
267 | { | |
268 | int len = TYPE_LENGTH (type); | |
269 | return (len == 8 || len == 16 || len == 32); | |
270 | } | |
271 | default: | |
272 | break; | |
273 | } | |
274 | ||
275 | return 0; | |
276 | } | |
277 | ||
0497f5b0 JB |
278 | /* Check whether TYPE is "Structure or Union". |
279 | ||
280 | In terms of Ada subprogram calls, arrays are treated the same as | |
281 | struct and union types. So this function also returns non-zero | |
282 | for array types. */ | |
c906108c | 283 | |
386c036b MK |
284 | static int |
285 | sparc_structure_or_union_p (const struct type *type) | |
286 | { | |
287 | switch (TYPE_CODE (type)) | |
288 | { | |
289 | case TYPE_CODE_STRUCT: | |
290 | case TYPE_CODE_UNION: | |
0497f5b0 | 291 | case TYPE_CODE_ARRAY: |
386c036b MK |
292 | return 1; |
293 | default: | |
294 | break; | |
c906108c | 295 | } |
386c036b MK |
296 | |
297 | return 0; | |
c906108c | 298 | } |
386c036b MK |
299 | |
300 | /* Register information. */ | |
7a36499a IR |
301 | #define SPARC32_FPU_REGISTERS \ |
302 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ | |
303 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ | |
304 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \ | |
305 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" | |
306 | #define SPARC32_CP0_REGISTERS \ | |
307 | "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" | |
386c036b | 308 | |
3f7b46f2 IR |
309 | static const char *sparc_core_register_names[] = { SPARC_CORE_REGISTERS }; |
310 | static const char *sparc32_fpu_register_names[] = { SPARC32_FPU_REGISTERS }; | |
311 | static const char *sparc32_cp0_register_names[] = { SPARC32_CP0_REGISTERS }; | |
312 | ||
386c036b | 313 | static const char *sparc32_register_names[] = |
5af923b0 | 314 | { |
7a36499a IR |
315 | SPARC_CORE_REGISTERS, |
316 | SPARC32_FPU_REGISTERS, | |
317 | SPARC32_CP0_REGISTERS | |
5af923b0 MS |
318 | }; |
319 | ||
386c036b MK |
320 | /* Total number of registers. */ |
321 | #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) | |
c906108c | 322 | |
386c036b MK |
323 | /* We provide the aliases %d0..%d30 for the floating registers as |
324 | "psuedo" registers. */ | |
325 | ||
326 | static const char *sparc32_pseudo_register_names[] = | |
327 | { | |
328 | "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", | |
329 | "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" | |
330 | }; | |
331 | ||
332 | /* Total number of pseudo registers. */ | |
333 | #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) | |
334 | ||
7a36499a IR |
335 | /* Return the name of pseudo register REGNUM. */ |
336 | ||
337 | static const char * | |
338 | sparc32_pseudo_register_name (struct gdbarch *gdbarch, int regnum) | |
339 | { | |
340 | regnum -= gdbarch_num_regs (gdbarch); | |
341 | ||
342 | if (regnum < SPARC32_NUM_PSEUDO_REGS) | |
343 | return sparc32_pseudo_register_names[regnum]; | |
344 | ||
345 | internal_error (__FILE__, __LINE__, | |
346 | _("sparc32_pseudo_register_name: bad register number %d"), | |
347 | regnum); | |
348 | } | |
349 | ||
386c036b MK |
350 | /* Return the name of register REGNUM. */ |
351 | ||
352 | static const char * | |
d93859e2 | 353 | sparc32_register_name (struct gdbarch *gdbarch, int regnum) |
386c036b | 354 | { |
3f7b46f2 IR |
355 | if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
356 | return tdesc_register_name (gdbarch, regnum); | |
357 | ||
7a36499a | 358 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) |
386c036b MK |
359 | return sparc32_register_names[regnum]; |
360 | ||
7a36499a | 361 | return sparc32_pseudo_register_name (gdbarch, regnum); |
386c036b | 362 | } |
2d457077 | 363 | \f |
209bd28e | 364 | /* Construct types for ISA-specific registers. */ |
2d457077 | 365 | |
209bd28e UW |
366 | static struct type * |
367 | sparc_psr_type (struct gdbarch *gdbarch) | |
368 | { | |
369 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2d457077 | 370 | |
209bd28e UW |
371 | if (!tdep->sparc_psr_type) |
372 | { | |
373 | struct type *type; | |
2d457077 | 374 | |
e9bb382b | 375 | type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 4); |
209bd28e UW |
376 | append_flags_type_flag (type, 5, "ET"); |
377 | append_flags_type_flag (type, 6, "PS"); | |
378 | append_flags_type_flag (type, 7, "S"); | |
379 | append_flags_type_flag (type, 12, "EF"); | |
380 | append_flags_type_flag (type, 13, "EC"); | |
2d457077 | 381 | |
209bd28e UW |
382 | tdep->sparc_psr_type = type; |
383 | } | |
384 | ||
385 | return tdep->sparc_psr_type; | |
386 | } | |
387 | ||
388 | static struct type * | |
389 | sparc_fsr_type (struct gdbarch *gdbarch) | |
2d457077 | 390 | { |
209bd28e UW |
391 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
392 | ||
393 | if (!tdep->sparc_fsr_type) | |
394 | { | |
395 | struct type *type; | |
396 | ||
e9bb382b | 397 | type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 4); |
209bd28e UW |
398 | append_flags_type_flag (type, 0, "NXA"); |
399 | append_flags_type_flag (type, 1, "DZA"); | |
400 | append_flags_type_flag (type, 2, "UFA"); | |
401 | append_flags_type_flag (type, 3, "OFA"); | |
402 | append_flags_type_flag (type, 4, "NVA"); | |
403 | append_flags_type_flag (type, 5, "NXC"); | |
404 | append_flags_type_flag (type, 6, "DZC"); | |
405 | append_flags_type_flag (type, 7, "UFC"); | |
406 | append_flags_type_flag (type, 8, "OFC"); | |
407 | append_flags_type_flag (type, 9, "NVC"); | |
408 | append_flags_type_flag (type, 22, "NS"); | |
409 | append_flags_type_flag (type, 23, "NXM"); | |
410 | append_flags_type_flag (type, 24, "DZM"); | |
411 | append_flags_type_flag (type, 25, "UFM"); | |
412 | append_flags_type_flag (type, 26, "OFM"); | |
413 | append_flags_type_flag (type, 27, "NVM"); | |
414 | ||
415 | tdep->sparc_fsr_type = type; | |
416 | } | |
417 | ||
418 | return tdep->sparc_fsr_type; | |
2d457077 | 419 | } |
386c036b | 420 | |
7a36499a IR |
421 | /* Return the GDB type object for the "standard" data type of data in |
422 | pseudo register REGNUM. */ | |
423 | ||
424 | static struct type * | |
425 | sparc32_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
426 | { | |
427 | regnum -= gdbarch_num_regs (gdbarch); | |
428 | ||
429 | if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) | |
430 | return builtin_type (gdbarch)->builtin_double; | |
431 | ||
432 | internal_error (__FILE__, __LINE__, | |
433 | _("sparc32_pseudo_register_type: bad register number %d"), | |
434 | regnum); | |
435 | } | |
436 | ||
386c036b | 437 | /* Return the GDB type object for the "standard" data type of data in |
c378eb4e | 438 | register REGNUM. */ |
386c036b MK |
439 | |
440 | static struct type * | |
441 | sparc32_register_type (struct gdbarch *gdbarch, int regnum) | |
442 | { | |
3f7b46f2 IR |
443 | if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
444 | return tdesc_register_type (gdbarch, regnum); | |
445 | ||
386c036b | 446 | if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) |
0dfff4cb | 447 | return builtin_type (gdbarch)->builtin_float; |
386c036b | 448 | |
386c036b | 449 | if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) |
0dfff4cb | 450 | return builtin_type (gdbarch)->builtin_data_ptr; |
386c036b MK |
451 | |
452 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) | |
0dfff4cb | 453 | return builtin_type (gdbarch)->builtin_func_ptr; |
386c036b | 454 | |
2d457077 | 455 | if (regnum == SPARC32_PSR_REGNUM) |
209bd28e | 456 | return sparc_psr_type (gdbarch); |
2d457077 MK |
457 | |
458 | if (regnum == SPARC32_FSR_REGNUM) | |
209bd28e | 459 | return sparc_fsr_type (gdbarch); |
2d457077 | 460 | |
7a36499a IR |
461 | if (regnum >= gdbarch_num_regs (gdbarch)) |
462 | return sparc32_pseudo_register_type (gdbarch, regnum); | |
463 | ||
df4df182 | 464 | return builtin_type (gdbarch)->builtin_int32; |
386c036b MK |
465 | } |
466 | ||
05d1431c | 467 | static enum register_status |
386c036b MK |
468 | sparc32_pseudo_register_read (struct gdbarch *gdbarch, |
469 | struct regcache *regcache, | |
e1613aba | 470 | int regnum, gdb_byte *buf) |
386c036b | 471 | { |
05d1431c PA |
472 | enum register_status status; |
473 | ||
7a36499a | 474 | regnum -= gdbarch_num_regs (gdbarch); |
386c036b MK |
475 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); |
476 | ||
477 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
05d1431c PA |
478 | status = regcache_raw_read (regcache, regnum, buf); |
479 | if (status == REG_VALID) | |
480 | status = regcache_raw_read (regcache, regnum + 1, buf + 4); | |
481 | return status; | |
386c036b MK |
482 | } |
483 | ||
484 | static void | |
485 | sparc32_pseudo_register_write (struct gdbarch *gdbarch, | |
486 | struct regcache *regcache, | |
e1613aba | 487 | int regnum, const gdb_byte *buf) |
386c036b | 488 | { |
7a36499a | 489 | regnum -= gdbarch_num_regs (gdbarch); |
386c036b MK |
490 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); |
491 | ||
492 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
493 | regcache_raw_write (regcache, regnum, buf); | |
e1613aba | 494 | regcache_raw_write (regcache, regnum + 1, buf + 4); |
386c036b MK |
495 | } |
496 | \f | |
c9cf6e20 | 497 | /* Implement the stack_frame_destroyed_p gdbarch method. */ |
961842b2 JM |
498 | |
499 | int | |
c9cf6e20 | 500 | sparc_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
961842b2 JM |
501 | { |
502 | /* This function must return true if we are one instruction after an | |
503 | instruction that destroyed the stack frame of the current | |
504 | function. The SPARC instructions used to restore the callers | |
505 | stack frame are RESTORE and RETURN/RETT. | |
506 | ||
507 | Of these RETURN/RETT is a branch instruction and thus we return | |
508 | true if we are in its delay slot. | |
509 | ||
510 | RESTORE is almost always found in the delay slot of a branch | |
511 | instruction that transfers control to the caller, such as JMPL. | |
512 | Thus the next instruction is in the caller frame and we don't | |
513 | need to do anything about it. */ | |
514 | ||
515 | unsigned int insn = sparc_fetch_instruction (pc - 4); | |
516 | ||
517 | return X_RETTURN (insn); | |
518 | } | |
519 | \f | |
386c036b | 520 | |
49a45ecf JB |
521 | static CORE_ADDR |
522 | sparc32_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) | |
523 | { | |
524 | /* The ABI requires double-word alignment. */ | |
525 | return address & ~0x7; | |
526 | } | |
527 | ||
386c036b MK |
528 | static CORE_ADDR |
529 | sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
82585c72 | 530 | CORE_ADDR funcaddr, |
386c036b MK |
531 | struct value **args, int nargs, |
532 | struct type *value_type, | |
e4fd649a UW |
533 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, |
534 | struct regcache *regcache) | |
c906108c | 535 | { |
e17a4113 UW |
536 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
537 | ||
386c036b MK |
538 | *bp_addr = sp - 4; |
539 | *real_pc = funcaddr; | |
540 | ||
d80b854b | 541 | if (using_struct_return (gdbarch, NULL, value_type)) |
c906108c | 542 | { |
e1613aba | 543 | gdb_byte buf[4]; |
386c036b MK |
544 | |
545 | /* This is an UNIMP instruction. */ | |
e17a4113 UW |
546 | store_unsigned_integer (buf, 4, byte_order, |
547 | TYPE_LENGTH (value_type) & 0x1fff); | |
386c036b MK |
548 | write_memory (sp - 8, buf, 4); |
549 | return sp - 8; | |
c906108c SS |
550 | } |
551 | ||
386c036b MK |
552 | return sp - 4; |
553 | } | |
554 | ||
555 | static CORE_ADDR | |
556 | sparc32_store_arguments (struct regcache *regcache, int nargs, | |
557 | struct value **args, CORE_ADDR sp, | |
558 | int struct_return, CORE_ADDR struct_addr) | |
559 | { | |
df4df182 | 560 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
e17a4113 | 561 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
386c036b MK |
562 | /* Number of words in the "parameter array". */ |
563 | int num_elements = 0; | |
564 | int element = 0; | |
565 | int i; | |
566 | ||
567 | for (i = 0; i < nargs; i++) | |
c906108c | 568 | { |
4991999e | 569 | struct type *type = value_type (args[i]); |
386c036b MK |
570 | int len = TYPE_LENGTH (type); |
571 | ||
572 | if (sparc_structure_or_union_p (type) | |
fe10a582 DM |
573 | || (sparc_floating_p (type) && len == 16) |
574 | || sparc_complex_floating_p (type)) | |
c906108c | 575 | { |
386c036b MK |
576 | /* Structure, Union and Quad-Precision Arguments. */ |
577 | sp -= len; | |
578 | ||
579 | /* Use doubleword alignment for these values. That's always | |
580 | correct, and wasting a few bytes shouldn't be a problem. */ | |
581 | sp &= ~0x7; | |
582 | ||
0fd88904 | 583 | write_memory (sp, value_contents (args[i]), len); |
386c036b MK |
584 | args[i] = value_from_pointer (lookup_pointer_type (type), sp); |
585 | num_elements++; | |
586 | } | |
587 | else if (sparc_floating_p (type)) | |
588 | { | |
589 | /* Floating arguments. */ | |
590 | gdb_assert (len == 4 || len == 8); | |
591 | num_elements += (len / 4); | |
c906108c | 592 | } |
c5aa993b JM |
593 | else |
594 | { | |
386c036b MK |
595 | /* Integral and pointer arguments. */ |
596 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
597 | ||
598 | if (len < 4) | |
df4df182 UW |
599 | args[i] = value_cast (builtin_type (gdbarch)->builtin_int32, |
600 | args[i]); | |
386c036b | 601 | num_elements += ((len + 3) / 4); |
c5aa993b | 602 | } |
c906108c | 603 | } |
c906108c | 604 | |
386c036b | 605 | /* Always allocate at least six words. */ |
325fac50 | 606 | sp -= std::max (6, num_elements) * 4; |
c906108c | 607 | |
386c036b MK |
608 | /* The psABI says that "Software convention requires space for the |
609 | struct/union return value pointer, even if the word is unused." */ | |
610 | sp -= 4; | |
c906108c | 611 | |
386c036b MK |
612 | /* The psABI says that "Although software convention and the |
613 | operating system require every stack frame to be doubleword | |
614 | aligned." */ | |
615 | sp &= ~0x7; | |
c906108c | 616 | |
386c036b | 617 | for (i = 0; i < nargs; i++) |
c906108c | 618 | { |
0fd88904 | 619 | const bfd_byte *valbuf = value_contents (args[i]); |
4991999e | 620 | struct type *type = value_type (args[i]); |
386c036b | 621 | int len = TYPE_LENGTH (type); |
c906108c | 622 | |
386c036b | 623 | gdb_assert (len == 4 || len == 8); |
c906108c | 624 | |
386c036b MK |
625 | if (element < 6) |
626 | { | |
627 | int regnum = SPARC_O0_REGNUM + element; | |
c906108c | 628 | |
386c036b MK |
629 | regcache_cooked_write (regcache, regnum, valbuf); |
630 | if (len > 4 && element < 5) | |
631 | regcache_cooked_write (regcache, regnum + 1, valbuf + 4); | |
632 | } | |
5af923b0 | 633 | |
386c036b MK |
634 | /* Always store the argument in memory. */ |
635 | write_memory (sp + 4 + element * 4, valbuf, len); | |
636 | element += len / 4; | |
637 | } | |
c906108c | 638 | |
386c036b | 639 | gdb_assert (element == num_elements); |
c906108c | 640 | |
386c036b | 641 | if (struct_return) |
c906108c | 642 | { |
e1613aba | 643 | gdb_byte buf[4]; |
c906108c | 644 | |
e17a4113 | 645 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
386c036b MK |
646 | write_memory (sp, buf, 4); |
647 | } | |
c906108c | 648 | |
386c036b | 649 | return sp; |
c906108c SS |
650 | } |
651 | ||
386c036b | 652 | static CORE_ADDR |
7d9b040b | 653 | sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
386c036b MK |
654 | struct regcache *regcache, CORE_ADDR bp_addr, |
655 | int nargs, struct value **args, CORE_ADDR sp, | |
656 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 657 | { |
386c036b MK |
658 | CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8)); |
659 | ||
660 | /* Set return address. */ | |
661 | regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); | |
662 | ||
663 | /* Set up function arguments. */ | |
664 | sp = sparc32_store_arguments (regcache, nargs, args, sp, | |
665 | struct_return, struct_addr); | |
666 | ||
667 | /* Allocate the 16-word window save area. */ | |
668 | sp -= 16 * 4; | |
c906108c | 669 | |
386c036b MK |
670 | /* Stack should be doubleword aligned at this point. */ |
671 | gdb_assert (sp % 8 == 0); | |
c906108c | 672 | |
386c036b MK |
673 | /* Finally, update the stack pointer. */ |
674 | regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); | |
675 | ||
676 | return sp; | |
677 | } | |
678 | \f | |
c906108c | 679 | |
386c036b MK |
680 | /* Use the program counter to determine the contents and size of a |
681 | breakpoint instruction. Return a pointer to a string of bytes that | |
682 | encode a breakpoint instruction, store the length of the string in | |
683 | *LEN and optionally adjust *PC to point to the correct memory | |
684 | location for inserting the breakpoint. */ | |
04180708 | 685 | constexpr gdb_byte sparc_break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; |
c5aa993b | 686 | |
04180708 | 687 | typedef BP_MANIPULATION (sparc_break_insn) sparc_breakpoint; |
386c036b | 688 | \f |
c906108c | 689 | |
386c036b | 690 | /* Allocate and initialize a frame cache. */ |
c906108c | 691 | |
386c036b MK |
692 | static struct sparc_frame_cache * |
693 | sparc_alloc_frame_cache (void) | |
694 | { | |
695 | struct sparc_frame_cache *cache; | |
c906108c | 696 | |
386c036b | 697 | cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); |
c906108c | 698 | |
386c036b MK |
699 | /* Base address. */ |
700 | cache->base = 0; | |
701 | cache->pc = 0; | |
c906108c | 702 | |
386c036b MK |
703 | /* Frameless until proven otherwise. */ |
704 | cache->frameless_p = 1; | |
369c397b JB |
705 | cache->frame_offset = 0; |
706 | cache->saved_regs_mask = 0; | |
707 | cache->copied_regs_mask = 0; | |
386c036b MK |
708 | cache->struct_return_p = 0; |
709 | ||
710 | return cache; | |
711 | } | |
712 | ||
b0b92586 JB |
713 | /* GCC generates several well-known sequences of instructions at the begining |
714 | of each function prologue when compiling with -fstack-check. If one of | |
715 | such sequences starts at START_PC, then return the address of the | |
716 | instruction immediately past this sequence. Otherwise, return START_PC. */ | |
717 | ||
718 | static CORE_ADDR | |
719 | sparc_skip_stack_check (const CORE_ADDR start_pc) | |
720 | { | |
721 | CORE_ADDR pc = start_pc; | |
722 | unsigned long insn; | |
2067c8d4 | 723 | int probing_loop = 0; |
b0b92586 JB |
724 | |
725 | /* With GCC, all stack checking sequences begin with the same two | |
2067c8d4 | 726 | instructions, plus an optional one in the case of a probing loop: |
b0b92586 | 727 | |
2067c8d4 JG |
728 | sethi <some immediate>, %g1 |
729 | sub %sp, %g1, %g1 | |
730 | ||
731 | or: | |
732 | ||
733 | sethi <some immediate>, %g1 | |
734 | sethi <some immediate>, %g4 | |
735 | sub %sp, %g1, %g1 | |
736 | ||
737 | or: | |
738 | ||
739 | sethi <some immediate>, %g1 | |
740 | sub %sp, %g1, %g1 | |
741 | sethi <some immediate>, %g4 | |
742 | ||
743 | If the optional instruction is found (setting g4), assume that a | |
744 | probing loop will follow. */ | |
745 | ||
746 | /* sethi <some immediate>, %g1 */ | |
b0b92586 JB |
747 | insn = sparc_fetch_instruction (pc); |
748 | pc = pc + 4; | |
749 | if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1)) | |
750 | return start_pc; | |
751 | ||
2067c8d4 | 752 | /* optional: sethi <some immediate>, %g4 */ |
b0b92586 JB |
753 | insn = sparc_fetch_instruction (pc); |
754 | pc = pc + 4; | |
2067c8d4 JG |
755 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) |
756 | { | |
757 | probing_loop = 1; | |
758 | insn = sparc_fetch_instruction (pc); | |
759 | pc = pc + 4; | |
760 | } | |
761 | ||
762 | /* sub %sp, %g1, %g1 */ | |
b0b92586 JB |
763 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) |
764 | && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1)) | |
765 | return start_pc; | |
766 | ||
767 | insn = sparc_fetch_instruction (pc); | |
768 | pc = pc + 4; | |
769 | ||
2067c8d4 JG |
770 | /* optional: sethi <some immediate>, %g4 */ |
771 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) | |
772 | { | |
773 | probing_loop = 1; | |
774 | insn = sparc_fetch_instruction (pc); | |
775 | pc = pc + 4; | |
776 | } | |
777 | ||
b0b92586 JB |
778 | /* First possible sequence: |
779 | [first two instructions above] | |
780 | clr [%g1 - some immediate] */ | |
781 | ||
782 | /* clr [%g1 - some immediate] */ | |
783 | if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
784 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
785 | { | |
786 | /* Valid stack-check sequence, return the new PC. */ | |
787 | return pc; | |
788 | } | |
789 | ||
790 | /* Second possible sequence: A small number of probes. | |
791 | [first two instructions above] | |
792 | clr [%g1] | |
793 | add %g1, -<some immediate>, %g1 | |
794 | clr [%g1] | |
795 | [repeat the two instructions above any (small) number of times] | |
796 | clr [%g1 - some immediate] */ | |
797 | ||
798 | /* clr [%g1] */ | |
799 | else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
800 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
801 | { | |
802 | while (1) | |
803 | { | |
804 | /* add %g1, -<some immediate>, %g1 */ | |
805 | insn = sparc_fetch_instruction (pc); | |
806 | pc = pc + 4; | |
807 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
808 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
809 | break; | |
810 | ||
811 | /* clr [%g1] */ | |
812 | insn = sparc_fetch_instruction (pc); | |
813 | pc = pc + 4; | |
814 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
815 | && X_RD (insn) == 0 && X_RS1 (insn) == 1)) | |
816 | return start_pc; | |
817 | } | |
818 | ||
819 | /* clr [%g1 - some immediate] */ | |
820 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
821 | && X_RS1 (insn) == 1 && X_RD (insn) == 0)) | |
822 | return start_pc; | |
823 | ||
824 | /* We found a valid stack-check sequence, return the new PC. */ | |
825 | return pc; | |
826 | } | |
827 | ||
828 | /* Third sequence: A probing loop. | |
2067c8d4 | 829 | [first three instructions above] |
b0b92586 JB |
830 | sub %g1, %g4, %g4 |
831 | cmp %g1, %g4 | |
832 | be <disp> | |
833 | add %g1, -<some immediate>, %g1 | |
834 | ba <disp> | |
835 | clr [%g1] | |
2067c8d4 JG |
836 | |
837 | And an optional last probe for the remainder: | |
838 | ||
b0b92586 JB |
839 | clr [%g4 - some immediate] */ |
840 | ||
2067c8d4 | 841 | if (probing_loop) |
b0b92586 JB |
842 | { |
843 | /* sub %g1, %g4, %g4 */ | |
b0b92586 JB |
844 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) |
845 | && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
846 | return start_pc; | |
847 | ||
848 | /* cmp %g1, %g4 */ | |
849 | insn = sparc_fetch_instruction (pc); | |
850 | pc = pc + 4; | |
851 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn) | |
852 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
853 | return start_pc; | |
854 | ||
855 | /* be <disp> */ | |
856 | insn = sparc_fetch_instruction (pc); | |
857 | pc = pc + 4; | |
858 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1)) | |
859 | return start_pc; | |
860 | ||
861 | /* add %g1, -<some immediate>, %g1 */ | |
862 | insn = sparc_fetch_instruction (pc); | |
863 | pc = pc + 4; | |
864 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
865 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
866 | return start_pc; | |
867 | ||
868 | /* ba <disp> */ | |
869 | insn = sparc_fetch_instruction (pc); | |
870 | pc = pc + 4; | |
871 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8)) | |
872 | return start_pc; | |
873 | ||
2067c8d4 | 874 | /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */ |
b0b92586 JB |
875 | insn = sparc_fetch_instruction (pc); |
876 | pc = pc + 4; | |
2067c8d4 JG |
877 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 |
878 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 | |
879 | && (!X_I(insn) || X_SIMM13 (insn) == 0))) | |
b0b92586 JB |
880 | return start_pc; |
881 | ||
2067c8d4 JG |
882 | /* We found a valid stack-check sequence, return the new PC. */ |
883 | ||
884 | /* optional: clr [%g4 - some immediate] */ | |
b0b92586 JB |
885 | insn = sparc_fetch_instruction (pc); |
886 | pc = pc + 4; | |
887 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
888 | && X_RS1 (insn) == 4 && X_RD (insn) == 0)) | |
2067c8d4 JG |
889 | return pc - 4; |
890 | else | |
891 | return pc; | |
b0b92586 JB |
892 | } |
893 | ||
894 | /* No stack check code in our prologue, return the start_pc. */ | |
895 | return start_pc; | |
896 | } | |
897 | ||
369c397b JB |
898 | /* Record the effect of a SAVE instruction on CACHE. */ |
899 | ||
900 | void | |
901 | sparc_record_save_insn (struct sparc_frame_cache *cache) | |
902 | { | |
903 | /* The frame is set up. */ | |
904 | cache->frameless_p = 0; | |
905 | ||
906 | /* The frame pointer contains the CFA. */ | |
907 | cache->frame_offset = 0; | |
908 | ||
909 | /* The `local' and `in' registers are all saved. */ | |
910 | cache->saved_regs_mask = 0xffff; | |
911 | ||
912 | /* The `out' registers are all renamed. */ | |
913 | cache->copied_regs_mask = 0xff; | |
914 | } | |
915 | ||
916 | /* Do a full analysis of the prologue at PC and update CACHE accordingly. | |
917 | Bail out early if CURRENT_PC is reached. Return the address where | |
918 | the analysis stopped. | |
919 | ||
920 | We handle both the traditional register window model and the single | |
921 | register window (aka flat) model. */ | |
922 | ||
386c036b | 923 | CORE_ADDR |
be8626e0 MD |
924 | sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, |
925 | CORE_ADDR current_pc, struct sparc_frame_cache *cache) | |
c906108c | 926 | { |
be8626e0 | 927 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
386c036b MK |
928 | unsigned long insn; |
929 | int offset = 0; | |
c906108c | 930 | int dest = -1; |
c906108c | 931 | |
b0b92586 JB |
932 | pc = sparc_skip_stack_check (pc); |
933 | ||
386c036b MK |
934 | if (current_pc <= pc) |
935 | return current_pc; | |
936 | ||
937 | /* We have to handle to "Procedure Linkage Table" (PLT) special. On | |
938 | SPARC the linker usually defines a symbol (typically | |
939 | _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. | |
940 | This symbol makes us end up here with PC pointing at the start of | |
941 | the PLT and CURRENT_PC probably pointing at a PLT entry. If we | |
942 | would do our normal prologue analysis, we would probably conclude | |
943 | that we've got a frame when in reality we don't, since the | |
944 | dynamic linker patches up the first PLT with some code that | |
945 | starts with a SAVE instruction. Patch up PC such that it points | |
946 | at the start of our PLT entry. */ | |
3e5d3a5a | 947 | if (tdep->plt_entry_size > 0 && in_plt_section (current_pc)) |
386c036b | 948 | pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); |
c906108c | 949 | |
386c036b MK |
950 | insn = sparc_fetch_instruction (pc); |
951 | ||
369c397b JB |
952 | /* Recognize store insns and record their sources. */ |
953 | while (X_OP (insn) == 3 | |
954 | && (X_OP3 (insn) == 0x4 /* stw */ | |
955 | || X_OP3 (insn) == 0x7 /* std */ | |
956 | || X_OP3 (insn) == 0xe) /* stx */ | |
957 | && X_RS1 (insn) == SPARC_SP_REGNUM) | |
958 | { | |
959 | int regnum = X_RD (insn); | |
960 | ||
961 | /* Recognize stores into the corresponding stack slots. */ | |
962 | if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM | |
963 | && ((X_I (insn) | |
964 | && X_SIMM13 (insn) == (X_OP3 (insn) == 0xe | |
965 | ? (regnum - SPARC_L0_REGNUM) * 8 + BIAS | |
966 | : (regnum - SPARC_L0_REGNUM) * 4)) | |
967 | || (!X_I (insn) && regnum == SPARC_L0_REGNUM))) | |
968 | { | |
969 | cache->saved_regs_mask |= (1 << (regnum - SPARC_L0_REGNUM)); | |
970 | if (X_OP3 (insn) == 0x7) | |
971 | cache->saved_regs_mask |= (1 << (regnum + 1 - SPARC_L0_REGNUM)); | |
972 | } | |
973 | ||
974 | offset += 4; | |
975 | ||
976 | insn = sparc_fetch_instruction (pc + offset); | |
977 | } | |
978 | ||
386c036b MK |
979 | /* Recognize a SETHI insn and record its destination. */ |
980 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) | |
c906108c SS |
981 | { |
982 | dest = X_RD (insn); | |
386c036b MK |
983 | offset += 4; |
984 | ||
369c397b | 985 | insn = sparc_fetch_instruction (pc + offset); |
c906108c SS |
986 | } |
987 | ||
386c036b MK |
988 | /* Allow for an arithmetic operation on DEST or %g1. */ |
989 | if (X_OP (insn) == 2 && X_I (insn) | |
c906108c SS |
990 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) |
991 | { | |
386c036b | 992 | offset += 4; |
c906108c | 993 | |
369c397b | 994 | insn = sparc_fetch_instruction (pc + offset); |
c906108c | 995 | } |
c906108c | 996 | |
386c036b MK |
997 | /* Check for the SAVE instruction that sets up the frame. */ |
998 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) | |
c906108c | 999 | { |
369c397b JB |
1000 | sparc_record_save_insn (cache); |
1001 | offset += 4; | |
1002 | return pc + offset; | |
1003 | } | |
1004 | ||
1005 | /* Check for an arithmetic operation on %sp. */ | |
1006 | if (X_OP (insn) == 2 | |
1007 | && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) | |
1008 | && X_RS1 (insn) == SPARC_SP_REGNUM | |
1009 | && X_RD (insn) == SPARC_SP_REGNUM) | |
1010 | { | |
1011 | if (X_I (insn)) | |
1012 | { | |
1013 | cache->frame_offset = X_SIMM13 (insn); | |
1014 | if (X_OP3 (insn) == 0) | |
1015 | cache->frame_offset = -cache->frame_offset; | |
1016 | } | |
1017 | offset += 4; | |
1018 | ||
1019 | insn = sparc_fetch_instruction (pc + offset); | |
1020 | ||
1021 | /* Check for an arithmetic operation that sets up the frame. */ | |
1022 | if (X_OP (insn) == 2 | |
1023 | && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) | |
1024 | && X_RS1 (insn) == SPARC_SP_REGNUM | |
1025 | && X_RD (insn) == SPARC_FP_REGNUM) | |
1026 | { | |
1027 | cache->frameless_p = 0; | |
1028 | cache->frame_offset = 0; | |
1029 | /* We could check that the amount subtracted to %sp above is the | |
1030 | same as the one added here, but this seems superfluous. */ | |
1031 | cache->copied_regs_mask |= 0x40; | |
1032 | offset += 4; | |
1033 | ||
1034 | insn = sparc_fetch_instruction (pc + offset); | |
1035 | } | |
1036 | ||
1037 | /* Check for a move (or) operation that copies the return register. */ | |
1038 | if (X_OP (insn) == 2 | |
1039 | && X_OP3 (insn) == 0x2 | |
1040 | && !X_I (insn) | |
1041 | && X_RS1 (insn) == SPARC_G0_REGNUM | |
1042 | && X_RS2 (insn) == SPARC_O7_REGNUM | |
1043 | && X_RD (insn) == SPARC_I7_REGNUM) | |
1044 | { | |
1045 | cache->copied_regs_mask |= 0x80; | |
1046 | offset += 4; | |
1047 | } | |
1048 | ||
1049 | return pc + offset; | |
c906108c SS |
1050 | } |
1051 | ||
1052 | return pc; | |
1053 | } | |
1054 | ||
386c036b | 1055 | static CORE_ADDR |
236369e7 | 1056 | sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) |
386c036b MK |
1057 | { |
1058 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
236369e7 | 1059 | return frame_unwind_register_unsigned (this_frame, tdep->pc_regnum); |
386c036b MK |
1060 | } |
1061 | ||
1062 | /* Return PC of first real instruction of the function starting at | |
1063 | START_PC. */ | |
f510d44e | 1064 | |
386c036b | 1065 | static CORE_ADDR |
6093d2eb | 1066 | sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1067 | { |
f510d44e DM |
1068 | struct symtab_and_line sal; |
1069 | CORE_ADDR func_start, func_end; | |
386c036b | 1070 | struct sparc_frame_cache cache; |
f510d44e DM |
1071 | |
1072 | /* This is the preferred method, find the end of the prologue by | |
1073 | using the debugging information. */ | |
1074 | if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) | |
1075 | { | |
1076 | sal = find_pc_line (func_start, 0); | |
1077 | ||
1078 | if (sal.end < func_end | |
1079 | && start_pc <= sal.end) | |
1080 | return sal.end; | |
1081 | } | |
1082 | ||
be8626e0 | 1083 | start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache); |
075ccec8 MK |
1084 | |
1085 | /* The psABI says that "Although the first 6 words of arguments | |
1086 | reside in registers, the standard stack frame reserves space for | |
1087 | them.". It also suggests that a function may use that space to | |
1088 | "write incoming arguments 0 to 5" into that space, and that's | |
1089 | indeed what GCC seems to be doing. In that case GCC will | |
1090 | generate debug information that points to the stack slots instead | |
1091 | of the registers, so we should consider the instructions that | |
369c397b | 1092 | write out these incoming arguments onto the stack. */ |
075ccec8 | 1093 | |
369c397b | 1094 | while (1) |
075ccec8 MK |
1095 | { |
1096 | unsigned long insn = sparc_fetch_instruction (start_pc); | |
1097 | ||
369c397b JB |
1098 | /* Recognize instructions that store incoming arguments into the |
1099 | corresponding stack slots. */ | |
1100 | if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 | |
1101 | && X_I (insn) && X_RS1 (insn) == SPARC_FP_REGNUM) | |
075ccec8 | 1102 | { |
369c397b JB |
1103 | int regnum = X_RD (insn); |
1104 | ||
1105 | /* Case of arguments still in %o[0..5]. */ | |
1106 | if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O5_REGNUM | |
1107 | && !(cache.copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM))) | |
1108 | && X_SIMM13 (insn) == 68 + (regnum - SPARC_O0_REGNUM) * 4) | |
1109 | { | |
1110 | start_pc += 4; | |
1111 | continue; | |
1112 | } | |
1113 | ||
1114 | /* Case of arguments copied into %i[0..5]. */ | |
1115 | if (regnum >= SPARC_I0_REGNUM && regnum <= SPARC_I5_REGNUM | |
1116 | && (cache.copied_regs_mask & (1 << (regnum - SPARC_I0_REGNUM))) | |
1117 | && X_SIMM13 (insn) == 68 + (regnum - SPARC_I0_REGNUM) * 4) | |
1118 | { | |
1119 | start_pc += 4; | |
1120 | continue; | |
1121 | } | |
075ccec8 MK |
1122 | } |
1123 | ||
1124 | break; | |
1125 | } | |
1126 | ||
1127 | return start_pc; | |
c906108c SS |
1128 | } |
1129 | ||
386c036b | 1130 | /* Normal frames. */ |
9319a2fe | 1131 | |
386c036b | 1132 | struct sparc_frame_cache * |
236369e7 | 1133 | sparc_frame_cache (struct frame_info *this_frame, void **this_cache) |
9319a2fe | 1134 | { |
386c036b | 1135 | struct sparc_frame_cache *cache; |
9319a2fe | 1136 | |
386c036b | 1137 | if (*this_cache) |
19ba03f4 | 1138 | return (struct sparc_frame_cache *) *this_cache; |
c906108c | 1139 | |
386c036b MK |
1140 | cache = sparc_alloc_frame_cache (); |
1141 | *this_cache = cache; | |
c906108c | 1142 | |
236369e7 | 1143 | cache->pc = get_frame_func (this_frame); |
386c036b | 1144 | if (cache->pc != 0) |
236369e7 JB |
1145 | sparc_analyze_prologue (get_frame_arch (this_frame), cache->pc, |
1146 | get_frame_pc (this_frame), cache); | |
386c036b MK |
1147 | |
1148 | if (cache->frameless_p) | |
c906108c | 1149 | { |
cbeae229 MK |
1150 | /* This function is frameless, so %fp (%i6) holds the frame |
1151 | pointer for our calling frame. Use %sp (%o6) as this frame's | |
1152 | base address. */ | |
1153 | cache->base = | |
236369e7 | 1154 | get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
cbeae229 MK |
1155 | } |
1156 | else | |
1157 | { | |
1158 | /* For normal frames, %fp (%i6) holds the frame pointer, the | |
1159 | base address for the current stack frame. */ | |
1160 | cache->base = | |
236369e7 | 1161 | get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM); |
c906108c | 1162 | } |
c906108c | 1163 | |
369c397b JB |
1164 | cache->base += cache->frame_offset; |
1165 | ||
5b2d44a0 MK |
1166 | if (cache->base & 1) |
1167 | cache->base += BIAS; | |
1168 | ||
386c036b | 1169 | return cache; |
c906108c | 1170 | } |
c906108c | 1171 | |
aff37fc1 DM |
1172 | static int |
1173 | sparc32_struct_return_from_sym (struct symbol *sym) | |
1174 | { | |
1175 | struct type *type = check_typedef (SYMBOL_TYPE (sym)); | |
1176 | enum type_code code = TYPE_CODE (type); | |
1177 | ||
1178 | if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) | |
1179 | { | |
1180 | type = check_typedef (TYPE_TARGET_TYPE (type)); | |
1181 | if (sparc_structure_or_union_p (type) | |
1182 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
1183 | return 1; | |
1184 | } | |
1185 | ||
1186 | return 0; | |
1187 | } | |
1188 | ||
386c036b | 1189 | struct sparc_frame_cache * |
236369e7 | 1190 | sparc32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 1191 | { |
386c036b MK |
1192 | struct sparc_frame_cache *cache; |
1193 | struct symbol *sym; | |
c906108c | 1194 | |
386c036b | 1195 | if (*this_cache) |
19ba03f4 | 1196 | return (struct sparc_frame_cache *) *this_cache; |
c906108c | 1197 | |
236369e7 | 1198 | cache = sparc_frame_cache (this_frame, this_cache); |
c906108c | 1199 | |
386c036b MK |
1200 | sym = find_pc_function (cache->pc); |
1201 | if (sym) | |
c906108c | 1202 | { |
aff37fc1 | 1203 | cache->struct_return_p = sparc32_struct_return_from_sym (sym); |
c906108c | 1204 | } |
5465445a JB |
1205 | else |
1206 | { | |
1207 | /* There is no debugging information for this function to | |
1208 | help us determine whether this function returns a struct | |
1209 | or not. So we rely on another heuristic which is to check | |
1210 | the instruction at the return address and see if this is | |
1211 | an "unimp" instruction. If it is, then it is a struct-return | |
1212 | function. */ | |
1213 | CORE_ADDR pc; | |
369c397b JB |
1214 | int regnum = |
1215 | (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; | |
5465445a | 1216 | |
236369e7 | 1217 | pc = get_frame_register_unsigned (this_frame, regnum) + 8; |
5465445a JB |
1218 | if (sparc_is_unimp_insn (pc)) |
1219 | cache->struct_return_p = 1; | |
1220 | } | |
c906108c | 1221 | |
386c036b MK |
1222 | return cache; |
1223 | } | |
1224 | ||
1225 | static void | |
236369e7 | 1226 | sparc32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
386c036b MK |
1227 | struct frame_id *this_id) |
1228 | { | |
1229 | struct sparc_frame_cache *cache = | |
236369e7 | 1230 | sparc32_frame_cache (this_frame, this_cache); |
386c036b MK |
1231 | |
1232 | /* This marks the outermost frame. */ | |
1233 | if (cache->base == 0) | |
1234 | return; | |
1235 | ||
1236 | (*this_id) = frame_id_build (cache->base, cache->pc); | |
1237 | } | |
c906108c | 1238 | |
236369e7 JB |
1239 | static struct value * |
1240 | sparc32_frame_prev_register (struct frame_info *this_frame, | |
1241 | void **this_cache, int regnum) | |
386c036b | 1242 | { |
e17a4113 | 1243 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
386c036b | 1244 | struct sparc_frame_cache *cache = |
236369e7 | 1245 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 1246 | |
386c036b | 1247 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) |
c906108c | 1248 | { |
236369e7 | 1249 | CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; |
386c036b | 1250 | |
236369e7 JB |
1251 | /* If this functions has a Structure, Union or Quad-Precision |
1252 | return value, we have to skip the UNIMP instruction that encodes | |
1253 | the size of the structure. */ | |
1254 | if (cache->struct_return_p) | |
1255 | pc += 4; | |
386c036b | 1256 | |
369c397b JB |
1257 | regnum = |
1258 | (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; | |
236369e7 JB |
1259 | pc += get_frame_register_unsigned (this_frame, regnum) + 8; |
1260 | return frame_unwind_got_constant (this_frame, regnum, pc); | |
c906108c SS |
1261 | } |
1262 | ||
42cdca6c MK |
1263 | /* Handle StackGhost. */ |
1264 | { | |
e17a4113 | 1265 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
42cdca6c MK |
1266 | |
1267 | if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM) | |
1268 | { | |
236369e7 JB |
1269 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
1270 | ULONGEST i7; | |
1271 | ||
1272 | /* Read the value in from memory. */ | |
1273 | i7 = get_frame_memory_unsigned (this_frame, addr, 4); | |
1274 | return frame_unwind_got_constant (this_frame, regnum, i7 ^ wcookie); | |
42cdca6c MK |
1275 | } |
1276 | } | |
1277 | ||
369c397b | 1278 | /* The previous frame's `local' and `in' registers may have been saved |
386c036b | 1279 | in the register save area. */ |
369c397b JB |
1280 | if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM |
1281 | && (cache->saved_regs_mask & (1 << (regnum - SPARC_L0_REGNUM)))) | |
c906108c | 1282 | { |
236369e7 | 1283 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
386c036b | 1284 | |
236369e7 | 1285 | return frame_unwind_got_memory (this_frame, regnum, addr); |
386c036b | 1286 | } |
c906108c | 1287 | |
369c397b JB |
1288 | /* The previous frame's `out' registers may be accessible as the current |
1289 | frame's `in' registers. */ | |
1290 | if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM | |
1291 | && (cache->copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM)))) | |
386c036b | 1292 | regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); |
5af923b0 | 1293 | |
236369e7 | 1294 | return frame_unwind_got_register (this_frame, regnum, regnum); |
386c036b | 1295 | } |
c906108c | 1296 | |
386c036b MK |
1297 | static const struct frame_unwind sparc32_frame_unwind = |
1298 | { | |
1299 | NORMAL_FRAME, | |
8fbca658 | 1300 | default_frame_unwind_stop_reason, |
386c036b | 1301 | sparc32_frame_this_id, |
236369e7 JB |
1302 | sparc32_frame_prev_register, |
1303 | NULL, | |
1304 | default_frame_sniffer | |
386c036b | 1305 | }; |
386c036b | 1306 | \f |
c906108c | 1307 | |
386c036b | 1308 | static CORE_ADDR |
236369e7 | 1309 | sparc32_frame_base_address (struct frame_info *this_frame, void **this_cache) |
386c036b MK |
1310 | { |
1311 | struct sparc_frame_cache *cache = | |
236369e7 | 1312 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 1313 | |
386c036b MK |
1314 | return cache->base; |
1315 | } | |
c906108c | 1316 | |
386c036b MK |
1317 | static const struct frame_base sparc32_frame_base = |
1318 | { | |
1319 | &sparc32_frame_unwind, | |
1320 | sparc32_frame_base_address, | |
1321 | sparc32_frame_base_address, | |
1322 | sparc32_frame_base_address | |
1323 | }; | |
c906108c | 1324 | |
386c036b | 1325 | static struct frame_id |
236369e7 | 1326 | sparc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
386c036b MK |
1327 | { |
1328 | CORE_ADDR sp; | |
5af923b0 | 1329 | |
236369e7 | 1330 | sp = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
5b2d44a0 MK |
1331 | if (sp & 1) |
1332 | sp += BIAS; | |
236369e7 | 1333 | return frame_id_build (sp, get_frame_pc (this_frame)); |
386c036b MK |
1334 | } |
1335 | \f | |
c906108c | 1336 | |
3923a2b2 MK |
1337 | /* Extract a function return value of TYPE from REGCACHE, and copy |
1338 | that into VALBUF. */ | |
5af923b0 | 1339 | |
386c036b MK |
1340 | static void |
1341 | sparc32_extract_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1342 | gdb_byte *valbuf) |
386c036b MK |
1343 | { |
1344 | int len = TYPE_LENGTH (type); | |
fe10a582 | 1345 | gdb_byte buf[32]; |
c906108c | 1346 | |
386c036b MK |
1347 | gdb_assert (!sparc_structure_or_union_p (type)); |
1348 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 1349 | |
fe10a582 | 1350 | if (sparc_floating_p (type) || sparc_complex_floating_p (type)) |
5af923b0 | 1351 | { |
386c036b MK |
1352 | /* Floating return values. */ |
1353 | regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf); | |
1354 | if (len > 4) | |
1355 | regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4); | |
fe10a582 DM |
1356 | if (len > 8) |
1357 | { | |
1358 | regcache_cooked_read (regcache, SPARC_F2_REGNUM, buf + 8); | |
1359 | regcache_cooked_read (regcache, SPARC_F3_REGNUM, buf + 12); | |
1360 | } | |
1361 | if (len > 16) | |
1362 | { | |
1363 | regcache_cooked_read (regcache, SPARC_F4_REGNUM, buf + 16); | |
1364 | regcache_cooked_read (regcache, SPARC_F5_REGNUM, buf + 20); | |
1365 | regcache_cooked_read (regcache, SPARC_F6_REGNUM, buf + 24); | |
1366 | regcache_cooked_read (regcache, SPARC_F7_REGNUM, buf + 28); | |
1367 | } | |
386c036b | 1368 | memcpy (valbuf, buf, len); |
5af923b0 MS |
1369 | } |
1370 | else | |
1371 | { | |
386c036b MK |
1372 | /* Integral and pointer return values. */ |
1373 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
c906108c | 1374 | |
386c036b MK |
1375 | regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); |
1376 | if (len > 4) | |
1377 | { | |
1378 | regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4); | |
1379 | gdb_assert (len == 8); | |
1380 | memcpy (valbuf, buf, 8); | |
1381 | } | |
1382 | else | |
1383 | { | |
1384 | /* Just stripping off any unused bytes should preserve the | |
1385 | signed-ness just fine. */ | |
1386 | memcpy (valbuf, buf + 4 - len, len); | |
1387 | } | |
1388 | } | |
1389 | } | |
c906108c | 1390 | |
3923a2b2 MK |
1391 | /* Store the function return value of type TYPE from VALBUF into |
1392 | REGCACHE. */ | |
c906108c | 1393 | |
386c036b MK |
1394 | static void |
1395 | sparc32_store_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1396 | const gdb_byte *valbuf) |
386c036b MK |
1397 | { |
1398 | int len = TYPE_LENGTH (type); | |
e1613aba | 1399 | gdb_byte buf[8]; |
c906108c | 1400 | |
386c036b MK |
1401 | gdb_assert (!sparc_structure_or_union_p (type)); |
1402 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
a9789a6b | 1403 | gdb_assert (len <= 8); |
c906108c | 1404 | |
fe10a582 | 1405 | if (sparc_floating_p (type) || sparc_complex_floating_p (type)) |
386c036b MK |
1406 | { |
1407 | /* Floating return values. */ | |
1408 | memcpy (buf, valbuf, len); | |
1409 | regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf); | |
1410 | if (len > 4) | |
1411 | regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4); | |
fe10a582 DM |
1412 | if (len > 8) |
1413 | { | |
1414 | regcache_cooked_write (regcache, SPARC_F2_REGNUM, buf + 8); | |
1415 | regcache_cooked_write (regcache, SPARC_F3_REGNUM, buf + 12); | |
1416 | } | |
1417 | if (len > 16) | |
1418 | { | |
1419 | regcache_cooked_write (regcache, SPARC_F4_REGNUM, buf + 16); | |
1420 | regcache_cooked_write (regcache, SPARC_F5_REGNUM, buf + 20); | |
1421 | regcache_cooked_write (regcache, SPARC_F6_REGNUM, buf + 24); | |
1422 | regcache_cooked_write (regcache, SPARC_F7_REGNUM, buf + 28); | |
1423 | } | |
386c036b MK |
1424 | } |
1425 | else | |
c906108c | 1426 | { |
386c036b MK |
1427 | /* Integral and pointer return values. */ |
1428 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
1429 | ||
1430 | if (len > 4) | |
2757dd86 | 1431 | { |
386c036b MK |
1432 | gdb_assert (len == 8); |
1433 | memcpy (buf, valbuf, 8); | |
1434 | regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4); | |
2757dd86 AC |
1435 | } |
1436 | else | |
1437 | { | |
386c036b MK |
1438 | /* ??? Do we need to do any sign-extension here? */ |
1439 | memcpy (buf + 4 - len, valbuf, len); | |
2757dd86 | 1440 | } |
386c036b | 1441 | regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); |
c906108c SS |
1442 | } |
1443 | } | |
1444 | ||
b9d4c5ed | 1445 | static enum return_value_convention |
6a3a010b | 1446 | sparc32_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
1447 | struct type *type, struct regcache *regcache, |
1448 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
b9d4c5ed | 1449 | { |
e17a4113 UW |
1450 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1451 | ||
0a8f48b9 MK |
1452 | /* The psABI says that "...every stack frame reserves the word at |
1453 | %fp+64. If a function returns a structure, union, or | |
1454 | quad-precision value, this word should hold the address of the | |
1455 | object into which the return value should be copied." This | |
1456 | guarantees that we can always find the return value, not just | |
1457 | before the function returns. */ | |
1458 | ||
b9d4c5ed MK |
1459 | if (sparc_structure_or_union_p (type) |
1460 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
0a8f48b9 | 1461 | { |
bbfdfe1c DM |
1462 | ULONGEST sp; |
1463 | CORE_ADDR addr; | |
1464 | ||
0a8f48b9 MK |
1465 | if (readbuf) |
1466 | { | |
0a8f48b9 | 1467 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); |
e17a4113 | 1468 | addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); |
0a8f48b9 MK |
1469 | read_memory (addr, readbuf, TYPE_LENGTH (type)); |
1470 | } | |
bbfdfe1c DM |
1471 | if (writebuf) |
1472 | { | |
1473 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1474 | addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); | |
1475 | write_memory (addr, writebuf, TYPE_LENGTH (type)); | |
1476 | } | |
0a8f48b9 MK |
1477 | |
1478 | return RETURN_VALUE_ABI_PRESERVES_ADDRESS; | |
1479 | } | |
b9d4c5ed MK |
1480 | |
1481 | if (readbuf) | |
1482 | sparc32_extract_return_value (type, regcache, readbuf); | |
1483 | if (writebuf) | |
1484 | sparc32_store_return_value (type, regcache, writebuf); | |
1485 | ||
1486 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1487 | } | |
1488 | ||
386c036b MK |
1489 | static int |
1490 | sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) | |
c906108c | 1491 | { |
386c036b | 1492 | return (sparc_structure_or_union_p (type) |
fe10a582 DM |
1493 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16) |
1494 | || sparc_complex_floating_p (type)); | |
386c036b | 1495 | } |
c906108c | 1496 | |
aff37fc1 | 1497 | static int |
4a4e5149 | 1498 | sparc32_dwarf2_struct_return_p (struct frame_info *this_frame) |
aff37fc1 | 1499 | { |
236369e7 | 1500 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
aff37fc1 DM |
1501 | struct symbol *sym = find_pc_function (pc); |
1502 | ||
1503 | if (sym) | |
1504 | return sparc32_struct_return_from_sym (sym); | |
1505 | return 0; | |
1506 | } | |
1507 | ||
f5a9b87d DM |
1508 | static void |
1509 | sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 | 1510 | struct dwarf2_frame_state_reg *reg, |
4a4e5149 | 1511 | struct frame_info *this_frame) |
f5a9b87d | 1512 | { |
aff37fc1 DM |
1513 | int off; |
1514 | ||
f5a9b87d DM |
1515 | switch (regnum) |
1516 | { | |
1517 | case SPARC_G0_REGNUM: | |
1518 | /* Since %g0 is always zero, there is no point in saving it, and | |
1519 | people will be inclined omit it from the CFI. Make sure we | |
1520 | don't warn about that. */ | |
1521 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
1522 | break; | |
1523 | case SPARC_SP_REGNUM: | |
1524 | reg->how = DWARF2_FRAME_REG_CFA; | |
1525 | break; | |
1526 | case SPARC32_PC_REGNUM: | |
f5a9b87d DM |
1527 | case SPARC32_NPC_REGNUM: |
1528 | reg->how = DWARF2_FRAME_REG_RA_OFFSET; | |
aff37fc1 | 1529 | off = 8; |
4a4e5149 | 1530 | if (sparc32_dwarf2_struct_return_p (this_frame)) |
aff37fc1 DM |
1531 | off += 4; |
1532 | if (regnum == SPARC32_NPC_REGNUM) | |
1533 | off += 4; | |
1534 | reg->loc.offset = off; | |
f5a9b87d DM |
1535 | break; |
1536 | } | |
1537 | } | |
1538 | ||
386c036b MK |
1539 | \f |
1540 | /* The SPARC Architecture doesn't have hardware single-step support, | |
1541 | and most operating systems don't implement it either, so we provide | |
1542 | software single-step mechanism. */ | |
c906108c | 1543 | |
386c036b | 1544 | static CORE_ADDR |
cd76b525 | 1545 | sparc_analyze_control_transfer (struct regcache *regcache, |
c893be75 | 1546 | CORE_ADDR pc, CORE_ADDR *npc) |
386c036b MK |
1547 | { |
1548 | unsigned long insn = sparc_fetch_instruction (pc); | |
1549 | int conditional_p = X_COND (insn) & 0x7; | |
8d1b3521 | 1550 | int branch_p = 0, fused_p = 0; |
386c036b | 1551 | long offset = 0; /* Must be signed for sign-extend. */ |
c906108c | 1552 | |
8d1b3521 | 1553 | if (X_OP (insn) == 0 && X_OP2 (insn) == 3) |
c906108c | 1554 | { |
8d1b3521 DM |
1555 | if ((insn & 0x10000000) == 0) |
1556 | { | |
1557 | /* Branch on Integer Register with Prediction (BPr). */ | |
1558 | branch_p = 1; | |
1559 | conditional_p = 1; | |
1560 | } | |
1561 | else | |
1562 | { | |
1563 | /* Compare and Branch */ | |
1564 | branch_p = 1; | |
1565 | fused_p = 1; | |
1566 | offset = 4 * X_DISP10 (insn); | |
1567 | } | |
c906108c | 1568 | } |
386c036b | 1569 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) |
c906108c | 1570 | { |
386c036b MK |
1571 | /* Branch on Floating-Point Condition Codes (FBfcc). */ |
1572 | branch_p = 1; | |
1573 | offset = 4 * X_DISP22 (insn); | |
c906108c | 1574 | } |
386c036b MK |
1575 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) |
1576 | { | |
1577 | /* Branch on Floating-Point Condition Codes with Prediction | |
1578 | (FBPfcc). */ | |
1579 | branch_p = 1; | |
1580 | offset = 4 * X_DISP19 (insn); | |
1581 | } | |
1582 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) | |
1583 | { | |
1584 | /* Branch on Integer Condition Codes (Bicc). */ | |
1585 | branch_p = 1; | |
1586 | offset = 4 * X_DISP22 (insn); | |
1587 | } | |
1588 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) | |
c906108c | 1589 | { |
386c036b MK |
1590 | /* Branch on Integer Condition Codes with Prediction (BPcc). */ |
1591 | branch_p = 1; | |
1592 | offset = 4 * X_DISP19 (insn); | |
c906108c | 1593 | } |
c893be75 MK |
1594 | else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a) |
1595 | { | |
cd76b525 YQ |
1596 | struct frame_info *frame = get_current_frame (); |
1597 | ||
c893be75 | 1598 | /* Trap instruction (TRAP). */ |
cd76b525 YQ |
1599 | return gdbarch_tdep (get_regcache_arch (regcache))->step_trap (frame, |
1600 | insn); | |
c893be75 | 1601 | } |
386c036b MK |
1602 | |
1603 | /* FIXME: Handle DONE and RETRY instructions. */ | |
1604 | ||
386c036b | 1605 | if (branch_p) |
c906108c | 1606 | { |
8d1b3521 DM |
1607 | if (fused_p) |
1608 | { | |
1609 | /* Fused compare-and-branch instructions are non-delayed, | |
1610 | and do not have an annuling capability. So we need to | |
1611 | always set a breakpoint on both the NPC and the branch | |
1612 | target address. */ | |
1613 | gdb_assert (offset != 0); | |
1614 | return pc + offset; | |
1615 | } | |
1616 | else if (conditional_p) | |
c906108c | 1617 | { |
386c036b MK |
1618 | /* For conditional branches, return nPC + 4 iff the annul |
1619 | bit is 1. */ | |
1620 | return (X_A (insn) ? *npc + 4 : 0); | |
c906108c SS |
1621 | } |
1622 | else | |
1623 | { | |
386c036b MK |
1624 | /* For unconditional branches, return the target if its |
1625 | specified condition is "always" and return nPC + 4 if the | |
1626 | condition is "never". If the annul bit is 1, set *NPC to | |
1627 | zero. */ | |
1628 | if (X_COND (insn) == 0x0) | |
1629 | pc = *npc, offset = 4; | |
1630 | if (X_A (insn)) | |
1631 | *npc = 0; | |
1632 | ||
386c036b | 1633 | return pc + offset; |
c906108c SS |
1634 | } |
1635 | } | |
386c036b MK |
1636 | |
1637 | return 0; | |
c906108c SS |
1638 | } |
1639 | ||
c893be75 | 1640 | static CORE_ADDR |
0b1b3e42 | 1641 | sparc_step_trap (struct frame_info *frame, unsigned long insn) |
c893be75 MK |
1642 | { |
1643 | return 0; | |
1644 | } | |
1645 | ||
93f9a11f | 1646 | static VEC (CORE_ADDR) * |
f5ea389a | 1647 | sparc_software_single_step (struct regcache *regcache) |
386c036b | 1648 | { |
cd76b525 | 1649 | struct gdbarch *arch = get_regcache_arch (regcache); |
c893be75 | 1650 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
8181d85f | 1651 | CORE_ADDR npc, nnpc; |
c906108c | 1652 | |
e0cd558a | 1653 | CORE_ADDR pc, orig_npc; |
93f9a11f | 1654 | VEC (CORE_ADDR) *next_pcs = NULL; |
c906108c | 1655 | |
cd76b525 YQ |
1656 | pc = regcache_raw_get_unsigned (regcache, tdep->pc_regnum); |
1657 | orig_npc = npc = regcache_raw_get_unsigned (regcache, tdep->npc_regnum); | |
c906108c | 1658 | |
e0cd558a | 1659 | /* Analyze the instruction at PC. */ |
cd76b525 | 1660 | nnpc = sparc_analyze_control_transfer (regcache, pc, &npc); |
e0cd558a | 1661 | if (npc != 0) |
93f9a11f | 1662 | VEC_safe_push (CORE_ADDR, next_pcs, npc); |
8181d85f | 1663 | |
e0cd558a | 1664 | if (nnpc != 0) |
93f9a11f | 1665 | VEC_safe_push (CORE_ADDR, next_pcs, nnpc); |
c906108c | 1666 | |
e0cd558a UW |
1667 | /* Assert that we have set at least one breakpoint, and that |
1668 | they're not set at the same spot - unless we're going | |
1669 | from here straight to NULL, i.e. a call or jump to 0. */ | |
1670 | gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0); | |
1671 | gdb_assert (nnpc != npc || orig_npc == 0); | |
e6590a1b | 1672 | |
93f9a11f | 1673 | return next_pcs; |
386c036b MK |
1674 | } |
1675 | ||
1676 | static void | |
61a1198a | 1677 | sparc_write_pc (struct regcache *regcache, CORE_ADDR pc) |
386c036b | 1678 | { |
61a1198a | 1679 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
386c036b | 1680 | |
61a1198a UW |
1681 | regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc); |
1682 | regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4); | |
386c036b MK |
1683 | } |
1684 | \f | |
5af923b0 | 1685 | |
e5139de8 | 1686 | /* Iterate over core file register note sections. */ |
a54124c5 | 1687 | |
e5139de8 AA |
1688 | static void |
1689 | sparc_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
1690 | iterate_over_regset_sections_cb *cb, | |
1691 | void *cb_data, | |
1692 | const struct regcache *regcache) | |
a54124c5 MK |
1693 | { |
1694 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1695 | ||
e5139de8 AA |
1696 | cb (".reg", tdep->sizeof_gregset, tdep->gregset, NULL, cb_data); |
1697 | cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data); | |
a54124c5 MK |
1698 | } |
1699 | \f | |
1700 | ||
3f7b46f2 IR |
1701 | static int |
1702 | validate_tdesc_registers (const struct target_desc *tdesc, | |
1703 | struct tdesc_arch_data *tdesc_data, | |
1704 | const char *feature_name, | |
1705 | const char *register_names[], | |
1706 | unsigned int registers_num, | |
1707 | unsigned int reg_start) | |
1708 | { | |
1709 | int valid_p = 1; | |
1710 | const struct tdesc_feature *feature; | |
1711 | ||
1712 | feature = tdesc_find_feature (tdesc, feature_name); | |
1713 | if (feature == NULL) | |
1714 | return 0; | |
1715 | ||
1716 | for (unsigned int i = 0; i < registers_num; i++) | |
1717 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1718 | reg_start + i, | |
1719 | register_names[i]); | |
1720 | ||
1721 | return valid_p; | |
1722 | } | |
1723 | ||
386c036b MK |
1724 | static struct gdbarch * |
1725 | sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1726 | { | |
1727 | struct gdbarch_tdep *tdep; | |
3f7b46f2 | 1728 | const struct target_desc *tdesc = info.target_desc; |
386c036b | 1729 | struct gdbarch *gdbarch; |
3f7b46f2 | 1730 | int valid_p = 1; |
c906108c | 1731 | |
386c036b MK |
1732 | /* If there is already a candidate, use it. */ |
1733 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1734 | if (arches != NULL) | |
1735 | return arches->gdbarch; | |
c906108c | 1736 | |
386c036b | 1737 | /* Allocate space for the new architecture. */ |
41bf6aca | 1738 | tdep = XCNEW (struct gdbarch_tdep); |
386c036b | 1739 | gdbarch = gdbarch_alloc (&info, tdep); |
5af923b0 | 1740 | |
386c036b MK |
1741 | tdep->pc_regnum = SPARC32_PC_REGNUM; |
1742 | tdep->npc_regnum = SPARC32_NPC_REGNUM; | |
c893be75 | 1743 | tdep->step_trap = sparc_step_trap; |
3f7b46f2 IR |
1744 | tdep->fpu_register_names = sparc32_fpu_register_names; |
1745 | tdep->fpu_registers_num = ARRAY_SIZE (sparc32_fpu_register_names); | |
1746 | tdep->cp0_register_names = sparc32_cp0_register_names; | |
1747 | tdep->cp0_registers_num = ARRAY_SIZE (sparc32_cp0_register_names); | |
386c036b MK |
1748 | |
1749 | set_gdbarch_long_double_bit (gdbarch, 128); | |
8da61cc4 | 1750 | set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad); |
386c036b MK |
1751 | |
1752 | set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); | |
1753 | set_gdbarch_register_name (gdbarch, sparc32_register_name); | |
1754 | set_gdbarch_register_type (gdbarch, sparc32_register_type); | |
1755 | set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); | |
3f7b46f2 IR |
1756 | set_tdesc_pseudo_register_name (gdbarch, sparc32_pseudo_register_name); |
1757 | set_tdesc_pseudo_register_type (gdbarch, sparc32_pseudo_register_type); | |
386c036b MK |
1758 | set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); |
1759 | set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); | |
1760 | ||
1761 | /* Register numbers of various important registers. */ | |
1762 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ | |
1763 | set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ | |
1764 | set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ | |
1765 | ||
1766 | /* Call dummy code. */ | |
49a45ecf | 1767 | set_gdbarch_frame_align (gdbarch, sparc32_frame_align); |
386c036b MK |
1768 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
1769 | set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); | |
1770 | set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); | |
1771 | ||
b9d4c5ed | 1772 | set_gdbarch_return_value (gdbarch, sparc32_return_value); |
386c036b MK |
1773 | set_gdbarch_stabs_argument_has_addr |
1774 | (gdbarch, sparc32_stabs_argument_has_addr); | |
1775 | ||
1776 | set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); | |
1777 | ||
1778 | /* Stack grows downward. */ | |
1779 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
c906108c | 1780 | |
04180708 YQ |
1781 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
1782 | sparc_breakpoint::kind_from_pc); | |
1783 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
1784 | sparc_breakpoint::bp_from_kind); | |
c906108c | 1785 | |
386c036b | 1786 | set_gdbarch_frame_args_skip (gdbarch, 8); |
5af923b0 | 1787 | |
386c036b | 1788 | set_gdbarch_print_insn (gdbarch, print_insn_sparc); |
c906108c | 1789 | |
386c036b MK |
1790 | set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); |
1791 | set_gdbarch_write_pc (gdbarch, sparc_write_pc); | |
c906108c | 1792 | |
236369e7 | 1793 | set_gdbarch_dummy_id (gdbarch, sparc_dummy_id); |
c906108c | 1794 | |
386c036b | 1795 | set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc); |
c906108c | 1796 | |
386c036b MK |
1797 | frame_base_set_default (gdbarch, &sparc32_frame_base); |
1798 | ||
f5a9b87d DM |
1799 | /* Hook in the DWARF CFI frame unwinder. */ |
1800 | dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg); | |
1801 | /* FIXME: kettenis/20050423: Don't enable the unwinder until the | |
1802 | StackGhost issues have been resolved. */ | |
1803 | ||
b2a0b9b2 DM |
1804 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1805 | gdbarch_init_osabi (info, gdbarch); | |
1806 | ||
236369e7 | 1807 | frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind); |
c906108c | 1808 | |
3f7b46f2 IR |
1809 | if (tdesc_has_registers (tdesc)) |
1810 | { | |
1811 | struct tdesc_arch_data *tdesc_data = tdesc_data_alloc (); | |
1812 | ||
1813 | /* Validate that the descriptor provides the mandatory registers | |
1814 | and allocate their numbers. */ | |
1815 | valid_p &= validate_tdesc_registers (tdesc, tdesc_data, | |
1816 | "org.gnu.gdb.sparc.cpu", | |
1817 | sparc_core_register_names, | |
1818 | ARRAY_SIZE (sparc_core_register_names), | |
1819 | SPARC_G0_REGNUM); | |
1820 | valid_p &= validate_tdesc_registers (tdesc, tdesc_data, | |
1821 | "org.gnu.gdb.sparc.fpu", | |
1822 | tdep->fpu_register_names, | |
1823 | tdep->fpu_registers_num, | |
1824 | SPARC_F0_REGNUM); | |
1825 | valid_p &= validate_tdesc_registers (tdesc, tdesc_data, | |
1826 | "org.gnu.gdb.sparc.cp0", | |
1827 | tdep->cp0_register_names, | |
1828 | tdep->cp0_registers_num, | |
1291063d JM |
1829 | SPARC_F0_REGNUM |
1830 | + tdep->fpu_registers_num); | |
3f7b46f2 IR |
1831 | if (!valid_p) |
1832 | { | |
1833 | tdesc_data_cleanup (tdesc_data); | |
1834 | return NULL; | |
1835 | } | |
1836 | ||
1837 | /* Target description may have changed. */ | |
1838 | info.tdep_info = tdesc_data; | |
1839 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); | |
1840 | } | |
1841 | ||
a54124c5 | 1842 | /* If we have register sets, enable the generic core file support. */ |
4c72d57a | 1843 | if (tdep->gregset) |
e5139de8 AA |
1844 | set_gdbarch_iterate_over_regset_sections |
1845 | (gdbarch, sparc_iterate_over_regset_sections); | |
a54124c5 | 1846 | |
7e35103a JB |
1847 | register_sparc_ravenscar_ops (gdbarch); |
1848 | ||
386c036b MK |
1849 | return gdbarch; |
1850 | } | |
1851 | \f | |
1852 | /* Helper functions for dealing with register windows. */ | |
1853 | ||
1854 | void | |
1855 | sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) | |
c906108c | 1856 | { |
e17a4113 UW |
1857 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1858 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
386c036b | 1859 | int offset = 0; |
e1613aba | 1860 | gdb_byte buf[8]; |
386c036b MK |
1861 | int i; |
1862 | ||
1863 | if (sp & 1) | |
1864 | { | |
1865 | /* Registers are 64-bit. */ | |
1866 | sp += BIAS; | |
c906108c | 1867 | |
386c036b MK |
1868 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1869 | { | |
1870 | if (regnum == i || regnum == -1) | |
1871 | { | |
1872 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); | |
f700a364 MK |
1873 | |
1874 | /* Handle StackGhost. */ | |
1875 | if (i == SPARC_I7_REGNUM) | |
1876 | { | |
e17a4113 UW |
1877 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1878 | ULONGEST i7; | |
f700a364 | 1879 | |
e17a4113 UW |
1880 | i7 = extract_unsigned_integer (buf + offset, 8, byte_order); |
1881 | store_unsigned_integer (buf + offset, 8, byte_order, | |
1882 | i7 ^ wcookie); | |
f700a364 MK |
1883 | } |
1884 | ||
386c036b MK |
1885 | regcache_raw_supply (regcache, i, buf); |
1886 | } | |
1887 | } | |
1888 | } | |
1889 | else | |
c906108c | 1890 | { |
386c036b MK |
1891 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1892 | pointer. */ | |
1893 | sp &= 0xffffffffUL; | |
c906108c | 1894 | |
386c036b MK |
1895 | /* Clear out the top half of the temporary buffer, and put the |
1896 | register value in the bottom half if we're in 64-bit mode. */ | |
e6d4f032 | 1897 | if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) |
c906108c | 1898 | { |
386c036b MK |
1899 | memset (buf, 0, 4); |
1900 | offset = 4; | |
1901 | } | |
c906108c | 1902 | |
386c036b MK |
1903 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1904 | { | |
1905 | if (regnum == i || regnum == -1) | |
1906 | { | |
1907 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), | |
1908 | buf + offset, 4); | |
42cdca6c MK |
1909 | |
1910 | /* Handle StackGhost. */ | |
1911 | if (i == SPARC_I7_REGNUM) | |
1912 | { | |
e17a4113 UW |
1913 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1914 | ULONGEST i7; | |
42cdca6c | 1915 | |
e17a4113 UW |
1916 | i7 = extract_unsigned_integer (buf + offset, 4, byte_order); |
1917 | store_unsigned_integer (buf + offset, 4, byte_order, | |
1918 | i7 ^ wcookie); | |
42cdca6c MK |
1919 | } |
1920 | ||
386c036b MK |
1921 | regcache_raw_supply (regcache, i, buf); |
1922 | } | |
c906108c SS |
1923 | } |
1924 | } | |
c906108c | 1925 | } |
c906108c SS |
1926 | |
1927 | void | |
386c036b MK |
1928 | sparc_collect_rwindow (const struct regcache *regcache, |
1929 | CORE_ADDR sp, int regnum) | |
c906108c | 1930 | { |
e17a4113 UW |
1931 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1932 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
386c036b | 1933 | int offset = 0; |
e1613aba | 1934 | gdb_byte buf[8]; |
386c036b | 1935 | int i; |
5af923b0 | 1936 | |
386c036b | 1937 | if (sp & 1) |
5af923b0 | 1938 | { |
386c036b MK |
1939 | /* Registers are 64-bit. */ |
1940 | sp += BIAS; | |
c906108c | 1941 | |
386c036b MK |
1942 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1943 | { | |
1944 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1945 | { | |
1946 | regcache_raw_collect (regcache, i, buf); | |
f700a364 MK |
1947 | |
1948 | /* Handle StackGhost. */ | |
1949 | if (i == SPARC_I7_REGNUM) | |
1950 | { | |
e17a4113 UW |
1951 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1952 | ULONGEST i7; | |
f700a364 | 1953 | |
e17a4113 UW |
1954 | i7 = extract_unsigned_integer (buf + offset, 8, byte_order); |
1955 | store_unsigned_integer (buf, 8, byte_order, i7 ^ wcookie); | |
f700a364 MK |
1956 | } |
1957 | ||
386c036b MK |
1958 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); |
1959 | } | |
1960 | } | |
5af923b0 MS |
1961 | } |
1962 | else | |
1963 | { | |
386c036b MK |
1964 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1965 | pointer. */ | |
1966 | sp &= 0xffffffffUL; | |
1967 | ||
1968 | /* Only use the bottom half if we're in 64-bit mode. */ | |
e6d4f032 | 1969 | if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) |
386c036b MK |
1970 | offset = 4; |
1971 | ||
1972 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1973 | { | |
1974 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1975 | { | |
1976 | regcache_raw_collect (regcache, i, buf); | |
42cdca6c MK |
1977 | |
1978 | /* Handle StackGhost. */ | |
1979 | if (i == SPARC_I7_REGNUM) | |
1980 | { | |
e17a4113 UW |
1981 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1982 | ULONGEST i7; | |
42cdca6c | 1983 | |
e17a4113 UW |
1984 | i7 = extract_unsigned_integer (buf + offset, 4, byte_order); |
1985 | store_unsigned_integer (buf + offset, 4, byte_order, | |
1986 | i7 ^ wcookie); | |
42cdca6c MK |
1987 | } |
1988 | ||
386c036b MK |
1989 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), |
1990 | buf + offset, 4); | |
1991 | } | |
1992 | } | |
5af923b0 | 1993 | } |
c906108c SS |
1994 | } |
1995 | ||
386c036b MK |
1996 | /* Helper functions for dealing with register sets. */ |
1997 | ||
c906108c | 1998 | void |
b4fd25c9 | 1999 | sparc32_supply_gregset (const struct sparc_gregmap *gregmap, |
386c036b MK |
2000 | struct regcache *regcache, |
2001 | int regnum, const void *gregs) | |
c906108c | 2002 | { |
19ba03f4 | 2003 | const gdb_byte *regs = (const gdb_byte *) gregs; |
22e74ef9 | 2004 | gdb_byte zero[4] = { 0 }; |
386c036b | 2005 | int i; |
5af923b0 | 2006 | |
386c036b MK |
2007 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
2008 | regcache_raw_supply (regcache, SPARC32_PSR_REGNUM, | |
b4fd25c9 | 2009 | regs + gregmap->r_psr_offset); |
c906108c | 2010 | |
386c036b MK |
2011 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
2012 | regcache_raw_supply (regcache, SPARC32_PC_REGNUM, | |
b4fd25c9 | 2013 | regs + gregmap->r_pc_offset); |
5af923b0 | 2014 | |
386c036b MK |
2015 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) |
2016 | regcache_raw_supply (regcache, SPARC32_NPC_REGNUM, | |
b4fd25c9 | 2017 | regs + gregmap->r_npc_offset); |
5af923b0 | 2018 | |
386c036b MK |
2019 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
2020 | regcache_raw_supply (regcache, SPARC32_Y_REGNUM, | |
b4fd25c9 | 2021 | regs + gregmap->r_y_offset); |
5af923b0 | 2022 | |
386c036b | 2023 | if (regnum == SPARC_G0_REGNUM || regnum == -1) |
22e74ef9 | 2024 | regcache_raw_supply (regcache, SPARC_G0_REGNUM, &zero); |
5af923b0 | 2025 | |
386c036b | 2026 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) |
c906108c | 2027 | { |
b4fd25c9 | 2028 | int offset = gregmap->r_g1_offset; |
386c036b MK |
2029 | |
2030 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
2031 | { | |
2032 | if (regnum == i || regnum == -1) | |
2033 | regcache_raw_supply (regcache, i, regs + offset); | |
2034 | offset += 4; | |
2035 | } | |
c906108c | 2036 | } |
386c036b MK |
2037 | |
2038 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
c906108c | 2039 | { |
386c036b MK |
2040 | /* Not all of the register set variants include Locals and |
2041 | Inputs. For those that don't, we read them off the stack. */ | |
b4fd25c9 | 2042 | if (gregmap->r_l0_offset == -1) |
386c036b MK |
2043 | { |
2044 | ULONGEST sp; | |
2045 | ||
2046 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
2047 | sparc_supply_rwindow (regcache, sp, regnum); | |
2048 | } | |
2049 | else | |
2050 | { | |
b4fd25c9 | 2051 | int offset = gregmap->r_l0_offset; |
386c036b MK |
2052 | |
2053 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
2054 | { | |
2055 | if (regnum == i || regnum == -1) | |
2056 | regcache_raw_supply (regcache, i, regs + offset); | |
2057 | offset += 4; | |
2058 | } | |
2059 | } | |
c906108c SS |
2060 | } |
2061 | } | |
2062 | ||
c5aa993b | 2063 | void |
b4fd25c9 | 2064 | sparc32_collect_gregset (const struct sparc_gregmap *gregmap, |
386c036b MK |
2065 | const struct regcache *regcache, |
2066 | int regnum, void *gregs) | |
c906108c | 2067 | { |
19ba03f4 | 2068 | gdb_byte *regs = (gdb_byte *) gregs; |
386c036b | 2069 | int i; |
c5aa993b | 2070 | |
386c036b MK |
2071 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
2072 | regcache_raw_collect (regcache, SPARC32_PSR_REGNUM, | |
b4fd25c9 | 2073 | regs + gregmap->r_psr_offset); |
60054393 | 2074 | |
386c036b MK |
2075 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
2076 | regcache_raw_collect (regcache, SPARC32_PC_REGNUM, | |
b4fd25c9 | 2077 | regs + gregmap->r_pc_offset); |
386c036b MK |
2078 | |
2079 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) | |
2080 | regcache_raw_collect (regcache, SPARC32_NPC_REGNUM, | |
b4fd25c9 | 2081 | regs + gregmap->r_npc_offset); |
5af923b0 | 2082 | |
386c036b MK |
2083 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
2084 | regcache_raw_collect (regcache, SPARC32_Y_REGNUM, | |
b4fd25c9 | 2085 | regs + gregmap->r_y_offset); |
386c036b MK |
2086 | |
2087 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) | |
5af923b0 | 2088 | { |
b4fd25c9 | 2089 | int offset = gregmap->r_g1_offset; |
386c036b MK |
2090 | |
2091 | /* %g0 is always zero. */ | |
2092 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
2093 | { | |
2094 | if (regnum == i || regnum == -1) | |
2095 | regcache_raw_collect (regcache, i, regs + offset); | |
2096 | offset += 4; | |
2097 | } | |
5af923b0 | 2098 | } |
386c036b MK |
2099 | |
2100 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
5af923b0 | 2101 | { |
386c036b MK |
2102 | /* Not all of the register set variants include Locals and |
2103 | Inputs. For those that don't, we read them off the stack. */ | |
b4fd25c9 | 2104 | if (gregmap->r_l0_offset != -1) |
386c036b | 2105 | { |
b4fd25c9 | 2106 | int offset = gregmap->r_l0_offset; |
386c036b MK |
2107 | |
2108 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
2109 | { | |
2110 | if (regnum == i || regnum == -1) | |
2111 | regcache_raw_collect (regcache, i, regs + offset); | |
2112 | offset += 4; | |
2113 | } | |
2114 | } | |
5af923b0 | 2115 | } |
c906108c SS |
2116 | } |
2117 | ||
c906108c | 2118 | void |
b4fd25c9 | 2119 | sparc32_supply_fpregset (const struct sparc_fpregmap *fpregmap, |
db75c717 | 2120 | struct regcache *regcache, |
386c036b | 2121 | int regnum, const void *fpregs) |
c906108c | 2122 | { |
19ba03f4 | 2123 | const gdb_byte *regs = (const gdb_byte *) fpregs; |
386c036b | 2124 | int i; |
60054393 | 2125 | |
386c036b | 2126 | for (i = 0; i < 32; i++) |
c906108c | 2127 | { |
386c036b | 2128 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) |
db75c717 | 2129 | regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, |
b4fd25c9 | 2130 | regs + fpregmap->r_f0_offset + (i * 4)); |
c906108c | 2131 | } |
5af923b0 | 2132 | |
386c036b | 2133 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
db75c717 | 2134 | regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, |
b4fd25c9 | 2135 | regs + fpregmap->r_fsr_offset); |
c906108c SS |
2136 | } |
2137 | ||
386c036b | 2138 | void |
b4fd25c9 | 2139 | sparc32_collect_fpregset (const struct sparc_fpregmap *fpregmap, |
db75c717 | 2140 | const struct regcache *regcache, |
386c036b | 2141 | int regnum, void *fpregs) |
c906108c | 2142 | { |
19ba03f4 | 2143 | gdb_byte *regs = (gdb_byte *) fpregs; |
386c036b | 2144 | int i; |
c906108c | 2145 | |
386c036b MK |
2146 | for (i = 0; i < 32; i++) |
2147 | { | |
2148 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) | |
db75c717 | 2149 | regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, |
b4fd25c9 | 2150 | regs + fpregmap->r_f0_offset + (i * 4)); |
386c036b | 2151 | } |
c906108c | 2152 | |
386c036b | 2153 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
db75c717 | 2154 | regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, |
b4fd25c9 | 2155 | regs + fpregmap->r_fsr_offset); |
c906108c | 2156 | } |
c906108c | 2157 | \f |
c906108c | 2158 | |
386c036b | 2159 | /* SunOS 4. */ |
c906108c | 2160 | |
386c036b | 2161 | /* From <machine/reg.h>. */ |
b4fd25c9 | 2162 | const struct sparc_gregmap sparc32_sunos4_gregmap = |
c906108c | 2163 | { |
386c036b MK |
2164 | 0 * 4, /* %psr */ |
2165 | 1 * 4, /* %pc */ | |
2166 | 2 * 4, /* %npc */ | |
2167 | 3 * 4, /* %y */ | |
2168 | -1, /* %wim */ | |
2169 | -1, /* %tbr */ | |
2170 | 4 * 4, /* %g1 */ | |
2171 | -1 /* %l0 */ | |
2172 | }; | |
db75c717 | 2173 | |
b4fd25c9 | 2174 | const struct sparc_fpregmap sparc32_sunos4_fpregmap = |
db75c717 DM |
2175 | { |
2176 | 0 * 4, /* %f0 */ | |
2177 | 33 * 4, /* %fsr */ | |
2178 | }; | |
2179 | ||
b4fd25c9 | 2180 | const struct sparc_fpregmap sparc32_bsd_fpregmap = |
db75c717 DM |
2181 | { |
2182 | 0 * 4, /* %f0 */ | |
2183 | 32 * 4, /* %fsr */ | |
2184 | }; | |
386c036b | 2185 | \f |
c906108c | 2186 | |
386c036b MK |
2187 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
2188 | void _initialize_sparc_tdep (void); | |
c906108c SS |
2189 | |
2190 | void | |
386c036b | 2191 | _initialize_sparc_tdep (void) |
c906108c | 2192 | { |
386c036b | 2193 | register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init); |
ef3cf062 | 2194 | } |