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c906108c SS |
1 | /* Target-dependent code for the SPARC for GDB, the GNU debugger. |
2 | Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997 | |
3 | Free Software Foundation, Inc. | |
4 | ||
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
21 | |
22 | /* ??? Support for calling functions from gdb in sparc64 is unfinished. */ | |
23 | ||
24 | #include "defs.h" | |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "obstack.h" | |
28 | #include "target.h" | |
29 | #include "value.h" | |
30 | #include "bfd.h" | |
31 | #include "gdb_string.h" | |
32 | ||
33 | #ifdef USE_PROC_FS | |
34 | #include <sys/procfs.h> | |
35 | #endif | |
36 | ||
37 | #include "gdbcore.h" | |
38 | ||
39 | #if defined(TARGET_SPARCLET) || defined(TARGET_SPARCLITE) | |
40 | #define SPARC_HAS_FPU 0 | |
41 | #else | |
42 | #define SPARC_HAS_FPU 1 | |
43 | #endif | |
44 | ||
45 | #ifdef GDB_TARGET_IS_SPARC64 | |
46 | #define FP_REGISTER_BYTES (64 * 4) | |
47 | #else | |
48 | #define FP_REGISTER_BYTES (32 * 4) | |
49 | #endif | |
50 | ||
51 | /* If not defined, assume 32 bit sparc. */ | |
52 | #ifndef FP_MAX_REGNUM | |
53 | #define FP_MAX_REGNUM (FP0_REGNUM + 32) | |
54 | #endif | |
55 | ||
56 | #define SPARC_INTREG_SIZE (REGISTER_RAW_SIZE (G0_REGNUM)) | |
57 | ||
58 | /* From infrun.c */ | |
59 | extern int stop_after_trap; | |
60 | ||
61 | /* We don't store all registers immediately when requested, since they | |
62 | get sent over in large chunks anyway. Instead, we accumulate most | |
63 | of the changes and send them over once. "deferred_stores" keeps | |
64 | track of which sets of registers we have locally-changed copies of, | |
65 | so we only need send the groups that have changed. */ | |
66 | ||
67 | int deferred_stores = 0; /* Cumulates stores we want to do eventually. */ | |
68 | ||
69 | ||
70 | /* Some machines, such as Fujitsu SPARClite 86x, have a bi-endian mode | |
71 | where instructions are big-endian and data are little-endian. | |
72 | This flag is set when we detect that the target is of this type. */ | |
73 | ||
74 | int bi_endian = 0; | |
75 | ||
76 | ||
77 | /* Fetch a single instruction. Even on bi-endian machines | |
78 | such as sparc86x, instructions are always big-endian. */ | |
79 | ||
80 | static unsigned long | |
81 | fetch_instruction (pc) | |
82 | CORE_ADDR pc; | |
83 | { | |
84 | unsigned long retval; | |
85 | int i; | |
86 | unsigned char buf[4]; | |
87 | ||
88 | read_memory (pc, buf, sizeof (buf)); | |
89 | ||
90 | /* Start at the most significant end of the integer, and work towards | |
91 | the least significant. */ | |
92 | retval = 0; | |
93 | for (i = 0; i < sizeof (buf); ++i) | |
94 | retval = (retval << 8) | buf[i]; | |
95 | return retval; | |
96 | } | |
97 | ||
98 | ||
99 | /* Branches with prediction are treated like their non-predicting cousins. */ | |
100 | /* FIXME: What about floating point branches? */ | |
101 | ||
102 | /* Macros to extract fields from sparc instructions. */ | |
103 | #define X_OP(i) (((i) >> 30) & 0x3) | |
104 | #define X_RD(i) (((i) >> 25) & 0x1f) | |
105 | #define X_A(i) (((i) >> 29) & 1) | |
106 | #define X_COND(i) (((i) >> 25) & 0xf) | |
107 | #define X_OP2(i) (((i) >> 22) & 0x7) | |
108 | #define X_IMM22(i) ((i) & 0x3fffff) | |
109 | #define X_OP3(i) (((i) >> 19) & 0x3f) | |
110 | #define X_RS1(i) (((i) >> 14) & 0x1f) | |
111 | #define X_I(i) (((i) >> 13) & 1) | |
112 | #define X_IMM13(i) ((i) & 0x1fff) | |
113 | /* Sign extension macros. */ | |
114 | #define X_SIMM13(i) ((X_IMM13 (i) ^ 0x1000) - 0x1000) | |
115 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) | |
116 | #define X_CC(i) (((i) >> 20) & 3) | |
117 | #define X_P(i) (((i) >> 19) & 1) | |
118 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) | |
119 | #define X_RCOND(i) (((i) >> 25) & 7) | |
120 | #define X_DISP16(i) ((((((i) >> 6) && 0xc000) | ((i) & 0x3fff)) ^ 0x8000) - 0x8000) | |
121 | #define X_FCN(i) (((i) >> 25) & 31) | |
122 | ||
123 | typedef enum | |
124 | { | |
125 | Error, not_branch, bicc, bicca, ba, baa, ticc, ta, | |
126 | #ifdef GDB_TARGET_IS_SPARC64 | |
127 | done_retry | |
128 | #endif | |
c5aa993b JM |
129 | } |
130 | branch_type; | |
c906108c SS |
131 | |
132 | /* Simulate single-step ptrace call for sun4. Code written by Gary | |
133 | Beihl (beihl@mcc.com). */ | |
134 | ||
135 | /* npc4 and next_pc describe the situation at the time that the | |
136 | step-breakpoint was set, not necessary the current value of NPC_REGNUM. */ | |
137 | static CORE_ADDR next_pc, npc4, target; | |
138 | static int brknpc4, brktrg; | |
139 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
140 | static binsn_quantum break_mem[3]; | |
141 | ||
142 | static branch_type isbranch PARAMS ((long, CORE_ADDR, CORE_ADDR *)); | |
143 | ||
144 | /* single_step() is called just before we want to resume the inferior, | |
145 | if we want to single-step it but there is no hardware or kernel single-step | |
146 | support (as on all SPARCs). We find all the possible targets of the | |
147 | coming instruction and breakpoint them. | |
148 | ||
149 | single_step is also called just after the inferior stops. If we had | |
150 | set up a simulated single-step, we undo our damage. */ | |
151 | ||
152 | void | |
153 | sparc_software_single_step (ignore, insert_breakpoints_p) | |
c5aa993b | 154 | enum target_signal ignore; /* pid, but we don't need it */ |
c906108c SS |
155 | int insert_breakpoints_p; |
156 | { | |
157 | branch_type br; | |
158 | CORE_ADDR pc; | |
159 | long pc_instruction; | |
160 | ||
161 | if (insert_breakpoints_p) | |
162 | { | |
163 | /* Always set breakpoint for NPC. */ | |
164 | next_pc = read_register (NPC_REGNUM); | |
c5aa993b | 165 | npc4 = next_pc + 4; /* branch not taken */ |
c906108c SS |
166 | |
167 | target_insert_breakpoint (next_pc, break_mem[0]); | |
168 | /* printf_unfiltered ("set break at %x\n",next_pc); */ | |
169 | ||
170 | pc = read_register (PC_REGNUM); | |
171 | pc_instruction = fetch_instruction (pc); | |
172 | br = isbranch (pc_instruction, pc, &target); | |
173 | brknpc4 = brktrg = 0; | |
174 | ||
175 | if (br == bicca) | |
176 | { | |
177 | /* Conditional annulled branch will either end up at | |
178 | npc (if taken) or at npc+4 (if not taken). | |
179 | Trap npc+4. */ | |
180 | brknpc4 = 1; | |
181 | target_insert_breakpoint (npc4, break_mem[1]); | |
182 | } | |
183 | else if (br == baa && target != next_pc) | |
184 | { | |
185 | /* Unconditional annulled branch will always end up at | |
186 | the target. */ | |
187 | brktrg = 1; | |
188 | target_insert_breakpoint (target, break_mem[2]); | |
189 | } | |
190 | #ifdef GDB_TARGET_IS_SPARC64 | |
191 | else if (br == done_retry) | |
192 | { | |
193 | brktrg = 1; | |
194 | target_insert_breakpoint (target, break_mem[2]); | |
195 | } | |
196 | #endif | |
197 | } | |
198 | else | |
199 | { | |
200 | /* Remove breakpoints */ | |
201 | target_remove_breakpoint (next_pc, break_mem[0]); | |
202 | ||
203 | if (brknpc4) | |
204 | target_remove_breakpoint (npc4, break_mem[1]); | |
205 | ||
206 | if (brktrg) | |
207 | target_remove_breakpoint (target, break_mem[2]); | |
208 | } | |
209 | } | |
210 | \f | |
211 | /* Call this for each newly created frame. For SPARC, we need to calculate | |
212 | the bottom of the frame, and do some extra work if the prologue | |
213 | has been generated via the -mflat option to GCC. In particular, | |
214 | we need to know where the previous fp and the pc have been stashed, | |
215 | since their exact position within the frame may vary. */ | |
216 | ||
217 | void | |
218 | sparc_init_extra_frame_info (fromleaf, fi) | |
219 | int fromleaf; | |
220 | struct frame_info *fi; | |
221 | { | |
222 | char *name; | |
223 | CORE_ADDR prologue_start, prologue_end; | |
224 | int insn; | |
225 | ||
226 | fi->bottom = | |
227 | (fi->next ? | |
228 | (fi->frame == fi->next->frame ? fi->next->bottom : fi->next->frame) : | |
229 | read_sp ()); | |
230 | ||
231 | /* If fi->next is NULL, then we already set ->frame by passing read_fp() | |
232 | to create_new_frame. */ | |
233 | if (fi->next) | |
234 | { | |
235 | char buf[MAX_REGISTER_RAW_SIZE]; | |
236 | ||
237 | /* Compute ->frame as if not flat. If it is flat, we'll change | |
c5aa993b | 238 | it later. */ |
c906108c SS |
239 | if (fi->next->next != NULL |
240 | && (fi->next->next->signal_handler_caller | |
241 | || frame_in_dummy (fi->next->next)) | |
242 | && frameless_look_for_prologue (fi->next)) | |
243 | { | |
244 | /* A frameless function interrupted by a signal did not change | |
245 | the frame pointer, fix up frame pointer accordingly. */ | |
246 | fi->frame = FRAME_FP (fi->next); | |
247 | fi->bottom = fi->next->bottom; | |
248 | } | |
249 | else | |
250 | { | |
251 | /* Should we adjust for stack bias here? */ | |
252 | get_saved_register (buf, 0, 0, fi, FP_REGNUM, 0); | |
253 | fi->frame = extract_address (buf, REGISTER_RAW_SIZE (FP_REGNUM)); | |
254 | #ifdef GDB_TARGET_IS_SPARC64 | |
255 | if (fi->frame & 1) | |
256 | fi->frame += 2047; | |
257 | #endif | |
c5aa993b | 258 | |
c906108c SS |
259 | } |
260 | } | |
261 | ||
262 | /* Decide whether this is a function with a ``flat register window'' | |
263 | frame. For such functions, the frame pointer is actually in %i7. */ | |
264 | fi->flat = 0; | |
265 | fi->in_prologue = 0; | |
266 | if (find_pc_partial_function (fi->pc, &name, &prologue_start, &prologue_end)) | |
267 | { | |
268 | /* See if the function starts with an add (which will be of a | |
c5aa993b JM |
269 | negative number if a flat frame) to the sp. FIXME: Does not |
270 | handle large frames which will need more than one instruction | |
271 | to adjust the sp. */ | |
c906108c SS |
272 | insn = fetch_instruction (prologue_start, 4); |
273 | if (X_OP (insn) == 2 && X_RD (insn) == 14 && X_OP3 (insn) == 0 | |
274 | && X_I (insn) && X_SIMM13 (insn) < 0) | |
275 | { | |
276 | int offset = X_SIMM13 (insn); | |
277 | ||
278 | /* Then look for a save of %i7 into the frame. */ | |
279 | insn = fetch_instruction (prologue_start + 4); | |
280 | if (X_OP (insn) == 3 | |
281 | && X_RD (insn) == 31 | |
282 | && X_OP3 (insn) == 4 | |
283 | && X_RS1 (insn) == 14) | |
284 | { | |
285 | char buf[MAX_REGISTER_RAW_SIZE]; | |
286 | ||
287 | /* We definitely have a flat frame now. */ | |
288 | fi->flat = 1; | |
289 | ||
290 | fi->sp_offset = offset; | |
291 | ||
292 | /* Overwrite the frame's address with the value in %i7. */ | |
293 | get_saved_register (buf, 0, 0, fi, I7_REGNUM, 0); | |
294 | fi->frame = extract_address (buf, REGISTER_RAW_SIZE (I7_REGNUM)); | |
295 | #ifdef GDB_TARGET_IS_SPARC64 | |
296 | if (fi->frame & 1) | |
297 | fi->frame += 2047; | |
298 | #endif | |
299 | /* Record where the fp got saved. */ | |
300 | fi->fp_addr = fi->frame + fi->sp_offset + X_SIMM13 (insn); | |
301 | ||
302 | /* Also try to collect where the pc got saved to. */ | |
303 | fi->pc_addr = 0; | |
304 | insn = fetch_instruction (prologue_start + 12); | |
305 | if (X_OP (insn) == 3 | |
306 | && X_RD (insn) == 15 | |
307 | && X_OP3 (insn) == 4 | |
308 | && X_RS1 (insn) == 14) | |
309 | fi->pc_addr = fi->frame + fi->sp_offset + X_SIMM13 (insn); | |
310 | } | |
311 | } | |
c5aa993b JM |
312 | else |
313 | { | |
314 | /* Check if the PC is in the function prologue before a SAVE | |
315 | instruction has been executed yet. If so, set the frame | |
316 | to the current value of the stack pointer and set | |
317 | the in_prologue flag. */ | |
318 | CORE_ADDR addr; | |
319 | struct symtab_and_line sal; | |
320 | ||
321 | sal = find_pc_line (prologue_start, 0); | |
322 | if (sal.line == 0) /* no line info, use PC */ | |
323 | prologue_end = fi->pc; | |
324 | else if (sal.end < prologue_end) | |
325 | prologue_end = sal.end; | |
326 | if (fi->pc < prologue_end) | |
327 | { | |
328 | for (addr = prologue_start; addr < fi->pc; addr += 4) | |
329 | { | |
330 | insn = read_memory_integer (addr, 4); | |
331 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) | |
332 | break; /* SAVE seen, stop searching */ | |
333 | } | |
334 | if (addr >= fi->pc) | |
335 | { | |
336 | fi->in_prologue = 1; | |
337 | fi->frame = read_register (SP_REGNUM); | |
338 | } | |
339 | } | |
340 | } | |
c906108c SS |
341 | } |
342 | if (fi->next && fi->frame == 0) | |
343 | { | |
344 | /* Kludge to cause init_prev_frame_info to destroy the new frame. */ | |
345 | fi->frame = fi->next->frame; | |
346 | fi->pc = fi->next->pc; | |
347 | } | |
348 | } | |
349 | ||
350 | CORE_ADDR | |
351 | sparc_frame_chain (frame) | |
352 | struct frame_info *frame; | |
353 | { | |
354 | /* Value that will cause FRAME_CHAIN_VALID to not worry about the chain | |
355 | value. If it realy is zero, we detect it later in | |
356 | sparc_init_prev_frame. */ | |
c5aa993b | 357 | return (CORE_ADDR) 1; |
c906108c SS |
358 | } |
359 | ||
360 | CORE_ADDR | |
361 | sparc_extract_struct_value_address (regbuf) | |
362 | char regbuf[REGISTER_BYTES]; | |
363 | { | |
364 | return extract_address (regbuf + REGISTER_BYTE (O0_REGNUM), | |
365 | REGISTER_RAW_SIZE (O0_REGNUM)); | |
366 | } | |
367 | ||
368 | /* Find the pc saved in frame FRAME. */ | |
369 | ||
370 | CORE_ADDR | |
371 | sparc_frame_saved_pc (frame) | |
372 | struct frame_info *frame; | |
373 | { | |
374 | char buf[MAX_REGISTER_RAW_SIZE]; | |
375 | CORE_ADDR addr; | |
376 | ||
377 | if (frame->signal_handler_caller) | |
378 | { | |
379 | /* This is the signal trampoline frame. | |
c5aa993b | 380 | Get the saved PC from the sigcontext structure. */ |
c906108c SS |
381 | |
382 | #ifndef SIGCONTEXT_PC_OFFSET | |
383 | #define SIGCONTEXT_PC_OFFSET 12 | |
384 | #endif | |
385 | ||
386 | CORE_ADDR sigcontext_addr; | |
387 | char scbuf[TARGET_PTR_BIT / HOST_CHAR_BIT]; | |
388 | int saved_pc_offset = SIGCONTEXT_PC_OFFSET; | |
389 | char *name = NULL; | |
390 | ||
391 | /* Solaris2 ucbsigvechandler passes a pointer to a sigcontext | |
c5aa993b | 392 | as the third parameter. The offset to the saved pc is 12. */ |
c906108c | 393 | find_pc_partial_function (frame->pc, &name, |
c5aa993b | 394 | (CORE_ADDR *) NULL, (CORE_ADDR *) NULL); |
c906108c SS |
395 | if (name && STREQ (name, "ucbsigvechandler")) |
396 | saved_pc_offset = 12; | |
397 | ||
398 | /* The sigcontext address is contained in register O2. */ | |
c5aa993b JM |
399 | get_saved_register (buf, (int *) NULL, (CORE_ADDR *) NULL, |
400 | frame, O0_REGNUM + 2, (enum lval_type *) NULL); | |
c906108c SS |
401 | sigcontext_addr = extract_address (buf, REGISTER_RAW_SIZE (O0_REGNUM + 2)); |
402 | ||
403 | /* Don't cause a memory_error when accessing sigcontext in case the | |
c5aa993b | 404 | stack layout has changed or the stack is corrupt. */ |
c906108c SS |
405 | target_read_memory (sigcontext_addr + saved_pc_offset, |
406 | scbuf, sizeof (scbuf)); | |
407 | return extract_address (scbuf, sizeof (scbuf)); | |
408 | } | |
409 | else if (frame->in_prologue || | |
410 | (frame->next != NULL | |
411 | && (frame->next->signal_handler_caller | |
c5aa993b | 412 | || frame_in_dummy (frame->next)) |
c906108c SS |
413 | && frameless_look_for_prologue (frame))) |
414 | { | |
415 | /* A frameless function interrupted by a signal did not save | |
c5aa993b JM |
416 | the PC, it is still in %o7. */ |
417 | get_saved_register (buf, (int *) NULL, (CORE_ADDR *) NULL, | |
418 | frame, O7_REGNUM, (enum lval_type *) NULL); | |
c906108c SS |
419 | return PC_ADJUST (extract_address (buf, SPARC_INTREG_SIZE)); |
420 | } | |
421 | if (frame->flat) | |
422 | addr = frame->pc_addr; | |
423 | else | |
424 | addr = frame->bottom + FRAME_SAVED_I0 + | |
425 | SPARC_INTREG_SIZE * (I7_REGNUM - I0_REGNUM); | |
426 | ||
427 | if (addr == 0) | |
428 | /* A flat frame leaf function might not save the PC anywhere, | |
429 | just leave it in %o7. */ | |
430 | return PC_ADJUST (read_register (O7_REGNUM)); | |
431 | ||
432 | read_memory (addr, buf, SPARC_INTREG_SIZE); | |
433 | return PC_ADJUST (extract_address (buf, SPARC_INTREG_SIZE)); | |
434 | } | |
435 | ||
436 | /* Since an individual frame in the frame cache is defined by two | |
437 | arguments (a frame pointer and a stack pointer), we need two | |
438 | arguments to get info for an arbitrary stack frame. This routine | |
439 | takes two arguments and makes the cached frames look as if these | |
440 | two arguments defined a frame on the cache. This allows the rest | |
441 | of info frame to extract the important arguments without | |
442 | difficulty. */ | |
443 | ||
444 | struct frame_info * | |
445 | setup_arbitrary_frame (argc, argv) | |
446 | int argc; | |
447 | CORE_ADDR *argv; | |
448 | { | |
449 | struct frame_info *frame; | |
450 | ||
451 | if (argc != 2) | |
452 | error ("Sparc frame specifications require two arguments: fp and sp"); | |
453 | ||
454 | frame = create_new_frame (argv[0], 0); | |
455 | ||
456 | if (!frame) | |
96baa820 | 457 | internal_error ("create_new_frame returned invalid frame"); |
c5aa993b | 458 | |
c906108c SS |
459 | frame->bottom = argv[1]; |
460 | frame->pc = FRAME_SAVED_PC (frame); | |
461 | return frame; | |
462 | } | |
463 | ||
464 | /* Given a pc value, skip it forward past the function prologue by | |
465 | disassembling instructions that appear to be a prologue. | |
466 | ||
467 | If FRAMELESS_P is set, we are only testing to see if the function | |
468 | is frameless. This allows a quicker answer. | |
469 | ||
470 | This routine should be more specific in its actions; making sure | |
471 | that it uses the same register in the initial prologue section. */ | |
472 | ||
473 | static CORE_ADDR examine_prologue PARAMS ((CORE_ADDR, int, struct frame_info *, | |
474 | struct frame_saved_regs *)); | |
475 | ||
c5aa993b | 476 | static CORE_ADDR |
c906108c SS |
477 | examine_prologue (start_pc, frameless_p, fi, saved_regs) |
478 | CORE_ADDR start_pc; | |
479 | int frameless_p; | |
480 | struct frame_info *fi; | |
481 | struct frame_saved_regs *saved_regs; | |
482 | { | |
483 | int insn; | |
484 | int dest = -1; | |
485 | CORE_ADDR pc = start_pc; | |
486 | int is_flat = 0; | |
487 | ||
488 | insn = fetch_instruction (pc); | |
489 | ||
490 | /* Recognize the `sethi' insn and record its destination. */ | |
491 | if (X_OP (insn) == 0 && X_OP2 (insn) == 4) | |
492 | { | |
493 | dest = X_RD (insn); | |
494 | pc += 4; | |
495 | insn = fetch_instruction (pc); | |
496 | } | |
497 | ||
498 | /* Recognize an add immediate value to register to either %g1 or | |
499 | the destination register recorded above. Actually, this might | |
500 | well recognize several different arithmetic operations. | |
501 | It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1" | |
502 | followed by "save %sp, %g1, %sp" is a valid prologue (Not that | |
503 | I imagine any compiler really does that, however). */ | |
504 | if (X_OP (insn) == 2 | |
505 | && X_I (insn) | |
506 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) | |
507 | { | |
508 | pc += 4; | |
509 | insn = fetch_instruction (pc); | |
510 | } | |
511 | ||
512 | /* Recognize any SAVE insn. */ | |
513 | if (X_OP (insn) == 2 && X_OP3 (insn) == 60) | |
514 | { | |
515 | pc += 4; | |
c5aa993b JM |
516 | if (frameless_p) /* If the save is all we care about, */ |
517 | return pc; /* return before doing more work */ | |
c906108c SS |
518 | insn = fetch_instruction (pc); |
519 | } | |
520 | /* Recognize add to %sp. */ | |
521 | else if (X_OP (insn) == 2 && X_RD (insn) == 14 && X_OP3 (insn) == 0) | |
522 | { | |
523 | pc += 4; | |
c5aa993b JM |
524 | if (frameless_p) /* If the add is all we care about, */ |
525 | return pc; /* return before doing more work */ | |
c906108c SS |
526 | is_flat = 1; |
527 | insn = fetch_instruction (pc); | |
528 | /* Recognize store of frame pointer (i7). */ | |
529 | if (X_OP (insn) == 3 | |
530 | && X_RD (insn) == 31 | |
531 | && X_OP3 (insn) == 4 | |
532 | && X_RS1 (insn) == 14) | |
533 | { | |
534 | pc += 4; | |
535 | insn = fetch_instruction (pc); | |
536 | ||
537 | /* Recognize sub %sp, <anything>, %i7. */ | |
c5aa993b | 538 | if (X_OP (insn) == 2 |
c906108c SS |
539 | && X_OP3 (insn) == 4 |
540 | && X_RS1 (insn) == 14 | |
541 | && X_RD (insn) == 31) | |
542 | { | |
543 | pc += 4; | |
544 | insn = fetch_instruction (pc); | |
545 | } | |
546 | else | |
547 | return pc; | |
548 | } | |
549 | else | |
550 | return pc; | |
551 | } | |
552 | else | |
553 | /* Without a save or add instruction, it's not a prologue. */ | |
554 | return start_pc; | |
555 | ||
556 | while (1) | |
557 | { | |
558 | /* Recognize stores into the frame from the input registers. | |
c5aa993b JM |
559 | This recognizes all non alternate stores of input register, |
560 | into a location offset from the frame pointer. */ | |
c906108c | 561 | if ((X_OP (insn) == 3 |
c5aa993b JM |
562 | && (X_OP3 (insn) & 0x3c) == 4 /* Store, non-alternate. */ |
563 | && (X_RD (insn) & 0x18) == 0x18 /* Input register. */ | |
564 | && X_I (insn) /* Immediate mode. */ | |
c906108c | 565 | && X_RS1 (insn) == 30 /* Off of frame pointer. */ |
c5aa993b | 566 | /* Into reserved stack space. */ |
c906108c SS |
567 | && X_SIMM13 (insn) >= 0x44 |
568 | && X_SIMM13 (insn) < 0x5b)) | |
569 | ; | |
570 | else if (is_flat | |
571 | && X_OP (insn) == 3 | |
572 | && X_OP3 (insn) == 4 | |
573 | && X_RS1 (insn) == 14 | |
c5aa993b | 574 | ) |
c906108c SS |
575 | { |
576 | if (saved_regs && X_I (insn)) | |
577 | saved_regs->regs[X_RD (insn)] = | |
578 | fi->frame + fi->sp_offset + X_SIMM13 (insn); | |
579 | } | |
580 | else | |
581 | break; | |
582 | pc += 4; | |
583 | insn = fetch_instruction (pc); | |
584 | } | |
585 | ||
586 | return pc; | |
587 | } | |
588 | ||
c5aa993b | 589 | CORE_ADDR |
b83266a0 | 590 | sparc_skip_prologue (start_pc, frameless_p) |
c906108c SS |
591 | CORE_ADDR start_pc; |
592 | int frameless_p; | |
593 | { | |
594 | return examine_prologue (start_pc, frameless_p, NULL, NULL); | |
595 | } | |
596 | ||
597 | /* Check instruction at ADDR to see if it is a branch. | |
598 | All non-annulled instructions will go to NPC or will trap. | |
599 | Set *TARGET if we find a candidate branch; set to zero if not. | |
600 | ||
601 | This isn't static as it's used by remote-sa.sparc.c. */ | |
602 | ||
603 | static branch_type | |
604 | isbranch (instruction, addr, target) | |
605 | long instruction; | |
606 | CORE_ADDR addr, *target; | |
607 | { | |
608 | branch_type val = not_branch; | |
609 | long int offset = 0; /* Must be signed for sign-extend. */ | |
610 | ||
611 | *target = 0; | |
612 | ||
613 | if (X_OP (instruction) == 0 | |
614 | && (X_OP2 (instruction) == 2 | |
615 | || X_OP2 (instruction) == 6 | |
616 | || X_OP2 (instruction) == 1 | |
617 | || X_OP2 (instruction) == 3 | |
618 | || X_OP2 (instruction) == 5 | |
619 | #ifndef GDB_TARGET_IS_SPARC64 | |
620 | || X_OP2 (instruction) == 7 | |
621 | #endif | |
c5aa993b | 622 | )) |
c906108c SS |
623 | { |
624 | if (X_COND (instruction) == 8) | |
625 | val = X_A (instruction) ? baa : ba; | |
626 | else | |
627 | val = X_A (instruction) ? bicca : bicc; | |
628 | switch (X_OP2 (instruction)) | |
629 | { | |
630 | case 2: | |
631 | case 6: | |
632 | #ifndef GDB_TARGET_IS_SPARC64 | |
633 | case 7: | |
634 | #endif | |
635 | offset = 4 * X_DISP22 (instruction); | |
636 | break; | |
637 | case 1: | |
638 | case 5: | |
639 | offset = 4 * X_DISP19 (instruction); | |
640 | break; | |
641 | case 3: | |
642 | offset = 4 * X_DISP16 (instruction); | |
643 | break; | |
644 | } | |
645 | *target = addr + offset; | |
646 | } | |
647 | #ifdef GDB_TARGET_IS_SPARC64 | |
648 | else if (X_OP (instruction) == 2 | |
649 | && X_OP3 (instruction) == 62) | |
650 | { | |
651 | if (X_FCN (instruction) == 0) | |
652 | { | |
653 | /* done */ | |
654 | *target = read_register (TNPC_REGNUM); | |
655 | val = done_retry; | |
656 | } | |
657 | else if (X_FCN (instruction) == 1) | |
658 | { | |
659 | /* retry */ | |
660 | *target = read_register (TPC_REGNUM); | |
661 | val = done_retry; | |
662 | } | |
663 | } | |
664 | #endif | |
665 | ||
666 | return val; | |
667 | } | |
668 | \f | |
669 | /* Find register number REGNUM relative to FRAME and put its | |
670 | (raw) contents in *RAW_BUFFER. Set *OPTIMIZED if the variable | |
671 | was optimized out (and thus can't be fetched). If the variable | |
672 | was fetched from memory, set *ADDRP to where it was fetched from, | |
673 | otherwise it was fetched from a register. | |
674 | ||
675 | The argument RAW_BUFFER must point to aligned memory. */ | |
676 | ||
677 | void | |
7a292a7a | 678 | sparc_get_saved_register (raw_buffer, optimized, addrp, frame, regnum, lval) |
c906108c SS |
679 | char *raw_buffer; |
680 | int *optimized; | |
681 | CORE_ADDR *addrp; | |
682 | struct frame_info *frame; | |
683 | int regnum; | |
684 | enum lval_type *lval; | |
685 | { | |
686 | struct frame_info *frame1; | |
687 | CORE_ADDR addr; | |
688 | ||
689 | if (!target_has_registers) | |
690 | error ("No registers."); | |
691 | ||
692 | if (optimized) | |
693 | *optimized = 0; | |
694 | ||
695 | addr = 0; | |
696 | ||
697 | /* FIXME This code extracted from infcmd.c; should put elsewhere! */ | |
698 | if (frame == NULL) | |
699 | { | |
700 | /* error ("No selected frame."); */ | |
701 | if (!target_has_registers) | |
c5aa993b JM |
702 | error ("The program has no registers now."); |
703 | if (selected_frame == NULL) | |
704 | error ("No selected frame."); | |
c906108c | 705 | /* Try to use selected frame */ |
c5aa993b | 706 | frame = get_prev_frame (selected_frame); |
c906108c | 707 | if (frame == 0) |
c5aa993b | 708 | error ("Cmd not meaningful in the outermost frame."); |
c906108c SS |
709 | } |
710 | ||
711 | ||
712 | frame1 = frame->next; | |
713 | ||
714 | /* Get saved PC from the frame info if not in innermost frame. */ | |
715 | if (regnum == PC_REGNUM && frame1 != NULL) | |
716 | { | |
717 | if (lval != NULL) | |
718 | *lval = not_lval; | |
719 | if (raw_buffer != NULL) | |
720 | { | |
721 | /* Put it back in target format. */ | |
722 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), frame->pc); | |
723 | } | |
724 | if (addrp != NULL) | |
725 | *addrp = 0; | |
726 | return; | |
727 | } | |
728 | ||
729 | while (frame1 != NULL) | |
730 | { | |
731 | if (frame1->pc >= (frame1->bottom ? frame1->bottom : | |
732 | read_sp ()) | |
733 | && frame1->pc <= FRAME_FP (frame1)) | |
734 | { | |
735 | /* Dummy frame. All but the window regs are in there somewhere. | |
736 | The window registers are saved on the stack, just like in a | |
737 | normal frame. */ | |
738 | if (regnum >= G1_REGNUM && regnum < G1_REGNUM + 7) | |
739 | addr = frame1->frame + (regnum - G0_REGNUM) * SPARC_INTREG_SIZE | |
740 | - (FP_REGISTER_BYTES + 8 * SPARC_INTREG_SIZE); | |
741 | else if (regnum >= I0_REGNUM && regnum < I0_REGNUM + 8) | |
742 | addr = (frame1->prev->bottom | |
743 | + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE | |
744 | + FRAME_SAVED_I0); | |
745 | else if (regnum >= L0_REGNUM && regnum < L0_REGNUM + 8) | |
746 | addr = (frame1->prev->bottom | |
747 | + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE | |
748 | + FRAME_SAVED_L0); | |
749 | else if (regnum >= O0_REGNUM && regnum < O0_REGNUM + 8) | |
750 | addr = frame1->frame + (regnum - O0_REGNUM) * SPARC_INTREG_SIZE | |
751 | - (FP_REGISTER_BYTES + 16 * SPARC_INTREG_SIZE); | |
752 | #ifdef FP0_REGNUM | |
753 | else if (regnum >= FP0_REGNUM && regnum < FP0_REGNUM + 32) | |
754 | addr = frame1->frame + (regnum - FP0_REGNUM) * 4 | |
755 | - (FP_REGISTER_BYTES); | |
756 | #ifdef GDB_TARGET_IS_SPARC64 | |
757 | else if (regnum >= FP0_REGNUM + 32 && regnum < FP_MAX_REGNUM) | |
758 | addr = frame1->frame + 32 * 4 + (regnum - FP0_REGNUM - 32) * 8 | |
759 | - (FP_REGISTER_BYTES); | |
760 | #endif | |
761 | #endif /* FP0_REGNUM */ | |
762 | else if (regnum >= Y_REGNUM && regnum < NUM_REGS) | |
763 | addr = frame1->frame + (regnum - Y_REGNUM) * SPARC_INTREG_SIZE | |
764 | - (FP_REGISTER_BYTES + 24 * SPARC_INTREG_SIZE); | |
765 | } | |
766 | else if (frame1->flat) | |
767 | { | |
768 | ||
769 | if (regnum == RP_REGNUM) | |
770 | addr = frame1->pc_addr; | |
771 | else if (regnum == I7_REGNUM) | |
772 | addr = frame1->fp_addr; | |
773 | else | |
774 | { | |
775 | CORE_ADDR func_start; | |
776 | struct frame_saved_regs regs; | |
777 | memset (®s, 0, sizeof (regs)); | |
778 | ||
779 | find_pc_partial_function (frame1->pc, NULL, &func_start, NULL); | |
780 | examine_prologue (func_start, 0, frame1, ®s); | |
781 | addr = regs.regs[regnum]; | |
782 | } | |
783 | } | |
784 | else | |
785 | { | |
786 | /* Normal frame. Local and In registers are saved on stack. */ | |
787 | if (regnum >= I0_REGNUM && regnum < I0_REGNUM + 8) | |
788 | addr = (frame1->prev->bottom | |
789 | + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE | |
790 | + FRAME_SAVED_I0); | |
791 | else if (regnum >= L0_REGNUM && regnum < L0_REGNUM + 8) | |
792 | addr = (frame1->prev->bottom | |
793 | + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE | |
794 | + FRAME_SAVED_L0); | |
795 | else if (regnum >= O0_REGNUM && regnum < O0_REGNUM + 8) | |
796 | { | |
797 | /* Outs become ins. */ | |
798 | get_saved_register (raw_buffer, optimized, addrp, frame1, | |
799 | (regnum - O0_REGNUM + I0_REGNUM), lval); | |
800 | return; | |
801 | } | |
802 | } | |
803 | if (addr != 0) | |
804 | break; | |
805 | frame1 = frame1->next; | |
806 | } | |
807 | if (addr != 0) | |
808 | { | |
809 | if (lval != NULL) | |
810 | *lval = lval_memory; | |
811 | if (regnum == SP_REGNUM) | |
812 | { | |
813 | if (raw_buffer != NULL) | |
814 | { | |
815 | /* Put it back in target format. */ | |
816 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), addr); | |
817 | } | |
818 | if (addrp != NULL) | |
819 | *addrp = 0; | |
820 | return; | |
821 | } | |
822 | if (raw_buffer != NULL) | |
823 | read_memory (addr, raw_buffer, REGISTER_RAW_SIZE (regnum)); | |
824 | } | |
825 | else | |
826 | { | |
827 | if (lval != NULL) | |
828 | *lval = lval_register; | |
829 | addr = REGISTER_BYTE (regnum); | |
830 | if (raw_buffer != NULL) | |
831 | read_register_gen (regnum, raw_buffer); | |
832 | } | |
833 | if (addrp != NULL) | |
834 | *addrp = addr; | |
835 | } | |
836 | ||
837 | /* Push an empty stack frame, and record in it the current PC, regs, etc. | |
838 | ||
839 | We save the non-windowed registers and the ins. The locals and outs | |
840 | are new; they don't need to be saved. The i's and l's of | |
841 | the last frame were already saved on the stack. */ | |
842 | ||
843 | /* Definitely see tm-sparc.h for more doc of the frame format here. */ | |
844 | ||
845 | #ifdef GDB_TARGET_IS_SPARC64 | |
846 | #define DUMMY_REG_SAVE_OFFSET (128 + 16) | |
847 | #else | |
848 | #define DUMMY_REG_SAVE_OFFSET 0x60 | |
849 | #endif | |
850 | ||
851 | /* See tm-sparc.h for how this is calculated. */ | |
852 | #ifdef FP0_REGNUM | |
853 | #define DUMMY_STACK_REG_BUF_SIZE \ | |
854 | (((8+8+8) * SPARC_INTREG_SIZE) + FP_REGISTER_BYTES) | |
855 | #else | |
856 | #define DUMMY_STACK_REG_BUF_SIZE \ | |
857 | (((8+8+8) * SPARC_INTREG_SIZE) ) | |
858 | #endif /* FP0_REGNUM */ | |
859 | #define DUMMY_STACK_SIZE (DUMMY_STACK_REG_BUF_SIZE + DUMMY_REG_SAVE_OFFSET) | |
860 | ||
861 | void | |
862 | sparc_push_dummy_frame () | |
863 | { | |
864 | CORE_ADDR sp, old_sp; | |
865 | char register_temp[DUMMY_STACK_SIZE]; | |
866 | ||
867 | old_sp = sp = read_sp (); | |
868 | ||
869 | #ifdef GDB_TARGET_IS_SPARC64 | |
870 | /* PC, NPC, CCR, FSR, FPRS, Y, ASI */ | |
871 | read_register_bytes (REGISTER_BYTE (PC_REGNUM), ®ister_temp[0], | |
872 | REGISTER_RAW_SIZE (PC_REGNUM) * 7); | |
873 | read_register_bytes (REGISTER_BYTE (PSTATE_REGNUM), ®ister_temp[8], | |
874 | REGISTER_RAW_SIZE (PSTATE_REGNUM)); | |
875 | /* FIXME: not sure what needs to be saved here. */ | |
876 | #else | |
877 | /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */ | |
878 | read_register_bytes (REGISTER_BYTE (Y_REGNUM), ®ister_temp[0], | |
879 | REGISTER_RAW_SIZE (Y_REGNUM) * 8); | |
880 | #endif | |
881 | ||
882 | read_register_bytes (REGISTER_BYTE (O0_REGNUM), | |
883 | ®ister_temp[8 * SPARC_INTREG_SIZE], | |
884 | SPARC_INTREG_SIZE * 8); | |
885 | ||
886 | read_register_bytes (REGISTER_BYTE (G0_REGNUM), | |
887 | ®ister_temp[16 * SPARC_INTREG_SIZE], | |
888 | SPARC_INTREG_SIZE * 8); | |
889 | ||
890 | #ifdef FP0_REGNUM | |
891 | read_register_bytes (REGISTER_BYTE (FP0_REGNUM), | |
892 | ®ister_temp[24 * SPARC_INTREG_SIZE], | |
893 | FP_REGISTER_BYTES); | |
894 | #endif /* FP0_REGNUM */ | |
895 | ||
896 | sp -= DUMMY_STACK_SIZE; | |
897 | ||
898 | write_sp (sp); | |
899 | ||
900 | write_memory (sp + DUMMY_REG_SAVE_OFFSET, ®ister_temp[0], | |
901 | DUMMY_STACK_REG_BUF_SIZE); | |
902 | ||
903 | if (strcmp (target_shortname, "sim") != 0) | |
904 | { | |
905 | write_fp (old_sp); | |
906 | ||
907 | /* Set return address register for the call dummy to the current PC. */ | |
c5aa993b | 908 | write_register (I7_REGNUM, read_pc () - 8); |
c906108c SS |
909 | } |
910 | else | |
911 | { | |
912 | /* The call dummy will write this value to FP before executing | |
913 | the 'save'. This ensures that register window flushes work | |
c5aa993b JM |
914 | correctly in the simulator. */ |
915 | write_register (G0_REGNUM + 1, read_register (FP_REGNUM)); | |
916 | ||
c906108c SS |
917 | /* The call dummy will write this value to FP after executing |
918 | the 'save'. */ | |
c5aa993b JM |
919 | write_register (G0_REGNUM + 2, old_sp); |
920 | ||
c906108c | 921 | /* The call dummy will write this value to the return address (%i7) after |
c5aa993b JM |
922 | executing the 'save'. */ |
923 | write_register (G0_REGNUM + 3, read_pc () - 8); | |
924 | ||
c906108c | 925 | /* Set the FP that the call dummy will be using after the 'save'. |
c5aa993b | 926 | This makes backtraces from an inferior function call work properly. */ |
c906108c SS |
927 | write_register (FP_REGNUM, old_sp); |
928 | } | |
929 | } | |
930 | ||
931 | /* sparc_frame_find_saved_regs (). This function is here only because | |
932 | pop_frame uses it. Note there is an interesting corner case which | |
933 | I think few ports of GDB get right--if you are popping a frame | |
934 | which does not save some register that *is* saved by a more inner | |
935 | frame (such a frame will never be a dummy frame because dummy | |
936 | frames save all registers). Rewriting pop_frame to use | |
937 | get_saved_register would solve this problem and also get rid of the | |
938 | ugly duplication between sparc_frame_find_saved_regs and | |
939 | get_saved_register. | |
940 | ||
941 | Stores, into a struct frame_saved_regs, | |
942 | the addresses of the saved registers of frame described by FRAME_INFO. | |
943 | This includes special registers such as pc and fp saved in special | |
944 | ways in the stack frame. sp is even more special: | |
945 | the address we return for it IS the sp for the next frame. | |
946 | ||
947 | Note that on register window machines, we are currently making the | |
948 | assumption that window registers are being saved somewhere in the | |
949 | frame in which they are being used. If they are stored in an | |
950 | inferior frame, find_saved_register will break. | |
951 | ||
952 | On the Sun 4, the only time all registers are saved is when | |
953 | a dummy frame is involved. Otherwise, the only saved registers | |
954 | are the LOCAL and IN registers which are saved as a result | |
955 | of the "save/restore" opcodes. This condition is determined | |
956 | by address rather than by value. | |
957 | ||
958 | The "pc" is not stored in a frame on the SPARC. (What is stored | |
959 | is a return address minus 8.) sparc_pop_frame knows how to | |
960 | deal with that. Other routines might or might not. | |
961 | ||
962 | See tm-sparc.h (PUSH_DUMMY_FRAME and friends) for CRITICAL information | |
963 | about how this works. */ | |
964 | ||
965 | static void sparc_frame_find_saved_regs PARAMS ((struct frame_info *, | |
966 | struct frame_saved_regs *)); | |
967 | ||
968 | static void | |
969 | sparc_frame_find_saved_regs (fi, saved_regs_addr) | |
970 | struct frame_info *fi; | |
971 | struct frame_saved_regs *saved_regs_addr; | |
972 | { | |
973 | register int regnum; | |
974 | CORE_ADDR frame_addr = FRAME_FP (fi); | |
975 | ||
976 | if (!fi) | |
96baa820 | 977 | internal_error ("Bad frame info struct in FRAME_FIND_SAVED_REGS"); |
c906108c SS |
978 | |
979 | memset (saved_regs_addr, 0, sizeof (*saved_regs_addr)); | |
980 | ||
981 | if (fi->pc >= (fi->bottom ? fi->bottom : | |
c5aa993b JM |
982 | read_sp ()) |
983 | && fi->pc <= FRAME_FP (fi)) | |
c906108c SS |
984 | { |
985 | /* Dummy frame. All but the window regs are in there somewhere. */ | |
c5aa993b | 986 | for (regnum = G1_REGNUM; regnum < G1_REGNUM + 7; regnum++) |
c906108c SS |
987 | saved_regs_addr->regs[regnum] = |
988 | frame_addr + (regnum - G0_REGNUM) * SPARC_INTREG_SIZE | |
c5aa993b JM |
989 | - DUMMY_STACK_REG_BUF_SIZE + 16 * SPARC_INTREG_SIZE; |
990 | for (regnum = I0_REGNUM; regnum < I0_REGNUM + 8; regnum++) | |
c906108c SS |
991 | saved_regs_addr->regs[regnum] = |
992 | frame_addr + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE | |
c5aa993b | 993 | - DUMMY_STACK_REG_BUF_SIZE + 8 * SPARC_INTREG_SIZE; |
c906108c SS |
994 | #ifdef FP0_REGNUM |
995 | for (regnum = FP0_REGNUM; regnum < FP0_REGNUM + 32; regnum++) | |
996 | saved_regs_addr->regs[regnum] = | |
997 | frame_addr + (regnum - FP0_REGNUM) * 4 | |
c5aa993b | 998 | - DUMMY_STACK_REG_BUF_SIZE + 24 * SPARC_INTREG_SIZE; |
c906108c SS |
999 | #ifdef GDB_TARGET_IS_SPARC64 |
1000 | for (regnum = FP0_REGNUM + 32; regnum < FP_MAX_REGNUM; regnum++) | |
1001 | saved_regs_addr->regs[regnum] = | |
1002 | frame_addr + 32 * 4 + (regnum - FP0_REGNUM - 32) * 4 | |
c5aa993b | 1003 | - DUMMY_STACK_REG_BUF_SIZE + 24 * SPARC_INTREG_SIZE; |
c906108c SS |
1004 | #endif |
1005 | #endif /* FP0_REGNUM */ | |
1006 | #ifdef GDB_TARGET_IS_SPARC64 | |
1007 | for (regnum = PC_REGNUM; regnum < PC_REGNUM + 7; regnum++) | |
1008 | { | |
1009 | saved_regs_addr->regs[regnum] = | |
c5aa993b JM |
1010 | frame_addr + (regnum - PC_REGNUM) * SPARC_INTREG_SIZE |
1011 | - DUMMY_STACK_REG_BUF_SIZE; | |
c906108c | 1012 | } |
c5aa993b | 1013 | saved_regs_addr->regs[PSTATE_REGNUM] = |
c906108c SS |
1014 | frame_addr + 8 * SPARC_INTREG_SIZE - DUMMY_STACK_REG_BUF_SIZE; |
1015 | #else | |
1016 | for (regnum = Y_REGNUM; regnum < NUM_REGS; regnum++) | |
1017 | saved_regs_addr->regs[regnum] = | |
c5aa993b JM |
1018 | frame_addr + (regnum - Y_REGNUM) * SPARC_INTREG_SIZE |
1019 | - DUMMY_STACK_REG_BUF_SIZE; | |
c906108c SS |
1020 | #endif |
1021 | frame_addr = fi->bottom ? | |
1022 | fi->bottom : read_sp (); | |
1023 | } | |
1024 | else if (fi->flat) | |
1025 | { | |
1026 | CORE_ADDR func_start; | |
1027 | find_pc_partial_function (fi->pc, NULL, &func_start, NULL); | |
1028 | examine_prologue (func_start, 0, fi, saved_regs_addr); | |
1029 | ||
1030 | /* Flat register window frame. */ | |
1031 | saved_regs_addr->regs[RP_REGNUM] = fi->pc_addr; | |
1032 | saved_regs_addr->regs[I7_REGNUM] = fi->fp_addr; | |
1033 | } | |
1034 | else | |
1035 | { | |
1036 | /* Normal frame. Just Local and In registers */ | |
1037 | frame_addr = fi->bottom ? | |
1038 | fi->bottom : read_sp (); | |
c5aa993b | 1039 | for (regnum = L0_REGNUM; regnum < L0_REGNUM + 8; regnum++) |
c906108c SS |
1040 | saved_regs_addr->regs[regnum] = |
1041 | (frame_addr + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE | |
1042 | + FRAME_SAVED_L0); | |
c5aa993b | 1043 | for (regnum = I0_REGNUM; regnum < I0_REGNUM + 8; regnum++) |
c906108c SS |
1044 | saved_regs_addr->regs[regnum] = |
1045 | (frame_addr + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE | |
1046 | + FRAME_SAVED_I0); | |
1047 | } | |
1048 | if (fi->next) | |
1049 | { | |
1050 | if (fi->flat) | |
1051 | { | |
1052 | saved_regs_addr->regs[O7_REGNUM] = fi->pc_addr; | |
1053 | } | |
1054 | else | |
1055 | { | |
1056 | /* Pull off either the next frame pointer or the stack pointer */ | |
1057 | CORE_ADDR next_next_frame_addr = | |
c5aa993b JM |
1058 | (fi->next->bottom ? |
1059 | fi->next->bottom : | |
1060 | read_sp ()); | |
1061 | for (regnum = O0_REGNUM; regnum < O0_REGNUM + 8; regnum++) | |
c906108c SS |
1062 | saved_regs_addr->regs[regnum] = |
1063 | (next_next_frame_addr | |
1064 | + (regnum - O0_REGNUM) * SPARC_INTREG_SIZE | |
1065 | + FRAME_SAVED_I0); | |
1066 | } | |
1067 | } | |
1068 | /* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */ | |
1069 | /* FIXME -- should this adjust for the sparc64 offset? */ | |
1070 | saved_regs_addr->regs[SP_REGNUM] = FRAME_FP (fi); | |
1071 | } | |
1072 | ||
1073 | /* Discard from the stack the innermost frame, restoring all saved registers. | |
1074 | ||
1075 | Note that the values stored in fsr by get_frame_saved_regs are *in | |
1076 | the context of the called frame*. What this means is that the i | |
1077 | regs of fsr must be restored into the o regs of the (calling) frame that | |
1078 | we pop into. We don't care about the output regs of the calling frame, | |
1079 | since unless it's a dummy frame, it won't have any output regs in it. | |
1080 | ||
1081 | We never have to bother with %l (local) regs, since the called routine's | |
1082 | locals get tossed, and the calling routine's locals are already saved | |
1083 | on its stack. */ | |
1084 | ||
1085 | /* Definitely see tm-sparc.h for more doc of the frame format here. */ | |
1086 | ||
1087 | void | |
1088 | sparc_pop_frame () | |
1089 | { | |
1090 | register struct frame_info *frame = get_current_frame (); | |
1091 | register CORE_ADDR pc; | |
1092 | struct frame_saved_regs fsr; | |
1093 | char raw_buffer[REGISTER_BYTES]; | |
1094 | int regnum; | |
1095 | ||
1096 | sparc_frame_find_saved_regs (frame, &fsr); | |
1097 | #ifdef FP0_REGNUM | |
1098 | if (fsr.regs[FP0_REGNUM]) | |
1099 | { | |
1100 | read_memory (fsr.regs[FP0_REGNUM], raw_buffer, FP_REGISTER_BYTES); | |
1101 | write_register_bytes (REGISTER_BYTE (FP0_REGNUM), | |
1102 | raw_buffer, FP_REGISTER_BYTES); | |
1103 | } | |
1104 | #ifndef GDB_TARGET_IS_SPARC64 | |
1105 | if (fsr.regs[FPS_REGNUM]) | |
1106 | { | |
1107 | read_memory (fsr.regs[FPS_REGNUM], raw_buffer, 4); | |
1108 | write_register_bytes (REGISTER_BYTE (FPS_REGNUM), raw_buffer, 4); | |
1109 | } | |
1110 | if (fsr.regs[CPS_REGNUM]) | |
1111 | { | |
1112 | read_memory (fsr.regs[CPS_REGNUM], raw_buffer, 4); | |
1113 | write_register_bytes (REGISTER_BYTE (CPS_REGNUM), raw_buffer, 4); | |
1114 | } | |
1115 | #endif | |
1116 | #endif /* FP0_REGNUM */ | |
1117 | if (fsr.regs[G1_REGNUM]) | |
1118 | { | |
1119 | read_memory (fsr.regs[G1_REGNUM], raw_buffer, 7 * SPARC_INTREG_SIZE); | |
1120 | write_register_bytes (REGISTER_BYTE (G1_REGNUM), raw_buffer, | |
1121 | 7 * SPARC_INTREG_SIZE); | |
1122 | } | |
1123 | ||
1124 | if (frame->flat) | |
1125 | { | |
1126 | /* Each register might or might not have been saved, need to test | |
c5aa993b | 1127 | individually. */ |
c906108c SS |
1128 | for (regnum = L0_REGNUM; regnum < L0_REGNUM + 8; ++regnum) |
1129 | if (fsr.regs[regnum]) | |
1130 | write_register (regnum, read_memory_integer (fsr.regs[regnum], | |
1131 | SPARC_INTREG_SIZE)); | |
1132 | for (regnum = I0_REGNUM; regnum < I0_REGNUM + 8; ++regnum) | |
1133 | if (fsr.regs[regnum]) | |
1134 | write_register (regnum, read_memory_integer (fsr.regs[regnum], | |
1135 | SPARC_INTREG_SIZE)); | |
1136 | ||
1137 | /* Handle all outs except stack pointer (o0-o5; o7). */ | |
1138 | for (regnum = O0_REGNUM; regnum < O0_REGNUM + 6; ++regnum) | |
1139 | if (fsr.regs[regnum]) | |
1140 | write_register (regnum, read_memory_integer (fsr.regs[regnum], | |
1141 | SPARC_INTREG_SIZE)); | |
1142 | if (fsr.regs[O0_REGNUM + 7]) | |
1143 | write_register (O0_REGNUM + 7, | |
1144 | read_memory_integer (fsr.regs[O0_REGNUM + 7], | |
1145 | SPARC_INTREG_SIZE)); | |
1146 | ||
1147 | write_sp (frame->frame); | |
1148 | } | |
1149 | else if (fsr.regs[I0_REGNUM]) | |
1150 | { | |
1151 | CORE_ADDR sp; | |
1152 | ||
1153 | char reg_temp[REGISTER_BYTES]; | |
1154 | ||
1155 | read_memory (fsr.regs[I0_REGNUM], raw_buffer, 8 * SPARC_INTREG_SIZE); | |
1156 | ||
1157 | /* Get the ins and locals which we are about to restore. Just | |
c5aa993b JM |
1158 | moving the stack pointer is all that is really needed, except |
1159 | store_inferior_registers is then going to write the ins and | |
1160 | locals from the registers array, so we need to muck with the | |
1161 | registers array. */ | |
c906108c SS |
1162 | sp = fsr.regs[SP_REGNUM]; |
1163 | #ifdef GDB_TARGET_IS_SPARC64 | |
1164 | if (sp & 1) | |
1165 | sp += 2047; | |
1166 | #endif | |
1167 | read_memory (sp, reg_temp, SPARC_INTREG_SIZE * 16); | |
1168 | ||
1169 | /* Restore the out registers. | |
c5aa993b | 1170 | Among other things this writes the new stack pointer. */ |
c906108c SS |
1171 | write_register_bytes (REGISTER_BYTE (O0_REGNUM), raw_buffer, |
1172 | SPARC_INTREG_SIZE * 8); | |
1173 | ||
1174 | write_register_bytes (REGISTER_BYTE (L0_REGNUM), reg_temp, | |
1175 | SPARC_INTREG_SIZE * 16); | |
1176 | } | |
1177 | #ifndef GDB_TARGET_IS_SPARC64 | |
1178 | if (fsr.regs[PS_REGNUM]) | |
1179 | write_register (PS_REGNUM, read_memory_integer (fsr.regs[PS_REGNUM], 4)); | |
1180 | #endif | |
1181 | if (fsr.regs[Y_REGNUM]) | |
1182 | write_register (Y_REGNUM, read_memory_integer (fsr.regs[Y_REGNUM], REGISTER_RAW_SIZE (Y_REGNUM))); | |
1183 | if (fsr.regs[PC_REGNUM]) | |
1184 | { | |
1185 | /* Explicitly specified PC (and maybe NPC) -- just restore them. */ | |
1186 | write_register (PC_REGNUM, read_memory_integer (fsr.regs[PC_REGNUM], | |
c5aa993b | 1187 | REGISTER_RAW_SIZE (PC_REGNUM))); |
c906108c SS |
1188 | if (fsr.regs[NPC_REGNUM]) |
1189 | write_register (NPC_REGNUM, | |
1190 | read_memory_integer (fsr.regs[NPC_REGNUM], | |
c5aa993b | 1191 | REGISTER_RAW_SIZE (NPC_REGNUM))); |
c906108c SS |
1192 | } |
1193 | else if (frame->flat) | |
1194 | { | |
1195 | if (frame->pc_addr) | |
1196 | pc = PC_ADJUST ((CORE_ADDR) | |
1197 | read_memory_integer (frame->pc_addr, | |
1198 | REGISTER_RAW_SIZE (PC_REGNUM))); | |
1199 | else | |
1200 | { | |
1201 | /* I think this happens only in the innermost frame, if so then | |
1202 | it is a complicated way of saying | |
1203 | "pc = read_register (O7_REGNUM);". */ | |
1204 | char buf[MAX_REGISTER_RAW_SIZE]; | |
1205 | get_saved_register (buf, 0, 0, frame, O7_REGNUM, 0); | |
1206 | pc = PC_ADJUST (extract_address | |
1207 | (buf, REGISTER_RAW_SIZE (O7_REGNUM))); | |
1208 | } | |
1209 | ||
c5aa993b | 1210 | write_register (PC_REGNUM, pc); |
c906108c SS |
1211 | write_register (NPC_REGNUM, pc + 4); |
1212 | } | |
1213 | else if (fsr.regs[I7_REGNUM]) | |
1214 | { | |
1215 | /* Return address in %i7 -- adjust it, then restore PC and NPC from it */ | |
1216 | pc = PC_ADJUST ((CORE_ADDR) read_memory_integer (fsr.regs[I7_REGNUM], | |
1217 | SPARC_INTREG_SIZE)); | |
c5aa993b | 1218 | write_register (PC_REGNUM, pc); |
c906108c SS |
1219 | write_register (NPC_REGNUM, pc + 4); |
1220 | } | |
1221 | flush_cached_frames (); | |
1222 | } | |
1223 | ||
1224 | /* On the Sun 4 under SunOS, the compile will leave a fake insn which | |
1225 | encodes the structure size being returned. If we detect such | |
1226 | a fake insn, step past it. */ | |
1227 | ||
1228 | CORE_ADDR | |
c5aa993b | 1229 | sparc_pc_adjust (pc) |
c906108c SS |
1230 | CORE_ADDR pc; |
1231 | { | |
1232 | unsigned long insn; | |
1233 | char buf[4]; | |
1234 | int err; | |
1235 | ||
1236 | err = target_read_memory (pc + 8, buf, 4); | |
1237 | insn = extract_unsigned_integer (buf, 4); | |
1238 | if ((err == 0) && (insn & 0xffc00000) == 0) | |
c5aa993b | 1239 | return pc + 12; |
c906108c | 1240 | else |
c5aa993b | 1241 | return pc + 8; |
c906108c SS |
1242 | } |
1243 | ||
1244 | /* If pc is in a shared library trampoline, return its target. | |
1245 | The SunOs 4.x linker rewrites the jump table entries for PIC | |
1246 | compiled modules in the main executable to bypass the dynamic linker | |
1247 | with jumps of the form | |
c5aa993b JM |
1248 | sethi %hi(addr),%g1 |
1249 | jmp %g1+%lo(addr) | |
c906108c SS |
1250 | and removes the corresponding jump table relocation entry in the |
1251 | dynamic relocations. | |
1252 | find_solib_trampoline_target relies on the presence of the jump | |
1253 | table relocation entry, so we have to detect these jump instructions | |
1254 | by hand. */ | |
1255 | ||
1256 | CORE_ADDR | |
1257 | sunos4_skip_trampoline_code (pc) | |
1258 | CORE_ADDR pc; | |
1259 | { | |
1260 | unsigned long insn1; | |
1261 | char buf[4]; | |
1262 | int err; | |
1263 | ||
1264 | err = target_read_memory (pc, buf, 4); | |
1265 | insn1 = extract_unsigned_integer (buf, 4); | |
1266 | if (err == 0 && (insn1 & 0xffc00000) == 0x03000000) | |
1267 | { | |
1268 | unsigned long insn2; | |
1269 | ||
1270 | err = target_read_memory (pc + 4, buf, 4); | |
1271 | insn2 = extract_unsigned_integer (buf, 4); | |
1272 | if (err == 0 && (insn2 & 0xffffe000) == 0x81c06000) | |
1273 | { | |
1274 | CORE_ADDR target_pc = (insn1 & 0x3fffff) << 10; | |
1275 | int delta = insn2 & 0x1fff; | |
1276 | ||
1277 | /* Sign extend the displacement. */ | |
1278 | if (delta & 0x1000) | |
1279 | delta |= ~0x1fff; | |
1280 | return target_pc + delta; | |
1281 | } | |
1282 | } | |
1283 | return find_solib_trampoline_target (pc); | |
1284 | } | |
1285 | \f | |
c5aa993b | 1286 | #ifdef USE_PROC_FS /* Target dependent support for /proc */ |
9846de1b | 1287 | /* *INDENT-OFF* */ |
c906108c SS |
1288 | /* The /proc interface divides the target machine's register set up into |
1289 | two different sets, the general register set (gregset) and the floating | |
1290 | point register set (fpregset). For each set, there is an ioctl to get | |
1291 | the current register set and another ioctl to set the current values. | |
1292 | ||
1293 | The actual structure passed through the ioctl interface is, of course, | |
1294 | naturally machine dependent, and is different for each set of registers. | |
1295 | For the sparc for example, the general register set is typically defined | |
1296 | by: | |
1297 | ||
1298 | typedef int gregset_t[38]; | |
1299 | ||
1300 | #define R_G0 0 | |
1301 | ... | |
1302 | #define R_TBR 37 | |
1303 | ||
1304 | and the floating point set by: | |
1305 | ||
1306 | typedef struct prfpregset { | |
1307 | union { | |
1308 | u_long pr_regs[32]; | |
1309 | double pr_dregs[16]; | |
1310 | } pr_fr; | |
1311 | void * pr_filler; | |
1312 | u_long pr_fsr; | |
1313 | u_char pr_qcnt; | |
1314 | u_char pr_q_entrysize; | |
1315 | u_char pr_en; | |
1316 | u_long pr_q[64]; | |
1317 | } prfpregset_t; | |
1318 | ||
1319 | These routines provide the packing and unpacking of gregset_t and | |
1320 | fpregset_t formatted data. | |
1321 | ||
1322 | */ | |
9846de1b | 1323 | /* *INDENT-ON* */ |
c906108c | 1324 | |
c5aa993b JM |
1325 | |
1326 | ||
c906108c SS |
1327 | /* Given a pointer to a general register set in /proc format (gregset_t *), |
1328 | unpack the register contents and supply them as gdb's idea of the current | |
1329 | register values. */ | |
1330 | ||
1331 | void | |
1332 | supply_gregset (gregsetp) | |
c5aa993b | 1333 | prgregset_t *gregsetp; |
c906108c SS |
1334 | { |
1335 | register int regi; | |
1336 | register prgreg_t *regp = (prgreg_t *) gregsetp; | |
c5aa993b JM |
1337 | static char zerobuf[MAX_REGISTER_RAW_SIZE] = |
1338 | {0}; | |
c906108c SS |
1339 | |
1340 | /* GDB register numbers for Gn, On, Ln, In all match /proc reg numbers. */ | |
c5aa993b | 1341 | for (regi = G0_REGNUM; regi <= I7_REGNUM; regi++) |
c906108c SS |
1342 | { |
1343 | supply_register (regi, (char *) (regp + regi)); | |
1344 | } | |
1345 | ||
1346 | /* These require a bit more care. */ | |
1347 | supply_register (PS_REGNUM, (char *) (regp + R_PS)); | |
1348 | supply_register (PC_REGNUM, (char *) (regp + R_PC)); | |
c5aa993b JM |
1349 | supply_register (NPC_REGNUM, (char *) (regp + R_nPC)); |
1350 | supply_register (Y_REGNUM, (char *) (regp + R_Y)); | |
c906108c SS |
1351 | |
1352 | /* Fill inaccessible registers with zero. */ | |
1353 | supply_register (WIM_REGNUM, zerobuf); | |
1354 | supply_register (TBR_REGNUM, zerobuf); | |
1355 | supply_register (CPS_REGNUM, zerobuf); | |
1356 | } | |
1357 | ||
1358 | void | |
1359 | fill_gregset (gregsetp, regno) | |
c5aa993b JM |
1360 | prgregset_t *gregsetp; |
1361 | int regno; | |
c906108c SS |
1362 | { |
1363 | int regi; | |
1364 | register prgreg_t *regp = (prgreg_t *) gregsetp; | |
1365 | ||
c5aa993b | 1366 | for (regi = 0; regi <= R_I7; regi++) |
c906108c SS |
1367 | { |
1368 | if ((regno == -1) || (regno == regi)) | |
1369 | { | |
1370 | *(regp + regi) = *(int *) ®isters[REGISTER_BYTE (regi)]; | |
1371 | } | |
1372 | } | |
1373 | if ((regno == -1) || (regno == PS_REGNUM)) | |
1374 | { | |
1375 | *(regp + R_PS) = *(int *) ®isters[REGISTER_BYTE (PS_REGNUM)]; | |
1376 | } | |
1377 | if ((regno == -1) || (regno == PC_REGNUM)) | |
1378 | { | |
1379 | *(regp + R_PC) = *(int *) ®isters[REGISTER_BYTE (PC_REGNUM)]; | |
1380 | } | |
1381 | if ((regno == -1) || (regno == NPC_REGNUM)) | |
1382 | { | |
1383 | *(regp + R_nPC) = *(int *) ®isters[REGISTER_BYTE (NPC_REGNUM)]; | |
1384 | } | |
1385 | if ((regno == -1) || (regno == Y_REGNUM)) | |
1386 | { | |
1387 | *(regp + R_Y) = *(int *) ®isters[REGISTER_BYTE (Y_REGNUM)]; | |
1388 | } | |
1389 | } | |
1390 | ||
1391 | #if defined (FP0_REGNUM) | |
1392 | ||
1393 | /* Given a pointer to a floating point register set in /proc format | |
c5aa993b JM |
1394 | (fpregset_t *), unpack the register contents and supply them as gdb's |
1395 | idea of the current floating point register values. */ | |
c906108c | 1396 | |
c5aa993b | 1397 | void |
c906108c | 1398 | supply_fpregset (fpregsetp) |
c5aa993b | 1399 | prfpregset_t *fpregsetp; |
c906108c SS |
1400 | { |
1401 | register int regi; | |
1402 | char *from; | |
c5aa993b JM |
1403 | |
1404 | for (regi = FP0_REGNUM; regi < FP_MAX_REGNUM; regi++) | |
c906108c | 1405 | { |
c5aa993b | 1406 | from = (char *) &fpregsetp->pr_fr.pr_regs[regi - FP0_REGNUM]; |
c906108c SS |
1407 | supply_register (regi, from); |
1408 | } | |
1409 | supply_register (FPS_REGNUM, (char *) &(fpregsetp->pr_fsr)); | |
1410 | } | |
1411 | ||
1412 | /* Given a pointer to a floating point register set in /proc format | |
c5aa993b JM |
1413 | (fpregset_t *), update the register specified by REGNO from gdb's idea |
1414 | of the current floating point register set. If REGNO is -1, update | |
1415 | them all. */ | |
c906108c SS |
1416 | /* ??? This will probably need some changes for sparc64. */ |
1417 | ||
1418 | void | |
1419 | fill_fpregset (fpregsetp, regno) | |
c5aa993b JM |
1420 | prfpregset_t *fpregsetp; |
1421 | int regno; | |
c906108c SS |
1422 | { |
1423 | int regi; | |
1424 | char *to; | |
1425 | char *from; | |
1426 | ||
c5aa993b | 1427 | for (regi = FP0_REGNUM; regi < FP_MAX_REGNUM; regi++) |
c906108c SS |
1428 | { |
1429 | if ((regno == -1) || (regno == regi)) | |
1430 | { | |
1431 | from = (char *) ®isters[REGISTER_BYTE (regi)]; | |
c5aa993b | 1432 | to = (char *) &fpregsetp->pr_fr.pr_regs[regi - FP0_REGNUM]; |
c906108c SS |
1433 | memcpy (to, from, REGISTER_RAW_SIZE (regi)); |
1434 | } | |
1435 | } | |
1436 | if ((regno == -1) || (regno == FPS_REGNUM)) | |
1437 | { | |
1438 | fpregsetp->pr_fsr = *(int *) ®isters[REGISTER_BYTE (FPS_REGNUM)]; | |
1439 | } | |
1440 | } | |
1441 | ||
c5aa993b | 1442 | #endif /* defined (FP0_REGNUM) */ |
c906108c | 1443 | |
c5aa993b | 1444 | #endif /* USE_PROC_FS */ |
c906108c SS |
1445 | |
1446 | ||
1447 | #ifdef GET_LONGJMP_TARGET | |
1448 | ||
1449 | /* Figure out where the longjmp will land. We expect that we have just entered | |
1450 | longjmp and haven't yet setup the stack frame, so the args are still in the | |
1451 | output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we | |
1452 | extract the pc (JB_PC) that we will land at. The pc is copied into ADDR. | |
1453 | This routine returns true on success */ | |
1454 | ||
1455 | int | |
1456 | get_longjmp_target (pc) | |
1457 | CORE_ADDR *pc; | |
1458 | { | |
1459 | CORE_ADDR jb_addr; | |
1460 | #define LONGJMP_TARGET_SIZE 4 | |
1461 | char buf[LONGJMP_TARGET_SIZE]; | |
1462 | ||
1463 | jb_addr = read_register (O0_REGNUM); | |
1464 | ||
1465 | if (target_read_memory (jb_addr + JB_PC * JB_ELEMENT_SIZE, buf, | |
1466 | LONGJMP_TARGET_SIZE)) | |
1467 | return 0; | |
1468 | ||
1469 | *pc = extract_address (buf, LONGJMP_TARGET_SIZE); | |
1470 | ||
1471 | return 1; | |
1472 | } | |
1473 | #endif /* GET_LONGJMP_TARGET */ | |
1474 | \f | |
1475 | #ifdef STATIC_TRANSFORM_NAME | |
1476 | /* SunPRO (3.0 at least), encodes the static variables. This is not | |
1477 | related to C++ mangling, it is done for C too. */ | |
1478 | ||
1479 | char * | |
1480 | sunpro_static_transform_name (name) | |
1481 | char *name; | |
1482 | { | |
1483 | char *p; | |
1484 | if (name[0] == '$') | |
1485 | { | |
1486 | /* For file-local statics there will be a dollar sign, a bunch | |
c5aa993b JM |
1487 | of junk (the contents of which match a string given in the |
1488 | N_OPT), a period and the name. For function-local statics | |
1489 | there will be a bunch of junk (which seems to change the | |
1490 | second character from 'A' to 'B'), a period, the name of the | |
1491 | function, and the name. So just skip everything before the | |
1492 | last period. */ | |
c906108c SS |
1493 | p = strrchr (name, '.'); |
1494 | if (p != NULL) | |
1495 | name = p + 1; | |
1496 | } | |
1497 | return name; | |
1498 | } | |
1499 | #endif /* STATIC_TRANSFORM_NAME */ | |
1500 | \f | |
1501 | ||
1502 | /* Utilities for printing registers. | |
1503 | Page numbers refer to the SPARC Architecture Manual. */ | |
1504 | ||
1505 | static void dump_ccreg PARAMS ((char *, int)); | |
1506 | ||
1507 | static void | |
1508 | dump_ccreg (reg, val) | |
1509 | char *reg; | |
1510 | int val; | |
1511 | { | |
1512 | /* page 41 */ | |
1513 | printf_unfiltered ("%s:%s,%s,%s,%s", reg, | |
c5aa993b JM |
1514 | val & 8 ? "N" : "NN", |
1515 | val & 4 ? "Z" : "NZ", | |
1516 | val & 2 ? "O" : "NO", | |
1517 | val & 1 ? "C" : "NC" | |
1518 | ); | |
c906108c SS |
1519 | } |
1520 | ||
1521 | static char * | |
1522 | decode_asi (val) | |
1523 | int val; | |
1524 | { | |
1525 | /* page 72 */ | |
1526 | switch (val) | |
1527 | { | |
c5aa993b JM |
1528 | case 4: |
1529 | return "ASI_NUCLEUS"; | |
1530 | case 0x0c: | |
1531 | return "ASI_NUCLEUS_LITTLE"; | |
1532 | case 0x10: | |
1533 | return "ASI_AS_IF_USER_PRIMARY"; | |
1534 | case 0x11: | |
1535 | return "ASI_AS_IF_USER_SECONDARY"; | |
1536 | case 0x18: | |
1537 | return "ASI_AS_IF_USER_PRIMARY_LITTLE"; | |
1538 | case 0x19: | |
1539 | return "ASI_AS_IF_USER_SECONDARY_LITTLE"; | |
1540 | case 0x80: | |
1541 | return "ASI_PRIMARY"; | |
1542 | case 0x81: | |
1543 | return "ASI_SECONDARY"; | |
1544 | case 0x82: | |
1545 | return "ASI_PRIMARY_NOFAULT"; | |
1546 | case 0x83: | |
1547 | return "ASI_SECONDARY_NOFAULT"; | |
1548 | case 0x88: | |
1549 | return "ASI_PRIMARY_LITTLE"; | |
1550 | case 0x89: | |
1551 | return "ASI_SECONDARY_LITTLE"; | |
1552 | case 0x8a: | |
1553 | return "ASI_PRIMARY_NOFAULT_LITTLE"; | |
1554 | case 0x8b: | |
1555 | return "ASI_SECONDARY_NOFAULT_LITTLE"; | |
1556 | default: | |
1557 | return NULL; | |
c906108c SS |
1558 | } |
1559 | } | |
1560 | ||
1561 | /* PRINT_REGISTER_HOOK routine. | |
1562 | Pretty print various registers. */ | |
1563 | /* FIXME: Would be nice if this did some fancy things for 32 bit sparc. */ | |
1564 | ||
1565 | void | |
1566 | sparc_print_register_hook (regno) | |
1567 | int regno; | |
1568 | { | |
1569 | ULONGEST val; | |
1570 | ||
1571 | /* Handle double/quad versions of lower 32 fp regs. */ | |
1572 | if (regno >= FP0_REGNUM && regno < FP0_REGNUM + 32 | |
1573 | && (regno & 1) == 0) | |
1574 | { | |
1575 | char value[16]; | |
1576 | ||
1577 | if (!read_relative_register_raw_bytes (regno, value) | |
1578 | && !read_relative_register_raw_bytes (regno + 1, value + 4)) | |
1579 | { | |
1580 | printf_unfiltered ("\t"); | |
1581 | print_floating (value, builtin_type_double, gdb_stdout); | |
1582 | } | |
c5aa993b | 1583 | #if 0 /* FIXME: gdb doesn't handle long doubles */ |
c906108c SS |
1584 | if ((regno & 3) == 0) |
1585 | { | |
1586 | if (!read_relative_register_raw_bytes (regno + 2, value + 8) | |
1587 | && !read_relative_register_raw_bytes (regno + 3, value + 12)) | |
1588 | { | |
1589 | printf_unfiltered ("\t"); | |
1590 | print_floating (value, builtin_type_long_double, gdb_stdout); | |
1591 | } | |
1592 | } | |
1593 | #endif | |
1594 | return; | |
1595 | } | |
1596 | ||
c5aa993b | 1597 | #if 0 /* FIXME: gdb doesn't handle long doubles */ |
c906108c SS |
1598 | /* Print upper fp regs as long double if appropriate. */ |
1599 | if (regno >= FP0_REGNUM + 32 && regno < FP_MAX_REGNUM | |
c5aa993b JM |
1600 | /* We test for even numbered regs and not a multiple of 4 because |
1601 | the upper fp regs are recorded as doubles. */ | |
c906108c SS |
1602 | && (regno & 1) == 0) |
1603 | { | |
1604 | char value[16]; | |
1605 | ||
1606 | if (!read_relative_register_raw_bytes (regno, value) | |
1607 | && !read_relative_register_raw_bytes (regno + 1, value + 8)) | |
1608 | { | |
1609 | printf_unfiltered ("\t"); | |
1610 | print_floating (value, builtin_type_long_double, gdb_stdout); | |
1611 | } | |
1612 | return; | |
1613 | } | |
1614 | #endif | |
1615 | ||
1616 | /* FIXME: Some of these are priviledged registers. | |
1617 | Not sure how they should be handled. */ | |
1618 | ||
1619 | #define BITS(n, mask) ((int) (((val) >> (n)) & (mask))) | |
1620 | ||
1621 | val = read_register (regno); | |
1622 | ||
1623 | /* pages 40 - 60 */ | |
1624 | switch (regno) | |
1625 | { | |
1626 | #ifdef GDB_TARGET_IS_SPARC64 | |
c5aa993b JM |
1627 | case CCR_REGNUM: |
1628 | printf_unfiltered ("\t"); | |
c906108c | 1629 | dump_ccreg ("xcc", val >> 4); |
c5aa993b | 1630 | printf_unfiltered (", "); |
c906108c SS |
1631 | dump_ccreg ("icc", val & 15); |
1632 | break; | |
c5aa993b | 1633 | case FPRS_REGNUM: |
c906108c SS |
1634 | printf ("\tfef:%d, du:%d, dl:%d", |
1635 | BITS (2, 1), BITS (1, 1), BITS (0, 1)); | |
1636 | break; | |
c5aa993b | 1637 | case FSR_REGNUM: |
c906108c | 1638 | { |
c5aa993b JM |
1639 | static char *fcc[4] = |
1640 | {"=", "<", ">", "?"}; | |
1641 | static char *rd[4] = | |
1642 | {"N", "0", "+", "-"}; | |
c906108c SS |
1643 | /* Long, yes, but I'd rather leave it as is and use a wide screen. */ |
1644 | printf ("\t0:%s, 1:%s, 2:%s, 3:%s, rd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, aexc:%d, cexc:%d", | |
1645 | fcc[BITS (10, 3)], fcc[BITS (32, 3)], | |
1646 | fcc[BITS (34, 3)], fcc[BITS (36, 3)], | |
1647 | rd[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7), | |
1648 | BITS (14, 7), BITS (13, 1), BITS (5, 31), BITS (0, 31)); | |
1649 | break; | |
1650 | } | |
c5aa993b | 1651 | case ASI_REGNUM: |
c906108c SS |
1652 | { |
1653 | char *asi = decode_asi (val); | |
1654 | if (asi != NULL) | |
1655 | printf ("\t%s", asi); | |
1656 | break; | |
1657 | } | |
c5aa993b | 1658 | case VER_REGNUM: |
c906108c SS |
1659 | printf ("\tmanuf:%d, impl:%d, mask:%d, maxtl:%d, maxwin:%d", |
1660 | BITS (48, 0xffff), BITS (32, 0xffff), | |
1661 | BITS (24, 0xff), BITS (8, 0xff), BITS (0, 31)); | |
1662 | break; | |
c5aa993b | 1663 | case PSTATE_REGNUM: |
c906108c | 1664 | { |
c5aa993b JM |
1665 | static char *mm[4] = |
1666 | {"tso", "pso", "rso", "?"}; | |
c906108c SS |
1667 | printf ("\tcle:%d, tle:%d, mm:%s, red:%d, pef:%d, am:%d, priv:%d, ie:%d, ag:%d", |
1668 | BITS (9, 1), BITS (8, 1), mm[BITS (6, 3)], BITS (5, 1), | |
1669 | BITS (4, 1), BITS (3, 1), BITS (2, 1), BITS (1, 1), | |
1670 | BITS (0, 1)); | |
1671 | break; | |
1672 | } | |
c5aa993b | 1673 | case TSTATE_REGNUM: |
c906108c SS |
1674 | /* FIXME: print all 4? */ |
1675 | break; | |
c5aa993b | 1676 | case TT_REGNUM: |
c906108c SS |
1677 | /* FIXME: print all 4? */ |
1678 | break; | |
c5aa993b | 1679 | case TPC_REGNUM: |
c906108c SS |
1680 | /* FIXME: print all 4? */ |
1681 | break; | |
c5aa993b | 1682 | case TNPC_REGNUM: |
c906108c SS |
1683 | /* FIXME: print all 4? */ |
1684 | break; | |
c5aa993b | 1685 | case WSTATE_REGNUM: |
c906108c SS |
1686 | printf ("\tother:%d, normal:%d", BITS (3, 7), BITS (0, 7)); |
1687 | break; | |
c5aa993b | 1688 | case CWP_REGNUM: |
c906108c SS |
1689 | printf ("\t%d", BITS (0, 31)); |
1690 | break; | |
c5aa993b | 1691 | case CANSAVE_REGNUM: |
c906108c SS |
1692 | printf ("\t%-2d before spill", BITS (0, 31)); |
1693 | break; | |
c5aa993b | 1694 | case CANRESTORE_REGNUM: |
c906108c SS |
1695 | printf ("\t%-2d before fill", BITS (0, 31)); |
1696 | break; | |
c5aa993b | 1697 | case CLEANWIN_REGNUM: |
c906108c SS |
1698 | printf ("\t%-2d before clean", BITS (0, 31)); |
1699 | break; | |
c5aa993b | 1700 | case OTHERWIN_REGNUM: |
c906108c SS |
1701 | printf ("\t%d", BITS (0, 31)); |
1702 | break; | |
1703 | #else | |
1704 | case PS_REGNUM: | |
1705 | printf ("\ticc:%c%c%c%c, pil:%d, s:%d, ps:%d, et:%d, cwp:%d", | |
1706 | BITS (23, 1) ? 'N' : '-', BITS (22, 1) ? 'Z' : '-', | |
1707 | BITS (21, 1) ? 'V' : '-', BITS (20, 1) ? 'C' : '-', | |
1708 | BITS (8, 15), BITS (7, 1), BITS (6, 1), BITS (5, 1), | |
1709 | BITS (0, 31)); | |
1710 | break; | |
1711 | case FPS_REGNUM: | |
1712 | { | |
c5aa993b JM |
1713 | static char *fcc[4] = |
1714 | {"=", "<", ">", "?"}; | |
1715 | static char *rd[4] = | |
1716 | {"N", "0", "+", "-"}; | |
c906108c SS |
1717 | /* Long, yes, but I'd rather leave it as is and use a wide screen. */ |
1718 | printf ("\trd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, " | |
1719 | "fcc:%s, aexc:%d, cexc:%d", | |
1720 | rd[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7), | |
1721 | BITS (14, 7), BITS (13, 1), fcc[BITS (10, 3)], BITS (5, 31), | |
1722 | BITS (0, 31)); | |
1723 | break; | |
1724 | } | |
1725 | ||
c5aa993b | 1726 | #endif /* GDB_TARGET_IS_SPARC64 */ |
c906108c SS |
1727 | } |
1728 | ||
1729 | #undef BITS | |
1730 | } | |
1731 | \f | |
1732 | int | |
1733 | gdb_print_insn_sparc (memaddr, info) | |
1734 | bfd_vma memaddr; | |
1735 | disassemble_info *info; | |
1736 | { | |
1737 | /* It's necessary to override mach again because print_insn messes it up. */ | |
96baa820 | 1738 | info->mach = TARGET_ARCHITECTURE->mach; |
c906108c SS |
1739 | return print_insn_sparc (memaddr, info); |
1740 | } | |
1741 | \f | |
1742 | /* The SPARC passes the arguments on the stack; arguments smaller | |
1743 | than an int are promoted to an int. */ | |
1744 | ||
1745 | CORE_ADDR | |
1746 | sparc_push_arguments (nargs, args, sp, struct_return, struct_addr) | |
1747 | int nargs; | |
1748 | value_ptr *args; | |
1749 | CORE_ADDR sp; | |
1750 | int struct_return; | |
1751 | CORE_ADDR struct_addr; | |
1752 | { | |
1753 | int i; | |
1754 | int accumulate_size = 0; | |
1755 | struct sparc_arg | |
1756 | { | |
1757 | char *contents; | |
1758 | int len; | |
1759 | int offset; | |
1760 | }; | |
1761 | struct sparc_arg *sparc_args = | |
c5aa993b | 1762 | (struct sparc_arg *) alloca (nargs * sizeof (struct sparc_arg)); |
c906108c SS |
1763 | struct sparc_arg *m_arg; |
1764 | ||
1765 | /* Promote arguments if necessary, and calculate their stack offsets | |
1766 | and sizes. */ | |
1767 | for (i = 0, m_arg = sparc_args; i < nargs; i++, m_arg++) | |
1768 | { | |
1769 | value_ptr arg = args[i]; | |
1770 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
1771 | /* Cast argument to long if necessary as the compiler does it too. */ | |
1772 | switch (TYPE_CODE (arg_type)) | |
1773 | { | |
1774 | case TYPE_CODE_INT: | |
1775 | case TYPE_CODE_BOOL: | |
1776 | case TYPE_CODE_CHAR: | |
1777 | case TYPE_CODE_RANGE: | |
1778 | case TYPE_CODE_ENUM: | |
1779 | if (TYPE_LENGTH (arg_type) < TYPE_LENGTH (builtin_type_long)) | |
1780 | { | |
1781 | arg_type = builtin_type_long; | |
1782 | arg = value_cast (arg_type, arg); | |
1783 | } | |
1784 | break; | |
1785 | default: | |
1786 | break; | |
1787 | } | |
1788 | m_arg->len = TYPE_LENGTH (arg_type); | |
1789 | m_arg->offset = accumulate_size; | |
1790 | accumulate_size = (accumulate_size + m_arg->len + 3) & ~3; | |
c5aa993b | 1791 | m_arg->contents = VALUE_CONTENTS (arg); |
c906108c SS |
1792 | } |
1793 | ||
1794 | /* Make room for the arguments on the stack. */ | |
1795 | accumulate_size += CALL_DUMMY_STACK_ADJUST; | |
1796 | sp = ((sp - accumulate_size) & ~7) + CALL_DUMMY_STACK_ADJUST; | |
1797 | ||
1798 | /* `Push' arguments on the stack. */ | |
c5aa993b JM |
1799 | for (i = nargs; m_arg--, --i >= 0;) |
1800 | write_memory (sp + m_arg->offset, m_arg->contents, m_arg->len); | |
c906108c SS |
1801 | |
1802 | return sp; | |
1803 | } | |
1804 | ||
1805 | ||
1806 | /* Extract from an array REGBUF containing the (raw) register state | |
1807 | a function return value of type TYPE, and copy that, in virtual format, | |
1808 | into VALBUF. */ | |
1809 | ||
1810 | void | |
1811 | sparc_extract_return_value (type, regbuf, valbuf) | |
1812 | struct type *type; | |
1813 | char *regbuf; | |
1814 | char *valbuf; | |
1815 | { | |
1816 | int typelen = TYPE_LENGTH (type); | |
1817 | int regsize = REGISTER_RAW_SIZE (O0_REGNUM); | |
1818 | ||
1819 | if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU) | |
c5aa993b | 1820 | memcpy (valbuf, ®buf[REGISTER_BYTE (FP0_REGNUM)], typelen); |
c906108c SS |
1821 | else |
1822 | memcpy (valbuf, | |
c5aa993b JM |
1823 | ®buf[O0_REGNUM * regsize + |
1824 | (typelen >= regsize | |
1825 | || TARGET_BYTE_ORDER == LITTLE_ENDIAN ? 0 | |
1826 | : regsize - typelen)], | |
c906108c SS |
1827 | typelen); |
1828 | } | |
1829 | ||
1830 | ||
1831 | /* Write into appropriate registers a function return value | |
1832 | of type TYPE, given in virtual format. On SPARCs with FPUs, | |
1833 | float values are returned in %f0 (and %f1). In all other cases, | |
1834 | values are returned in register %o0. */ | |
1835 | ||
1836 | void | |
1837 | sparc_store_return_value (type, valbuf) | |
1838 | struct type *type; | |
1839 | char *valbuf; | |
1840 | { | |
1841 | int regno; | |
1842 | char buffer[MAX_REGISTER_RAW_SIZE]; | |
1843 | ||
1844 | if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU) | |
1845 | /* Floating-point values are returned in the register pair */ | |
1846 | /* formed by %f0 and %f1 (doubles are, anyway). */ | |
1847 | regno = FP0_REGNUM; | |
1848 | else | |
1849 | /* Other values are returned in register %o0. */ | |
1850 | regno = O0_REGNUM; | |
1851 | ||
1852 | /* Add leading zeros to the value. */ | |
c5aa993b | 1853 | if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (regno)) |
c906108c | 1854 | { |
c5aa993b JM |
1855 | bzero (buffer, REGISTER_RAW_SIZE (regno)); |
1856 | memcpy (buffer + REGISTER_RAW_SIZE (regno) - TYPE_LENGTH (type), valbuf, | |
c906108c | 1857 | TYPE_LENGTH (type)); |
c5aa993b JM |
1858 | write_register_bytes (REGISTER_BYTE (regno), buffer, |
1859 | REGISTER_RAW_SIZE (regno)); | |
c906108c SS |
1860 | } |
1861 | else | |
1862 | write_register_bytes (REGISTER_BYTE (regno), valbuf, TYPE_LENGTH (type)); | |
1863 | } | |
1864 | ||
1865 | ||
1866 | /* Insert the function address into a call dummy instruction sequence | |
1867 | stored at DUMMY. | |
1868 | ||
1869 | For structs and unions, if the function was compiled with Sun cc, | |
1870 | it expects 'unimp' after the call. But gcc doesn't use that | |
1871 | (twisted) convention. So leave a nop there for gcc (FIX_CALL_DUMMY | |
1872 | can assume it is operating on a pristine CALL_DUMMY, not one that | |
1873 | has already been customized for a different function). */ | |
1874 | ||
1875 | void | |
1876 | sparc_fix_call_dummy (dummy, pc, fun, value_type, using_gcc) | |
1877 | char *dummy; | |
1878 | CORE_ADDR pc; | |
1879 | CORE_ADDR fun; | |
1880 | struct type *value_type; | |
1881 | int using_gcc; | |
1882 | { | |
1883 | int i; | |
1884 | ||
1885 | /* Store the relative adddress of the target function into the | |
1886 | 'call' instruction. */ | |
1887 | store_unsigned_integer (dummy + CALL_DUMMY_CALL_OFFSET, 4, | |
1888 | (0x40000000 | |
1889 | | (((fun - (pc + CALL_DUMMY_CALL_OFFSET)) >> 2) | |
c5aa993b | 1890 | & 0x3fffffff))); |
c906108c SS |
1891 | |
1892 | /* Comply with strange Sun cc calling convention for struct-returning | |
1893 | functions. */ | |
1894 | if (!using_gcc | |
1895 | && (TYPE_CODE (value_type) == TYPE_CODE_STRUCT | |
1896 | || TYPE_CODE (value_type) == TYPE_CODE_UNION)) | |
1897 | store_unsigned_integer (dummy + CALL_DUMMY_CALL_OFFSET + 8, 4, | |
1898 | TYPE_LENGTH (value_type) & 0x1fff); | |
1899 | ||
1900 | #ifndef GDB_TARGET_IS_SPARC64 | |
1901 | /* If this is not a simulator target, change the first four instructions | |
1902 | of the call dummy to NOPs. Those instructions include a 'save' | |
1903 | instruction and are designed to work around problems with register | |
1904 | window flushing in the simulator. */ | |
1905 | if (strcmp (target_shortname, "sim") != 0) | |
1906 | { | |
1907 | for (i = 0; i < 4; i++) | |
1908 | store_unsigned_integer (dummy + (i * 4), 4, 0x01000000); | |
1909 | } | |
1910 | #endif | |
1911 | ||
1912 | /* If this is a bi-endian target, GDB has written the call dummy | |
1913 | in little-endian order. We must byte-swap it back to big-endian. */ | |
1914 | if (bi_endian) | |
1915 | { | |
1916 | for (i = 0; i < CALL_DUMMY_LENGTH; i += 4) | |
1917 | { | |
c5aa993b JM |
1918 | char tmp = dummy[i]; |
1919 | dummy[i] = dummy[i + 3]; | |
1920 | dummy[i + 3] = tmp; | |
1921 | tmp = dummy[i + 1]; | |
1922 | dummy[i + 1] = dummy[i + 2]; | |
1923 | dummy[i + 2] = tmp; | |
c906108c SS |
1924 | } |
1925 | } | |
1926 | } | |
1927 | ||
1928 | ||
1929 | /* Set target byte order based on machine type. */ | |
1930 | ||
1931 | static int | |
1932 | sparc_target_architecture_hook (ap) | |
1933 | const bfd_arch_info_type *ap; | |
1934 | { | |
1935 | int i, j; | |
1936 | ||
1937 | if (ap->mach == bfd_mach_sparc_sparclite_le) | |
1938 | { | |
1939 | if (TARGET_BYTE_ORDER_SELECTABLE_P) | |
1940 | { | |
1941 | target_byte_order = LITTLE_ENDIAN; | |
1942 | bi_endian = 1; | |
1943 | } | |
1944 | else | |
1945 | { | |
1946 | warning ("This GDB does not support little endian sparclite."); | |
1947 | } | |
1948 | } | |
1949 | else | |
1950 | bi_endian = 0; | |
1951 | return 1; | |
1952 | } | |
c906108c | 1953 | \f |
c5aa993b | 1954 | |
c906108c SS |
1955 | void |
1956 | _initialize_sparc_tdep () | |
1957 | { | |
1958 | tm_print_insn = gdb_print_insn_sparc; | |
c5aa993b | 1959 | tm_print_insn_info.mach = TM_PRINT_INSN_MACH; /* Selects sparc/sparclite */ |
c906108c SS |
1960 | target_architecture_hook = sparc_target_architecture_hook; |
1961 | } | |
1962 | ||
1963 | ||
1964 | #ifdef GDB_TARGET_IS_SPARC64 | |
1965 | ||
1966 | /* Compensate for stack bias. Note that we currently don't handle mixed | |
1967 | 32/64 bit code. */ | |
1968 | CORE_ADDR | |
1969 | sparc64_read_sp () | |
1970 | { | |
1971 | CORE_ADDR sp = read_register (SP_REGNUM); | |
1972 | ||
1973 | if (sp & 1) | |
1974 | sp += 2047; | |
1975 | return sp; | |
1976 | } | |
1977 | ||
1978 | CORE_ADDR | |
1979 | sparc64_read_fp () | |
1980 | { | |
1981 | CORE_ADDR fp = read_register (FP_REGNUM); | |
1982 | ||
1983 | if (fp & 1) | |
1984 | fp += 2047; | |
1985 | return fp; | |
1986 | } | |
1987 | ||
1988 | void | |
1989 | sparc64_write_sp (val) | |
1990 | CORE_ADDR val; | |
1991 | { | |
1992 | CORE_ADDR oldsp = read_register (SP_REGNUM); | |
1993 | if (oldsp & 1) | |
1994 | write_register (SP_REGNUM, val - 2047); | |
1995 | else | |
1996 | write_register (SP_REGNUM, val); | |
1997 | } | |
1998 | ||
1999 | void | |
2000 | sparc64_write_fp (val) | |
2001 | CORE_ADDR val; | |
2002 | { | |
2003 | CORE_ADDR oldfp = read_register (FP_REGNUM); | |
2004 | if (oldfp & 1) | |
2005 | write_register (FP_REGNUM, val - 2047); | |
2006 | else | |
2007 | write_register (FP_REGNUM, val); | |
2008 | } | |
2009 | ||
2010 | /* The SPARC 64 ABI passes floating-point arguments in FP0-31. They are | |
2011 | also copied onto the stack in the correct places. */ | |
2012 | ||
2013 | CORE_ADDR | |
2014 | sp64_push_arguments (nargs, args, sp, struct_return, struct_retaddr) | |
2015 | int nargs; | |
2016 | value_ptr *args; | |
2017 | CORE_ADDR sp; | |
2018 | unsigned char struct_return; | |
2019 | CORE_ADDR struct_retaddr; | |
2020 | { | |
2021 | int x; | |
2022 | int regnum = 0; | |
2023 | CORE_ADDR tempsp; | |
c5aa993b JM |
2024 | |
2025 | sp = (sp & ~(((unsigned long) TYPE_LENGTH (builtin_type_long)) - 1UL)); | |
c906108c SS |
2026 | |
2027 | /* Figure out how much space we'll need. */ | |
2028 | for (x = nargs - 1; x >= 0; x--) | |
2029 | { | |
2030 | int len = TYPE_LENGTH (check_typedef (VALUE_TYPE (args[x]))); | |
2031 | value_ptr copyarg = args[x]; | |
2032 | int copylen = len; | |
2033 | ||
2034 | /* This code is, of course, no longer correct. */ | |
2035 | if (copylen < TYPE_LENGTH (builtin_type_long)) | |
2036 | { | |
c5aa993b JM |
2037 | copyarg = value_cast (builtin_type_long, copyarg); |
2038 | copylen = TYPE_LENGTH (builtin_type_long); | |
2039 | } | |
c906108c SS |
2040 | sp -= copylen; |
2041 | } | |
2042 | ||
2043 | /* Round down. */ | |
2044 | sp = sp & ~7; | |
2045 | tempsp = sp; | |
2046 | ||
2047 | /* Now write the arguments onto the stack, while writing FP arguments | |
2048 | into the FP registers. */ | |
2049 | for (x = 0; x < nargs; x++) | |
2050 | { | |
2051 | int len = TYPE_LENGTH (check_typedef (VALUE_TYPE (args[x]))); | |
2052 | value_ptr copyarg = args[x]; | |
2053 | int copylen = len; | |
2054 | ||
2055 | /* This code is, of course, no longer correct. */ | |
2056 | if (copylen < TYPE_LENGTH (builtin_type_long)) | |
2057 | { | |
c5aa993b JM |
2058 | copyarg = value_cast (builtin_type_long, copyarg); |
2059 | copylen = TYPE_LENGTH (builtin_type_long); | |
2060 | } | |
c906108c SS |
2061 | write_memory (tempsp, VALUE_CONTENTS (copyarg), copylen); |
2062 | tempsp += copylen; | |
2063 | if (TYPE_CODE (VALUE_TYPE (args[x])) == TYPE_CODE_FLT && regnum < 32) | |
2064 | { | |
2065 | /* This gets copied into a FP register. */ | |
2066 | int nextreg = regnum + 2; | |
2067 | char *data = VALUE_CONTENTS (args[x]); | |
2068 | /* Floats go into the lower half of a FP register pair; quads | |
2069 | use 2 pairs. */ | |
2070 | ||
2071 | if (len == 16) | |
2072 | nextreg += 2; | |
2073 | else if (len == 4) | |
2074 | regnum++; | |
2075 | ||
2076 | write_register_bytes (REGISTER_BYTE (FP0_REGNUM + regnum), | |
2077 | data, | |
2078 | len); | |
2079 | regnum = nextreg; | |
2080 | } | |
2081 | } | |
2082 | return sp; | |
2083 | } | |
2084 | ||
2085 | /* Values <= 32 bytes are returned in o0-o3 (floating-point values are | |
2086 | returned in f0-f3). */ | |
2087 | void | |
2088 | sparc64_extract_return_value (type, regbuf, valbuf, bitoffset) | |
2089 | struct type *type; | |
2090 | char *regbuf; | |
2091 | char *valbuf; | |
2092 | int bitoffset; | |
2093 | { | |
2094 | int typelen = TYPE_LENGTH (type); | |
2095 | int regsize = REGISTER_RAW_SIZE (O0_REGNUM); | |
2096 | ||
2097 | if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU) | |
2098 | { | |
c5aa993b | 2099 | memcpy (valbuf, ®buf[REGISTER_BYTE (FP0_REGNUM)], typelen); |
c906108c SS |
2100 | return; |
2101 | } | |
2102 | ||
2103 | if (TYPE_CODE (type) != TYPE_CODE_STRUCT | |
2104 | || (TYPE_LENGTH (type) > 32)) | |
2105 | { | |
2106 | memcpy (valbuf, | |
c5aa993b | 2107 | ®buf[O0_REGNUM * regsize + |
c906108c SS |
2108 | (typelen >= regsize ? 0 : regsize - typelen)], |
2109 | typelen); | |
2110 | return; | |
2111 | } | |
2112 | else | |
2113 | { | |
2114 | char *o0 = ®buf[O0_REGNUM * regsize]; | |
2115 | char *f0 = ®buf[FP0_REGNUM * regsize]; | |
2116 | int x; | |
2117 | ||
2118 | for (x = 0; x < TYPE_NFIELDS (type); x++) | |
2119 | { | |
c5aa993b | 2120 | struct field *f = &TYPE_FIELDS (type)[x]; |
c906108c SS |
2121 | /* FIXME: We may need to handle static fields here. */ |
2122 | int whichreg = (f->loc.bitpos + bitoffset) / 32; | |
2123 | int remainder = ((f->loc.bitpos + bitoffset) % 32) / 8; | |
2124 | int where = (f->loc.bitpos + bitoffset) / 8; | |
2125 | int size = TYPE_LENGTH (f->type); | |
2126 | int typecode = TYPE_CODE (f->type); | |
2127 | ||
2128 | if (typecode == TYPE_CODE_STRUCT) | |
2129 | { | |
2130 | sparc64_extract_return_value (f->type, | |
2131 | regbuf, | |
2132 | valbuf, | |
2133 | bitoffset + f->loc.bitpos); | |
2134 | } | |
2135 | else if (typecode == TYPE_CODE_FLT) | |
2136 | { | |
2137 | memcpy (valbuf + where, &f0[whichreg * 4] + remainder, size); | |
2138 | } | |
2139 | else | |
2140 | { | |
2141 | memcpy (valbuf + where, &o0[whichreg * 4] + remainder, size); | |
2142 | } | |
2143 | } | |
2144 | } | |
2145 | } | |
2acceee2 JM |
2146 | |
2147 | ||
c906108c | 2148 | #endif |