Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the SPARC for GDB, the GNU debugger. |
cda5a58a AC |
2 | |
3 | Copyright 1986, 1987, 1989, 1990, 1991, 1992, 1993, 1994, 1995, | |
1e698235 | 4 | 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, |
cda5a58a | 5 | Inc. |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b JM |
19 | You should have received a copy of the GNU General Public License |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 59 Temple Place - Suite 330, | |
22 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
23 | |
24 | /* ??? Support for calling functions from gdb in sparc64 is unfinished. */ | |
25 | ||
26 | #include "defs.h" | |
5af923b0 | 27 | #include "arch-utils.h" |
c906108c SS |
28 | #include "frame.h" |
29 | #include "inferior.h" | |
c906108c SS |
30 | #include "target.h" |
31 | #include "value.h" | |
32 | #include "bfd.h" | |
33 | #include "gdb_string.h" | |
4e052eda | 34 | #include "regcache.h" |
ef3cf062 | 35 | #include "osabi.h" |
c906108c | 36 | |
c139e7d9 DJ |
37 | #include "sparc-tdep.h" |
38 | ||
c906108c SS |
39 | #ifdef USE_PROC_FS |
40 | #include <sys/procfs.h> | |
13437d4b KB |
41 | /* Prototypes for supply_gregset etc. */ |
42 | #include "gregset.h" | |
c906108c SS |
43 | #endif |
44 | ||
45 | #include "gdbcore.h" | |
43bd9a9e | 46 | #include "gdb_assert.h" |
c906108c | 47 | |
5af923b0 MS |
48 | #include "symfile.h" /* for 'entry_point_address' */ |
49 | ||
4eb8c7fc DM |
50 | /* |
51 | * Some local macros that have multi-arch and non-multi-arch versions: | |
52 | */ | |
53 | ||
54 | #if (GDB_MULTI_ARCH > 0) | |
55 | ||
07020390 AC |
56 | #if 0 |
57 | // OBSOLETE /* Does the target have Floating Point registers? */ | |
58 | // OBSOLETE #define SPARC_HAS_FPU (gdbarch_tdep (current_gdbarch)->has_fpu) | |
59 | #endif | |
60 | #define SPARC_HAS_FPU 1 | |
4eb8c7fc DM |
61 | /* Number of bytes devoted to Floating Point registers: */ |
62 | #define FP_REGISTER_BYTES (gdbarch_tdep (current_gdbarch)->fp_register_bytes) | |
63 | /* Highest numbered Floating Point register. */ | |
64 | #define FP_MAX_REGNUM (gdbarch_tdep (current_gdbarch)->fp_max_regnum) | |
65 | /* Size of a general (integer) register: */ | |
66 | #define SPARC_INTREG_SIZE (gdbarch_tdep (current_gdbarch)->intreg_size) | |
67 | /* Offset within the call dummy stack of the saved registers. */ | |
68 | #define DUMMY_REG_SAVE_OFFSET (gdbarch_tdep (current_gdbarch)->reg_save_offset) | |
69 | ||
70 | #else /* non-multi-arch */ | |
71 | ||
72 | ||
73 | /* Does the target have Floating Point registers? */ | |
f81824a9 AC |
74 | #if 0 |
75 | // OBSOLETE #if defined(TARGET_SPARCLET) || defined(TARGET_SPARCLITE) | |
76 | // OBSOLETE #define SPARC_HAS_FPU 0 | |
77 | // OBSOLETE #else | |
78 | // OBSOLETE #define SPARC_HAS_FPU 1 | |
79 | // OBSOLETE #endif | |
4eb8c7fc | 80 | #endif |
f81824a9 | 81 | #define SPARC_HAS_FPU 1 |
4eb8c7fc DM |
82 | |
83 | /* Number of bytes devoted to Floating Point registers: */ | |
84 | #if (GDB_TARGET_IS_SPARC64) | |
85 | #define FP_REGISTER_BYTES (64 * 4) | |
86 | #else | |
87 | #if (SPARC_HAS_FPU) | |
88 | #define FP_REGISTER_BYTES (32 * 4) | |
89 | #else | |
90 | #define FP_REGISTER_BYTES 0 | |
91 | #endif | |
92 | #endif | |
93 | ||
94 | /* Highest numbered Floating Point register. */ | |
95 | #if (GDB_TARGET_IS_SPARC64) | |
96 | #define FP_MAX_REGNUM (FP0_REGNUM + 48) | |
97 | #else | |
98 | #define FP_MAX_REGNUM (FP0_REGNUM + 32) | |
99 | #endif | |
100 | ||
101 | /* Size of a general (integer) register: */ | |
102 | #define SPARC_INTREG_SIZE (REGISTER_RAW_SIZE (G0_REGNUM)) | |
103 | ||
104 | /* Offset within the call dummy stack of the saved registers. */ | |
105 | #if (GDB_TARGET_IS_SPARC64) | |
106 | #define DUMMY_REG_SAVE_OFFSET (128 + 16) | |
107 | #else | |
108 | #define DUMMY_REG_SAVE_OFFSET 0x60 | |
109 | #endif | |
110 | ||
111 | #endif /* GDB_MULTI_ARCH */ | |
112 | ||
113 | struct gdbarch_tdep | |
114 | { | |
f81824a9 AC |
115 | #if 0 |
116 | // OBSOLETE int has_fpu; | |
117 | #endif | |
4eb8c7fc DM |
118 | int fp_register_bytes; |
119 | int y_regnum; | |
120 | int fp_max_regnum; | |
121 | int intreg_size; | |
122 | int reg_save_offset; | |
123 | int call_dummy_call_offset; | |
124 | int print_insn_mach; | |
125 | }; | |
5af923b0 MS |
126 | |
127 | /* Now make GDB_TARGET_IS_SPARC64 a runtime test. */ | |
128 | /* FIXME MVS: or try testing bfd_arch_info.arch and bfd_arch_info.mach ... | |
129 | * define GDB_TARGET_IS_SPARC64 \ | |
130 | * (TARGET_ARCHITECTURE->arch == bfd_arch_sparc && \ | |
131 | * (TARGET_ARCHITECTURE->mach == bfd_mach_sparc_v9 || \ | |
132 | * TARGET_ARCHITECTURE->mach == bfd_mach_sparc_v9a)) | |
133 | */ | |
134 | ||
c906108c SS |
135 | /* We don't store all registers immediately when requested, since they |
136 | get sent over in large chunks anyway. Instead, we accumulate most | |
137 | of the changes and send them over once. "deferred_stores" keeps | |
138 | track of which sets of registers we have locally-changed copies of, | |
139 | so we only need send the groups that have changed. */ | |
140 | ||
5af923b0 | 141 | int deferred_stores = 0; /* Accumulated stores we want to do eventually. */ |
c906108c SS |
142 | |
143 | ||
f81824a9 AC |
144 | #if 0 |
145 | // OBSOLETE /* Some machines, such as Fujitsu SPARClite 86x, have a bi-endian mode | |
146 | // OBSOLETE where instructions are big-endian and data are little-endian. | |
147 | // OBSOLETE This flag is set when we detect that the target is of this type. */ | |
148 | // OBSOLETE | |
149 | // OBSOLETE int bi_endian = 0; | |
150 | #endif | |
c906108c SS |
151 | |
152 | ||
aaab4dba AC |
153 | const unsigned char * |
154 | sparc_breakpoint_from_pc (CORE_ADDR *pc, int *len) | |
155 | { | |
156 | static const char breakpoint[] = {0x91, 0xd0, 0x20, 0x01}; | |
157 | (*len) = sizeof (breakpoint); | |
158 | return breakpoint; | |
159 | } | |
160 | ||
c906108c SS |
161 | /* Fetch a single instruction. Even on bi-endian machines |
162 | such as sparc86x, instructions are always big-endian. */ | |
163 | ||
164 | static unsigned long | |
fba45db2 | 165 | fetch_instruction (CORE_ADDR pc) |
c906108c SS |
166 | { |
167 | unsigned long retval; | |
168 | int i; | |
169 | unsigned char buf[4]; | |
170 | ||
171 | read_memory (pc, buf, sizeof (buf)); | |
172 | ||
173 | /* Start at the most significant end of the integer, and work towards | |
174 | the least significant. */ | |
175 | retval = 0; | |
176 | for (i = 0; i < sizeof (buf); ++i) | |
177 | retval = (retval << 8) | buf[i]; | |
178 | return retval; | |
179 | } | |
180 | ||
181 | ||
182 | /* Branches with prediction are treated like their non-predicting cousins. */ | |
183 | /* FIXME: What about floating point branches? */ | |
184 | ||
185 | /* Macros to extract fields from sparc instructions. */ | |
186 | #define X_OP(i) (((i) >> 30) & 0x3) | |
187 | #define X_RD(i) (((i) >> 25) & 0x1f) | |
188 | #define X_A(i) (((i) >> 29) & 1) | |
189 | #define X_COND(i) (((i) >> 25) & 0xf) | |
190 | #define X_OP2(i) (((i) >> 22) & 0x7) | |
191 | #define X_IMM22(i) ((i) & 0x3fffff) | |
192 | #define X_OP3(i) (((i) >> 19) & 0x3f) | |
193 | #define X_RS1(i) (((i) >> 14) & 0x1f) | |
194 | #define X_I(i) (((i) >> 13) & 1) | |
195 | #define X_IMM13(i) ((i) & 0x1fff) | |
196 | /* Sign extension macros. */ | |
197 | #define X_SIMM13(i) ((X_IMM13 (i) ^ 0x1000) - 0x1000) | |
198 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) | |
199 | #define X_CC(i) (((i) >> 20) & 3) | |
200 | #define X_P(i) (((i) >> 19) & 1) | |
201 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) | |
202 | #define X_RCOND(i) (((i) >> 25) & 7) | |
203 | #define X_DISP16(i) ((((((i) >> 6) && 0xc000) | ((i) & 0x3fff)) ^ 0x8000) - 0x8000) | |
204 | #define X_FCN(i) (((i) >> 25) & 31) | |
205 | ||
206 | typedef enum | |
207 | { | |
5af923b0 MS |
208 | Error, not_branch, bicc, bicca, ba, baa, ticc, ta, done_retry |
209 | } branch_type; | |
c906108c SS |
210 | |
211 | /* Simulate single-step ptrace call for sun4. Code written by Gary | |
212 | Beihl (beihl@mcc.com). */ | |
213 | ||
214 | /* npc4 and next_pc describe the situation at the time that the | |
215 | step-breakpoint was set, not necessary the current value of NPC_REGNUM. */ | |
216 | static CORE_ADDR next_pc, npc4, target; | |
217 | static int brknpc4, brktrg; | |
218 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
219 | static binsn_quantum break_mem[3]; | |
220 | ||
5af923b0 | 221 | static branch_type isbranch (long, CORE_ADDR, CORE_ADDR *); |
c906108c SS |
222 | |
223 | /* single_step() is called just before we want to resume the inferior, | |
224 | if we want to single-step it but there is no hardware or kernel single-step | |
225 | support (as on all SPARCs). We find all the possible targets of the | |
226 | coming instruction and breakpoint them. | |
227 | ||
228 | single_step is also called just after the inferior stops. If we had | |
229 | set up a simulated single-step, we undo our damage. */ | |
230 | ||
231 | void | |
fba45db2 KB |
232 | sparc_software_single_step (enum target_signal ignore, /* pid, but we don't need it */ |
233 | int insert_breakpoints_p) | |
c906108c SS |
234 | { |
235 | branch_type br; | |
236 | CORE_ADDR pc; | |
237 | long pc_instruction; | |
238 | ||
239 | if (insert_breakpoints_p) | |
240 | { | |
241 | /* Always set breakpoint for NPC. */ | |
242 | next_pc = read_register (NPC_REGNUM); | |
c5aa993b | 243 | npc4 = next_pc + 4; /* branch not taken */ |
c906108c SS |
244 | |
245 | target_insert_breakpoint (next_pc, break_mem[0]); | |
246 | /* printf_unfiltered ("set break at %x\n",next_pc); */ | |
247 | ||
248 | pc = read_register (PC_REGNUM); | |
249 | pc_instruction = fetch_instruction (pc); | |
250 | br = isbranch (pc_instruction, pc, &target); | |
251 | brknpc4 = brktrg = 0; | |
252 | ||
253 | if (br == bicca) | |
254 | { | |
255 | /* Conditional annulled branch will either end up at | |
256 | npc (if taken) or at npc+4 (if not taken). | |
257 | Trap npc+4. */ | |
258 | brknpc4 = 1; | |
259 | target_insert_breakpoint (npc4, break_mem[1]); | |
260 | } | |
261 | else if (br == baa && target != next_pc) | |
262 | { | |
263 | /* Unconditional annulled branch will always end up at | |
264 | the target. */ | |
265 | brktrg = 1; | |
266 | target_insert_breakpoint (target, break_mem[2]); | |
267 | } | |
5af923b0 | 268 | else if (GDB_TARGET_IS_SPARC64 && br == done_retry) |
c906108c SS |
269 | { |
270 | brktrg = 1; | |
271 | target_insert_breakpoint (target, break_mem[2]); | |
272 | } | |
c906108c SS |
273 | } |
274 | else | |
275 | { | |
276 | /* Remove breakpoints */ | |
277 | target_remove_breakpoint (next_pc, break_mem[0]); | |
278 | ||
279 | if (brknpc4) | |
280 | target_remove_breakpoint (npc4, break_mem[1]); | |
281 | ||
282 | if (brktrg) | |
283 | target_remove_breakpoint (target, break_mem[2]); | |
284 | } | |
285 | } | |
286 | \f | |
5af923b0 MS |
287 | struct frame_extra_info |
288 | { | |
289 | CORE_ADDR bottom; | |
290 | int in_prologue; | |
291 | int flat; | |
292 | /* Following fields only relevant for flat frames. */ | |
293 | CORE_ADDR pc_addr; | |
294 | CORE_ADDR fp_addr; | |
295 | /* Add this to ->frame to get the value of the stack pointer at the | |
296 | time of the register saves. */ | |
297 | int sp_offset; | |
298 | }; | |
299 | ||
300 | /* Call this for each newly created frame. For SPARC, we need to | |
301 | calculate the bottom of the frame, and do some extra work if the | |
302 | prologue has been generated via the -mflat option to GCC. In | |
303 | particular, we need to know where the previous fp and the pc have | |
304 | been stashed, since their exact position within the frame may vary. */ | |
c906108c SS |
305 | |
306 | void | |
fba45db2 | 307 | sparc_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c SS |
308 | { |
309 | char *name; | |
310 | CORE_ADDR prologue_start, prologue_end; | |
311 | int insn; | |
312 | ||
a00a19e9 | 313 | frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info)); |
5af923b0 MS |
314 | frame_saved_regs_zalloc (fi); |
315 | ||
da50a4b7 | 316 | get_frame_extra_info (fi)->bottom = |
11c02a10 AC |
317 | (get_next_frame (fi) |
318 | ? (get_frame_base (fi) == get_frame_base (get_next_frame (fi)) | |
da50a4b7 | 319 | ? get_frame_extra_info (get_next_frame (fi))->bottom |
11c02a10 AC |
320 | : get_frame_base (get_next_frame (fi))) |
321 | : read_sp ()); | |
c906108c | 322 | |
0ba6dca9 AC |
323 | /* If fi->next is NULL, then we already set ->frame by passing |
324 | deprecated_read_fp() to create_new_frame. */ | |
11c02a10 | 325 | if (get_next_frame (fi)) |
c906108c | 326 | { |
d9d9c31f | 327 | char buf[MAX_REGISTER_SIZE]; |
c906108c SS |
328 | |
329 | /* Compute ->frame as if not flat. If it is flat, we'll change | |
c5aa993b | 330 | it later. */ |
11c02a10 AC |
331 | if (get_next_frame (get_next_frame (fi)) != NULL |
332 | && ((get_frame_type (get_next_frame (get_next_frame (fi))) == SIGTRAMP_FRAME) | |
333 | || deprecated_frame_in_dummy (get_next_frame (get_next_frame (fi)))) | |
334 | && frameless_look_for_prologue (get_next_frame (fi))) | |
c906108c SS |
335 | { |
336 | /* A frameless function interrupted by a signal did not change | |
337 | the frame pointer, fix up frame pointer accordingly. */ | |
11c02a10 | 338 | deprecated_update_frame_base_hack (fi, get_frame_base (get_next_frame (fi))); |
da50a4b7 AC |
339 | get_frame_extra_info (fi)->bottom = |
340 | get_frame_extra_info (get_next_frame (fi))->bottom; | |
c906108c SS |
341 | } |
342 | else | |
343 | { | |
344 | /* Should we adjust for stack bias here? */ | |
ac2adee5 | 345 | ULONGEST tmp; |
0ba6dca9 | 346 | frame_read_unsigned_register (fi, DEPRECATED_FP_REGNUM, &tmp); |
ac2adee5 | 347 | deprecated_update_frame_base_hack (fi, tmp); |
1e2330ba AC |
348 | if (GDB_TARGET_IS_SPARC64 && (get_frame_base (fi) & 1)) |
349 | deprecated_update_frame_base_hack (fi, get_frame_base (fi) + 2047); | |
c906108c SS |
350 | } |
351 | } | |
352 | ||
353 | /* Decide whether this is a function with a ``flat register window'' | |
354 | frame. For such functions, the frame pointer is actually in %i7. */ | |
da50a4b7 AC |
355 | get_frame_extra_info (fi)->flat = 0; |
356 | get_frame_extra_info (fi)->in_prologue = 0; | |
50abf9e5 | 357 | if (find_pc_partial_function (get_frame_pc (fi), &name, &prologue_start, &prologue_end)) |
c906108c SS |
358 | { |
359 | /* See if the function starts with an add (which will be of a | |
c5aa993b JM |
360 | negative number if a flat frame) to the sp. FIXME: Does not |
361 | handle large frames which will need more than one instruction | |
362 | to adjust the sp. */ | |
d0901120 | 363 | insn = fetch_instruction (prologue_start); |
c906108c SS |
364 | if (X_OP (insn) == 2 && X_RD (insn) == 14 && X_OP3 (insn) == 0 |
365 | && X_I (insn) && X_SIMM13 (insn) < 0) | |
366 | { | |
367 | int offset = X_SIMM13 (insn); | |
368 | ||
369 | /* Then look for a save of %i7 into the frame. */ | |
370 | insn = fetch_instruction (prologue_start + 4); | |
371 | if (X_OP (insn) == 3 | |
372 | && X_RD (insn) == 31 | |
373 | && X_OP3 (insn) == 4 | |
374 | && X_RS1 (insn) == 14) | |
375 | { | |
d9d9c31f | 376 | char buf[MAX_REGISTER_SIZE]; |
c906108c SS |
377 | |
378 | /* We definitely have a flat frame now. */ | |
da50a4b7 | 379 | get_frame_extra_info (fi)->flat = 1; |
c906108c | 380 | |
da50a4b7 | 381 | get_frame_extra_info (fi)->sp_offset = offset; |
c906108c SS |
382 | |
383 | /* Overwrite the frame's address with the value in %i7. */ | |
ac2adee5 AC |
384 | { |
385 | ULONGEST tmp; | |
386 | frame_read_unsigned_register (fi, I7_REGNUM, &tmp); | |
387 | deprecated_update_frame_base_hack (fi, tmp); | |
388 | } | |
5af923b0 | 389 | |
1e2330ba AC |
390 | if (GDB_TARGET_IS_SPARC64 && (get_frame_base (fi) & 1)) |
391 | deprecated_update_frame_base_hack (fi, get_frame_base (fi) + 2047); | |
5af923b0 | 392 | |
c906108c | 393 | /* Record where the fp got saved. */ |
da50a4b7 AC |
394 | get_frame_extra_info (fi)->fp_addr = |
395 | get_frame_base (fi) + get_frame_extra_info (fi)->sp_offset + X_SIMM13 (insn); | |
c906108c SS |
396 | |
397 | /* Also try to collect where the pc got saved to. */ | |
da50a4b7 | 398 | get_frame_extra_info (fi)->pc_addr = 0; |
c906108c SS |
399 | insn = fetch_instruction (prologue_start + 12); |
400 | if (X_OP (insn) == 3 | |
401 | && X_RD (insn) == 15 | |
402 | && X_OP3 (insn) == 4 | |
403 | && X_RS1 (insn) == 14) | |
da50a4b7 AC |
404 | get_frame_extra_info (fi)->pc_addr = |
405 | get_frame_base (fi) + get_frame_extra_info (fi)->sp_offset + X_SIMM13 (insn); | |
c906108c SS |
406 | } |
407 | } | |
c5aa993b JM |
408 | else |
409 | { | |
410 | /* Check if the PC is in the function prologue before a SAVE | |
411 | instruction has been executed yet. If so, set the frame | |
412 | to the current value of the stack pointer and set | |
413 | the in_prologue flag. */ | |
414 | CORE_ADDR addr; | |
415 | struct symtab_and_line sal; | |
416 | ||
417 | sal = find_pc_line (prologue_start, 0); | |
418 | if (sal.line == 0) /* no line info, use PC */ | |
50abf9e5 | 419 | prologue_end = get_frame_pc (fi); |
c5aa993b JM |
420 | else if (sal.end < prologue_end) |
421 | prologue_end = sal.end; | |
50abf9e5 | 422 | if (get_frame_pc (fi) < prologue_end) |
c5aa993b | 423 | { |
50abf9e5 | 424 | for (addr = prologue_start; addr < get_frame_pc (fi); addr += 4) |
c5aa993b JM |
425 | { |
426 | insn = read_memory_integer (addr, 4); | |
427 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) | |
428 | break; /* SAVE seen, stop searching */ | |
429 | } | |
50abf9e5 | 430 | if (addr >= get_frame_pc (fi)) |
c5aa993b | 431 | { |
da50a4b7 | 432 | get_frame_extra_info (fi)->in_prologue = 1; |
8ccd593b | 433 | deprecated_update_frame_base_hack (fi, read_register (SP_REGNUM)); |
c5aa993b JM |
434 | } |
435 | } | |
436 | } | |
c906108c | 437 | } |
11c02a10 | 438 | if (get_next_frame (fi) && get_frame_base (fi) == 0) |
c906108c SS |
439 | { |
440 | /* Kludge to cause init_prev_frame_info to destroy the new frame. */ | |
11c02a10 AC |
441 | deprecated_update_frame_base_hack (fi, get_frame_base (get_next_frame (fi))); |
442 | deprecated_update_frame_pc_hack (fi, get_frame_pc (get_next_frame (fi))); | |
c906108c SS |
443 | } |
444 | } | |
445 | ||
446 | CORE_ADDR | |
fba45db2 | 447 | sparc_frame_chain (struct frame_info *frame) |
c906108c | 448 | { |
618ce49f AC |
449 | /* Value that will cause DEPRECATED_FRAME_CHAIN_VALID to not worry |
450 | about the chain value. If it really is zero, we detect it later | |
451 | in sparc_init_prev_frame. | |
881324eb | 452 | |
e6ba3bc9 AC |
453 | Note: kevinb/2003-02-18: The constant 1 used to be returned here, |
454 | but, after some recent changes to legacy_frame_chain_valid(), | |
455 | this value is no longer suitable for causing | |
456 | legacy_frame_chain_valid() to "not worry about the chain value." | |
457 | The constant ~0 (i.e, 0xfff...) causes the failing test in | |
458 | legacy_frame_chain_valid() to succeed thus preserving the "not | |
459 | worry" property. I had considered using something like | |
460 | ``get_frame_base (frame) + 1''. However, I think a constant | |
461 | value is better, because when debugging this problem, I knew that | |
462 | something funny was going on as soon as I saw the constant 1 | |
463 | being used as the frame chain elsewhere in GDB. */ | |
881324eb KB |
464 | |
465 | return ~ (CORE_ADDR) 0; | |
c906108c SS |
466 | } |
467 | ||
c906108c SS |
468 | /* Find the pc saved in frame FRAME. */ |
469 | ||
470 | CORE_ADDR | |
fba45db2 | 471 | sparc_frame_saved_pc (struct frame_info *frame) |
c906108c | 472 | { |
d9d9c31f | 473 | char buf[MAX_REGISTER_SIZE]; |
c906108c SS |
474 | CORE_ADDR addr; |
475 | ||
5a203e44 | 476 | if ((get_frame_type (frame) == SIGTRAMP_FRAME)) |
c906108c SS |
477 | { |
478 | /* This is the signal trampoline frame. | |
c5aa993b | 479 | Get the saved PC from the sigcontext structure. */ |
c906108c SS |
480 | |
481 | #ifndef SIGCONTEXT_PC_OFFSET | |
482 | #define SIGCONTEXT_PC_OFFSET 12 | |
483 | #endif | |
484 | ||
485 | CORE_ADDR sigcontext_addr; | |
5af923b0 | 486 | char *scbuf; |
c906108c SS |
487 | int saved_pc_offset = SIGCONTEXT_PC_OFFSET; |
488 | char *name = NULL; | |
489 | ||
5af923b0 MS |
490 | scbuf = alloca (TARGET_PTR_BIT / HOST_CHAR_BIT); |
491 | ||
c906108c | 492 | /* Solaris2 ucbsigvechandler passes a pointer to a sigcontext |
c5aa993b | 493 | as the third parameter. The offset to the saved pc is 12. */ |
50abf9e5 | 494 | find_pc_partial_function (get_frame_pc (frame), &name, |
c5aa993b | 495 | (CORE_ADDR *) NULL, (CORE_ADDR *) NULL); |
c906108c SS |
496 | if (name && STREQ (name, "ucbsigvechandler")) |
497 | saved_pc_offset = 12; | |
498 | ||
499 | /* The sigcontext address is contained in register O2. */ | |
ac2adee5 AC |
500 | { |
501 | ULONGEST tmp; | |
502 | frame_read_unsigned_register (frame, O0_REGNUM + 2, &tmp); | |
503 | sigcontext_addr = tmp; | |
504 | } | |
c906108c SS |
505 | |
506 | /* Don't cause a memory_error when accessing sigcontext in case the | |
c5aa993b | 507 | stack layout has changed or the stack is corrupt. */ |
c906108c SS |
508 | target_read_memory (sigcontext_addr + saved_pc_offset, |
509 | scbuf, sizeof (scbuf)); | |
7c0b4a20 | 510 | return extract_unsigned_integer (scbuf, sizeof (scbuf)); |
c906108c | 511 | } |
da50a4b7 | 512 | else if (get_frame_extra_info (frame)->in_prologue || |
11c02a10 AC |
513 | (get_next_frame (frame) != NULL && |
514 | ((get_frame_type (get_next_frame (frame)) == SIGTRAMP_FRAME) || | |
515 | deprecated_frame_in_dummy (get_next_frame (frame))) && | |
5af923b0 | 516 | frameless_look_for_prologue (frame))) |
c906108c SS |
517 | { |
518 | /* A frameless function interrupted by a signal did not save | |
c5aa993b | 519 | the PC, it is still in %o7. */ |
ac2adee5 AC |
520 | ULONGEST tmp; |
521 | frame_read_unsigned_register (frame, O7_REGNUM, &tmp); | |
522 | return PC_ADJUST (tmp); | |
c906108c | 523 | } |
da50a4b7 AC |
524 | if (get_frame_extra_info (frame)->flat) |
525 | addr = get_frame_extra_info (frame)->pc_addr; | |
c906108c | 526 | else |
da50a4b7 | 527 | addr = get_frame_extra_info (frame)->bottom + FRAME_SAVED_I0 + |
c906108c SS |
528 | SPARC_INTREG_SIZE * (I7_REGNUM - I0_REGNUM); |
529 | ||
530 | if (addr == 0) | |
531 | /* A flat frame leaf function might not save the PC anywhere, | |
532 | just leave it in %o7. */ | |
533 | return PC_ADJUST (read_register (O7_REGNUM)); | |
534 | ||
535 | read_memory (addr, buf, SPARC_INTREG_SIZE); | |
7c0b4a20 | 536 | return PC_ADJUST (extract_unsigned_integer (buf, SPARC_INTREG_SIZE)); |
c906108c SS |
537 | } |
538 | ||
539 | /* Since an individual frame in the frame cache is defined by two | |
540 | arguments (a frame pointer and a stack pointer), we need two | |
541 | arguments to get info for an arbitrary stack frame. This routine | |
542 | takes two arguments and makes the cached frames look as if these | |
543 | two arguments defined a frame on the cache. This allows the rest | |
544 | of info frame to extract the important arguments without | |
545 | difficulty. */ | |
546 | ||
547 | struct frame_info * | |
fba45db2 | 548 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
c906108c SS |
549 | { |
550 | struct frame_info *frame; | |
551 | ||
552 | if (argc != 2) | |
553 | error ("Sparc frame specifications require two arguments: fp and sp"); | |
554 | ||
555 | frame = create_new_frame (argv[0], 0); | |
556 | ||
557 | if (!frame) | |
8e65ff28 AC |
558 | internal_error (__FILE__, __LINE__, |
559 | "create_new_frame returned invalid frame"); | |
c5aa993b | 560 | |
da50a4b7 | 561 | get_frame_extra_info (frame)->bottom = argv[1]; |
8bedc050 | 562 | deprecated_update_frame_pc_hack (frame, DEPRECATED_FRAME_SAVED_PC (frame)); |
c906108c SS |
563 | return frame; |
564 | } | |
565 | ||
566 | /* Given a pc value, skip it forward past the function prologue by | |
567 | disassembling instructions that appear to be a prologue. | |
568 | ||
569 | If FRAMELESS_P is set, we are only testing to see if the function | |
570 | is frameless. This allows a quicker answer. | |
571 | ||
572 | This routine should be more specific in its actions; making sure | |
573 | that it uses the same register in the initial prologue section. */ | |
574 | ||
5af923b0 MS |
575 | static CORE_ADDR examine_prologue (CORE_ADDR, int, struct frame_info *, |
576 | CORE_ADDR *); | |
c906108c | 577 | |
c5aa993b | 578 | static CORE_ADDR |
fba45db2 KB |
579 | examine_prologue (CORE_ADDR start_pc, int frameless_p, struct frame_info *fi, |
580 | CORE_ADDR *saved_regs) | |
c906108c SS |
581 | { |
582 | int insn; | |
583 | int dest = -1; | |
584 | CORE_ADDR pc = start_pc; | |
585 | int is_flat = 0; | |
586 | ||
587 | insn = fetch_instruction (pc); | |
588 | ||
589 | /* Recognize the `sethi' insn and record its destination. */ | |
590 | if (X_OP (insn) == 0 && X_OP2 (insn) == 4) | |
591 | { | |
592 | dest = X_RD (insn); | |
593 | pc += 4; | |
594 | insn = fetch_instruction (pc); | |
595 | } | |
596 | ||
597 | /* Recognize an add immediate value to register to either %g1 or | |
598 | the destination register recorded above. Actually, this might | |
599 | well recognize several different arithmetic operations. | |
600 | It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1" | |
601 | followed by "save %sp, %g1, %sp" is a valid prologue (Not that | |
602 | I imagine any compiler really does that, however). */ | |
603 | if (X_OP (insn) == 2 | |
604 | && X_I (insn) | |
605 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) | |
606 | { | |
607 | pc += 4; | |
608 | insn = fetch_instruction (pc); | |
609 | } | |
610 | ||
611 | /* Recognize any SAVE insn. */ | |
612 | if (X_OP (insn) == 2 && X_OP3 (insn) == 60) | |
613 | { | |
614 | pc += 4; | |
c5aa993b JM |
615 | if (frameless_p) /* If the save is all we care about, */ |
616 | return pc; /* return before doing more work */ | |
c906108c SS |
617 | insn = fetch_instruction (pc); |
618 | } | |
619 | /* Recognize add to %sp. */ | |
620 | else if (X_OP (insn) == 2 && X_RD (insn) == 14 && X_OP3 (insn) == 0) | |
621 | { | |
622 | pc += 4; | |
c5aa993b JM |
623 | if (frameless_p) /* If the add is all we care about, */ |
624 | return pc; /* return before doing more work */ | |
c906108c SS |
625 | is_flat = 1; |
626 | insn = fetch_instruction (pc); | |
627 | /* Recognize store of frame pointer (i7). */ | |
628 | if (X_OP (insn) == 3 | |
629 | && X_RD (insn) == 31 | |
630 | && X_OP3 (insn) == 4 | |
631 | && X_RS1 (insn) == 14) | |
632 | { | |
633 | pc += 4; | |
634 | insn = fetch_instruction (pc); | |
635 | ||
636 | /* Recognize sub %sp, <anything>, %i7. */ | |
c5aa993b | 637 | if (X_OP (insn) == 2 |
c906108c SS |
638 | && X_OP3 (insn) == 4 |
639 | && X_RS1 (insn) == 14 | |
640 | && X_RD (insn) == 31) | |
641 | { | |
642 | pc += 4; | |
643 | insn = fetch_instruction (pc); | |
644 | } | |
645 | else | |
646 | return pc; | |
647 | } | |
648 | else | |
649 | return pc; | |
650 | } | |
651 | else | |
652 | /* Without a save or add instruction, it's not a prologue. */ | |
653 | return start_pc; | |
654 | ||
655 | while (1) | |
656 | { | |
657 | /* Recognize stores into the frame from the input registers. | |
5af923b0 MS |
658 | This recognizes all non alternate stores of an input register, |
659 | into a location offset from the frame pointer between | |
660 | +68 and +92. */ | |
661 | ||
662 | /* The above will fail for arguments that are promoted | |
663 | (eg. shorts to ints or floats to doubles), because the compiler | |
664 | will pass them in positive-offset frame space, but the prologue | |
665 | will save them (after conversion) in negative frame space at an | |
666 | unpredictable offset. Therefore I am going to remove the | |
667 | restriction on the target-address of the save, on the theory | |
668 | that any unbroken sequence of saves from input registers must | |
669 | be part of the prologue. In un-optimized code (at least), I'm | |
670 | fairly sure that the compiler would emit SOME other instruction | |
671 | (eg. a move or add) before emitting another save that is actually | |
672 | a part of the function body. | |
673 | ||
674 | Besides, the reserved stack space is different for SPARC64 anyway. | |
675 | ||
676 | MVS 4/23/2000 */ | |
677 | ||
678 | if (X_OP (insn) == 3 | |
679 | && (X_OP3 (insn) & 0x3c) == 4 /* Store, non-alternate. */ | |
680 | && (X_RD (insn) & 0x18) == 0x18 /* Input register. */ | |
681 | && X_I (insn) /* Immediate mode. */ | |
682 | && X_RS1 (insn) == 30) /* Off of frame pointer. */ | |
683 | ; /* empty statement -- fall thru to end of loop */ | |
684 | else if (GDB_TARGET_IS_SPARC64 | |
685 | && X_OP (insn) == 3 | |
686 | && (X_OP3 (insn) & 0x3c) == 12 /* store, extended (64-bit) */ | |
687 | && (X_RD (insn) & 0x18) == 0x18 /* input register */ | |
688 | && X_I (insn) /* immediate mode */ | |
689 | && X_RS1 (insn) == 30) /* off of frame pointer */ | |
690 | ; /* empty statement -- fall thru to end of loop */ | |
691 | else if (X_OP (insn) == 3 | |
692 | && (X_OP3 (insn) & 0x3c) == 36 /* store, floating-point */ | |
693 | && X_I (insn) /* immediate mode */ | |
694 | && X_RS1 (insn) == 30) /* off of frame pointer */ | |
695 | ; /* empty statement -- fall thru to end of loop */ | |
c906108c SS |
696 | else if (is_flat |
697 | && X_OP (insn) == 3 | |
5af923b0 MS |
698 | && X_OP3 (insn) == 4 /* store? */ |
699 | && X_RS1 (insn) == 14) /* off of frame pointer */ | |
c906108c SS |
700 | { |
701 | if (saved_regs && X_I (insn)) | |
5af923b0 | 702 | saved_regs[X_RD (insn)] = |
da50a4b7 | 703 | get_frame_base (fi) + get_frame_extra_info (fi)->sp_offset + X_SIMM13 (insn); |
c906108c SS |
704 | } |
705 | else | |
706 | break; | |
707 | pc += 4; | |
708 | insn = fetch_instruction (pc); | |
709 | } | |
710 | ||
711 | return pc; | |
712 | } | |
713 | ||
f510d44e DM |
714 | /* Advance PC across any function entry prologue instructions to reach |
715 | some "real" code. */ | |
716 | ||
c5aa993b | 717 | CORE_ADDR |
f510d44e | 718 | sparc_skip_prologue (CORE_ADDR start_pc) |
c906108c | 719 | { |
f510d44e DM |
720 | struct symtab_and_line sal; |
721 | CORE_ADDR func_start, func_end; | |
722 | ||
723 | /* This is the preferred method, find the end of the prologue by | |
724 | using the debugging information. */ | |
725 | if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) | |
726 | { | |
727 | sal = find_pc_line (func_start, 0); | |
728 | ||
729 | if (sal.end < func_end | |
730 | && start_pc <= sal.end) | |
731 | return sal.end; | |
732 | } | |
733 | ||
734 | /* Oh well, examine the code by hand. */ | |
735 | return examine_prologue (start_pc, 0, NULL, NULL); | |
c906108c SS |
736 | } |
737 | ||
9319a2fe DM |
738 | /* Is the prologue at IP frameless? */ |
739 | ||
740 | int | |
741 | sparc_prologue_frameless_p (CORE_ADDR ip) | |
742 | { | |
f510d44e | 743 | return ip == examine_prologue (ip, 1, NULL, NULL); |
9319a2fe DM |
744 | } |
745 | ||
c906108c SS |
746 | /* Check instruction at ADDR to see if it is a branch. |
747 | All non-annulled instructions will go to NPC or will trap. | |
748 | Set *TARGET if we find a candidate branch; set to zero if not. | |
749 | ||
750 | This isn't static as it's used by remote-sa.sparc.c. */ | |
751 | ||
752 | static branch_type | |
fba45db2 | 753 | isbranch (long instruction, CORE_ADDR addr, CORE_ADDR *target) |
c906108c SS |
754 | { |
755 | branch_type val = not_branch; | |
756 | long int offset = 0; /* Must be signed for sign-extend. */ | |
757 | ||
758 | *target = 0; | |
759 | ||
760 | if (X_OP (instruction) == 0 | |
761 | && (X_OP2 (instruction) == 2 | |
762 | || X_OP2 (instruction) == 6 | |
763 | || X_OP2 (instruction) == 1 | |
764 | || X_OP2 (instruction) == 3 | |
765 | || X_OP2 (instruction) == 5 | |
5af923b0 | 766 | || (GDB_TARGET_IS_SPARC64 && X_OP2 (instruction) == 7))) |
c906108c SS |
767 | { |
768 | if (X_COND (instruction) == 8) | |
769 | val = X_A (instruction) ? baa : ba; | |
770 | else | |
771 | val = X_A (instruction) ? bicca : bicc; | |
772 | switch (X_OP2 (instruction)) | |
773 | { | |
5af923b0 MS |
774 | case 7: |
775 | if (!GDB_TARGET_IS_SPARC64) | |
776 | break; | |
777 | /* else fall thru */ | |
c906108c SS |
778 | case 2: |
779 | case 6: | |
c906108c SS |
780 | offset = 4 * X_DISP22 (instruction); |
781 | break; | |
782 | case 1: | |
783 | case 5: | |
784 | offset = 4 * X_DISP19 (instruction); | |
785 | break; | |
786 | case 3: | |
787 | offset = 4 * X_DISP16 (instruction); | |
788 | break; | |
789 | } | |
790 | *target = addr + offset; | |
791 | } | |
5af923b0 MS |
792 | else if (GDB_TARGET_IS_SPARC64 |
793 | && X_OP (instruction) == 2 | |
c906108c SS |
794 | && X_OP3 (instruction) == 62) |
795 | { | |
796 | if (X_FCN (instruction) == 0) | |
797 | { | |
798 | /* done */ | |
799 | *target = read_register (TNPC_REGNUM); | |
800 | val = done_retry; | |
801 | } | |
802 | else if (X_FCN (instruction) == 1) | |
803 | { | |
804 | /* retry */ | |
805 | *target = read_register (TPC_REGNUM); | |
806 | val = done_retry; | |
807 | } | |
808 | } | |
c906108c SS |
809 | |
810 | return val; | |
811 | } | |
812 | \f | |
813 | /* Find register number REGNUM relative to FRAME and put its | |
814 | (raw) contents in *RAW_BUFFER. Set *OPTIMIZED if the variable | |
815 | was optimized out (and thus can't be fetched). If the variable | |
816 | was fetched from memory, set *ADDRP to where it was fetched from, | |
817 | otherwise it was fetched from a register. | |
818 | ||
819 | The argument RAW_BUFFER must point to aligned memory. */ | |
820 | ||
821 | void | |
fba45db2 KB |
822 | sparc_get_saved_register (char *raw_buffer, int *optimized, CORE_ADDR *addrp, |
823 | struct frame_info *frame, int regnum, | |
824 | enum lval_type *lval) | |
c906108c SS |
825 | { |
826 | struct frame_info *frame1; | |
827 | CORE_ADDR addr; | |
828 | ||
829 | if (!target_has_registers) | |
830 | error ("No registers."); | |
831 | ||
832 | if (optimized) | |
833 | *optimized = 0; | |
834 | ||
835 | addr = 0; | |
836 | ||
837 | /* FIXME This code extracted from infcmd.c; should put elsewhere! */ | |
838 | if (frame == NULL) | |
839 | { | |
840 | /* error ("No selected frame."); */ | |
841 | if (!target_has_registers) | |
c5aa993b | 842 | error ("The program has no registers now."); |
6e7f8b9c | 843 | if (deprecated_selected_frame == NULL) |
c5aa993b | 844 | error ("No selected frame."); |
c906108c | 845 | /* Try to use selected frame */ |
6e7f8b9c | 846 | frame = get_prev_frame (deprecated_selected_frame); |
c906108c | 847 | if (frame == 0) |
c5aa993b | 848 | error ("Cmd not meaningful in the outermost frame."); |
c906108c SS |
849 | } |
850 | ||
851 | ||
11c02a10 | 852 | frame1 = get_next_frame (frame); |
c906108c SS |
853 | |
854 | /* Get saved PC from the frame info if not in innermost frame. */ | |
855 | if (regnum == PC_REGNUM && frame1 != NULL) | |
856 | { | |
857 | if (lval != NULL) | |
858 | *lval = not_lval; | |
859 | if (raw_buffer != NULL) | |
860 | { | |
861 | /* Put it back in target format. */ | |
fbd9dcd3 | 862 | store_unsigned_integer (raw_buffer, REGISTER_RAW_SIZE (regnum), get_frame_pc (frame)); |
c906108c SS |
863 | } |
864 | if (addrp != NULL) | |
865 | *addrp = 0; | |
866 | return; | |
867 | } | |
868 | ||
869 | while (frame1 != NULL) | |
870 | { | |
5af923b0 MS |
871 | /* FIXME MVS: wrong test for dummy frame at entry. */ |
872 | ||
da50a4b7 AC |
873 | if (get_frame_pc (frame1) >= (get_frame_extra_info (frame1)->bottom |
874 | ? get_frame_extra_info (frame1)->bottom | |
875 | : read_sp ()) | |
50abf9e5 | 876 | && get_frame_pc (frame1) <= get_frame_base (frame1)) |
c906108c SS |
877 | { |
878 | /* Dummy frame. All but the window regs are in there somewhere. | |
879 | The window registers are saved on the stack, just like in a | |
880 | normal frame. */ | |
881 | if (regnum >= G1_REGNUM && regnum < G1_REGNUM + 7) | |
1e2330ba | 882 | addr = get_frame_base (frame1) + (regnum - G0_REGNUM) * SPARC_INTREG_SIZE |
c906108c SS |
883 | - (FP_REGISTER_BYTES + 8 * SPARC_INTREG_SIZE); |
884 | else if (regnum >= I0_REGNUM && regnum < I0_REGNUM + 8) | |
f621c63e AC |
885 | /* NOTE: cagney/2002-05-04: The call to get_prev_frame() |
886 | is safe/cheap - there will always be a prev frame. | |
887 | This is because frame1 is initialized to frame->next | |
888 | (frame1->prev == frame) and is then advanced towards | |
889 | the innermost (next) frame. */ | |
da50a4b7 | 890 | addr = (get_frame_extra_info (get_prev_frame (frame1))->bottom |
c906108c SS |
891 | + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE |
892 | + FRAME_SAVED_I0); | |
893 | else if (regnum >= L0_REGNUM && regnum < L0_REGNUM + 8) | |
f621c63e AC |
894 | /* NOTE: cagney/2002-05-04: The call to get_prev_frame() |
895 | is safe/cheap - there will always be a prev frame. | |
896 | This is because frame1 is initialized to frame->next | |
897 | (frame1->prev == frame) and is then advanced towards | |
898 | the innermost (next) frame. */ | |
da50a4b7 | 899 | addr = (get_frame_extra_info (get_prev_frame (frame1))->bottom |
c906108c SS |
900 | + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE |
901 | + FRAME_SAVED_L0); | |
902 | else if (regnum >= O0_REGNUM && regnum < O0_REGNUM + 8) | |
1e2330ba | 903 | addr = get_frame_base (frame1) + (regnum - O0_REGNUM) * SPARC_INTREG_SIZE |
c906108c | 904 | - (FP_REGISTER_BYTES + 16 * SPARC_INTREG_SIZE); |
5af923b0 | 905 | else if (SPARC_HAS_FPU && |
60054393 | 906 | regnum >= FP0_REGNUM && regnum < FP0_REGNUM + 32) |
1e2330ba | 907 | addr = get_frame_base (frame1) + (regnum - FP0_REGNUM) * 4 |
c906108c | 908 | - (FP_REGISTER_BYTES); |
5af923b0 | 909 | else if (GDB_TARGET_IS_SPARC64 && SPARC_HAS_FPU && |
60054393 | 910 | regnum >= FP0_REGNUM + 32 && regnum < FP_MAX_REGNUM) |
1e2330ba | 911 | addr = get_frame_base (frame1) + 32 * 4 + (regnum - FP0_REGNUM - 32) * 8 |
c906108c | 912 | - (FP_REGISTER_BYTES); |
c906108c | 913 | else if (regnum >= Y_REGNUM && regnum < NUM_REGS) |
1e2330ba | 914 | addr = get_frame_base (frame1) + (regnum - Y_REGNUM) * SPARC_INTREG_SIZE |
c906108c SS |
915 | - (FP_REGISTER_BYTES + 24 * SPARC_INTREG_SIZE); |
916 | } | |
da50a4b7 | 917 | else if (get_frame_extra_info (frame1)->flat) |
c906108c SS |
918 | { |
919 | ||
920 | if (regnum == RP_REGNUM) | |
da50a4b7 | 921 | addr = get_frame_extra_info (frame1)->pc_addr; |
c906108c | 922 | else if (regnum == I7_REGNUM) |
da50a4b7 | 923 | addr = get_frame_extra_info (frame1)->fp_addr; |
c906108c SS |
924 | else |
925 | { | |
926 | CORE_ADDR func_start; | |
5af923b0 MS |
927 | CORE_ADDR *regs; |
928 | ||
929 | regs = alloca (NUM_REGS * sizeof (CORE_ADDR)); | |
930 | memset (regs, 0, NUM_REGS * sizeof (CORE_ADDR)); | |
c906108c | 931 | |
50abf9e5 | 932 | find_pc_partial_function (get_frame_pc (frame1), NULL, &func_start, NULL); |
5af923b0 MS |
933 | examine_prologue (func_start, 0, frame1, regs); |
934 | addr = regs[regnum]; | |
c906108c SS |
935 | } |
936 | } | |
937 | else | |
938 | { | |
939 | /* Normal frame. Local and In registers are saved on stack. */ | |
940 | if (regnum >= I0_REGNUM && regnum < I0_REGNUM + 8) | |
da50a4b7 | 941 | addr = (get_frame_extra_info (get_prev_frame (frame1))->bottom |
c906108c SS |
942 | + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE |
943 | + FRAME_SAVED_I0); | |
944 | else if (regnum >= L0_REGNUM && regnum < L0_REGNUM + 8) | |
da50a4b7 | 945 | addr = (get_frame_extra_info (get_prev_frame (frame1))->bottom |
c906108c SS |
946 | + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE |
947 | + FRAME_SAVED_L0); | |
948 | else if (regnum >= O0_REGNUM && regnum < O0_REGNUM + 8) | |
949 | { | |
950 | /* Outs become ins. */ | |
ac2adee5 AC |
951 | int realnum; |
952 | frame_register (frame1, (regnum - O0_REGNUM + I0_REGNUM), | |
953 | optimized, lval, addrp, &realnum, raw_buffer); | |
c906108c SS |
954 | return; |
955 | } | |
956 | } | |
957 | if (addr != 0) | |
958 | break; | |
11c02a10 | 959 | frame1 = get_next_frame (frame1); |
c906108c SS |
960 | } |
961 | if (addr != 0) | |
962 | { | |
963 | if (lval != NULL) | |
964 | *lval = lval_memory; | |
965 | if (regnum == SP_REGNUM) | |
966 | { | |
967 | if (raw_buffer != NULL) | |
968 | { | |
969 | /* Put it back in target format. */ | |
fbd9dcd3 | 970 | store_unsigned_integer (raw_buffer, REGISTER_RAW_SIZE (regnum), addr); |
c906108c SS |
971 | } |
972 | if (addrp != NULL) | |
973 | *addrp = 0; | |
974 | return; | |
975 | } | |
976 | if (raw_buffer != NULL) | |
977 | read_memory (addr, raw_buffer, REGISTER_RAW_SIZE (regnum)); | |
978 | } | |
979 | else | |
980 | { | |
981 | if (lval != NULL) | |
982 | *lval = lval_register; | |
983 | addr = REGISTER_BYTE (regnum); | |
984 | if (raw_buffer != NULL) | |
4caf0990 | 985 | deprecated_read_register_gen (regnum, raw_buffer); |
c906108c SS |
986 | } |
987 | if (addrp != NULL) | |
988 | *addrp = addr; | |
989 | } | |
990 | ||
991 | /* Push an empty stack frame, and record in it the current PC, regs, etc. | |
992 | ||
993 | We save the non-windowed registers and the ins. The locals and outs | |
994 | are new; they don't need to be saved. The i's and l's of | |
995 | the last frame were already saved on the stack. */ | |
996 | ||
997 | /* Definitely see tm-sparc.h for more doc of the frame format here. */ | |
998 | ||
c906108c | 999 | /* See tm-sparc.h for how this is calculated. */ |
5af923b0 | 1000 | |
c906108c | 1001 | #define DUMMY_STACK_REG_BUF_SIZE \ |
60054393 | 1002 | (((8+8+8) * SPARC_INTREG_SIZE) + FP_REGISTER_BYTES) |
5af923b0 MS |
1003 | #define DUMMY_STACK_SIZE \ |
1004 | (DUMMY_STACK_REG_BUF_SIZE + DUMMY_REG_SAVE_OFFSET) | |
c906108c SS |
1005 | |
1006 | void | |
fba45db2 | 1007 | sparc_push_dummy_frame (void) |
c906108c SS |
1008 | { |
1009 | CORE_ADDR sp, old_sp; | |
5af923b0 MS |
1010 | char *register_temp; |
1011 | ||
1012 | register_temp = alloca (DUMMY_STACK_SIZE); | |
c906108c SS |
1013 | |
1014 | old_sp = sp = read_sp (); | |
1015 | ||
5af923b0 MS |
1016 | if (GDB_TARGET_IS_SPARC64) |
1017 | { | |
1018 | /* PC, NPC, CCR, FSR, FPRS, Y, ASI */ | |
73937e03 AC |
1019 | deprecated_read_register_bytes (REGISTER_BYTE (PC_REGNUM), |
1020 | ®ister_temp[0], | |
1021 | REGISTER_RAW_SIZE (PC_REGNUM) * 7); | |
1022 | deprecated_read_register_bytes (REGISTER_BYTE (PSTATE_REGNUM), | |
1023 | ®ister_temp[7 * SPARC_INTREG_SIZE], | |
1024 | REGISTER_RAW_SIZE (PSTATE_REGNUM)); | |
5af923b0 MS |
1025 | /* FIXME: not sure what needs to be saved here. */ |
1026 | } | |
1027 | else | |
1028 | { | |
1029 | /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */ | |
73937e03 AC |
1030 | deprecated_read_register_bytes (REGISTER_BYTE (Y_REGNUM), |
1031 | ®ister_temp[0], | |
1032 | REGISTER_RAW_SIZE (Y_REGNUM) * 8); | |
5af923b0 | 1033 | } |
c906108c | 1034 | |
73937e03 AC |
1035 | deprecated_read_register_bytes (REGISTER_BYTE (O0_REGNUM), |
1036 | ®ister_temp[8 * SPARC_INTREG_SIZE], | |
1037 | SPARC_INTREG_SIZE * 8); | |
c906108c | 1038 | |
73937e03 AC |
1039 | deprecated_read_register_bytes (REGISTER_BYTE (G0_REGNUM), |
1040 | ®ister_temp[16 * SPARC_INTREG_SIZE], | |
1041 | SPARC_INTREG_SIZE * 8); | |
c906108c | 1042 | |
5af923b0 | 1043 | if (SPARC_HAS_FPU) |
73937e03 AC |
1044 | deprecated_read_register_bytes (REGISTER_BYTE (FP0_REGNUM), |
1045 | ®ister_temp[24 * SPARC_INTREG_SIZE], | |
1046 | FP_REGISTER_BYTES); | |
c906108c SS |
1047 | |
1048 | sp -= DUMMY_STACK_SIZE; | |
1049 | ||
6c0e89ed | 1050 | DEPRECATED_DUMMY_WRITE_SP (sp); |
c906108c SS |
1051 | |
1052 | write_memory (sp + DUMMY_REG_SAVE_OFFSET, ®ister_temp[0], | |
1053 | DUMMY_STACK_REG_BUF_SIZE); | |
1054 | ||
1055 | if (strcmp (target_shortname, "sim") != 0) | |
1056 | { | |
2757dd86 AC |
1057 | /* NOTE: cagney/2002-04-04: The code below originally contained |
1058 | GDB's _only_ call to write_fp(). That call was eliminated by | |
1059 | inlining the corresponding code. For the 64 bit case, the | |
1060 | old function (sparc64_write_fp) did the below although I'm | |
1061 | not clear why. The same goes for why this is only done when | |
1062 | the underlying target is a simulator. */ | |
f32e7a74 | 1063 | if (GDB_TARGET_IS_SPARC64) |
2757dd86 AC |
1064 | { |
1065 | /* Target is a 64 bit SPARC. */ | |
0ba6dca9 | 1066 | CORE_ADDR oldfp = read_register (DEPRECATED_FP_REGNUM); |
2757dd86 | 1067 | if (oldfp & 1) |
0ba6dca9 | 1068 | write_register (DEPRECATED_FP_REGNUM, old_sp - 2047); |
2757dd86 | 1069 | else |
0ba6dca9 | 1070 | write_register (DEPRECATED_FP_REGNUM, old_sp); |
2757dd86 AC |
1071 | } |
1072 | else | |
1073 | { | |
1074 | /* Target is a 32 bit SPARC. */ | |
0ba6dca9 | 1075 | write_register (DEPRECATED_FP_REGNUM, old_sp); |
2757dd86 | 1076 | } |
c906108c | 1077 | /* Set return address register for the call dummy to the current PC. */ |
c5aa993b | 1078 | write_register (I7_REGNUM, read_pc () - 8); |
c906108c SS |
1079 | } |
1080 | else | |
1081 | { | |
1082 | /* The call dummy will write this value to FP before executing | |
1083 | the 'save'. This ensures that register window flushes work | |
c5aa993b | 1084 | correctly in the simulator. */ |
0ba6dca9 | 1085 | write_register (G0_REGNUM + 1, read_register (DEPRECATED_FP_REGNUM)); |
c5aa993b | 1086 | |
c906108c SS |
1087 | /* The call dummy will write this value to FP after executing |
1088 | the 'save'. */ | |
c5aa993b JM |
1089 | write_register (G0_REGNUM + 2, old_sp); |
1090 | ||
c906108c | 1091 | /* The call dummy will write this value to the return address (%i7) after |
c5aa993b JM |
1092 | executing the 'save'. */ |
1093 | write_register (G0_REGNUM + 3, read_pc () - 8); | |
1094 | ||
c906108c | 1095 | /* Set the FP that the call dummy will be using after the 'save'. |
c5aa993b | 1096 | This makes backtraces from an inferior function call work properly. */ |
0ba6dca9 | 1097 | write_register (DEPRECATED_FP_REGNUM, old_sp); |
c906108c SS |
1098 | } |
1099 | } | |
1100 | ||
1101 | /* sparc_frame_find_saved_regs (). This function is here only because | |
1102 | pop_frame uses it. Note there is an interesting corner case which | |
1103 | I think few ports of GDB get right--if you are popping a frame | |
1104 | which does not save some register that *is* saved by a more inner | |
1105 | frame (such a frame will never be a dummy frame because dummy | |
ac2adee5 AC |
1106 | frames save all registers). |
1107 | ||
1108 | NOTE: cagney/2003-03-12: Since pop_frame has been rewritten to use | |
1109 | frame_unwind_register() the need for this function is questionable. | |
c906108c | 1110 | |
5af923b0 | 1111 | Stores, into an array of CORE_ADDR, |
c906108c SS |
1112 | the addresses of the saved registers of frame described by FRAME_INFO. |
1113 | This includes special registers such as pc and fp saved in special | |
1114 | ways in the stack frame. sp is even more special: | |
1115 | the address we return for it IS the sp for the next frame. | |
1116 | ||
1117 | Note that on register window machines, we are currently making the | |
1118 | assumption that window registers are being saved somewhere in the | |
1119 | frame in which they are being used. If they are stored in an | |
1120 | inferior frame, find_saved_register will break. | |
1121 | ||
1122 | On the Sun 4, the only time all registers are saved is when | |
1123 | a dummy frame is involved. Otherwise, the only saved registers | |
1124 | are the LOCAL and IN registers which are saved as a result | |
1125 | of the "save/restore" opcodes. This condition is determined | |
1126 | by address rather than by value. | |
1127 | ||
1128 | The "pc" is not stored in a frame on the SPARC. (What is stored | |
1129 | is a return address minus 8.) sparc_pop_frame knows how to | |
1130 | deal with that. Other routines might or might not. | |
1131 | ||
1132 | See tm-sparc.h (PUSH_DUMMY_FRAME and friends) for CRITICAL information | |
1133 | about how this works. */ | |
1134 | ||
5af923b0 | 1135 | static void sparc_frame_find_saved_regs (struct frame_info *, CORE_ADDR *); |
c906108c SS |
1136 | |
1137 | static void | |
fba45db2 | 1138 | sparc_frame_find_saved_regs (struct frame_info *fi, CORE_ADDR *saved_regs_addr) |
c906108c SS |
1139 | { |
1140 | register int regnum; | |
c193f6ac | 1141 | CORE_ADDR frame_addr = get_frame_base (fi); |
c906108c | 1142 | |
43bd9a9e | 1143 | gdb_assert (fi != NULL); |
c906108c | 1144 | |
5af923b0 | 1145 | memset (saved_regs_addr, 0, NUM_REGS * sizeof (CORE_ADDR)); |
c906108c | 1146 | |
da50a4b7 AC |
1147 | if (get_frame_pc (fi) >= (get_frame_extra_info (fi)->bottom |
1148 | ? get_frame_extra_info (fi)->bottom | |
1149 | : read_sp ()) | |
50abf9e5 | 1150 | && get_frame_pc (fi) <= get_frame_base (fi)) |
c906108c SS |
1151 | { |
1152 | /* Dummy frame. All but the window regs are in there somewhere. */ | |
c5aa993b | 1153 | for (regnum = G1_REGNUM; regnum < G1_REGNUM + 7; regnum++) |
5af923b0 | 1154 | saved_regs_addr[regnum] = |
c906108c | 1155 | frame_addr + (regnum - G0_REGNUM) * SPARC_INTREG_SIZE |
c5aa993b | 1156 | - DUMMY_STACK_REG_BUF_SIZE + 16 * SPARC_INTREG_SIZE; |
5af923b0 | 1157 | |
c5aa993b | 1158 | for (regnum = I0_REGNUM; regnum < I0_REGNUM + 8; regnum++) |
5af923b0 | 1159 | saved_regs_addr[regnum] = |
c906108c | 1160 | frame_addr + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE |
c5aa993b | 1161 | - DUMMY_STACK_REG_BUF_SIZE + 8 * SPARC_INTREG_SIZE; |
60054393 | 1162 | |
5af923b0 MS |
1163 | if (SPARC_HAS_FPU) |
1164 | for (regnum = FP0_REGNUM; regnum < FP_MAX_REGNUM; regnum++) | |
1165 | saved_regs_addr[regnum] = frame_addr + (regnum - FP0_REGNUM) * 4 | |
1166 | - DUMMY_STACK_REG_BUF_SIZE + 24 * SPARC_INTREG_SIZE; | |
1167 | ||
1168 | if (GDB_TARGET_IS_SPARC64) | |
c906108c | 1169 | { |
5af923b0 MS |
1170 | for (regnum = PC_REGNUM; regnum < PC_REGNUM + 7; regnum++) |
1171 | { | |
1172 | saved_regs_addr[regnum] = | |
1173 | frame_addr + (regnum - PC_REGNUM) * SPARC_INTREG_SIZE | |
1174 | - DUMMY_STACK_REG_BUF_SIZE; | |
1175 | } | |
1176 | saved_regs_addr[PSTATE_REGNUM] = | |
1177 | frame_addr + 8 * SPARC_INTREG_SIZE - DUMMY_STACK_REG_BUF_SIZE; | |
c906108c | 1178 | } |
5af923b0 MS |
1179 | else |
1180 | for (regnum = Y_REGNUM; regnum < NUM_REGS; regnum++) | |
1181 | saved_regs_addr[regnum] = | |
1182 | frame_addr + (regnum - Y_REGNUM) * SPARC_INTREG_SIZE | |
1183 | - DUMMY_STACK_REG_BUF_SIZE; | |
1184 | ||
da50a4b7 AC |
1185 | frame_addr = (get_frame_extra_info (fi)->bottom |
1186 | ? get_frame_extra_info (fi)->bottom | |
1187 | : read_sp ()); | |
c906108c | 1188 | } |
da50a4b7 | 1189 | else if (get_frame_extra_info (fi)->flat) |
c906108c SS |
1190 | { |
1191 | CORE_ADDR func_start; | |
50abf9e5 | 1192 | find_pc_partial_function (get_frame_pc (fi), NULL, &func_start, NULL); |
c906108c SS |
1193 | examine_prologue (func_start, 0, fi, saved_regs_addr); |
1194 | ||
1195 | /* Flat register window frame. */ | |
da50a4b7 AC |
1196 | saved_regs_addr[RP_REGNUM] = get_frame_extra_info (fi)->pc_addr; |
1197 | saved_regs_addr[I7_REGNUM] = get_frame_extra_info (fi)->fp_addr; | |
c906108c SS |
1198 | } |
1199 | else | |
1200 | { | |
1201 | /* Normal frame. Just Local and In registers */ | |
da50a4b7 AC |
1202 | frame_addr = (get_frame_extra_info (fi)->bottom |
1203 | ? get_frame_extra_info (fi)->bottom | |
1204 | : read_sp ()); | |
c5aa993b | 1205 | for (regnum = L0_REGNUM; regnum < L0_REGNUM + 8; regnum++) |
5af923b0 | 1206 | saved_regs_addr[regnum] = |
c906108c SS |
1207 | (frame_addr + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE |
1208 | + FRAME_SAVED_L0); | |
c5aa993b | 1209 | for (regnum = I0_REGNUM; regnum < I0_REGNUM + 8; regnum++) |
5af923b0 | 1210 | saved_regs_addr[regnum] = |
c906108c SS |
1211 | (frame_addr + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE |
1212 | + FRAME_SAVED_I0); | |
1213 | } | |
11c02a10 | 1214 | if (get_next_frame (fi)) |
c906108c | 1215 | { |
da50a4b7 | 1216 | if (get_frame_extra_info (fi)->flat) |
c906108c | 1217 | { |
da50a4b7 | 1218 | saved_regs_addr[O7_REGNUM] = get_frame_extra_info (fi)->pc_addr; |
c906108c SS |
1219 | } |
1220 | else | |
1221 | { | |
1222 | /* Pull off either the next frame pointer or the stack pointer */ | |
1223 | CORE_ADDR next_next_frame_addr = | |
da50a4b7 AC |
1224 | (get_frame_extra_info (get_next_frame (fi))->bottom |
1225 | ? get_frame_extra_info (get_next_frame (fi))->bottom | |
1226 | : read_sp ()); | |
c5aa993b | 1227 | for (regnum = O0_REGNUM; regnum < O0_REGNUM + 8; regnum++) |
5af923b0 | 1228 | saved_regs_addr[regnum] = |
c906108c SS |
1229 | (next_next_frame_addr |
1230 | + (regnum - O0_REGNUM) * SPARC_INTREG_SIZE | |
1231 | + FRAME_SAVED_I0); | |
1232 | } | |
1233 | } | |
1234 | /* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */ | |
1235 | /* FIXME -- should this adjust for the sparc64 offset? */ | |
c193f6ac | 1236 | saved_regs_addr[SP_REGNUM] = get_frame_base (fi); |
c906108c SS |
1237 | } |
1238 | ||
1239 | /* Discard from the stack the innermost frame, restoring all saved registers. | |
1240 | ||
95486978 AC |
1241 | Note that the values stored in fsr by |
1242 | deprecated_get_frame_saved_regs are *in the context of the called | |
1243 | frame*. What this means is that the i regs of fsr must be restored | |
1244 | into the o regs of the (calling) frame that we pop into. We don't | |
1245 | care about the output regs of the calling frame, since unless it's | |
1246 | a dummy frame, it won't have any output regs in it. | |
c906108c SS |
1247 | |
1248 | We never have to bother with %l (local) regs, since the called routine's | |
1249 | locals get tossed, and the calling routine's locals are already saved | |
1250 | on its stack. */ | |
1251 | ||
1252 | /* Definitely see tm-sparc.h for more doc of the frame format here. */ | |
1253 | ||
1254 | void | |
fba45db2 | 1255 | sparc_pop_frame (void) |
c906108c SS |
1256 | { |
1257 | register struct frame_info *frame = get_current_frame (); | |
1258 | register CORE_ADDR pc; | |
5af923b0 MS |
1259 | CORE_ADDR *fsr; |
1260 | char *raw_buffer; | |
c906108c SS |
1261 | int regnum; |
1262 | ||
5af923b0 | 1263 | fsr = alloca (NUM_REGS * sizeof (CORE_ADDR)); |
b8b527c5 | 1264 | raw_buffer = alloca (DEPRECATED_REGISTER_BYTES); |
5af923b0 MS |
1265 | sparc_frame_find_saved_regs (frame, &fsr[0]); |
1266 | if (SPARC_HAS_FPU) | |
c906108c | 1267 | { |
5af923b0 | 1268 | if (fsr[FP0_REGNUM]) |
60054393 | 1269 | { |
5af923b0 | 1270 | read_memory (fsr[FP0_REGNUM], raw_buffer, FP_REGISTER_BYTES); |
73937e03 AC |
1271 | deprecated_write_register_bytes (REGISTER_BYTE (FP0_REGNUM), |
1272 | raw_buffer, FP_REGISTER_BYTES); | |
60054393 | 1273 | } |
5af923b0 | 1274 | if (!(GDB_TARGET_IS_SPARC64)) |
60054393 | 1275 | { |
5af923b0 MS |
1276 | if (fsr[FPS_REGNUM]) |
1277 | { | |
1278 | read_memory (fsr[FPS_REGNUM], raw_buffer, SPARC_INTREG_SIZE); | |
4caf0990 | 1279 | deprecated_write_register_gen (FPS_REGNUM, raw_buffer); |
5af923b0 MS |
1280 | } |
1281 | if (fsr[CPS_REGNUM]) | |
1282 | { | |
1283 | read_memory (fsr[CPS_REGNUM], raw_buffer, SPARC_INTREG_SIZE); | |
4caf0990 | 1284 | deprecated_write_register_gen (CPS_REGNUM, raw_buffer); |
5af923b0 | 1285 | } |
60054393 | 1286 | } |
60054393 | 1287 | } |
5af923b0 | 1288 | if (fsr[G1_REGNUM]) |
c906108c | 1289 | { |
5af923b0 | 1290 | read_memory (fsr[G1_REGNUM], raw_buffer, 7 * SPARC_INTREG_SIZE); |
73937e03 AC |
1291 | deprecated_write_register_bytes (REGISTER_BYTE (G1_REGNUM), raw_buffer, |
1292 | 7 * SPARC_INTREG_SIZE); | |
c906108c SS |
1293 | } |
1294 | ||
da50a4b7 | 1295 | if (get_frame_extra_info (frame)->flat) |
c906108c SS |
1296 | { |
1297 | /* Each register might or might not have been saved, need to test | |
c5aa993b | 1298 | individually. */ |
c906108c | 1299 | for (regnum = L0_REGNUM; regnum < L0_REGNUM + 8; ++regnum) |
5af923b0 MS |
1300 | if (fsr[regnum]) |
1301 | write_register (regnum, read_memory_integer (fsr[regnum], | |
c906108c SS |
1302 | SPARC_INTREG_SIZE)); |
1303 | for (regnum = I0_REGNUM; regnum < I0_REGNUM + 8; ++regnum) | |
5af923b0 MS |
1304 | if (fsr[regnum]) |
1305 | write_register (regnum, read_memory_integer (fsr[regnum], | |
c906108c SS |
1306 | SPARC_INTREG_SIZE)); |
1307 | ||
1308 | /* Handle all outs except stack pointer (o0-o5; o7). */ | |
1309 | for (regnum = O0_REGNUM; regnum < O0_REGNUM + 6; ++regnum) | |
5af923b0 MS |
1310 | if (fsr[regnum]) |
1311 | write_register (regnum, read_memory_integer (fsr[regnum], | |
c906108c | 1312 | SPARC_INTREG_SIZE)); |
5af923b0 | 1313 | if (fsr[O0_REGNUM + 7]) |
c906108c | 1314 | write_register (O0_REGNUM + 7, |
5af923b0 | 1315 | read_memory_integer (fsr[O0_REGNUM + 7], |
c906108c SS |
1316 | SPARC_INTREG_SIZE)); |
1317 | ||
6c0e89ed | 1318 | DEPRECATED_DUMMY_WRITE_SP (get_frame_base (frame)); |
c906108c | 1319 | } |
5af923b0 | 1320 | else if (fsr[I0_REGNUM]) |
c906108c SS |
1321 | { |
1322 | CORE_ADDR sp; | |
1323 | ||
5af923b0 MS |
1324 | char *reg_temp; |
1325 | ||
69cdf6a2 | 1326 | reg_temp = alloca (SPARC_INTREG_SIZE * 16); |
c906108c | 1327 | |
5af923b0 | 1328 | read_memory (fsr[I0_REGNUM], raw_buffer, 8 * SPARC_INTREG_SIZE); |
c906108c SS |
1329 | |
1330 | /* Get the ins and locals which we are about to restore. Just | |
c5aa993b JM |
1331 | moving the stack pointer is all that is really needed, except |
1332 | store_inferior_registers is then going to write the ins and | |
1333 | locals from the registers array, so we need to muck with the | |
1334 | registers array. */ | |
5af923b0 MS |
1335 | sp = fsr[SP_REGNUM]; |
1336 | ||
1337 | if (GDB_TARGET_IS_SPARC64 && (sp & 1)) | |
c906108c | 1338 | sp += 2047; |
5af923b0 | 1339 | |
c906108c SS |
1340 | read_memory (sp, reg_temp, SPARC_INTREG_SIZE * 16); |
1341 | ||
1342 | /* Restore the out registers. | |
c5aa993b | 1343 | Among other things this writes the new stack pointer. */ |
73937e03 AC |
1344 | deprecated_write_register_bytes (REGISTER_BYTE (O0_REGNUM), raw_buffer, |
1345 | SPARC_INTREG_SIZE * 8); | |
c906108c | 1346 | |
73937e03 AC |
1347 | deprecated_write_register_bytes (REGISTER_BYTE (L0_REGNUM), reg_temp, |
1348 | SPARC_INTREG_SIZE * 16); | |
c906108c | 1349 | } |
5af923b0 MS |
1350 | |
1351 | if (!(GDB_TARGET_IS_SPARC64)) | |
1352 | if (fsr[PS_REGNUM]) | |
1353 | write_register (PS_REGNUM, | |
1354 | read_memory_integer (fsr[PS_REGNUM], | |
1355 | REGISTER_RAW_SIZE (PS_REGNUM))); | |
1356 | ||
1357 | if (fsr[Y_REGNUM]) | |
1358 | write_register (Y_REGNUM, | |
1359 | read_memory_integer (fsr[Y_REGNUM], | |
1360 | REGISTER_RAW_SIZE (Y_REGNUM))); | |
1361 | if (fsr[PC_REGNUM]) | |
c906108c SS |
1362 | { |
1363 | /* Explicitly specified PC (and maybe NPC) -- just restore them. */ | |
5af923b0 MS |
1364 | write_register (PC_REGNUM, |
1365 | read_memory_integer (fsr[PC_REGNUM], | |
1366 | REGISTER_RAW_SIZE (PC_REGNUM))); | |
1367 | if (fsr[NPC_REGNUM]) | |
c906108c | 1368 | write_register (NPC_REGNUM, |
5af923b0 MS |
1369 | read_memory_integer (fsr[NPC_REGNUM], |
1370 | REGISTER_RAW_SIZE (NPC_REGNUM))); | |
c906108c | 1371 | } |
da50a4b7 | 1372 | else if (get_frame_extra_info (frame)->flat) |
c906108c | 1373 | { |
da50a4b7 | 1374 | if (get_frame_extra_info (frame)->pc_addr) |
c906108c | 1375 | pc = PC_ADJUST ((CORE_ADDR) |
da50a4b7 | 1376 | read_memory_integer (get_frame_extra_info (frame)->pc_addr, |
c906108c SS |
1377 | REGISTER_RAW_SIZE (PC_REGNUM))); |
1378 | else | |
1379 | { | |
1380 | /* I think this happens only in the innermost frame, if so then | |
1381 | it is a complicated way of saying | |
1382 | "pc = read_register (O7_REGNUM);". */ | |
ac2adee5 AC |
1383 | ULONGEST tmp; |
1384 | frame_read_unsigned_register (frame, O7_REGNUM, &tmp); | |
1385 | pc = PC_ADJUST (tmp); | |
c906108c SS |
1386 | } |
1387 | ||
c5aa993b | 1388 | write_register (PC_REGNUM, pc); |
c906108c SS |
1389 | write_register (NPC_REGNUM, pc + 4); |
1390 | } | |
5af923b0 | 1391 | else if (fsr[I7_REGNUM]) |
c906108c SS |
1392 | { |
1393 | /* Return address in %i7 -- adjust it, then restore PC and NPC from it */ | |
5af923b0 | 1394 | pc = PC_ADJUST ((CORE_ADDR) read_memory_integer (fsr[I7_REGNUM], |
c906108c | 1395 | SPARC_INTREG_SIZE)); |
c5aa993b | 1396 | write_register (PC_REGNUM, pc); |
c906108c SS |
1397 | write_register (NPC_REGNUM, pc + 4); |
1398 | } | |
1399 | flush_cached_frames (); | |
1400 | } | |
1401 | ||
1402 | /* On the Sun 4 under SunOS, the compile will leave a fake insn which | |
1403 | encodes the structure size being returned. If we detect such | |
1404 | a fake insn, step past it. */ | |
1405 | ||
1406 | CORE_ADDR | |
fba45db2 | 1407 | sparc_pc_adjust (CORE_ADDR pc) |
c906108c SS |
1408 | { |
1409 | unsigned long insn; | |
1410 | char buf[4]; | |
1411 | int err; | |
1412 | ||
1413 | err = target_read_memory (pc + 8, buf, 4); | |
1414 | insn = extract_unsigned_integer (buf, 4); | |
1415 | if ((err == 0) && (insn & 0xffc00000) == 0) | |
c5aa993b | 1416 | return pc + 12; |
c906108c | 1417 | else |
c5aa993b | 1418 | return pc + 8; |
c906108c SS |
1419 | } |
1420 | ||
1421 | /* If pc is in a shared library trampoline, return its target. | |
1422 | The SunOs 4.x linker rewrites the jump table entries for PIC | |
1423 | compiled modules in the main executable to bypass the dynamic linker | |
1424 | with jumps of the form | |
c5aa993b JM |
1425 | sethi %hi(addr),%g1 |
1426 | jmp %g1+%lo(addr) | |
c906108c SS |
1427 | and removes the corresponding jump table relocation entry in the |
1428 | dynamic relocations. | |
1429 | find_solib_trampoline_target relies on the presence of the jump | |
1430 | table relocation entry, so we have to detect these jump instructions | |
1431 | by hand. */ | |
1432 | ||
1433 | CORE_ADDR | |
fba45db2 | 1434 | sunos4_skip_trampoline_code (CORE_ADDR pc) |
c906108c SS |
1435 | { |
1436 | unsigned long insn1; | |
1437 | char buf[4]; | |
1438 | int err; | |
1439 | ||
1440 | err = target_read_memory (pc, buf, 4); | |
1441 | insn1 = extract_unsigned_integer (buf, 4); | |
1442 | if (err == 0 && (insn1 & 0xffc00000) == 0x03000000) | |
1443 | { | |
1444 | unsigned long insn2; | |
1445 | ||
1446 | err = target_read_memory (pc + 4, buf, 4); | |
1447 | insn2 = extract_unsigned_integer (buf, 4); | |
1448 | if (err == 0 && (insn2 & 0xffffe000) == 0x81c06000) | |
1449 | { | |
1450 | CORE_ADDR target_pc = (insn1 & 0x3fffff) << 10; | |
1451 | int delta = insn2 & 0x1fff; | |
1452 | ||
1453 | /* Sign extend the displacement. */ | |
1454 | if (delta & 0x1000) | |
1455 | delta |= ~0x1fff; | |
1456 | return target_pc + delta; | |
1457 | } | |
1458 | } | |
1459 | return find_solib_trampoline_target (pc); | |
1460 | } | |
1461 | \f | |
c5aa993b | 1462 | #ifdef USE_PROC_FS /* Target dependent support for /proc */ |
9846de1b | 1463 | /* *INDENT-OFF* */ |
c906108c SS |
1464 | /* The /proc interface divides the target machine's register set up into |
1465 | two different sets, the general register set (gregset) and the floating | |
1466 | point register set (fpregset). For each set, there is an ioctl to get | |
1467 | the current register set and another ioctl to set the current values. | |
1468 | ||
1469 | The actual structure passed through the ioctl interface is, of course, | |
1470 | naturally machine dependent, and is different for each set of registers. | |
1471 | For the sparc for example, the general register set is typically defined | |
1472 | by: | |
1473 | ||
1474 | typedef int gregset_t[38]; | |
1475 | ||
1476 | #define R_G0 0 | |
1477 | ... | |
1478 | #define R_TBR 37 | |
1479 | ||
1480 | and the floating point set by: | |
1481 | ||
1482 | typedef struct prfpregset { | |
1483 | union { | |
1484 | u_long pr_regs[32]; | |
1485 | double pr_dregs[16]; | |
1486 | } pr_fr; | |
1487 | void * pr_filler; | |
1488 | u_long pr_fsr; | |
1489 | u_char pr_qcnt; | |
1490 | u_char pr_q_entrysize; | |
1491 | u_char pr_en; | |
1492 | u_long pr_q[64]; | |
1493 | } prfpregset_t; | |
1494 | ||
1495 | These routines provide the packing and unpacking of gregset_t and | |
1496 | fpregset_t formatted data. | |
1497 | ||
1498 | */ | |
9846de1b | 1499 | /* *INDENT-ON* */ |
c906108c SS |
1500 | |
1501 | /* Given a pointer to a general register set in /proc format (gregset_t *), | |
1502 | unpack the register contents and supply them as gdb's idea of the current | |
1503 | register values. */ | |
1504 | ||
1505 | void | |
fba45db2 | 1506 | supply_gregset (gdb_gregset_t *gregsetp) |
c906108c | 1507 | { |
5af923b0 MS |
1508 | prgreg_t *regp = (prgreg_t *) gregsetp; |
1509 | int regi, offset = 0; | |
1510 | ||
1511 | /* If the host is 64-bit sparc, but the target is 32-bit sparc, | |
1512 | then the gregset may contain 64-bit ints while supply_register | |
1513 | is expecting 32-bit ints. Compensate. */ | |
1514 | if (sizeof (regp[0]) == 8 && SPARC_INTREG_SIZE == 4) | |
1515 | offset = 4; | |
c906108c SS |
1516 | |
1517 | /* GDB register numbers for Gn, On, Ln, In all match /proc reg numbers. */ | |
5af923b0 | 1518 | /* FIXME MVS: assumes the order of the first 32 elements... */ |
c5aa993b | 1519 | for (regi = G0_REGNUM; regi <= I7_REGNUM; regi++) |
c906108c | 1520 | { |
5af923b0 | 1521 | supply_register (regi, ((char *) (regp + regi)) + offset); |
c906108c SS |
1522 | } |
1523 | ||
1524 | /* These require a bit more care. */ | |
5af923b0 MS |
1525 | supply_register (PC_REGNUM, ((char *) (regp + R_PC)) + offset); |
1526 | supply_register (NPC_REGNUM, ((char *) (regp + R_nPC)) + offset); | |
1527 | supply_register (Y_REGNUM, ((char *) (regp + R_Y)) + offset); | |
1528 | ||
1529 | if (GDB_TARGET_IS_SPARC64) | |
1530 | { | |
1531 | #ifdef R_CCR | |
1532 | supply_register (CCR_REGNUM, ((char *) (regp + R_CCR)) + offset); | |
1533 | #else | |
1534 | supply_register (CCR_REGNUM, NULL); | |
1535 | #endif | |
1536 | #ifdef R_FPRS | |
1537 | supply_register (FPRS_REGNUM, ((char *) (regp + R_FPRS)) + offset); | |
1538 | #else | |
1539 | supply_register (FPRS_REGNUM, NULL); | |
1540 | #endif | |
1541 | #ifdef R_ASI | |
1542 | supply_register (ASI_REGNUM, ((char *) (regp + R_ASI)) + offset); | |
1543 | #else | |
1544 | supply_register (ASI_REGNUM, NULL); | |
1545 | #endif | |
1546 | } | |
1547 | else /* sparc32 */ | |
1548 | { | |
1549 | #ifdef R_PS | |
1550 | supply_register (PS_REGNUM, ((char *) (regp + R_PS)) + offset); | |
1551 | #else | |
1552 | supply_register (PS_REGNUM, NULL); | |
1553 | #endif | |
1554 | ||
1555 | /* For 64-bit hosts, R_WIM and R_TBR may not be defined. | |
1556 | Steal R_ASI and R_FPRS, and hope for the best! */ | |
1557 | ||
1558 | #if !defined (R_WIM) && defined (R_ASI) | |
1559 | #define R_WIM R_ASI | |
1560 | #endif | |
1561 | ||
1562 | #if !defined (R_TBR) && defined (R_FPRS) | |
1563 | #define R_TBR R_FPRS | |
1564 | #endif | |
1565 | ||
1566 | #if defined (R_WIM) | |
1567 | supply_register (WIM_REGNUM, ((char *) (regp + R_WIM)) + offset); | |
1568 | #else | |
1569 | supply_register (WIM_REGNUM, NULL); | |
1570 | #endif | |
1571 | ||
1572 | #if defined (R_TBR) | |
1573 | supply_register (TBR_REGNUM, ((char *) (regp + R_TBR)) + offset); | |
1574 | #else | |
1575 | supply_register (TBR_REGNUM, NULL); | |
1576 | #endif | |
1577 | } | |
c906108c SS |
1578 | |
1579 | /* Fill inaccessible registers with zero. */ | |
5af923b0 MS |
1580 | if (GDB_TARGET_IS_SPARC64) |
1581 | { | |
1582 | /* | |
1583 | * don't know how to get value of any of the following: | |
1584 | */ | |
1585 | supply_register (VER_REGNUM, NULL); | |
1586 | supply_register (TICK_REGNUM, NULL); | |
1587 | supply_register (PIL_REGNUM, NULL); | |
1588 | supply_register (PSTATE_REGNUM, NULL); | |
1589 | supply_register (TSTATE_REGNUM, NULL); | |
1590 | supply_register (TBA_REGNUM, NULL); | |
1591 | supply_register (TL_REGNUM, NULL); | |
1592 | supply_register (TT_REGNUM, NULL); | |
1593 | supply_register (TPC_REGNUM, NULL); | |
1594 | supply_register (TNPC_REGNUM, NULL); | |
1595 | supply_register (WSTATE_REGNUM, NULL); | |
1596 | supply_register (CWP_REGNUM, NULL); | |
1597 | supply_register (CANSAVE_REGNUM, NULL); | |
1598 | supply_register (CANRESTORE_REGNUM, NULL); | |
1599 | supply_register (CLEANWIN_REGNUM, NULL); | |
1600 | supply_register (OTHERWIN_REGNUM, NULL); | |
1601 | supply_register (ASR16_REGNUM, NULL); | |
1602 | supply_register (ASR17_REGNUM, NULL); | |
1603 | supply_register (ASR18_REGNUM, NULL); | |
1604 | supply_register (ASR19_REGNUM, NULL); | |
1605 | supply_register (ASR20_REGNUM, NULL); | |
1606 | supply_register (ASR21_REGNUM, NULL); | |
1607 | supply_register (ASR22_REGNUM, NULL); | |
1608 | supply_register (ASR23_REGNUM, NULL); | |
1609 | supply_register (ASR24_REGNUM, NULL); | |
1610 | supply_register (ASR25_REGNUM, NULL); | |
1611 | supply_register (ASR26_REGNUM, NULL); | |
1612 | supply_register (ASR27_REGNUM, NULL); | |
1613 | supply_register (ASR28_REGNUM, NULL); | |
1614 | supply_register (ASR29_REGNUM, NULL); | |
1615 | supply_register (ASR30_REGNUM, NULL); | |
1616 | supply_register (ASR31_REGNUM, NULL); | |
1617 | supply_register (ICC_REGNUM, NULL); | |
1618 | supply_register (XCC_REGNUM, NULL); | |
1619 | } | |
1620 | else | |
1621 | { | |
1622 | supply_register (CPS_REGNUM, NULL); | |
1623 | } | |
c906108c SS |
1624 | } |
1625 | ||
1626 | void | |
fba45db2 | 1627 | fill_gregset (gdb_gregset_t *gregsetp, int regno) |
c906108c | 1628 | { |
5af923b0 MS |
1629 | prgreg_t *regp = (prgreg_t *) gregsetp; |
1630 | int regi, offset = 0; | |
1631 | ||
1632 | /* If the host is 64-bit sparc, but the target is 32-bit sparc, | |
1633 | then the gregset may contain 64-bit ints while supply_register | |
1634 | is expecting 32-bit ints. Compensate. */ | |
1635 | if (sizeof (regp[0]) == 8 && SPARC_INTREG_SIZE == 4) | |
1636 | offset = 4; | |
c906108c | 1637 | |
c5aa993b | 1638 | for (regi = 0; regi <= R_I7; regi++) |
5af923b0 | 1639 | if ((regno == -1) || (regno == regi)) |
4caf0990 | 1640 | deprecated_read_register_gen (regi, (char *) (regp + regi) + offset); |
5af923b0 | 1641 | |
c906108c | 1642 | if ((regno == -1) || (regno == PC_REGNUM)) |
4caf0990 | 1643 | deprecated_read_register_gen (PC_REGNUM, (char *) (regp + R_PC) + offset); |
5af923b0 | 1644 | |
c906108c | 1645 | if ((regno == -1) || (regno == NPC_REGNUM)) |
4caf0990 | 1646 | deprecated_read_register_gen (NPC_REGNUM, (char *) (regp + R_nPC) + offset); |
5af923b0 MS |
1647 | |
1648 | if ((regno == -1) || (regno == Y_REGNUM)) | |
4caf0990 | 1649 | deprecated_read_register_gen (Y_REGNUM, (char *) (regp + R_Y) + offset); |
5af923b0 MS |
1650 | |
1651 | if (GDB_TARGET_IS_SPARC64) | |
c906108c | 1652 | { |
5af923b0 MS |
1653 | #ifdef R_CCR |
1654 | if (regno == -1 || regno == CCR_REGNUM) | |
4caf0990 | 1655 | deprecated_read_register_gen (CCR_REGNUM, ((char *) (regp + R_CCR)) + offset); |
5af923b0 MS |
1656 | #endif |
1657 | #ifdef R_FPRS | |
1658 | if (regno == -1 || regno == FPRS_REGNUM) | |
4caf0990 | 1659 | deprecated_read_register_gen (FPRS_REGNUM, ((char *) (regp + R_FPRS)) + offset); |
5af923b0 MS |
1660 | #endif |
1661 | #ifdef R_ASI | |
1662 | if (regno == -1 || regno == ASI_REGNUM) | |
4caf0990 | 1663 | deprecated_read_register_gen (ASI_REGNUM, ((char *) (regp + R_ASI)) + offset); |
5af923b0 | 1664 | #endif |
c906108c | 1665 | } |
5af923b0 | 1666 | else /* sparc32 */ |
c906108c | 1667 | { |
5af923b0 MS |
1668 | #ifdef R_PS |
1669 | if (regno == -1 || regno == PS_REGNUM) | |
4caf0990 | 1670 | deprecated_read_register_gen (PS_REGNUM, ((char *) (regp + R_PS)) + offset); |
5af923b0 MS |
1671 | #endif |
1672 | ||
1673 | /* For 64-bit hosts, R_WIM and R_TBR may not be defined. | |
1674 | Steal R_ASI and R_FPRS, and hope for the best! */ | |
1675 | ||
1676 | #if !defined (R_WIM) && defined (R_ASI) | |
1677 | #define R_WIM R_ASI | |
1678 | #endif | |
1679 | ||
1680 | #if !defined (R_TBR) && defined (R_FPRS) | |
1681 | #define R_TBR R_FPRS | |
1682 | #endif | |
1683 | ||
1684 | #if defined (R_WIM) | |
1685 | if (regno == -1 || regno == WIM_REGNUM) | |
4caf0990 | 1686 | deprecated_read_register_gen (WIM_REGNUM, ((char *) (regp + R_WIM)) + offset); |
5af923b0 MS |
1687 | #else |
1688 | if (regno == -1 || regno == WIM_REGNUM) | |
4caf0990 | 1689 | deprecated_read_register_gen (WIM_REGNUM, NULL); |
5af923b0 MS |
1690 | #endif |
1691 | ||
1692 | #if defined (R_TBR) | |
1693 | if (regno == -1 || regno == TBR_REGNUM) | |
4caf0990 | 1694 | deprecated_read_register_gen (TBR_REGNUM, ((char *) (regp + R_TBR)) + offset); |
5af923b0 MS |
1695 | #else |
1696 | if (regno == -1 || regno == TBR_REGNUM) | |
4caf0990 | 1697 | deprecated_read_register_gen (TBR_REGNUM, NULL); |
5af923b0 | 1698 | #endif |
c906108c SS |
1699 | } |
1700 | } | |
1701 | ||
c906108c | 1702 | /* Given a pointer to a floating point register set in /proc format |
c5aa993b JM |
1703 | (fpregset_t *), unpack the register contents and supply them as gdb's |
1704 | idea of the current floating point register values. */ | |
c906108c | 1705 | |
c5aa993b | 1706 | void |
fba45db2 | 1707 | supply_fpregset (gdb_fpregset_t *fpregsetp) |
c906108c SS |
1708 | { |
1709 | register int regi; | |
1710 | char *from; | |
c5aa993b | 1711 | |
5af923b0 | 1712 | if (!SPARC_HAS_FPU) |
60054393 MS |
1713 | return; |
1714 | ||
c5aa993b | 1715 | for (regi = FP0_REGNUM; regi < FP_MAX_REGNUM; regi++) |
c906108c | 1716 | { |
c5aa993b | 1717 | from = (char *) &fpregsetp->pr_fr.pr_regs[regi - FP0_REGNUM]; |
c906108c SS |
1718 | supply_register (regi, from); |
1719 | } | |
5af923b0 MS |
1720 | |
1721 | if (GDB_TARGET_IS_SPARC64) | |
1722 | { | |
1723 | /* | |
1724 | * don't know how to get value of the following. | |
1725 | */ | |
1726 | supply_register (FSR_REGNUM, NULL); /* zero it out for now */ | |
1727 | supply_register (FCC0_REGNUM, NULL); | |
1728 | supply_register (FCC1_REGNUM, NULL); /* don't know how to get value */ | |
1729 | supply_register (FCC2_REGNUM, NULL); /* don't know how to get value */ | |
1730 | supply_register (FCC3_REGNUM, NULL); /* don't know how to get value */ | |
1731 | } | |
1732 | else | |
1733 | { | |
1734 | supply_register (FPS_REGNUM, (char *) &(fpregsetp->pr_fsr)); | |
1735 | } | |
c906108c SS |
1736 | } |
1737 | ||
1738 | /* Given a pointer to a floating point register set in /proc format | |
c5aa993b JM |
1739 | (fpregset_t *), update the register specified by REGNO from gdb's idea |
1740 | of the current floating point register set. If REGNO is -1, update | |
1741 | them all. */ | |
5af923b0 | 1742 | /* This will probably need some changes for sparc64. */ |
c906108c SS |
1743 | |
1744 | void | |
fba45db2 | 1745 | fill_fpregset (gdb_fpregset_t *fpregsetp, int regno) |
c906108c SS |
1746 | { |
1747 | int regi; | |
1748 | char *to; | |
1749 | char *from; | |
1750 | ||
5af923b0 | 1751 | if (!SPARC_HAS_FPU) |
60054393 MS |
1752 | return; |
1753 | ||
c5aa993b | 1754 | for (regi = FP0_REGNUM; regi < FP_MAX_REGNUM; regi++) |
c906108c SS |
1755 | { |
1756 | if ((regno == -1) || (regno == regi)) | |
1757 | { | |
524d7c18 | 1758 | from = (char *) &deprecated_registers[REGISTER_BYTE (regi)]; |
c5aa993b | 1759 | to = (char *) &fpregsetp->pr_fr.pr_regs[regi - FP0_REGNUM]; |
c906108c SS |
1760 | memcpy (to, from, REGISTER_RAW_SIZE (regi)); |
1761 | } | |
1762 | } | |
5af923b0 MS |
1763 | |
1764 | if (!(GDB_TARGET_IS_SPARC64)) /* FIXME: does Sparc64 have this register? */ | |
1765 | if ((regno == -1) || (regno == FPS_REGNUM)) | |
1766 | { | |
524d7c18 | 1767 | from = (char *)&deprecated_registers[REGISTER_BYTE (FPS_REGNUM)]; |
5af923b0 MS |
1768 | to = (char *) &fpregsetp->pr_fsr; |
1769 | memcpy (to, from, REGISTER_RAW_SIZE (FPS_REGNUM)); | |
1770 | } | |
c906108c SS |
1771 | } |
1772 | ||
c5aa993b | 1773 | #endif /* USE_PROC_FS */ |
c906108c | 1774 | |
a48442a0 RE |
1775 | /* Because of Multi-arch, GET_LONGJMP_TARGET is always defined. So test |
1776 | for a definition of JB_PC. */ | |
1777 | #ifdef JB_PC | |
c906108c SS |
1778 | |
1779 | /* Figure out where the longjmp will land. We expect that we have just entered | |
1780 | longjmp and haven't yet setup the stack frame, so the args are still in the | |
1781 | output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we | |
1782 | extract the pc (JB_PC) that we will land at. The pc is copied into ADDR. | |
1783 | This routine returns true on success */ | |
1784 | ||
1785 | int | |
fba45db2 | 1786 | get_longjmp_target (CORE_ADDR *pc) |
c906108c SS |
1787 | { |
1788 | CORE_ADDR jb_addr; | |
1789 | #define LONGJMP_TARGET_SIZE 4 | |
1790 | char buf[LONGJMP_TARGET_SIZE]; | |
1791 | ||
1792 | jb_addr = read_register (O0_REGNUM); | |
1793 | ||
1794 | if (target_read_memory (jb_addr + JB_PC * JB_ELEMENT_SIZE, buf, | |
1795 | LONGJMP_TARGET_SIZE)) | |
1796 | return 0; | |
1797 | ||
7c0b4a20 | 1798 | *pc = extract_unsigned_integer (buf, LONGJMP_TARGET_SIZE); |
c906108c SS |
1799 | |
1800 | return 1; | |
1801 | } | |
1802 | #endif /* GET_LONGJMP_TARGET */ | |
1803 | \f | |
1804 | #ifdef STATIC_TRANSFORM_NAME | |
1805 | /* SunPRO (3.0 at least), encodes the static variables. This is not | |
1806 | related to C++ mangling, it is done for C too. */ | |
1807 | ||
1808 | char * | |
fba45db2 | 1809 | sunpro_static_transform_name (char *name) |
c906108c SS |
1810 | { |
1811 | char *p; | |
1812 | if (name[0] == '$') | |
1813 | { | |
1814 | /* For file-local statics there will be a dollar sign, a bunch | |
c5aa993b JM |
1815 | of junk (the contents of which match a string given in the |
1816 | N_OPT), a period and the name. For function-local statics | |
1817 | there will be a bunch of junk (which seems to change the | |
1818 | second character from 'A' to 'B'), a period, the name of the | |
1819 | function, and the name. So just skip everything before the | |
1820 | last period. */ | |
c906108c SS |
1821 | p = strrchr (name, '.'); |
1822 | if (p != NULL) | |
1823 | name = p + 1; | |
1824 | } | |
1825 | return name; | |
1826 | } | |
1827 | #endif /* STATIC_TRANSFORM_NAME */ | |
1828 | \f | |
1829 | ||
1830 | /* Utilities for printing registers. | |
1831 | Page numbers refer to the SPARC Architecture Manual. */ | |
1832 | ||
5af923b0 | 1833 | static void dump_ccreg (char *, int); |
c906108c SS |
1834 | |
1835 | static void | |
fba45db2 | 1836 | dump_ccreg (char *reg, int val) |
c906108c SS |
1837 | { |
1838 | /* page 41 */ | |
1839 | printf_unfiltered ("%s:%s,%s,%s,%s", reg, | |
c5aa993b JM |
1840 | val & 8 ? "N" : "NN", |
1841 | val & 4 ? "Z" : "NZ", | |
1842 | val & 2 ? "O" : "NO", | |
5af923b0 | 1843 | val & 1 ? "C" : "NC"); |
c906108c SS |
1844 | } |
1845 | ||
1846 | static char * | |
fba45db2 | 1847 | decode_asi (int val) |
c906108c SS |
1848 | { |
1849 | /* page 72 */ | |
1850 | switch (val) | |
1851 | { | |
c5aa993b JM |
1852 | case 4: |
1853 | return "ASI_NUCLEUS"; | |
1854 | case 0x0c: | |
1855 | return "ASI_NUCLEUS_LITTLE"; | |
1856 | case 0x10: | |
1857 | return "ASI_AS_IF_USER_PRIMARY"; | |
1858 | case 0x11: | |
1859 | return "ASI_AS_IF_USER_SECONDARY"; | |
1860 | case 0x18: | |
1861 | return "ASI_AS_IF_USER_PRIMARY_LITTLE"; | |
1862 | case 0x19: | |
1863 | return "ASI_AS_IF_USER_SECONDARY_LITTLE"; | |
1864 | case 0x80: | |
1865 | return "ASI_PRIMARY"; | |
1866 | case 0x81: | |
1867 | return "ASI_SECONDARY"; | |
1868 | case 0x82: | |
1869 | return "ASI_PRIMARY_NOFAULT"; | |
1870 | case 0x83: | |
1871 | return "ASI_SECONDARY_NOFAULT"; | |
1872 | case 0x88: | |
1873 | return "ASI_PRIMARY_LITTLE"; | |
1874 | case 0x89: | |
1875 | return "ASI_SECONDARY_LITTLE"; | |
1876 | case 0x8a: | |
1877 | return "ASI_PRIMARY_NOFAULT_LITTLE"; | |
1878 | case 0x8b: | |
1879 | return "ASI_SECONDARY_NOFAULT_LITTLE"; | |
1880 | default: | |
1881 | return NULL; | |
c906108c SS |
1882 | } |
1883 | } | |
1884 | ||
867f3898 | 1885 | /* Pretty print various registers. */ |
c906108c SS |
1886 | /* FIXME: Would be nice if this did some fancy things for 32 bit sparc. */ |
1887 | ||
87647bb0 | 1888 | static void |
fba45db2 | 1889 | sparc_print_register_hook (int regno) |
c906108c SS |
1890 | { |
1891 | ULONGEST val; | |
1892 | ||
1893 | /* Handle double/quad versions of lower 32 fp regs. */ | |
1894 | if (regno >= FP0_REGNUM && regno < FP0_REGNUM + 32 | |
1895 | && (regno & 1) == 0) | |
1896 | { | |
1897 | char value[16]; | |
1898 | ||
6e7f8b9c AC |
1899 | if (frame_register_read (deprecated_selected_frame, regno, value) |
1900 | && frame_register_read (deprecated_selected_frame, regno + 1, value + 4)) | |
c906108c SS |
1901 | { |
1902 | printf_unfiltered ("\t"); | |
1903 | print_floating (value, builtin_type_double, gdb_stdout); | |
1904 | } | |
c5aa993b | 1905 | #if 0 /* FIXME: gdb doesn't handle long doubles */ |
c906108c SS |
1906 | if ((regno & 3) == 0) |
1907 | { | |
6e7f8b9c AC |
1908 | if (frame_register_read (deprecated_selected_frame, regno + 2, value + 8) |
1909 | && frame_register_read (deprecated_selected_frame, regno + 3, value + 12)) | |
c906108c SS |
1910 | { |
1911 | printf_unfiltered ("\t"); | |
1912 | print_floating (value, builtin_type_long_double, gdb_stdout); | |
1913 | } | |
1914 | } | |
1915 | #endif | |
1916 | return; | |
1917 | } | |
1918 | ||
c5aa993b | 1919 | #if 0 /* FIXME: gdb doesn't handle long doubles */ |
c906108c SS |
1920 | /* Print upper fp regs as long double if appropriate. */ |
1921 | if (regno >= FP0_REGNUM + 32 && regno < FP_MAX_REGNUM | |
c5aa993b JM |
1922 | /* We test for even numbered regs and not a multiple of 4 because |
1923 | the upper fp regs are recorded as doubles. */ | |
c906108c SS |
1924 | && (regno & 1) == 0) |
1925 | { | |
1926 | char value[16]; | |
1927 | ||
6e7f8b9c AC |
1928 | if (frame_register_read (deprecated_selected_frame, regno, value) |
1929 | && frame_register_read (deprecated_selected_frame, regno + 1, value + 8)) | |
c906108c SS |
1930 | { |
1931 | printf_unfiltered ("\t"); | |
1932 | print_floating (value, builtin_type_long_double, gdb_stdout); | |
1933 | } | |
1934 | return; | |
1935 | } | |
1936 | #endif | |
1937 | ||
1938 | /* FIXME: Some of these are priviledged registers. | |
1939 | Not sure how they should be handled. */ | |
1940 | ||
1941 | #define BITS(n, mask) ((int) (((val) >> (n)) & (mask))) | |
1942 | ||
1943 | val = read_register (regno); | |
1944 | ||
1945 | /* pages 40 - 60 */ | |
5af923b0 MS |
1946 | if (GDB_TARGET_IS_SPARC64) |
1947 | switch (regno) | |
c906108c | 1948 | { |
5af923b0 MS |
1949 | case CCR_REGNUM: |
1950 | printf_unfiltered ("\t"); | |
1951 | dump_ccreg ("xcc", val >> 4); | |
1952 | printf_unfiltered (", "); | |
1953 | dump_ccreg ("icc", val & 15); | |
c906108c | 1954 | break; |
5af923b0 MS |
1955 | case FPRS_REGNUM: |
1956 | printf ("\tfef:%d, du:%d, dl:%d", | |
1957 | BITS (2, 1), BITS (1, 1), BITS (0, 1)); | |
c906108c | 1958 | break; |
5af923b0 MS |
1959 | case FSR_REGNUM: |
1960 | { | |
1961 | static char *fcc[4] = | |
1962 | {"=", "<", ">", "?"}; | |
1963 | static char *rd[4] = | |
1964 | {"N", "0", "+", "-"}; | |
1965 | /* Long, but I'd rather leave it as is and use a wide screen. */ | |
1966 | printf_filtered ("\t0:%s, 1:%s, 2:%s, 3:%s, rd:%s, tem:%d, ", | |
1967 | fcc[BITS (10, 3)], fcc[BITS (32, 3)], | |
1968 | fcc[BITS (34, 3)], fcc[BITS (36, 3)], | |
1969 | rd[BITS (30, 3)], BITS (23, 31)); | |
1970 | printf_filtered ("ns:%d, ver:%d, ftt:%d, qne:%d, aexc:%d, cexc:%d", | |
1971 | BITS (22, 1), BITS (17, 7), BITS (14, 7), | |
1972 | BITS (13, 1), BITS (5, 31), BITS (0, 31)); | |
1973 | break; | |
1974 | } | |
1975 | case ASI_REGNUM: | |
1976 | { | |
1977 | char *asi = decode_asi (val); | |
1978 | if (asi != NULL) | |
1979 | printf ("\t%s", asi); | |
1980 | break; | |
1981 | } | |
1982 | case VER_REGNUM: | |
1983 | printf ("\tmanuf:%d, impl:%d, mask:%d, maxtl:%d, maxwin:%d", | |
1984 | BITS (48, 0xffff), BITS (32, 0xffff), | |
1985 | BITS (24, 0xff), BITS (8, 0xff), BITS (0, 31)); | |
1986 | break; | |
1987 | case PSTATE_REGNUM: | |
1988 | { | |
1989 | static char *mm[4] = | |
1990 | {"tso", "pso", "rso", "?"}; | |
1991 | printf_filtered ("\tcle:%d, tle:%d, mm:%s, red:%d, ", | |
1992 | BITS (9, 1), BITS (8, 1), | |
1993 | mm[BITS (6, 3)], BITS (5, 1)); | |
1994 | printf_filtered ("pef:%d, am:%d, priv:%d, ie:%d, ag:%d", | |
1995 | BITS (4, 1), BITS (3, 1), BITS (2, 1), | |
1996 | BITS (1, 1), BITS (0, 1)); | |
1997 | break; | |
1998 | } | |
1999 | case TSTATE_REGNUM: | |
2000 | /* FIXME: print all 4? */ | |
2001 | break; | |
2002 | case TT_REGNUM: | |
2003 | /* FIXME: print all 4? */ | |
2004 | break; | |
2005 | case TPC_REGNUM: | |
2006 | /* FIXME: print all 4? */ | |
2007 | break; | |
2008 | case TNPC_REGNUM: | |
2009 | /* FIXME: print all 4? */ | |
2010 | break; | |
2011 | case WSTATE_REGNUM: | |
2012 | printf ("\tother:%d, normal:%d", BITS (3, 7), BITS (0, 7)); | |
2013 | break; | |
2014 | case CWP_REGNUM: | |
2015 | printf ("\t%d", BITS (0, 31)); | |
2016 | break; | |
2017 | case CANSAVE_REGNUM: | |
2018 | printf ("\t%-2d before spill", BITS (0, 31)); | |
2019 | break; | |
2020 | case CANRESTORE_REGNUM: | |
2021 | printf ("\t%-2d before fill", BITS (0, 31)); | |
2022 | break; | |
2023 | case CLEANWIN_REGNUM: | |
2024 | printf ("\t%-2d before clean", BITS (0, 31)); | |
2025 | break; | |
2026 | case OTHERWIN_REGNUM: | |
2027 | printf ("\t%d", BITS (0, 31)); | |
c906108c SS |
2028 | break; |
2029 | } | |
5af923b0 MS |
2030 | else /* Sparc32 */ |
2031 | switch (regno) | |
c906108c | 2032 | { |
5af923b0 MS |
2033 | case PS_REGNUM: |
2034 | printf ("\ticc:%c%c%c%c, pil:%d, s:%d, ps:%d, et:%d, cwp:%d", | |
2035 | BITS (23, 1) ? 'N' : '-', BITS (22, 1) ? 'Z' : '-', | |
2036 | BITS (21, 1) ? 'V' : '-', BITS (20, 1) ? 'C' : '-', | |
2037 | BITS (8, 15), BITS (7, 1), BITS (6, 1), BITS (5, 1), | |
c906108c SS |
2038 | BITS (0, 31)); |
2039 | break; | |
5af923b0 MS |
2040 | case FPS_REGNUM: |
2041 | { | |
2042 | static char *fcc[4] = | |
2043 | {"=", "<", ">", "?"}; | |
2044 | static char *rd[4] = | |
2045 | {"N", "0", "+", "-"}; | |
2046 | /* Long, but I'd rather leave it as is and use a wide screen. */ | |
2047 | printf ("\trd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, " | |
2048 | "fcc:%s, aexc:%d, cexc:%d", | |
2049 | rd[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7), | |
2050 | BITS (14, 7), BITS (13, 1), fcc[BITS (10, 3)], BITS (5, 31), | |
2051 | BITS (0, 31)); | |
2052 | break; | |
2053 | } | |
c906108c SS |
2054 | } |
2055 | ||
c906108c SS |
2056 | #undef BITS |
2057 | } | |
87647bb0 AC |
2058 | |
2059 | static void | |
2060 | sparc_print_registers (struct gdbarch *gdbarch, | |
2061 | struct ui_file *file, | |
2062 | struct frame_info *frame, | |
2063 | int regnum, int print_all, | |
2064 | void (*print_register_hook) (int)) | |
2065 | { | |
2066 | int i; | |
2067 | const int numregs = NUM_REGS + NUM_PSEUDO_REGS; | |
0c92afe8 AC |
2068 | char raw_buffer[MAX_REGISTER_SIZE]; |
2069 | char virtual_buffer[MAX_REGISTER_SIZE]; | |
87647bb0 AC |
2070 | |
2071 | for (i = 0; i < numregs; i++) | |
2072 | { | |
2073 | /* Decide between printing all regs, non-float / vector regs, or | |
2074 | specific reg. */ | |
2075 | if (regnum == -1) | |
2076 | { | |
2077 | if (!print_all) | |
2078 | { | |
2079 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (i)) == TYPE_CODE_FLT) | |
2080 | continue; | |
2081 | if (TYPE_VECTOR (REGISTER_VIRTUAL_TYPE (i))) | |
2082 | continue; | |
2083 | } | |
2084 | } | |
2085 | else | |
2086 | { | |
2087 | if (i != regnum) | |
2088 | continue; | |
2089 | } | |
2090 | ||
2091 | /* If the register name is empty, it is undefined for this | |
2092 | processor, so don't display anything. */ | |
2093 | if (REGISTER_NAME (i) == NULL || *(REGISTER_NAME (i)) == '\0') | |
2094 | continue; | |
2095 | ||
2096 | fputs_filtered (REGISTER_NAME (i), file); | |
2097 | print_spaces_filtered (15 - strlen (REGISTER_NAME (i)), file); | |
2098 | ||
2099 | /* Get the data in raw format. */ | |
2100 | if (! frame_register_read (frame, i, raw_buffer)) | |
2101 | { | |
2102 | fprintf_filtered (file, "*value not available*\n"); | |
2103 | continue; | |
2104 | } | |
2105 | ||
bf7488d2 | 2106 | memcpy (virtual_buffer, raw_buffer, REGISTER_VIRTUAL_SIZE (i)); |
87647bb0 AC |
2107 | |
2108 | /* If virtual format is floating, print it that way, and in raw | |
2109 | hex. */ | |
2110 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (i)) == TYPE_CODE_FLT) | |
2111 | { | |
2112 | int j; | |
2113 | ||
2114 | val_print (REGISTER_VIRTUAL_TYPE (i), virtual_buffer, 0, 0, | |
2115 | file, 0, 1, 0, Val_pretty_default); | |
2116 | ||
2117 | fprintf_filtered (file, "\t(raw 0x"); | |
2118 | for (j = 0; j < REGISTER_RAW_SIZE (i); j++) | |
2119 | { | |
2120 | int idx; | |
2121 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2122 | idx = j; | |
2123 | else | |
2124 | idx = REGISTER_RAW_SIZE (i) - 1 - j; | |
2125 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]); | |
2126 | } | |
2127 | fprintf_filtered (file, ")"); | |
2128 | } | |
2129 | else | |
2130 | { | |
2131 | /* Print the register in hex. */ | |
2132 | val_print (REGISTER_VIRTUAL_TYPE (i), virtual_buffer, 0, 0, | |
2133 | file, 'x', 1, 0, Val_pretty_default); | |
2134 | /* If not a vector register, print it also according to its | |
2135 | natural format. */ | |
2136 | if (TYPE_VECTOR (REGISTER_VIRTUAL_TYPE (i)) == 0) | |
2137 | { | |
2138 | fprintf_filtered (file, "\t"); | |
2139 | val_print (REGISTER_VIRTUAL_TYPE (i), virtual_buffer, 0, 0, | |
2140 | file, 0, 1, 0, Val_pretty_default); | |
2141 | } | |
2142 | } | |
2143 | ||
2144 | /* Some sparc specific info. */ | |
2145 | if (print_register_hook != NULL) | |
2146 | print_register_hook (i); | |
2147 | ||
2148 | fprintf_filtered (file, "\n"); | |
2149 | } | |
2150 | } | |
2151 | ||
2152 | static void | |
2153 | sparc_print_registers_info (struct gdbarch *gdbarch, | |
2154 | struct ui_file *file, | |
2155 | struct frame_info *frame, | |
2156 | int regnum, int print_all) | |
2157 | { | |
2158 | sparc_print_registers (gdbarch, file, frame, regnum, print_all, | |
2159 | sparc_print_register_hook); | |
2160 | } | |
2161 | ||
2162 | void | |
2163 | sparc_do_registers_info (int regnum, int all) | |
2164 | { | |
6e7f8b9c | 2165 | sparc_print_registers_info (current_gdbarch, gdb_stdout, deprecated_selected_frame, |
87647bb0 AC |
2166 | regnum, all); |
2167 | } | |
2168 | ||
f81824a9 AC |
2169 | #if 0 |
2170 | // OBSOLETE static void | |
2171 | // OBSOLETE sparclet_print_registers_info (struct gdbarch *gdbarch, | |
2172 | // OBSOLETE struct ui_file *file, | |
2173 | // OBSOLETE struct frame_info *frame, | |
2174 | // OBSOLETE int regnum, int print_all) | |
2175 | // OBSOLETE { | |
2176 | // OBSOLETE sparc_print_registers (gdbarch, file, frame, regnum, print_all, NULL); | |
2177 | // OBSOLETE } | |
2178 | // OBSOLETE | |
2179 | // OBSOLETE void | |
2180 | // OBSOLETE sparclet_do_registers_info (int regnum, int all) | |
2181 | // OBSOLETE { | |
2182 | // OBSOLETE sparclet_print_registers_info (current_gdbarch, gdb_stdout, | |
2183 | // OBSOLETE deprecated_selected_frame, regnum, all); | |
2184 | // OBSOLETE } | |
2185 | #endif | |
87647bb0 | 2186 | |
c906108c | 2187 | \f |
a78f21af | 2188 | static int |
fba45db2 | 2189 | gdb_print_insn_sparc (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
2190 | { |
2191 | /* It's necessary to override mach again because print_insn messes it up. */ | |
96baa820 | 2192 | info->mach = TARGET_ARCHITECTURE->mach; |
c906108c SS |
2193 | return print_insn_sparc (memaddr, info); |
2194 | } | |
2195 | \f | |
c906108c | 2196 | |
eb2c22dc MK |
2197 | #define SPARC_F0_REGNUM FP0_REGNUM /* %f0 */ |
2198 | #define SPARC_F1_REGNUM (FP0_REGNUM + 1)/* %f1 */ | |
2199 | #define SPARC_O0_REGNUM O0_REGNUM /* %o0 */ | |
2200 | #define SPARC_O1_REGNUM O1_REGNUM /* %o1 */ | |
2201 | ||
2202 | /* Push the arguments onto the stack and into the appropriate registers. */ | |
2203 | ||
2204 | static CORE_ADDR | |
2205 | sparc32_do_push_arguments (struct regcache *regcache, int nargs, | |
2206 | struct value **args, CORE_ADDR sp) | |
c906108c | 2207 | { |
eb2c22dc MK |
2208 | CORE_ADDR *addr; |
2209 | int size = 0; | |
2210 | int i; | |
2211 | ||
2212 | /* Structure, union and quad-precision arguments are passed by | |
2213 | reference. We allocate space for these arguments on the stack | |
2214 | and record their addresses in an array. Array elements for | |
2215 | arguments that are passed by value will be set to zero.*/ | |
2216 | addr = alloca (nargs * sizeof (CORE_ADDR)); | |
2217 | ||
2218 | for (i = nargs - 1; i >= 0; i--) | |
c906108c | 2219 | { |
eb2c22dc MK |
2220 | struct type *type = VALUE_ENCLOSING_TYPE (args[i]); |
2221 | enum type_code code = TYPE_CODE (type); | |
2222 | int len = TYPE_LENGTH (type); | |
2223 | ||
2224 | /* Push the contents of structure, union and quad-precision | |
2225 | arguments on the stack. */ | |
2226 | if (code == TYPE_CODE_STRUCT || code == TYPE_CODE_UNION || len > 8) | |
2227 | { | |
2228 | /* Keep the stack doubleword aligned. */ | |
2229 | sp -= (len + 7) & ~7; | |
2230 | write_memory (sp, VALUE_CONTENTS_ALL (args[i]), len); | |
2231 | addr[i] = sp; | |
2232 | size += 4; | |
2233 | } | |
2234 | else | |
2235 | { | |
2236 | addr[i] = 0; | |
2237 | size += (len > 4) ? 8 : 4; | |
2238 | } | |
2239 | } | |
2240 | ||
2241 | /* The needed space for outgoing arguments should be a multiple of 4. */ | |
2242 | gdb_assert (size % 4 == 0); | |
2243 | ||
2244 | /* Make sure we reserve space for the first six words of arguments | |
2245 | in the stack frame, even if we don't need them. */ | |
2246 | if (size < 24) | |
2247 | sp -= (24 - size); | |
2248 | ||
2249 | /* Make sure we end up with a doubleword aligned stack in the end. | |
2250 | Reserve an extra word if necessary in order to accomplish this. */ | |
2251 | if ((sp - size) % 8 == 0) | |
2252 | sp -= 4; | |
2253 | ||
2254 | /* Now push the arguments onto the stack. */ | |
2255 | for (i = nargs - 1; i >=0; i--) | |
c906108c | 2256 | { |
eb2c22dc MK |
2257 | char buf[8]; |
2258 | int len; | |
2259 | ||
2260 | if (addr[i]) | |
c906108c | 2261 | { |
eb2c22dc MK |
2262 | store_unsigned_integer (buf, 4, addr[i]); |
2263 | len = 4; | |
2264 | } | |
2265 | else | |
2266 | { | |
2267 | struct value *arg = args[i]; | |
2268 | ||
2269 | len = TYPE_LENGTH (VALUE_ENCLOSING_TYPE (arg)); | |
2270 | ||
2271 | /* Expand signed and unsigned bytes and halfwords as needed. */ | |
2272 | if (len < 4) | |
c906108c | 2273 | { |
eb2c22dc MK |
2274 | arg = value_cast (builtin_type_long, arg); |
2275 | len = 4; | |
c906108c | 2276 | } |
eb2c22dc MK |
2277 | else if (len > 4 && len < 8) |
2278 | { | |
2279 | arg = value_cast (builtin_type_long_long, arg); | |
2280 | len = 4; | |
2281 | } | |
2282 | ||
2283 | gdb_assert (len == 4 || len == 8); | |
2284 | memcpy (buf, VALUE_CONTENTS_ALL (arg), len); | |
2285 | } | |
2286 | ||
2287 | /* We always write the argument word on the stack. */ | |
2288 | sp -= len; | |
2289 | write_memory (sp, buf, len); | |
2290 | ||
2291 | /* If this argument occupies one of the first 6 words, write it | |
2292 | into the appropriate register too. */ | |
2293 | size -= len; | |
2294 | if (size < 24) | |
2295 | { | |
2296 | int regnum = SPARC_O0_REGNUM + (size / 4); | |
2297 | ||
2298 | regcache_cooked_write (regcache, regnum, buf); | |
2299 | if (len == 8 && size < 20) | |
2300 | regcache_cooked_write (regcache, regnum + 1, buf + 4); | |
c906108c | 2301 | } |
c906108c SS |
2302 | } |
2303 | ||
eb2c22dc MK |
2304 | /* Reserve space for the struct/union return value pointer. */ |
2305 | sp -= 4; | |
2306 | ||
2307 | /* Stack should be doubleword aligned at this point. */ | |
2308 | gdb_assert (sp % 8 == 0); | |
2309 | ||
2310 | /* Return the adjusted stack pointer. */ | |
2311 | return sp; | |
2312 | } | |
c906108c | 2313 | |
eb2c22dc MK |
2314 | /* The SPARC passes the arguments on the stack; arguments smaller |
2315 | than an int are promoted to an int. The first 6 words worth of | |
2316 | args are also passed in registers o0 - o5. */ | |
2317 | ||
2318 | CORE_ADDR | |
2319 | sparc32_push_arguments (int nargs, struct value **args, CORE_ADDR sp, | |
2320 | int struct_return, CORE_ADDR struct_addr) | |
2321 | { | |
2322 | sp = sparc32_do_push_arguments (current_regcache, nargs, args, sp); | |
2323 | ||
2324 | /* FIXME: kettenis/20030525: We don't let this function set the | |
2325 | struct/union return pointer just yet. */ | |
2326 | #if 0 | |
2327 | if (struct_return) | |
5af923b0 | 2328 | { |
eb2c22dc MK |
2329 | char buf[4]; |
2330 | ||
2331 | /* The space for the struct/union return value pointer has | |
2332 | already been reserved. */ | |
2333 | store_unsigned_integer (buf, 4, struct_addr); | |
2334 | write (sp, buf, 4); | |
5af923b0 | 2335 | } |
c906108c SS |
2336 | |
2337 | return sp; | |
eb2c22dc MK |
2338 | #else |
2339 | return sp + 4; | |
2340 | #endif | |
c906108c SS |
2341 | } |
2342 | ||
44b7b84e MK |
2343 | /* Extract from REGCACHE a function return value of type TYPE and copy |
2344 | that into VALBUF. | |
2345 | ||
2346 | Note that REGCACHE specifies the register values for the frame of | |
2347 | the calling function. This means that we need to fetch the value | |
2348 | form %o0 and %o1, which correspond to %i0 and %i1 in the frame of | |
2349 | the called function. */ | |
c906108c SS |
2350 | |
2351 | void | |
44b7b84e MK |
2352 | sparc32_extract_return_value (struct type *type, struct regcache *regcache, |
2353 | void *valbuf) | |
c906108c | 2354 | { |
44b7b84e MK |
2355 | int len = TYPE_LENGTH (type); |
2356 | char buf[8]; | |
c906108c SS |
2357 | |
2358 | if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU) | |
44b7b84e MK |
2359 | { |
2360 | if (len == 4 || len == 8) | |
2361 | { | |
2362 | regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf); | |
2363 | regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4); | |
2364 | memcpy (valbuf, buf, len); | |
2365 | return; | |
2366 | } | |
2367 | else | |
2368 | internal_error (__FILE__, __LINE__, "\ | |
2369 | Cannot extract floating-point return value of %d bytes long.", len); | |
2370 | } | |
2371 | ||
2372 | if (len <= 4) | |
2373 | { | |
2374 | regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); | |
2375 | memcpy (valbuf, buf + 4 - len, len); | |
2376 | } | |
2377 | else if (len <= 8) | |
2378 | { | |
2379 | regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); | |
2380 | regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4); | |
2381 | memcpy (valbuf, buf + 8 - len, len); | |
2382 | } | |
c906108c | 2383 | else |
44b7b84e MK |
2384 | internal_error (__FILE__, __LINE__, |
2385 | "Cannot extract return value of %d bytes long.", len); | |
c906108c SS |
2386 | } |
2387 | ||
44b7b84e MK |
2388 | /* Write into REGBUF a function return value VALBUF of type TYPE. */ |
2389 | ||
2390 | void | |
2391 | sparc32_store_return_value (struct type *type, struct regcache *regcache, | |
2392 | const void *valbuf) | |
2393 | { | |
2394 | int len = TYPE_LENGTH (type); | |
2395 | char buf[8]; | |
2396 | ||
2397 | if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU) | |
2398 | { | |
2399 | const char *buf = valbuf; | |
2400 | ||
2401 | if (len == 4) | |
2402 | { | |
2403 | regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf); | |
2404 | return; | |
2405 | } | |
2406 | else if (len == 8) | |
2407 | { | |
2408 | regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf); | |
2409 | regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4); | |
2410 | return; | |
2411 | } | |
2412 | else | |
2413 | internal_error (__FILE__, __LINE__, "\ | |
2414 | Cannot extract floating-point return value of %d bytes long.", len); | |
2415 | } | |
2416 | ||
2417 | /* Add leading zeros to the value. */ | |
2418 | memset (buf, 0, sizeof buf); | |
2419 | ||
2420 | if (len <= 4) | |
2421 | { | |
2422 | memcpy (buf + 4 - len, valbuf, len); | |
2423 | regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); | |
2424 | } | |
2425 | else if (len <= 8) | |
2426 | { | |
2427 | memcpy (buf + 8 - len, valbuf, len); | |
2428 | regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); | |
2429 | regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf); | |
2430 | } | |
2431 | else | |
2432 | internal_error (__FILE__, __LINE__, | |
2433 | "Cannot extract return value of %d bytes long.", len); | |
2434 | } | |
2435 | ||
2436 | /* Extract from REGCACHE the address in which a function should return | |
2437 | its structure value. */ | |
2438 | ||
2439 | CORE_ADDR | |
2440 | sparc_extract_struct_value_address (struct regcache *regcache) | |
2441 | { | |
2442 | ULONGEST addr; | |
2443 | ||
2444 | regcache_cooked_read_unsigned (regcache, SPARC_O0_REGNUM, &addr); | |
2445 | return addr; | |
2446 | } | |
c906108c | 2447 | |
44b7b84e | 2448 | /* FIXME: kettenis/2003/05/24: Still used for sparc64. */ |
c906108c | 2449 | |
a78f21af | 2450 | static void |
fba45db2 | 2451 | sparc_store_return_value (struct type *type, char *valbuf) |
c906108c SS |
2452 | { |
2453 | int regno; | |
d9d9c31f | 2454 | char buffer[MAX_REGISTER_SIZE]; |
c906108c SS |
2455 | |
2456 | if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU) | |
2457 | /* Floating-point values are returned in the register pair */ | |
2458 | /* formed by %f0 and %f1 (doubles are, anyway). */ | |
2459 | regno = FP0_REGNUM; | |
2460 | else | |
2461 | /* Other values are returned in register %o0. */ | |
2462 | regno = O0_REGNUM; | |
2463 | ||
2464 | /* Add leading zeros to the value. */ | |
c5aa993b | 2465 | if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (regno)) |
c906108c | 2466 | { |
5af923b0 | 2467 | memset (buffer, 0, REGISTER_RAW_SIZE (regno)); |
c5aa993b | 2468 | memcpy (buffer + REGISTER_RAW_SIZE (regno) - TYPE_LENGTH (type), valbuf, |
c906108c | 2469 | TYPE_LENGTH (type)); |
4caf0990 | 2470 | deprecated_write_register_gen (regno, buffer); |
c906108c SS |
2471 | } |
2472 | else | |
73937e03 AC |
2473 | deprecated_write_register_bytes (REGISTER_BYTE (regno), valbuf, |
2474 | TYPE_LENGTH (type)); | |
c906108c SS |
2475 | } |
2476 | ||
f81824a9 AC |
2477 | #if 0 |
2478 | // OBSOLETE extern void | |
2479 | // OBSOLETE sparclet_store_return_value (struct type *type, char *valbuf) | |
2480 | // OBSOLETE { | |
2481 | // OBSOLETE /* Other values are returned in register %o0. */ | |
2482 | // OBSOLETE deprecated_write_register_bytes (REGISTER_BYTE (O0_REGNUM), valbuf, | |
2483 | // OBSOLETE TYPE_LENGTH (type)); | |
2484 | // OBSOLETE } | |
2485 | #endif | |
5af923b0 MS |
2486 | |
2487 | ||
4eb8c7fc DM |
2488 | #ifndef CALL_DUMMY_CALL_OFFSET |
2489 | #define CALL_DUMMY_CALL_OFFSET \ | |
2490 | (gdbarch_tdep (current_gdbarch)->call_dummy_call_offset) | |
2491 | #endif /* CALL_DUMMY_CALL_OFFSET */ | |
2492 | ||
c906108c SS |
2493 | /* Insert the function address into a call dummy instruction sequence |
2494 | stored at DUMMY. | |
2495 | ||
2496 | For structs and unions, if the function was compiled with Sun cc, | |
2497 | it expects 'unimp' after the call. But gcc doesn't use that | |
b1e29e33 AC |
2498 | (twisted) convention. So leave a nop there for gcc |
2499 | (DEPRECATED_FIX_CALL_DUMMY can assume it is operating on a pristine | |
2500 | CALL_DUMMY, not one that has already been customized for a | |
2501 | different function). */ | |
c906108c SS |
2502 | |
2503 | void | |
fba45db2 KB |
2504 | sparc_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, |
2505 | struct type *value_type, int using_gcc) | |
c906108c SS |
2506 | { |
2507 | int i; | |
2508 | ||
2509 | /* Store the relative adddress of the target function into the | |
2510 | 'call' instruction. */ | |
2511 | store_unsigned_integer (dummy + CALL_DUMMY_CALL_OFFSET, 4, | |
2512 | (0x40000000 | |
2513 | | (((fun - (pc + CALL_DUMMY_CALL_OFFSET)) >> 2) | |
c5aa993b | 2514 | & 0x3fffffff))); |
c906108c | 2515 | |
9e36d949 PS |
2516 | /* If the called function returns an aggregate value, fill in the UNIMP |
2517 | instruction containing the size of the returned aggregate return value, | |
2518 | which follows the call instruction. | |
2519 | For details see the SPARC Architecture Manual Version 8, Appendix D.3. | |
2520 | ||
2521 | Adjust the call_dummy_breakpoint_offset for the bp_call_dummy breakpoint | |
2522 | to the proper address in the call dummy, so that `finish' after a stop | |
2523 | in a call dummy works. | |
04714b91 AC |
2524 | |
2525 | Tweeking current_gdbarch is not an optimal solution, but the call | |
2526 | to sparc_fix_call_dummy is immediately followed by a call to | |
2527 | call_function_by_hand, which is the only function where | |
2528 | dummy_breakpoint_offset is actually used, if it is non-zero. */ | |
9e36d949 PS |
2529 | if (TYPE_CODE (value_type) == TYPE_CODE_STRUCT |
2530 | || TYPE_CODE (value_type) == TYPE_CODE_UNION) | |
2531 | { | |
2532 | store_unsigned_integer (dummy + CALL_DUMMY_CALL_OFFSET + 8, 4, | |
2533 | TYPE_LENGTH (value_type) & 0x1fff); | |
b1e29e33 | 2534 | set_gdbarch_deprecated_call_dummy_breakpoint_offset (current_gdbarch, 0x30); |
9e36d949 PS |
2535 | } |
2536 | else | |
b1e29e33 | 2537 | set_gdbarch_deprecated_call_dummy_breakpoint_offset (current_gdbarch, 0x2c); |
c906108c | 2538 | |
5af923b0 | 2539 | if (!(GDB_TARGET_IS_SPARC64)) |
c906108c | 2540 | { |
5af923b0 MS |
2541 | /* If this is not a simulator target, change the first four |
2542 | instructions of the call dummy to NOPs. Those instructions | |
2543 | include a 'save' instruction and are designed to work around | |
2544 | problems with register window flushing in the simulator. */ | |
2545 | ||
2546 | if (strcmp (target_shortname, "sim") != 0) | |
2547 | { | |
2548 | for (i = 0; i < 4; i++) | |
2549 | store_unsigned_integer (dummy + (i * 4), 4, 0x01000000); | |
2550 | } | |
c906108c | 2551 | } |
c906108c | 2552 | |
f81824a9 AC |
2553 | #if 0 |
2554 | // OBSOLETE /* If this is a bi-endian target, GDB has written the call dummy | |
2555 | // OBSOLETE in little-endian order. We must byte-swap it back to big-endian. */ | |
2556 | // OBSOLETE if (bi_endian) | |
2557 | // OBSOLETE { | |
2558 | // OBSOLETE for (i = 0; i < CALL_DUMMY_LENGTH; i += 4) | |
2559 | // OBSOLETE { | |
2560 | // OBSOLETE char tmp = dummy[i]; | |
2561 | // OBSOLETE dummy[i] = dummy[i + 3]; | |
2562 | // OBSOLETE dummy[i + 3] = tmp; | |
2563 | // OBSOLETE tmp = dummy[i + 1]; | |
2564 | // OBSOLETE dummy[i + 1] = dummy[i + 2]; | |
2565 | // OBSOLETE dummy[i + 2] = tmp; | |
2566 | // OBSOLETE } | |
2567 | // OBSOLETE } | |
2568 | #endif | |
c906108c SS |
2569 | } |
2570 | ||
2571 | ||
f81824a9 AC |
2572 | #if 0 |
2573 | // OBSOLETE /* Set target byte order based on machine type. */ | |
2574 | // OBSOLETE | |
2575 | // OBSOLETE static int | |
2576 | // OBSOLETE sparc_target_architecture_hook (const bfd_arch_info_type *ap) | |
2577 | // OBSOLETE { | |
2578 | // OBSOLETE int i, j; | |
2579 | // OBSOLETE | |
2580 | // OBSOLETE if (ap->mach == bfd_mach_sparc_sparclite_le) | |
2581 | // OBSOLETE { | |
2582 | // OBSOLETE target_byte_order = BFD_ENDIAN_LITTLE; | |
2583 | // OBSOLETE bi_endian = 1; | |
2584 | // OBSOLETE } | |
2585 | // OBSOLETE else | |
2586 | // OBSOLETE bi_endian = 0; | |
2587 | // OBSOLETE return 1; | |
2588 | // OBSOLETE } | |
2589 | #endif | |
c5aa993b | 2590 | |
5af923b0 MS |
2591 | /* |
2592 | * Module "constructor" function. | |
2593 | */ | |
2594 | ||
2595 | static struct gdbarch * sparc_gdbarch_init (struct gdbarch_info info, | |
2596 | struct gdbarch_list *arches); | |
ef3cf062 | 2597 | static void sparc_dump_tdep (struct gdbarch *, struct ui_file *); |
5af923b0 | 2598 | |
a78f21af AC |
2599 | extern initialize_file_ftype _initialize_sparc_tdep; /* -Wmissing-prototypes */ |
2600 | ||
c906108c | 2601 | void |
fba45db2 | 2602 | _initialize_sparc_tdep (void) |
c906108c | 2603 | { |
5af923b0 | 2604 | /* Hook us into the gdbarch mechanism. */ |
ef3cf062 | 2605 | gdbarch_register (bfd_arch_sparc, sparc_gdbarch_init, sparc_dump_tdep); |
5af923b0 | 2606 | |
d7a27068 | 2607 | deprecated_tm_print_insn = gdb_print_insn_sparc; |
810ecf9f | 2608 | deprecated_tm_print_insn_info.mach = TM_PRINT_INSN_MACH; /* Selects sparc/sparclite */ |
f81824a9 | 2609 | /* OBSOLETE target_architecture_hook = sparc_target_architecture_hook; */ |
c906108c SS |
2610 | } |
2611 | ||
5af923b0 MS |
2612 | /* Compensate for stack bias. Note that we currently don't handle |
2613 | mixed 32/64 bit code. */ | |
c906108c | 2614 | |
a78f21af | 2615 | static CORE_ADDR |
5af923b0 | 2616 | sparc64_read_sp (void) |
c906108c SS |
2617 | { |
2618 | CORE_ADDR sp = read_register (SP_REGNUM); | |
2619 | ||
2620 | if (sp & 1) | |
2621 | sp += 2047; | |
2622 | return sp; | |
2623 | } | |
2624 | ||
a78f21af | 2625 | static CORE_ADDR |
5af923b0 | 2626 | sparc64_read_fp (void) |
c906108c | 2627 | { |
0ba6dca9 | 2628 | CORE_ADDR fp = read_register (DEPRECATED_FP_REGNUM); |
c906108c SS |
2629 | |
2630 | if (fp & 1) | |
2631 | fp += 2047; | |
2632 | return fp; | |
2633 | } | |
2634 | ||
a78f21af | 2635 | static void |
fba45db2 | 2636 | sparc64_write_sp (CORE_ADDR val) |
c906108c SS |
2637 | { |
2638 | CORE_ADDR oldsp = read_register (SP_REGNUM); | |
2639 | if (oldsp & 1) | |
2640 | write_register (SP_REGNUM, val - 2047); | |
2641 | else | |
2642 | write_register (SP_REGNUM, val); | |
2643 | } | |
2644 | ||
5af923b0 MS |
2645 | /* The SPARC 64 ABI passes floating-point arguments in FP0 to FP31, |
2646 | and all other arguments in O0 to O5. They are also copied onto | |
2647 | the stack in the correct places. Apparently (empirically), | |
2648 | structs of less than 16 bytes are passed member-by-member in | |
2649 | separate registers, but I am unable to figure out the algorithm. | |
2650 | Some members go in floating point regs, but I don't know which. | |
2651 | ||
2652 | FIXME: Handle small structs (less than 16 bytes containing floats). | |
2653 | ||
2654 | The counting regimen for using both integer and FP registers | |
2655 | for argument passing is rather odd -- a single counter is used | |
2656 | for both; this means that if the arguments alternate between | |
2657 | int and float, we will waste every other register of both types. */ | |
c906108c | 2658 | |
a78f21af | 2659 | static CORE_ADDR |
ea7c478f | 2660 | sparc64_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
fba45db2 | 2661 | int struct_return, CORE_ADDR struct_retaddr) |
c906108c | 2662 | { |
5af923b0 | 2663 | int i, j, register_counter = 0; |
c906108c | 2664 | CORE_ADDR tempsp; |
5af923b0 MS |
2665 | struct type *sparc_intreg_type = |
2666 | TYPE_LENGTH (builtin_type_long) == SPARC_INTREG_SIZE ? | |
2667 | builtin_type_long : builtin_type_long_long; | |
c5aa993b | 2668 | |
5af923b0 | 2669 | sp = (sp & ~(((unsigned long) SPARC_INTREG_SIZE) - 1UL)); |
c906108c SS |
2670 | |
2671 | /* Figure out how much space we'll need. */ | |
5af923b0 | 2672 | for (i = nargs - 1; i >= 0; i--) |
c906108c | 2673 | { |
5af923b0 | 2674 | int len = TYPE_LENGTH (check_typedef (VALUE_TYPE (args[i]))); |
ea7c478f | 2675 | struct value *copyarg = args[i]; |
c906108c SS |
2676 | int copylen = len; |
2677 | ||
5af923b0 | 2678 | if (copylen < SPARC_INTREG_SIZE) |
c906108c | 2679 | { |
5af923b0 MS |
2680 | copyarg = value_cast (sparc_intreg_type, copyarg); |
2681 | copylen = SPARC_INTREG_SIZE; | |
c5aa993b | 2682 | } |
c906108c SS |
2683 | sp -= copylen; |
2684 | } | |
2685 | ||
2686 | /* Round down. */ | |
2687 | sp = sp & ~7; | |
2688 | tempsp = sp; | |
2689 | ||
5af923b0 MS |
2690 | /* if STRUCT_RETURN, then first argument is the struct return location. */ |
2691 | if (struct_return) | |
2692 | write_register (O0_REGNUM + register_counter++, struct_retaddr); | |
2693 | ||
2694 | /* Now write the arguments onto the stack, while writing FP | |
2695 | arguments into the FP registers, and other arguments into the | |
2696 | first six 'O' registers. */ | |
2697 | ||
2698 | for (i = 0; i < nargs; i++) | |
c906108c | 2699 | { |
5af923b0 | 2700 | int len = TYPE_LENGTH (check_typedef (VALUE_TYPE (args[i]))); |
ea7c478f | 2701 | struct value *copyarg = args[i]; |
5af923b0 | 2702 | enum type_code typecode = TYPE_CODE (VALUE_TYPE (args[i])); |
c906108c SS |
2703 | int copylen = len; |
2704 | ||
5af923b0 MS |
2705 | if (typecode == TYPE_CODE_INT || |
2706 | typecode == TYPE_CODE_BOOL || | |
2707 | typecode == TYPE_CODE_CHAR || | |
2708 | typecode == TYPE_CODE_RANGE || | |
2709 | typecode == TYPE_CODE_ENUM) | |
2710 | if (len < SPARC_INTREG_SIZE) | |
2711 | { | |
2712 | /* Small ints will all take up the size of one intreg on | |
2713 | the stack. */ | |
2714 | copyarg = value_cast (sparc_intreg_type, copyarg); | |
2715 | copylen = SPARC_INTREG_SIZE; | |
2716 | } | |
2717 | ||
c906108c SS |
2718 | write_memory (tempsp, VALUE_CONTENTS (copyarg), copylen); |
2719 | tempsp += copylen; | |
5af923b0 MS |
2720 | |
2721 | /* Corner case: Structs consisting of a single float member are floats. | |
2722 | * FIXME! I don't know about structs containing multiple floats! | |
2723 | * Structs containing mixed floats and ints are even more weird. | |
2724 | */ | |
2725 | ||
2726 | ||
2727 | ||
2728 | /* Separate float args from all other args. */ | |
2729 | if (typecode == TYPE_CODE_FLT && SPARC_HAS_FPU) | |
c906108c | 2730 | { |
5af923b0 MS |
2731 | if (register_counter < 16) |
2732 | { | |
2733 | /* This arg gets copied into a FP register. */ | |
2734 | int fpreg; | |
2735 | ||
2736 | switch (len) { | |
2737 | case 4: /* Single-precision (float) */ | |
2738 | fpreg = FP0_REGNUM + 2 * register_counter + 1; | |
2739 | register_counter += 1; | |
2740 | break; | |
2741 | case 8: /* Double-precision (double) */ | |
2742 | fpreg = FP0_REGNUM + 2 * register_counter; | |
2743 | register_counter += 1; | |
2744 | break; | |
2745 | case 16: /* Quad-precision (long double) */ | |
2746 | fpreg = FP0_REGNUM + 2 * register_counter; | |
2747 | register_counter += 2; | |
2748 | break; | |
93d56215 AC |
2749 | default: |
2750 | internal_error (__FILE__, __LINE__, "bad switch"); | |
5af923b0 | 2751 | } |
73937e03 AC |
2752 | deprecated_write_register_bytes (REGISTER_BYTE (fpreg), |
2753 | VALUE_CONTENTS (args[i]), | |
2754 | len); | |
5af923b0 | 2755 | } |
c906108c | 2756 | } |
5af923b0 MS |
2757 | else /* all other args go into the first six 'o' registers */ |
2758 | { | |
2759 | for (j = 0; | |
2760 | j < len && register_counter < 6; | |
2761 | j += SPARC_INTREG_SIZE) | |
2762 | { | |
2763 | int oreg = O0_REGNUM + register_counter; | |
2764 | ||
4caf0990 | 2765 | deprecated_write_register_gen (oreg, VALUE_CONTENTS (copyarg) + j); |
5af923b0 MS |
2766 | register_counter += 1; |
2767 | } | |
2768 | } | |
c906108c SS |
2769 | } |
2770 | return sp; | |
2771 | } | |
2772 | ||
2773 | /* Values <= 32 bytes are returned in o0-o3 (floating-point values are | |
2774 | returned in f0-f3). */ | |
5af923b0 | 2775 | |
a78f21af | 2776 | static void |
fba45db2 KB |
2777 | sp64_extract_return_value (struct type *type, char *regbuf, char *valbuf, |
2778 | int bitoffset) | |
c906108c SS |
2779 | { |
2780 | int typelen = TYPE_LENGTH (type); | |
2781 | int regsize = REGISTER_RAW_SIZE (O0_REGNUM); | |
2782 | ||
2783 | if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU) | |
2784 | { | |
c5aa993b | 2785 | memcpy (valbuf, ®buf[REGISTER_BYTE (FP0_REGNUM)], typelen); |
c906108c SS |
2786 | return; |
2787 | } | |
2788 | ||
2789 | if (TYPE_CODE (type) != TYPE_CODE_STRUCT | |
2790 | || (TYPE_LENGTH (type) > 32)) | |
2791 | { | |
2792 | memcpy (valbuf, | |
c5aa993b | 2793 | ®buf[O0_REGNUM * regsize + |
c906108c SS |
2794 | (typelen >= regsize ? 0 : regsize - typelen)], |
2795 | typelen); | |
2796 | return; | |
2797 | } | |
2798 | else | |
2799 | { | |
2800 | char *o0 = ®buf[O0_REGNUM * regsize]; | |
2801 | char *f0 = ®buf[FP0_REGNUM * regsize]; | |
2802 | int x; | |
2803 | ||
2804 | for (x = 0; x < TYPE_NFIELDS (type); x++) | |
2805 | { | |
c5aa993b | 2806 | struct field *f = &TYPE_FIELDS (type)[x]; |
c906108c SS |
2807 | /* FIXME: We may need to handle static fields here. */ |
2808 | int whichreg = (f->loc.bitpos + bitoffset) / 32; | |
2809 | int remainder = ((f->loc.bitpos + bitoffset) % 32) / 8; | |
2810 | int where = (f->loc.bitpos + bitoffset) / 8; | |
2811 | int size = TYPE_LENGTH (f->type); | |
2812 | int typecode = TYPE_CODE (f->type); | |
2813 | ||
2814 | if (typecode == TYPE_CODE_STRUCT) | |
2815 | { | |
5af923b0 MS |
2816 | sp64_extract_return_value (f->type, |
2817 | regbuf, | |
2818 | valbuf, | |
2819 | bitoffset + f->loc.bitpos); | |
c906108c | 2820 | } |
5af923b0 | 2821 | else if (typecode == TYPE_CODE_FLT && SPARC_HAS_FPU) |
c906108c SS |
2822 | { |
2823 | memcpy (valbuf + where, &f0[whichreg * 4] + remainder, size); | |
2824 | } | |
2825 | else | |
2826 | { | |
2827 | memcpy (valbuf + where, &o0[whichreg * 4] + remainder, size); | |
2828 | } | |
2829 | } | |
2830 | } | |
2831 | } | |
2acceee2 | 2832 | |
a78f21af | 2833 | static void |
5af923b0 MS |
2834 | sparc64_extract_return_value (struct type *type, char *regbuf, char *valbuf) |
2835 | { | |
2836 | sp64_extract_return_value (type, regbuf, valbuf, 0); | |
2837 | } | |
2838 | ||
f81824a9 AC |
2839 | #if 0 |
2840 | // OBSOLETE extern void | |
2841 | // OBSOLETE sparclet_extract_return_value (struct type *type, | |
2842 | // OBSOLETE char *regbuf, | |
2843 | // OBSOLETE char *valbuf) | |
2844 | // OBSOLETE { | |
2845 | // OBSOLETE regbuf += REGISTER_RAW_SIZE (O0_REGNUM) * 8; | |
2846 | // OBSOLETE if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (O0_REGNUM)) | |
2847 | // OBSOLETE regbuf += REGISTER_RAW_SIZE (O0_REGNUM) - TYPE_LENGTH (type); | |
2848 | // OBSOLETE | |
2849 | // OBSOLETE memcpy ((void *) valbuf, regbuf, TYPE_LENGTH (type)); | |
2850 | // OBSOLETE } | |
2851 | #endif | |
5af923b0 MS |
2852 | |
2853 | extern CORE_ADDR | |
2854 | sparc32_stack_align (CORE_ADDR addr) | |
2855 | { | |
2856 | return ((addr + 7) & -8); | |
2857 | } | |
2858 | ||
a78f21af | 2859 | static CORE_ADDR |
5af923b0 MS |
2860 | sparc64_stack_align (CORE_ADDR addr) |
2861 | { | |
2862 | return ((addr + 15) & -16); | |
2863 | } | |
2864 | ||
2865 | extern void | |
2866 | sparc_print_extra_frame_info (struct frame_info *fi) | |
2867 | { | |
da50a4b7 | 2868 | if (fi && get_frame_extra_info (fi) && get_frame_extra_info (fi)->flat) |
5af923b0 | 2869 | printf_filtered (" flat, pc saved at 0x%s, fp saved at 0x%s\n", |
da50a4b7 AC |
2870 | paddr_nz (get_frame_extra_info (fi)->pc_addr), |
2871 | paddr_nz (get_frame_extra_info (fi)->fp_addr)); | |
5af923b0 MS |
2872 | } |
2873 | ||
2874 | /* MULTI_ARCH support */ | |
2875 | ||
e23457df AC |
2876 | const char * |
2877 | legacy_register_name (int i) | |
2878 | { | |
2879 | #ifdef REGISTER_NAMES | |
2880 | static char *names[] = REGISTER_NAMES; | |
2881 | if (i < 0 || i >= (sizeof (names) / sizeof (*names))) | |
2882 | return NULL; | |
2883 | else | |
2884 | return names[i]; | |
2885 | #else | |
2886 | internal_error (__FILE__, __LINE__, | |
2887 | "legacy_register_name: called."); | |
2888 | return NULL; | |
2889 | #endif | |
2890 | } | |
2891 | ||
fa88f677 | 2892 | static const char * |
5af923b0 MS |
2893 | sparc32_register_name (int regno) |
2894 | { | |
2895 | static char *register_names[] = | |
2896 | { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", | |
2897 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", | |
2898 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", | |
2899 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", | |
2900 | ||
2901 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
2902 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
2903 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
2904 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
2905 | ||
2906 | "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr" | |
2907 | }; | |
2908 | ||
2909 | if (regno < 0 || | |
2910 | regno >= (sizeof (register_names) / sizeof (register_names[0]))) | |
2911 | return NULL; | |
2912 | else | |
2913 | return register_names[regno]; | |
2914 | } | |
2915 | ||
fa88f677 | 2916 | static const char * |
5af923b0 MS |
2917 | sparc64_register_name (int regno) |
2918 | { | |
2919 | static char *register_names[] = | |
2920 | { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", | |
2921 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", | |
2922 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", | |
2923 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", | |
2924 | ||
2925 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
2926 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
2927 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
2928 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
2929 | "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46", | |
2930 | "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62", | |
2931 | ||
2932 | "pc", "npc", "ccr", "fsr", "fprs", "y", "asi", "ver", | |
2933 | "tick", "pil", "pstate", "tstate", "tba", "tl", "tt", "tpc", | |
2934 | "tnpc", "wstate", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", | |
2935 | "asr16", "asr17", "asr18", "asr19", "asr20", "asr21", "asr22", "asr23", | |
2936 | "asr24", "asr25", "asr26", "asr27", "asr28", "asr29", "asr30", "asr31", | |
2937 | /* These are here at the end to simplify removing them if we have to. */ | |
2938 | "icc", "xcc", "fcc0", "fcc1", "fcc2", "fcc3" | |
2939 | }; | |
2940 | ||
2941 | if (regno < 0 || | |
2942 | regno >= (sizeof (register_names) / sizeof (register_names[0]))) | |
2943 | return NULL; | |
2944 | else | |
2945 | return register_names[regno]; | |
2946 | } | |
2947 | ||
5af923b0 | 2948 | #if 0 |
f81824a9 AC |
2949 | // OBSOLETE static const char * |
2950 | // OBSOLETE sparclite_register_name (int regno) | |
2951 | // OBSOLETE { | |
2952 | // OBSOLETE static char *register_names[] = | |
2953 | // OBSOLETE { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", | |
2954 | // OBSOLETE "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", | |
2955 | // OBSOLETE "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", | |
2956 | // OBSOLETE "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", | |
2957 | // OBSOLETE | |
2958 | // OBSOLETE "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
2959 | // OBSOLETE "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
2960 | // OBSOLETE "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
2961 | // OBSOLETE "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
2962 | // OBSOLETE | |
2963 | // OBSOLETE "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr", | |
2964 | // OBSOLETE "dia1", "dia2", "dda1", "dda2", "ddv1", "ddv2", "dcr", "dsr" | |
2965 | // OBSOLETE }; | |
2966 | // OBSOLETE | |
2967 | // OBSOLETE if (regno < 0 || | |
2968 | // OBSOLETE regno >= (sizeof (register_names) / sizeof (register_names[0]))) | |
2969 | // OBSOLETE return NULL; | |
2970 | // OBSOLETE else | |
2971 | // OBSOLETE return register_names[regno]; | |
2972 | // OBSOLETE } | |
2973 | #endif | |
5af923b0 | 2974 | |
f81824a9 AC |
2975 | #if 0 |
2976 | // OBSOLETE static const char * | |
2977 | // OBSOLETE sparclet_register_name (int regno) | |
2978 | // OBSOLETE { | |
2979 | // OBSOLETE static char *register_names[] = | |
2980 | // OBSOLETE { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", | |
2981 | // OBSOLETE "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", | |
2982 | // OBSOLETE "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", | |
2983 | // OBSOLETE "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", | |
2984 | // OBSOLETE | |
2985 | // OBSOLETE "", "", "", "", "", "", "", "", /* no floating point registers */ | |
2986 | // OBSOLETE "", "", "", "", "", "", "", "", | |
2987 | // OBSOLETE "", "", "", "", "", "", "", "", | |
2988 | // OBSOLETE "", "", "", "", "", "", "", "", | |
2989 | // OBSOLETE | |
2990 | // OBSOLETE "y", "psr", "wim", "tbr", "pc", "npc", "", "", /* no FPSR or CPSR */ | |
2991 | // OBSOLETE "ccsr", "ccpr", "cccrcr", "ccor", "ccobr", "ccibr", "ccir", "", | |
2992 | // OBSOLETE | |
2993 | // OBSOLETE /* ASR15 ASR19 (don't display them) */ | |
2994 | // OBSOLETE "asr1", "", "asr17", "asr18", "", "asr20", "asr21", "asr22" | |
2995 | // OBSOLETE /* None of the rest get displayed */ | |
2996 | // OBSOLETE #if 0 | |
2997 | // OBSOLETE "awr0", "awr1", "awr2", "awr3", "awr4", "awr5", "awr6", "awr7", | |
2998 | // OBSOLETE "awr8", "awr9", "awr10", "awr11", "awr12", "awr13", "awr14", "awr15", | |
2999 | // OBSOLETE "awr16", "awr17", "awr18", "awr19", "awr20", "awr21", "awr22", "awr23", | |
3000 | // OBSOLETE "awr24", "awr25", "awr26", "awr27", "awr28", "awr29", "awr30", "awr31", | |
3001 | // OBSOLETE "apsr" | |
3002 | // OBSOLETE #endif /* 0 */ | |
3003 | // OBSOLETE }; | |
3004 | // OBSOLETE | |
3005 | // OBSOLETE if (regno < 0 || | |
3006 | // OBSOLETE regno >= (sizeof (register_names) / sizeof (register_names[0]))) | |
3007 | // OBSOLETE return NULL; | |
3008 | // OBSOLETE else | |
3009 | // OBSOLETE return register_names[regno]; | |
3010 | // OBSOLETE } | |
3011 | #endif | |
5af923b0 | 3012 | |
a78f21af | 3013 | static CORE_ADDR |
5af923b0 MS |
3014 | sparc_push_return_address (CORE_ADDR pc_unused, CORE_ADDR sp) |
3015 | { | |
3016 | if (CALL_DUMMY_LOCATION == AT_ENTRY_POINT) | |
3017 | { | |
3018 | /* The return PC of the dummy_frame is the former 'current' PC | |
3019 | (where we were before we made the target function call). | |
3020 | This is saved in %i7 by push_dummy_frame. | |
3021 | ||
3022 | We will save the 'call dummy location' (ie. the address | |
3023 | to which the target function will return) in %o7. | |
3024 | This address will actually be the program's entry point. | |
3025 | There will be a special call_dummy breakpoint there. */ | |
3026 | ||
3027 | write_register (O7_REGNUM, | |
3028 | CALL_DUMMY_ADDRESS () - 8); | |
3029 | } | |
3030 | ||
3031 | return sp; | |
3032 | } | |
3033 | ||
3034 | /* Should call_function allocate stack space for a struct return? */ | |
3035 | ||
3036 | static int | |
3037 | sparc64_use_struct_convention (int gcc_p, struct type *type) | |
3038 | { | |
3039 | return (TYPE_LENGTH (type) > 32); | |
3040 | } | |
3041 | ||
3042 | /* Store the address of the place in which to copy the structure the | |
3043 | subroutine will return. This is called from call_function_by_hand. | |
3044 | The ultimate mystery is, tho, what is the value "16"? | |
3045 | ||
3046 | MVS: That's the offset from where the sp is now, to where the | |
3047 | subroutine is gonna expect to find the struct return address. */ | |
3048 | ||
3049 | static void | |
3050 | sparc32_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) | |
3051 | { | |
3052 | char *val; | |
3053 | CORE_ADDR o7; | |
3054 | ||
3055 | val = alloca (SPARC_INTREG_SIZE); | |
3056 | store_unsigned_integer (val, SPARC_INTREG_SIZE, addr); | |
3057 | write_memory (sp + (16 * SPARC_INTREG_SIZE), val, SPARC_INTREG_SIZE); | |
3058 | ||
3059 | if (CALL_DUMMY_LOCATION == AT_ENTRY_POINT) | |
3060 | { | |
3061 | /* Now adjust the value of the link register, which was previously | |
3062 | stored by push_return_address. Functions that return structs are | |
3063 | peculiar in that they return to link register + 12, rather than | |
3064 | link register + 8. */ | |
3065 | ||
3066 | o7 = read_register (O7_REGNUM); | |
3067 | write_register (O7_REGNUM, o7 - 4); | |
3068 | } | |
3069 | } | |
3070 | ||
3071 | static void | |
3072 | sparc64_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) | |
3073 | { | |
3074 | /* FIXME: V9 uses %o0 for this. */ | |
3075 | /* FIXME MVS: Only for small enough structs!!! */ | |
2acceee2 | 3076 | |
5af923b0 MS |
3077 | target_write_memory (sp + (16 * SPARC_INTREG_SIZE), |
3078 | (char *) &addr, SPARC_INTREG_SIZE); | |
3079 | #if 0 | |
3080 | if (CALL_DUMMY_LOCATION == AT_ENTRY_POINT) | |
3081 | { | |
3082 | /* Now adjust the value of the link register, which was previously | |
3083 | stored by push_return_address. Functions that return structs are | |
3084 | peculiar in that they return to link register + 12, rather than | |
3085 | link register + 8. */ | |
3086 | ||
3087 | write_register (O7_REGNUM, read_register (O7_REGNUM) - 4); | |
3088 | } | |
c906108c | 3089 | #endif |
5af923b0 MS |
3090 | } |
3091 | ||
3092 | /* Default target data type for register REGNO. */ | |
3093 | ||
3094 | static struct type * | |
3095 | sparc32_register_virtual_type (int regno) | |
3096 | { | |
3097 | if (regno == PC_REGNUM || | |
0ba6dca9 | 3098 | regno == DEPRECATED_FP_REGNUM || |
5af923b0 MS |
3099 | regno == SP_REGNUM) |
3100 | return builtin_type_unsigned_int; | |
3101 | if (regno < 32) | |
3102 | return builtin_type_int; | |
3103 | if (regno < 64) | |
3104 | return builtin_type_float; | |
3105 | return builtin_type_int; | |
3106 | } | |
3107 | ||
3108 | static struct type * | |
3109 | sparc64_register_virtual_type (int regno) | |
3110 | { | |
3111 | if (regno == PC_REGNUM || | |
0ba6dca9 | 3112 | regno == DEPRECATED_FP_REGNUM || |
5af923b0 MS |
3113 | regno == SP_REGNUM) |
3114 | return builtin_type_unsigned_long_long; | |
3115 | if (regno < 32) | |
3116 | return builtin_type_long_long; | |
3117 | if (regno < 64) | |
3118 | return builtin_type_float; | |
3119 | if (regno < 80) | |
3120 | return builtin_type_double; | |
3121 | return builtin_type_long_long; | |
3122 | } | |
3123 | ||
3124 | /* Number of bytes of storage in the actual machine representation for | |
3125 | register REGNO. */ | |
3126 | ||
3127 | static int | |
3128 | sparc32_register_size (int regno) | |
3129 | { | |
3130 | return 4; | |
3131 | } | |
3132 | ||
3133 | static int | |
3134 | sparc64_register_size (int regno) | |
3135 | { | |
3136 | return (regno < 32 ? 8 : regno < 64 ? 4 : 8); | |
3137 | } | |
3138 | ||
3139 | /* Index within the `registers' buffer of the first byte of the space | |
3140 | for register REGNO. */ | |
3141 | ||
3142 | static int | |
3143 | sparc32_register_byte (int regno) | |
3144 | { | |
3145 | return (regno * 4); | |
3146 | } | |
3147 | ||
3148 | static int | |
3149 | sparc64_register_byte (int regno) | |
3150 | { | |
3151 | if (regno < 32) | |
3152 | return regno * 8; | |
3153 | else if (regno < 64) | |
3154 | return 32 * 8 + (regno - 32) * 4; | |
3155 | else if (regno < 80) | |
3156 | return 32 * 8 + 32 * 4 + (regno - 64) * 8; | |
3157 | else | |
3158 | return 64 * 8 + (regno - 80) * 8; | |
3159 | } | |
3160 | ||
5af923b0 MS |
3161 | /* Immediately after a function call, return the saved pc. |
3162 | Can't go through the frames for this because on some machines | |
3163 | the new frame is not set up until the new function executes | |
3164 | some instructions. */ | |
3165 | ||
3166 | static CORE_ADDR | |
3167 | sparc_saved_pc_after_call (struct frame_info *fi) | |
3168 | { | |
3169 | return sparc_pc_adjust (read_register (RP_REGNUM)); | |
3170 | } | |
3171 | ||
5af923b0 MS |
3172 | /* Init saved regs: nothing to do, just a place-holder function. */ |
3173 | ||
3174 | static void | |
3175 | sparc_frame_init_saved_regs (struct frame_info *fi_ignored) | |
3176 | { /* no-op */ | |
3177 | } | |
3178 | ||
5af923b0 MS |
3179 | /* gdbarch fix call dummy: |
3180 | All this function does is rearrange the arguments before calling | |
3181 | sparc_fix_call_dummy (which does the real work). */ | |
3182 | ||
3183 | static void | |
3184 | sparc_gdbarch_fix_call_dummy (char *dummy, | |
3185 | CORE_ADDR pc, | |
3186 | CORE_ADDR fun, | |
3187 | int nargs, | |
3188 | struct value **args, | |
3189 | struct type *type, | |
3190 | int gcc_p) | |
3191 | { | |
3192 | if (CALL_DUMMY_LOCATION == ON_STACK) | |
3193 | sparc_fix_call_dummy (dummy, pc, fun, type, gcc_p); | |
3194 | } | |
3195 | ||
5af923b0 MS |
3196 | /* CALL_DUMMY_ADDRESS: fetch the breakpoint address for a call dummy. */ |
3197 | ||
3198 | static CORE_ADDR | |
3199 | sparc_call_dummy_address (void) | |
3200 | { | |
b1e29e33 | 3201 | return (DEPRECATED_CALL_DUMMY_START_OFFSET) + DEPRECATED_CALL_DUMMY_BREAKPOINT_OFFSET; |
5af923b0 MS |
3202 | } |
3203 | ||
3204 | /* Supply the Y register number to those that need it. */ | |
3205 | ||
9f9970a3 | 3206 | int |
5af923b0 MS |
3207 | sparc_y_regnum (void) |
3208 | { | |
3209 | return gdbarch_tdep (current_gdbarch)->y_regnum; | |
3210 | } | |
3211 | ||
3212 | int | |
3213 | sparc_reg_struct_has_addr (int gcc_p, struct type *type) | |
3214 | { | |
3215 | if (GDB_TARGET_IS_SPARC64) | |
3216 | return (TYPE_LENGTH (type) > 32); | |
3217 | else | |
3218 | return (gcc_p != 1); | |
3219 | } | |
3220 | ||
606e3b82 | 3221 | int |
5af923b0 MS |
3222 | sparc_intreg_size (void) |
3223 | { | |
3224 | return SPARC_INTREG_SIZE; | |
3225 | } | |
3226 | ||
3227 | static int | |
3228 | sparc_return_value_on_stack (struct type *type) | |
3229 | { | |
3230 | if (TYPE_CODE (type) == TYPE_CODE_FLT && | |
3231 | TYPE_LENGTH (type) > 8) | |
3232 | return 1; | |
3233 | else | |
3234 | return 0; | |
3235 | } | |
3236 | ||
143985b7 | 3237 | /* Get the ith function argument for the current function. */ |
a78f21af AC |
3238 | static CORE_ADDR |
3239 | sparc_fetch_pointer_argument (struct frame_info *frame, int argi, | |
3240 | struct type *type) | |
143985b7 AF |
3241 | { |
3242 | CORE_ADDR addr; | |
3243 | frame_read_register (frame, O0_REGNUM + argi, &addr); | |
3244 | return addr; | |
3245 | } | |
3246 | ||
5af923b0 MS |
3247 | /* |
3248 | * Gdbarch "constructor" function. | |
3249 | */ | |
3250 | ||
3251 | #define SPARC32_CALL_DUMMY_ON_STACK | |
3252 | ||
3253 | #define SPARC_SP_REGNUM 14 | |
3254 | #define SPARC_FP_REGNUM 30 | |
3255 | #define SPARC_FP0_REGNUM 32 | |
3256 | #define SPARC32_NPC_REGNUM 69 | |
3257 | #define SPARC32_PC_REGNUM 68 | |
3258 | #define SPARC32_Y_REGNUM 64 | |
3259 | #define SPARC64_PC_REGNUM 80 | |
3260 | #define SPARC64_NPC_REGNUM 81 | |
3261 | #define SPARC64_Y_REGNUM 85 | |
3262 | ||
3263 | static struct gdbarch * | |
3264 | sparc_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
3265 | { | |
3266 | struct gdbarch *gdbarch; | |
3267 | struct gdbarch_tdep *tdep; | |
3268 | ||
3269 | static LONGEST call_dummy_32[] = | |
3270 | { 0xbc100001, 0x9de38000, 0xbc100002, 0xbe100003, | |
3271 | 0xda03a058, 0xd803a054, 0xd603a050, 0xd403a04c, | |
3272 | 0xd203a048, 0x40000000, 0xd003a044, 0x01000000, | |
3273 | 0x91d02001, 0x01000000 | |
3274 | }; | |
3275 | static LONGEST call_dummy_64[] = | |
3276 | { 0x9de3bec0fd3fa7f7LL, 0xf93fa7eff53fa7e7LL, | |
3277 | 0xf13fa7dfed3fa7d7LL, 0xe93fa7cfe53fa7c7LL, | |
3278 | 0xe13fa7bfdd3fa7b7LL, 0xd93fa7afd53fa7a7LL, | |
3279 | 0xd13fa79fcd3fa797LL, 0xc93fa78fc53fa787LL, | |
3280 | 0xc13fa77fcc3fa777LL, 0xc83fa76fc43fa767LL, | |
3281 | 0xc03fa75ffc3fa757LL, 0xf83fa74ff43fa747LL, | |
3282 | 0xf03fa73f01000000LL, 0x0100000001000000LL, | |
3283 | 0x0100000091580000LL, 0xd027a72b93500000LL, | |
3284 | 0xd027a72791480000LL, 0xd027a72391400000LL, | |
3285 | 0xd027a71fda5ba8a7LL, 0xd85ba89fd65ba897LL, | |
3286 | 0xd45ba88fd25ba887LL, 0x9fc02000d05ba87fLL, | |
3287 | 0x0100000091d02001LL, 0x0100000001000000LL | |
3288 | }; | |
3289 | static LONGEST call_dummy_nil[] = {0}; | |
3290 | ||
ef3cf062 JT |
3291 | /* Try to determine the OS ABI of the object we are loading. */ |
3292 | ||
4be87837 DJ |
3293 | if (info.abfd != NULL |
3294 | && info.osabi == GDB_OSABI_UNKNOWN) | |
ef3cf062 | 3295 | { |
4be87837 DJ |
3296 | /* If it's an ELF file, assume it's Solaris. */ |
3297 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
3298 | info.osabi = GDB_OSABI_SOLARIS; | |
ef3cf062 JT |
3299 | } |
3300 | ||
5af923b0 | 3301 | /* First see if there is already a gdbarch that can satisfy the request. */ |
4be87837 DJ |
3302 | arches = gdbarch_list_lookup_by_info (arches, &info); |
3303 | if (arches != NULL) | |
3304 | return arches->gdbarch; | |
5af923b0 MS |
3305 | |
3306 | /* None found: is the request for a sparc architecture? */ | |
aca21d9a | 3307 | if (info.bfd_arch_info->arch != bfd_arch_sparc) |
5af923b0 MS |
3308 | return NULL; /* No; then it's not for us. */ |
3309 | ||
3310 | /* Yes: create a new gdbarch for the specified machine type. */ | |
3311 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); | |
3312 | gdbarch = gdbarch_alloc (&info, tdep); | |
3313 | ||
3314 | /* First set settings that are common for all sparc architectures. */ | |
3315 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); | |
aaab4dba | 3316 | set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc); |
5af923b0 MS |
3317 | set_gdbarch_decr_pc_after_break (gdbarch, 0); |
3318 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
44b7b84e MK |
3319 | set_gdbarch_extract_struct_value_address (gdbarch, |
3320 | sparc_extract_struct_value_address); | |
b1e29e33 | 3321 | set_gdbarch_deprecated_fix_call_dummy (gdbarch, sparc_gdbarch_fix_call_dummy); |
5af923b0 | 3322 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
0ba6dca9 | 3323 | set_gdbarch_deprecated_fp_regnum (gdbarch, SPARC_FP_REGNUM); |
5af923b0 | 3324 | set_gdbarch_fp0_regnum (gdbarch, SPARC_FP0_REGNUM); |
618ce49f | 3325 | set_gdbarch_deprecated_frame_chain (gdbarch, sparc_frame_chain); |
f30ee0bc | 3326 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sparc_frame_init_saved_regs); |
8bedc050 | 3327 | set_gdbarch_deprecated_frame_saved_pc (gdbarch, sparc_frame_saved_pc); |
5af923b0 MS |
3328 | set_gdbarch_frameless_function_invocation (gdbarch, |
3329 | frameless_look_for_prologue); | |
129c1cd6 | 3330 | set_gdbarch_deprecated_get_saved_register (gdbarch, sparc_get_saved_register); |
e9582e71 | 3331 | set_gdbarch_deprecated_init_extra_frame_info (gdbarch, sparc_init_extra_frame_info); |
5af923b0 MS |
3332 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
3333 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
3334 | set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT); | |
3335 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
a0ed5532 AC |
3336 | set_gdbarch_deprecated_max_register_raw_size (gdbarch, 8); |
3337 | set_gdbarch_deprecated_max_register_virtual_size (gdbarch, 8); | |
749b82f6 | 3338 | set_gdbarch_deprecated_pop_frame (gdbarch, sparc_pop_frame); |
28f617b3 | 3339 | set_gdbarch_deprecated_push_return_address (gdbarch, sparc_push_return_address); |
f3824013 | 3340 | set_gdbarch_deprecated_push_dummy_frame (gdbarch, sparc_push_dummy_frame); |
5af923b0 MS |
3341 | set_gdbarch_reg_struct_has_addr (gdbarch, sparc_reg_struct_has_addr); |
3342 | set_gdbarch_return_value_on_stack (gdbarch, sparc_return_value_on_stack); | |
6913c89a | 3343 | set_gdbarch_deprecated_saved_pc_after_call (gdbarch, sparc_saved_pc_after_call); |
9319a2fe | 3344 | set_gdbarch_prologue_frameless_p (gdbarch, sparc_prologue_frameless_p); |
5af923b0 | 3345 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
f510d44e | 3346 | set_gdbarch_skip_prologue (gdbarch, sparc_skip_prologue); |
5af923b0 | 3347 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); |
07555a72 | 3348 | set_gdbarch_deprecated_use_generic_dummy_frames (gdbarch, 0); |
5af923b0 MS |
3349 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
3350 | ||
143985b7 AF |
3351 | /* Helper for function argument information. */ |
3352 | set_gdbarch_fetch_pointer_argument (gdbarch, sparc_fetch_pointer_argument); | |
3353 | ||
5af923b0 MS |
3354 | /* |
3355 | * Settings that depend only on 32/64 bit word size | |
3356 | */ | |
3357 | ||
3358 | switch (info.bfd_arch_info->mach) | |
3359 | { | |
3360 | case bfd_mach_sparc: | |
f81824a9 AC |
3361 | #if 0 |
3362 | // OBSOLETE case bfd_mach_sparc_sparclet: | |
3363 | // OBSOLETE case bfd_mach_sparc_sparclite: | |
3364 | #endif | |
5af923b0 MS |
3365 | case bfd_mach_sparc_v8plus: |
3366 | case bfd_mach_sparc_v8plusa: | |
f81824a9 AC |
3367 | #if 0 |
3368 | // OBSOLETE case bfd_mach_sparc_sparclite_le: | |
3369 | #endif | |
5af923b0 MS |
3370 | /* 32-bit machine types: */ |
3371 | ||
3372 | #ifdef SPARC32_CALL_DUMMY_ON_STACK | |
ae45cd16 | 3373 | set_gdbarch_deprecated_pc_in_call_dummy (gdbarch, deprecated_pc_in_call_dummy_on_stack); |
5af923b0 | 3374 | set_gdbarch_call_dummy_address (gdbarch, sparc_call_dummy_address); |
b1e29e33 AC |
3375 | set_gdbarch_deprecated_call_dummy_breakpoint_offset (gdbarch, 0x30); |
3376 | set_gdbarch_deprecated_call_dummy_length (gdbarch, 0x38); | |
7e57f5f4 | 3377 | |
7043d8dc AC |
3378 | /* NOTE: cagney/2003-05-01: Using the just added push_dummy_code |
3379 | architecture method, it is now possible to implement a | |
3380 | generic dummy frames based inferior function call that stores | |
3381 | the breakpoint (and struct info) on the stack. Further, by | |
3382 | treating a SIGSEG at a breakpoint as equivalent to a SIGTRAP | |
3383 | it is even possible to make this work when the stack is | |
3384 | no-execute. | |
3385 | ||
3386 | NOTE: cagney/2002-04-26: Based from info posted by Peter | |
7e57f5f4 AC |
3387 | Schauer around Oct '99. Briefly, due to aspects of the SPARC |
3388 | ABI, it isn't possible to use ON_STACK with a strictly | |
3389 | compliant compiler. | |
3390 | ||
3391 | Peter Schauer writes ... | |
3392 | ||
3393 | No, any call from GDB to a user function returning a | |
3394 | struct/union will fail miserably. Try this: | |
3395 | ||
3396 | *NOINDENT* | |
3397 | struct x | |
3398 | { | |
3399 | int a[4]; | |
3400 | }; | |
3401 | ||
3402 | struct x gx; | |
3403 | ||
3404 | struct x | |
3405 | sret () | |
3406 | { | |
3407 | return gx; | |
3408 | } | |
3409 | ||
3410 | main () | |
3411 | { | |
3412 | int i; | |
3413 | for (i = 0; i < 4; i++) | |
3414 | gx.a[i] = i + 1; | |
3415 | gx = sret (); | |
3416 | } | |
3417 | *INDENT* | |
3418 | ||
3419 | Set a breakpoint at the gx = sret () statement, run to it and | |
3420 | issue a `print sret()'. It will not succed with your | |
3421 | approach, and I doubt that continuing the program will work | |
3422 | as well. | |
3423 | ||
3424 | For details of the ABI see the Sparc Architecture Manual. I | |
3425 | have Version 8 (Prentice Hall ISBN 0-13-825001-4) and the | |
3426 | calling conventions for functions returning aggregate values | |
3427 | are explained in Appendix D.3. */ | |
3428 | ||
5af923b0 | 3429 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
b1e29e33 | 3430 | set_gdbarch_deprecated_call_dummy_words (gdbarch, call_dummy_32); |
5af923b0 | 3431 | #else |
ae45cd16 | 3432 | set_gdbarch_deprecated_pc_in_call_dummy (gdbarch, deprecated_pc_in_call_dummy_at_entry_point); |
b1e29e33 | 3433 | set_gdbarch_deprecated_call_dummy_words (gdbarch, call_dummy_nil); |
5af923b0 | 3434 | #endif |
1bf6d5cc | 3435 | set_gdbarch_deprecated_call_dummy_stack_adjust (gdbarch, 68); |
5af923b0 MS |
3436 | set_gdbarch_frame_args_skip (gdbarch, 68); |
3437 | set_gdbarch_function_start_offset (gdbarch, 0); | |
3438 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
3439 | set_gdbarch_npc_regnum (gdbarch, SPARC32_NPC_REGNUM); | |
3440 | set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); | |
3441 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
b81774d8 | 3442 | set_gdbarch_deprecated_push_arguments (gdbarch, sparc32_push_arguments); |
5af923b0 | 3443 | |
9c04cab7 AC |
3444 | set_gdbarch_deprecated_register_byte (gdbarch, sparc32_register_byte); |
3445 | set_gdbarch_deprecated_register_raw_size (gdbarch, sparc32_register_size); | |
b1e29e33 | 3446 | set_gdbarch_deprecated_register_size (gdbarch, 4); |
9c04cab7 AC |
3447 | set_gdbarch_deprecated_register_virtual_size (gdbarch, sparc32_register_size); |
3448 | set_gdbarch_deprecated_register_virtual_type (gdbarch, sparc32_register_virtual_type); | |
5af923b0 | 3449 | #ifdef SPARC32_CALL_DUMMY_ON_STACK |
b1e29e33 | 3450 | set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, sizeof (call_dummy_32)); |
5af923b0 | 3451 | #else |
b1e29e33 | 3452 | set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, 0); |
5af923b0 MS |
3453 | #endif |
3454 | set_gdbarch_stack_align (gdbarch, sparc32_stack_align); | |
f933a9c5 | 3455 | set_gdbarch_deprecated_extra_stack_alignment_needed (gdbarch, 1); |
4183d812 | 3456 | set_gdbarch_deprecated_store_struct_return (gdbarch, sparc32_store_struct_return); |
5af923b0 MS |
3457 | set_gdbarch_use_struct_convention (gdbarch, |
3458 | generic_use_struct_convention); | |
b46e02f6 | 3459 | set_gdbarch_deprecated_dummy_write_sp (gdbarch, deprecated_write_sp); |
5af923b0 MS |
3460 | tdep->y_regnum = SPARC32_Y_REGNUM; |
3461 | tdep->fp_max_regnum = SPARC_FP0_REGNUM + 32; | |
3462 | tdep->intreg_size = 4; | |
3463 | tdep->reg_save_offset = 0x60; | |
3464 | tdep->call_dummy_call_offset = 0x24; | |
3465 | break; | |
3466 | ||
3467 | case bfd_mach_sparc_v9: | |
3468 | case bfd_mach_sparc_v9a: | |
3469 | /* 64-bit machine types: */ | |
3470 | default: /* Any new machine type is likely to be 64-bit. */ | |
3471 | ||
3472 | #ifdef SPARC64_CALL_DUMMY_ON_STACK | |
ae45cd16 | 3473 | set_gdbarch_deprecated_pc_in_call_dummy (gdbarch, deprecated_pc_in_call_dummy_on_stack); |
5af923b0 | 3474 | set_gdbarch_call_dummy_address (gdbarch, sparc_call_dummy_address); |
b1e29e33 AC |
3475 | set_gdbarch_deprecated_call_dummy_breakpoint_offset (gdbarch, 8 * 4); |
3476 | set_gdbarch_deprecated_call_dummy_length (gdbarch, 192); | |
5af923b0 | 3477 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
b1e29e33 AC |
3478 | set_gdbarch_deprecated_call_dummy_start_offset (gdbarch, 148); |
3479 | set_gdbarch_deprecated_call_dummy_words (gdbarch, call_dummy_64); | |
5af923b0 | 3480 | #else |
ae45cd16 | 3481 | set_gdbarch_deprecated_pc_in_call_dummy (gdbarch, deprecated_pc_in_call_dummy_at_entry_point); |
b1e29e33 | 3482 | set_gdbarch_deprecated_call_dummy_words (gdbarch, call_dummy_nil); |
5af923b0 | 3483 | #endif |
1bf6d5cc | 3484 | set_gdbarch_deprecated_call_dummy_stack_adjust (gdbarch, 128); |
5af923b0 MS |
3485 | set_gdbarch_frame_args_skip (gdbarch, 136); |
3486 | set_gdbarch_function_start_offset (gdbarch, 0); | |
3487 | set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
3488 | set_gdbarch_npc_regnum (gdbarch, SPARC64_NPC_REGNUM); | |
3489 | set_gdbarch_pc_regnum (gdbarch, SPARC64_PC_REGNUM); | |
3490 | set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
b81774d8 | 3491 | set_gdbarch_deprecated_push_arguments (gdbarch, sparc64_push_arguments); |
5af923b0 | 3492 | /* NOTE different for at_entry */ |
0ba6dca9 | 3493 | set_gdbarch_deprecated_target_read_fp (gdbarch, sparc64_read_fp); |
5af923b0 MS |
3494 | set_gdbarch_read_sp (gdbarch, sparc64_read_sp); |
3495 | /* Some of the registers aren't 64 bits, but it's a lot simpler just | |
3496 | to assume they all are (since most of them are). */ | |
9c04cab7 AC |
3497 | set_gdbarch_deprecated_register_byte (gdbarch, sparc64_register_byte); |
3498 | set_gdbarch_deprecated_register_raw_size (gdbarch, sparc64_register_size); | |
b1e29e33 | 3499 | set_gdbarch_deprecated_register_size (gdbarch, 8); |
9c04cab7 AC |
3500 | set_gdbarch_deprecated_register_virtual_size (gdbarch, sparc64_register_size); |
3501 | set_gdbarch_deprecated_register_virtual_type (gdbarch, sparc64_register_virtual_type); | |
5af923b0 | 3502 | #ifdef SPARC64_CALL_DUMMY_ON_STACK |
b1e29e33 | 3503 | set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, sizeof (call_dummy_64)); |
5af923b0 | 3504 | #else |
b1e29e33 | 3505 | set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, 0); |
5af923b0 MS |
3506 | #endif |
3507 | set_gdbarch_stack_align (gdbarch, sparc64_stack_align); | |
f933a9c5 | 3508 | set_gdbarch_deprecated_extra_stack_alignment_needed (gdbarch, 1); |
4183d812 | 3509 | set_gdbarch_deprecated_store_struct_return (gdbarch, sparc64_store_struct_return); |
5af923b0 MS |
3510 | set_gdbarch_use_struct_convention (gdbarch, |
3511 | sparc64_use_struct_convention); | |
6c0e89ed | 3512 | set_gdbarch_deprecated_dummy_write_sp (gdbarch, sparc64_write_sp); |
5af923b0 MS |
3513 | tdep->y_regnum = SPARC64_Y_REGNUM; |
3514 | tdep->fp_max_regnum = SPARC_FP0_REGNUM + 48; | |
3515 | tdep->intreg_size = 8; | |
3516 | tdep->reg_save_offset = 0x90; | |
3517 | tdep->call_dummy_call_offset = 148 + 4 * 5; | |
3518 | break; | |
3519 | } | |
3520 | ||
3521 | /* | |
3522 | * Settings that vary per-architecture: | |
3523 | */ | |
3524 | ||
3525 | switch (info.bfd_arch_info->mach) | |
3526 | { | |
3527 | case bfd_mach_sparc: | |
44b7b84e MK |
3528 | set_gdbarch_extract_return_value (gdbarch, sparc32_extract_return_value); |
3529 | set_gdbarch_store_return_value (gdbarch, sparc32_store_return_value); | |
5af923b0 | 3530 | set_gdbarch_num_regs (gdbarch, 72); |
b8b527c5 | 3531 | set_gdbarch_deprecated_register_bytes (gdbarch, 32*4 + 32*4 + 8*4); |
5af923b0 | 3532 | set_gdbarch_register_name (gdbarch, sparc32_register_name); |
f81824a9 AC |
3533 | #if 0 |
3534 | // OBSOLETE tdep->has_fpu = 1; /* (all but sparclet and sparclite) */ | |
3535 | #endif | |
5af923b0 MS |
3536 | tdep->fp_register_bytes = 32 * 4; |
3537 | tdep->print_insn_mach = bfd_mach_sparc; | |
3538 | break; | |
f81824a9 AC |
3539 | #if 0 |
3540 | // OBSOLETE case bfd_mach_sparc_sparclet: | |
3541 | // OBSOLETE set_gdbarch_deprecated_extract_return_value (gdbarch, sparclet_extract_return_value); | |
3542 | // OBSOLETE set_gdbarch_num_regs (gdbarch, 32 + 32 + 8 + 8 + 8); | |
3543 | // OBSOLETE set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4 + 8*4 + 8*4); | |
3544 | // OBSOLETE set_gdbarch_register_name (gdbarch, sparclet_register_name); | |
3545 | // OBSOLETE set_gdbarch_deprecated_store_return_value (gdbarch, sparclet_store_return_value); | |
3546 | // OBSOLETE tdep->has_fpu = 0; /* (all but sparclet and sparclite) */ | |
3547 | // OBSOLETE tdep->fp_register_bytes = 0; | |
3548 | // OBSOLETE tdep->print_insn_mach = bfd_mach_sparc_sparclet; | |
3549 | // OBSOLETE break; | |
3550 | #endif | |
3551 | #if 0 | |
3552 | // OBSOLETE case bfd_mach_sparc_sparclite: | |
3553 | // OBSOLETE set_gdbarch_deprecated_extract_return_value (gdbarch, sparc32_extract_return_value); | |
3554 | // OBSOLETE set_gdbarch_num_regs (gdbarch, 80); | |
3555 | // OBSOLETE set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4 + 8*4); | |
3556 | // OBSOLETE set_gdbarch_register_name (gdbarch, sparclite_register_name); | |
3557 | // OBSOLETE set_gdbarch_deprecated_store_return_value (gdbarch, sparc_store_return_value); | |
3558 | // OBSOLETE tdep->has_fpu = 0; /* (all but sparclet and sparclite) */ | |
3559 | // OBSOLETE tdep->fp_register_bytes = 0; | |
3560 | // OBSOLETE tdep->print_insn_mach = bfd_mach_sparc_sparclite; | |
3561 | // OBSOLETE break; | |
3562 | #endif | |
5af923b0 | 3563 | case bfd_mach_sparc_v8plus: |
44b7b84e MK |
3564 | set_gdbarch_extract_return_value (gdbarch, sparc32_extract_return_value); |
3565 | set_gdbarch_store_return_value (gdbarch, sparc32_store_return_value); | |
5af923b0 | 3566 | set_gdbarch_num_regs (gdbarch, 72); |
b8b527c5 | 3567 | set_gdbarch_deprecated_register_bytes (gdbarch, 32*4 + 32*4 + 8*4); |
5af923b0 | 3568 | set_gdbarch_register_name (gdbarch, sparc32_register_name); |
5af923b0 MS |
3569 | tdep->print_insn_mach = bfd_mach_sparc; |
3570 | tdep->fp_register_bytes = 32 * 4; | |
f81824a9 AC |
3571 | #if 0 |
3572 | // OBSOLETE tdep->has_fpu = 1; /* (all but sparclet and sparclite) */ | |
3573 | #endif | |
5af923b0 MS |
3574 | break; |
3575 | case bfd_mach_sparc_v8plusa: | |
44b7b84e MK |
3576 | set_gdbarch_extract_return_value (gdbarch, sparc32_extract_return_value); |
3577 | set_gdbarch_store_return_value (gdbarch, sparc32_store_return_value); | |
5af923b0 | 3578 | set_gdbarch_num_regs (gdbarch, 72); |
b8b527c5 | 3579 | set_gdbarch_deprecated_register_bytes (gdbarch, 32*4 + 32*4 + 8*4); |
5af923b0 | 3580 | set_gdbarch_register_name (gdbarch, sparc32_register_name); |
f81824a9 AC |
3581 | #if 0 |
3582 | // OBSOLETE tdep->has_fpu = 1; /* (all but sparclet and sparclite) */ | |
3583 | #endif | |
5af923b0 MS |
3584 | tdep->fp_register_bytes = 32 * 4; |
3585 | tdep->print_insn_mach = bfd_mach_sparc; | |
3586 | break; | |
f81824a9 AC |
3587 | #if 0 |
3588 | // OBSOLETE case bfd_mach_sparc_sparclite_le: | |
3589 | // OBSOLETE set_gdbarch_deprecated_extract_return_value (gdbarch, sparc32_extract_return_value); | |
3590 | // OBSOLETE set_gdbarch_num_regs (gdbarch, 80); | |
3591 | // OBSOLETE set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4 + 8*4); | |
3592 | // OBSOLETE set_gdbarch_register_name (gdbarch, sparclite_register_name); | |
3593 | // OBSOLETE set_gdbarch_deprecated_store_return_value (gdbarch, sparc_store_return_value); | |
3594 | // OBSOLETE tdep->has_fpu = 0; /* (all but sparclet and sparclite) */ | |
3595 | // OBSOLETE tdep->fp_register_bytes = 0; | |
3596 | // OBSOLETE tdep->print_insn_mach = bfd_mach_sparc_sparclite; | |
3597 | // OBSOLETE break; | |
3598 | #endif | |
5af923b0 | 3599 | case bfd_mach_sparc_v9: |
26e9b323 | 3600 | set_gdbarch_deprecated_extract_return_value (gdbarch, sparc64_extract_return_value); |
5af923b0 | 3601 | set_gdbarch_num_regs (gdbarch, 125); |
b8b527c5 | 3602 | set_gdbarch_deprecated_register_bytes (gdbarch, 32*8 + 32*8 + 45*8); |
5af923b0 | 3603 | set_gdbarch_register_name (gdbarch, sparc64_register_name); |
ebba8386 | 3604 | set_gdbarch_deprecated_store_return_value (gdbarch, sparc_store_return_value); |
f81824a9 AC |
3605 | #if 0 |
3606 | // OBSOLETE tdep->has_fpu = 1; /* (all but sparclet and sparclite) */ | |
3607 | #endif | |
5af923b0 MS |
3608 | tdep->fp_register_bytes = 64 * 4; |
3609 | tdep->print_insn_mach = bfd_mach_sparc_v9a; | |
3610 | break; | |
3611 | case bfd_mach_sparc_v9a: | |
26e9b323 | 3612 | set_gdbarch_deprecated_extract_return_value (gdbarch, sparc64_extract_return_value); |
5af923b0 | 3613 | set_gdbarch_num_regs (gdbarch, 125); |
b8b527c5 | 3614 | set_gdbarch_deprecated_register_bytes (gdbarch, 32*8 + 32*8 + 45*8); |
5af923b0 | 3615 | set_gdbarch_register_name (gdbarch, sparc64_register_name); |
ebba8386 | 3616 | set_gdbarch_deprecated_store_return_value (gdbarch, sparc_store_return_value); |
f81824a9 AC |
3617 | #if 0 |
3618 | // OBSOLETE tdep->has_fpu = 1; /* (all but sparclet and sparclite) */ | |
3619 | #endif | |
5af923b0 MS |
3620 | tdep->fp_register_bytes = 64 * 4; |
3621 | tdep->print_insn_mach = bfd_mach_sparc_v9a; | |
3622 | break; | |
3623 | } | |
3624 | ||
ef3cf062 | 3625 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
4be87837 | 3626 | gdbarch_init_osabi (info, gdbarch); |
ef3cf062 | 3627 | |
5af923b0 MS |
3628 | return gdbarch; |
3629 | } | |
3630 | ||
ef3cf062 JT |
3631 | static void |
3632 | sparc_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
3633 | { | |
3634 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3635 | ||
3636 | if (tdep == NULL) | |
3637 | return; | |
3638 | ||
f81824a9 AC |
3639 | #if 0 |
3640 | // OBSOLETE fprintf_unfiltered (file, "sparc_dump_tdep: has_fpu = %d\n", | |
3641 | // OBSOLETE tdep->has_fpu); | |
3642 | #endif | |
4be87837 DJ |
3643 | fprintf_unfiltered (file, "sparc_dump_tdep: fp_register_bytes = %d\n", |
3644 | tdep->fp_register_bytes); | |
3645 | fprintf_unfiltered (file, "sparc_dump_tdep: y_regnum = %d\n", | |
3646 | tdep->y_regnum); | |
3647 | fprintf_unfiltered (file, "sparc_dump_tdep: fp_max_regnum = %d\n", | |
3648 | tdep->fp_max_regnum); | |
3649 | fprintf_unfiltered (file, "sparc_dump_tdep: intreg_size = %d\n", | |
3650 | tdep->intreg_size); | |
3651 | fprintf_unfiltered (file, "sparc_dump_tdep: reg_save_offset = %d\n", | |
3652 | tdep->reg_save_offset); | |
3653 | fprintf_unfiltered (file, "sparc_dump_tdep: call_dummy_call_offset = %d\n", | |
3654 | tdep->call_dummy_call_offset); | |
3655 | fprintf_unfiltered (file, "sparc_dump_tdep: print_insn_match = %d\n", | |
d995ff4b | 3656 | tdep->print_insn_mach); |
ef3cf062 | 3657 | } |