Commit | Line | Data |
---|---|---|
386c036b | 1 | /* Target-dependent code for SPARC. |
cda5a58a | 2 | |
6aba47ca | 3 | Copyright (C) 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
197e01b6 EZ |
19 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
20 | Boston, MA 02110-1301, USA. */ | |
c906108c | 21 | |
c906108c | 22 | #include "defs.h" |
5af923b0 | 23 | #include "arch-utils.h" |
386c036b | 24 | #include "dis-asm.h" |
f5a9b87d | 25 | #include "dwarf2-frame.h" |
386c036b | 26 | #include "floatformat.h" |
c906108c | 27 | #include "frame.h" |
386c036b MK |
28 | #include "frame-base.h" |
29 | #include "frame-unwind.h" | |
30 | #include "gdbcore.h" | |
31 | #include "gdbtypes.h" | |
c906108c | 32 | #include "inferior.h" |
386c036b MK |
33 | #include "symtab.h" |
34 | #include "objfiles.h" | |
35 | #include "osabi.h" | |
36 | #include "regcache.h" | |
c906108c SS |
37 | #include "target.h" |
38 | #include "value.h" | |
c906108c | 39 | |
43bd9a9e | 40 | #include "gdb_assert.h" |
386c036b | 41 | #include "gdb_string.h" |
c906108c | 42 | |
386c036b | 43 | #include "sparc-tdep.h" |
c906108c | 44 | |
a54124c5 MK |
45 | struct regset; |
46 | ||
9eb42ed1 MK |
47 | /* This file implements the SPARC 32-bit ABI as defined by the section |
48 | "Low-Level System Information" of the SPARC Compliance Definition | |
49 | (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD | |
f2e7c15d | 50 | lists changes with respect to the original 32-bit psABI as defined |
9eb42ed1 | 51 | in the "System V ABI, SPARC Processor Supplement". |
386c036b MK |
52 | |
53 | Note that if we talk about SunOS, we mean SunOS 4.x, which was | |
54 | BSD-based, which is sometimes (retroactively?) referred to as | |
55 | Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and | |
56 | above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 | |
57 | suffering from severe version number inflation). Solaris 2.x is | |
58 | also known as SunOS 5.x, since that's what uname(1) says. Solaris | |
59 | 2.x is SVR4-based. */ | |
60 | ||
61 | /* Please use the sparc32_-prefix for 32-bit specific code, the | |
62 | sparc64_-prefix for 64-bit specific code and the sparc_-prefix for | |
63 | code that can handle both. The 64-bit specific code lives in | |
64 | sparc64-tdep.c; don't add any here. */ | |
65 | ||
66 | /* The SPARC Floating-Point Quad-Precision format is similar to | |
67 | big-endian IA-64 Quad-recision format. */ | |
8da61cc4 | 68 | #define floatformats_sparc_quad floatformats_ia64_quad |
386c036b MK |
69 | |
70 | /* The stack pointer is offset from the stack frame by a BIAS of 2047 | |
71 | (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC | |
72 | hosts, so undefine it first. */ | |
73 | #undef BIAS | |
74 | #define BIAS 2047 | |
75 | ||
76 | /* Macros to extract fields from SPARC instructions. */ | |
c906108c SS |
77 | #define X_OP(i) (((i) >> 30) & 0x3) |
78 | #define X_RD(i) (((i) >> 25) & 0x1f) | |
79 | #define X_A(i) (((i) >> 29) & 1) | |
80 | #define X_COND(i) (((i) >> 25) & 0xf) | |
81 | #define X_OP2(i) (((i) >> 22) & 0x7) | |
82 | #define X_IMM22(i) ((i) & 0x3fffff) | |
83 | #define X_OP3(i) (((i) >> 19) & 0x3f) | |
075ccec8 | 84 | #define X_RS1(i) (((i) >> 14) & 0x1f) |
b0b92586 | 85 | #define X_RS2(i) ((i) & 0x1f) |
c906108c | 86 | #define X_I(i) (((i) >> 13) & 1) |
c906108c | 87 | /* Sign extension macros. */ |
c906108c | 88 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) |
c906108c | 89 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) |
075ccec8 | 90 | #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000) |
c906108c | 91 | |
386c036b MK |
92 | /* Fetch the instruction at PC. Instructions are always big-endian |
93 | even if the processor operates in little-endian mode. */ | |
94 | ||
95 | unsigned long | |
96 | sparc_fetch_instruction (CORE_ADDR pc) | |
c906108c | 97 | { |
e1613aba | 98 | gdb_byte buf[4]; |
386c036b MK |
99 | unsigned long insn; |
100 | int i; | |
101 | ||
690668cc | 102 | /* If we can't read the instruction at PC, return zero. */ |
b5bf31df | 103 | if (read_memory_nobpt (pc, buf, sizeof (buf))) |
690668cc | 104 | return 0; |
c906108c | 105 | |
386c036b MK |
106 | insn = 0; |
107 | for (i = 0; i < sizeof (buf); i++) | |
108 | insn = (insn << 8) | buf[i]; | |
109 | return insn; | |
110 | } | |
42cdca6c MK |
111 | \f |
112 | ||
5465445a JB |
113 | /* Return non-zero if the instruction corresponding to PC is an "unimp" |
114 | instruction. */ | |
115 | ||
116 | static int | |
117 | sparc_is_unimp_insn (CORE_ADDR pc) | |
118 | { | |
119 | const unsigned long insn = sparc_fetch_instruction (pc); | |
120 | ||
121 | return ((insn & 0xc1c00000) == 0); | |
122 | } | |
123 | ||
42cdca6c MK |
124 | /* OpenBSD/sparc includes StackGhost, which according to the author's |
125 | website http://stackghost.cerias.purdue.edu "... transparently and | |
126 | automatically protects applications' stack frames; more | |
127 | specifically, it guards the return pointers. The protection | |
128 | mechanisms require no application source or binary modification and | |
129 | imposes only a negligible performance penalty." | |
130 | ||
131 | The same website provides the following description of how | |
132 | StackGhost works: | |
133 | ||
134 | "StackGhost interfaces with the kernel trap handler that would | |
135 | normally write out registers to the stack and the handler that | |
136 | would read them back in. By XORing a cookie into the | |
137 | return-address saved in the user stack when it is actually written | |
138 | to the stack, and then XOR it out when the return-address is pulled | |
139 | from the stack, StackGhost can cause attacker corrupted return | |
140 | pointers to behave in a manner the attacker cannot predict. | |
141 | StackGhost can also use several unused bits in the return pointer | |
142 | to detect a smashed return pointer and abort the process." | |
143 | ||
144 | For GDB this means that whenever we're reading %i7 from a stack | |
145 | frame's window save area, we'll have to XOR the cookie. | |
146 | ||
147 | More information on StackGuard can be found on in: | |
148 | ||
149 | Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated | |
150 | Stack Protection." 2001. Published in USENIX Security Symposium | |
151 | '01. */ | |
152 | ||
153 | /* Fetch StackGhost Per-Process XOR cookie. */ | |
154 | ||
155 | ULONGEST | |
156 | sparc_fetch_wcookie (void) | |
157 | { | |
baf92889 | 158 | struct target_ops *ops = ¤t_target; |
e1613aba | 159 | gdb_byte buf[8]; |
baf92889 MK |
160 | int len; |
161 | ||
13547ab6 | 162 | len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8); |
baf92889 MK |
163 | if (len == -1) |
164 | return 0; | |
42cdca6c | 165 | |
baf92889 MK |
166 | /* We should have either an 32-bit or an 64-bit cookie. */ |
167 | gdb_assert (len == 4 || len == 8); | |
168 | ||
169 | return extract_unsigned_integer (buf, len); | |
170 | } | |
386c036b | 171 | \f |
baf92889 | 172 | |
386c036b MK |
173 | /* The functions on this page are intended to be used to classify |
174 | function arguments. */ | |
c906108c | 175 | |
386c036b | 176 | /* Check whether TYPE is "Integral or Pointer". */ |
c906108c | 177 | |
386c036b MK |
178 | static int |
179 | sparc_integral_or_pointer_p (const struct type *type) | |
c906108c | 180 | { |
80ad1639 MK |
181 | int len = TYPE_LENGTH (type); |
182 | ||
386c036b | 183 | switch (TYPE_CODE (type)) |
c906108c | 184 | { |
386c036b MK |
185 | case TYPE_CODE_INT: |
186 | case TYPE_CODE_BOOL: | |
187 | case TYPE_CODE_CHAR: | |
188 | case TYPE_CODE_ENUM: | |
189 | case TYPE_CODE_RANGE: | |
80ad1639 MK |
190 | /* We have byte, half-word, word and extended-word/doubleword |
191 | integral types. The doubleword is an extension to the | |
192 | original 32-bit ABI by the SCD 2.4.x. */ | |
193 | return (len == 1 || len == 2 || len == 4 || len == 8); | |
386c036b MK |
194 | case TYPE_CODE_PTR: |
195 | case TYPE_CODE_REF: | |
80ad1639 MK |
196 | /* Allow either 32-bit or 64-bit pointers. */ |
197 | return (len == 4 || len == 8); | |
386c036b MK |
198 | default: |
199 | break; | |
200 | } | |
c906108c | 201 | |
386c036b MK |
202 | return 0; |
203 | } | |
c906108c | 204 | |
386c036b | 205 | /* Check whether TYPE is "Floating". */ |
c906108c | 206 | |
386c036b MK |
207 | static int |
208 | sparc_floating_p (const struct type *type) | |
209 | { | |
210 | switch (TYPE_CODE (type)) | |
c906108c | 211 | { |
386c036b MK |
212 | case TYPE_CODE_FLT: |
213 | { | |
214 | int len = TYPE_LENGTH (type); | |
215 | return (len == 4 || len == 8 || len == 16); | |
216 | } | |
217 | default: | |
218 | break; | |
219 | } | |
220 | ||
221 | return 0; | |
222 | } | |
c906108c | 223 | |
386c036b | 224 | /* Check whether TYPE is "Structure or Union". */ |
c906108c | 225 | |
386c036b MK |
226 | static int |
227 | sparc_structure_or_union_p (const struct type *type) | |
228 | { | |
229 | switch (TYPE_CODE (type)) | |
230 | { | |
231 | case TYPE_CODE_STRUCT: | |
232 | case TYPE_CODE_UNION: | |
233 | return 1; | |
234 | default: | |
235 | break; | |
c906108c | 236 | } |
386c036b MK |
237 | |
238 | return 0; | |
c906108c | 239 | } |
386c036b MK |
240 | |
241 | /* Register information. */ | |
242 | ||
243 | static const char *sparc32_register_names[] = | |
5af923b0 | 244 | { |
386c036b MK |
245 | "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
246 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", | |
247 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", | |
248 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", | |
249 | ||
250 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
251 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
252 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
253 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
254 | ||
255 | "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" | |
5af923b0 MS |
256 | }; |
257 | ||
386c036b MK |
258 | /* Total number of registers. */ |
259 | #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) | |
c906108c | 260 | |
386c036b MK |
261 | /* We provide the aliases %d0..%d30 for the floating registers as |
262 | "psuedo" registers. */ | |
263 | ||
264 | static const char *sparc32_pseudo_register_names[] = | |
265 | { | |
266 | "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", | |
267 | "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" | |
268 | }; | |
269 | ||
270 | /* Total number of pseudo registers. */ | |
271 | #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) | |
272 | ||
273 | /* Return the name of register REGNUM. */ | |
274 | ||
275 | static const char * | |
276 | sparc32_register_name (int regnum) | |
277 | { | |
278 | if (regnum >= 0 && regnum < SPARC32_NUM_REGS) | |
279 | return sparc32_register_names[regnum]; | |
280 | ||
281 | if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS) | |
282 | return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS]; | |
283 | ||
284 | return NULL; | |
285 | } | |
2d457077 MK |
286 | \f |
287 | ||
288 | /* Type for %psr. */ | |
289 | struct type *sparc_psr_type; | |
290 | ||
291 | /* Type for %fsr. */ | |
292 | struct type *sparc_fsr_type; | |
293 | ||
294 | /* Construct types for ISA-specific registers. */ | |
295 | ||
296 | static void | |
297 | sparc_init_types (void) | |
298 | { | |
299 | struct type *type; | |
300 | ||
301 | type = init_flags_type ("builtin_type_sparc_psr", 4); | |
302 | append_flags_type_flag (type, 5, "ET"); | |
303 | append_flags_type_flag (type, 6, "PS"); | |
304 | append_flags_type_flag (type, 7, "S"); | |
305 | append_flags_type_flag (type, 12, "EF"); | |
306 | append_flags_type_flag (type, 13, "EC"); | |
307 | sparc_psr_type = type; | |
308 | ||
309 | type = init_flags_type ("builtin_type_sparc_fsr", 4); | |
310 | append_flags_type_flag (type, 0, "NXA"); | |
311 | append_flags_type_flag (type, 1, "DZA"); | |
312 | append_flags_type_flag (type, 2, "UFA"); | |
313 | append_flags_type_flag (type, 3, "OFA"); | |
314 | append_flags_type_flag (type, 4, "NVA"); | |
315 | append_flags_type_flag (type, 5, "NXC"); | |
316 | append_flags_type_flag (type, 6, "DZC"); | |
317 | append_flags_type_flag (type, 7, "UFC"); | |
318 | append_flags_type_flag (type, 8, "OFC"); | |
319 | append_flags_type_flag (type, 9, "NVC"); | |
320 | append_flags_type_flag (type, 22, "NS"); | |
321 | append_flags_type_flag (type, 23, "NXM"); | |
322 | append_flags_type_flag (type, 24, "DZM"); | |
323 | append_flags_type_flag (type, 25, "UFM"); | |
324 | append_flags_type_flag (type, 26, "OFM"); | |
325 | append_flags_type_flag (type, 27, "NVM"); | |
326 | sparc_fsr_type = type; | |
327 | } | |
386c036b MK |
328 | |
329 | /* Return the GDB type object for the "standard" data type of data in | |
330 | register REGNUM. */ | |
331 | ||
332 | static struct type * | |
333 | sparc32_register_type (struct gdbarch *gdbarch, int regnum) | |
334 | { | |
335 | if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) | |
336 | return builtin_type_float; | |
337 | ||
338 | if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) | |
339 | return builtin_type_double; | |
340 | ||
341 | if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) | |
342 | return builtin_type_void_data_ptr; | |
343 | ||
344 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) | |
345 | return builtin_type_void_func_ptr; | |
346 | ||
2d457077 MK |
347 | if (regnum == SPARC32_PSR_REGNUM) |
348 | return sparc_psr_type; | |
349 | ||
350 | if (regnum == SPARC32_FSR_REGNUM) | |
351 | return sparc_fsr_type; | |
352 | ||
386c036b MK |
353 | return builtin_type_int32; |
354 | } | |
355 | ||
356 | static void | |
357 | sparc32_pseudo_register_read (struct gdbarch *gdbarch, | |
358 | struct regcache *regcache, | |
e1613aba | 359 | int regnum, gdb_byte *buf) |
386c036b MK |
360 | { |
361 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); | |
362 | ||
363 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
364 | regcache_raw_read (regcache, regnum, buf); | |
e1613aba | 365 | regcache_raw_read (regcache, regnum + 1, buf + 4); |
386c036b MK |
366 | } |
367 | ||
368 | static void | |
369 | sparc32_pseudo_register_write (struct gdbarch *gdbarch, | |
370 | struct regcache *regcache, | |
e1613aba | 371 | int regnum, const gdb_byte *buf) |
386c036b MK |
372 | { |
373 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); | |
374 | ||
375 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
376 | regcache_raw_write (regcache, regnum, buf); | |
e1613aba | 377 | regcache_raw_write (regcache, regnum + 1, buf + 4); |
386c036b MK |
378 | } |
379 | \f | |
380 | ||
381 | static CORE_ADDR | |
382 | sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
383 | CORE_ADDR funcaddr, int using_gcc, | |
384 | struct value **args, int nargs, | |
385 | struct type *value_type, | |
386 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr) | |
c906108c | 387 | { |
386c036b MK |
388 | *bp_addr = sp - 4; |
389 | *real_pc = funcaddr; | |
390 | ||
391 | if (using_struct_return (value_type, using_gcc)) | |
c906108c | 392 | { |
e1613aba | 393 | gdb_byte buf[4]; |
386c036b MK |
394 | |
395 | /* This is an UNIMP instruction. */ | |
396 | store_unsigned_integer (buf, 4, TYPE_LENGTH (value_type) & 0x1fff); | |
397 | write_memory (sp - 8, buf, 4); | |
398 | return sp - 8; | |
c906108c SS |
399 | } |
400 | ||
386c036b MK |
401 | return sp - 4; |
402 | } | |
403 | ||
404 | static CORE_ADDR | |
405 | sparc32_store_arguments (struct regcache *regcache, int nargs, | |
406 | struct value **args, CORE_ADDR sp, | |
407 | int struct_return, CORE_ADDR struct_addr) | |
408 | { | |
409 | /* Number of words in the "parameter array". */ | |
410 | int num_elements = 0; | |
411 | int element = 0; | |
412 | int i; | |
413 | ||
414 | for (i = 0; i < nargs; i++) | |
c906108c | 415 | { |
4991999e | 416 | struct type *type = value_type (args[i]); |
386c036b MK |
417 | int len = TYPE_LENGTH (type); |
418 | ||
419 | if (sparc_structure_or_union_p (type) | |
420 | || (sparc_floating_p (type) && len == 16)) | |
c906108c | 421 | { |
386c036b MK |
422 | /* Structure, Union and Quad-Precision Arguments. */ |
423 | sp -= len; | |
424 | ||
425 | /* Use doubleword alignment for these values. That's always | |
426 | correct, and wasting a few bytes shouldn't be a problem. */ | |
427 | sp &= ~0x7; | |
428 | ||
0fd88904 | 429 | write_memory (sp, value_contents (args[i]), len); |
386c036b MK |
430 | args[i] = value_from_pointer (lookup_pointer_type (type), sp); |
431 | num_elements++; | |
432 | } | |
433 | else if (sparc_floating_p (type)) | |
434 | { | |
435 | /* Floating arguments. */ | |
436 | gdb_assert (len == 4 || len == 8); | |
437 | num_elements += (len / 4); | |
c906108c | 438 | } |
c5aa993b JM |
439 | else |
440 | { | |
386c036b MK |
441 | /* Integral and pointer arguments. */ |
442 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
443 | ||
444 | if (len < 4) | |
445 | args[i] = value_cast (builtin_type_int32, args[i]); | |
446 | num_elements += ((len + 3) / 4); | |
c5aa993b | 447 | } |
c906108c | 448 | } |
c906108c | 449 | |
386c036b MK |
450 | /* Always allocate at least six words. */ |
451 | sp -= max (6, num_elements) * 4; | |
c906108c | 452 | |
386c036b MK |
453 | /* The psABI says that "Software convention requires space for the |
454 | struct/union return value pointer, even if the word is unused." */ | |
455 | sp -= 4; | |
c906108c | 456 | |
386c036b MK |
457 | /* The psABI says that "Although software convention and the |
458 | operating system require every stack frame to be doubleword | |
459 | aligned." */ | |
460 | sp &= ~0x7; | |
c906108c | 461 | |
386c036b | 462 | for (i = 0; i < nargs; i++) |
c906108c | 463 | { |
0fd88904 | 464 | const bfd_byte *valbuf = value_contents (args[i]); |
4991999e | 465 | struct type *type = value_type (args[i]); |
386c036b | 466 | int len = TYPE_LENGTH (type); |
c906108c | 467 | |
386c036b | 468 | gdb_assert (len == 4 || len == 8); |
c906108c | 469 | |
386c036b MK |
470 | if (element < 6) |
471 | { | |
472 | int regnum = SPARC_O0_REGNUM + element; | |
c906108c | 473 | |
386c036b MK |
474 | regcache_cooked_write (regcache, regnum, valbuf); |
475 | if (len > 4 && element < 5) | |
476 | regcache_cooked_write (regcache, regnum + 1, valbuf + 4); | |
477 | } | |
5af923b0 | 478 | |
386c036b MK |
479 | /* Always store the argument in memory. */ |
480 | write_memory (sp + 4 + element * 4, valbuf, len); | |
481 | element += len / 4; | |
482 | } | |
c906108c | 483 | |
386c036b | 484 | gdb_assert (element == num_elements); |
c906108c | 485 | |
386c036b | 486 | if (struct_return) |
c906108c | 487 | { |
e1613aba | 488 | gdb_byte buf[4]; |
c906108c | 489 | |
386c036b MK |
490 | store_unsigned_integer (buf, 4, struct_addr); |
491 | write_memory (sp, buf, 4); | |
492 | } | |
c906108c | 493 | |
386c036b | 494 | return sp; |
c906108c SS |
495 | } |
496 | ||
386c036b | 497 | static CORE_ADDR |
7d9b040b | 498 | sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
386c036b MK |
499 | struct regcache *regcache, CORE_ADDR bp_addr, |
500 | int nargs, struct value **args, CORE_ADDR sp, | |
501 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 502 | { |
386c036b MK |
503 | CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8)); |
504 | ||
505 | /* Set return address. */ | |
506 | regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); | |
507 | ||
508 | /* Set up function arguments. */ | |
509 | sp = sparc32_store_arguments (regcache, nargs, args, sp, | |
510 | struct_return, struct_addr); | |
511 | ||
512 | /* Allocate the 16-word window save area. */ | |
513 | sp -= 16 * 4; | |
c906108c | 514 | |
386c036b MK |
515 | /* Stack should be doubleword aligned at this point. */ |
516 | gdb_assert (sp % 8 == 0); | |
c906108c | 517 | |
386c036b MK |
518 | /* Finally, update the stack pointer. */ |
519 | regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); | |
520 | ||
521 | return sp; | |
522 | } | |
523 | \f | |
c906108c | 524 | |
386c036b MK |
525 | /* Use the program counter to determine the contents and size of a |
526 | breakpoint instruction. Return a pointer to a string of bytes that | |
527 | encode a breakpoint instruction, store the length of the string in | |
528 | *LEN and optionally adjust *PC to point to the correct memory | |
529 | location for inserting the breakpoint. */ | |
530 | ||
e1613aba | 531 | static const gdb_byte * |
386c036b MK |
532 | sparc_breakpoint_from_pc (CORE_ADDR *pc, int *len) |
533 | { | |
864a1a37 | 534 | static const gdb_byte break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; |
c5aa993b | 535 | |
386c036b MK |
536 | *len = sizeof (break_insn); |
537 | return break_insn; | |
c906108c | 538 | } |
386c036b | 539 | \f |
c906108c | 540 | |
386c036b | 541 | /* Allocate and initialize a frame cache. */ |
c906108c | 542 | |
386c036b MK |
543 | static struct sparc_frame_cache * |
544 | sparc_alloc_frame_cache (void) | |
545 | { | |
546 | struct sparc_frame_cache *cache; | |
547 | int i; | |
c906108c | 548 | |
386c036b | 549 | cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); |
c906108c | 550 | |
386c036b MK |
551 | /* Base address. */ |
552 | cache->base = 0; | |
553 | cache->pc = 0; | |
c906108c | 554 | |
386c036b MK |
555 | /* Frameless until proven otherwise. */ |
556 | cache->frameless_p = 1; | |
557 | ||
558 | cache->struct_return_p = 0; | |
559 | ||
560 | return cache; | |
561 | } | |
562 | ||
b0b92586 JB |
563 | /* GCC generates several well-known sequences of instructions at the begining |
564 | of each function prologue when compiling with -fstack-check. If one of | |
565 | such sequences starts at START_PC, then return the address of the | |
566 | instruction immediately past this sequence. Otherwise, return START_PC. */ | |
567 | ||
568 | static CORE_ADDR | |
569 | sparc_skip_stack_check (const CORE_ADDR start_pc) | |
570 | { | |
571 | CORE_ADDR pc = start_pc; | |
572 | unsigned long insn; | |
573 | int offset_stack_checking_sequence = 0; | |
574 | ||
575 | /* With GCC, all stack checking sequences begin with the same two | |
576 | instructions. */ | |
577 | ||
578 | /* sethi <some immediate>,%g1 */ | |
579 | insn = sparc_fetch_instruction (pc); | |
580 | pc = pc + 4; | |
581 | if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1)) | |
582 | return start_pc; | |
583 | ||
584 | /* sub %sp, %g1, %g1 */ | |
585 | insn = sparc_fetch_instruction (pc); | |
586 | pc = pc + 4; | |
587 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) | |
588 | && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1)) | |
589 | return start_pc; | |
590 | ||
591 | insn = sparc_fetch_instruction (pc); | |
592 | pc = pc + 4; | |
593 | ||
594 | /* First possible sequence: | |
595 | [first two instructions above] | |
596 | clr [%g1 - some immediate] */ | |
597 | ||
598 | /* clr [%g1 - some immediate] */ | |
599 | if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
600 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
601 | { | |
602 | /* Valid stack-check sequence, return the new PC. */ | |
603 | return pc; | |
604 | } | |
605 | ||
606 | /* Second possible sequence: A small number of probes. | |
607 | [first two instructions above] | |
608 | clr [%g1] | |
609 | add %g1, -<some immediate>, %g1 | |
610 | clr [%g1] | |
611 | [repeat the two instructions above any (small) number of times] | |
612 | clr [%g1 - some immediate] */ | |
613 | ||
614 | /* clr [%g1] */ | |
615 | else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
616 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
617 | { | |
618 | while (1) | |
619 | { | |
620 | /* add %g1, -<some immediate>, %g1 */ | |
621 | insn = sparc_fetch_instruction (pc); | |
622 | pc = pc + 4; | |
623 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
624 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
625 | break; | |
626 | ||
627 | /* clr [%g1] */ | |
628 | insn = sparc_fetch_instruction (pc); | |
629 | pc = pc + 4; | |
630 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
631 | && X_RD (insn) == 0 && X_RS1 (insn) == 1)) | |
632 | return start_pc; | |
633 | } | |
634 | ||
635 | /* clr [%g1 - some immediate] */ | |
636 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
637 | && X_RS1 (insn) == 1 && X_RD (insn) == 0)) | |
638 | return start_pc; | |
639 | ||
640 | /* We found a valid stack-check sequence, return the new PC. */ | |
641 | return pc; | |
642 | } | |
643 | ||
644 | /* Third sequence: A probing loop. | |
645 | [first two instructions above] | |
646 | sethi <some immediate>, %g4 | |
647 | sub %g1, %g4, %g4 | |
648 | cmp %g1, %g4 | |
649 | be <disp> | |
650 | add %g1, -<some immediate>, %g1 | |
651 | ba <disp> | |
652 | clr [%g1] | |
653 | clr [%g4 - some immediate] */ | |
654 | ||
655 | /* sethi <some immediate>, %g4 */ | |
656 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) | |
657 | { | |
658 | /* sub %g1, %g4, %g4 */ | |
659 | insn = sparc_fetch_instruction (pc); | |
660 | pc = pc + 4; | |
661 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) | |
662 | && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
663 | return start_pc; | |
664 | ||
665 | /* cmp %g1, %g4 */ | |
666 | insn = sparc_fetch_instruction (pc); | |
667 | pc = pc + 4; | |
668 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn) | |
669 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
670 | return start_pc; | |
671 | ||
672 | /* be <disp> */ | |
673 | insn = sparc_fetch_instruction (pc); | |
674 | pc = pc + 4; | |
675 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1)) | |
676 | return start_pc; | |
677 | ||
678 | /* add %g1, -<some immediate>, %g1 */ | |
679 | insn = sparc_fetch_instruction (pc); | |
680 | pc = pc + 4; | |
681 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
682 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
683 | return start_pc; | |
684 | ||
685 | /* ba <disp> */ | |
686 | insn = sparc_fetch_instruction (pc); | |
687 | pc = pc + 4; | |
688 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8)) | |
689 | return start_pc; | |
690 | ||
691 | /* clr [%g1] */ | |
692 | insn = sparc_fetch_instruction (pc); | |
693 | pc = pc + 4; | |
694 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
695 | && X_RD (insn) == 0 && X_RS1 (insn) == 1)) | |
696 | return start_pc; | |
697 | ||
698 | /* clr [%g4 - some immediate] */ | |
699 | insn = sparc_fetch_instruction (pc); | |
700 | pc = pc + 4; | |
701 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
702 | && X_RS1 (insn) == 4 && X_RD (insn) == 0)) | |
703 | return start_pc; | |
704 | ||
705 | /* We found a valid stack-check sequence, return the new PC. */ | |
706 | return pc; | |
707 | } | |
708 | ||
709 | /* No stack check code in our prologue, return the start_pc. */ | |
710 | return start_pc; | |
711 | } | |
712 | ||
386c036b MK |
713 | CORE_ADDR |
714 | sparc_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, | |
715 | struct sparc_frame_cache *cache) | |
c906108c | 716 | { |
386c036b MK |
717 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
718 | unsigned long insn; | |
719 | int offset = 0; | |
c906108c | 720 | int dest = -1; |
c906108c | 721 | |
b0b92586 JB |
722 | pc = sparc_skip_stack_check (pc); |
723 | ||
386c036b MK |
724 | if (current_pc <= pc) |
725 | return current_pc; | |
726 | ||
727 | /* We have to handle to "Procedure Linkage Table" (PLT) special. On | |
728 | SPARC the linker usually defines a symbol (typically | |
729 | _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. | |
730 | This symbol makes us end up here with PC pointing at the start of | |
731 | the PLT and CURRENT_PC probably pointing at a PLT entry. If we | |
732 | would do our normal prologue analysis, we would probably conclude | |
733 | that we've got a frame when in reality we don't, since the | |
734 | dynamic linker patches up the first PLT with some code that | |
735 | starts with a SAVE instruction. Patch up PC such that it points | |
736 | at the start of our PLT entry. */ | |
737 | if (tdep->plt_entry_size > 0 && in_plt_section (current_pc, NULL)) | |
738 | pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); | |
c906108c | 739 | |
386c036b MK |
740 | insn = sparc_fetch_instruction (pc); |
741 | ||
742 | /* Recognize a SETHI insn and record its destination. */ | |
743 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) | |
c906108c SS |
744 | { |
745 | dest = X_RD (insn); | |
386c036b MK |
746 | offset += 4; |
747 | ||
748 | insn = sparc_fetch_instruction (pc + 4); | |
c906108c SS |
749 | } |
750 | ||
386c036b MK |
751 | /* Allow for an arithmetic operation on DEST or %g1. */ |
752 | if (X_OP (insn) == 2 && X_I (insn) | |
c906108c SS |
753 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) |
754 | { | |
386c036b | 755 | offset += 4; |
c906108c | 756 | |
386c036b | 757 | insn = sparc_fetch_instruction (pc + 8); |
c906108c | 758 | } |
c906108c | 759 | |
386c036b MK |
760 | /* Check for the SAVE instruction that sets up the frame. */ |
761 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) | |
c906108c | 762 | { |
386c036b MK |
763 | cache->frameless_p = 0; |
764 | return pc + offset + 4; | |
c906108c SS |
765 | } |
766 | ||
767 | return pc; | |
768 | } | |
769 | ||
386c036b MK |
770 | static CORE_ADDR |
771 | sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
772 | { | |
773 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
774 | return frame_unwind_register_unsigned (next_frame, tdep->pc_regnum); | |
775 | } | |
776 | ||
777 | /* Return PC of first real instruction of the function starting at | |
778 | START_PC. */ | |
f510d44e | 779 | |
386c036b MK |
780 | static CORE_ADDR |
781 | sparc32_skip_prologue (CORE_ADDR start_pc) | |
c906108c | 782 | { |
f510d44e DM |
783 | struct symtab_and_line sal; |
784 | CORE_ADDR func_start, func_end; | |
386c036b | 785 | struct sparc_frame_cache cache; |
f510d44e DM |
786 | |
787 | /* This is the preferred method, find the end of the prologue by | |
788 | using the debugging information. */ | |
789 | if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) | |
790 | { | |
791 | sal = find_pc_line (func_start, 0); | |
792 | ||
793 | if (sal.end < func_end | |
794 | && start_pc <= sal.end) | |
795 | return sal.end; | |
796 | } | |
797 | ||
075ccec8 MK |
798 | start_pc = sparc_analyze_prologue (start_pc, 0xffffffffUL, &cache); |
799 | ||
800 | /* The psABI says that "Although the first 6 words of arguments | |
801 | reside in registers, the standard stack frame reserves space for | |
802 | them.". It also suggests that a function may use that space to | |
803 | "write incoming arguments 0 to 5" into that space, and that's | |
804 | indeed what GCC seems to be doing. In that case GCC will | |
805 | generate debug information that points to the stack slots instead | |
806 | of the registers, so we should consider the instructions that | |
807 | write out these incoming arguments onto the stack. Of course we | |
808 | only need to do this if we have a stack frame. */ | |
809 | ||
810 | while (!cache.frameless_p) | |
811 | { | |
812 | unsigned long insn = sparc_fetch_instruction (start_pc); | |
813 | ||
814 | /* Recognize instructions that store incoming arguments in | |
815 | %i0...%i5 into the corresponding stack slot. */ | |
816 | if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 && X_I (insn) | |
817 | && (X_RD (insn) >= 24 && X_RD (insn) <= 29) && X_RS1 (insn) == 30 | |
818 | && X_SIMM13 (insn) == 68 + (X_RD (insn) - 24) * 4) | |
819 | { | |
820 | start_pc += 4; | |
821 | continue; | |
822 | } | |
823 | ||
824 | break; | |
825 | } | |
826 | ||
827 | return start_pc; | |
c906108c SS |
828 | } |
829 | ||
386c036b | 830 | /* Normal frames. */ |
9319a2fe | 831 | |
386c036b MK |
832 | struct sparc_frame_cache * |
833 | sparc_frame_cache (struct frame_info *next_frame, void **this_cache) | |
9319a2fe | 834 | { |
386c036b | 835 | struct sparc_frame_cache *cache; |
9319a2fe | 836 | |
386c036b MK |
837 | if (*this_cache) |
838 | return *this_cache; | |
c906108c | 839 | |
386c036b MK |
840 | cache = sparc_alloc_frame_cache (); |
841 | *this_cache = cache; | |
c906108c | 842 | |
93d42b30 | 843 | cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME); |
386c036b | 844 | if (cache->pc != 0) |
93d42b30 | 845 | sparc_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache); |
386c036b MK |
846 | |
847 | if (cache->frameless_p) | |
c906108c | 848 | { |
cbeae229 MK |
849 | /* This function is frameless, so %fp (%i6) holds the frame |
850 | pointer for our calling frame. Use %sp (%o6) as this frame's | |
851 | base address. */ | |
852 | cache->base = | |
853 | frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM); | |
854 | } | |
855 | else | |
856 | { | |
857 | /* For normal frames, %fp (%i6) holds the frame pointer, the | |
858 | base address for the current stack frame. */ | |
859 | cache->base = | |
860 | frame_unwind_register_unsigned (next_frame, SPARC_FP_REGNUM); | |
c906108c | 861 | } |
c906108c | 862 | |
5b2d44a0 MK |
863 | if (cache->base & 1) |
864 | cache->base += BIAS; | |
865 | ||
386c036b | 866 | return cache; |
c906108c | 867 | } |
c906108c | 868 | |
aff37fc1 DM |
869 | static int |
870 | sparc32_struct_return_from_sym (struct symbol *sym) | |
871 | { | |
872 | struct type *type = check_typedef (SYMBOL_TYPE (sym)); | |
873 | enum type_code code = TYPE_CODE (type); | |
874 | ||
875 | if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) | |
876 | { | |
877 | type = check_typedef (TYPE_TARGET_TYPE (type)); | |
878 | if (sparc_structure_or_union_p (type) | |
879 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
880 | return 1; | |
881 | } | |
882 | ||
883 | return 0; | |
884 | } | |
885 | ||
386c036b MK |
886 | struct sparc_frame_cache * |
887 | sparc32_frame_cache (struct frame_info *next_frame, void **this_cache) | |
c906108c | 888 | { |
386c036b MK |
889 | struct sparc_frame_cache *cache; |
890 | struct symbol *sym; | |
c906108c | 891 | |
386c036b MK |
892 | if (*this_cache) |
893 | return *this_cache; | |
c906108c | 894 | |
386c036b | 895 | cache = sparc_frame_cache (next_frame, this_cache); |
c906108c | 896 | |
386c036b MK |
897 | sym = find_pc_function (cache->pc); |
898 | if (sym) | |
c906108c | 899 | { |
aff37fc1 | 900 | cache->struct_return_p = sparc32_struct_return_from_sym (sym); |
c906108c | 901 | } |
5465445a JB |
902 | else |
903 | { | |
904 | /* There is no debugging information for this function to | |
905 | help us determine whether this function returns a struct | |
906 | or not. So we rely on another heuristic which is to check | |
907 | the instruction at the return address and see if this is | |
908 | an "unimp" instruction. If it is, then it is a struct-return | |
909 | function. */ | |
910 | CORE_ADDR pc; | |
911 | int regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM; | |
912 | ||
913 | pc = frame_unwind_register_unsigned (next_frame, regnum) + 8; | |
914 | if (sparc_is_unimp_insn (pc)) | |
915 | cache->struct_return_p = 1; | |
916 | } | |
c906108c | 917 | |
386c036b MK |
918 | return cache; |
919 | } | |
920 | ||
921 | static void | |
922 | sparc32_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
923 | struct frame_id *this_id) | |
924 | { | |
925 | struct sparc_frame_cache *cache = | |
926 | sparc32_frame_cache (next_frame, this_cache); | |
927 | ||
928 | /* This marks the outermost frame. */ | |
929 | if (cache->base == 0) | |
930 | return; | |
931 | ||
932 | (*this_id) = frame_id_build (cache->base, cache->pc); | |
933 | } | |
c906108c | 934 | |
386c036b MK |
935 | static void |
936 | sparc32_frame_prev_register (struct frame_info *next_frame, void **this_cache, | |
937 | int regnum, int *optimizedp, | |
938 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
47ef841b | 939 | int *realnump, gdb_byte *valuep) |
386c036b MK |
940 | { |
941 | struct sparc_frame_cache *cache = | |
942 | sparc32_frame_cache (next_frame, this_cache); | |
c906108c | 943 | |
386c036b | 944 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) |
c906108c | 945 | { |
386c036b MK |
946 | *optimizedp = 0; |
947 | *lvalp = not_lval; | |
948 | *addrp = 0; | |
949 | *realnump = -1; | |
950 | if (valuep) | |
c906108c | 951 | { |
386c036b MK |
952 | CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; |
953 | ||
954 | /* If this functions has a Structure, Union or | |
955 | Quad-Precision return value, we have to skip the UNIMP | |
956 | instruction that encodes the size of the structure. */ | |
957 | if (cache->struct_return_p) | |
958 | pc += 4; | |
959 | ||
960 | regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM; | |
961 | pc += frame_unwind_register_unsigned (next_frame, regnum) + 8; | |
962 | store_unsigned_integer (valuep, 4, pc); | |
c906108c | 963 | } |
c906108c SS |
964 | return; |
965 | } | |
966 | ||
42cdca6c MK |
967 | /* Handle StackGhost. */ |
968 | { | |
969 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
970 | ||
971 | if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM) | |
972 | { | |
973 | *optimizedp = 0; | |
974 | *lvalp = not_lval; | |
975 | *addrp = 0; | |
976 | *realnump = -1; | |
977 | if (valuep) | |
978 | { | |
979 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; | |
7d34766b | 980 | ULONGEST i7; |
42cdca6c MK |
981 | |
982 | /* Read the value in from memory. */ | |
7d34766b MK |
983 | i7 = get_frame_memory_unsigned (next_frame, addr, 4); |
984 | store_unsigned_integer (valuep, 4, i7 ^ wcookie); | |
42cdca6c MK |
985 | } |
986 | return; | |
987 | } | |
988 | } | |
989 | ||
386c036b MK |
990 | /* The previous frame's `local' and `in' registers have been saved |
991 | in the register save area. */ | |
992 | if (!cache->frameless_p | |
993 | && regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) | |
c906108c | 994 | { |
386c036b MK |
995 | *optimizedp = 0; |
996 | *lvalp = lval_memory; | |
997 | *addrp = cache->base + (regnum - SPARC_L0_REGNUM) * 4; | |
998 | *realnump = -1; | |
999 | if (valuep) | |
c906108c | 1000 | { |
386c036b MK |
1001 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
1002 | ||
1003 | /* Read the value in from memory. */ | |
1004 | read_memory (*addrp, valuep, register_size (gdbarch, regnum)); | |
c906108c | 1005 | } |
386c036b MK |
1006 | return; |
1007 | } | |
c906108c | 1008 | |
386c036b MK |
1009 | /* The previous frame's `out' registers are accessable as the |
1010 | current frame's `in' registers. */ | |
1011 | if (!cache->frameless_p | |
1012 | && regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM) | |
1013 | regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); | |
5af923b0 | 1014 | |
00b25ff3 AC |
1015 | *optimizedp = 0; |
1016 | *lvalp = lval_register; | |
1017 | *addrp = 0; | |
1018 | *realnump = regnum; | |
1019 | if (valuep) | |
1020 | frame_unwind_register (next_frame, (*realnump), valuep); | |
386c036b | 1021 | } |
c906108c | 1022 | |
386c036b MK |
1023 | static const struct frame_unwind sparc32_frame_unwind = |
1024 | { | |
1025 | NORMAL_FRAME, | |
1026 | sparc32_frame_this_id, | |
1027 | sparc32_frame_prev_register | |
1028 | }; | |
1029 | ||
1030 | static const struct frame_unwind * | |
1031 | sparc32_frame_sniffer (struct frame_info *next_frame) | |
1032 | { | |
1033 | return &sparc32_frame_unwind; | |
c906108c | 1034 | } |
386c036b | 1035 | \f |
c906108c | 1036 | |
386c036b MK |
1037 | static CORE_ADDR |
1038 | sparc32_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
1039 | { | |
1040 | struct sparc_frame_cache *cache = | |
1041 | sparc32_frame_cache (next_frame, this_cache); | |
c906108c | 1042 | |
386c036b MK |
1043 | return cache->base; |
1044 | } | |
c906108c | 1045 | |
386c036b MK |
1046 | static const struct frame_base sparc32_frame_base = |
1047 | { | |
1048 | &sparc32_frame_unwind, | |
1049 | sparc32_frame_base_address, | |
1050 | sparc32_frame_base_address, | |
1051 | sparc32_frame_base_address | |
1052 | }; | |
c906108c | 1053 | |
386c036b MK |
1054 | static struct frame_id |
1055 | sparc_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1056 | { | |
1057 | CORE_ADDR sp; | |
5af923b0 | 1058 | |
386c036b | 1059 | sp = frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM); |
5b2d44a0 MK |
1060 | if (sp & 1) |
1061 | sp += BIAS; | |
386c036b MK |
1062 | return frame_id_build (sp, frame_pc_unwind (next_frame)); |
1063 | } | |
1064 | \f | |
c906108c | 1065 | |
386c036b MK |
1066 | /* Extract from an array REGBUF containing the (raw) register state, a |
1067 | function return value of TYPE, and copy that into VALBUF. */ | |
5af923b0 | 1068 | |
386c036b MK |
1069 | static void |
1070 | sparc32_extract_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1071 | gdb_byte *valbuf) |
386c036b MK |
1072 | { |
1073 | int len = TYPE_LENGTH (type); | |
e1613aba | 1074 | gdb_byte buf[8]; |
c906108c | 1075 | |
386c036b MK |
1076 | gdb_assert (!sparc_structure_or_union_p (type)); |
1077 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 1078 | |
386c036b | 1079 | if (sparc_floating_p (type)) |
5af923b0 | 1080 | { |
386c036b MK |
1081 | /* Floating return values. */ |
1082 | regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf); | |
1083 | if (len > 4) | |
1084 | regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4); | |
1085 | memcpy (valbuf, buf, len); | |
5af923b0 MS |
1086 | } |
1087 | else | |
1088 | { | |
386c036b MK |
1089 | /* Integral and pointer return values. */ |
1090 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
c906108c | 1091 | |
386c036b MK |
1092 | regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); |
1093 | if (len > 4) | |
1094 | { | |
1095 | regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4); | |
1096 | gdb_assert (len == 8); | |
1097 | memcpy (valbuf, buf, 8); | |
1098 | } | |
1099 | else | |
1100 | { | |
1101 | /* Just stripping off any unused bytes should preserve the | |
1102 | signed-ness just fine. */ | |
1103 | memcpy (valbuf, buf + 4 - len, len); | |
1104 | } | |
1105 | } | |
1106 | } | |
c906108c | 1107 | |
386c036b MK |
1108 | /* Write into the appropriate registers a function return value stored |
1109 | in VALBUF of type TYPE. */ | |
c906108c | 1110 | |
386c036b MK |
1111 | static void |
1112 | sparc32_store_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1113 | const gdb_byte *valbuf) |
386c036b MK |
1114 | { |
1115 | int len = TYPE_LENGTH (type); | |
e1613aba | 1116 | gdb_byte buf[8]; |
c906108c | 1117 | |
386c036b MK |
1118 | gdb_assert (!sparc_structure_or_union_p (type)); |
1119 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 1120 | |
386c036b MK |
1121 | if (sparc_floating_p (type)) |
1122 | { | |
1123 | /* Floating return values. */ | |
1124 | memcpy (buf, valbuf, len); | |
1125 | regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf); | |
1126 | if (len > 4) | |
1127 | regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4); | |
1128 | } | |
1129 | else | |
c906108c | 1130 | { |
386c036b MK |
1131 | /* Integral and pointer return values. */ |
1132 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
1133 | ||
1134 | if (len > 4) | |
2757dd86 | 1135 | { |
386c036b MK |
1136 | gdb_assert (len == 8); |
1137 | memcpy (buf, valbuf, 8); | |
1138 | regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4); | |
2757dd86 AC |
1139 | } |
1140 | else | |
1141 | { | |
386c036b MK |
1142 | /* ??? Do we need to do any sign-extension here? */ |
1143 | memcpy (buf + 4 - len, valbuf, len); | |
2757dd86 | 1144 | } |
386c036b | 1145 | regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); |
c906108c SS |
1146 | } |
1147 | } | |
1148 | ||
b9d4c5ed MK |
1149 | static enum return_value_convention |
1150 | sparc32_return_value (struct gdbarch *gdbarch, struct type *type, | |
e1613aba MK |
1151 | struct regcache *regcache, gdb_byte *readbuf, |
1152 | const gdb_byte *writebuf) | |
b9d4c5ed | 1153 | { |
0a8f48b9 MK |
1154 | /* The psABI says that "...every stack frame reserves the word at |
1155 | %fp+64. If a function returns a structure, union, or | |
1156 | quad-precision value, this word should hold the address of the | |
1157 | object into which the return value should be copied." This | |
1158 | guarantees that we can always find the return value, not just | |
1159 | before the function returns. */ | |
1160 | ||
b9d4c5ed MK |
1161 | if (sparc_structure_or_union_p (type) |
1162 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
0a8f48b9 MK |
1163 | { |
1164 | if (readbuf) | |
1165 | { | |
1166 | ULONGEST sp; | |
1167 | CORE_ADDR addr; | |
1168 | ||
1169 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1170 | addr = read_memory_unsigned_integer (sp + 64, 4); | |
1171 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
1172 | } | |
1173 | ||
1174 | return RETURN_VALUE_ABI_PRESERVES_ADDRESS; | |
1175 | } | |
b9d4c5ed MK |
1176 | |
1177 | if (readbuf) | |
1178 | sparc32_extract_return_value (type, regcache, readbuf); | |
1179 | if (writebuf) | |
1180 | sparc32_store_return_value (type, regcache, writebuf); | |
1181 | ||
1182 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1183 | } | |
1184 | ||
386c036b MK |
1185 | static int |
1186 | sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) | |
c906108c | 1187 | { |
386c036b MK |
1188 | return (sparc_structure_or_union_p (type) |
1189 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)); | |
1190 | } | |
c906108c | 1191 | |
aff37fc1 DM |
1192 | static int |
1193 | sparc32_dwarf2_struct_return_p (struct frame_info *next_frame) | |
1194 | { | |
93d42b30 | 1195 | CORE_ADDR pc = frame_unwind_address_in_block (next_frame, NORMAL_FRAME); |
aff37fc1 DM |
1196 | struct symbol *sym = find_pc_function (pc); |
1197 | ||
1198 | if (sym) | |
1199 | return sparc32_struct_return_from_sym (sym); | |
1200 | return 0; | |
1201 | } | |
1202 | ||
f5a9b87d DM |
1203 | static void |
1204 | sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 DM |
1205 | struct dwarf2_frame_state_reg *reg, |
1206 | struct frame_info *next_frame) | |
f5a9b87d | 1207 | { |
aff37fc1 DM |
1208 | int off; |
1209 | ||
f5a9b87d DM |
1210 | switch (regnum) |
1211 | { | |
1212 | case SPARC_G0_REGNUM: | |
1213 | /* Since %g0 is always zero, there is no point in saving it, and | |
1214 | people will be inclined omit it from the CFI. Make sure we | |
1215 | don't warn about that. */ | |
1216 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
1217 | break; | |
1218 | case SPARC_SP_REGNUM: | |
1219 | reg->how = DWARF2_FRAME_REG_CFA; | |
1220 | break; | |
1221 | case SPARC32_PC_REGNUM: | |
f5a9b87d DM |
1222 | case SPARC32_NPC_REGNUM: |
1223 | reg->how = DWARF2_FRAME_REG_RA_OFFSET; | |
aff37fc1 DM |
1224 | off = 8; |
1225 | if (sparc32_dwarf2_struct_return_p (next_frame)) | |
1226 | off += 4; | |
1227 | if (regnum == SPARC32_NPC_REGNUM) | |
1228 | off += 4; | |
1229 | reg->loc.offset = off; | |
f5a9b87d DM |
1230 | break; |
1231 | } | |
1232 | } | |
1233 | ||
386c036b MK |
1234 | \f |
1235 | /* The SPARC Architecture doesn't have hardware single-step support, | |
1236 | and most operating systems don't implement it either, so we provide | |
1237 | software single-step mechanism. */ | |
c906108c | 1238 | |
386c036b | 1239 | static CORE_ADDR |
0b1b3e42 | 1240 | sparc_analyze_control_transfer (struct frame_info *frame, |
c893be75 | 1241 | CORE_ADDR pc, CORE_ADDR *npc) |
386c036b MK |
1242 | { |
1243 | unsigned long insn = sparc_fetch_instruction (pc); | |
1244 | int conditional_p = X_COND (insn) & 0x7; | |
1245 | int branch_p = 0; | |
1246 | long offset = 0; /* Must be signed for sign-extend. */ | |
c906108c | 1247 | |
386c036b | 1248 | if (X_OP (insn) == 0 && X_OP2 (insn) == 3 && (insn & 0x1000000) == 0) |
c906108c | 1249 | { |
386c036b MK |
1250 | /* Branch on Integer Register with Prediction (BPr). */ |
1251 | branch_p = 1; | |
1252 | conditional_p = 1; | |
c906108c | 1253 | } |
386c036b | 1254 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) |
c906108c | 1255 | { |
386c036b MK |
1256 | /* Branch on Floating-Point Condition Codes (FBfcc). */ |
1257 | branch_p = 1; | |
1258 | offset = 4 * X_DISP22 (insn); | |
c906108c | 1259 | } |
386c036b MK |
1260 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) |
1261 | { | |
1262 | /* Branch on Floating-Point Condition Codes with Prediction | |
1263 | (FBPfcc). */ | |
1264 | branch_p = 1; | |
1265 | offset = 4 * X_DISP19 (insn); | |
1266 | } | |
1267 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) | |
1268 | { | |
1269 | /* Branch on Integer Condition Codes (Bicc). */ | |
1270 | branch_p = 1; | |
1271 | offset = 4 * X_DISP22 (insn); | |
1272 | } | |
1273 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) | |
c906108c | 1274 | { |
386c036b MK |
1275 | /* Branch on Integer Condition Codes with Prediction (BPcc). */ |
1276 | branch_p = 1; | |
1277 | offset = 4 * X_DISP19 (insn); | |
c906108c | 1278 | } |
c893be75 MK |
1279 | else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a) |
1280 | { | |
1281 | /* Trap instruction (TRAP). */ | |
0b1b3e42 | 1282 | return gdbarch_tdep (get_frame_arch (frame))->step_trap (frame, insn); |
c893be75 | 1283 | } |
386c036b MK |
1284 | |
1285 | /* FIXME: Handle DONE and RETRY instructions. */ | |
1286 | ||
386c036b | 1287 | if (branch_p) |
c906108c | 1288 | { |
386c036b | 1289 | if (conditional_p) |
c906108c | 1290 | { |
386c036b MK |
1291 | /* For conditional branches, return nPC + 4 iff the annul |
1292 | bit is 1. */ | |
1293 | return (X_A (insn) ? *npc + 4 : 0); | |
c906108c SS |
1294 | } |
1295 | else | |
1296 | { | |
386c036b MK |
1297 | /* For unconditional branches, return the target if its |
1298 | specified condition is "always" and return nPC + 4 if the | |
1299 | condition is "never". If the annul bit is 1, set *NPC to | |
1300 | zero. */ | |
1301 | if (X_COND (insn) == 0x0) | |
1302 | pc = *npc, offset = 4; | |
1303 | if (X_A (insn)) | |
1304 | *npc = 0; | |
1305 | ||
1306 | gdb_assert (offset != 0); | |
1307 | return pc + offset; | |
c906108c SS |
1308 | } |
1309 | } | |
386c036b MK |
1310 | |
1311 | return 0; | |
c906108c SS |
1312 | } |
1313 | ||
c893be75 | 1314 | static CORE_ADDR |
0b1b3e42 | 1315 | sparc_step_trap (struct frame_info *frame, unsigned long insn) |
c893be75 MK |
1316 | { |
1317 | return 0; | |
1318 | } | |
1319 | ||
e6590a1b | 1320 | int |
0b1b3e42 | 1321 | sparc_software_single_step (struct frame_info *frame) |
386c036b | 1322 | { |
0b1b3e42 | 1323 | struct gdbarch *arch = get_frame_arch (frame); |
c893be75 | 1324 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
8181d85f | 1325 | CORE_ADDR npc, nnpc; |
c906108c | 1326 | |
e0cd558a | 1327 | CORE_ADDR pc, orig_npc; |
c906108c | 1328 | |
0b1b3e42 UW |
1329 | pc = get_frame_register_unsigned (frame, tdep->pc_regnum); |
1330 | orig_npc = npc = get_frame_register_unsigned (frame, tdep->npc_regnum); | |
c906108c | 1331 | |
e0cd558a | 1332 | /* Analyze the instruction at PC. */ |
0b1b3e42 | 1333 | nnpc = sparc_analyze_control_transfer (frame, pc, &npc); |
e0cd558a UW |
1334 | if (npc != 0) |
1335 | insert_single_step_breakpoint (npc); | |
8181d85f | 1336 | |
e0cd558a UW |
1337 | if (nnpc != 0) |
1338 | insert_single_step_breakpoint (nnpc); | |
c906108c | 1339 | |
e0cd558a UW |
1340 | /* Assert that we have set at least one breakpoint, and that |
1341 | they're not set at the same spot - unless we're going | |
1342 | from here straight to NULL, i.e. a call or jump to 0. */ | |
1343 | gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0); | |
1344 | gdb_assert (nnpc != npc || orig_npc == 0); | |
e6590a1b UW |
1345 | |
1346 | return 1; | |
386c036b MK |
1347 | } |
1348 | ||
1349 | static void | |
1350 | sparc_write_pc (CORE_ADDR pc, ptid_t ptid) | |
1351 | { | |
1352 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1353 | ||
1354 | write_register_pid (tdep->pc_regnum, pc, ptid); | |
1355 | write_register_pid (tdep->npc_regnum, pc + 4, ptid); | |
1356 | } | |
1357 | \f | |
1358 | /* Unglobalize NAME. */ | |
1359 | ||
1360 | char * | |
1361 | sparc_stabs_unglobalize_name (char *name) | |
1362 | { | |
1363 | /* The Sun compilers (Sun ONE Studio, Forte Developer, Sun WorkShop, | |
1364 | SunPRO) convert file static variables into global values, a | |
1365 | process known as globalization. In order to do this, the | |
1366 | compiler will create a unique prefix and prepend it to each file | |
1367 | static variable. For static variables within a function, this | |
1368 | globalization prefix is followed by the function name (nested | |
1369 | static variables within a function are supposed to generate a | |
1370 | warning message, and are left alone). The procedure is | |
1371 | documented in the Stabs Interface Manual, which is distrubuted | |
1372 | with the compilers, although version 4.0 of the manual seems to | |
1373 | be incorrect in some places, at least for SPARC. The | |
1374 | globalization prefix is encoded into an N_OPT stab, with the form | |
1375 | "G=<prefix>". The globalization prefix always seems to start | |
1376 | with a dollar sign '$'; a dot '.' is used as a seperator. So we | |
1377 | simply strip everything up until the last dot. */ | |
c906108c | 1378 | |
386c036b | 1379 | if (name[0] == '$') |
c906108c | 1380 | { |
386c036b MK |
1381 | char *p = strrchr (name, '.'); |
1382 | if (p) | |
1383 | return p + 1; | |
c906108c | 1384 | } |
c906108c | 1385 | |
386c036b MK |
1386 | return name; |
1387 | } | |
1388 | \f | |
5af923b0 | 1389 | |
a54124c5 MK |
1390 | /* Return the appropriate register set for the core section identified |
1391 | by SECT_NAME and SECT_SIZE. */ | |
1392 | ||
1393 | const struct regset * | |
1394 | sparc_regset_from_core_section (struct gdbarch *gdbarch, | |
1395 | const char *sect_name, size_t sect_size) | |
1396 | { | |
1397 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1398 | ||
c558d81a | 1399 | if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset) |
a54124c5 MK |
1400 | return tdep->gregset; |
1401 | ||
c558d81a | 1402 | if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset) |
a54124c5 MK |
1403 | return tdep->fpregset; |
1404 | ||
1405 | return NULL; | |
1406 | } | |
1407 | \f | |
1408 | ||
386c036b MK |
1409 | static struct gdbarch * |
1410 | sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1411 | { | |
1412 | struct gdbarch_tdep *tdep; | |
1413 | struct gdbarch *gdbarch; | |
c906108c | 1414 | |
386c036b MK |
1415 | /* If there is already a candidate, use it. */ |
1416 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1417 | if (arches != NULL) | |
1418 | return arches->gdbarch; | |
c906108c | 1419 | |
386c036b MK |
1420 | /* Allocate space for the new architecture. */ |
1421 | tdep = XMALLOC (struct gdbarch_tdep); | |
1422 | gdbarch = gdbarch_alloc (&info, tdep); | |
5af923b0 | 1423 | |
386c036b MK |
1424 | tdep->pc_regnum = SPARC32_PC_REGNUM; |
1425 | tdep->npc_regnum = SPARC32_NPC_REGNUM; | |
a54124c5 | 1426 | tdep->gregset = NULL; |
c558d81a | 1427 | tdep->sizeof_gregset = 0; |
a54124c5 | 1428 | tdep->fpregset = NULL; |
c558d81a | 1429 | tdep->sizeof_fpregset = 0; |
386c036b | 1430 | tdep->plt_entry_size = 0; |
c893be75 | 1431 | tdep->step_trap = sparc_step_trap; |
386c036b MK |
1432 | |
1433 | set_gdbarch_long_double_bit (gdbarch, 128); | |
8da61cc4 | 1434 | set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad); |
386c036b MK |
1435 | |
1436 | set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); | |
1437 | set_gdbarch_register_name (gdbarch, sparc32_register_name); | |
1438 | set_gdbarch_register_type (gdbarch, sparc32_register_type); | |
1439 | set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); | |
1440 | set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); | |
1441 | set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); | |
1442 | ||
1443 | /* Register numbers of various important registers. */ | |
1444 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ | |
1445 | set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ | |
1446 | set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ | |
1447 | ||
1448 | /* Call dummy code. */ | |
1449 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); | |
1450 | set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); | |
1451 | set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); | |
1452 | ||
b9d4c5ed | 1453 | set_gdbarch_return_value (gdbarch, sparc32_return_value); |
386c036b MK |
1454 | set_gdbarch_stabs_argument_has_addr |
1455 | (gdbarch, sparc32_stabs_argument_has_addr); | |
1456 | ||
1457 | set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); | |
1458 | ||
1459 | /* Stack grows downward. */ | |
1460 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
c906108c | 1461 | |
386c036b | 1462 | set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc); |
c906108c | 1463 | |
386c036b | 1464 | set_gdbarch_frame_args_skip (gdbarch, 8); |
5af923b0 | 1465 | |
386c036b | 1466 | set_gdbarch_print_insn (gdbarch, print_insn_sparc); |
c906108c | 1467 | |
386c036b MK |
1468 | set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); |
1469 | set_gdbarch_write_pc (gdbarch, sparc_write_pc); | |
c906108c | 1470 | |
386c036b | 1471 | set_gdbarch_unwind_dummy_id (gdbarch, sparc_unwind_dummy_id); |
c906108c | 1472 | |
386c036b | 1473 | set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc); |
c906108c | 1474 | |
386c036b MK |
1475 | frame_base_set_default (gdbarch, &sparc32_frame_base); |
1476 | ||
f5a9b87d DM |
1477 | /* Hook in the DWARF CFI frame unwinder. */ |
1478 | dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg); | |
1479 | /* FIXME: kettenis/20050423: Don't enable the unwinder until the | |
1480 | StackGhost issues have been resolved. */ | |
1481 | ||
b2a0b9b2 DM |
1482 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1483 | gdbarch_init_osabi (info, gdbarch); | |
1484 | ||
386c036b | 1485 | frame_unwind_append_sniffer (gdbarch, sparc32_frame_sniffer); |
c906108c | 1486 | |
a54124c5 | 1487 | /* If we have register sets, enable the generic core file support. */ |
4c72d57a | 1488 | if (tdep->gregset) |
a54124c5 MK |
1489 | set_gdbarch_regset_from_core_section (gdbarch, |
1490 | sparc_regset_from_core_section); | |
1491 | ||
386c036b MK |
1492 | return gdbarch; |
1493 | } | |
1494 | \f | |
1495 | /* Helper functions for dealing with register windows. */ | |
1496 | ||
1497 | void | |
1498 | sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) | |
c906108c | 1499 | { |
386c036b | 1500 | int offset = 0; |
e1613aba | 1501 | gdb_byte buf[8]; |
386c036b MK |
1502 | int i; |
1503 | ||
1504 | if (sp & 1) | |
1505 | { | |
1506 | /* Registers are 64-bit. */ | |
1507 | sp += BIAS; | |
c906108c | 1508 | |
386c036b MK |
1509 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1510 | { | |
1511 | if (regnum == i || regnum == -1) | |
1512 | { | |
1513 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); | |
f700a364 MK |
1514 | |
1515 | /* Handle StackGhost. */ | |
1516 | if (i == SPARC_I7_REGNUM) | |
1517 | { | |
1518 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
1519 | ULONGEST i7 = extract_unsigned_integer (buf + offset, 8); | |
1520 | ||
1521 | store_unsigned_integer (buf + offset, 8, i7 ^ wcookie); | |
1522 | } | |
1523 | ||
386c036b MK |
1524 | regcache_raw_supply (regcache, i, buf); |
1525 | } | |
1526 | } | |
1527 | } | |
1528 | else | |
c906108c | 1529 | { |
386c036b MK |
1530 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1531 | pointer. */ | |
1532 | sp &= 0xffffffffUL; | |
c906108c | 1533 | |
386c036b MK |
1534 | /* Clear out the top half of the temporary buffer, and put the |
1535 | register value in the bottom half if we're in 64-bit mode. */ | |
1536 | if (gdbarch_ptr_bit (current_gdbarch) == 64) | |
c906108c | 1537 | { |
386c036b MK |
1538 | memset (buf, 0, 4); |
1539 | offset = 4; | |
1540 | } | |
c906108c | 1541 | |
386c036b MK |
1542 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1543 | { | |
1544 | if (regnum == i || regnum == -1) | |
1545 | { | |
1546 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), | |
1547 | buf + offset, 4); | |
42cdca6c MK |
1548 | |
1549 | /* Handle StackGhost. */ | |
1550 | if (i == SPARC_I7_REGNUM) | |
1551 | { | |
1552 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
7d34766b | 1553 | ULONGEST i7 = extract_unsigned_integer (buf + offset, 4); |
42cdca6c | 1554 | |
7d34766b | 1555 | store_unsigned_integer (buf + offset, 4, i7 ^ wcookie); |
42cdca6c MK |
1556 | } |
1557 | ||
386c036b MK |
1558 | regcache_raw_supply (regcache, i, buf); |
1559 | } | |
c906108c SS |
1560 | } |
1561 | } | |
c906108c | 1562 | } |
c906108c SS |
1563 | |
1564 | void | |
386c036b MK |
1565 | sparc_collect_rwindow (const struct regcache *regcache, |
1566 | CORE_ADDR sp, int regnum) | |
c906108c | 1567 | { |
386c036b | 1568 | int offset = 0; |
e1613aba | 1569 | gdb_byte buf[8]; |
386c036b | 1570 | int i; |
5af923b0 | 1571 | |
386c036b | 1572 | if (sp & 1) |
5af923b0 | 1573 | { |
386c036b MK |
1574 | /* Registers are 64-bit. */ |
1575 | sp += BIAS; | |
c906108c | 1576 | |
386c036b MK |
1577 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1578 | { | |
1579 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1580 | { | |
1581 | regcache_raw_collect (regcache, i, buf); | |
f700a364 MK |
1582 | |
1583 | /* Handle StackGhost. */ | |
1584 | if (i == SPARC_I7_REGNUM) | |
1585 | { | |
1586 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
1587 | ULONGEST i7 = extract_unsigned_integer (buf + offset, 8); | |
1588 | ||
1589 | store_unsigned_integer (buf, 8, i7 ^ wcookie); | |
1590 | } | |
1591 | ||
386c036b MK |
1592 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); |
1593 | } | |
1594 | } | |
5af923b0 MS |
1595 | } |
1596 | else | |
1597 | { | |
386c036b MK |
1598 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1599 | pointer. */ | |
1600 | sp &= 0xffffffffUL; | |
1601 | ||
1602 | /* Only use the bottom half if we're in 64-bit mode. */ | |
1603 | if (gdbarch_ptr_bit (current_gdbarch) == 64) | |
1604 | offset = 4; | |
1605 | ||
1606 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1607 | { | |
1608 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1609 | { | |
1610 | regcache_raw_collect (regcache, i, buf); | |
42cdca6c MK |
1611 | |
1612 | /* Handle StackGhost. */ | |
1613 | if (i == SPARC_I7_REGNUM) | |
1614 | { | |
1615 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
7d34766b | 1616 | ULONGEST i7 = extract_unsigned_integer (buf + offset, 4); |
42cdca6c | 1617 | |
7d34766b | 1618 | store_unsigned_integer (buf + offset, 4, i7 ^ wcookie); |
42cdca6c MK |
1619 | } |
1620 | ||
386c036b MK |
1621 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), |
1622 | buf + offset, 4); | |
1623 | } | |
1624 | } | |
5af923b0 | 1625 | } |
c906108c SS |
1626 | } |
1627 | ||
386c036b MK |
1628 | /* Helper functions for dealing with register sets. */ |
1629 | ||
c906108c | 1630 | void |
386c036b MK |
1631 | sparc32_supply_gregset (const struct sparc_gregset *gregset, |
1632 | struct regcache *regcache, | |
1633 | int regnum, const void *gregs) | |
c906108c | 1634 | { |
e1613aba | 1635 | const gdb_byte *regs = gregs; |
386c036b | 1636 | int i; |
5af923b0 | 1637 | |
386c036b MK |
1638 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1639 | regcache_raw_supply (regcache, SPARC32_PSR_REGNUM, | |
1640 | regs + gregset->r_psr_offset); | |
c906108c | 1641 | |
386c036b MK |
1642 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1643 | regcache_raw_supply (regcache, SPARC32_PC_REGNUM, | |
1644 | regs + gregset->r_pc_offset); | |
5af923b0 | 1645 | |
386c036b MK |
1646 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) |
1647 | regcache_raw_supply (regcache, SPARC32_NPC_REGNUM, | |
1648 | regs + gregset->r_npc_offset); | |
5af923b0 | 1649 | |
386c036b MK |
1650 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1651 | regcache_raw_supply (regcache, SPARC32_Y_REGNUM, | |
1652 | regs + gregset->r_y_offset); | |
5af923b0 | 1653 | |
386c036b MK |
1654 | if (regnum == SPARC_G0_REGNUM || regnum == -1) |
1655 | regcache_raw_supply (regcache, SPARC_G0_REGNUM, NULL); | |
5af923b0 | 1656 | |
386c036b | 1657 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) |
c906108c | 1658 | { |
386c036b MK |
1659 | int offset = gregset->r_g1_offset; |
1660 | ||
1661 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1662 | { | |
1663 | if (regnum == i || regnum == -1) | |
1664 | regcache_raw_supply (regcache, i, regs + offset); | |
1665 | offset += 4; | |
1666 | } | |
c906108c | 1667 | } |
386c036b MK |
1668 | |
1669 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
c906108c | 1670 | { |
386c036b MK |
1671 | /* Not all of the register set variants include Locals and |
1672 | Inputs. For those that don't, we read them off the stack. */ | |
1673 | if (gregset->r_l0_offset == -1) | |
1674 | { | |
1675 | ULONGEST sp; | |
1676 | ||
1677 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1678 | sparc_supply_rwindow (regcache, sp, regnum); | |
1679 | } | |
1680 | else | |
1681 | { | |
1682 | int offset = gregset->r_l0_offset; | |
1683 | ||
1684 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1685 | { | |
1686 | if (regnum == i || regnum == -1) | |
1687 | regcache_raw_supply (regcache, i, regs + offset); | |
1688 | offset += 4; | |
1689 | } | |
1690 | } | |
c906108c SS |
1691 | } |
1692 | } | |
1693 | ||
c5aa993b | 1694 | void |
386c036b MK |
1695 | sparc32_collect_gregset (const struct sparc_gregset *gregset, |
1696 | const struct regcache *regcache, | |
1697 | int regnum, void *gregs) | |
c906108c | 1698 | { |
e1613aba | 1699 | gdb_byte *regs = gregs; |
386c036b | 1700 | int i; |
c5aa993b | 1701 | |
386c036b MK |
1702 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1703 | regcache_raw_collect (regcache, SPARC32_PSR_REGNUM, | |
1704 | regs + gregset->r_psr_offset); | |
60054393 | 1705 | |
386c036b MK |
1706 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1707 | regcache_raw_collect (regcache, SPARC32_PC_REGNUM, | |
1708 | regs + gregset->r_pc_offset); | |
1709 | ||
1710 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) | |
1711 | regcache_raw_collect (regcache, SPARC32_NPC_REGNUM, | |
1712 | regs + gregset->r_npc_offset); | |
5af923b0 | 1713 | |
386c036b MK |
1714 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1715 | regcache_raw_collect (regcache, SPARC32_Y_REGNUM, | |
1716 | regs + gregset->r_y_offset); | |
1717 | ||
1718 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) | |
5af923b0 | 1719 | { |
386c036b MK |
1720 | int offset = gregset->r_g1_offset; |
1721 | ||
1722 | /* %g0 is always zero. */ | |
1723 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1724 | { | |
1725 | if (regnum == i || regnum == -1) | |
1726 | regcache_raw_collect (regcache, i, regs + offset); | |
1727 | offset += 4; | |
1728 | } | |
5af923b0 | 1729 | } |
386c036b MK |
1730 | |
1731 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
5af923b0 | 1732 | { |
386c036b MK |
1733 | /* Not all of the register set variants include Locals and |
1734 | Inputs. For those that don't, we read them off the stack. */ | |
1735 | if (gregset->r_l0_offset != -1) | |
1736 | { | |
1737 | int offset = gregset->r_l0_offset; | |
1738 | ||
1739 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1740 | { | |
1741 | if (regnum == i || regnum == -1) | |
1742 | regcache_raw_collect (regcache, i, regs + offset); | |
1743 | offset += 4; | |
1744 | } | |
1745 | } | |
5af923b0 | 1746 | } |
c906108c SS |
1747 | } |
1748 | ||
c906108c | 1749 | void |
386c036b MK |
1750 | sparc32_supply_fpregset (struct regcache *regcache, |
1751 | int regnum, const void *fpregs) | |
c906108c | 1752 | { |
e1613aba | 1753 | const gdb_byte *regs = fpregs; |
386c036b | 1754 | int i; |
60054393 | 1755 | |
386c036b | 1756 | for (i = 0; i < 32; i++) |
c906108c | 1757 | { |
386c036b MK |
1758 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) |
1759 | regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, regs + (i * 4)); | |
c906108c | 1760 | } |
5af923b0 | 1761 | |
386c036b MK |
1762 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
1763 | regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4); | |
c906108c SS |
1764 | } |
1765 | ||
386c036b MK |
1766 | void |
1767 | sparc32_collect_fpregset (const struct regcache *regcache, | |
1768 | int regnum, void *fpregs) | |
c906108c | 1769 | { |
e1613aba | 1770 | gdb_byte *regs = fpregs; |
386c036b | 1771 | int i; |
c906108c | 1772 | |
386c036b MK |
1773 | for (i = 0; i < 32; i++) |
1774 | { | |
1775 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) | |
1776 | regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, regs + (i * 4)); | |
1777 | } | |
c906108c | 1778 | |
386c036b MK |
1779 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
1780 | regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4); | |
c906108c | 1781 | } |
c906108c | 1782 | \f |
c906108c | 1783 | |
386c036b | 1784 | /* SunOS 4. */ |
c906108c | 1785 | |
386c036b MK |
1786 | /* From <machine/reg.h>. */ |
1787 | const struct sparc_gregset sparc32_sunos4_gregset = | |
c906108c | 1788 | { |
386c036b MK |
1789 | 0 * 4, /* %psr */ |
1790 | 1 * 4, /* %pc */ | |
1791 | 2 * 4, /* %npc */ | |
1792 | 3 * 4, /* %y */ | |
1793 | -1, /* %wim */ | |
1794 | -1, /* %tbr */ | |
1795 | 4 * 4, /* %g1 */ | |
1796 | -1 /* %l0 */ | |
1797 | }; | |
1798 | \f | |
c906108c | 1799 | |
386c036b MK |
1800 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
1801 | void _initialize_sparc_tdep (void); | |
c906108c SS |
1802 | |
1803 | void | |
386c036b | 1804 | _initialize_sparc_tdep (void) |
c906108c | 1805 | { |
386c036b | 1806 | register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init); |
2d457077 MK |
1807 | |
1808 | /* Initialize the SPARC-specific register types. */ | |
1809 | sparc_init_types(); | |
ef3cf062 | 1810 | } |