Commit | Line | Data |
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f9e3b3cc JG |
1 | /* Target-dependent code for the SPARC for GDB, the GNU debugger. |
2 | Copyright 1986, 1987, 1989, 1991, 1992 Free Software Foundation, Inc. | |
bd5635a1 RP |
3 | |
4 | This file is part of GDB. | |
5 | ||
5259796b | 6 | This program is free software; you can redistribute it and/or modify |
bd5635a1 | 7 | it under the terms of the GNU General Public License as published by |
5259796b JG |
8 | the Free Software Foundation; either version 2 of the License, or |
9 | (at your option) any later version. | |
bd5635a1 | 10 | |
5259796b | 11 | This program is distributed in the hope that it will be useful, |
bd5635a1 RP |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
5259796b JG |
17 | along with this program; if not, write to the Free Software |
18 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
bd5635a1 | 19 | |
bd5635a1 | 20 | #include "defs.h" |
bd5635a1 RP |
21 | #include "frame.h" |
22 | #include "inferior.h" | |
23 | #include "obstack.h" | |
bd5635a1 RP |
24 | #include "target.h" |
25 | #include "ieee-float.h" | |
26 | ||
8f86a4e4 JG |
27 | #ifdef USE_PROC_FS |
28 | #include <sys/procfs.h> | |
29 | #else | |
bd5635a1 | 30 | #include <sys/ptrace.h> |
8f86a4e4 | 31 | #endif |
bd5635a1 | 32 | |
bd5635a1 RP |
33 | #include "gdbcore.h" |
34 | ||
35 | /* From infrun.c */ | |
36 | extern int stop_after_trap; | |
37 | ||
38 | typedef enum | |
39 | { | |
f9e3b3cc | 40 | Error, not_branch, bicc, bicca, ba, baa, ticc, ta |
bd5635a1 RP |
41 | } branch_type; |
42 | ||
43 | /* Simulate single-step ptrace call for sun4. Code written by Gary | |
44 | Beihl (beihl@mcc.com). */ | |
45 | ||
46 | /* npc4 and next_pc describe the situation at the time that the | |
47 | step-breakpoint was set, not necessary the current value of NPC_REGNUM. */ | |
48 | static CORE_ADDR next_pc, npc4, target; | |
49 | static int brknpc4, brktrg; | |
50 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
51 | static binsn_quantum break_mem[3]; | |
52 | ||
53 | /* Non-zero if we just simulated a single-step ptrace call. This is | |
54 | needed because we cannot remove the breakpoints in the inferior | |
55 | process until after the `wait' in `wait_for_inferior'. Used for | |
56 | sun4. */ | |
57 | ||
58 | int one_stepped; | |
59 | ||
d11c44f1 JG |
60 | /* single_step() is called just before we want to resume the inferior, |
61 | if we want to single-step it but there is no hardware or kernel single-step | |
62 | support (as on all SPARCs). We find all the possible targets of the | |
63 | coming instruction and breakpoint them. | |
64 | ||
65 | single_step is also called just after the inferior stops. If we had | |
66 | set up a simulated single-step, we undo our damage. */ | |
67 | ||
bd5635a1 | 68 | void |
8f86a4e4 JG |
69 | single_step (ignore) |
70 | int ignore; /* pid, but we don't need it */ | |
bd5635a1 RP |
71 | { |
72 | branch_type br, isannulled(); | |
73 | CORE_ADDR pc; | |
74 | long pc_instruction; | |
75 | ||
76 | if (!one_stepped) | |
77 | { | |
78 | /* Always set breakpoint for NPC. */ | |
79 | next_pc = read_register (NPC_REGNUM); | |
80 | npc4 = next_pc + 4; /* branch not taken */ | |
81 | ||
82 | target_insert_breakpoint (next_pc, break_mem[0]); | |
83 | /* printf ("set break at %x\n",next_pc); */ | |
84 | ||
85 | pc = read_register (PC_REGNUM); | |
86 | pc_instruction = read_memory_integer (pc, sizeof(pc_instruction)); | |
87 | br = isannulled (pc_instruction, pc, &target); | |
88 | brknpc4 = brktrg = 0; | |
89 | ||
90 | if (br == bicca) | |
91 | { | |
92 | /* Conditional annulled branch will either end up at | |
93 | npc (if taken) or at npc+4 (if not taken). | |
94 | Trap npc+4. */ | |
95 | brknpc4 = 1; | |
96 | target_insert_breakpoint (npc4, break_mem[1]); | |
97 | } | |
98 | else if (br == baa && target != next_pc) | |
99 | { | |
100 | /* Unconditional annulled branch will always end up at | |
101 | the target. */ | |
102 | brktrg = 1; | |
103 | target_insert_breakpoint (target, break_mem[2]); | |
104 | } | |
105 | ||
d11c44f1 | 106 | /* We are ready to let it go */ |
bd5635a1 RP |
107 | one_stepped = 1; |
108 | return; | |
109 | } | |
110 | else | |
111 | { | |
112 | /* Remove breakpoints */ | |
113 | target_remove_breakpoint (next_pc, break_mem[0]); | |
114 | ||
115 | if (brknpc4) | |
116 | target_remove_breakpoint (npc4, break_mem[1]); | |
117 | ||
118 | if (brktrg) | |
119 | target_remove_breakpoint (target, break_mem[2]); | |
120 | ||
121 | one_stepped = 0; | |
122 | } | |
123 | } | |
124 | \f | |
f9e3b3cc JG |
125 | #define FRAME_SAVED_L0 0 /* Byte offset from SP */ |
126 | #define FRAME_SAVED_I0 32 /* Byte offset from SP */ | |
127 | ||
d11c44f1 JG |
128 | CORE_ADDR |
129 | sparc_frame_chain (thisframe) | |
130 | FRAME thisframe; | |
131 | { | |
132 | CORE_ADDR retval; | |
5259796b | 133 | int err; |
f9e3b3cc JG |
134 | CORE_ADDR addr; |
135 | ||
136 | addr = thisframe->frame + FRAME_SAVED_I0 + | |
137 | REGISTER_RAW_SIZE(FP_REGNUM) * (FP_REGNUM - I0_REGNUM); | |
138 | err = target_read_memory (addr, (char *) &retval, sizeof (CORE_ADDR)); | |
5259796b JG |
139 | if (err) |
140 | return 0; | |
f9e3b3cc | 141 | SWAP_TARGET_AND_HOST (&retval, sizeof (retval)); |
d11c44f1 JG |
142 | return retval; |
143 | } | |
144 | ||
145 | CORE_ADDR | |
146 | sparc_extract_struct_value_address (regbuf) | |
147 | char regbuf[REGISTER_BYTES]; | |
148 | { | |
f9e3b3cc JG |
149 | /* FIXME, handle byte swapping */ |
150 | return read_memory_integer (((int *)(regbuf))[SP_REGNUM]+(16*4), | |
151 | sizeof (CORE_ADDR)); | |
d11c44f1 JG |
152 | } |
153 | ||
f9e3b3cc JG |
154 | /* Find the pc saved in frame FRAME. */ |
155 | ||
bd5635a1 RP |
156 | CORE_ADDR |
157 | frame_saved_pc (frame) | |
158 | FRAME frame; | |
159 | { | |
160 | CORE_ADDR prev_pc; | |
161 | ||
f9e3b3cc JG |
162 | if (get_current_frame () == frame) /* FIXME, debug check. Remove >=gdb-4.6 */ |
163 | { | |
164 | if (read_register (SP_REGNUM) != frame->bottom) abort(); | |
165 | } | |
166 | ||
167 | read_memory ((CORE_ADDR) (frame->bottom + FRAME_SAVED_I0 + | |
168 | REGISTER_RAW_SIZE(I7_REGNUM) * (I7_REGNUM - I0_REGNUM)), | |
169 | (char *) &prev_pc, | |
170 | sizeof (CORE_ADDR)); | |
171 | ||
172 | SWAP_TARGET_AND_HOST (&prev_pc, sizeof (prev_pc)); | |
bd5635a1 RP |
173 | return PC_ADJUST (prev_pc); |
174 | } | |
175 | ||
176 | /* | |
177 | * Since an individual frame in the frame cache is defined by two | |
178 | * arguments (a frame pointer and a stack pointer), we need two | |
179 | * arguments to get info for an arbitrary stack frame. This routine | |
180 | * takes two arguments and makes the cached frames look as if these | |
181 | * two arguments defined a frame on the cache. This allows the rest | |
182 | * of info frame to extract the important arguments without | |
183 | * difficulty. | |
184 | */ | |
185 | FRAME | |
186 | setup_arbitrary_frame (frame, stack) | |
187 | FRAME_ADDR frame, stack; | |
188 | { | |
189 | FRAME fid = create_new_frame (frame, 0); | |
190 | ||
191 | if (!fid) | |
192 | fatal ("internal: create_new_frame returned invalid frame id"); | |
193 | ||
194 | fid->bottom = stack; | |
5259796b | 195 | fid->pc = FRAME_SAVED_PC (fid); |
bd5635a1 RP |
196 | return fid; |
197 | } | |
198 | ||
199 | /* This code was written by Gary Beihl (beihl@mcc.com). | |
200 | It was modified by Michael Tiemann (tiemann@corto.inria.fr). */ | |
201 | ||
202 | /* | |
203 | * This routine appears to be passed a size by which to increase the | |
204 | * stack. It then executes a save instruction in the inferior to | |
205 | * increase the stack by this amount. Only the register window system | |
206 | * should be affected by this; the program counter & etc. will not be. | |
207 | * | |
208 | * This instructions used for this purpose are: | |
209 | * | |
210 | * sethi %hi(0x0),g1 * | |
211 | * add g1,0x1ee0,g1 * | |
212 | * save sp,g1,sp | |
213 | * sethi %hi(0x0),g1 * | |
214 | * add g1,0x1ee0,g1 * | |
215 | * t g0,0x1,o0 | |
216 | * sethi %hi(0x0),g0 (nop) | |
217 | * | |
218 | * I presume that these set g1 to be the negative of the size, do a | |
219 | * save (putting the stack pointer at sp - size) and restore the | |
220 | * original contents of g1. A * indicates that the actual value of | |
221 | * the instruction is modified below. | |
222 | */ | |
223 | static int save_insn_opcodes[] = { | |
224 | 0x03000000, 0x82007ee0, 0x9de38001, 0x03000000, | |
225 | 0x82007ee0, 0x91d02001, 0x01000000 }; | |
226 | ||
227 | /* Neither do_save_insn or do_restore_insn save stack configuration | |
228 | (current_frame, etc), | |
229 | since the stack is in an indeterminate state through the call to | |
230 | each of them. That responsibility of the routine which calls them. */ | |
231 | ||
232 | static void | |
233 | do_save_insn (size) | |
234 | int size; | |
235 | { | |
236 | int g1 = read_register (G1_REGNUM); | |
237 | CORE_ADDR sp = read_register (SP_REGNUM); | |
238 | CORE_ADDR pc = read_register (PC_REGNUM); | |
239 | CORE_ADDR npc = read_register (NPC_REGNUM); | |
240 | CORE_ADDR fake_pc = sp - sizeof (save_insn_opcodes); | |
241 | struct inferior_status inf_status; | |
242 | ||
243 | save_inferior_status (&inf_status, 0); /* Don't restore stack info */ | |
244 | /* | |
245 | * See above. | |
246 | */ | |
247 | save_insn_opcodes[0] = 0x03000000 | ((-size >> 10) & 0x3fffff); | |
248 | save_insn_opcodes[1] = 0x82006000 | (-size & 0x3ff); | |
249 | save_insn_opcodes[3] = 0x03000000 | ((g1 >> 10) & 0x3fffff); | |
250 | save_insn_opcodes[4] = 0x82006000 | (g1 & 0x3ff); | |
251 | write_memory (fake_pc, (char *)save_insn_opcodes, sizeof (save_insn_opcodes)); | |
252 | ||
253 | clear_proceed_status (); | |
254 | stop_after_trap = 1; | |
255 | proceed (fake_pc, 0, 0); | |
256 | ||
257 | write_register (PC_REGNUM, pc); | |
258 | write_register (NPC_REGNUM, npc); | |
259 | restore_inferior_status (&inf_status); | |
260 | } | |
261 | ||
262 | /* | |
263 | * This routine takes a program counter value. It restores the | |
264 | * register window system to the frame above the current one. | |
265 | * THIS ROUTINE CLOBBERS PC AND NPC IN THE TARGET! | |
266 | */ | |
267 | ||
268 | /* The following insns translate to: | |
269 | ||
270 | restore %g0,%g0,%g0 | |
271 | t %g0,1 | |
272 | sethi %hi(0),%g0 */ | |
273 | ||
274 | static int restore_insn_opcodes[] = { 0x81e80000, 0x91d02001, 0x01000000 }; | |
275 | ||
276 | static void | |
277 | do_restore_insn () | |
278 | { | |
279 | CORE_ADDR sp = read_register (SP_REGNUM); | |
280 | CORE_ADDR fake_pc = sp - sizeof (restore_insn_opcodes); | |
281 | struct inferior_status inf_status; | |
282 | ||
283 | save_inferior_status (&inf_status, 0); /* Don't restore stack info */ | |
284 | ||
285 | write_memory (fake_pc, (char *)restore_insn_opcodes, | |
286 | sizeof (restore_insn_opcodes)); | |
287 | ||
288 | clear_proceed_status (); | |
289 | stop_after_trap = 1; | |
290 | proceed (fake_pc, 0, 0); | |
291 | ||
292 | restore_inferior_status (&inf_status); | |
293 | } | |
294 | ||
5259796b JG |
295 | /* Given a pc value, skip it forward past the function prologue by |
296 | disassembling instructions that appear to be a prologue. | |
297 | ||
298 | If FRAMELESS_P is set, we are only testing to see if the function | |
299 | is frameless. This allows a quicker answer. | |
300 | ||
301 | This routine should be more specific in its actions; making sure | |
192cbba9 | 302 | that it uses the same register in the initial prologue section. */ |
bd5635a1 | 303 | CORE_ADDR |
5259796b | 304 | skip_prologue (start_pc, frameless_p) |
192cbba9 | 305 | CORE_ADDR start_pc; |
5259796b | 306 | int frameless_p; |
bd5635a1 RP |
307 | { |
308 | union | |
309 | { | |
310 | unsigned long int code; | |
311 | struct | |
312 | { | |
313 | unsigned int op:2; | |
314 | unsigned int rd:5; | |
315 | unsigned int op2:3; | |
316 | unsigned int imm22:22; | |
317 | } sethi; | |
318 | struct | |
319 | { | |
320 | unsigned int op:2; | |
321 | unsigned int rd:5; | |
322 | unsigned int op3:6; | |
323 | unsigned int rs1:5; | |
324 | unsigned int i:1; | |
325 | unsigned int simm13:13; | |
326 | } add; | |
327 | int i; | |
328 | } x; | |
329 | int dest = -1; | |
192cbba9 | 330 | CORE_ADDR pc = start_pc; |
bd5635a1 RP |
331 | |
332 | x.i = read_memory_integer (pc, 4); | |
333 | ||
334 | /* Recognize the `sethi' insn and record its destination. */ | |
335 | if (x.sethi.op == 0 && x.sethi.op2 == 4) | |
336 | { | |
337 | dest = x.sethi.rd; | |
338 | pc += 4; | |
339 | x.i = read_memory_integer (pc, 4); | |
340 | } | |
341 | ||
342 | /* Recognize an add immediate value to register to either %g1 or | |
343 | the destination register recorded above. Actually, this might | |
192cbba9 JK |
344 | well recognize several different arithmetic operations. |
345 | It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1" | |
346 | followed by "save %sp, %g1, %sp" is a valid prologue (Not that | |
347 | I imagine any compiler really does that, however). */ | |
bd5635a1 RP |
348 | if (x.add.op == 2 && x.add.i && (x.add.rd == 1 || x.add.rd == dest)) |
349 | { | |
350 | pc += 4; | |
351 | x.i = read_memory_integer (pc, 4); | |
352 | } | |
353 | ||
354 | /* This recognizes any SAVE insn. But why do the XOR and then | |
355 | the compare? That's identical to comparing against 60 (as long | |
356 | as there isn't any sign extension). */ | |
357 | if (x.add.op == 2 && (x.add.op3 ^ 32) == 28) | |
358 | { | |
359 | pc += 4; | |
5259796b JG |
360 | if (frameless_p) /* If the save is all we care about, */ |
361 | return pc; /* return before doing more work */ | |
bd5635a1 RP |
362 | x.i = read_memory_integer (pc, 4); |
363 | } | |
5259796b JG |
364 | else |
365 | { | |
366 | /* Without a save instruction, it's not a prologue. */ | |
367 | return start_pc; | |
368 | } | |
bd5635a1 RP |
369 | |
370 | /* Now we need to recognize stores into the frame from the input | |
371 | registers. This recognizes all non alternate stores of input | |
372 | register, into a location offset from the frame pointer. */ | |
373 | while (x.add.op == 3 | |
374 | && (x.add.op3 & 0x3c) == 4 /* Store, non-alternate. */ | |
375 | && (x.add.rd & 0x18) == 0x18 /* Input register. */ | |
376 | && x.add.i /* Immediate mode. */ | |
377 | && x.add.rs1 == 30 /* Off of frame pointer. */ | |
378 | /* Into reserved stack space. */ | |
379 | && x.add.simm13 >= 0x44 | |
380 | && x.add.simm13 < 0x5b) | |
381 | { | |
382 | pc += 4; | |
383 | x.i = read_memory_integer (pc, 4); | |
384 | } | |
5259796b | 385 | return pc; |
bd5635a1 RP |
386 | } |
387 | ||
388 | /* Check instruction at ADDR to see if it is an annulled branch. | |
389 | All other instructions will go to NPC or will trap. | |
390 | Set *TARGET if we find a canidate branch; set to zero if not. */ | |
391 | ||
392 | branch_type | |
393 | isannulled (instruction, addr, target) | |
394 | long instruction; | |
395 | CORE_ADDR addr, *target; | |
396 | { | |
397 | branch_type val = not_branch; | |
398 | long int offset; /* Must be signed for sign-extend. */ | |
399 | union | |
400 | { | |
401 | unsigned long int code; | |
402 | struct | |
403 | { | |
404 | unsigned int op:2; | |
405 | unsigned int a:1; | |
406 | unsigned int cond:4; | |
407 | unsigned int op2:3; | |
408 | unsigned int disp22:22; | |
409 | } b; | |
410 | } insn; | |
411 | ||
412 | *target = 0; | |
413 | insn.code = instruction; | |
414 | ||
415 | if (insn.b.op == 0 | |
416 | && (insn.b.op2 == 2 || insn.b.op2 == 6 || insn.b.op2 == 7)) | |
417 | { | |
418 | if (insn.b.cond == 8) | |
419 | val = insn.b.a ? baa : ba; | |
420 | else | |
421 | val = insn.b.a ? bicca : bicc; | |
422 | offset = 4 * ((int) (insn.b.disp22 << 10) >> 10); | |
423 | *target = addr + offset; | |
424 | } | |
425 | ||
426 | return val; | |
427 | } | |
428 | ||
429 | /* sparc_frame_find_saved_regs () | |
430 | ||
431 | Stores, into a struct frame_saved_regs, | |
432 | the addresses of the saved registers of frame described by FRAME_INFO. | |
433 | This includes special registers such as pc and fp saved in special | |
434 | ways in the stack frame. sp is even more special: | |
435 | the address we return for it IS the sp for the next frame. | |
436 | ||
437 | Note that on register window machines, we are currently making the | |
438 | assumption that window registers are being saved somewhere in the | |
439 | frame in which they are being used. If they are stored in an | |
440 | inferior frame, find_saved_register will break. | |
441 | ||
442 | On the Sun 4, the only time all registers are saved is when | |
443 | a dummy frame is involved. Otherwise, the only saved registers | |
444 | are the LOCAL and IN registers which are saved as a result | |
445 | of the "save/restore" opcodes. This condition is determined | |
446 | by address rather than by value. | |
447 | ||
448 | The "pc" is not stored in a frame on the SPARC. (What is stored | |
449 | is a return address minus 8.) sparc_pop_frame knows how to | |
450 | deal with that. Other routines might or might not. | |
451 | ||
452 | See tm-sparc.h (PUSH_FRAME and friends) for CRITICAL information | |
453 | about how this works. */ | |
454 | ||
455 | void | |
456 | sparc_frame_find_saved_regs (fi, saved_regs_addr) | |
457 | struct frame_info *fi; | |
458 | struct frame_saved_regs *saved_regs_addr; | |
459 | { | |
460 | register int regnum; | |
461 | FRAME_ADDR frame = read_register (FP_REGNUM); | |
462 | FRAME fid = FRAME_INFO_ID (fi); | |
463 | ||
464 | if (!fid) | |
465 | fatal ("Bad frame info struct in FRAME_FIND_SAVED_REGS"); | |
466 | ||
467 | bzero (saved_regs_addr, sizeof (*saved_regs_addr)); | |
468 | ||
469 | /* Old test. | |
470 | if (fi->pc >= frame - CALL_DUMMY_LENGTH - 0x140 | |
471 | && fi->pc <= frame) */ | |
472 | ||
473 | if (fi->pc >= (fi->bottom ? fi->bottom : | |
474 | read_register (SP_REGNUM)) | |
475 | && fi->pc <= FRAME_FP(fi)) | |
476 | { | |
477 | /* Dummy frame. All but the window regs are in there somewhere. */ | |
478 | for (regnum = G1_REGNUM; regnum < G1_REGNUM+7; regnum++) | |
479 | saved_regs_addr->regs[regnum] = | |
480 | frame + (regnum - G0_REGNUM) * 4 - 0xa0; | |
481 | for (regnum = I0_REGNUM; regnum < I0_REGNUM+8; regnum++) | |
482 | saved_regs_addr->regs[regnum] = | |
483 | frame + (regnum - I0_REGNUM) * 4 - 0xc0; | |
484 | for (regnum = FP0_REGNUM; regnum < FP0_REGNUM + 32; regnum++) | |
485 | saved_regs_addr->regs[regnum] = | |
486 | frame + (regnum - FP0_REGNUM) * 4 - 0x80; | |
487 | for (regnum = Y_REGNUM; regnum < NUM_REGS; regnum++) | |
488 | saved_regs_addr->regs[regnum] = | |
489 | frame + (regnum - Y_REGNUM) * 4 - 0xe0; | |
490 | frame = fi->bottom ? | |
491 | fi->bottom : read_register (SP_REGNUM); | |
492 | } | |
493 | else | |
494 | { | |
495 | /* Normal frame. Just Local and In registers */ | |
496 | frame = fi->bottom ? | |
497 | fi->bottom : read_register (SP_REGNUM); | |
498 | for (regnum = L0_REGNUM; regnum < L0_REGNUM+16; regnum++) | |
499 | saved_regs_addr->regs[regnum] = frame + (regnum-L0_REGNUM) * 4; | |
500 | } | |
501 | if (fi->next) | |
502 | { | |
503 | /* Pull off either the next frame pointer or the stack pointer */ | |
504 | FRAME_ADDR next_next_frame = | |
505 | (fi->next->bottom ? | |
506 | fi->next->bottom : | |
507 | read_register (SP_REGNUM)); | |
508 | for (regnum = O0_REGNUM; regnum < O0_REGNUM+8; regnum++) | |
509 | saved_regs_addr->regs[regnum] = next_next_frame + regnum * 4; | |
510 | } | |
511 | /* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */ | |
512 | saved_regs_addr->regs[SP_REGNUM] = FRAME_FP (fi); | |
513 | } | |
514 | ||
515 | /* Push an empty stack frame, and record in it the current PC, regs, etc. | |
516 | ||
517 | Note that the write's are of registers in the context of the newly | |
518 | pushed frame. Thus the the fp*'s, the g*'s, the i*'s, and | |
519 | the randoms, of the new frame, are being saved. The locals and outs | |
520 | are new; they don't need to be saved. The i's and l's of | |
521 | the last frame were saved by the do_save_insn in the register | |
522 | file (now on the stack, since a context switch happended imm after). | |
523 | ||
524 | The return pointer register %i7 does not have | |
525 | the pc saved into it (return from this frame will be accomplished | |
526 | by a POP_FRAME). In fact, we must leave it unclobbered, since we | |
527 | must preserve it in the calling routine except across call instructions. */ | |
528 | ||
529 | /* Definitely see tm-sparc.h for more doc of the frame format here. */ | |
530 | ||
531 | void | |
532 | sparc_push_dummy_frame () | |
533 | { | |
534 | CORE_ADDR fp; | |
535 | char register_temp[REGISTER_BYTES]; | |
536 | ||
537 | do_save_insn (0x140); /* FIXME where does this value come from? */ | |
538 | fp = read_register (FP_REGNUM); | |
539 | ||
540 | read_register_bytes (REGISTER_BYTE (FP0_REGNUM), register_temp, 32 * 4); | |
541 | write_memory (fp - 0x80, register_temp, 32 * 4); | |
542 | ||
543 | read_register_bytes (REGISTER_BYTE (G0_REGNUM), register_temp, 8 * 4); | |
544 | write_memory (fp - 0xa0, register_temp, 8 * 4); | |
545 | ||
546 | read_register_bytes (REGISTER_BYTE (I0_REGNUM), register_temp, 8 * 4); | |
547 | write_memory (fp - 0xc0, register_temp, 8 * 4); | |
548 | ||
549 | /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */ | |
550 | read_register_bytes (REGISTER_BYTE (Y_REGNUM), register_temp, 8 * 4); | |
551 | write_memory (fp - 0xe0, register_temp, 8 * 4); | |
552 | } | |
553 | ||
554 | /* Discard from the stack the innermost frame, restoring all saved registers. | |
555 | ||
556 | Note that the values stored in fsr by get_frame_saved_regs are *in | |
557 | the context of the called frame*. What this means is that the i | |
558 | regs of fsr must be restored into the o regs of the (calling) frame that | |
559 | we pop into. We don't care about the output regs of the calling frame, | |
560 | since unless it's a dummy frame, it won't have any output regs in it. | |
561 | ||
562 | We never have to bother with %l (local) regs, since the called routine's | |
563 | locals get tossed, and the calling routine's locals are already saved | |
564 | on its stack. */ | |
565 | ||
566 | /* Definitely see tm-sparc.h for more doc of the frame format here. */ | |
567 | ||
568 | void | |
569 | sparc_pop_frame () | |
570 | { | |
571 | register FRAME frame = get_current_frame (); | |
572 | register CORE_ADDR pc; | |
573 | struct frame_saved_regs fsr; | |
574 | struct frame_info *fi; | |
575 | char raw_buffer[REGISTER_BYTES]; | |
576 | ||
577 | fi = get_frame_info (frame); | |
578 | get_frame_saved_regs (fi, &fsr); | |
579 | do_restore_insn (); | |
580 | if (fsr.regs[FP0_REGNUM]) | |
581 | { | |
582 | read_memory (fsr.regs[FP0_REGNUM], raw_buffer, 32 * 4); | |
583 | write_register_bytes (REGISTER_BYTE (FP0_REGNUM), raw_buffer, 32 * 4); | |
584 | } | |
585 | if (fsr.regs[G1_REGNUM]) | |
586 | { | |
587 | read_memory (fsr.regs[G1_REGNUM], raw_buffer, 7 * 4); | |
588 | write_register_bytes (REGISTER_BYTE (G1_REGNUM), raw_buffer, 7 * 4); | |
589 | } | |
590 | if (fsr.regs[I0_REGNUM]) | |
591 | { | |
592 | read_memory (fsr.regs[I0_REGNUM], raw_buffer, 8 * 4); | |
593 | write_register_bytes (REGISTER_BYTE (O0_REGNUM), raw_buffer, 8 * 4); | |
594 | } | |
595 | if (fsr.regs[PS_REGNUM]) | |
596 | write_register (PS_REGNUM, read_memory_integer (fsr.regs[PS_REGNUM], 4)); | |
597 | if (fsr.regs[Y_REGNUM]) | |
598 | write_register (Y_REGNUM, read_memory_integer (fsr.regs[Y_REGNUM], 4)); | |
599 | if (fsr.regs[PC_REGNUM]) | |
600 | { | |
601 | /* Explicitly specified PC (and maybe NPC) -- just restore them. */ | |
602 | write_register (PC_REGNUM, read_memory_integer (fsr.regs[PC_REGNUM], 4)); | |
603 | if (fsr.regs[NPC_REGNUM]) | |
604 | write_register (NPC_REGNUM, | |
605 | read_memory_integer (fsr.regs[NPC_REGNUM], 4)); | |
606 | } | |
607 | else if (fsr.regs[I7_REGNUM]) | |
608 | { | |
609 | /* Return address in %i7 -- adjust it, then restore PC and NPC from it */ | |
610 | pc = PC_ADJUST (read_memory_integer (fsr.regs[I7_REGNUM], 4)); | |
611 | write_register (PC_REGNUM, pc); | |
612 | write_register (NPC_REGNUM, pc + 4); | |
613 | } | |
614 | flush_cached_frames (); | |
615 | set_current_frame ( create_new_frame (read_register (FP_REGNUM), | |
616 | read_pc ())); | |
617 | } | |
618 | ||
5e5215eb JG |
619 | /* On the Sun 4 under SunOS, the compile will leave a fake insn which |
620 | encodes the structure size being returned. If we detect such | |
621 | a fake insn, step past it. */ | |
622 | ||
623 | CORE_ADDR | |
624 | sparc_pc_adjust(pc) | |
625 | CORE_ADDR pc; | |
626 | { | |
627 | long insn; | |
628 | int err; | |
629 | ||
630 | err = target_read_memory (pc + 8, (char *)&insn, sizeof(long)); | |
631 | SWAP_TARGET_AND_HOST (&insn, sizeof(long)); | |
632 | if ((err == 0) && (insn & 0xfffffe00) == 0) | |
633 | return pc+12; | |
634 | else | |
635 | return pc+8; | |
636 | } | |
637 | ||
638 | ||
bd5635a1 RP |
639 | /* Structure of SPARC extended floating point numbers. |
640 | This information is not currently used by GDB, since no current SPARC | |
641 | implementations support extended float. */ | |
642 | ||
f9e3b3cc | 643 | const struct ext_format ext_format_sparc = { |
bd5635a1 | 644 | /* tot sbyte smask expbyte manbyte */ |
f9e3b3cc | 645 | 16, 0, 0x80, 0,1, 4,8, /* sparc */ |
bd5635a1 | 646 | }; |
8f86a4e4 JG |
647 | \f |
648 | #ifdef USE_PROC_FS /* Target dependent support for /proc */ | |
649 | ||
650 | /* The /proc interface divides the target machine's register set up into | |
651 | two different sets, the general register set (gregset) and the floating | |
652 | point register set (fpregset). For each set, there is an ioctl to get | |
653 | the current register set and another ioctl to set the current values. | |
654 | ||
655 | The actual structure passed through the ioctl interface is, of course, | |
656 | naturally machine dependent, and is different for each set of registers. | |
657 | For the sparc for example, the general register set is typically defined | |
658 | by: | |
659 | ||
660 | typedef int gregset_t[38]; | |
661 | ||
662 | #define R_G0 0 | |
663 | ... | |
664 | #define R_TBR 37 | |
665 | ||
666 | and the floating point set by: | |
667 | ||
668 | typedef struct prfpregset { | |
669 | union { | |
670 | u_long pr_regs[32]; | |
671 | double pr_dregs[16]; | |
672 | } pr_fr; | |
673 | void * pr_filler; | |
674 | u_long pr_fsr; | |
675 | u_char pr_qcnt; | |
676 | u_char pr_q_entrysize; | |
677 | u_char pr_en; | |
678 | u_long pr_q[64]; | |
679 | } prfpregset_t; | |
680 | ||
681 | These routines provide the packing and unpacking of gregset_t and | |
682 | fpregset_t formatted data. | |
683 | ||
684 | */ | |
685 | ||
686 | ||
687 | /* Given a pointer to a general register set in /proc format (gregset_t *), | |
688 | unpack the register contents and supply them as gdb's idea of the current | |
689 | register values. */ | |
690 | ||
691 | void | |
692 | supply_gregset (gregsetp) | |
693 | prgregset_t *gregsetp; | |
694 | { | |
695 | register int regno; | |
696 | register prgreg_t *regp = (prgreg_t *) gregsetp; | |
697 | ||
698 | /* GDB register numbers for Gn, On, Ln, In all match /proc reg numbers. */ | |
699 | for (regno = G0_REGNUM ; regno <= I7_REGNUM ; regno++) | |
700 | { | |
701 | supply_register (regno, (char *) (regp + regno)); | |
702 | } | |
703 | ||
704 | /* These require a bit more care. */ | |
705 | supply_register (PS_REGNUM, (char *) (regp + R_PS)); | |
706 | supply_register (PC_REGNUM, (char *) (regp + R_PC)); | |
707 | supply_register (NPC_REGNUM,(char *) (regp + R_nPC)); | |
708 | supply_register (Y_REGNUM, (char *) (regp + R_Y)); | |
709 | } | |
710 | ||
711 | void | |
712 | fill_gregset (gregsetp, regno) | |
713 | prgregset_t *gregsetp; | |
714 | int regno; | |
715 | { | |
716 | int regi; | |
717 | register prgreg_t *regp = (prgreg_t *) gregsetp; | |
718 | extern char registers[]; | |
719 | ||
720 | for (regi = 0 ; regi <= R_I7 ; regi++) | |
721 | { | |
722 | if ((regno == -1) || (regno == regi)) | |
723 | { | |
724 | *(regp + regno) = *(int *) ®isters[REGISTER_BYTE (regi)]; | |
725 | } | |
726 | } | |
727 | if ((regno == -1) || (regno == PS_REGNUM)) | |
728 | { | |
729 | *(regp + R_PS) = *(int *) ®isters[REGISTER_BYTE (PS_REGNUM)]; | |
730 | } | |
731 | if ((regno == -1) || (regno == PC_REGNUM)) | |
732 | { | |
733 | *(regp + R_PC) = *(int *) ®isters[REGISTER_BYTE (PC_REGNUM)]; | |
734 | } | |
735 | if ((regno == -1) || (regno == NPC_REGNUM)) | |
736 | { | |
737 | *(regp + R_nPC) = *(int *) ®isters[REGISTER_BYTE (NPC_REGNUM)]; | |
738 | } | |
739 | if ((regno == -1) || (regno == Y_REGNUM)) | |
740 | { | |
741 | *(regp + R_Y) = *(int *) ®isters[REGISTER_BYTE (Y_REGNUM)]; | |
742 | } | |
743 | } | |
744 | ||
745 | #if defined (FP0_REGNUM) | |
746 | ||
747 | /* Given a pointer to a floating point register set in /proc format | |
748 | (fpregset_t *), unpack the register contents and supply them as gdb's | |
749 | idea of the current floating point register values. */ | |
750 | ||
751 | void | |
752 | supply_fpregset (fpregsetp) | |
753 | prfpregset_t *fpregsetp; | |
754 | { | |
755 | register int regi; | |
756 | char *from; | |
757 | ||
758 | for (regi = FP0_REGNUM ; regi < FP0_REGNUM+32 ; regi++) | |
759 | { | |
760 | from = (char *) &fpregsetp->pr_fr.pr_regs[regi-FP0_REGNUM]; | |
761 | supply_register (regi, from); | |
762 | } | |
763 | supply_register (FPS_REGNUM, (char *) &(fpregsetp->pr_fsr)); | |
764 | } | |
765 | ||
766 | /* Given a pointer to a floating point register set in /proc format | |
767 | (fpregset_t *), update the register specified by REGNO from gdb's idea | |
768 | of the current floating point register set. If REGNO is -1, update | |
769 | them all. */ | |
770 | ||
771 | void | |
772 | fill_fpregset (fpregsetp, regno) | |
773 | prfpregset_t *fpregsetp; | |
774 | int regno; | |
775 | { | |
776 | int regi; | |
777 | char *to; | |
778 | char *from; | |
779 | extern char registers[]; | |
780 | ||
781 | for (regi = FP0_REGNUM ; regi < FP0_REGNUM+32 ; regi++) | |
782 | { | |
783 | if ((regno == -1) || (regno == regi)) | |
784 | { | |
785 | from = (char *) ®isters[REGISTER_BYTE (regi)]; | |
786 | to = (char *) &fpregsetp->pr_fr.pr_regs[regi-FP0_REGNUM]; | |
787 | bcopy (from, to, REGISTER_RAW_SIZE (regno)); | |
788 | } | |
789 | } | |
790 | if ((regno == -1) || (regno == FPS_REGNUM)) | |
791 | { | |
792 | fpregsetp->pr_fsr = *(int *) ®isters[REGISTER_BYTE (FPS_REGNUM)]; | |
793 | } | |
794 | } | |
795 | ||
796 | #endif /* defined (FP0_REGNUM) */ | |
797 | ||
798 | #endif /* USE_PROC_FS */ | |
799 | ||
800 | ||
801 | #ifdef GET_LONGJMP_TARGET | |
f9e3b3cc JG |
802 | |
803 | /* Figure out where the longjmp will land. We expect that we have just entered | |
804 | longjmp and haven't yet setup the stack frame, so the args are still in the | |
805 | output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we | |
806 | extract the pc (JB_PC) that we will land at. The pc is copied into ADDR. | |
807 | This routine returns true on success */ | |
808 | ||
809 | int | |
810 | get_longjmp_target(pc) | |
811 | CORE_ADDR *pc; | |
812 | { | |
813 | CORE_ADDR jb_addr; | |
814 | ||
815 | jb_addr = read_register(O0_REGNUM); | |
816 | ||
817 | if (target_read_memory(jb_addr + JB_PC * JB_ELEMENT_SIZE, (char *) pc, | |
818 | sizeof(CORE_ADDR))) | |
819 | return 0; | |
820 | ||
821 | SWAP_TARGET_AND_HOST(pc, sizeof(CORE_ADDR)); | |
822 | ||
823 | return 1; | |
824 | } | |
8f86a4e4 | 825 | #endif /* GET_LONGJMP_TARGET */ |