Commit | Line | Data |
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386c036b | 1 | /* Target-dependent code for SPARC. |
cda5a58a | 2 | |
6aba47ca | 3 | Copyright (C) 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 19 | |
c906108c | 20 | #include "defs.h" |
5af923b0 | 21 | #include "arch-utils.h" |
386c036b | 22 | #include "dis-asm.h" |
f5a9b87d | 23 | #include "dwarf2-frame.h" |
386c036b | 24 | #include "floatformat.h" |
c906108c | 25 | #include "frame.h" |
386c036b MK |
26 | #include "frame-base.h" |
27 | #include "frame-unwind.h" | |
28 | #include "gdbcore.h" | |
29 | #include "gdbtypes.h" | |
c906108c | 30 | #include "inferior.h" |
386c036b MK |
31 | #include "symtab.h" |
32 | #include "objfiles.h" | |
33 | #include "osabi.h" | |
34 | #include "regcache.h" | |
c906108c SS |
35 | #include "target.h" |
36 | #include "value.h" | |
c906108c | 37 | |
43bd9a9e | 38 | #include "gdb_assert.h" |
386c036b | 39 | #include "gdb_string.h" |
c906108c | 40 | |
386c036b | 41 | #include "sparc-tdep.h" |
c906108c | 42 | |
a54124c5 MK |
43 | struct regset; |
44 | ||
9eb42ed1 MK |
45 | /* This file implements the SPARC 32-bit ABI as defined by the section |
46 | "Low-Level System Information" of the SPARC Compliance Definition | |
47 | (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD | |
f2e7c15d | 48 | lists changes with respect to the original 32-bit psABI as defined |
9eb42ed1 | 49 | in the "System V ABI, SPARC Processor Supplement". |
386c036b MK |
50 | |
51 | Note that if we talk about SunOS, we mean SunOS 4.x, which was | |
52 | BSD-based, which is sometimes (retroactively?) referred to as | |
53 | Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and | |
54 | above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 | |
55 | suffering from severe version number inflation). Solaris 2.x is | |
56 | also known as SunOS 5.x, since that's what uname(1) says. Solaris | |
57 | 2.x is SVR4-based. */ | |
58 | ||
59 | /* Please use the sparc32_-prefix for 32-bit specific code, the | |
60 | sparc64_-prefix for 64-bit specific code and the sparc_-prefix for | |
61 | code that can handle both. The 64-bit specific code lives in | |
62 | sparc64-tdep.c; don't add any here. */ | |
63 | ||
64 | /* The SPARC Floating-Point Quad-Precision format is similar to | |
65 | big-endian IA-64 Quad-recision format. */ | |
8da61cc4 | 66 | #define floatformats_sparc_quad floatformats_ia64_quad |
386c036b MK |
67 | |
68 | /* The stack pointer is offset from the stack frame by a BIAS of 2047 | |
69 | (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC | |
70 | hosts, so undefine it first. */ | |
71 | #undef BIAS | |
72 | #define BIAS 2047 | |
73 | ||
74 | /* Macros to extract fields from SPARC instructions. */ | |
c906108c SS |
75 | #define X_OP(i) (((i) >> 30) & 0x3) |
76 | #define X_RD(i) (((i) >> 25) & 0x1f) | |
77 | #define X_A(i) (((i) >> 29) & 1) | |
78 | #define X_COND(i) (((i) >> 25) & 0xf) | |
79 | #define X_OP2(i) (((i) >> 22) & 0x7) | |
80 | #define X_IMM22(i) ((i) & 0x3fffff) | |
81 | #define X_OP3(i) (((i) >> 19) & 0x3f) | |
075ccec8 | 82 | #define X_RS1(i) (((i) >> 14) & 0x1f) |
b0b92586 | 83 | #define X_RS2(i) ((i) & 0x1f) |
c906108c | 84 | #define X_I(i) (((i) >> 13) & 1) |
c906108c | 85 | /* Sign extension macros. */ |
c906108c | 86 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) |
c906108c | 87 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) |
075ccec8 | 88 | #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000) |
c906108c | 89 | |
386c036b MK |
90 | /* Fetch the instruction at PC. Instructions are always big-endian |
91 | even if the processor operates in little-endian mode. */ | |
92 | ||
93 | unsigned long | |
94 | sparc_fetch_instruction (CORE_ADDR pc) | |
c906108c | 95 | { |
e1613aba | 96 | gdb_byte buf[4]; |
386c036b MK |
97 | unsigned long insn; |
98 | int i; | |
99 | ||
690668cc | 100 | /* If we can't read the instruction at PC, return zero. */ |
b5bf31df | 101 | if (read_memory_nobpt (pc, buf, sizeof (buf))) |
690668cc | 102 | return 0; |
c906108c | 103 | |
386c036b MK |
104 | insn = 0; |
105 | for (i = 0; i < sizeof (buf); i++) | |
106 | insn = (insn << 8) | buf[i]; | |
107 | return insn; | |
108 | } | |
42cdca6c MK |
109 | \f |
110 | ||
5465445a JB |
111 | /* Return non-zero if the instruction corresponding to PC is an "unimp" |
112 | instruction. */ | |
113 | ||
114 | static int | |
115 | sparc_is_unimp_insn (CORE_ADDR pc) | |
116 | { | |
117 | const unsigned long insn = sparc_fetch_instruction (pc); | |
118 | ||
119 | return ((insn & 0xc1c00000) == 0); | |
120 | } | |
121 | ||
42cdca6c MK |
122 | /* OpenBSD/sparc includes StackGhost, which according to the author's |
123 | website http://stackghost.cerias.purdue.edu "... transparently and | |
124 | automatically protects applications' stack frames; more | |
125 | specifically, it guards the return pointers. The protection | |
126 | mechanisms require no application source or binary modification and | |
127 | imposes only a negligible performance penalty." | |
128 | ||
129 | The same website provides the following description of how | |
130 | StackGhost works: | |
131 | ||
132 | "StackGhost interfaces with the kernel trap handler that would | |
133 | normally write out registers to the stack and the handler that | |
134 | would read them back in. By XORing a cookie into the | |
135 | return-address saved in the user stack when it is actually written | |
136 | to the stack, and then XOR it out when the return-address is pulled | |
137 | from the stack, StackGhost can cause attacker corrupted return | |
138 | pointers to behave in a manner the attacker cannot predict. | |
139 | StackGhost can also use several unused bits in the return pointer | |
140 | to detect a smashed return pointer and abort the process." | |
141 | ||
142 | For GDB this means that whenever we're reading %i7 from a stack | |
143 | frame's window save area, we'll have to XOR the cookie. | |
144 | ||
145 | More information on StackGuard can be found on in: | |
146 | ||
147 | Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated | |
148 | Stack Protection." 2001. Published in USENIX Security Symposium | |
149 | '01. */ | |
150 | ||
151 | /* Fetch StackGhost Per-Process XOR cookie. */ | |
152 | ||
153 | ULONGEST | |
154 | sparc_fetch_wcookie (void) | |
155 | { | |
baf92889 | 156 | struct target_ops *ops = ¤t_target; |
e1613aba | 157 | gdb_byte buf[8]; |
baf92889 MK |
158 | int len; |
159 | ||
13547ab6 | 160 | len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8); |
baf92889 MK |
161 | if (len == -1) |
162 | return 0; | |
42cdca6c | 163 | |
baf92889 MK |
164 | /* We should have either an 32-bit or an 64-bit cookie. */ |
165 | gdb_assert (len == 4 || len == 8); | |
166 | ||
167 | return extract_unsigned_integer (buf, len); | |
168 | } | |
386c036b | 169 | \f |
baf92889 | 170 | |
386c036b MK |
171 | /* The functions on this page are intended to be used to classify |
172 | function arguments. */ | |
c906108c | 173 | |
386c036b | 174 | /* Check whether TYPE is "Integral or Pointer". */ |
c906108c | 175 | |
386c036b MK |
176 | static int |
177 | sparc_integral_or_pointer_p (const struct type *type) | |
c906108c | 178 | { |
80ad1639 MK |
179 | int len = TYPE_LENGTH (type); |
180 | ||
386c036b | 181 | switch (TYPE_CODE (type)) |
c906108c | 182 | { |
386c036b MK |
183 | case TYPE_CODE_INT: |
184 | case TYPE_CODE_BOOL: | |
185 | case TYPE_CODE_CHAR: | |
186 | case TYPE_CODE_ENUM: | |
187 | case TYPE_CODE_RANGE: | |
80ad1639 MK |
188 | /* We have byte, half-word, word and extended-word/doubleword |
189 | integral types. The doubleword is an extension to the | |
190 | original 32-bit ABI by the SCD 2.4.x. */ | |
191 | return (len == 1 || len == 2 || len == 4 || len == 8); | |
386c036b MK |
192 | case TYPE_CODE_PTR: |
193 | case TYPE_CODE_REF: | |
80ad1639 MK |
194 | /* Allow either 32-bit or 64-bit pointers. */ |
195 | return (len == 4 || len == 8); | |
386c036b MK |
196 | default: |
197 | break; | |
198 | } | |
c906108c | 199 | |
386c036b MK |
200 | return 0; |
201 | } | |
c906108c | 202 | |
386c036b | 203 | /* Check whether TYPE is "Floating". */ |
c906108c | 204 | |
386c036b MK |
205 | static int |
206 | sparc_floating_p (const struct type *type) | |
207 | { | |
208 | switch (TYPE_CODE (type)) | |
c906108c | 209 | { |
386c036b MK |
210 | case TYPE_CODE_FLT: |
211 | { | |
212 | int len = TYPE_LENGTH (type); | |
213 | return (len == 4 || len == 8 || len == 16); | |
214 | } | |
215 | default: | |
216 | break; | |
217 | } | |
218 | ||
219 | return 0; | |
220 | } | |
c906108c | 221 | |
386c036b | 222 | /* Check whether TYPE is "Structure or Union". */ |
c906108c | 223 | |
386c036b MK |
224 | static int |
225 | sparc_structure_or_union_p (const struct type *type) | |
226 | { | |
227 | switch (TYPE_CODE (type)) | |
228 | { | |
229 | case TYPE_CODE_STRUCT: | |
230 | case TYPE_CODE_UNION: | |
231 | return 1; | |
232 | default: | |
233 | break; | |
c906108c | 234 | } |
386c036b MK |
235 | |
236 | return 0; | |
c906108c | 237 | } |
386c036b MK |
238 | |
239 | /* Register information. */ | |
240 | ||
241 | static const char *sparc32_register_names[] = | |
5af923b0 | 242 | { |
386c036b MK |
243 | "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
244 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", | |
245 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", | |
246 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", | |
247 | ||
248 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
249 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
250 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
251 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
252 | ||
253 | "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" | |
5af923b0 MS |
254 | }; |
255 | ||
386c036b MK |
256 | /* Total number of registers. */ |
257 | #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) | |
c906108c | 258 | |
386c036b MK |
259 | /* We provide the aliases %d0..%d30 for the floating registers as |
260 | "psuedo" registers. */ | |
261 | ||
262 | static const char *sparc32_pseudo_register_names[] = | |
263 | { | |
264 | "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", | |
265 | "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" | |
266 | }; | |
267 | ||
268 | /* Total number of pseudo registers. */ | |
269 | #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) | |
270 | ||
271 | /* Return the name of register REGNUM. */ | |
272 | ||
273 | static const char * | |
d93859e2 | 274 | sparc32_register_name (struct gdbarch *gdbarch, int regnum) |
386c036b MK |
275 | { |
276 | if (regnum >= 0 && regnum < SPARC32_NUM_REGS) | |
277 | return sparc32_register_names[regnum]; | |
278 | ||
279 | if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS) | |
280 | return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS]; | |
281 | ||
282 | return NULL; | |
283 | } | |
2d457077 MK |
284 | \f |
285 | ||
286 | /* Type for %psr. */ | |
287 | struct type *sparc_psr_type; | |
288 | ||
289 | /* Type for %fsr. */ | |
290 | struct type *sparc_fsr_type; | |
291 | ||
292 | /* Construct types for ISA-specific registers. */ | |
293 | ||
294 | static void | |
295 | sparc_init_types (void) | |
296 | { | |
297 | struct type *type; | |
298 | ||
299 | type = init_flags_type ("builtin_type_sparc_psr", 4); | |
300 | append_flags_type_flag (type, 5, "ET"); | |
301 | append_flags_type_flag (type, 6, "PS"); | |
302 | append_flags_type_flag (type, 7, "S"); | |
303 | append_flags_type_flag (type, 12, "EF"); | |
304 | append_flags_type_flag (type, 13, "EC"); | |
305 | sparc_psr_type = type; | |
306 | ||
307 | type = init_flags_type ("builtin_type_sparc_fsr", 4); | |
308 | append_flags_type_flag (type, 0, "NXA"); | |
309 | append_flags_type_flag (type, 1, "DZA"); | |
310 | append_flags_type_flag (type, 2, "UFA"); | |
311 | append_flags_type_flag (type, 3, "OFA"); | |
312 | append_flags_type_flag (type, 4, "NVA"); | |
313 | append_flags_type_flag (type, 5, "NXC"); | |
314 | append_flags_type_flag (type, 6, "DZC"); | |
315 | append_flags_type_flag (type, 7, "UFC"); | |
316 | append_flags_type_flag (type, 8, "OFC"); | |
317 | append_flags_type_flag (type, 9, "NVC"); | |
318 | append_flags_type_flag (type, 22, "NS"); | |
319 | append_flags_type_flag (type, 23, "NXM"); | |
320 | append_flags_type_flag (type, 24, "DZM"); | |
321 | append_flags_type_flag (type, 25, "UFM"); | |
322 | append_flags_type_flag (type, 26, "OFM"); | |
323 | append_flags_type_flag (type, 27, "NVM"); | |
324 | sparc_fsr_type = type; | |
325 | } | |
386c036b MK |
326 | |
327 | /* Return the GDB type object for the "standard" data type of data in | |
328 | register REGNUM. */ | |
329 | ||
330 | static struct type * | |
331 | sparc32_register_type (struct gdbarch *gdbarch, int regnum) | |
332 | { | |
333 | if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) | |
334 | return builtin_type_float; | |
335 | ||
336 | if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) | |
337 | return builtin_type_double; | |
338 | ||
339 | if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) | |
340 | return builtin_type_void_data_ptr; | |
341 | ||
342 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) | |
343 | return builtin_type_void_func_ptr; | |
344 | ||
2d457077 MK |
345 | if (regnum == SPARC32_PSR_REGNUM) |
346 | return sparc_psr_type; | |
347 | ||
348 | if (regnum == SPARC32_FSR_REGNUM) | |
349 | return sparc_fsr_type; | |
350 | ||
386c036b MK |
351 | return builtin_type_int32; |
352 | } | |
353 | ||
354 | static void | |
355 | sparc32_pseudo_register_read (struct gdbarch *gdbarch, | |
356 | struct regcache *regcache, | |
e1613aba | 357 | int regnum, gdb_byte *buf) |
386c036b MK |
358 | { |
359 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); | |
360 | ||
361 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
362 | regcache_raw_read (regcache, regnum, buf); | |
e1613aba | 363 | regcache_raw_read (regcache, regnum + 1, buf + 4); |
386c036b MK |
364 | } |
365 | ||
366 | static void | |
367 | sparc32_pseudo_register_write (struct gdbarch *gdbarch, | |
368 | struct regcache *regcache, | |
e1613aba | 369 | int regnum, const gdb_byte *buf) |
386c036b MK |
370 | { |
371 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); | |
372 | ||
373 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
374 | regcache_raw_write (regcache, regnum, buf); | |
e1613aba | 375 | regcache_raw_write (regcache, regnum + 1, buf + 4); |
386c036b MK |
376 | } |
377 | \f | |
378 | ||
379 | static CORE_ADDR | |
380 | sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
82585c72 | 381 | CORE_ADDR funcaddr, |
386c036b MK |
382 | struct value **args, int nargs, |
383 | struct type *value_type, | |
e4fd649a UW |
384 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, |
385 | struct regcache *regcache) | |
c906108c | 386 | { |
386c036b MK |
387 | *bp_addr = sp - 4; |
388 | *real_pc = funcaddr; | |
389 | ||
82585c72 | 390 | if (using_struct_return (value_type)) |
c906108c | 391 | { |
e1613aba | 392 | gdb_byte buf[4]; |
386c036b MK |
393 | |
394 | /* This is an UNIMP instruction. */ | |
395 | store_unsigned_integer (buf, 4, TYPE_LENGTH (value_type) & 0x1fff); | |
396 | write_memory (sp - 8, buf, 4); | |
397 | return sp - 8; | |
c906108c SS |
398 | } |
399 | ||
386c036b MK |
400 | return sp - 4; |
401 | } | |
402 | ||
403 | static CORE_ADDR | |
404 | sparc32_store_arguments (struct regcache *regcache, int nargs, | |
405 | struct value **args, CORE_ADDR sp, | |
406 | int struct_return, CORE_ADDR struct_addr) | |
407 | { | |
408 | /* Number of words in the "parameter array". */ | |
409 | int num_elements = 0; | |
410 | int element = 0; | |
411 | int i; | |
412 | ||
413 | for (i = 0; i < nargs; i++) | |
c906108c | 414 | { |
4991999e | 415 | struct type *type = value_type (args[i]); |
386c036b MK |
416 | int len = TYPE_LENGTH (type); |
417 | ||
418 | if (sparc_structure_or_union_p (type) | |
419 | || (sparc_floating_p (type) && len == 16)) | |
c906108c | 420 | { |
386c036b MK |
421 | /* Structure, Union and Quad-Precision Arguments. */ |
422 | sp -= len; | |
423 | ||
424 | /* Use doubleword alignment for these values. That's always | |
425 | correct, and wasting a few bytes shouldn't be a problem. */ | |
426 | sp &= ~0x7; | |
427 | ||
0fd88904 | 428 | write_memory (sp, value_contents (args[i]), len); |
386c036b MK |
429 | args[i] = value_from_pointer (lookup_pointer_type (type), sp); |
430 | num_elements++; | |
431 | } | |
432 | else if (sparc_floating_p (type)) | |
433 | { | |
434 | /* Floating arguments. */ | |
435 | gdb_assert (len == 4 || len == 8); | |
436 | num_elements += (len / 4); | |
c906108c | 437 | } |
c5aa993b JM |
438 | else |
439 | { | |
386c036b MK |
440 | /* Integral and pointer arguments. */ |
441 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
442 | ||
443 | if (len < 4) | |
444 | args[i] = value_cast (builtin_type_int32, args[i]); | |
445 | num_elements += ((len + 3) / 4); | |
c5aa993b | 446 | } |
c906108c | 447 | } |
c906108c | 448 | |
386c036b MK |
449 | /* Always allocate at least six words. */ |
450 | sp -= max (6, num_elements) * 4; | |
c906108c | 451 | |
386c036b MK |
452 | /* The psABI says that "Software convention requires space for the |
453 | struct/union return value pointer, even if the word is unused." */ | |
454 | sp -= 4; | |
c906108c | 455 | |
386c036b MK |
456 | /* The psABI says that "Although software convention and the |
457 | operating system require every stack frame to be doubleword | |
458 | aligned." */ | |
459 | sp &= ~0x7; | |
c906108c | 460 | |
386c036b | 461 | for (i = 0; i < nargs; i++) |
c906108c | 462 | { |
0fd88904 | 463 | const bfd_byte *valbuf = value_contents (args[i]); |
4991999e | 464 | struct type *type = value_type (args[i]); |
386c036b | 465 | int len = TYPE_LENGTH (type); |
c906108c | 466 | |
386c036b | 467 | gdb_assert (len == 4 || len == 8); |
c906108c | 468 | |
386c036b MK |
469 | if (element < 6) |
470 | { | |
471 | int regnum = SPARC_O0_REGNUM + element; | |
c906108c | 472 | |
386c036b MK |
473 | regcache_cooked_write (regcache, regnum, valbuf); |
474 | if (len > 4 && element < 5) | |
475 | regcache_cooked_write (regcache, regnum + 1, valbuf + 4); | |
476 | } | |
5af923b0 | 477 | |
386c036b MK |
478 | /* Always store the argument in memory. */ |
479 | write_memory (sp + 4 + element * 4, valbuf, len); | |
480 | element += len / 4; | |
481 | } | |
c906108c | 482 | |
386c036b | 483 | gdb_assert (element == num_elements); |
c906108c | 484 | |
386c036b | 485 | if (struct_return) |
c906108c | 486 | { |
e1613aba | 487 | gdb_byte buf[4]; |
c906108c | 488 | |
386c036b MK |
489 | store_unsigned_integer (buf, 4, struct_addr); |
490 | write_memory (sp, buf, 4); | |
491 | } | |
c906108c | 492 | |
386c036b | 493 | return sp; |
c906108c SS |
494 | } |
495 | ||
386c036b | 496 | static CORE_ADDR |
7d9b040b | 497 | sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
386c036b MK |
498 | struct regcache *regcache, CORE_ADDR bp_addr, |
499 | int nargs, struct value **args, CORE_ADDR sp, | |
500 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 501 | { |
386c036b MK |
502 | CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8)); |
503 | ||
504 | /* Set return address. */ | |
505 | regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); | |
506 | ||
507 | /* Set up function arguments. */ | |
508 | sp = sparc32_store_arguments (regcache, nargs, args, sp, | |
509 | struct_return, struct_addr); | |
510 | ||
511 | /* Allocate the 16-word window save area. */ | |
512 | sp -= 16 * 4; | |
c906108c | 513 | |
386c036b MK |
514 | /* Stack should be doubleword aligned at this point. */ |
515 | gdb_assert (sp % 8 == 0); | |
c906108c | 516 | |
386c036b MK |
517 | /* Finally, update the stack pointer. */ |
518 | regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); | |
519 | ||
520 | return sp; | |
521 | } | |
522 | \f | |
c906108c | 523 | |
386c036b MK |
524 | /* Use the program counter to determine the contents and size of a |
525 | breakpoint instruction. Return a pointer to a string of bytes that | |
526 | encode a breakpoint instruction, store the length of the string in | |
527 | *LEN and optionally adjust *PC to point to the correct memory | |
528 | location for inserting the breakpoint. */ | |
529 | ||
e1613aba | 530 | static const gdb_byte * |
386c036b MK |
531 | sparc_breakpoint_from_pc (CORE_ADDR *pc, int *len) |
532 | { | |
864a1a37 | 533 | static const gdb_byte break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; |
c5aa993b | 534 | |
386c036b MK |
535 | *len = sizeof (break_insn); |
536 | return break_insn; | |
c906108c | 537 | } |
386c036b | 538 | \f |
c906108c | 539 | |
386c036b | 540 | /* Allocate and initialize a frame cache. */ |
c906108c | 541 | |
386c036b MK |
542 | static struct sparc_frame_cache * |
543 | sparc_alloc_frame_cache (void) | |
544 | { | |
545 | struct sparc_frame_cache *cache; | |
546 | int i; | |
c906108c | 547 | |
386c036b | 548 | cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); |
c906108c | 549 | |
386c036b MK |
550 | /* Base address. */ |
551 | cache->base = 0; | |
552 | cache->pc = 0; | |
c906108c | 553 | |
386c036b MK |
554 | /* Frameless until proven otherwise. */ |
555 | cache->frameless_p = 1; | |
556 | ||
557 | cache->struct_return_p = 0; | |
558 | ||
559 | return cache; | |
560 | } | |
561 | ||
b0b92586 JB |
562 | /* GCC generates several well-known sequences of instructions at the begining |
563 | of each function prologue when compiling with -fstack-check. If one of | |
564 | such sequences starts at START_PC, then return the address of the | |
565 | instruction immediately past this sequence. Otherwise, return START_PC. */ | |
566 | ||
567 | static CORE_ADDR | |
568 | sparc_skip_stack_check (const CORE_ADDR start_pc) | |
569 | { | |
570 | CORE_ADDR pc = start_pc; | |
571 | unsigned long insn; | |
572 | int offset_stack_checking_sequence = 0; | |
573 | ||
574 | /* With GCC, all stack checking sequences begin with the same two | |
575 | instructions. */ | |
576 | ||
577 | /* sethi <some immediate>,%g1 */ | |
578 | insn = sparc_fetch_instruction (pc); | |
579 | pc = pc + 4; | |
580 | if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1)) | |
581 | return start_pc; | |
582 | ||
583 | /* sub %sp, %g1, %g1 */ | |
584 | insn = sparc_fetch_instruction (pc); | |
585 | pc = pc + 4; | |
586 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) | |
587 | && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1)) | |
588 | return start_pc; | |
589 | ||
590 | insn = sparc_fetch_instruction (pc); | |
591 | pc = pc + 4; | |
592 | ||
593 | /* First possible sequence: | |
594 | [first two instructions above] | |
595 | clr [%g1 - some immediate] */ | |
596 | ||
597 | /* clr [%g1 - some immediate] */ | |
598 | if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
599 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
600 | { | |
601 | /* Valid stack-check sequence, return the new PC. */ | |
602 | return pc; | |
603 | } | |
604 | ||
605 | /* Second possible sequence: A small number of probes. | |
606 | [first two instructions above] | |
607 | clr [%g1] | |
608 | add %g1, -<some immediate>, %g1 | |
609 | clr [%g1] | |
610 | [repeat the two instructions above any (small) number of times] | |
611 | clr [%g1 - some immediate] */ | |
612 | ||
613 | /* clr [%g1] */ | |
614 | else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
615 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
616 | { | |
617 | while (1) | |
618 | { | |
619 | /* add %g1, -<some immediate>, %g1 */ | |
620 | insn = sparc_fetch_instruction (pc); | |
621 | pc = pc + 4; | |
622 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
623 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
624 | break; | |
625 | ||
626 | /* clr [%g1] */ | |
627 | insn = sparc_fetch_instruction (pc); | |
628 | pc = pc + 4; | |
629 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
630 | && X_RD (insn) == 0 && X_RS1 (insn) == 1)) | |
631 | return start_pc; | |
632 | } | |
633 | ||
634 | /* clr [%g1 - some immediate] */ | |
635 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
636 | && X_RS1 (insn) == 1 && X_RD (insn) == 0)) | |
637 | return start_pc; | |
638 | ||
639 | /* We found a valid stack-check sequence, return the new PC. */ | |
640 | return pc; | |
641 | } | |
642 | ||
643 | /* Third sequence: A probing loop. | |
644 | [first two instructions above] | |
645 | sethi <some immediate>, %g4 | |
646 | sub %g1, %g4, %g4 | |
647 | cmp %g1, %g4 | |
648 | be <disp> | |
649 | add %g1, -<some immediate>, %g1 | |
650 | ba <disp> | |
651 | clr [%g1] | |
652 | clr [%g4 - some immediate] */ | |
653 | ||
654 | /* sethi <some immediate>, %g4 */ | |
655 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) | |
656 | { | |
657 | /* sub %g1, %g4, %g4 */ | |
658 | insn = sparc_fetch_instruction (pc); | |
659 | pc = pc + 4; | |
660 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) | |
661 | && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
662 | return start_pc; | |
663 | ||
664 | /* cmp %g1, %g4 */ | |
665 | insn = sparc_fetch_instruction (pc); | |
666 | pc = pc + 4; | |
667 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn) | |
668 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
669 | return start_pc; | |
670 | ||
671 | /* be <disp> */ | |
672 | insn = sparc_fetch_instruction (pc); | |
673 | pc = pc + 4; | |
674 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1)) | |
675 | return start_pc; | |
676 | ||
677 | /* add %g1, -<some immediate>, %g1 */ | |
678 | insn = sparc_fetch_instruction (pc); | |
679 | pc = pc + 4; | |
680 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
681 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
682 | return start_pc; | |
683 | ||
684 | /* ba <disp> */ | |
685 | insn = sparc_fetch_instruction (pc); | |
686 | pc = pc + 4; | |
687 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8)) | |
688 | return start_pc; | |
689 | ||
690 | /* clr [%g1] */ | |
691 | insn = sparc_fetch_instruction (pc); | |
692 | pc = pc + 4; | |
693 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
694 | && X_RD (insn) == 0 && X_RS1 (insn) == 1)) | |
695 | return start_pc; | |
696 | ||
697 | /* clr [%g4 - some immediate] */ | |
698 | insn = sparc_fetch_instruction (pc); | |
699 | pc = pc + 4; | |
700 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
701 | && X_RS1 (insn) == 4 && X_RD (insn) == 0)) | |
702 | return start_pc; | |
703 | ||
704 | /* We found a valid stack-check sequence, return the new PC. */ | |
705 | return pc; | |
706 | } | |
707 | ||
708 | /* No stack check code in our prologue, return the start_pc. */ | |
709 | return start_pc; | |
710 | } | |
711 | ||
386c036b MK |
712 | CORE_ADDR |
713 | sparc_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, | |
714 | struct sparc_frame_cache *cache) | |
c906108c | 715 | { |
386c036b MK |
716 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
717 | unsigned long insn; | |
718 | int offset = 0; | |
c906108c | 719 | int dest = -1; |
c906108c | 720 | |
b0b92586 JB |
721 | pc = sparc_skip_stack_check (pc); |
722 | ||
386c036b MK |
723 | if (current_pc <= pc) |
724 | return current_pc; | |
725 | ||
726 | /* We have to handle to "Procedure Linkage Table" (PLT) special. On | |
727 | SPARC the linker usually defines a symbol (typically | |
728 | _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. | |
729 | This symbol makes us end up here with PC pointing at the start of | |
730 | the PLT and CURRENT_PC probably pointing at a PLT entry. If we | |
731 | would do our normal prologue analysis, we would probably conclude | |
732 | that we've got a frame when in reality we don't, since the | |
733 | dynamic linker patches up the first PLT with some code that | |
734 | starts with a SAVE instruction. Patch up PC such that it points | |
735 | at the start of our PLT entry. */ | |
736 | if (tdep->plt_entry_size > 0 && in_plt_section (current_pc, NULL)) | |
737 | pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); | |
c906108c | 738 | |
386c036b MK |
739 | insn = sparc_fetch_instruction (pc); |
740 | ||
741 | /* Recognize a SETHI insn and record its destination. */ | |
742 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) | |
c906108c SS |
743 | { |
744 | dest = X_RD (insn); | |
386c036b MK |
745 | offset += 4; |
746 | ||
747 | insn = sparc_fetch_instruction (pc + 4); | |
c906108c SS |
748 | } |
749 | ||
386c036b MK |
750 | /* Allow for an arithmetic operation on DEST or %g1. */ |
751 | if (X_OP (insn) == 2 && X_I (insn) | |
c906108c SS |
752 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) |
753 | { | |
386c036b | 754 | offset += 4; |
c906108c | 755 | |
386c036b | 756 | insn = sparc_fetch_instruction (pc + 8); |
c906108c | 757 | } |
c906108c | 758 | |
386c036b MK |
759 | /* Check for the SAVE instruction that sets up the frame. */ |
760 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) | |
c906108c | 761 | { |
386c036b MK |
762 | cache->frameless_p = 0; |
763 | return pc + offset + 4; | |
c906108c SS |
764 | } |
765 | ||
766 | return pc; | |
767 | } | |
768 | ||
386c036b MK |
769 | static CORE_ADDR |
770 | sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
771 | { | |
772 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
773 | return frame_unwind_register_unsigned (next_frame, tdep->pc_regnum); | |
774 | } | |
775 | ||
776 | /* Return PC of first real instruction of the function starting at | |
777 | START_PC. */ | |
f510d44e | 778 | |
386c036b MK |
779 | static CORE_ADDR |
780 | sparc32_skip_prologue (CORE_ADDR start_pc) | |
c906108c | 781 | { |
f510d44e DM |
782 | struct symtab_and_line sal; |
783 | CORE_ADDR func_start, func_end; | |
386c036b | 784 | struct sparc_frame_cache cache; |
f510d44e DM |
785 | |
786 | /* This is the preferred method, find the end of the prologue by | |
787 | using the debugging information. */ | |
788 | if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) | |
789 | { | |
790 | sal = find_pc_line (func_start, 0); | |
791 | ||
792 | if (sal.end < func_end | |
793 | && start_pc <= sal.end) | |
794 | return sal.end; | |
795 | } | |
796 | ||
075ccec8 MK |
797 | start_pc = sparc_analyze_prologue (start_pc, 0xffffffffUL, &cache); |
798 | ||
799 | /* The psABI says that "Although the first 6 words of arguments | |
800 | reside in registers, the standard stack frame reserves space for | |
801 | them.". It also suggests that a function may use that space to | |
802 | "write incoming arguments 0 to 5" into that space, and that's | |
803 | indeed what GCC seems to be doing. In that case GCC will | |
804 | generate debug information that points to the stack slots instead | |
805 | of the registers, so we should consider the instructions that | |
806 | write out these incoming arguments onto the stack. Of course we | |
807 | only need to do this if we have a stack frame. */ | |
808 | ||
809 | while (!cache.frameless_p) | |
810 | { | |
811 | unsigned long insn = sparc_fetch_instruction (start_pc); | |
812 | ||
813 | /* Recognize instructions that store incoming arguments in | |
814 | %i0...%i5 into the corresponding stack slot. */ | |
815 | if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 && X_I (insn) | |
816 | && (X_RD (insn) >= 24 && X_RD (insn) <= 29) && X_RS1 (insn) == 30 | |
817 | && X_SIMM13 (insn) == 68 + (X_RD (insn) - 24) * 4) | |
818 | { | |
819 | start_pc += 4; | |
820 | continue; | |
821 | } | |
822 | ||
823 | break; | |
824 | } | |
825 | ||
826 | return start_pc; | |
c906108c SS |
827 | } |
828 | ||
386c036b | 829 | /* Normal frames. */ |
9319a2fe | 830 | |
386c036b MK |
831 | struct sparc_frame_cache * |
832 | sparc_frame_cache (struct frame_info *next_frame, void **this_cache) | |
9319a2fe | 833 | { |
386c036b | 834 | struct sparc_frame_cache *cache; |
9319a2fe | 835 | |
386c036b MK |
836 | if (*this_cache) |
837 | return *this_cache; | |
c906108c | 838 | |
386c036b MK |
839 | cache = sparc_alloc_frame_cache (); |
840 | *this_cache = cache; | |
c906108c | 841 | |
93d42b30 | 842 | cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME); |
386c036b | 843 | if (cache->pc != 0) |
93d42b30 | 844 | sparc_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache); |
386c036b MK |
845 | |
846 | if (cache->frameless_p) | |
c906108c | 847 | { |
cbeae229 MK |
848 | /* This function is frameless, so %fp (%i6) holds the frame |
849 | pointer for our calling frame. Use %sp (%o6) as this frame's | |
850 | base address. */ | |
851 | cache->base = | |
852 | frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM); | |
853 | } | |
854 | else | |
855 | { | |
856 | /* For normal frames, %fp (%i6) holds the frame pointer, the | |
857 | base address for the current stack frame. */ | |
858 | cache->base = | |
859 | frame_unwind_register_unsigned (next_frame, SPARC_FP_REGNUM); | |
c906108c | 860 | } |
c906108c | 861 | |
5b2d44a0 MK |
862 | if (cache->base & 1) |
863 | cache->base += BIAS; | |
864 | ||
386c036b | 865 | return cache; |
c906108c | 866 | } |
c906108c | 867 | |
aff37fc1 DM |
868 | static int |
869 | sparc32_struct_return_from_sym (struct symbol *sym) | |
870 | { | |
871 | struct type *type = check_typedef (SYMBOL_TYPE (sym)); | |
872 | enum type_code code = TYPE_CODE (type); | |
873 | ||
874 | if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) | |
875 | { | |
876 | type = check_typedef (TYPE_TARGET_TYPE (type)); | |
877 | if (sparc_structure_or_union_p (type) | |
878 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
879 | return 1; | |
880 | } | |
881 | ||
882 | return 0; | |
883 | } | |
884 | ||
386c036b MK |
885 | struct sparc_frame_cache * |
886 | sparc32_frame_cache (struct frame_info *next_frame, void **this_cache) | |
c906108c | 887 | { |
386c036b MK |
888 | struct sparc_frame_cache *cache; |
889 | struct symbol *sym; | |
c906108c | 890 | |
386c036b MK |
891 | if (*this_cache) |
892 | return *this_cache; | |
c906108c | 893 | |
386c036b | 894 | cache = sparc_frame_cache (next_frame, this_cache); |
c906108c | 895 | |
386c036b MK |
896 | sym = find_pc_function (cache->pc); |
897 | if (sym) | |
c906108c | 898 | { |
aff37fc1 | 899 | cache->struct_return_p = sparc32_struct_return_from_sym (sym); |
c906108c | 900 | } |
5465445a JB |
901 | else |
902 | { | |
903 | /* There is no debugging information for this function to | |
904 | help us determine whether this function returns a struct | |
905 | or not. So we rely on another heuristic which is to check | |
906 | the instruction at the return address and see if this is | |
907 | an "unimp" instruction. If it is, then it is a struct-return | |
908 | function. */ | |
909 | CORE_ADDR pc; | |
910 | int regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM; | |
911 | ||
912 | pc = frame_unwind_register_unsigned (next_frame, regnum) + 8; | |
913 | if (sparc_is_unimp_insn (pc)) | |
914 | cache->struct_return_p = 1; | |
915 | } | |
c906108c | 916 | |
386c036b MK |
917 | return cache; |
918 | } | |
919 | ||
920 | static void | |
921 | sparc32_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
922 | struct frame_id *this_id) | |
923 | { | |
924 | struct sparc_frame_cache *cache = | |
925 | sparc32_frame_cache (next_frame, this_cache); | |
926 | ||
927 | /* This marks the outermost frame. */ | |
928 | if (cache->base == 0) | |
929 | return; | |
930 | ||
931 | (*this_id) = frame_id_build (cache->base, cache->pc); | |
932 | } | |
c906108c | 933 | |
386c036b MK |
934 | static void |
935 | sparc32_frame_prev_register (struct frame_info *next_frame, void **this_cache, | |
936 | int regnum, int *optimizedp, | |
937 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
47ef841b | 938 | int *realnump, gdb_byte *valuep) |
386c036b MK |
939 | { |
940 | struct sparc_frame_cache *cache = | |
941 | sparc32_frame_cache (next_frame, this_cache); | |
c906108c | 942 | |
386c036b | 943 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) |
c906108c | 944 | { |
386c036b MK |
945 | *optimizedp = 0; |
946 | *lvalp = not_lval; | |
947 | *addrp = 0; | |
948 | *realnump = -1; | |
949 | if (valuep) | |
c906108c | 950 | { |
386c036b MK |
951 | CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; |
952 | ||
953 | /* If this functions has a Structure, Union or | |
954 | Quad-Precision return value, we have to skip the UNIMP | |
955 | instruction that encodes the size of the structure. */ | |
956 | if (cache->struct_return_p) | |
957 | pc += 4; | |
958 | ||
959 | regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM; | |
960 | pc += frame_unwind_register_unsigned (next_frame, regnum) + 8; | |
961 | store_unsigned_integer (valuep, 4, pc); | |
c906108c | 962 | } |
c906108c SS |
963 | return; |
964 | } | |
965 | ||
42cdca6c MK |
966 | /* Handle StackGhost. */ |
967 | { | |
968 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
969 | ||
970 | if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM) | |
971 | { | |
972 | *optimizedp = 0; | |
973 | *lvalp = not_lval; | |
974 | *addrp = 0; | |
975 | *realnump = -1; | |
976 | if (valuep) | |
977 | { | |
978 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; | |
7d34766b | 979 | ULONGEST i7; |
42cdca6c MK |
980 | |
981 | /* Read the value in from memory. */ | |
7d34766b MK |
982 | i7 = get_frame_memory_unsigned (next_frame, addr, 4); |
983 | store_unsigned_integer (valuep, 4, i7 ^ wcookie); | |
42cdca6c MK |
984 | } |
985 | return; | |
986 | } | |
987 | } | |
988 | ||
386c036b MK |
989 | /* The previous frame's `local' and `in' registers have been saved |
990 | in the register save area. */ | |
991 | if (!cache->frameless_p | |
992 | && regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) | |
c906108c | 993 | { |
386c036b MK |
994 | *optimizedp = 0; |
995 | *lvalp = lval_memory; | |
996 | *addrp = cache->base + (regnum - SPARC_L0_REGNUM) * 4; | |
997 | *realnump = -1; | |
998 | if (valuep) | |
c906108c | 999 | { |
386c036b MK |
1000 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
1001 | ||
1002 | /* Read the value in from memory. */ | |
1003 | read_memory (*addrp, valuep, register_size (gdbarch, regnum)); | |
c906108c | 1004 | } |
386c036b MK |
1005 | return; |
1006 | } | |
c906108c | 1007 | |
386c036b MK |
1008 | /* The previous frame's `out' registers are accessable as the |
1009 | current frame's `in' registers. */ | |
1010 | if (!cache->frameless_p | |
1011 | && regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM) | |
1012 | regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); | |
5af923b0 | 1013 | |
00b25ff3 AC |
1014 | *optimizedp = 0; |
1015 | *lvalp = lval_register; | |
1016 | *addrp = 0; | |
1017 | *realnump = regnum; | |
1018 | if (valuep) | |
1019 | frame_unwind_register (next_frame, (*realnump), valuep); | |
386c036b | 1020 | } |
c906108c | 1021 | |
386c036b MK |
1022 | static const struct frame_unwind sparc32_frame_unwind = |
1023 | { | |
1024 | NORMAL_FRAME, | |
1025 | sparc32_frame_this_id, | |
1026 | sparc32_frame_prev_register | |
1027 | }; | |
1028 | ||
1029 | static const struct frame_unwind * | |
1030 | sparc32_frame_sniffer (struct frame_info *next_frame) | |
1031 | { | |
1032 | return &sparc32_frame_unwind; | |
c906108c | 1033 | } |
386c036b | 1034 | \f |
c906108c | 1035 | |
386c036b MK |
1036 | static CORE_ADDR |
1037 | sparc32_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
1038 | { | |
1039 | struct sparc_frame_cache *cache = | |
1040 | sparc32_frame_cache (next_frame, this_cache); | |
c906108c | 1041 | |
386c036b MK |
1042 | return cache->base; |
1043 | } | |
c906108c | 1044 | |
386c036b MK |
1045 | static const struct frame_base sparc32_frame_base = |
1046 | { | |
1047 | &sparc32_frame_unwind, | |
1048 | sparc32_frame_base_address, | |
1049 | sparc32_frame_base_address, | |
1050 | sparc32_frame_base_address | |
1051 | }; | |
c906108c | 1052 | |
386c036b MK |
1053 | static struct frame_id |
1054 | sparc_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1055 | { | |
1056 | CORE_ADDR sp; | |
5af923b0 | 1057 | |
386c036b | 1058 | sp = frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM); |
5b2d44a0 MK |
1059 | if (sp & 1) |
1060 | sp += BIAS; | |
386c036b MK |
1061 | return frame_id_build (sp, frame_pc_unwind (next_frame)); |
1062 | } | |
1063 | \f | |
c906108c | 1064 | |
386c036b MK |
1065 | /* Extract from an array REGBUF containing the (raw) register state, a |
1066 | function return value of TYPE, and copy that into VALBUF. */ | |
5af923b0 | 1067 | |
386c036b MK |
1068 | static void |
1069 | sparc32_extract_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1070 | gdb_byte *valbuf) |
386c036b MK |
1071 | { |
1072 | int len = TYPE_LENGTH (type); | |
e1613aba | 1073 | gdb_byte buf[8]; |
c906108c | 1074 | |
386c036b MK |
1075 | gdb_assert (!sparc_structure_or_union_p (type)); |
1076 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 1077 | |
386c036b | 1078 | if (sparc_floating_p (type)) |
5af923b0 | 1079 | { |
386c036b MK |
1080 | /* Floating return values. */ |
1081 | regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf); | |
1082 | if (len > 4) | |
1083 | regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4); | |
1084 | memcpy (valbuf, buf, len); | |
5af923b0 MS |
1085 | } |
1086 | else | |
1087 | { | |
386c036b MK |
1088 | /* Integral and pointer return values. */ |
1089 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
c906108c | 1090 | |
386c036b MK |
1091 | regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); |
1092 | if (len > 4) | |
1093 | { | |
1094 | regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4); | |
1095 | gdb_assert (len == 8); | |
1096 | memcpy (valbuf, buf, 8); | |
1097 | } | |
1098 | else | |
1099 | { | |
1100 | /* Just stripping off any unused bytes should preserve the | |
1101 | signed-ness just fine. */ | |
1102 | memcpy (valbuf, buf + 4 - len, len); | |
1103 | } | |
1104 | } | |
1105 | } | |
c906108c | 1106 | |
386c036b MK |
1107 | /* Write into the appropriate registers a function return value stored |
1108 | in VALBUF of type TYPE. */ | |
c906108c | 1109 | |
386c036b MK |
1110 | static void |
1111 | sparc32_store_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1112 | const gdb_byte *valbuf) |
386c036b MK |
1113 | { |
1114 | int len = TYPE_LENGTH (type); | |
e1613aba | 1115 | gdb_byte buf[8]; |
c906108c | 1116 | |
386c036b MK |
1117 | gdb_assert (!sparc_structure_or_union_p (type)); |
1118 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 1119 | |
386c036b MK |
1120 | if (sparc_floating_p (type)) |
1121 | { | |
1122 | /* Floating return values. */ | |
1123 | memcpy (buf, valbuf, len); | |
1124 | regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf); | |
1125 | if (len > 4) | |
1126 | regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4); | |
1127 | } | |
1128 | else | |
c906108c | 1129 | { |
386c036b MK |
1130 | /* Integral and pointer return values. */ |
1131 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
1132 | ||
1133 | if (len > 4) | |
2757dd86 | 1134 | { |
386c036b MK |
1135 | gdb_assert (len == 8); |
1136 | memcpy (buf, valbuf, 8); | |
1137 | regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4); | |
2757dd86 AC |
1138 | } |
1139 | else | |
1140 | { | |
386c036b MK |
1141 | /* ??? Do we need to do any sign-extension here? */ |
1142 | memcpy (buf + 4 - len, valbuf, len); | |
2757dd86 | 1143 | } |
386c036b | 1144 | regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); |
c906108c SS |
1145 | } |
1146 | } | |
1147 | ||
b9d4c5ed MK |
1148 | static enum return_value_convention |
1149 | sparc32_return_value (struct gdbarch *gdbarch, struct type *type, | |
e1613aba MK |
1150 | struct regcache *regcache, gdb_byte *readbuf, |
1151 | const gdb_byte *writebuf) | |
b9d4c5ed | 1152 | { |
0a8f48b9 MK |
1153 | /* The psABI says that "...every stack frame reserves the word at |
1154 | %fp+64. If a function returns a structure, union, or | |
1155 | quad-precision value, this word should hold the address of the | |
1156 | object into which the return value should be copied." This | |
1157 | guarantees that we can always find the return value, not just | |
1158 | before the function returns. */ | |
1159 | ||
b9d4c5ed MK |
1160 | if (sparc_structure_or_union_p (type) |
1161 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
0a8f48b9 MK |
1162 | { |
1163 | if (readbuf) | |
1164 | { | |
1165 | ULONGEST sp; | |
1166 | CORE_ADDR addr; | |
1167 | ||
1168 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1169 | addr = read_memory_unsigned_integer (sp + 64, 4); | |
1170 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
1171 | } | |
1172 | ||
1173 | return RETURN_VALUE_ABI_PRESERVES_ADDRESS; | |
1174 | } | |
b9d4c5ed MK |
1175 | |
1176 | if (readbuf) | |
1177 | sparc32_extract_return_value (type, regcache, readbuf); | |
1178 | if (writebuf) | |
1179 | sparc32_store_return_value (type, regcache, writebuf); | |
1180 | ||
1181 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1182 | } | |
1183 | ||
386c036b MK |
1184 | static int |
1185 | sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) | |
c906108c | 1186 | { |
386c036b MK |
1187 | return (sparc_structure_or_union_p (type) |
1188 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)); | |
1189 | } | |
c906108c | 1190 | |
aff37fc1 DM |
1191 | static int |
1192 | sparc32_dwarf2_struct_return_p (struct frame_info *next_frame) | |
1193 | { | |
93d42b30 | 1194 | CORE_ADDR pc = frame_unwind_address_in_block (next_frame, NORMAL_FRAME); |
aff37fc1 DM |
1195 | struct symbol *sym = find_pc_function (pc); |
1196 | ||
1197 | if (sym) | |
1198 | return sparc32_struct_return_from_sym (sym); | |
1199 | return 0; | |
1200 | } | |
1201 | ||
f5a9b87d DM |
1202 | static void |
1203 | sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 DM |
1204 | struct dwarf2_frame_state_reg *reg, |
1205 | struct frame_info *next_frame) | |
f5a9b87d | 1206 | { |
aff37fc1 DM |
1207 | int off; |
1208 | ||
f5a9b87d DM |
1209 | switch (regnum) |
1210 | { | |
1211 | case SPARC_G0_REGNUM: | |
1212 | /* Since %g0 is always zero, there is no point in saving it, and | |
1213 | people will be inclined omit it from the CFI. Make sure we | |
1214 | don't warn about that. */ | |
1215 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
1216 | break; | |
1217 | case SPARC_SP_REGNUM: | |
1218 | reg->how = DWARF2_FRAME_REG_CFA; | |
1219 | break; | |
1220 | case SPARC32_PC_REGNUM: | |
f5a9b87d DM |
1221 | case SPARC32_NPC_REGNUM: |
1222 | reg->how = DWARF2_FRAME_REG_RA_OFFSET; | |
aff37fc1 DM |
1223 | off = 8; |
1224 | if (sparc32_dwarf2_struct_return_p (next_frame)) | |
1225 | off += 4; | |
1226 | if (regnum == SPARC32_NPC_REGNUM) | |
1227 | off += 4; | |
1228 | reg->loc.offset = off; | |
f5a9b87d DM |
1229 | break; |
1230 | } | |
1231 | } | |
1232 | ||
386c036b MK |
1233 | \f |
1234 | /* The SPARC Architecture doesn't have hardware single-step support, | |
1235 | and most operating systems don't implement it either, so we provide | |
1236 | software single-step mechanism. */ | |
c906108c | 1237 | |
386c036b | 1238 | static CORE_ADDR |
0b1b3e42 | 1239 | sparc_analyze_control_transfer (struct frame_info *frame, |
c893be75 | 1240 | CORE_ADDR pc, CORE_ADDR *npc) |
386c036b MK |
1241 | { |
1242 | unsigned long insn = sparc_fetch_instruction (pc); | |
1243 | int conditional_p = X_COND (insn) & 0x7; | |
1244 | int branch_p = 0; | |
1245 | long offset = 0; /* Must be signed for sign-extend. */ | |
c906108c | 1246 | |
386c036b | 1247 | if (X_OP (insn) == 0 && X_OP2 (insn) == 3 && (insn & 0x1000000) == 0) |
c906108c | 1248 | { |
386c036b MK |
1249 | /* Branch on Integer Register with Prediction (BPr). */ |
1250 | branch_p = 1; | |
1251 | conditional_p = 1; | |
c906108c | 1252 | } |
386c036b | 1253 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) |
c906108c | 1254 | { |
386c036b MK |
1255 | /* Branch on Floating-Point Condition Codes (FBfcc). */ |
1256 | branch_p = 1; | |
1257 | offset = 4 * X_DISP22 (insn); | |
c906108c | 1258 | } |
386c036b MK |
1259 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) |
1260 | { | |
1261 | /* Branch on Floating-Point Condition Codes with Prediction | |
1262 | (FBPfcc). */ | |
1263 | branch_p = 1; | |
1264 | offset = 4 * X_DISP19 (insn); | |
1265 | } | |
1266 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) | |
1267 | { | |
1268 | /* Branch on Integer Condition Codes (Bicc). */ | |
1269 | branch_p = 1; | |
1270 | offset = 4 * X_DISP22 (insn); | |
1271 | } | |
1272 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) | |
c906108c | 1273 | { |
386c036b MK |
1274 | /* Branch on Integer Condition Codes with Prediction (BPcc). */ |
1275 | branch_p = 1; | |
1276 | offset = 4 * X_DISP19 (insn); | |
c906108c | 1277 | } |
c893be75 MK |
1278 | else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a) |
1279 | { | |
1280 | /* Trap instruction (TRAP). */ | |
0b1b3e42 | 1281 | return gdbarch_tdep (get_frame_arch (frame))->step_trap (frame, insn); |
c893be75 | 1282 | } |
386c036b MK |
1283 | |
1284 | /* FIXME: Handle DONE and RETRY instructions. */ | |
1285 | ||
386c036b | 1286 | if (branch_p) |
c906108c | 1287 | { |
386c036b | 1288 | if (conditional_p) |
c906108c | 1289 | { |
386c036b MK |
1290 | /* For conditional branches, return nPC + 4 iff the annul |
1291 | bit is 1. */ | |
1292 | return (X_A (insn) ? *npc + 4 : 0); | |
c906108c SS |
1293 | } |
1294 | else | |
1295 | { | |
386c036b MK |
1296 | /* For unconditional branches, return the target if its |
1297 | specified condition is "always" and return nPC + 4 if the | |
1298 | condition is "never". If the annul bit is 1, set *NPC to | |
1299 | zero. */ | |
1300 | if (X_COND (insn) == 0x0) | |
1301 | pc = *npc, offset = 4; | |
1302 | if (X_A (insn)) | |
1303 | *npc = 0; | |
1304 | ||
1305 | gdb_assert (offset != 0); | |
1306 | return pc + offset; | |
c906108c SS |
1307 | } |
1308 | } | |
386c036b MK |
1309 | |
1310 | return 0; | |
c906108c SS |
1311 | } |
1312 | ||
c893be75 | 1313 | static CORE_ADDR |
0b1b3e42 | 1314 | sparc_step_trap (struct frame_info *frame, unsigned long insn) |
c893be75 MK |
1315 | { |
1316 | return 0; | |
1317 | } | |
1318 | ||
e6590a1b | 1319 | int |
0b1b3e42 | 1320 | sparc_software_single_step (struct frame_info *frame) |
386c036b | 1321 | { |
0b1b3e42 | 1322 | struct gdbarch *arch = get_frame_arch (frame); |
c893be75 | 1323 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
8181d85f | 1324 | CORE_ADDR npc, nnpc; |
c906108c | 1325 | |
e0cd558a | 1326 | CORE_ADDR pc, orig_npc; |
c906108c | 1327 | |
0b1b3e42 UW |
1328 | pc = get_frame_register_unsigned (frame, tdep->pc_regnum); |
1329 | orig_npc = npc = get_frame_register_unsigned (frame, tdep->npc_regnum); | |
c906108c | 1330 | |
e0cd558a | 1331 | /* Analyze the instruction at PC. */ |
0b1b3e42 | 1332 | nnpc = sparc_analyze_control_transfer (frame, pc, &npc); |
e0cd558a UW |
1333 | if (npc != 0) |
1334 | insert_single_step_breakpoint (npc); | |
8181d85f | 1335 | |
e0cd558a UW |
1336 | if (nnpc != 0) |
1337 | insert_single_step_breakpoint (nnpc); | |
c906108c | 1338 | |
e0cd558a UW |
1339 | /* Assert that we have set at least one breakpoint, and that |
1340 | they're not set at the same spot - unless we're going | |
1341 | from here straight to NULL, i.e. a call or jump to 0. */ | |
1342 | gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0); | |
1343 | gdb_assert (nnpc != npc || orig_npc == 0); | |
e6590a1b UW |
1344 | |
1345 | return 1; | |
386c036b MK |
1346 | } |
1347 | ||
1348 | static void | |
61a1198a | 1349 | sparc_write_pc (struct regcache *regcache, CORE_ADDR pc) |
386c036b | 1350 | { |
61a1198a | 1351 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
386c036b | 1352 | |
61a1198a UW |
1353 | regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc); |
1354 | regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4); | |
386c036b MK |
1355 | } |
1356 | \f | |
5af923b0 | 1357 | |
a54124c5 MK |
1358 | /* Return the appropriate register set for the core section identified |
1359 | by SECT_NAME and SECT_SIZE. */ | |
1360 | ||
1361 | const struct regset * | |
1362 | sparc_regset_from_core_section (struct gdbarch *gdbarch, | |
1363 | const char *sect_name, size_t sect_size) | |
1364 | { | |
1365 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1366 | ||
c558d81a | 1367 | if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset) |
a54124c5 MK |
1368 | return tdep->gregset; |
1369 | ||
c558d81a | 1370 | if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset) |
a54124c5 MK |
1371 | return tdep->fpregset; |
1372 | ||
1373 | return NULL; | |
1374 | } | |
1375 | \f | |
1376 | ||
386c036b MK |
1377 | static struct gdbarch * |
1378 | sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1379 | { | |
1380 | struct gdbarch_tdep *tdep; | |
1381 | struct gdbarch *gdbarch; | |
c906108c | 1382 | |
386c036b MK |
1383 | /* If there is already a candidate, use it. */ |
1384 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1385 | if (arches != NULL) | |
1386 | return arches->gdbarch; | |
c906108c | 1387 | |
386c036b MK |
1388 | /* Allocate space for the new architecture. */ |
1389 | tdep = XMALLOC (struct gdbarch_tdep); | |
1390 | gdbarch = gdbarch_alloc (&info, tdep); | |
5af923b0 | 1391 | |
386c036b MK |
1392 | tdep->pc_regnum = SPARC32_PC_REGNUM; |
1393 | tdep->npc_regnum = SPARC32_NPC_REGNUM; | |
a54124c5 | 1394 | tdep->gregset = NULL; |
c558d81a | 1395 | tdep->sizeof_gregset = 0; |
a54124c5 | 1396 | tdep->fpregset = NULL; |
c558d81a | 1397 | tdep->sizeof_fpregset = 0; |
386c036b | 1398 | tdep->plt_entry_size = 0; |
c893be75 | 1399 | tdep->step_trap = sparc_step_trap; |
386c036b MK |
1400 | |
1401 | set_gdbarch_long_double_bit (gdbarch, 128); | |
8da61cc4 | 1402 | set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad); |
386c036b MK |
1403 | |
1404 | set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); | |
1405 | set_gdbarch_register_name (gdbarch, sparc32_register_name); | |
1406 | set_gdbarch_register_type (gdbarch, sparc32_register_type); | |
1407 | set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); | |
1408 | set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); | |
1409 | set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); | |
1410 | ||
1411 | /* Register numbers of various important registers. */ | |
1412 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ | |
1413 | set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ | |
1414 | set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ | |
1415 | ||
1416 | /* Call dummy code. */ | |
1417 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); | |
1418 | set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); | |
1419 | set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); | |
1420 | ||
b9d4c5ed | 1421 | set_gdbarch_return_value (gdbarch, sparc32_return_value); |
386c036b MK |
1422 | set_gdbarch_stabs_argument_has_addr |
1423 | (gdbarch, sparc32_stabs_argument_has_addr); | |
1424 | ||
1425 | set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); | |
1426 | ||
1427 | /* Stack grows downward. */ | |
1428 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
c906108c | 1429 | |
386c036b | 1430 | set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc); |
c906108c | 1431 | |
386c036b | 1432 | set_gdbarch_frame_args_skip (gdbarch, 8); |
5af923b0 | 1433 | |
386c036b | 1434 | set_gdbarch_print_insn (gdbarch, print_insn_sparc); |
c906108c | 1435 | |
386c036b MK |
1436 | set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); |
1437 | set_gdbarch_write_pc (gdbarch, sparc_write_pc); | |
c906108c | 1438 | |
386c036b | 1439 | set_gdbarch_unwind_dummy_id (gdbarch, sparc_unwind_dummy_id); |
c906108c | 1440 | |
386c036b | 1441 | set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc); |
c906108c | 1442 | |
386c036b MK |
1443 | frame_base_set_default (gdbarch, &sparc32_frame_base); |
1444 | ||
f5a9b87d DM |
1445 | /* Hook in the DWARF CFI frame unwinder. */ |
1446 | dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg); | |
1447 | /* FIXME: kettenis/20050423: Don't enable the unwinder until the | |
1448 | StackGhost issues have been resolved. */ | |
1449 | ||
b2a0b9b2 DM |
1450 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1451 | gdbarch_init_osabi (info, gdbarch); | |
1452 | ||
386c036b | 1453 | frame_unwind_append_sniffer (gdbarch, sparc32_frame_sniffer); |
c906108c | 1454 | |
a54124c5 | 1455 | /* If we have register sets, enable the generic core file support. */ |
4c72d57a | 1456 | if (tdep->gregset) |
a54124c5 MK |
1457 | set_gdbarch_regset_from_core_section (gdbarch, |
1458 | sparc_regset_from_core_section); | |
1459 | ||
386c036b MK |
1460 | return gdbarch; |
1461 | } | |
1462 | \f | |
1463 | /* Helper functions for dealing with register windows. */ | |
1464 | ||
1465 | void | |
1466 | sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) | |
c906108c | 1467 | { |
386c036b | 1468 | int offset = 0; |
e1613aba | 1469 | gdb_byte buf[8]; |
386c036b MK |
1470 | int i; |
1471 | ||
1472 | if (sp & 1) | |
1473 | { | |
1474 | /* Registers are 64-bit. */ | |
1475 | sp += BIAS; | |
c906108c | 1476 | |
386c036b MK |
1477 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1478 | { | |
1479 | if (regnum == i || regnum == -1) | |
1480 | { | |
1481 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); | |
f700a364 MK |
1482 | |
1483 | /* Handle StackGhost. */ | |
1484 | if (i == SPARC_I7_REGNUM) | |
1485 | { | |
1486 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
1487 | ULONGEST i7 = extract_unsigned_integer (buf + offset, 8); | |
1488 | ||
1489 | store_unsigned_integer (buf + offset, 8, i7 ^ wcookie); | |
1490 | } | |
1491 | ||
386c036b MK |
1492 | regcache_raw_supply (regcache, i, buf); |
1493 | } | |
1494 | } | |
1495 | } | |
1496 | else | |
c906108c | 1497 | { |
386c036b MK |
1498 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1499 | pointer. */ | |
1500 | sp &= 0xffffffffUL; | |
c906108c | 1501 | |
386c036b MK |
1502 | /* Clear out the top half of the temporary buffer, and put the |
1503 | register value in the bottom half if we're in 64-bit mode. */ | |
e6d4f032 | 1504 | if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) |
c906108c | 1505 | { |
386c036b MK |
1506 | memset (buf, 0, 4); |
1507 | offset = 4; | |
1508 | } | |
c906108c | 1509 | |
386c036b MK |
1510 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1511 | { | |
1512 | if (regnum == i || regnum == -1) | |
1513 | { | |
1514 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), | |
1515 | buf + offset, 4); | |
42cdca6c MK |
1516 | |
1517 | /* Handle StackGhost. */ | |
1518 | if (i == SPARC_I7_REGNUM) | |
1519 | { | |
1520 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
7d34766b | 1521 | ULONGEST i7 = extract_unsigned_integer (buf + offset, 4); |
42cdca6c | 1522 | |
7d34766b | 1523 | store_unsigned_integer (buf + offset, 4, i7 ^ wcookie); |
42cdca6c MK |
1524 | } |
1525 | ||
386c036b MK |
1526 | regcache_raw_supply (regcache, i, buf); |
1527 | } | |
c906108c SS |
1528 | } |
1529 | } | |
c906108c | 1530 | } |
c906108c SS |
1531 | |
1532 | void | |
386c036b MK |
1533 | sparc_collect_rwindow (const struct regcache *regcache, |
1534 | CORE_ADDR sp, int regnum) | |
c906108c | 1535 | { |
386c036b | 1536 | int offset = 0; |
e1613aba | 1537 | gdb_byte buf[8]; |
386c036b | 1538 | int i; |
5af923b0 | 1539 | |
386c036b | 1540 | if (sp & 1) |
5af923b0 | 1541 | { |
386c036b MK |
1542 | /* Registers are 64-bit. */ |
1543 | sp += BIAS; | |
c906108c | 1544 | |
386c036b MK |
1545 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1546 | { | |
1547 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1548 | { | |
1549 | regcache_raw_collect (regcache, i, buf); | |
f700a364 MK |
1550 | |
1551 | /* Handle StackGhost. */ | |
1552 | if (i == SPARC_I7_REGNUM) | |
1553 | { | |
1554 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
1555 | ULONGEST i7 = extract_unsigned_integer (buf + offset, 8); | |
1556 | ||
1557 | store_unsigned_integer (buf, 8, i7 ^ wcookie); | |
1558 | } | |
1559 | ||
386c036b MK |
1560 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); |
1561 | } | |
1562 | } | |
5af923b0 MS |
1563 | } |
1564 | else | |
1565 | { | |
386c036b MK |
1566 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1567 | pointer. */ | |
1568 | sp &= 0xffffffffUL; | |
1569 | ||
1570 | /* Only use the bottom half if we're in 64-bit mode. */ | |
e6d4f032 | 1571 | if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) |
386c036b MK |
1572 | offset = 4; |
1573 | ||
1574 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1575 | { | |
1576 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1577 | { | |
1578 | regcache_raw_collect (regcache, i, buf); | |
42cdca6c MK |
1579 | |
1580 | /* Handle StackGhost. */ | |
1581 | if (i == SPARC_I7_REGNUM) | |
1582 | { | |
1583 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
7d34766b | 1584 | ULONGEST i7 = extract_unsigned_integer (buf + offset, 4); |
42cdca6c | 1585 | |
7d34766b | 1586 | store_unsigned_integer (buf + offset, 4, i7 ^ wcookie); |
42cdca6c MK |
1587 | } |
1588 | ||
386c036b MK |
1589 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), |
1590 | buf + offset, 4); | |
1591 | } | |
1592 | } | |
5af923b0 | 1593 | } |
c906108c SS |
1594 | } |
1595 | ||
386c036b MK |
1596 | /* Helper functions for dealing with register sets. */ |
1597 | ||
c906108c | 1598 | void |
386c036b MK |
1599 | sparc32_supply_gregset (const struct sparc_gregset *gregset, |
1600 | struct regcache *regcache, | |
1601 | int regnum, const void *gregs) | |
c906108c | 1602 | { |
e1613aba | 1603 | const gdb_byte *regs = gregs; |
386c036b | 1604 | int i; |
5af923b0 | 1605 | |
386c036b MK |
1606 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1607 | regcache_raw_supply (regcache, SPARC32_PSR_REGNUM, | |
1608 | regs + gregset->r_psr_offset); | |
c906108c | 1609 | |
386c036b MK |
1610 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1611 | regcache_raw_supply (regcache, SPARC32_PC_REGNUM, | |
1612 | regs + gregset->r_pc_offset); | |
5af923b0 | 1613 | |
386c036b MK |
1614 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) |
1615 | regcache_raw_supply (regcache, SPARC32_NPC_REGNUM, | |
1616 | regs + gregset->r_npc_offset); | |
5af923b0 | 1617 | |
386c036b MK |
1618 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1619 | regcache_raw_supply (regcache, SPARC32_Y_REGNUM, | |
1620 | regs + gregset->r_y_offset); | |
5af923b0 | 1621 | |
386c036b MK |
1622 | if (regnum == SPARC_G0_REGNUM || regnum == -1) |
1623 | regcache_raw_supply (regcache, SPARC_G0_REGNUM, NULL); | |
5af923b0 | 1624 | |
386c036b | 1625 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) |
c906108c | 1626 | { |
386c036b MK |
1627 | int offset = gregset->r_g1_offset; |
1628 | ||
1629 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1630 | { | |
1631 | if (regnum == i || regnum == -1) | |
1632 | regcache_raw_supply (regcache, i, regs + offset); | |
1633 | offset += 4; | |
1634 | } | |
c906108c | 1635 | } |
386c036b MK |
1636 | |
1637 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
c906108c | 1638 | { |
386c036b MK |
1639 | /* Not all of the register set variants include Locals and |
1640 | Inputs. For those that don't, we read them off the stack. */ | |
1641 | if (gregset->r_l0_offset == -1) | |
1642 | { | |
1643 | ULONGEST sp; | |
1644 | ||
1645 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1646 | sparc_supply_rwindow (regcache, sp, regnum); | |
1647 | } | |
1648 | else | |
1649 | { | |
1650 | int offset = gregset->r_l0_offset; | |
1651 | ||
1652 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1653 | { | |
1654 | if (regnum == i || regnum == -1) | |
1655 | regcache_raw_supply (regcache, i, regs + offset); | |
1656 | offset += 4; | |
1657 | } | |
1658 | } | |
c906108c SS |
1659 | } |
1660 | } | |
1661 | ||
c5aa993b | 1662 | void |
386c036b MK |
1663 | sparc32_collect_gregset (const struct sparc_gregset *gregset, |
1664 | const struct regcache *regcache, | |
1665 | int regnum, void *gregs) | |
c906108c | 1666 | { |
e1613aba | 1667 | gdb_byte *regs = gregs; |
386c036b | 1668 | int i; |
c5aa993b | 1669 | |
386c036b MK |
1670 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1671 | regcache_raw_collect (regcache, SPARC32_PSR_REGNUM, | |
1672 | regs + gregset->r_psr_offset); | |
60054393 | 1673 | |
386c036b MK |
1674 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1675 | regcache_raw_collect (regcache, SPARC32_PC_REGNUM, | |
1676 | regs + gregset->r_pc_offset); | |
1677 | ||
1678 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) | |
1679 | regcache_raw_collect (regcache, SPARC32_NPC_REGNUM, | |
1680 | regs + gregset->r_npc_offset); | |
5af923b0 | 1681 | |
386c036b MK |
1682 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1683 | regcache_raw_collect (regcache, SPARC32_Y_REGNUM, | |
1684 | regs + gregset->r_y_offset); | |
1685 | ||
1686 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) | |
5af923b0 | 1687 | { |
386c036b MK |
1688 | int offset = gregset->r_g1_offset; |
1689 | ||
1690 | /* %g0 is always zero. */ | |
1691 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1692 | { | |
1693 | if (regnum == i || regnum == -1) | |
1694 | regcache_raw_collect (regcache, i, regs + offset); | |
1695 | offset += 4; | |
1696 | } | |
5af923b0 | 1697 | } |
386c036b MK |
1698 | |
1699 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
5af923b0 | 1700 | { |
386c036b MK |
1701 | /* Not all of the register set variants include Locals and |
1702 | Inputs. For those that don't, we read them off the stack. */ | |
1703 | if (gregset->r_l0_offset != -1) | |
1704 | { | |
1705 | int offset = gregset->r_l0_offset; | |
1706 | ||
1707 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1708 | { | |
1709 | if (regnum == i || regnum == -1) | |
1710 | regcache_raw_collect (regcache, i, regs + offset); | |
1711 | offset += 4; | |
1712 | } | |
1713 | } | |
5af923b0 | 1714 | } |
c906108c SS |
1715 | } |
1716 | ||
c906108c | 1717 | void |
386c036b MK |
1718 | sparc32_supply_fpregset (struct regcache *regcache, |
1719 | int regnum, const void *fpregs) | |
c906108c | 1720 | { |
e1613aba | 1721 | const gdb_byte *regs = fpregs; |
386c036b | 1722 | int i; |
60054393 | 1723 | |
386c036b | 1724 | for (i = 0; i < 32; i++) |
c906108c | 1725 | { |
386c036b MK |
1726 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) |
1727 | regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, regs + (i * 4)); | |
c906108c | 1728 | } |
5af923b0 | 1729 | |
386c036b MK |
1730 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
1731 | regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4); | |
c906108c SS |
1732 | } |
1733 | ||
386c036b MK |
1734 | void |
1735 | sparc32_collect_fpregset (const struct regcache *regcache, | |
1736 | int regnum, void *fpregs) | |
c906108c | 1737 | { |
e1613aba | 1738 | gdb_byte *regs = fpregs; |
386c036b | 1739 | int i; |
c906108c | 1740 | |
386c036b MK |
1741 | for (i = 0; i < 32; i++) |
1742 | { | |
1743 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) | |
1744 | regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, regs + (i * 4)); | |
1745 | } | |
c906108c | 1746 | |
386c036b MK |
1747 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
1748 | regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4); | |
c906108c | 1749 | } |
c906108c | 1750 | \f |
c906108c | 1751 | |
386c036b | 1752 | /* SunOS 4. */ |
c906108c | 1753 | |
386c036b MK |
1754 | /* From <machine/reg.h>. */ |
1755 | const struct sparc_gregset sparc32_sunos4_gregset = | |
c906108c | 1756 | { |
386c036b MK |
1757 | 0 * 4, /* %psr */ |
1758 | 1 * 4, /* %pc */ | |
1759 | 2 * 4, /* %npc */ | |
1760 | 3 * 4, /* %y */ | |
1761 | -1, /* %wim */ | |
1762 | -1, /* %tbr */ | |
1763 | 4 * 4, /* %g1 */ | |
1764 | -1 /* %l0 */ | |
1765 | }; | |
1766 | \f | |
c906108c | 1767 | |
386c036b MK |
1768 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
1769 | void _initialize_sparc_tdep (void); | |
c906108c SS |
1770 | |
1771 | void | |
386c036b | 1772 | _initialize_sparc_tdep (void) |
c906108c | 1773 | { |
386c036b | 1774 | register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init); |
2d457077 MK |
1775 | |
1776 | /* Initialize the SPARC-specific register types. */ | |
1777 | sparc_init_types(); | |
ef3cf062 | 1778 | } |