Commit | Line | Data |
---|---|---|
bd5635a1 RP |
1 | /* Machine-dependent code which would otherwise be in inflow.c and core.c, |
2 | for GDB, the GNU debugger. | |
3 | Copyright (C) 1986, 1987, 1989 Free Software Foundation, Inc. | |
4 | This code is for the sparc cpu. | |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | GDB is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 1, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GDB is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GDB; see the file COPYING. If not, write to | |
20 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
21 | ||
22 | #include <stdio.h> | |
23 | #include "defs.h" | |
24 | #include "param.h" | |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "obstack.h" | |
28 | #include "signame.h" | |
29 | #include "target.h" | |
30 | #include "ieee-float.h" | |
31 | ||
bd5635a1 | 32 | #include <sys/ptrace.h> |
bd5635a1 | 33 | |
bd5635a1 RP |
34 | #include "gdbcore.h" |
35 | ||
36 | /* From infrun.c */ | |
37 | extern int stop_after_trap; | |
38 | ||
39 | typedef enum | |
40 | { | |
41 | Error, not_branch, bicc, bicca, ba, baa, ticc, ta, | |
42 | } branch_type; | |
43 | ||
44 | /* Simulate single-step ptrace call for sun4. Code written by Gary | |
45 | Beihl (beihl@mcc.com). */ | |
46 | ||
47 | /* npc4 and next_pc describe the situation at the time that the | |
48 | step-breakpoint was set, not necessary the current value of NPC_REGNUM. */ | |
49 | static CORE_ADDR next_pc, npc4, target; | |
50 | static int brknpc4, brktrg; | |
51 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
52 | static binsn_quantum break_mem[3]; | |
53 | ||
54 | /* Non-zero if we just simulated a single-step ptrace call. This is | |
55 | needed because we cannot remove the breakpoints in the inferior | |
56 | process until after the `wait' in `wait_for_inferior'. Used for | |
57 | sun4. */ | |
58 | ||
59 | int one_stepped; | |
60 | ||
d11c44f1 JG |
61 | /* single_step() is called just before we want to resume the inferior, |
62 | if we want to single-step it but there is no hardware or kernel single-step | |
63 | support (as on all SPARCs). We find all the possible targets of the | |
64 | coming instruction and breakpoint them. | |
65 | ||
66 | single_step is also called just after the inferior stops. If we had | |
67 | set up a simulated single-step, we undo our damage. */ | |
68 | ||
bd5635a1 | 69 | void |
d11c44f1 | 70 | single_step () |
bd5635a1 RP |
71 | { |
72 | branch_type br, isannulled(); | |
73 | CORE_ADDR pc; | |
74 | long pc_instruction; | |
75 | ||
76 | if (!one_stepped) | |
77 | { | |
78 | /* Always set breakpoint for NPC. */ | |
79 | next_pc = read_register (NPC_REGNUM); | |
80 | npc4 = next_pc + 4; /* branch not taken */ | |
81 | ||
82 | target_insert_breakpoint (next_pc, break_mem[0]); | |
83 | /* printf ("set break at %x\n",next_pc); */ | |
84 | ||
85 | pc = read_register (PC_REGNUM); | |
86 | pc_instruction = read_memory_integer (pc, sizeof(pc_instruction)); | |
87 | br = isannulled (pc_instruction, pc, &target); | |
88 | brknpc4 = brktrg = 0; | |
89 | ||
90 | if (br == bicca) | |
91 | { | |
92 | /* Conditional annulled branch will either end up at | |
93 | npc (if taken) or at npc+4 (if not taken). | |
94 | Trap npc+4. */ | |
95 | brknpc4 = 1; | |
96 | target_insert_breakpoint (npc4, break_mem[1]); | |
97 | } | |
98 | else if (br == baa && target != next_pc) | |
99 | { | |
100 | /* Unconditional annulled branch will always end up at | |
101 | the target. */ | |
102 | brktrg = 1; | |
103 | target_insert_breakpoint (target, break_mem[2]); | |
104 | } | |
105 | ||
d11c44f1 | 106 | /* We are ready to let it go */ |
bd5635a1 RP |
107 | one_stepped = 1; |
108 | return; | |
109 | } | |
110 | else | |
111 | { | |
112 | /* Remove breakpoints */ | |
113 | target_remove_breakpoint (next_pc, break_mem[0]); | |
114 | ||
115 | if (brknpc4) | |
116 | target_remove_breakpoint (npc4, break_mem[1]); | |
117 | ||
118 | if (brktrg) | |
119 | target_remove_breakpoint (target, break_mem[2]); | |
120 | ||
121 | one_stepped = 0; | |
122 | } | |
123 | } | |
124 | \f | |
d11c44f1 JG |
125 | CORE_ADDR |
126 | sparc_frame_chain (thisframe) | |
127 | FRAME thisframe; | |
128 | { | |
129 | CORE_ADDR retval; | |
130 | read_memory ((CORE_ADDR)&(((struct rwindow *)(thisframe->frame))->rw_in[6]), | |
131 | &retval, | |
132 | sizeof (CORE_ADDR)); | |
133 | return retval; | |
134 | } | |
135 | ||
136 | CORE_ADDR | |
137 | sparc_extract_struct_value_address (regbuf) | |
138 | char regbuf[REGISTER_BYTES]; | |
139 | { | |
140 | CORE_ADDR retval; | |
141 | read_memory (((int *)(regbuf))[SP_REGNUM]+(16*4), | |
142 | &retval, | |
143 | sizeof (CORE_ADDR)); | |
144 | return retval; | |
145 | } | |
146 | ||
bd5635a1 RP |
147 | /* |
148 | * Find the pc saved in frame FRAME. | |
149 | */ | |
150 | CORE_ADDR | |
151 | frame_saved_pc (frame) | |
152 | FRAME frame; | |
153 | { | |
154 | CORE_ADDR prev_pc; | |
155 | ||
156 | /* If it's at the bottom, the return value's stored in i7/rp */ | |
157 | if (get_current_frame () == frame) | |
d11c44f1 JG |
158 | read_memory ((CORE_ADDR)&((struct rwindow *) |
159 | (read_register (SP_REGNUM)))->rw_in[7], | |
160 | &prev_pc, sizeof (CORE_ADDR)); | |
bd5635a1 | 161 | else |
d11c44f1 JG |
162 | /* Wouldn't this always work? */ |
163 | read_memory ((CORE_ADDR)&((struct rwindow *)(frame->bottom))->rw_in[7], | |
164 | &prev_pc, | |
165 | sizeof (CORE_ADDR)); | |
bd5635a1 RP |
166 | |
167 | return PC_ADJUST (prev_pc); | |
168 | } | |
169 | ||
170 | /* | |
171 | * Since an individual frame in the frame cache is defined by two | |
172 | * arguments (a frame pointer and a stack pointer), we need two | |
173 | * arguments to get info for an arbitrary stack frame. This routine | |
174 | * takes two arguments and makes the cached frames look as if these | |
175 | * two arguments defined a frame on the cache. This allows the rest | |
176 | * of info frame to extract the important arguments without | |
177 | * difficulty. | |
178 | */ | |
179 | FRAME | |
180 | setup_arbitrary_frame (frame, stack) | |
181 | FRAME_ADDR frame, stack; | |
182 | { | |
183 | FRAME fid = create_new_frame (frame, 0); | |
184 | ||
185 | if (!fid) | |
186 | fatal ("internal: create_new_frame returned invalid frame id"); | |
187 | ||
188 | fid->bottom = stack; | |
189 | ||
190 | return fid; | |
191 | } | |
192 | ||
193 | /* This code was written by Gary Beihl (beihl@mcc.com). | |
194 | It was modified by Michael Tiemann (tiemann@corto.inria.fr). */ | |
195 | ||
196 | /* | |
197 | * This routine appears to be passed a size by which to increase the | |
198 | * stack. It then executes a save instruction in the inferior to | |
199 | * increase the stack by this amount. Only the register window system | |
200 | * should be affected by this; the program counter & etc. will not be. | |
201 | * | |
202 | * This instructions used for this purpose are: | |
203 | * | |
204 | * sethi %hi(0x0),g1 * | |
205 | * add g1,0x1ee0,g1 * | |
206 | * save sp,g1,sp | |
207 | * sethi %hi(0x0),g1 * | |
208 | * add g1,0x1ee0,g1 * | |
209 | * t g0,0x1,o0 | |
210 | * sethi %hi(0x0),g0 (nop) | |
211 | * | |
212 | * I presume that these set g1 to be the negative of the size, do a | |
213 | * save (putting the stack pointer at sp - size) and restore the | |
214 | * original contents of g1. A * indicates that the actual value of | |
215 | * the instruction is modified below. | |
216 | */ | |
217 | static int save_insn_opcodes[] = { | |
218 | 0x03000000, 0x82007ee0, 0x9de38001, 0x03000000, | |
219 | 0x82007ee0, 0x91d02001, 0x01000000 }; | |
220 | ||
221 | /* Neither do_save_insn or do_restore_insn save stack configuration | |
222 | (current_frame, etc), | |
223 | since the stack is in an indeterminate state through the call to | |
224 | each of them. That responsibility of the routine which calls them. */ | |
225 | ||
226 | static void | |
227 | do_save_insn (size) | |
228 | int size; | |
229 | { | |
230 | int g1 = read_register (G1_REGNUM); | |
231 | CORE_ADDR sp = read_register (SP_REGNUM); | |
232 | CORE_ADDR pc = read_register (PC_REGNUM); | |
233 | CORE_ADDR npc = read_register (NPC_REGNUM); | |
234 | CORE_ADDR fake_pc = sp - sizeof (save_insn_opcodes); | |
235 | struct inferior_status inf_status; | |
236 | ||
237 | save_inferior_status (&inf_status, 0); /* Don't restore stack info */ | |
238 | /* | |
239 | * See above. | |
240 | */ | |
241 | save_insn_opcodes[0] = 0x03000000 | ((-size >> 10) & 0x3fffff); | |
242 | save_insn_opcodes[1] = 0x82006000 | (-size & 0x3ff); | |
243 | save_insn_opcodes[3] = 0x03000000 | ((g1 >> 10) & 0x3fffff); | |
244 | save_insn_opcodes[4] = 0x82006000 | (g1 & 0x3ff); | |
245 | write_memory (fake_pc, (char *)save_insn_opcodes, sizeof (save_insn_opcodes)); | |
246 | ||
247 | clear_proceed_status (); | |
248 | stop_after_trap = 1; | |
249 | proceed (fake_pc, 0, 0); | |
250 | ||
251 | write_register (PC_REGNUM, pc); | |
252 | write_register (NPC_REGNUM, npc); | |
253 | restore_inferior_status (&inf_status); | |
254 | } | |
255 | ||
256 | /* | |
257 | * This routine takes a program counter value. It restores the | |
258 | * register window system to the frame above the current one. | |
259 | * THIS ROUTINE CLOBBERS PC AND NPC IN THE TARGET! | |
260 | */ | |
261 | ||
262 | /* The following insns translate to: | |
263 | ||
264 | restore %g0,%g0,%g0 | |
265 | t %g0,1 | |
266 | sethi %hi(0),%g0 */ | |
267 | ||
268 | static int restore_insn_opcodes[] = { 0x81e80000, 0x91d02001, 0x01000000 }; | |
269 | ||
270 | static void | |
271 | do_restore_insn () | |
272 | { | |
273 | CORE_ADDR sp = read_register (SP_REGNUM); | |
274 | CORE_ADDR fake_pc = sp - sizeof (restore_insn_opcodes); | |
275 | struct inferior_status inf_status; | |
276 | ||
277 | save_inferior_status (&inf_status, 0); /* Don't restore stack info */ | |
278 | ||
279 | write_memory (fake_pc, (char *)restore_insn_opcodes, | |
280 | sizeof (restore_insn_opcodes)); | |
281 | ||
282 | clear_proceed_status (); | |
283 | stop_after_trap = 1; | |
284 | proceed (fake_pc, 0, 0); | |
285 | ||
286 | restore_inferior_status (&inf_status); | |
287 | } | |
288 | ||
289 | /* This routine should be more specific in it's actions; making sure | |
192cbba9 | 290 | that it uses the same register in the initial prologue section. */ |
bd5635a1 | 291 | CORE_ADDR |
192cbba9 JK |
292 | skip_prologue (start_pc) |
293 | CORE_ADDR start_pc; | |
bd5635a1 RP |
294 | { |
295 | union | |
296 | { | |
297 | unsigned long int code; | |
298 | struct | |
299 | { | |
300 | unsigned int op:2; | |
301 | unsigned int rd:5; | |
302 | unsigned int op2:3; | |
303 | unsigned int imm22:22; | |
304 | } sethi; | |
305 | struct | |
306 | { | |
307 | unsigned int op:2; | |
308 | unsigned int rd:5; | |
309 | unsigned int op3:6; | |
310 | unsigned int rs1:5; | |
311 | unsigned int i:1; | |
312 | unsigned int simm13:13; | |
313 | } add; | |
314 | int i; | |
315 | } x; | |
316 | int dest = -1; | |
192cbba9 JK |
317 | CORE_ADDR pc = start_pc; |
318 | /* Have we found a save instruction? */ | |
319 | int found_save = 0; | |
bd5635a1 RP |
320 | |
321 | x.i = read_memory_integer (pc, 4); | |
322 | ||
323 | /* Recognize the `sethi' insn and record its destination. */ | |
324 | if (x.sethi.op == 0 && x.sethi.op2 == 4) | |
325 | { | |
326 | dest = x.sethi.rd; | |
327 | pc += 4; | |
328 | x.i = read_memory_integer (pc, 4); | |
329 | } | |
330 | ||
331 | /* Recognize an add immediate value to register to either %g1 or | |
332 | the destination register recorded above. Actually, this might | |
192cbba9 JK |
333 | well recognize several different arithmetic operations. |
334 | It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1" | |
335 | followed by "save %sp, %g1, %sp" is a valid prologue (Not that | |
336 | I imagine any compiler really does that, however). */ | |
bd5635a1 RP |
337 | if (x.add.op == 2 && x.add.i && (x.add.rd == 1 || x.add.rd == dest)) |
338 | { | |
339 | pc += 4; | |
340 | x.i = read_memory_integer (pc, 4); | |
341 | } | |
342 | ||
343 | /* This recognizes any SAVE insn. But why do the XOR and then | |
344 | the compare? That's identical to comparing against 60 (as long | |
345 | as there isn't any sign extension). */ | |
346 | if (x.add.op == 2 && (x.add.op3 ^ 32) == 28) | |
347 | { | |
192cbba9 | 348 | found_save = 1; |
bd5635a1 RP |
349 | pc += 4; |
350 | x.i = read_memory_integer (pc, 4); | |
351 | } | |
352 | ||
353 | /* Now we need to recognize stores into the frame from the input | |
354 | registers. This recognizes all non alternate stores of input | |
355 | register, into a location offset from the frame pointer. */ | |
356 | while (x.add.op == 3 | |
357 | && (x.add.op3 & 0x3c) == 4 /* Store, non-alternate. */ | |
358 | && (x.add.rd & 0x18) == 0x18 /* Input register. */ | |
359 | && x.add.i /* Immediate mode. */ | |
360 | && x.add.rs1 == 30 /* Off of frame pointer. */ | |
361 | /* Into reserved stack space. */ | |
362 | && x.add.simm13 >= 0x44 | |
363 | && x.add.simm13 < 0x5b) | |
364 | { | |
365 | pc += 4; | |
366 | x.i = read_memory_integer (pc, 4); | |
367 | } | |
192cbba9 JK |
368 | if (found_save) |
369 | return pc; | |
370 | else | |
371 | /* Without a save instruction, it's not a prologue. */ | |
372 | return start_pc; | |
bd5635a1 RP |
373 | } |
374 | ||
375 | /* Check instruction at ADDR to see if it is an annulled branch. | |
376 | All other instructions will go to NPC or will trap. | |
377 | Set *TARGET if we find a canidate branch; set to zero if not. */ | |
378 | ||
379 | branch_type | |
380 | isannulled (instruction, addr, target) | |
381 | long instruction; | |
382 | CORE_ADDR addr, *target; | |
383 | { | |
384 | branch_type val = not_branch; | |
385 | long int offset; /* Must be signed for sign-extend. */ | |
386 | union | |
387 | { | |
388 | unsigned long int code; | |
389 | struct | |
390 | { | |
391 | unsigned int op:2; | |
392 | unsigned int a:1; | |
393 | unsigned int cond:4; | |
394 | unsigned int op2:3; | |
395 | unsigned int disp22:22; | |
396 | } b; | |
397 | } insn; | |
398 | ||
399 | *target = 0; | |
400 | insn.code = instruction; | |
401 | ||
402 | if (insn.b.op == 0 | |
403 | && (insn.b.op2 == 2 || insn.b.op2 == 6 || insn.b.op2 == 7)) | |
404 | { | |
405 | if (insn.b.cond == 8) | |
406 | val = insn.b.a ? baa : ba; | |
407 | else | |
408 | val = insn.b.a ? bicca : bicc; | |
409 | offset = 4 * ((int) (insn.b.disp22 << 10) >> 10); | |
410 | *target = addr + offset; | |
411 | } | |
412 | ||
413 | return val; | |
414 | } | |
415 | ||
416 | /* sparc_frame_find_saved_regs () | |
417 | ||
418 | Stores, into a struct frame_saved_regs, | |
419 | the addresses of the saved registers of frame described by FRAME_INFO. | |
420 | This includes special registers such as pc and fp saved in special | |
421 | ways in the stack frame. sp is even more special: | |
422 | the address we return for it IS the sp for the next frame. | |
423 | ||
424 | Note that on register window machines, we are currently making the | |
425 | assumption that window registers are being saved somewhere in the | |
426 | frame in which they are being used. If they are stored in an | |
427 | inferior frame, find_saved_register will break. | |
428 | ||
429 | On the Sun 4, the only time all registers are saved is when | |
430 | a dummy frame is involved. Otherwise, the only saved registers | |
431 | are the LOCAL and IN registers which are saved as a result | |
432 | of the "save/restore" opcodes. This condition is determined | |
433 | by address rather than by value. | |
434 | ||
435 | The "pc" is not stored in a frame on the SPARC. (What is stored | |
436 | is a return address minus 8.) sparc_pop_frame knows how to | |
437 | deal with that. Other routines might or might not. | |
438 | ||
439 | See tm-sparc.h (PUSH_FRAME and friends) for CRITICAL information | |
440 | about how this works. */ | |
441 | ||
442 | void | |
443 | sparc_frame_find_saved_regs (fi, saved_regs_addr) | |
444 | struct frame_info *fi; | |
445 | struct frame_saved_regs *saved_regs_addr; | |
446 | { | |
447 | register int regnum; | |
448 | FRAME_ADDR frame = read_register (FP_REGNUM); | |
449 | FRAME fid = FRAME_INFO_ID (fi); | |
450 | ||
451 | if (!fid) | |
452 | fatal ("Bad frame info struct in FRAME_FIND_SAVED_REGS"); | |
453 | ||
454 | bzero (saved_regs_addr, sizeof (*saved_regs_addr)); | |
455 | ||
456 | /* Old test. | |
457 | if (fi->pc >= frame - CALL_DUMMY_LENGTH - 0x140 | |
458 | && fi->pc <= frame) */ | |
459 | ||
460 | if (fi->pc >= (fi->bottom ? fi->bottom : | |
461 | read_register (SP_REGNUM)) | |
462 | && fi->pc <= FRAME_FP(fi)) | |
463 | { | |
464 | /* Dummy frame. All but the window regs are in there somewhere. */ | |
465 | for (regnum = G1_REGNUM; regnum < G1_REGNUM+7; regnum++) | |
466 | saved_regs_addr->regs[regnum] = | |
467 | frame + (regnum - G0_REGNUM) * 4 - 0xa0; | |
468 | for (regnum = I0_REGNUM; regnum < I0_REGNUM+8; regnum++) | |
469 | saved_regs_addr->regs[regnum] = | |
470 | frame + (regnum - I0_REGNUM) * 4 - 0xc0; | |
471 | for (regnum = FP0_REGNUM; regnum < FP0_REGNUM + 32; regnum++) | |
472 | saved_regs_addr->regs[regnum] = | |
473 | frame + (regnum - FP0_REGNUM) * 4 - 0x80; | |
474 | for (regnum = Y_REGNUM; regnum < NUM_REGS; regnum++) | |
475 | saved_regs_addr->regs[regnum] = | |
476 | frame + (regnum - Y_REGNUM) * 4 - 0xe0; | |
477 | frame = fi->bottom ? | |
478 | fi->bottom : read_register (SP_REGNUM); | |
479 | } | |
480 | else | |
481 | { | |
482 | /* Normal frame. Just Local and In registers */ | |
483 | frame = fi->bottom ? | |
484 | fi->bottom : read_register (SP_REGNUM); | |
485 | for (regnum = L0_REGNUM; regnum < L0_REGNUM+16; regnum++) | |
486 | saved_regs_addr->regs[regnum] = frame + (regnum-L0_REGNUM) * 4; | |
487 | } | |
488 | if (fi->next) | |
489 | { | |
490 | /* Pull off either the next frame pointer or the stack pointer */ | |
491 | FRAME_ADDR next_next_frame = | |
492 | (fi->next->bottom ? | |
493 | fi->next->bottom : | |
494 | read_register (SP_REGNUM)); | |
495 | for (regnum = O0_REGNUM; regnum < O0_REGNUM+8; regnum++) | |
496 | saved_regs_addr->regs[regnum] = next_next_frame + regnum * 4; | |
497 | } | |
498 | /* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */ | |
499 | saved_regs_addr->regs[SP_REGNUM] = FRAME_FP (fi); | |
500 | } | |
501 | ||
502 | /* Push an empty stack frame, and record in it the current PC, regs, etc. | |
503 | ||
504 | Note that the write's are of registers in the context of the newly | |
505 | pushed frame. Thus the the fp*'s, the g*'s, the i*'s, and | |
506 | the randoms, of the new frame, are being saved. The locals and outs | |
507 | are new; they don't need to be saved. The i's and l's of | |
508 | the last frame were saved by the do_save_insn in the register | |
509 | file (now on the stack, since a context switch happended imm after). | |
510 | ||
511 | The return pointer register %i7 does not have | |
512 | the pc saved into it (return from this frame will be accomplished | |
513 | by a POP_FRAME). In fact, we must leave it unclobbered, since we | |
514 | must preserve it in the calling routine except across call instructions. */ | |
515 | ||
516 | /* Definitely see tm-sparc.h for more doc of the frame format here. */ | |
517 | ||
518 | void | |
519 | sparc_push_dummy_frame () | |
520 | { | |
521 | CORE_ADDR fp; | |
522 | char register_temp[REGISTER_BYTES]; | |
523 | ||
524 | do_save_insn (0x140); /* FIXME where does this value come from? */ | |
525 | fp = read_register (FP_REGNUM); | |
526 | ||
527 | read_register_bytes (REGISTER_BYTE (FP0_REGNUM), register_temp, 32 * 4); | |
528 | write_memory (fp - 0x80, register_temp, 32 * 4); | |
529 | ||
530 | read_register_bytes (REGISTER_BYTE (G0_REGNUM), register_temp, 8 * 4); | |
531 | write_memory (fp - 0xa0, register_temp, 8 * 4); | |
532 | ||
533 | read_register_bytes (REGISTER_BYTE (I0_REGNUM), register_temp, 8 * 4); | |
534 | write_memory (fp - 0xc0, register_temp, 8 * 4); | |
535 | ||
536 | /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */ | |
537 | read_register_bytes (REGISTER_BYTE (Y_REGNUM), register_temp, 8 * 4); | |
538 | write_memory (fp - 0xe0, register_temp, 8 * 4); | |
539 | } | |
540 | ||
541 | /* Discard from the stack the innermost frame, restoring all saved registers. | |
542 | ||
543 | Note that the values stored in fsr by get_frame_saved_regs are *in | |
544 | the context of the called frame*. What this means is that the i | |
545 | regs of fsr must be restored into the o regs of the (calling) frame that | |
546 | we pop into. We don't care about the output regs of the calling frame, | |
547 | since unless it's a dummy frame, it won't have any output regs in it. | |
548 | ||
549 | We never have to bother with %l (local) regs, since the called routine's | |
550 | locals get tossed, and the calling routine's locals are already saved | |
551 | on its stack. */ | |
552 | ||
553 | /* Definitely see tm-sparc.h for more doc of the frame format here. */ | |
554 | ||
555 | void | |
556 | sparc_pop_frame () | |
557 | { | |
558 | register FRAME frame = get_current_frame (); | |
559 | register CORE_ADDR pc; | |
560 | struct frame_saved_regs fsr; | |
561 | struct frame_info *fi; | |
562 | char raw_buffer[REGISTER_BYTES]; | |
563 | ||
564 | fi = get_frame_info (frame); | |
565 | get_frame_saved_regs (fi, &fsr); | |
566 | do_restore_insn (); | |
567 | if (fsr.regs[FP0_REGNUM]) | |
568 | { | |
569 | read_memory (fsr.regs[FP0_REGNUM], raw_buffer, 32 * 4); | |
570 | write_register_bytes (REGISTER_BYTE (FP0_REGNUM), raw_buffer, 32 * 4); | |
571 | } | |
572 | if (fsr.regs[G1_REGNUM]) | |
573 | { | |
574 | read_memory (fsr.regs[G1_REGNUM], raw_buffer, 7 * 4); | |
575 | write_register_bytes (REGISTER_BYTE (G1_REGNUM), raw_buffer, 7 * 4); | |
576 | } | |
577 | if (fsr.regs[I0_REGNUM]) | |
578 | { | |
579 | read_memory (fsr.regs[I0_REGNUM], raw_buffer, 8 * 4); | |
580 | write_register_bytes (REGISTER_BYTE (O0_REGNUM), raw_buffer, 8 * 4); | |
581 | } | |
582 | if (fsr.regs[PS_REGNUM]) | |
583 | write_register (PS_REGNUM, read_memory_integer (fsr.regs[PS_REGNUM], 4)); | |
584 | if (fsr.regs[Y_REGNUM]) | |
585 | write_register (Y_REGNUM, read_memory_integer (fsr.regs[Y_REGNUM], 4)); | |
586 | if (fsr.regs[PC_REGNUM]) | |
587 | { | |
588 | /* Explicitly specified PC (and maybe NPC) -- just restore them. */ | |
589 | write_register (PC_REGNUM, read_memory_integer (fsr.regs[PC_REGNUM], 4)); | |
590 | if (fsr.regs[NPC_REGNUM]) | |
591 | write_register (NPC_REGNUM, | |
592 | read_memory_integer (fsr.regs[NPC_REGNUM], 4)); | |
593 | } | |
594 | else if (fsr.regs[I7_REGNUM]) | |
595 | { | |
596 | /* Return address in %i7 -- adjust it, then restore PC and NPC from it */ | |
597 | pc = PC_ADJUST (read_memory_integer (fsr.regs[I7_REGNUM], 4)); | |
598 | write_register (PC_REGNUM, pc); | |
599 | write_register (NPC_REGNUM, pc + 4); | |
600 | } | |
601 | flush_cached_frames (); | |
602 | set_current_frame ( create_new_frame (read_register (FP_REGNUM), | |
603 | read_pc ())); | |
604 | } | |
605 | ||
606 | /* Structure of SPARC extended floating point numbers. | |
607 | This information is not currently used by GDB, since no current SPARC | |
608 | implementations support extended float. */ | |
609 | ||
610 | const struct ext_format ext_format_sparc[] = { | |
611 | /* tot sbyte smask expbyte manbyte */ | |
612 | { 16, 0, 0x80, 0,1, 4,8 }, /* sparc */ | |
613 | }; |