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b955f680 KH |
1 | /* Target-dependent code for the Fujitsu SPARCLITE for GDB, the GNU debugger. |
2 | Copyright 1994 Free Software Foundation, Inc. | |
3 | ||
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
18 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
19 | ||
20 | #include "defs.h" | |
21 | #include "gdbcore.h" | |
22 | #include "breakpoint.h" | |
23 | ||
24 | #define DDA2_SUP_ASI 0xb000000 | |
25 | #define DDA1_SUP_ASI 0xb0000 | |
26 | ||
27 | #define DDA2_ASI_MASK 0xff000000 | |
28 | #define DDA1_ASI_MASK 0xff0000 | |
29 | #define DIA2_SUP_MODE 0x8000 | |
30 | #define DIA1_SUP_MODE 0x4000 | |
31 | #define DDA2_ENABLE 0x100 | |
32 | #define DDA1_ENABLE 0x80 | |
33 | #define DIA2_ENABLE 0x40 | |
34 | #define DIA1_ENABLE 0x20 | |
35 | #define DSINGLE_STEP 0x10 | |
36 | #define DDV_TYPE_MASK 0xc | |
37 | #define DDV_TYPE_LOAD 0x0 | |
38 | #define DDV_TYPE_STORE 0x4 | |
39 | #define DDV_TYPE_ACCESS 0x8 | |
40 | #define DDV_TYPE_ALWAYS 0xc | |
41 | #define DDV_COND 0x2 | |
42 | #define DDV_MASK 0x1 | |
43 | ||
44 | int | |
45 | sparclite_insert_watchpoint(addr, len, type) | |
46 | CORE_ADDR addr; | |
47 | int len; | |
48 | int type; | |
49 | { | |
50 | CORE_ADDR dcr; | |
51 | ||
52 | dcr = read_register (DCR_REGNUM); | |
53 | ||
54 | if (!(dcr & DDA1_ENABLE)) | |
55 | { | |
56 | write_register (DDA1_REGNUM, addr); | |
57 | dcr &= ~(DDA1_ASI_MASK | DDV_TYPE_MASK); | |
58 | dcr |= (DDA1_SUP_ASI | DDA1_ENABLE); | |
59 | if (type == 1) | |
60 | { | |
61 | write_register (DDV1_REGNUM, 0); | |
62 | write_register (DDV2_REGNUM, 0xffffffff); | |
63 | dcr |= (DDV_TYPE_LOAD & (~DDV_COND & ~DDV_MASK)); | |
64 | } | |
65 | else if (type == 0) | |
66 | { | |
67 | write_register (DDV1_REGNUM, 0); | |
68 | write_register (DDV2_REGNUM, 0xffffffff); | |
69 | dcr |= (DDV_TYPE_STORE & (~DDV_COND & ~DDV_MASK)); | |
70 | } | |
71 | else | |
72 | { | |
73 | write_register (DDV1_REGNUM, 0); | |
74 | write_register (DDV2_REGNUM, 0xffffffff); | |
75 | dcr |= (DDV_TYPE_ACCESS); | |
76 | } | |
77 | write_register (DCR_REGNUM, dcr); | |
78 | } | |
79 | else if (!(dcr & DDA2_ENABLE)) | |
80 | { | |
81 | write_register (DDA2_REGNUM, addr); | |
82 | dcr &= ~(DDA2_ASI_MASK & DDV_TYPE_MASK); | |
83 | dcr |= (DDA2_SUP_ASI | DDA2_ENABLE); | |
84 | if (type == 1) | |
85 | { | |
86 | write_register (DDV1_REGNUM, 0); | |
87 | write_register (DDV2_REGNUM, 0xffffffff); | |
88 | dcr |= (DDV_TYPE_LOAD & ~DDV_COND & ~DDV_MASK); | |
89 | } | |
90 | else if (type == 0) | |
91 | { | |
92 | write_register (DDV1_REGNUM, 0); | |
93 | write_register (DDV2_REGNUM, 0xffffffff); | |
94 | dcr |= (DDV_TYPE_STORE & ~DDV_COND & ~DDV_MASK); | |
95 | } | |
96 | else | |
97 | { | |
98 | write_register (DDV1_REGNUM, 0); | |
99 | write_register (DDV2_REGNUM, 0xffffffff); | |
100 | dcr |= (DDV_TYPE_ACCESS); | |
101 | } | |
102 | write_register (DCR_REGNUM, dcr); | |
103 | } | |
104 | else | |
105 | return -1; | |
106 | ||
107 | return 0; | |
108 | } | |
109 | ||
110 | int | |
111 | sparclite_remove_watchpoint(addr, len, type) | |
112 | CORE_ADDR addr; | |
113 | int len; | |
114 | int type; | |
115 | { | |
116 | CORE_ADDR dcr, dda1, dda2; | |
117 | ||
118 | dcr = read_register (DCR_REGNUM); | |
119 | dda1 = read_register (DDA1_REGNUM); | |
120 | dda2 = read_register (DDA2_REGNUM); | |
121 | ||
122 | if ((dcr & DDA1_ENABLE) && addr == dda1) { | |
123 | write_register (DCR_REGNUM, (dcr & ~DDA1_ENABLE)); | |
124 | } | |
125 | else if ((dcr & DDA2_ENABLE) && addr == dda2) { | |
126 | write_register (DCR_REGNUM, (dcr & ~DDA2_ENABLE)); | |
127 | } | |
128 | else | |
129 | return -1; | |
130 | ||
131 | return 0; | |
132 | } | |
133 | ||
134 | int | |
135 | sparclite_insert_hw_breakpoint(addr, len) | |
136 | CORE_ADDR addr; | |
137 | int len; | |
138 | { | |
139 | CORE_ADDR dcr; | |
140 | ||
141 | dcr = read_register (DCR_REGNUM); | |
142 | ||
143 | if (!(dcr & DIA1_ENABLE)) { | |
144 | write_register (DIA1_REGNUM, addr); | |
145 | write_register (DCR_REGNUM, (dcr | DIA1_ENABLE | DIA1_SUP_MODE)); | |
146 | } | |
147 | else if (!(dcr & DIA2_ENABLE)) { | |
148 | write_register (DIA2_REGNUM, addr); | |
149 | write_register (DCR_REGNUM, (dcr | DIA2_ENABLE | DIA2_SUP_MODE)); | |
150 | } | |
151 | else | |
152 | return -1; | |
153 | ||
154 | return 0; | |
155 | } | |
156 | ||
157 | int | |
158 | sparclite_remove_hw_breakpoint(addr, shadow) | |
159 | CORE_ADDR addr; | |
160 | int shadow; | |
161 | { | |
162 | CORE_ADDR dcr, dia1, dia2; | |
163 | ||
164 | dcr = read_register (DCR_REGNUM); | |
165 | dia1 = read_register (DIA1_REGNUM); | |
166 | dia2 = read_register (DIA2_REGNUM); | |
167 | ||
168 | if ((dcr & DIA1_ENABLE) && addr == dia1) { | |
169 | write_register (DCR_REGNUM, (dcr & ~DIA1_ENABLE)); | |
170 | } | |
171 | else if ((dcr & DIA2_ENABLE) && addr == dia2) { | |
172 | write_register (DCR_REGNUM, (dcr & ~DIA2_ENABLE)); | |
173 | } | |
174 | else | |
175 | return -1; | |
176 | ||
177 | return 0; | |
178 | } | |
179 | ||
180 | int | |
181 | sparclite_check_watch_resources(type, cnt, ot) | |
182 | int type; | |
183 | int cnt; | |
184 | int ot; | |
185 | { | |
186 | if (type == bp_hardware_breakpoint) { | |
187 | if (TARGET_HW_BREAK_LIMIT == 0) return 0; | |
188 | else if (cnt <= TARGET_HW_BREAK_LIMIT) return 1; | |
189 | } | |
190 | else { | |
191 | if (TARGET_HW_WATCH_LIMIT == 0) return 0; | |
192 | else if (ot) return -1; | |
193 | else if (cnt <= TARGET_HW_WATCH_LIMIT) return 1; | |
194 | } | |
195 | return -1; | |
196 | } | |
197 | ||
198 | CORE_ADDR | |
199 | sparclite_stopped_data_address() | |
200 | { | |
201 | CORE_ADDR dsr, dda1, dda2; | |
202 | ||
203 | dsr = read_register (DSR_REGNUM); | |
204 | dda1 = read_register (DDA1_REGNUM); | |
205 | dda2 = read_register (DDA2_REGNUM); | |
206 | ||
207 | if (dsr & 0x10) return dda1; | |
208 | else if (dsr & 0x20) return dda2; | |
209 | else return 0; | |
210 | } |