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771b4502 UW |
1 | /* SPU target-dependent code for GDB, the GNU debugger. |
2 | Copyright (C) 2006 Free Software Foundation, Inc. | |
3 | ||
4 | Contributed by Ulrich Weigand <uweigand@de.ibm.com>. | |
5 | Based on a port by Sid Manning <sid@us.ibm.com>. | |
6 | ||
7 | This file is part of GDB. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 51 Franklin Street, Fifth Floor, | |
22 | Boston, MA 02110-1301, USA. */ | |
23 | ||
24 | #include "defs.h" | |
25 | #include "arch-utils.h" | |
26 | #include "gdbtypes.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
29 | #include "gdb_string.h" | |
30 | #include "gdb_assert.h" | |
31 | #include "frame.h" | |
32 | #include "frame-unwind.h" | |
33 | #include "frame-base.h" | |
34 | #include "trad-frame.h" | |
35 | #include "symtab.h" | |
36 | #include "symfile.h" | |
37 | #include "value.h" | |
38 | #include "inferior.h" | |
39 | #include "dis-asm.h" | |
40 | #include "objfiles.h" | |
41 | #include "language.h" | |
42 | #include "regcache.h" | |
43 | #include "reggroups.h" | |
44 | #include "floatformat.h" | |
45 | ||
46 | #include "spu-tdep.h" | |
47 | ||
f2d43c2c UW |
48 | /* SPU-specific vector type. */ |
49 | struct type *spu_builtin_type_vec128; | |
771b4502 UW |
50 | |
51 | /* Registers. */ | |
52 | ||
53 | static const char * | |
54 | spu_register_name (int reg_nr) | |
55 | { | |
56 | static char *register_names[] = | |
57 | { | |
58 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
59 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
60 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
61 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
62 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", | |
63 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", | |
64 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", | |
65 | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", | |
66 | "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71", | |
67 | "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79", | |
68 | "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87", | |
69 | "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95", | |
70 | "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103", | |
71 | "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111", | |
72 | "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119", | |
73 | "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127", | |
74 | "id", "pc", "sp" | |
75 | }; | |
76 | ||
77 | if (reg_nr < 0) | |
78 | return NULL; | |
79 | if (reg_nr >= sizeof register_names / sizeof *register_names) | |
80 | return NULL; | |
81 | ||
82 | return register_names[reg_nr]; | |
83 | } | |
84 | ||
85 | static struct type * | |
86 | spu_register_type (struct gdbarch *gdbarch, int reg_nr) | |
87 | { | |
88 | if (reg_nr < SPU_NUM_GPRS) | |
f2d43c2c | 89 | return spu_builtin_type_vec128; |
771b4502 UW |
90 | |
91 | switch (reg_nr) | |
92 | { | |
93 | case SPU_ID_REGNUM: | |
94 | return builtin_type_uint32; | |
95 | ||
96 | case SPU_PC_REGNUM: | |
97 | return builtin_type_void_func_ptr; | |
98 | ||
99 | case SPU_SP_REGNUM: | |
100 | return builtin_type_void_data_ptr; | |
101 | ||
102 | default: | |
103 | internal_error (__FILE__, __LINE__, "invalid regnum"); | |
104 | } | |
105 | } | |
106 | ||
107 | /* Pseudo registers for preferred slots - stack pointer. */ | |
108 | ||
109 | static void | |
110 | spu_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
111 | int regnum, gdb_byte *buf) | |
112 | { | |
113 | gdb_byte reg[16]; | |
114 | ||
115 | switch (regnum) | |
116 | { | |
117 | case SPU_SP_REGNUM: | |
118 | regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg); | |
119 | memcpy (buf, reg, 4); | |
120 | break; | |
121 | ||
122 | default: | |
123 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
124 | } | |
125 | } | |
126 | ||
127 | static void | |
128 | spu_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
129 | int regnum, const gdb_byte *buf) | |
130 | { | |
131 | gdb_byte reg[16]; | |
132 | ||
133 | switch (regnum) | |
134 | { | |
135 | case SPU_SP_REGNUM: | |
136 | regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg); | |
137 | memcpy (reg, buf, 4); | |
138 | regcache_raw_write (regcache, SPU_RAW_SP_REGNUM, reg); | |
139 | break; | |
140 | ||
141 | default: | |
142 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
143 | } | |
144 | } | |
145 | ||
146 | /* Value conversion -- access scalar values at the preferred slot. */ | |
147 | ||
148 | static int | |
149 | spu_convert_register_p (int regno, struct type *type) | |
150 | { | |
151 | return regno < SPU_NUM_GPRS && TYPE_LENGTH (type) < 16; | |
152 | } | |
153 | ||
154 | static void | |
155 | spu_register_to_value (struct frame_info *frame, int regnum, | |
156 | struct type *valtype, gdb_byte *out) | |
157 | { | |
158 | gdb_byte in[16]; | |
159 | int len = TYPE_LENGTH (valtype); | |
160 | int preferred_slot = len < 4 ? 4 - len : 0; | |
161 | gdb_assert (len < 16); | |
162 | ||
163 | get_frame_register (frame, regnum, in); | |
164 | memcpy (out, in + preferred_slot, len); | |
165 | } | |
166 | ||
167 | static void | |
168 | spu_value_to_register (struct frame_info *frame, int regnum, | |
169 | struct type *valtype, const gdb_byte *in) | |
170 | { | |
171 | gdb_byte out[16]; | |
172 | int len = TYPE_LENGTH (valtype); | |
173 | int preferred_slot = len < 4 ? 4 - len : 0; | |
174 | gdb_assert (len < 16); | |
175 | ||
176 | memset (out, 0, 16); | |
177 | memcpy (out + preferred_slot, in, len); | |
178 | put_frame_register (frame, regnum, out); | |
179 | } | |
180 | ||
181 | /* Register groups. */ | |
182 | ||
183 | static int | |
184 | spu_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
185 | struct reggroup *group) | |
186 | { | |
187 | /* Registers displayed via 'info regs'. */ | |
188 | if (group == general_reggroup) | |
189 | return 1; | |
190 | ||
191 | /* Registers displayed via 'info float'. */ | |
192 | if (group == float_reggroup) | |
193 | return 0; | |
194 | ||
195 | /* Registers that need to be saved/restored in order to | |
196 | push or pop frames. */ | |
197 | if (group == save_reggroup || group == restore_reggroup) | |
198 | return 1; | |
199 | ||
200 | return default_register_reggroup_p (gdbarch, regnum, group); | |
201 | } | |
202 | ||
203 | ||
204 | /* Decoding SPU instructions. */ | |
205 | ||
206 | enum | |
207 | { | |
208 | op_lqd = 0x34, | |
209 | op_lqx = 0x3c4, | |
210 | op_lqa = 0x61, | |
211 | op_lqr = 0x67, | |
212 | op_stqd = 0x24, | |
213 | op_stqx = 0x144, | |
214 | op_stqa = 0x41, | |
215 | op_stqr = 0x47, | |
216 | ||
217 | op_il = 0x081, | |
218 | op_ila = 0x21, | |
219 | op_a = 0x0c0, | |
220 | op_ai = 0x1c, | |
221 | ||
222 | op_selb = 0x4, | |
223 | ||
224 | op_br = 0x64, | |
225 | op_bra = 0x60, | |
226 | op_brsl = 0x66, | |
227 | op_brasl = 0x62, | |
228 | op_brnz = 0x42, | |
229 | op_brz = 0x40, | |
230 | op_brhnz = 0x46, | |
231 | op_brhz = 0x44, | |
232 | op_bi = 0x1a8, | |
233 | op_bisl = 0x1a9, | |
234 | op_biz = 0x128, | |
235 | op_binz = 0x129, | |
236 | op_bihz = 0x12a, | |
237 | op_bihnz = 0x12b, | |
238 | }; | |
239 | ||
240 | static int | |
241 | is_rr (unsigned int insn, int op, int *rt, int *ra, int *rb) | |
242 | { | |
243 | if ((insn >> 21) == op) | |
244 | { | |
245 | *rt = insn & 127; | |
246 | *ra = (insn >> 7) & 127; | |
247 | *rb = (insn >> 14) & 127; | |
248 | return 1; | |
249 | } | |
250 | ||
251 | return 0; | |
252 | } | |
253 | ||
254 | static int | |
255 | is_rrr (unsigned int insn, int op, int *rt, int *ra, int *rb, int *rc) | |
256 | { | |
257 | if ((insn >> 28) == op) | |
258 | { | |
259 | *rt = (insn >> 21) & 127; | |
260 | *ra = (insn >> 7) & 127; | |
261 | *rb = (insn >> 14) & 127; | |
262 | *rc = insn & 127; | |
263 | return 1; | |
264 | } | |
265 | ||
266 | return 0; | |
267 | } | |
268 | ||
269 | static int | |
270 | is_ri7 (unsigned int insn, int op, int *rt, int *ra, int *i7) | |
271 | { | |
272 | if ((insn >> 21) == op) | |
273 | { | |
274 | *rt = insn & 127; | |
275 | *ra = (insn >> 7) & 127; | |
276 | *i7 = (((insn >> 14) & 127) ^ 0x40) - 0x40; | |
277 | return 1; | |
278 | } | |
279 | ||
280 | return 0; | |
281 | } | |
282 | ||
283 | static int | |
284 | is_ri10 (unsigned int insn, int op, int *rt, int *ra, int *i10) | |
285 | { | |
286 | if ((insn >> 24) == op) | |
287 | { | |
288 | *rt = insn & 127; | |
289 | *ra = (insn >> 7) & 127; | |
290 | *i10 = (((insn >> 14) & 0x3ff) ^ 0x200) - 0x200; | |
291 | return 1; | |
292 | } | |
293 | ||
294 | return 0; | |
295 | } | |
296 | ||
297 | static int | |
298 | is_ri16 (unsigned int insn, int op, int *rt, int *i16) | |
299 | { | |
300 | if ((insn >> 23) == op) | |
301 | { | |
302 | *rt = insn & 127; | |
303 | *i16 = (((insn >> 7) & 0xffff) ^ 0x8000) - 0x8000; | |
304 | return 1; | |
305 | } | |
306 | ||
307 | return 0; | |
308 | } | |
309 | ||
310 | static int | |
311 | is_ri18 (unsigned int insn, int op, int *rt, int *i18) | |
312 | { | |
313 | if ((insn >> 25) == op) | |
314 | { | |
315 | *rt = insn & 127; | |
316 | *i18 = (((insn >> 7) & 0x3ffff) ^ 0x20000) - 0x20000; | |
317 | return 1; | |
318 | } | |
319 | ||
320 | return 0; | |
321 | } | |
322 | ||
323 | static int | |
324 | is_branch (unsigned int insn, int *offset, int *reg) | |
325 | { | |
326 | int rt, i7, i16; | |
327 | ||
328 | if (is_ri16 (insn, op_br, &rt, &i16) | |
329 | || is_ri16 (insn, op_brsl, &rt, &i16) | |
330 | || is_ri16 (insn, op_brnz, &rt, &i16) | |
331 | || is_ri16 (insn, op_brz, &rt, &i16) | |
332 | || is_ri16 (insn, op_brhnz, &rt, &i16) | |
333 | || is_ri16 (insn, op_brhz, &rt, &i16)) | |
334 | { | |
335 | *reg = SPU_PC_REGNUM; | |
336 | *offset = i16 << 2; | |
337 | return 1; | |
338 | } | |
339 | ||
340 | if (is_ri16 (insn, op_bra, &rt, &i16) | |
341 | || is_ri16 (insn, op_brasl, &rt, &i16)) | |
342 | { | |
343 | *reg = -1; | |
344 | *offset = i16 << 2; | |
345 | return 1; | |
346 | } | |
347 | ||
348 | if (is_ri7 (insn, op_bi, &rt, reg, &i7) | |
349 | || is_ri7 (insn, op_bisl, &rt, reg, &i7) | |
350 | || is_ri7 (insn, op_biz, &rt, reg, &i7) | |
351 | || is_ri7 (insn, op_binz, &rt, reg, &i7) | |
352 | || is_ri7 (insn, op_bihz, &rt, reg, &i7) | |
353 | || is_ri7 (insn, op_bihnz, &rt, reg, &i7)) | |
354 | { | |
355 | *offset = 0; | |
356 | return 1; | |
357 | } | |
358 | ||
359 | return 0; | |
360 | } | |
361 | ||
362 | ||
363 | /* Prolog parsing. */ | |
364 | ||
365 | struct spu_prologue_data | |
366 | { | |
367 | /* Stack frame size. -1 if analysis was unsuccessful. */ | |
368 | int size; | |
369 | ||
370 | /* How to find the CFA. The CFA is equal to SP at function entry. */ | |
371 | int cfa_reg; | |
372 | int cfa_offset; | |
373 | ||
374 | /* Offset relative to CFA where a register is saved. -1 if invalid. */ | |
375 | int reg_offset[SPU_NUM_GPRS]; | |
376 | }; | |
377 | ||
378 | static CORE_ADDR | |
379 | spu_analyze_prologue (CORE_ADDR start_pc, CORE_ADDR end_pc, | |
380 | struct spu_prologue_data *data) | |
381 | { | |
382 | int found_sp = 0; | |
383 | int found_fp = 0; | |
384 | int found_lr = 0; | |
385 | int reg_immed[SPU_NUM_GPRS]; | |
386 | gdb_byte buf[16]; | |
387 | CORE_ADDR prolog_pc = start_pc; | |
388 | CORE_ADDR pc; | |
389 | int i; | |
390 | ||
391 | ||
392 | /* Initialize DATA to default values. */ | |
393 | data->size = -1; | |
394 | ||
395 | data->cfa_reg = SPU_RAW_SP_REGNUM; | |
396 | data->cfa_offset = 0; | |
397 | ||
398 | for (i = 0; i < SPU_NUM_GPRS; i++) | |
399 | data->reg_offset[i] = -1; | |
400 | ||
401 | /* Set up REG_IMMED array. This is non-zero for a register if we know its | |
402 | preferred slot currently holds this immediate value. */ | |
403 | for (i = 0; i < SPU_NUM_GPRS; i++) | |
404 | reg_immed[i] = 0; | |
405 | ||
406 | /* Scan instructions until the first branch. | |
407 | ||
408 | The following instructions are important prolog components: | |
409 | ||
410 | - The first instruction to set up the stack pointer. | |
411 | - The first instruction to set up the frame pointer. | |
412 | - The first instruction to save the link register. | |
413 | ||
414 | We return the instruction after the latest of these three, | |
415 | or the incoming PC if none is found. The first instruction | |
416 | to set up the stack pointer also defines the frame size. | |
417 | ||
418 | Note that instructions saving incoming arguments to their stack | |
419 | slots are not counted as important, because they are hard to | |
420 | identify with certainty. This should not matter much, because | |
421 | arguments are relevant only in code compiled with debug data, | |
422 | and in such code the GDB core will advance until the first source | |
423 | line anyway, using SAL data. | |
424 | ||
425 | For purposes of stack unwinding, we analyze the following types | |
426 | of instructions in addition: | |
427 | ||
428 | - Any instruction adding to the current frame pointer. | |
429 | - Any instruction loading an immediate constant into a register. | |
430 | - Any instruction storing a register onto the stack. | |
431 | ||
432 | These are used to compute the CFA and REG_OFFSET output. */ | |
433 | ||
434 | for (pc = start_pc; pc < end_pc; pc += 4) | |
435 | { | |
436 | unsigned int insn; | |
437 | int rt, ra, rb, rc, immed; | |
438 | ||
439 | if (target_read_memory (pc, buf, 4)) | |
440 | break; | |
441 | insn = extract_unsigned_integer (buf, 4); | |
442 | ||
443 | /* AI is the typical instruction to set up a stack frame. | |
444 | It is also used to initialize the frame pointer. */ | |
445 | if (is_ri10 (insn, op_ai, &rt, &ra, &immed)) | |
446 | { | |
447 | if (rt == data->cfa_reg && ra == data->cfa_reg) | |
448 | data->cfa_offset -= immed; | |
449 | ||
450 | if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM | |
451 | && !found_sp) | |
452 | { | |
453 | found_sp = 1; | |
454 | prolog_pc = pc + 4; | |
455 | ||
456 | data->size = -immed; | |
457 | } | |
458 | else if (rt == SPU_FP_REGNUM && ra == SPU_RAW_SP_REGNUM | |
459 | && !found_fp) | |
460 | { | |
461 | found_fp = 1; | |
462 | prolog_pc = pc + 4; | |
463 | ||
464 | data->cfa_reg = SPU_FP_REGNUM; | |
465 | data->cfa_offset -= immed; | |
466 | } | |
467 | } | |
468 | ||
469 | /* A is used to set up stack frames of size >= 512 bytes. | |
470 | If we have tracked the contents of the addend register, | |
471 | we can handle this as well. */ | |
472 | else if (is_rr (insn, op_a, &rt, &ra, &rb)) | |
473 | { | |
474 | if (rt == data->cfa_reg && ra == data->cfa_reg) | |
475 | { | |
476 | if (reg_immed[rb] != 0) | |
477 | data->cfa_offset -= reg_immed[rb]; | |
478 | else | |
479 | data->cfa_reg = -1; /* We don't know the CFA any more. */ | |
480 | } | |
481 | ||
482 | if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM | |
483 | && !found_sp) | |
484 | { | |
485 | found_sp = 1; | |
486 | prolog_pc = pc + 4; | |
487 | ||
488 | if (reg_immed[rb] != 0) | |
489 | data->size = -reg_immed[rb]; | |
490 | } | |
491 | } | |
492 | ||
493 | /* We need to track IL and ILA used to load immediate constants | |
494 | in case they are later used as input to an A instruction. */ | |
495 | else if (is_ri16 (insn, op_il, &rt, &immed)) | |
496 | { | |
497 | reg_immed[rt] = immed; | |
498 | } | |
499 | ||
500 | else if (is_ri18 (insn, op_ila, &rt, &immed)) | |
501 | { | |
502 | reg_immed[rt] = immed & 0x3ffff; | |
503 | } | |
504 | ||
505 | /* STQD is used to save registers to the stack. */ | |
506 | else if (is_ri10 (insn, op_stqd, &rt, &ra, &immed)) | |
507 | { | |
508 | if (ra == data->cfa_reg) | |
509 | data->reg_offset[rt] = data->cfa_offset - (immed << 4); | |
510 | ||
511 | if (ra == data->cfa_reg && rt == SPU_LR_REGNUM | |
512 | && !found_lr) | |
513 | { | |
514 | found_lr = 1; | |
515 | prolog_pc = pc + 4; | |
516 | } | |
517 | } | |
518 | ||
519 | /* _start uses SELB to set up the stack pointer. */ | |
520 | else if (is_rrr (insn, op_selb, &rt, &ra, &rb, &rc)) | |
521 | { | |
522 | if (rt == SPU_RAW_SP_REGNUM && !found_sp) | |
523 | found_sp = 1; | |
524 | } | |
525 | ||
526 | /* We terminate if we find a branch. */ | |
527 | else if (is_branch (insn, &immed, &ra)) | |
528 | break; | |
529 | } | |
530 | ||
531 | ||
532 | /* If we successfully parsed until here, and didn't find any instruction | |
533 | modifying SP, we assume we have a frameless function. */ | |
534 | if (!found_sp) | |
535 | data->size = 0; | |
536 | ||
537 | /* Return cooked instead of raw SP. */ | |
538 | if (data->cfa_reg == SPU_RAW_SP_REGNUM) | |
539 | data->cfa_reg = SPU_SP_REGNUM; | |
540 | ||
541 | return prolog_pc; | |
542 | } | |
543 | ||
544 | /* Return the first instruction after the prologue starting at PC. */ | |
545 | static CORE_ADDR | |
546 | spu_skip_prologue (CORE_ADDR pc) | |
547 | { | |
548 | struct spu_prologue_data data; | |
549 | return spu_analyze_prologue (pc, (CORE_ADDR)-1, &data); | |
550 | } | |
551 | ||
552 | /* Return the frame pointer in use at address PC. */ | |
553 | static void | |
554 | spu_virtual_frame_pointer (CORE_ADDR pc, int *reg, LONGEST *offset) | |
555 | { | |
556 | struct spu_prologue_data data; | |
557 | spu_analyze_prologue (pc, (CORE_ADDR)-1, &data); | |
558 | ||
559 | if (data.size != -1 && data.cfa_reg != -1) | |
560 | { | |
561 | /* The 'frame pointer' address is CFA minus frame size. */ | |
562 | *reg = data.cfa_reg; | |
563 | *offset = data.cfa_offset - data.size; | |
564 | } | |
565 | else | |
566 | { | |
567 | /* ??? We don't really know ... */ | |
568 | *reg = SPU_SP_REGNUM; | |
569 | *offset = 0; | |
570 | } | |
571 | } | |
572 | ||
573 | /* Normal stack frames. */ | |
574 | ||
575 | struct spu_unwind_cache | |
576 | { | |
577 | CORE_ADDR func; | |
578 | CORE_ADDR frame_base; | |
579 | CORE_ADDR local_base; | |
580 | ||
581 | struct trad_frame_saved_reg *saved_regs; | |
582 | }; | |
583 | ||
584 | static struct spu_unwind_cache * | |
585 | spu_frame_unwind_cache (struct frame_info *next_frame, | |
586 | void **this_prologue_cache) | |
587 | { | |
588 | struct spu_unwind_cache *info; | |
589 | struct spu_prologue_data data; | |
590 | ||
591 | if (*this_prologue_cache) | |
592 | return *this_prologue_cache; | |
593 | ||
594 | info = FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache); | |
595 | *this_prologue_cache = info; | |
596 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
597 | info->frame_base = 0; | |
598 | info->local_base = 0; | |
599 | ||
600 | /* Find the start of the current function, and analyze its prologue. */ | |
601 | info->func = frame_func_unwind (next_frame); | |
602 | if (info->func == 0) | |
603 | { | |
604 | /* Fall back to using the current PC as frame ID. */ | |
605 | info->func = frame_pc_unwind (next_frame); | |
606 | data.size = -1; | |
607 | } | |
608 | else | |
609 | spu_analyze_prologue (info->func, frame_pc_unwind (next_frame), &data); | |
610 | ||
611 | ||
612 | /* If successful, use prologue analysis data. */ | |
613 | if (data.size != -1 && data.cfa_reg != -1) | |
614 | { | |
615 | CORE_ADDR cfa; | |
616 | int i; | |
617 | gdb_byte buf[16]; | |
618 | ||
619 | /* Determine CFA via unwound CFA_REG plus CFA_OFFSET. */ | |
620 | frame_unwind_register (next_frame, data.cfa_reg, buf); | |
621 | cfa = extract_unsigned_integer (buf, 4) + data.cfa_offset; | |
622 | ||
623 | /* Call-saved register slots. */ | |
624 | for (i = 0; i < SPU_NUM_GPRS; i++) | |
625 | if (i == SPU_LR_REGNUM | |
626 | || (i >= SPU_SAVED1_REGNUM && i <= SPU_SAVEDN_REGNUM)) | |
627 | if (data.reg_offset[i] != -1) | |
628 | info->saved_regs[i].addr = cfa - data.reg_offset[i]; | |
629 | ||
630 | /* The previous PC comes from the link register. */ | |
631 | if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM)) | |
632 | info->saved_regs[SPU_PC_REGNUM] = info->saved_regs[SPU_LR_REGNUM]; | |
633 | else | |
634 | info->saved_regs[SPU_PC_REGNUM].realreg = SPU_LR_REGNUM; | |
635 | ||
636 | /* The previous SP is equal to the CFA. */ | |
637 | trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM, cfa); | |
638 | ||
639 | /* Frame bases. */ | |
640 | info->frame_base = cfa; | |
641 | info->local_base = cfa - data.size; | |
642 | } | |
643 | ||
644 | /* Otherwise, fall back to reading the backchain link. */ | |
645 | else | |
646 | { | |
647 | CORE_ADDR reg, backchain; | |
648 | ||
649 | /* Get the backchain. */ | |
650 | reg = frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM); | |
651 | backchain = read_memory_unsigned_integer (reg, 4); | |
652 | ||
653 | /* A zero backchain terminates the frame chain. Also, sanity | |
654 | check against the local store size limit. */ | |
655 | if (backchain != 0 && backchain < SPU_LS_SIZE) | |
656 | { | |
657 | /* Assume the link register is saved into its slot. */ | |
658 | if (backchain + 16 < SPU_LS_SIZE) | |
659 | info->saved_regs[SPU_LR_REGNUM].addr = backchain + 16; | |
660 | ||
661 | /* This will also be the previous PC. */ | |
662 | if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM)) | |
663 | info->saved_regs[SPU_PC_REGNUM] = info->saved_regs[SPU_LR_REGNUM]; | |
664 | else | |
665 | info->saved_regs[SPU_PC_REGNUM].realreg = SPU_LR_REGNUM; | |
666 | ||
667 | /* The previous SP will equal the backchain value. */ | |
668 | trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM, backchain); | |
669 | ||
670 | /* Frame bases. */ | |
671 | info->frame_base = backchain; | |
672 | info->local_base = reg; | |
673 | } | |
674 | } | |
675 | ||
676 | return info; | |
677 | } | |
678 | ||
679 | static void | |
680 | spu_frame_this_id (struct frame_info *next_frame, | |
681 | void **this_prologue_cache, struct frame_id *this_id) | |
682 | { | |
683 | struct spu_unwind_cache *info = | |
684 | spu_frame_unwind_cache (next_frame, this_prologue_cache); | |
685 | ||
686 | if (info->frame_base == 0) | |
687 | return; | |
688 | ||
689 | *this_id = frame_id_build (info->frame_base, info->func); | |
690 | } | |
691 | ||
692 | static void | |
693 | spu_frame_prev_register (struct frame_info *next_frame, | |
694 | void **this_prologue_cache, | |
695 | int regnum, int *optimizedp, | |
696 | enum lval_type *lvalp, CORE_ADDR * addrp, | |
697 | int *realnump, gdb_byte *bufferp) | |
698 | { | |
699 | struct spu_unwind_cache *info | |
700 | = spu_frame_unwind_cache (next_frame, this_prologue_cache); | |
701 | ||
702 | /* Special-case the stack pointer. */ | |
703 | if (regnum == SPU_RAW_SP_REGNUM) | |
704 | regnum = SPU_SP_REGNUM; | |
705 | ||
706 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
707 | optimizedp, lvalp, addrp, realnump, bufferp); | |
708 | } | |
709 | ||
710 | static const struct frame_unwind spu_frame_unwind = { | |
711 | NORMAL_FRAME, | |
712 | spu_frame_this_id, | |
713 | spu_frame_prev_register | |
714 | }; | |
715 | ||
716 | const struct frame_unwind * | |
717 | spu_frame_sniffer (struct frame_info *next_frame) | |
718 | { | |
719 | return &spu_frame_unwind; | |
720 | } | |
721 | ||
722 | static CORE_ADDR | |
723 | spu_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
724 | { | |
725 | struct spu_unwind_cache *info | |
726 | = spu_frame_unwind_cache (next_frame, this_cache); | |
727 | return info->local_base; | |
728 | } | |
729 | ||
730 | static const struct frame_base spu_frame_base = { | |
731 | &spu_frame_unwind, | |
732 | spu_frame_base_address, | |
733 | spu_frame_base_address, | |
734 | spu_frame_base_address | |
735 | }; | |
736 | ||
737 | static CORE_ADDR | |
738 | spu_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
739 | { | |
740 | return frame_unwind_register_unsigned (next_frame, SPU_PC_REGNUM); | |
741 | } | |
742 | ||
743 | static CORE_ADDR | |
744 | spu_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
745 | { | |
746 | return frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM); | |
747 | } | |
748 | ||
749 | ||
750 | /* Function calling convention. */ | |
751 | ||
752 | static int | |
753 | spu_scalar_value_p (struct type *type) | |
754 | { | |
755 | switch (TYPE_CODE (type)) | |
756 | { | |
757 | case TYPE_CODE_INT: | |
758 | case TYPE_CODE_ENUM: | |
759 | case TYPE_CODE_RANGE: | |
760 | case TYPE_CODE_CHAR: | |
761 | case TYPE_CODE_BOOL: | |
762 | case TYPE_CODE_PTR: | |
763 | case TYPE_CODE_REF: | |
764 | return TYPE_LENGTH (type) <= 16; | |
765 | ||
766 | default: | |
767 | return 0; | |
768 | } | |
769 | } | |
770 | ||
771 | static void | |
772 | spu_value_to_regcache (struct regcache *regcache, int regnum, | |
773 | struct type *type, const gdb_byte *in) | |
774 | { | |
775 | int len = TYPE_LENGTH (type); | |
776 | ||
777 | if (spu_scalar_value_p (type)) | |
778 | { | |
779 | int preferred_slot = len < 4 ? 4 - len : 0; | |
780 | regcache_cooked_write_part (regcache, regnum, preferred_slot, len, in); | |
781 | } | |
782 | else | |
783 | { | |
784 | while (len >= 16) | |
785 | { | |
786 | regcache_cooked_write (regcache, regnum++, in); | |
787 | in += 16; | |
788 | len -= 16; | |
789 | } | |
790 | ||
791 | if (len > 0) | |
792 | regcache_cooked_write_part (regcache, regnum, 0, len, in); | |
793 | } | |
794 | } | |
795 | ||
796 | static void | |
797 | spu_regcache_to_value (struct regcache *regcache, int regnum, | |
798 | struct type *type, gdb_byte *out) | |
799 | { | |
800 | int len = TYPE_LENGTH (type); | |
801 | ||
802 | if (spu_scalar_value_p (type)) | |
803 | { | |
804 | int preferred_slot = len < 4 ? 4 - len : 0; | |
805 | regcache_cooked_read_part (regcache, regnum, preferred_slot, len, out); | |
806 | } | |
807 | else | |
808 | { | |
809 | while (len >= 16) | |
810 | { | |
811 | regcache_cooked_read (regcache, regnum++, out); | |
812 | out += 16; | |
813 | len -= 16; | |
814 | } | |
815 | ||
816 | if (len > 0) | |
817 | regcache_cooked_read_part (regcache, regnum, 0, len, out); | |
818 | } | |
819 | } | |
820 | ||
821 | static CORE_ADDR | |
822 | spu_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
823 | struct regcache *regcache, CORE_ADDR bp_addr, | |
824 | int nargs, struct value **args, CORE_ADDR sp, | |
825 | int struct_return, CORE_ADDR struct_addr) | |
826 | { | |
827 | int i; | |
828 | int regnum = SPU_ARG1_REGNUM; | |
829 | int stack_arg = -1; | |
830 | gdb_byte buf[16]; | |
831 | ||
832 | /* Set the return address. */ | |
833 | memset (buf, 0, sizeof buf); | |
834 | store_unsigned_integer (buf, 4, bp_addr); | |
835 | regcache_cooked_write (regcache, SPU_LR_REGNUM, buf); | |
836 | ||
837 | /* If STRUCT_RETURN is true, then the struct return address (in | |
838 | STRUCT_ADDR) will consume the first argument-passing register. | |
839 | Both adjust the register count and store that value. */ | |
840 | if (struct_return) | |
841 | { | |
842 | memset (buf, 0, sizeof buf); | |
843 | store_unsigned_integer (buf, 4, struct_addr); | |
844 | regcache_cooked_write (regcache, regnum++, buf); | |
845 | } | |
846 | ||
847 | /* Fill in argument registers. */ | |
848 | for (i = 0; i < nargs; i++) | |
849 | { | |
850 | struct value *arg = args[i]; | |
851 | struct type *type = check_typedef (value_type (arg)); | |
852 | const gdb_byte *contents = value_contents (arg); | |
853 | int len = TYPE_LENGTH (type); | |
854 | int n_regs = align_up (len, 16) / 16; | |
855 | ||
856 | /* If the argument doesn't wholly fit into registers, it and | |
857 | all subsequent arguments go to the stack. */ | |
858 | if (regnum + n_regs - 1 > SPU_ARGN_REGNUM) | |
859 | { | |
860 | stack_arg = i; | |
861 | break; | |
862 | } | |
863 | ||
864 | spu_value_to_regcache (regcache, regnum, type, contents); | |
865 | regnum += n_regs; | |
866 | } | |
867 | ||
868 | /* Overflow arguments go to the stack. */ | |
869 | if (stack_arg != -1) | |
870 | { | |
871 | CORE_ADDR ap; | |
872 | ||
873 | /* Allocate all required stack size. */ | |
874 | for (i = stack_arg; i < nargs; i++) | |
875 | { | |
876 | struct type *type = check_typedef (value_type (args[i])); | |
877 | sp -= align_up (TYPE_LENGTH (type), 16); | |
878 | } | |
879 | ||
880 | /* Fill in stack arguments. */ | |
881 | ap = sp; | |
882 | for (i = stack_arg; i < nargs; i++) | |
883 | { | |
884 | struct value *arg = args[i]; | |
885 | struct type *type = check_typedef (value_type (arg)); | |
886 | int len = TYPE_LENGTH (type); | |
887 | int preferred_slot; | |
888 | ||
889 | if (spu_scalar_value_p (type)) | |
890 | preferred_slot = len < 4 ? 4 - len : 0; | |
891 | else | |
892 | preferred_slot = 0; | |
893 | ||
894 | target_write_memory (ap + preferred_slot, value_contents (arg), len); | |
895 | ap += align_up (TYPE_LENGTH (type), 16); | |
896 | } | |
897 | } | |
898 | ||
899 | /* Allocate stack frame header. */ | |
900 | sp -= 32; | |
901 | ||
902 | /* Finally, update the SP register. */ | |
903 | regcache_cooked_write_unsigned (regcache, SPU_SP_REGNUM, sp); | |
904 | ||
905 | return sp; | |
906 | } | |
907 | ||
908 | static struct frame_id | |
909 | spu_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
910 | { | |
911 | return frame_id_build (spu_unwind_sp (gdbarch, next_frame), | |
912 | spu_unwind_pc (gdbarch, next_frame)); | |
913 | } | |
914 | ||
915 | /* Function return value access. */ | |
916 | ||
917 | static enum return_value_convention | |
918 | spu_return_value (struct gdbarch *gdbarch, struct type *type, | |
919 | struct regcache *regcache, gdb_byte *out, const gdb_byte *in) | |
920 | { | |
921 | enum return_value_convention rvc; | |
922 | ||
923 | if (TYPE_LENGTH (type) <= (SPU_ARGN_REGNUM - SPU_ARG1_REGNUM + 1) * 16) | |
924 | rvc = RETURN_VALUE_REGISTER_CONVENTION; | |
925 | else | |
926 | rvc = RETURN_VALUE_STRUCT_CONVENTION; | |
927 | ||
928 | if (in) | |
929 | { | |
930 | switch (rvc) | |
931 | { | |
932 | case RETURN_VALUE_REGISTER_CONVENTION: | |
933 | spu_value_to_regcache (regcache, SPU_ARG1_REGNUM, type, in); | |
934 | break; | |
935 | ||
936 | case RETURN_VALUE_STRUCT_CONVENTION: | |
937 | error ("Cannot set function return value."); | |
938 | break; | |
939 | } | |
940 | } | |
941 | else if (out) | |
942 | { | |
943 | switch (rvc) | |
944 | { | |
945 | case RETURN_VALUE_REGISTER_CONVENTION: | |
946 | spu_regcache_to_value (regcache, SPU_ARG1_REGNUM, type, out); | |
947 | break; | |
948 | ||
949 | case RETURN_VALUE_STRUCT_CONVENTION: | |
950 | error ("Function return value unknown."); | |
951 | break; | |
952 | } | |
953 | } | |
954 | ||
955 | return rvc; | |
956 | } | |
957 | ||
958 | ||
959 | /* Breakpoints. */ | |
960 | ||
961 | static const gdb_byte * | |
962 | spu_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr) | |
963 | { | |
964 | static const gdb_byte breakpoint[] = { 0x00, 0x00, 0x3f, 0xff }; | |
965 | ||
966 | *lenptr = sizeof breakpoint; | |
967 | return breakpoint; | |
968 | } | |
969 | ||
970 | ||
971 | /* Software single-stepping support. */ | |
972 | ||
973 | void | |
974 | spu_software_single_step (enum target_signal signal, int insert_breakpoints_p) | |
975 | { | |
976 | if (insert_breakpoints_p) | |
977 | { | |
978 | CORE_ADDR pc, next_pc; | |
979 | unsigned int insn; | |
980 | int offset, reg; | |
981 | gdb_byte buf[4]; | |
982 | ||
983 | regcache_cooked_read (current_regcache, SPU_PC_REGNUM, buf); | |
984 | pc = extract_unsigned_integer (buf, 4); | |
985 | ||
986 | if (target_read_memory (pc, buf, 4)) | |
987 | return; | |
988 | insn = extract_unsigned_integer (buf, 4); | |
989 | ||
990 | /* Next sequential instruction is at PC + 4, except if the current | |
991 | instruction is a PPE-assisted call, in which case it is at PC + 8. | |
992 | Wrap around LS limit to be on the safe side. */ | |
993 | if ((insn & 0xffffff00) == 0x00002100) | |
994 | next_pc = (pc + 8) & (SPU_LS_SIZE - 1) & -4; | |
995 | else | |
996 | next_pc = (pc + 4) & (SPU_LS_SIZE - 1) & -4; | |
997 | ||
998 | insert_single_step_breakpoint (next_pc); | |
999 | ||
1000 | if (is_branch (insn, &offset, ®)) | |
1001 | { | |
1002 | CORE_ADDR target = offset; | |
1003 | ||
1004 | if (reg == SPU_PC_REGNUM) | |
1005 | target += pc; | |
1006 | else if (reg != -1) | |
1007 | { | |
1008 | regcache_cooked_read_part (current_regcache, reg, 0, 4, buf); | |
1009 | target += extract_unsigned_integer (buf, 4); | |
1010 | } | |
1011 | ||
1012 | target = target & (SPU_LS_SIZE - 1) & -4; | |
1013 | if (target != next_pc) | |
1014 | insert_single_step_breakpoint (target); | |
1015 | } | |
1016 | } | |
1017 | else | |
1018 | remove_single_step_breakpoints (); | |
1019 | } | |
1020 | ||
1021 | ||
1022 | /* Set up gdbarch struct. */ | |
1023 | ||
1024 | static struct gdbarch * | |
1025 | spu_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1026 | { | |
1027 | struct gdbarch *gdbarch; | |
1028 | ||
1029 | /* Find a candidate among the list of pre-declared architectures. */ | |
1030 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1031 | if (arches != NULL) | |
1032 | return arches->gdbarch; | |
1033 | ||
1034 | /* Is is for us? */ | |
1035 | if (info.bfd_arch_info->mach != bfd_mach_spu) | |
1036 | return NULL; | |
1037 | ||
1038 | /* Yes, create a new architecture. */ | |
1039 | gdbarch = gdbarch_alloc (&info, NULL); | |
1040 | ||
1041 | /* Disassembler. */ | |
1042 | set_gdbarch_print_insn (gdbarch, print_insn_spu); | |
1043 | ||
1044 | /* Registers. */ | |
1045 | set_gdbarch_num_regs (gdbarch, SPU_NUM_REGS); | |
1046 | set_gdbarch_num_pseudo_regs (gdbarch, SPU_NUM_PSEUDO_REGS); | |
1047 | set_gdbarch_sp_regnum (gdbarch, SPU_SP_REGNUM); | |
1048 | set_gdbarch_pc_regnum (gdbarch, SPU_PC_REGNUM); | |
1049 | set_gdbarch_register_name (gdbarch, spu_register_name); | |
1050 | set_gdbarch_register_type (gdbarch, spu_register_type); | |
1051 | set_gdbarch_pseudo_register_read (gdbarch, spu_pseudo_register_read); | |
1052 | set_gdbarch_pseudo_register_write (gdbarch, spu_pseudo_register_write); | |
1053 | set_gdbarch_convert_register_p (gdbarch, spu_convert_register_p); | |
1054 | set_gdbarch_register_to_value (gdbarch, spu_register_to_value); | |
1055 | set_gdbarch_value_to_register (gdbarch, spu_value_to_register); | |
1056 | set_gdbarch_register_reggroup_p (gdbarch, spu_register_reggroup_p); | |
1057 | ||
1058 | /* Data types. */ | |
1059 | set_gdbarch_char_signed (gdbarch, 0); | |
1060 | set_gdbarch_ptr_bit (gdbarch, 32); | |
1061 | set_gdbarch_addr_bit (gdbarch, 32); | |
1062 | set_gdbarch_short_bit (gdbarch, 16); | |
1063 | set_gdbarch_int_bit (gdbarch, 32); | |
1064 | set_gdbarch_long_bit (gdbarch, 32); | |
1065 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1066 | set_gdbarch_float_bit (gdbarch, 32); | |
1067 | set_gdbarch_double_bit (gdbarch, 64); | |
1068 | set_gdbarch_long_double_bit (gdbarch, 64); | |
1069 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); | |
1070 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big); | |
1071 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
1072 | ||
1073 | /* Inferior function calls. */ | |
1074 | set_gdbarch_push_dummy_call (gdbarch, spu_push_dummy_call); | |
1075 | set_gdbarch_unwind_dummy_id (gdbarch, spu_unwind_dummy_id); | |
1076 | set_gdbarch_return_value (gdbarch, spu_return_value); | |
1077 | ||
1078 | /* Frame handling. */ | |
1079 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1080 | frame_unwind_append_sniffer (gdbarch, spu_frame_sniffer); | |
1081 | frame_base_set_default (gdbarch, &spu_frame_base); | |
1082 | set_gdbarch_unwind_pc (gdbarch, spu_unwind_pc); | |
1083 | set_gdbarch_unwind_sp (gdbarch, spu_unwind_sp); | |
1084 | set_gdbarch_virtual_frame_pointer (gdbarch, spu_virtual_frame_pointer); | |
1085 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
1086 | set_gdbarch_skip_prologue (gdbarch, spu_skip_prologue); | |
1087 | ||
1088 | /* Breakpoints. */ | |
1089 | set_gdbarch_decr_pc_after_break (gdbarch, 4); | |
1090 | set_gdbarch_breakpoint_from_pc (gdbarch, spu_breakpoint_from_pc); | |
1091 | set_gdbarch_cannot_step_breakpoint (gdbarch, 1); | |
1092 | set_gdbarch_software_single_step (gdbarch, spu_software_single_step); | |
1093 | ||
1094 | return gdbarch; | |
1095 | } | |
1096 | ||
f2d43c2c UW |
1097 | /* Implement a SPU-specific vector type as replacement |
1098 | for __gdb_builtin_type_vec128. */ | |
1099 | static void | |
1100 | spu_init_vector_type (void) | |
1101 | { | |
1102 | struct type *type; | |
1103 | ||
1104 | type = init_composite_type ("__spu_builtin_type_vec128", TYPE_CODE_UNION); | |
1105 | append_composite_type_field (type, "uint128", builtin_type_int128); | |
1106 | append_composite_type_field (type, "v2_int64", builtin_type_v2_int64); | |
1107 | append_composite_type_field (type, "v4_int32", builtin_type_v4_int32); | |
1108 | append_composite_type_field (type, "v8_int16", builtin_type_v8_int16); | |
1109 | append_composite_type_field (type, "v16_int8", builtin_type_v16_int8); | |
1110 | append_composite_type_field (type, "v2_double", builtin_type_v2_double); | |
1111 | append_composite_type_field (type, "v4_float", builtin_type_v4_float); | |
1112 | ||
1113 | TYPE_FLAGS (type) |= TYPE_FLAG_VECTOR; | |
1114 | TYPE_NAME (type) = "spu_builtin_type_vec128"; | |
1115 | spu_builtin_type_vec128 = type; | |
1116 | } | |
1117 | ||
771b4502 UW |
1118 | void |
1119 | _initialize_spu_tdep (void) | |
1120 | { | |
1121 | register_gdbarch_init (bfd_arch_spu, spu_gdbarch_init); | |
f2d43c2c UW |
1122 | |
1123 | spu_init_vector_type (); | |
771b4502 | 1124 | } |