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sim: change raddr to address_word
[deliverable/binutils-gdb.git] / gdb / spu-tdep.c
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771b4502 1/* SPU target-dependent code for GDB, the GNU debugger.
4c38e0a4 2 Copyright (C) 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
771b4502
UW		 3
4 Contributed by Ulrich Weigand <uweigand@de.ibm.com>.
5 Based on a port by Sid Manning <sid@us.ibm.com>.
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
a9762ec7 11 the Free Software Foundation; either version 3 of the License, or
771b4502
UW		 12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
a9762ec7 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
771b4502
UW		 21
22#include "defs.h"
23#include "arch-utils.h"
24#include "gdbtypes.h"
25#include "gdbcmd.h"
26#include "gdbcore.h"
27#include "gdb_string.h"
28#include "gdb_assert.h"
29#include "frame.h"
30#include "frame-unwind.h"
31#include "frame-base.h"
32#include "trad-frame.h"
33#include "symtab.h"
34#include "symfile.h"
35#include "value.h"
36#include "inferior.h"
37#include "dis-asm.h"
38#include "objfiles.h"
39#include "language.h"
40#include "regcache.h"
41#include "reggroups.h"
42#include "floatformat.h"
3285f3fe 43#include "block.h"
dcf52cd8 44#include "observer.h"
ff1a52c6 45#include "infcall.h"
771b4502
UW		 46
47#include "spu-tdep.h"
48
794ac428 49
3285f3fe
UW		 50/* The list of available "set spu " and "show spu " commands. */
51static struct cmd_list_element *setspucmdlist = NULL;
52static struct cmd_list_element *showspucmdlist = NULL;
53
54/* Whether to stop for new SPE contexts. */
55static int spu_stop_on_load_p = 0;
ff1a52c6
UW		 56/* Whether to automatically flush the SW-managed cache. */
57static int spu_auto_flush_cache_p = 1;
3285f3fe
UW		 58
59
794ac428
UW		 60/* The tdep structure. */
61struct gdbarch_tdep
62{
85e747d2
UW		 63 /* The spufs ID identifying our address space. */
64 int id;
65
794ac428
UW		 66 /* SPU-specific vector type. */
67 struct type *spu_builtin_type_vec128;
68};
69
70
f2d43c2c 71/* SPU-specific vector type. */
794ac428
UW		 72static struct type *
73spu_builtin_type_vec128 (struct gdbarch *gdbarch)
74{
75 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
76
77 if (!tdep->spu_builtin_type_vec128)
78 {
df4df182 79 const struct builtin_type *bt = builtin_type (gdbarch);
794ac428
UW		 80 struct type *t;
81
e9bb382b
UW		 82 t = arch_composite_type (gdbarch,
83 "__spu_builtin_type_vec128", TYPE_CODE_UNION);
df4df182 84 append_composite_type_field (t, "uint128", bt->builtin_int128);
794ac428 85 append_composite_type_field (t, "v2_int64",
df4df182 86 init_vector_type (bt->builtin_int64, 2));
794ac428 87 append_composite_type_field (t, "v4_int32",
df4df182 88 init_vector_type (bt->builtin_int32, 4));
794ac428 89 append_composite_type_field (t, "v8_int16",
df4df182 90 init_vector_type (bt->builtin_int16, 8));
794ac428 91 append_composite_type_field (t, "v16_int8",
df4df182 92 init_vector_type (bt->builtin_int8, 16));
794ac428 93 append_composite_type_field (t, "v2_double",
df4df182 94 init_vector_type (bt->builtin_double, 2));
794ac428 95 append_composite_type_field (t, "v4_float",
df4df182 96 init_vector_type (bt->builtin_float, 4));
794ac428 97
876cecd0 98 TYPE_VECTOR (t) = 1;
794ac428
UW		 99 TYPE_NAME (t) = "spu_builtin_type_vec128";
100
101 tdep->spu_builtin_type_vec128 = t;
102 }
103
104 return tdep->spu_builtin_type_vec128;
105}
106
771b4502 107
23d964e7
UW		 108/* The list of available "info spu " commands. */
109static struct cmd_list_element *infospucmdlist = NULL;
110
771b4502
UW		 111/* Registers. */
112
113static const char *
d93859e2 114spu_register_name (struct gdbarch *gdbarch, int reg_nr)
771b4502
UW		 115{
116 static char *register_names[] =
117 {
118 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
119 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
120 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
121 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
122 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
123 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
124 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
125 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
126 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
127 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
128 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
129 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
130 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
131 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
132 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
133 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
23d964e7 134 "id", "pc", "sp", "fpscr", "srr0", "lslr", "decr", "decr_status"
771b4502
UW		 135 };
136
137 if (reg_nr < 0)
138 return NULL;
139 if (reg_nr >= sizeof register_names / sizeof *register_names)
140 return NULL;
141
142 return register_names[reg_nr];
143}
144
145static struct type *
146spu_register_type (struct gdbarch *gdbarch, int reg_nr)
147{
148 if (reg_nr < SPU_NUM_GPRS)
794ac428 149 return spu_builtin_type_vec128 (gdbarch);
771b4502
UW		 150
151 switch (reg_nr)
152 {
153 case SPU_ID_REGNUM:
df4df182 154 return builtin_type (gdbarch)->builtin_uint32;
771b4502
UW		 155
156 case SPU_PC_REGNUM:
0dfff4cb 157 return builtin_type (gdbarch)->builtin_func_ptr;
771b4502
UW		 158
159 case SPU_SP_REGNUM:
0dfff4cb 160 return builtin_type (gdbarch)->builtin_data_ptr;
771b4502 161
23d964e7 162 case SPU_FPSCR_REGNUM:
df4df182 163 return builtin_type (gdbarch)->builtin_uint128;
23d964e7
UW		 164
165 case SPU_SRR0_REGNUM:
df4df182 166 return builtin_type (gdbarch)->builtin_uint32;
23d964e7
UW		 167
168 case SPU_LSLR_REGNUM:
df4df182 169 return builtin_type (gdbarch)->builtin_uint32;
23d964e7
UW		 170
171 case SPU_DECR_REGNUM:
df4df182 172 return builtin_type (gdbarch)->builtin_uint32;
23d964e7
UW		 173
174 case SPU_DECR_STATUS_REGNUM:
df4df182 175 return builtin_type (gdbarch)->builtin_uint32;
23d964e7 176
771b4502
UW		 177 default:
178 internal_error (__FILE__, __LINE__, "invalid regnum");
179 }
180}
181
182/* Pseudo registers for preferred slots - stack pointer. */
183
23d964e7
UW		 184static void
185spu_pseudo_register_read_spu (struct regcache *regcache, const char *regname,
186 gdb_byte *buf)
187{
e17a4113
UW		 188 struct gdbarch *gdbarch = get_regcache_arch (regcache);
189 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 190 gdb_byte reg[32];
191 char annex[32];
192 ULONGEST id;
193
194 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
195 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
196 memset (reg, 0, sizeof reg);
197 target_read (&current_target, TARGET_OBJECT_SPU, annex,
198 reg, 0, sizeof reg);
199
e17a4113 200 store_unsigned_integer (buf, 4, byte_order, strtoulst (reg, NULL, 16));
23d964e7
UW		 201}
202
771b4502
UW		 203static void
204spu_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
205 int regnum, gdb_byte *buf)
206{
207 gdb_byte reg[16];
23d964e7
UW		 208 char annex[32];
209 ULONGEST id;
771b4502
UW		 210
211 switch (regnum)
212 {
213 case SPU_SP_REGNUM:
214 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
215 memcpy (buf, reg, 4);
216 break;
217
23d964e7
UW		 218 case SPU_FPSCR_REGNUM:
219 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
220 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
221 target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
222 break;
223
224 case SPU_SRR0_REGNUM:
225 spu_pseudo_register_read_spu (regcache, "srr0", buf);
226 break;
227
228 case SPU_LSLR_REGNUM:
229 spu_pseudo_register_read_spu (regcache, "lslr", buf);
230 break;
231
232 case SPU_DECR_REGNUM:
233 spu_pseudo_register_read_spu (regcache, "decr", buf);
234 break;
235
236 case SPU_DECR_STATUS_REGNUM:
237 spu_pseudo_register_read_spu (regcache, "decr_status", buf);
238 break;
239
771b4502
UW		 240 default:
241 internal_error (__FILE__, __LINE__, _("invalid regnum"));
242 }
243}
244
23d964e7
UW		 245static void
246spu_pseudo_register_write_spu (struct regcache *regcache, const char *regname,
247 const gdb_byte *buf)
248{
e17a4113
UW		 249 struct gdbarch *gdbarch = get_regcache_arch (regcache);
250 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 251 gdb_byte reg[32];
252 char annex[32];
253 ULONGEST id;
254
255 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
256 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
257 xsnprintf (reg, sizeof reg, "0x%s",
e17a4113 258 phex_nz (extract_unsigned_integer (buf, 4, byte_order), 4));
23d964e7
UW		 259 target_write (&current_target, TARGET_OBJECT_SPU, annex,
260 reg, 0, strlen (reg));
261}
262
771b4502
UW		 263static void
264spu_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
265 int regnum, const gdb_byte *buf)
266{
267 gdb_byte reg[16];
23d964e7
UW		 268 char annex[32];
269 ULONGEST id;
771b4502
UW		 270
271 switch (regnum)
272 {
273 case SPU_SP_REGNUM:
274 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
275 memcpy (reg, buf, 4);
276 regcache_raw_write (regcache, SPU_RAW_SP_REGNUM, reg);
277 break;
278
23d964e7
UW		 279 case SPU_FPSCR_REGNUM:
280 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
281 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
282 target_write (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
283 break;
284
285 case SPU_SRR0_REGNUM:
286 spu_pseudo_register_write_spu (regcache, "srr0", buf);
287 break;
288
289 case SPU_LSLR_REGNUM:
290 spu_pseudo_register_write_spu (regcache, "lslr", buf);
291 break;
292
293 case SPU_DECR_REGNUM:
294 spu_pseudo_register_write_spu (regcache, "decr", buf);
295 break;
296
297 case SPU_DECR_STATUS_REGNUM:
298 spu_pseudo_register_write_spu (regcache, "decr_status", buf);
299 break;
300
771b4502
UW		 301 default:
302 internal_error (__FILE__, __LINE__, _("invalid regnum"));
303 }
304}
305
306/* Value conversion -- access scalar values at the preferred slot. */
307
9acbedc0
UW		 308static struct value *
309spu_value_from_register (struct type *type, int regnum,
310 struct frame_info *frame)
771b4502 311{
9acbedc0
UW		 312 struct value *value = default_value_from_register (type, regnum, frame);
313 int len = TYPE_LENGTH (type);
771b4502 314
9acbedc0
UW		 315 if (regnum < SPU_NUM_GPRS && len < 16)
316 {
317 int preferred_slot = len < 4 ? 4 - len : 0;
318 set_value_offset (value, preferred_slot);
319 }
771b4502 320
9acbedc0 321 return value;
771b4502
UW		 322}
323
324/* Register groups. */
325
326static int
327spu_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
328 struct reggroup *group)
329{
330 /* Registers displayed via 'info regs'. */
331 if (group == general_reggroup)
332 return 1;
333
334 /* Registers displayed via 'info float'. */
335 if (group == float_reggroup)
336 return 0;
337
338 /* Registers that need to be saved/restored in order to
339 push or pop frames. */
340 if (group == save_reggroup || group == restore_reggroup)
341 return 1;
342
343 return default_register_reggroup_p (gdbarch, regnum, group);
344}
345
ff1a52c6
UW		 346
347/* Address handling. */
36acd84e 348
85e747d2
UW		 349static int
350spu_gdbarch_id (struct gdbarch *gdbarch)
351{
352 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
353 int id = tdep->id;
354
355 /* The objfile architecture of a standalone SPU executable does not
356 provide an SPU ID. Retrieve it from the the objfile's relocated
357 address range in this special case. */
358 if (id == -1
359 && symfile_objfile && symfile_objfile->obfd
360 && bfd_get_arch (symfile_objfile->obfd) == bfd_arch_spu
361 && symfile_objfile->sections != symfile_objfile->sections_end)
362 id = SPUADDR_SPU (obj_section_addr (symfile_objfile->sections));
363
364 return id;
365}
366
367static ULONGEST
368spu_lslr (int id)
369{
370 gdb_byte buf[32];
371 char annex[32];
372
373 if (id == -1)
374 return SPU_LS_SIZE - 1;
375
376 xsnprintf (annex, sizeof annex, "%d/lslr", id);
377 memset (buf, 0, sizeof buf);
378 target_read (&current_target, TARGET_OBJECT_SPU, annex,
379 buf, 0, sizeof buf);
380
381 return strtoulst (buf, NULL, 16);
382}
383
ff1a52c6
UW		 384static int
385spu_address_class_type_flags (int byte_size, int dwarf2_addr_class)
386{
387 if (dwarf2_addr_class == 1)
388 return TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1;
389 else
390 return 0;
391}
392
393static const char *
394spu_address_class_type_flags_to_name (struct gdbarch *gdbarch, int type_flags)
395{
396 if (type_flags & TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1)
397 return "__ea";
398 else
399 return NULL;
400}
401
402static int
403spu_address_class_name_to_type_flags (struct gdbarch *gdbarch,
404 const char *name, int *type_flags_ptr)
405{
406 if (strcmp (name, "__ea") == 0)
407 {
408 *type_flags_ptr = TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1;
409 return 1;
410 }
411 else
412 return 0;
413}
414
85e747d2
UW		 415static void
416spu_address_to_pointer (struct gdbarch *gdbarch,
417 struct type *type, gdb_byte *buf, CORE_ADDR addr)
418{
419 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
420 store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order,
421 SPUADDR_ADDR (addr));
422}
423
36acd84e 424static CORE_ADDR
9898f801
UW		 425spu_pointer_to_address (struct gdbarch *gdbarch,
426 struct type *type, const gdb_byte *buf)
36acd84e 427{
85e747d2
UW		 428 int id = spu_gdbarch_id (gdbarch);
429 ULONGEST lslr = spu_lslr (id);
e17a4113
UW		 430 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
431 ULONGEST addr
432 = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order);
36acd84e 433
ff1a52c6
UW		 434 /* Do not convert __ea pointers. */
435 if (TYPE_ADDRESS_CLASS_1 (type))
436 return addr;
437
85e747d2 438 return addr? SPUADDR (id, addr & lslr) : 0;
36acd84e
UW		 439}
440
441static CORE_ADDR
442spu_integer_to_address (struct gdbarch *gdbarch,
443 struct type *type, const gdb_byte *buf)
444{
85e747d2
UW		 445 int id = spu_gdbarch_id (gdbarch);
446 ULONGEST lslr = spu_lslr (id);
36acd84e 447 ULONGEST addr = unpack_long (type, buf);
36acd84e 448
85e747d2 449 return SPUADDR (id, addr & lslr);
36acd84e
UW		 450}
451
771b4502
UW		 452
453/* Decoding SPU instructions. */
454
455enum
456 {
457 op_lqd = 0x34,
458 op_lqx = 0x3c4,
459 op_lqa = 0x61,
460 op_lqr = 0x67,
461 op_stqd = 0x24,
462 op_stqx = 0x144,
463 op_stqa = 0x41,
464 op_stqr = 0x47,
465
466 op_il = 0x081,
467 op_ila = 0x21,
468 op_a = 0x0c0,
469 op_ai = 0x1c,
470
471 op_selb = 0x4,
472
473 op_br = 0x64,
474 op_bra = 0x60,
475 op_brsl = 0x66,
476 op_brasl = 0x62,
477 op_brnz = 0x42,
478 op_brz = 0x40,
479 op_brhnz = 0x46,
480 op_brhz = 0x44,
481 op_bi = 0x1a8,
482 op_bisl = 0x1a9,
483 op_biz = 0x128,
484 op_binz = 0x129,
485 op_bihz = 0x12a,
486 op_bihnz = 0x12b,
487 };
488
489static int
490is_rr (unsigned int insn, int op, int *rt, int *ra, int *rb)
491{
492 if ((insn >> 21) == op)
493 {
494 *rt = insn & 127;
495 *ra = (insn >> 7) & 127;
496 *rb = (insn >> 14) & 127;
497 return 1;
498 }
499
500 return 0;
501}
502
503static int
504is_rrr (unsigned int insn, int op, int *rt, int *ra, int *rb, int *rc)
505{
506 if ((insn >> 28) == op)
507 {
508 *rt = (insn >> 21) & 127;
509 *ra = (insn >> 7) & 127;
510 *rb = (insn >> 14) & 127;
511 *rc = insn & 127;
512 return 1;
513 }
514
515 return 0;
516}
517
518static int
519is_ri7 (unsigned int insn, int op, int *rt, int *ra, int *i7)
520{
521 if ((insn >> 21) == op)
522 {
523 *rt = insn & 127;
524 *ra = (insn >> 7) & 127;
525 *i7 = (((insn >> 14) & 127) ^ 0x40) - 0x40;
526 return 1;
527 }
528
529 return 0;
530}
531
532static int
533is_ri10 (unsigned int insn, int op, int *rt, int *ra, int *i10)
534{
535 if ((insn >> 24) == op)
536 {
537 *rt = insn & 127;
538 *ra = (insn >> 7) & 127;
539 *i10 = (((insn >> 14) & 0x3ff) ^ 0x200) - 0x200;
540 return 1;
541 }
542
543 return 0;
544}
545
546static int
547is_ri16 (unsigned int insn, int op, int *rt, int *i16)
548{
549 if ((insn >> 23) == op)
550 {
551 *rt = insn & 127;
552 *i16 = (((insn >> 7) & 0xffff) ^ 0x8000) - 0x8000;
553 return 1;
554 }
555
556 return 0;
557}
558
559static int
560is_ri18 (unsigned int insn, int op, int *rt, int *i18)
561{
562 if ((insn >> 25) == op)
563 {
564 *rt = insn & 127;
565 *i18 = (((insn >> 7) & 0x3ffff) ^ 0x20000) - 0x20000;
566 return 1;
567 }
568
569 return 0;
570}
571
572static int
573is_branch (unsigned int insn, int *offset, int *reg)
574{
575 int rt, i7, i16;
576
577 if (is_ri16 (insn, op_br, &rt, &i16)
578 || is_ri16 (insn, op_brsl, &rt, &i16)
579 || is_ri16 (insn, op_brnz, &rt, &i16)
580 || is_ri16 (insn, op_brz, &rt, &i16)
581 || is_ri16 (insn, op_brhnz, &rt, &i16)
582 || is_ri16 (insn, op_brhz, &rt, &i16))
583 {
584 *reg = SPU_PC_REGNUM;
585 *offset = i16 << 2;
586 return 1;
587 }
588
589 if (is_ri16 (insn, op_bra, &rt, &i16)
590 || is_ri16 (insn, op_brasl, &rt, &i16))
591 {
592 *reg = -1;
593 *offset = i16 << 2;
594 return 1;
595 }
596
597 if (is_ri7 (insn, op_bi, &rt, reg, &i7)
598 || is_ri7 (insn, op_bisl, &rt, reg, &i7)
599 || is_ri7 (insn, op_biz, &rt, reg, &i7)
600 || is_ri7 (insn, op_binz, &rt, reg, &i7)
601 || is_ri7 (insn, op_bihz, &rt, reg, &i7)
602 || is_ri7 (insn, op_bihnz, &rt, reg, &i7))
603 {
604 *offset = 0;
605 return 1;
606 }
607
608 return 0;
609}
610
611
612/* Prolog parsing. */
613
614struct spu_prologue_data
615 {
616 /* Stack frame size. -1 if analysis was unsuccessful. */
617 int size;
618
619 /* How to find the CFA. The CFA is equal to SP at function entry. */
620 int cfa_reg;
621 int cfa_offset;
622
623 /* Offset relative to CFA where a register is saved. -1 if invalid. */
624 int reg_offset[SPU_NUM_GPRS];
625 };
626
627static CORE_ADDR
e17a4113
UW		 628spu_analyze_prologue (struct gdbarch *gdbarch,
629 CORE_ADDR start_pc, CORE_ADDR end_pc,
771b4502
UW		 630 struct spu_prologue_data *data)
631{
e17a4113 632 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
771b4502
UW		 633 int found_sp = 0;
634 int found_fp = 0;
635 int found_lr = 0;
ce50d78b 636 int found_bc = 0;
771b4502
UW		 637 int reg_immed[SPU_NUM_GPRS];
638 gdb_byte buf[16];
639 CORE_ADDR prolog_pc = start_pc;
640 CORE_ADDR pc;
641 int i;
642
643
644 /* Initialize DATA to default values. */
645 data->size = -1;
646
647 data->cfa_reg = SPU_RAW_SP_REGNUM;
648 data->cfa_offset = 0;
649
650 for (i = 0; i < SPU_NUM_GPRS; i++)
651 data->reg_offset[i] = -1;
652
653 /* Set up REG_IMMED array. This is non-zero for a register if we know its
654 preferred slot currently holds this immediate value. */
655 for (i = 0; i < SPU_NUM_GPRS; i++)
656 reg_immed[i] = 0;
657
658 /* Scan instructions until the first branch.
659
660 The following instructions are important prolog components:
661
662 - The first instruction to set up the stack pointer.
663 - The first instruction to set up the frame pointer.
664 - The first instruction to save the link register.
ce50d78b 665 - The first instruction to save the backchain.
771b4502 666
ce50d78b 667 We return the instruction after the latest of these four,
771b4502
UW		 668 or the incoming PC if none is found. The first instruction
669 to set up the stack pointer also defines the frame size.
670
671 Note that instructions saving incoming arguments to their stack
672 slots are not counted as important, because they are hard to
673 identify with certainty. This should not matter much, because
674 arguments are relevant only in code compiled with debug data,
675 and in such code the GDB core will advance until the first source
676 line anyway, using SAL data.
677
678 For purposes of stack unwinding, we analyze the following types
679 of instructions in addition:
680
681 - Any instruction adding to the current frame pointer.
682 - Any instruction loading an immediate constant into a register.
683 - Any instruction storing a register onto the stack.
684
685 These are used to compute the CFA and REG_OFFSET output. */
686
687 for (pc = start_pc; pc < end_pc; pc += 4)
688 {
689 unsigned int insn;
690 int rt, ra, rb, rc, immed;
691
692 if (target_read_memory (pc, buf, 4))
693 break;
e17a4113 694 insn = extract_unsigned_integer (buf, 4, byte_order);
771b4502
UW		 695
696 /* AI is the typical instruction to set up a stack frame.
697 It is also used to initialize the frame pointer. */
698 if (is_ri10 (insn, op_ai, &rt, &ra, &immed))
699 {
700 if (rt == data->cfa_reg && ra == data->cfa_reg)
701 data->cfa_offset -= immed;
702
703 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
704 && !found_sp)
705 {
706 found_sp = 1;
707 prolog_pc = pc + 4;
708
709 data->size = -immed;
710 }
711 else if (rt == SPU_FP_REGNUM && ra == SPU_RAW_SP_REGNUM
712 && !found_fp)
713 {
714 found_fp = 1;
715 prolog_pc = pc + 4;
716
717 data->cfa_reg = SPU_FP_REGNUM;
718 data->cfa_offset -= immed;
719 }
720 }
721
722 /* A is used to set up stack frames of size >= 512 bytes.
723 If we have tracked the contents of the addend register,
724 we can handle this as well. */
725 else if (is_rr (insn, op_a, &rt, &ra, &rb))
726 {
727 if (rt == data->cfa_reg && ra == data->cfa_reg)
728 {
729 if (reg_immed[rb] != 0)
730 data->cfa_offset -= reg_immed[rb];
731 else
732 data->cfa_reg = -1; /* We don't know the CFA any more. */
733 }
734
735 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
736 && !found_sp)
737 {
738 found_sp = 1;
739 prolog_pc = pc + 4;
740
741 if (reg_immed[rb] != 0)
742 data->size = -reg_immed[rb];
743 }
744 }
745
746 /* We need to track IL and ILA used to load immediate constants
747 in case they are later used as input to an A instruction. */
748 else if (is_ri16 (insn, op_il, &rt, &immed))
749 {
750 reg_immed[rt] = immed;
12102450
UW		 751
752 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
753 found_sp = 1;
771b4502
UW		 754 }
755
756 else if (is_ri18 (insn, op_ila, &rt, &immed))
757 {
758 reg_immed[rt] = immed & 0x3ffff;
12102450
UW		 759
760 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
761 found_sp = 1;
771b4502
UW		 762 }
763
764 /* STQD is used to save registers to the stack. */
765 else if (is_ri10 (insn, op_stqd, &rt, &ra, &immed))
766 {
767 if (ra == data->cfa_reg)
768 data->reg_offset[rt] = data->cfa_offset - (immed << 4);
769
770 if (ra == data->cfa_reg && rt == SPU_LR_REGNUM
771 && !found_lr)
772 {
773 found_lr = 1;
774 prolog_pc = pc + 4;
775 }
ce50d78b
UW		 776
777 if (ra == SPU_RAW_SP_REGNUM
778 && (found_sp? immed == 0 : rt == SPU_RAW_SP_REGNUM)
779 && !found_bc)
780 {
781 found_bc = 1;
782 prolog_pc = pc + 4;
783 }
771b4502
UW		 784 }
785
786 /* _start uses SELB to set up the stack pointer. */
787 else if (is_rrr (insn, op_selb, &rt, &ra, &rb, &rc))
788 {
789 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
790 found_sp = 1;
791 }
792
793 /* We terminate if we find a branch. */
794 else if (is_branch (insn, &immed, &ra))
795 break;
796 }
797
798
799 /* If we successfully parsed until here, and didn't find any instruction
800 modifying SP, we assume we have a frameless function. */
801 if (!found_sp)
802 data->size = 0;
803
804 /* Return cooked instead of raw SP. */
805 if (data->cfa_reg == SPU_RAW_SP_REGNUM)
806 data->cfa_reg = SPU_SP_REGNUM;
807
808 return prolog_pc;
809}
810
811/* Return the first instruction after the prologue starting at PC. */
812static CORE_ADDR
6093d2eb 813spu_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
771b4502
UW		 814{
815 struct spu_prologue_data data;
e17a4113 816 return spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data);
771b4502
UW		 817}
818
819/* Return the frame pointer in use at address PC. */
820static void
a54fba4c
MD		 821spu_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc,
822 int *reg, LONGEST *offset)
771b4502
UW		 823{
824 struct spu_prologue_data data;
e17a4113 825 spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data);
771b4502
UW		 826
827 if (data.size != -1 && data.cfa_reg != -1)
828 {
829 /* The 'frame pointer' address is CFA minus frame size. */
830 *reg = data.cfa_reg;
831 *offset = data.cfa_offset - data.size;
832 }
833 else
834 {
835 /* ??? We don't really know ... */
836 *reg = SPU_SP_REGNUM;
837 *offset = 0;
838 }
839}
840
fe5febed
UW		 841/* Return true if we are in the function's epilogue, i.e. after the
842 instruction that destroyed the function's stack frame.
843
844 1) scan forward from the point of execution:
845 a) If you find an instruction that modifies the stack pointer
846 or transfers control (except a return), execution is not in
847 an epilogue, return.
848 b) Stop scanning if you find a return instruction or reach the
849 end of the function or reach the hard limit for the size of
850 an epilogue.
851 2) scan backward from the point of execution:
852 a) If you find an instruction that modifies the stack pointer,
853 execution *is* in an epilogue, return.
854 b) Stop scanning if you reach an instruction that transfers
855 control or the beginning of the function or reach the hard
856 limit for the size of an epilogue. */
857
858static int
859spu_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
860{
e17a4113 861 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
fe5febed
UW		 862 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
863 bfd_byte buf[4];
864 unsigned int insn;
865 int rt, ra, rb, rc, immed;
866
867 /* Find the search limits based on function boundaries and hard limit.
868 We assume the epilogue can be up to 64 instructions long. */
869
870 const int spu_max_epilogue_size = 64 * 4;
871
872 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
873 return 0;
874
875 if (pc - func_start < spu_max_epilogue_size)
876 epilogue_start = func_start;
877 else
878 epilogue_start = pc - spu_max_epilogue_size;
879
880 if (func_end - pc < spu_max_epilogue_size)
881 epilogue_end = func_end;
882 else
883 epilogue_end = pc + spu_max_epilogue_size;
884
885 /* Scan forward until next 'bi $0'. */
886
887 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += 4)
888 {
889 if (target_read_memory (scan_pc, buf, 4))
890 return 0;
e17a4113 891 insn = extract_unsigned_integer (buf, 4, byte_order);
fe5febed
UW		 892
893 if (is_branch (insn, &immed, &ra))
894 {
895 if (immed == 0 && ra == SPU_LR_REGNUM)
896 break;
897
898 return 0;
899 }
900
901 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
902 || is_rr (insn, op_a, &rt, &ra, &rb)
903 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
904 {
905 if (rt == SPU_RAW_SP_REGNUM)
906 return 0;
907 }
908 }
909
910 if (scan_pc >= epilogue_end)
911 return 0;
912
913 /* Scan backward until adjustment to stack pointer (R1). */
914
915 for (scan_pc = pc - 4; scan_pc >= epilogue_start; scan_pc -= 4)
916 {
917 if (target_read_memory (scan_pc, buf, 4))
918 return 0;
e17a4113 919 insn = extract_unsigned_integer (buf, 4, byte_order);
fe5febed
UW		 920
921 if (is_branch (insn, &immed, &ra))
922 return 0;
923
924 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
925 || is_rr (insn, op_a, &rt, &ra, &rb)
926 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
927 {
928 if (rt == SPU_RAW_SP_REGNUM)
929 return 1;
930 }
931 }
932
933 return 0;
934}
935
936
771b4502
UW		 937/* Normal stack frames. */
938
939struct spu_unwind_cache
940{
941 CORE_ADDR func;
942 CORE_ADDR frame_base;
943 CORE_ADDR local_base;
944
945 struct trad_frame_saved_reg *saved_regs;
946};
947
948static struct spu_unwind_cache *
8d998b8f 949spu_frame_unwind_cache (struct frame_info *this_frame,
771b4502
UW		 950 void **this_prologue_cache)
951{
e17a4113 952 struct gdbarch *gdbarch = get_frame_arch (this_frame);
85e747d2 953 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 954 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
771b4502
UW		 955 struct spu_unwind_cache *info;
956 struct spu_prologue_data data;
85e747d2 957 CORE_ADDR id = tdep->id;
dcf52cd8 958 gdb_byte buf[16];
771b4502
UW		 959
960 if (*this_prologue_cache)
961 return *this_prologue_cache;
962
963 info = FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache);
964 *this_prologue_cache = info;
8d998b8f 965 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
771b4502
UW		 966 info->frame_base = 0;
967 info->local_base = 0;
968
969 /* Find the start of the current function, and analyze its prologue. */
8d998b8f 970 info->func = get_frame_func (this_frame);
771b4502
UW		 971 if (info->func == 0)
972 {
973 /* Fall back to using the current PC as frame ID. */
8d998b8f 974 info->func = get_frame_pc (this_frame);
771b4502
UW		 975 data.size = -1;
976 }
977 else
e17a4113
UW		 978 spu_analyze_prologue (gdbarch, info->func, get_frame_pc (this_frame),
979 &data);
771b4502
UW		 980
981 /* If successful, use prologue analysis data. */
982 if (data.size != -1 && data.cfa_reg != -1)
983 {
984 CORE_ADDR cfa;
985 int i;
771b4502
UW		 986
987 /* Determine CFA via unwound CFA_REG plus CFA_OFFSET. */
8d998b8f 988 get_frame_register (this_frame, data.cfa_reg, buf);
e17a4113 989 cfa = extract_unsigned_integer (buf, 4, byte_order) + data.cfa_offset;
85e747d2 990 cfa = SPUADDR (id, cfa);
771b4502
UW		 991
992 /* Call-saved register slots. */
993 for (i = 0; i < SPU_NUM_GPRS; i++)
994 if (i == SPU_LR_REGNUM
995 || (i >= SPU_SAVED1_REGNUM && i <= SPU_SAVEDN_REGNUM))
996 if (data.reg_offset[i] != -1)
997 info->saved_regs[i].addr = cfa - data.reg_offset[i];
998
771b4502
UW		 999 /* Frame bases. */
1000 info->frame_base = cfa;
1001 info->local_base = cfa - data.size;
1002 }
1003
1004 /* Otherwise, fall back to reading the backchain link. */
1005 else
1006 {
cdc9523a
UW		 1007 CORE_ADDR reg;
1008 LONGEST backchain;
1009 int status;
771b4502
UW		 1010
1011 /* Get the backchain. */
8d998b8f 1012 reg = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
85e747d2
UW		 1013 status = safe_read_memory_integer (SPUADDR (id, reg), 4, byte_order,
1014 &backchain);
771b4502
UW		 1015
1016 /* A zero backchain terminates the frame chain. Also, sanity
1017 check against the local store size limit. */
cdc9523a 1018 if (status && backchain > 0 && backchain < SPU_LS_SIZE)
771b4502
UW		 1019 {
1020 /* Assume the link register is saved into its slot. */
1021 if (backchain + 16 < SPU_LS_SIZE)
85e747d2 1022 info->saved_regs[SPU_LR_REGNUM].addr = SPUADDR (id, backchain + 16);
771b4502 1023
771b4502 1024 /* Frame bases. */
85e747d2
UW		 1025 info->frame_base = SPUADDR (id, backchain);
1026 info->local_base = SPUADDR (id, reg);
771b4502
UW		 1027 }
1028 }
dcf52cd8 1029
c4891da7
UW		 1030 /* If we didn't find a frame, we cannot determine SP / return address. */
1031 if (info->frame_base == 0)
1032 return info;
1033
dcf52cd8 1034 /* The previous SP is equal to the CFA. */
85e747d2
UW		 1035 trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM,
1036 SPUADDR_ADDR (info->frame_base));
dcf52cd8 1037
0a44cb36
UW		 1038 /* Read full contents of the unwound link register in order to
1039 be able to determine the return address. */
dcf52cd8
UW		 1040 if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM))
1041 target_read_memory (info->saved_regs[SPU_LR_REGNUM].addr, buf, 16);
1042 else
8d998b8f 1043 get_frame_register (this_frame, SPU_LR_REGNUM, buf);
dcf52cd8 1044
0a44cb36
UW		 1045 /* Normally, the return address is contained in the slot 0 of the
1046 link register, and slots 1-3 are zero. For an overlay return,
1047 slot 0 contains the address of the overlay manager return stub,
1048 slot 1 contains the partition number of the overlay section to
1049 be returned to, and slot 2 contains the return address within
1050 that section. Return the latter address in that case. */
e17a4113 1051 if (extract_unsigned_integer (buf + 8, 4, byte_order) != 0)
dcf52cd8 1052 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
e17a4113 1053 extract_unsigned_integer (buf + 8, 4, byte_order));
dcf52cd8
UW		 1054 else
1055 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
e17a4113 1056 extract_unsigned_integer (buf, 4, byte_order));
771b4502
UW		 1057
1058 return info;
1059}
1060
1061static void
8d998b8f 1062spu_frame_this_id (struct frame_info *this_frame,
771b4502
UW		 1063 void **this_prologue_cache, struct frame_id *this_id)
1064{
1065 struct spu_unwind_cache *info =
8d998b8f 1066 spu_frame_unwind_cache (this_frame, this_prologue_cache);
771b4502
UW		 1067
1068 if (info->frame_base == 0)
1069 return;
1070
1071 *this_id = frame_id_build (info->frame_base, info->func);
1072}
1073
8d998b8f
UW		 1074static struct value *
1075spu_frame_prev_register (struct frame_info *this_frame,
1076 void **this_prologue_cache, int regnum)
771b4502
UW		 1077{
1078 struct spu_unwind_cache *info
8d998b8f 1079 = spu_frame_unwind_cache (this_frame, this_prologue_cache);
771b4502
UW		 1080
1081 /* Special-case the stack pointer. */
1082 if (regnum == SPU_RAW_SP_REGNUM)
1083 regnum = SPU_SP_REGNUM;
1084
8d998b8f 1085 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
771b4502
UW		 1086}
1087
1088static const struct frame_unwind spu_frame_unwind = {
1089 NORMAL_FRAME,
1090 spu_frame_this_id,
8d998b8f
UW		 1091 spu_frame_prev_register,
1092 NULL,
1093 default_frame_sniffer
771b4502
UW		 1094};
1095
771b4502 1096static CORE_ADDR
8d998b8f 1097spu_frame_base_address (struct frame_info *this_frame, void **this_cache)
771b4502
UW		 1098{
1099 struct spu_unwind_cache *info
8d998b8f 1100 = spu_frame_unwind_cache (this_frame, this_cache);
771b4502
UW		 1101 return info->local_base;
1102}
1103
1104static const struct frame_base spu_frame_base = {
1105 &spu_frame_unwind,
1106 spu_frame_base_address,
1107 spu_frame_base_address,
1108 spu_frame_base_address
1109};
1110
1111static CORE_ADDR
1112spu_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1113{
85e747d2 1114 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
118dfbaf
UW		 1115 CORE_ADDR pc = frame_unwind_register_unsigned (next_frame, SPU_PC_REGNUM);
1116 /* Mask off interrupt enable bit. */
85e747d2 1117 return SPUADDR (tdep->id, pc & -4);
771b4502
UW		 1118}
1119
1120static CORE_ADDR
1121spu_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1122{
85e747d2
UW		 1123 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1124 CORE_ADDR sp = frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM);
1125 return SPUADDR (tdep->id, sp);
771b4502
UW		 1126}
1127
118dfbaf 1128static CORE_ADDR
61a1198a 1129spu_read_pc (struct regcache *regcache)
118dfbaf 1130{
85e747d2 1131 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
61a1198a
UW		 1132 ULONGEST pc;
1133 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &pc);
118dfbaf 1134 /* Mask off interrupt enable bit. */
85e747d2 1135 return SPUADDR (tdep->id, pc & -4);
118dfbaf
UW		 1136}
1137
1138static void
61a1198a 1139spu_write_pc (struct regcache *regcache, CORE_ADDR pc)
118dfbaf
UW		 1140{
1141 /* Keep interrupt enabled state unchanged. */
61a1198a
UW		 1142 ULONGEST old_pc;
1143 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &old_pc);
1144 regcache_cooked_write_unsigned (regcache, SPU_PC_REGNUM,
85e747d2 1145 (SPUADDR_ADDR (pc) & -4) | (old_pc & 3));
118dfbaf
UW		 1146}
1147
771b4502 1148
cc5f0d61
UW		 1149/* Cell/B.E. cross-architecture unwinder support. */
1150
1151struct spu2ppu_cache
1152{
1153 struct frame_id frame_id;
1154 struct regcache *regcache;
1155};
1156
1157static struct gdbarch *
1158spu2ppu_prev_arch (struct frame_info *this_frame, void **this_cache)
1159{
1160 struct spu2ppu_cache *cache = *this_cache;
1161 return get_regcache_arch (cache->regcache);
1162}
1163
1164static void
1165spu2ppu_this_id (struct frame_info *this_frame,
1166 void **this_cache, struct frame_id *this_id)
1167{
1168 struct spu2ppu_cache *cache = *this_cache;
1169 *this_id = cache->frame_id;
1170}
1171
1172static struct value *
1173spu2ppu_prev_register (struct frame_info *this_frame,
1174 void **this_cache, int regnum)
1175{
1176 struct spu2ppu_cache *cache = *this_cache;
1177 struct gdbarch *gdbarch = get_regcache_arch (cache->regcache);
1178 gdb_byte *buf;
1179
1180 buf = alloca (register_size (gdbarch, regnum));
1181 regcache_cooked_read (cache->regcache, regnum, buf);
1182 return frame_unwind_got_bytes (this_frame, regnum, buf);
1183}
1184
1185static int
1186spu2ppu_sniffer (const struct frame_unwind *self,
1187 struct frame_info *this_frame, void **this_prologue_cache)
1188{
1189 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1190 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1191 CORE_ADDR base, func, backchain;
1192 gdb_byte buf[4];
1193
1194 if (gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_spu)
1195 return 0;
1196
1197 base = get_frame_sp (this_frame);
1198 func = get_frame_pc (this_frame);
1199 if (target_read_memory (base, buf, 4))
1200 return 0;
1201 backchain = extract_unsigned_integer (buf, 4, byte_order);
1202
1203 if (!backchain)
1204 {
1205 struct frame_info *fi;
1206
1207 struct spu2ppu_cache *cache
1208 = FRAME_OBSTACK_CALLOC (1, struct spu2ppu_cache);
1209
1210 cache->frame_id = frame_id_build (base + 16, func);
1211
1212 for (fi = get_next_frame (this_frame); fi; fi = get_next_frame (fi))
1213 if (gdbarch_bfd_arch_info (get_frame_arch (fi))->arch != bfd_arch_spu)
1214 break;
1215
1216 if (fi)
1217 {
1218 cache->regcache = frame_save_as_regcache (fi);
1219 *this_prologue_cache = cache;
1220 return 1;
1221 }
1222 else
1223 {
1224 struct regcache *regcache;
1225 regcache = get_thread_arch_regcache (inferior_ptid, target_gdbarch);
1226 cache->regcache = regcache_dup (regcache);
1227 *this_prologue_cache = cache;
1228 return 1;
1229 }
1230 }
1231
1232 return 0;
1233}
1234
1235static void
1236spu2ppu_dealloc_cache (struct frame_info *self, void *this_cache)
1237{
1238 struct spu2ppu_cache *cache = this_cache;
1239 regcache_xfree (cache->regcache);
1240}
1241
1242static const struct frame_unwind spu2ppu_unwind = {
1243 ARCH_FRAME,
1244 spu2ppu_this_id,
1245 spu2ppu_prev_register,
1246 NULL,
1247 spu2ppu_sniffer,
1248 spu2ppu_dealloc_cache,
1249 spu2ppu_prev_arch,
1250};
1251
1252
771b4502
UW		 1253/* Function calling convention. */
1254
7b3dc0b7
UW		 1255static CORE_ADDR
1256spu_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1257{
1258 return sp & ~15;
1259}
1260
87805e63
UW		 1261static CORE_ADDR
1262spu_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
1263 struct value **args, int nargs, struct type *value_type,
1264 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
1265 struct regcache *regcache)
1266{
1267 /* Allocate space sufficient for a breakpoint, keeping the stack aligned. */
1268 sp = (sp - 4) & ~15;
1269 /* Store the address of that breakpoint */
1270 *bp_addr = sp;
1271 /* The call starts at the callee's entry point. */
1272 *real_pc = funaddr;
1273
1274 return sp;
1275}
1276
771b4502
UW		 1277static int
1278spu_scalar_value_p (struct type *type)
1279{
1280 switch (TYPE_CODE (type))
1281 {
1282 case TYPE_CODE_INT:
1283 case TYPE_CODE_ENUM:
1284 case TYPE_CODE_RANGE:
1285 case TYPE_CODE_CHAR:
1286 case TYPE_CODE_BOOL:
1287 case TYPE_CODE_PTR:
1288 case TYPE_CODE_REF:
1289 return TYPE_LENGTH (type) <= 16;
1290
1291 default:
1292 return 0;
1293 }
1294}
1295
1296static void
1297spu_value_to_regcache (struct regcache *regcache, int regnum,
1298 struct type *type, const gdb_byte *in)
1299{
1300 int len = TYPE_LENGTH (type);
1301
1302 if (spu_scalar_value_p (type))
1303 {
1304 int preferred_slot = len < 4 ? 4 - len : 0;
1305 regcache_cooked_write_part (regcache, regnum, preferred_slot, len, in);
1306 }
1307 else
1308 {
1309 while (len >= 16)
1310 {
1311 regcache_cooked_write (regcache, regnum++, in);
1312 in += 16;
1313 len -= 16;
1314 }
1315
1316 if (len > 0)
1317 regcache_cooked_write_part (regcache, regnum, 0, len, in);
1318 }
1319}
1320
1321static void
1322spu_regcache_to_value (struct regcache *regcache, int regnum,
1323 struct type *type, gdb_byte *out)
1324{
1325 int len = TYPE_LENGTH (type);
1326
1327 if (spu_scalar_value_p (type))
1328 {
1329 int preferred_slot = len < 4 ? 4 - len : 0;
1330 regcache_cooked_read_part (regcache, regnum, preferred_slot, len, out);
1331 }
1332 else
1333 {
1334 while (len >= 16)
1335 {
1336 regcache_cooked_read (regcache, regnum++, out);
1337 out += 16;
1338 len -= 16;
1339 }
1340
1341 if (len > 0)
1342 regcache_cooked_read_part (regcache, regnum, 0, len, out);
1343 }
1344}
1345
1346static CORE_ADDR
1347spu_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1348 struct regcache *regcache, CORE_ADDR bp_addr,
1349 int nargs, struct value **args, CORE_ADDR sp,
1350 int struct_return, CORE_ADDR struct_addr)
1351{
e17a4113 1352 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
9ff3afda 1353 CORE_ADDR sp_delta;
771b4502
UW		 1354 int i;
1355 int regnum = SPU_ARG1_REGNUM;
1356 int stack_arg = -1;
1357 gdb_byte buf[16];
1358
1359 /* Set the return address. */
1360 memset (buf, 0, sizeof buf);
85e747d2 1361 store_unsigned_integer (buf, 4, byte_order, SPUADDR_ADDR (bp_addr));
771b4502
UW		 1362 regcache_cooked_write (regcache, SPU_LR_REGNUM, buf);
1363
1364 /* If STRUCT_RETURN is true, then the struct return address (in
1365 STRUCT_ADDR) will consume the first argument-passing register.
1366 Both adjust the register count and store that value. */
1367 if (struct_return)
1368 {
1369 memset (buf, 0, sizeof buf);
85e747d2 1370 store_unsigned_integer (buf, 4, byte_order, SPUADDR_ADDR (struct_addr));
771b4502
UW		 1371 regcache_cooked_write (regcache, regnum++, buf);
1372 }
1373
1374 /* Fill in argument registers. */
1375 for (i = 0; i < nargs; i++)
1376 {
1377 struct value *arg = args[i];
1378 struct type *type = check_typedef (value_type (arg));
1379 const gdb_byte *contents = value_contents (arg);
1380 int len = TYPE_LENGTH (type);
1381 int n_regs = align_up (len, 16) / 16;
1382
1383 /* If the argument doesn't wholly fit into registers, it and
1384 all subsequent arguments go to the stack. */
1385 if (regnum + n_regs - 1 > SPU_ARGN_REGNUM)
1386 {
1387 stack_arg = i;
1388 break;
1389 }
1390
1391 spu_value_to_regcache (regcache, regnum, type, contents);
1392 regnum += n_regs;
1393 }
1394
1395 /* Overflow arguments go to the stack. */
1396 if (stack_arg != -1)
1397 {
1398 CORE_ADDR ap;
1399
1400 /* Allocate all required stack size. */
1401 for (i = stack_arg; i < nargs; i++)
1402 {
1403 struct type *type = check_typedef (value_type (args[i]));
1404 sp -= align_up (TYPE_LENGTH (type), 16);
1405 }
1406
1407 /* Fill in stack arguments. */
1408 ap = sp;
1409 for (i = stack_arg; i < nargs; i++)
1410 {
1411 struct value *arg = args[i];
1412 struct type *type = check_typedef (value_type (arg));
1413 int len = TYPE_LENGTH (type);
1414 int preferred_slot;
1415
1416 if (spu_scalar_value_p (type))
1417 preferred_slot = len < 4 ? 4 - len : 0;
1418 else
1419 preferred_slot = 0;
1420
1421 target_write_memory (ap + preferred_slot, value_contents (arg), len);
1422 ap += align_up (TYPE_LENGTH (type), 16);
1423 }
1424 }
1425
1426 /* Allocate stack frame header. */
1427 sp -= 32;
1428
ee82e879
UW		 1429 /* Store stack back chain. */
1430 regcache_cooked_read (regcache, SPU_RAW_SP_REGNUM, buf);
1431 target_write_memory (sp, buf, 16);
1432
9ff3afda 1433 /* Finally, update all slots of the SP register. */
e17a4113 1434 sp_delta = sp - extract_unsigned_integer (buf, 4, byte_order);
9ff3afda
UW		 1435 for (i = 0; i < 4; i++)
1436 {
e17a4113
UW		 1437 CORE_ADDR sp_slot = extract_unsigned_integer (buf + 4*i, 4, byte_order);
1438 store_unsigned_integer (buf + 4*i, 4, byte_order, sp_slot + sp_delta);
9ff3afda
UW		 1439 }
1440 regcache_cooked_write (regcache, SPU_RAW_SP_REGNUM, buf);
771b4502
UW		 1441
1442 return sp;
1443}
1444
1445static struct frame_id
8d998b8f 1446spu_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
771b4502 1447{
85e747d2 1448 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8d998b8f
UW		 1449 CORE_ADDR pc = get_frame_register_unsigned (this_frame, SPU_PC_REGNUM);
1450 CORE_ADDR sp = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
85e747d2 1451 return frame_id_build (SPUADDR (tdep->id, sp), SPUADDR (tdep->id, pc & -4));
771b4502
UW		 1452}
1453
1454/* Function return value access. */
1455
1456static enum return_value_convention
c055b101
CV		 1457spu_return_value (struct gdbarch *gdbarch, struct type *func_type,
1458 struct type *type, struct regcache *regcache,
1459 gdb_byte *out, const gdb_byte *in)
771b4502
UW		 1460{
1461 enum return_value_convention rvc;
1462
1463 if (TYPE_LENGTH (type) <= (SPU_ARGN_REGNUM - SPU_ARG1_REGNUM + 1) * 16)
1464 rvc = RETURN_VALUE_REGISTER_CONVENTION;
1465 else
1466 rvc = RETURN_VALUE_STRUCT_CONVENTION;
1467
1468 if (in)
1469 {
1470 switch (rvc)
1471 {
1472 case RETURN_VALUE_REGISTER_CONVENTION:
1473 spu_value_to_regcache (regcache, SPU_ARG1_REGNUM, type, in);
1474 break;
1475
1476 case RETURN_VALUE_STRUCT_CONVENTION:
1477 error ("Cannot set function return value.");
1478 break;
1479 }
1480 }
1481 else if (out)
1482 {
1483 switch (rvc)
1484 {
1485 case RETURN_VALUE_REGISTER_CONVENTION:
1486 spu_regcache_to_value (regcache, SPU_ARG1_REGNUM, type, out);
1487 break;
1488
1489 case RETURN_VALUE_STRUCT_CONVENTION:
1490 error ("Function return value unknown.");
1491 break;
1492 }
1493 }
1494
1495 return rvc;
1496}
1497
1498
1499/* Breakpoints. */
1500
1501static const gdb_byte *
67d57894 1502spu_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR * pcptr, int *lenptr)
771b4502
UW		 1503{
1504 static const gdb_byte breakpoint[] = { 0x00, 0x00, 0x3f, 0xff };
1505
1506 *lenptr = sizeof breakpoint;
1507 return breakpoint;
1508}
1509
1510
1511/* Software single-stepping support. */
1512
63807e1d 1513static int
0b1b3e42 1514spu_software_single_step (struct frame_info *frame)
771b4502 1515{
a6d9a66e 1516 struct gdbarch *gdbarch = get_frame_arch (frame);
6c95b8df 1517 struct address_space *aspace = get_frame_address_space (frame);
e17a4113 1518 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e0cd558a
UW		 1519 CORE_ADDR pc, next_pc;
1520 unsigned int insn;
1521 int offset, reg;
1522 gdb_byte buf[4];
771b4502 1523
0b1b3e42 1524 pc = get_frame_pc (frame);
771b4502 1525
e0cd558a
UW		 1526 if (target_read_memory (pc, buf, 4))
1527 return 1;
e17a4113 1528 insn = extract_unsigned_integer (buf, 4, byte_order);
771b4502 1529
e0cd558a
UW		 1530 /* Next sequential instruction is at PC + 4, except if the current
1531 instruction is a PPE-assisted call, in which case it is at PC + 8.
1532 Wrap around LS limit to be on the safe side. */
1533 if ((insn & 0xffffff00) == 0x00002100)
85e747d2 1534 next_pc = (SPUADDR_ADDR (pc) + 8) & (SPU_LS_SIZE - 1);
e0cd558a 1535 else
85e747d2 1536 next_pc = (SPUADDR_ADDR (pc) + 4) & (SPU_LS_SIZE - 1);
771b4502 1537
6c95b8df
PA		 1538 insert_single_step_breakpoint (gdbarch,
1539 aspace, SPUADDR (SPUADDR_SPU (pc), next_pc));
771b4502 1540
e0cd558a
UW		 1541 if (is_branch (insn, &offset, &reg))
1542 {
1543 CORE_ADDR target = offset;
771b4502 1544
e0cd558a 1545 if (reg == SPU_PC_REGNUM)
85e747d2 1546 target += SPUADDR_ADDR (pc);
e0cd558a
UW		 1547 else if (reg != -1)
1548 {
0b1b3e42 1549 get_frame_register_bytes (frame, reg, 0, 4, buf);
e17a4113 1550 target += extract_unsigned_integer (buf, 4, byte_order) & -4;
771b4502 1551 }
e0cd558a
UW		 1552
1553 target = target & (SPU_LS_SIZE - 1);
1554 if (target != next_pc)
6c95b8df 1555 insert_single_step_breakpoint (gdbarch, aspace,
85e747d2 1556 SPUADDR (SPUADDR_SPU (pc), target));
771b4502 1557 }
e6590a1b
UW		 1558
1559 return 1;
771b4502
UW		 1560}
1561
6e3f70d7
UW		 1562
1563/* Longjmp support. */
1564
1565static int
1566spu_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1567{
e17a4113 1568 struct gdbarch *gdbarch = get_frame_arch (frame);
85e747d2 1569 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 1570 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6e3f70d7
UW		 1571 gdb_byte buf[4];
1572 CORE_ADDR jb_addr;
1573
1574 /* Jump buffer is pointed to by the argument register $r3. */
1575 get_frame_register_bytes (frame, SPU_ARG1_REGNUM, 0, 4, buf);
e17a4113 1576 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
85e747d2 1577 if (target_read_memory (SPUADDR (tdep->id, jb_addr), buf, 4))
6e3f70d7
UW		 1578 return 0;
1579
e17a4113 1580 *pc = extract_unsigned_integer (buf, 4, byte_order);
85e747d2 1581 *pc = SPUADDR (tdep->id, *pc);
6e3f70d7
UW		 1582 return 1;
1583}
1584
1585
85e747d2
UW		 1586/* Disassembler. */
1587
1588struct spu_dis_asm_data
1589{
1590 struct gdbarch *gdbarch;
1591 int id;
1592};
1593
1594static void
1595spu_dis_asm_print_address (bfd_vma addr, struct disassemble_info *info)
1596{
1597 struct spu_dis_asm_data *data = info->application_data;
1598 print_address (data->gdbarch, SPUADDR (data->id, addr), info->stream);
1599}
1600
1601static int
1602gdb_print_insn_spu (bfd_vma memaddr, struct disassemble_info *info)
1603{
1604 /* The opcodes disassembler does 18-bit address arithmetic. Make sure the
1605 SPU ID encoded in the high bits is added back when we call print_address. */
1606 struct disassemble_info spu_info = *info;
1607 struct spu_dis_asm_data data;
1608 data.gdbarch = info->application_data;
1609 data.id = SPUADDR_SPU (memaddr);
1610
1611 spu_info.application_data = &data;
1612 spu_info.print_address_func = spu_dis_asm_print_address;
1613 return print_insn_spu (memaddr, &spu_info);
1614}
1615
1616
dcf52cd8
UW		 1617/* Target overlays for the SPU overlay manager.
1618
1619 See the documentation of simple_overlay_update for how the
1620 interface is supposed to work.
1621
1622 Data structures used by the overlay manager:
1623
1624 struct ovly_table
1625 {
1626 u32 vma;
1627 u32 size;
1628 u32 pos;
1629 u32 buf;
1630 } _ovly_table[]; -- one entry per overlay section
1631
1632 struct ovly_buf_table
1633 {
1634 u32 mapped;
1635 } _ovly_buf_table[]; -- one entry per overlay buffer
1636
1637 _ovly_table should never change.
1638
1639 Both tables are aligned to a 16-byte boundary, the symbols _ovly_table
1640 and _ovly_buf_table are of type STT_OBJECT and their size set to the size
1641 of the respective array. buf in _ovly_table is an index into _ovly_buf_table.
1642
1643 mapped is an index into _ovly_table. Both the mapped and buf indices start
1644 from one to reference the first entry in their respective tables. */
1645
1646/* Using the per-objfile private data mechanism, we store for each
1647 objfile an array of "struct spu_overlay_table" structures, one
1648 for each obj_section of the objfile. This structure holds two
1649 fields, MAPPED_PTR and MAPPED_VAL. If MAPPED_PTR is zero, this
1650 is *not* an overlay section. If it is non-zero, it represents
1651 a target address. The overlay section is mapped iff the target
1652 integer at this location equals MAPPED_VAL. */
1653
1654static const struct objfile_data *spu_overlay_data;
1655
1656struct spu_overlay_table
1657 {
1658 CORE_ADDR mapped_ptr;
1659 CORE_ADDR mapped_val;
1660 };
1661
1662/* Retrieve the overlay table for OBJFILE. If not already cached, read
1663 the _ovly_table data structure from the target and initialize the
1664 spu_overlay_table data structure from it. */
1665static struct spu_overlay_table *
1666spu_get_overlay_table (struct objfile *objfile)
1667{
e17a4113
UW		 1668 enum bfd_endian byte_order = bfd_big_endian (objfile->obfd)?
1669 BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
dcf52cd8
UW		 1670 struct minimal_symbol *ovly_table_msym, *ovly_buf_table_msym;
1671 CORE_ADDR ovly_table_base, ovly_buf_table_base;
1672 unsigned ovly_table_size, ovly_buf_table_size;
1673 struct spu_overlay_table *tbl;
1674 struct obj_section *osect;
1675 char *ovly_table;
1676 int i;
1677
1678 tbl = objfile_data (objfile, spu_overlay_data);
1679 if (tbl)
1680 return tbl;
1681
1682 ovly_table_msym = lookup_minimal_symbol ("_ovly_table", NULL, objfile);
1683 if (!ovly_table_msym)
1684 return NULL;
1685
1686 ovly_buf_table_msym = lookup_minimal_symbol ("_ovly_buf_table", NULL, objfile);
1687 if (!ovly_buf_table_msym)
1688 return NULL;
1689
1690 ovly_table_base = SYMBOL_VALUE_ADDRESS (ovly_table_msym);
1691 ovly_table_size = MSYMBOL_SIZE (ovly_table_msym);
1692
1693 ovly_buf_table_base = SYMBOL_VALUE_ADDRESS (ovly_buf_table_msym);
1694 ovly_buf_table_size = MSYMBOL_SIZE (ovly_buf_table_msym);
1695
1696 ovly_table = xmalloc (ovly_table_size);
1697 read_memory (ovly_table_base, ovly_table, ovly_table_size);
1698
1699 tbl = OBSTACK_CALLOC (&objfile->objfile_obstack,
1700 objfile->sections_end - objfile->sections,
1701 struct spu_overlay_table);
1702
1703 for (i = 0; i < ovly_table_size / 16; i++)
1704 {
e17a4113
UW		 1705 CORE_ADDR vma = extract_unsigned_integer (ovly_table + 16*i + 0,
1706 4, byte_order);
1707 CORE_ADDR size = extract_unsigned_integer (ovly_table + 16*i + 4,
1708 4, byte_order);
1709 CORE_ADDR pos = extract_unsigned_integer (ovly_table + 16*i + 8,
1710 4, byte_order);
1711 CORE_ADDR buf = extract_unsigned_integer (ovly_table + 16*i + 12,
1712 4, byte_order);
dcf52cd8
UW		 1713
1714 if (buf == 0 || (buf - 1) * 4 >= ovly_buf_table_size)
1715 continue;
1716
1717 ALL_OBJFILE_OSECTIONS (objfile, osect)
1718 if (vma == bfd_section_vma (objfile->obfd, osect->the_bfd_section)
1719 && pos == osect->the_bfd_section->filepos)
1720 {
1721 int ndx = osect - objfile->sections;
1722 tbl[ndx].mapped_ptr = ovly_buf_table_base + (buf - 1) * 4;
1723 tbl[ndx].mapped_val = i + 1;
1724 break;
1725 }
1726 }
1727
1728 xfree (ovly_table);
1729 set_objfile_data (objfile, spu_overlay_data, tbl);
1730 return tbl;
1731}
1732
1733/* Read _ovly_buf_table entry from the target to dermine whether
1734 OSECT is currently mapped, and update the mapped state. */
1735static void
1736spu_overlay_update_osect (struct obj_section *osect)
1737{
e17a4113
UW		 1738 enum bfd_endian byte_order = bfd_big_endian (osect->objfile->obfd)?
1739 BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
dcf52cd8 1740 struct spu_overlay_table *ovly_table;
85e747d2 1741 CORE_ADDR id, val;
dcf52cd8
UW		 1742
1743 ovly_table = spu_get_overlay_table (osect->objfile);
1744 if (!ovly_table)
1745 return;
1746
1747 ovly_table += osect - osect->objfile->sections;
1748 if (ovly_table->mapped_ptr == 0)
1749 return;
1750
85e747d2
UW		 1751 id = SPUADDR_SPU (obj_section_addr (osect));
1752 val = read_memory_unsigned_integer (SPUADDR (id, ovly_table->mapped_ptr),
1753 4, byte_order);
dcf52cd8
UW		 1754 osect->ovly_mapped = (val == ovly_table->mapped_val);
1755}
1756
1757/* If OSECT is NULL, then update all sections' mapped state.
1758 If OSECT is non-NULL, then update only OSECT's mapped state. */
1759static void
1760spu_overlay_update (struct obj_section *osect)
1761{
1762 /* Just one section. */
1763 if (osect)
1764 spu_overlay_update_osect (osect);
1765
1766 /* All sections. */
1767 else
1768 {
1769 struct objfile *objfile;
1770
1771 ALL_OBJSECTIONS (objfile, osect)
714835d5 1772 if (section_is_overlay (osect))
dcf52cd8
UW		 1773 spu_overlay_update_osect (osect);
1774 }
1775}
1776
1777/* Whenever a new objfile is loaded, read the target's _ovly_table.
1778 If there is one, go through all sections and make sure for non-
1779 overlay sections LMA equals VMA, while for overlay sections LMA
1780 is larger than local store size. */
1781static void
1782spu_overlay_new_objfile (struct objfile *objfile)
1783{
1784 struct spu_overlay_table *ovly_table;
1785 struct obj_section *osect;
1786
1787 /* If we've already touched this file, do nothing. */
1788 if (!objfile || objfile_data (objfile, spu_overlay_data) != NULL)
1789 return;
1790
0391f248
UW		 1791 /* Consider only SPU objfiles. */
1792 if (bfd_get_arch (objfile->obfd) != bfd_arch_spu)
1793 return;
1794
dcf52cd8
UW		 1795 /* Check if this objfile has overlays. */
1796 ovly_table = spu_get_overlay_table (objfile);
1797 if (!ovly_table)
1798 return;
1799
1800 /* Now go and fiddle with all the LMAs. */
1801 ALL_OBJFILE_OSECTIONS (objfile, osect)
1802 {
1803 bfd *obfd = objfile->obfd;
1804 asection *bsect = osect->the_bfd_section;
1805 int ndx = osect - objfile->sections;
1806
1807 if (ovly_table[ndx].mapped_ptr == 0)
1808 bfd_section_lma (obfd, bsect) = bfd_section_vma (obfd, bsect);
1809 else
1810 bfd_section_lma (obfd, bsect) = bsect->filepos + SPU_LS_SIZE;
1811 }
1812}
1813
771b4502 1814
3285f3fe
UW		 1815/* Insert temporary breakpoint on "main" function of newly loaded
1816 SPE context OBJFILE. */
1817static void
1818spu_catch_start (struct objfile *objfile)
1819{
1820 struct minimal_symbol *minsym;
1821 struct symtab *symtab;
1822 CORE_ADDR pc;
1823 char buf[32];
1824
1825 /* Do this only if requested by "set spu stop-on-load on". */
1826 if (!spu_stop_on_load_p)
1827 return;
1828
1829 /* Consider only SPU objfiles. */
1830 if (!objfile || bfd_get_arch (objfile->obfd) != bfd_arch_spu)
1831 return;
1832
1833 /* The main objfile is handled differently. */
1834 if (objfile == symfile_objfile)
1835 return;
1836
1837 /* There can be multiple symbols named "main". Search for the
1838 "main" in *this* objfile. */
1839 minsym = lookup_minimal_symbol ("main", NULL, objfile);
1840 if (!minsym)
1841 return;
1842
1843 /* If we have debugging information, try to use it -- this
1844 will allow us to properly skip the prologue. */
1845 pc = SYMBOL_VALUE_ADDRESS (minsym);
1846 symtab = find_pc_sect_symtab (pc, SYMBOL_OBJ_SECTION (minsym));
1847 if (symtab != NULL)
1848 {
1849 struct blockvector *bv = BLOCKVECTOR (symtab);
1850 struct block *block = BLOCKVECTOR_BLOCK (bv, GLOBAL_BLOCK);
1851 struct symbol *sym;
1852 struct symtab_and_line sal;
1853
94af9270 1854 sym = lookup_block_symbol (block, "main", VAR_DOMAIN);
3285f3fe
UW		 1855 if (sym)
1856 {
1857 fixup_symbol_section (sym, objfile);
1858 sal = find_function_start_sal (sym, 1);
1859 pc = sal.pc;
1860 }
1861 }
1862
1863 /* Use a numerical address for the set_breakpoint command to avoid having
1864 the breakpoint re-set incorrectly. */
1865 xsnprintf (buf, sizeof buf, "*%s", core_addr_to_string (pc));
d8c09fb5
JK		 1866 create_breakpoint (get_objfile_arch (objfile), buf /* arg */,
1867 NULL /* cond_string */, -1 /* thread */,
1868 0 /* parse_condition_and_thread */, 1 /* tempflag */,
1869 0 /* hardwareflag */, 0 /* traceflag */,
1870 0 /* ignore_count */,
1871 AUTO_BOOLEAN_FALSE /* pending_break_support */,
1872 NULL /* ops */, 0 /* from_tty */, 1 /* enabled */);
3285f3fe
UW		 1873}
1874
1875
ff1a52c6
UW		 1876/* Look up OBJFILE loaded into FRAME's SPU context. */
1877static struct objfile *
1878spu_objfile_from_frame (struct frame_info *frame)
1879{
1880 struct gdbarch *gdbarch = get_frame_arch (frame);
1881 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1882 struct objfile *obj;
1883
1884 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
1885 return NULL;
1886
1887 ALL_OBJFILES (obj)
1888 {
1889 if (obj->sections != obj->sections_end
1890 && SPUADDR_SPU (obj_section_addr (obj->sections)) == tdep->id)
1891 return obj;
1892 }
1893
1894 return NULL;
1895}
1896
1897/* Flush cache for ea pointer access if available. */
1898static void
1899flush_ea_cache (void)
1900{
1901 struct minimal_symbol *msymbol;
1902 struct objfile *obj;
1903
1904 if (!has_stack_frames ())
1905 return;
1906
1907 obj = spu_objfile_from_frame (get_current_frame ());
1908 if (obj == NULL)
1909 return;
1910
1911 /* Lookup inferior function __cache_flush. */
1912 msymbol = lookup_minimal_symbol ("__cache_flush", NULL, obj);
1913 if (msymbol != NULL)
1914 {
1915 struct type *type;
1916 CORE_ADDR addr;
1917
1918 type = objfile_type (obj)->builtin_void;
1919 type = lookup_function_type (type);
1920 type = lookup_pointer_type (type);
1921 addr = SYMBOL_VALUE_ADDRESS (msymbol);
1922
1923 call_function_by_hand (value_from_pointer (type, addr), 0, NULL);
1924 }
1925}
1926
1927/* This handler is called when the inferior has stopped. If it is stopped in
1928 SPU architecture then flush the ea cache if used. */
1929static void
1930spu_attach_normal_stop (struct bpstats *bs, int print_frame)
1931{
1932 if (!spu_auto_flush_cache_p)
1933 return;
1934
1935 /* Temporarily reset spu_auto_flush_cache_p to avoid recursively
1936 re-entering this function when __cache_flush stops. */
1937 spu_auto_flush_cache_p = 0;
1938 flush_ea_cache ();
1939 spu_auto_flush_cache_p = 1;
1940}
1941
1942
23d964e7
UW		 1943/* "info spu" commands. */
1944
1945static void
1946info_spu_event_command (char *args, int from_tty)
1947{
1948 struct frame_info *frame = get_selected_frame (NULL);
1949 ULONGEST event_status = 0;
1950 ULONGEST event_mask = 0;
1951 struct cleanup *chain;
1952 gdb_byte buf[100];
1953 char annex[32];
1954 LONGEST len;
1955 int rc, id;
1956
0391f248
UW		 1957 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
1958 error (_("\"info spu\" is only supported on the SPU architecture."));
1959
23d964e7
UW		 1960 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1961
1962 xsnprintf (annex, sizeof annex, "%d/event_status", id);
1963 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 1964 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 1965 if (len <= 0)
1966 error (_("Could not read event_status."));
9971ac47 1967 buf[len] = '\0';
23d964e7
UW		 1968 event_status = strtoulst (buf, NULL, 16);
1969
1970 xsnprintf (annex, sizeof annex, "%d/event_mask", id);
1971 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 1972 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 1973 if (len <= 0)
1974 error (_("Could not read event_mask."));
9971ac47 1975 buf[len] = '\0';
23d964e7
UW		 1976 event_mask = strtoulst (buf, NULL, 16);
1977
1978 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoEvent");
1979
1980 if (ui_out_is_mi_like_p (uiout))
1981 {
1982 ui_out_field_fmt (uiout, "event_status",
1983 "0x%s", phex_nz (event_status, 4));
1984 ui_out_field_fmt (uiout, "event_mask",
1985 "0x%s", phex_nz (event_mask, 4));
1986 }
1987 else
1988 {
1989 printf_filtered (_("Event Status 0x%s\n"), phex (event_status, 4));
1990 printf_filtered (_("Event Mask 0x%s\n"), phex (event_mask, 4));
1991 }
1992
1993 do_cleanups (chain);
1994}
1995
1996static void
1997info_spu_signal_command (char *args, int from_tty)
1998{
1999 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2000 struct gdbarch *gdbarch = get_frame_arch (frame);
2001 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2002 ULONGEST signal1 = 0;
2003 ULONGEST signal1_type = 0;
2004 int signal1_pending = 0;
2005 ULONGEST signal2 = 0;
2006 ULONGEST signal2_type = 0;
2007 int signal2_pending = 0;
2008 struct cleanup *chain;
2009 char annex[32];
2010 gdb_byte buf[100];
2011 LONGEST len;
2012 int rc, id;
2013
e17a4113 2014 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
0391f248
UW		 2015 error (_("\"info spu\" is only supported on the SPU architecture."));
2016
23d964e7
UW		 2017 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2018
2019 xsnprintf (annex, sizeof annex, "%d/signal1", id);
2020 len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
2021 if (len < 0)
2022 error (_("Could not read signal1."));
2023 else if (len == 4)
2024 {
e17a4113 2025 signal1 = extract_unsigned_integer (buf, 4, byte_order);
23d964e7
UW		 2026 signal1_pending = 1;
2027 }
2028
2029 xsnprintf (annex, sizeof annex, "%d/signal1_type", id);
2030 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2031 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2032 if (len <= 0)
2033 error (_("Could not read signal1_type."));
9971ac47 2034 buf[len] = '\0';
23d964e7
UW		 2035 signal1_type = strtoulst (buf, NULL, 16);
2036
2037 xsnprintf (annex, sizeof annex, "%d/signal2", id);
2038 len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
2039 if (len < 0)
2040 error (_("Could not read signal2."));
2041 else if (len == 4)
2042 {
e17a4113 2043 signal2 = extract_unsigned_integer (buf, 4, byte_order);
23d964e7
UW		 2044 signal2_pending = 1;
2045 }
2046
2047 xsnprintf (annex, sizeof annex, "%d/signal2_type", id);
2048 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2049 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2050 if (len <= 0)
2051 error (_("Could not read signal2_type."));
9971ac47 2052 buf[len] = '\0';
23d964e7
UW		 2053 signal2_type = strtoulst (buf, NULL, 16);
2054
2055 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoSignal");
2056
2057 if (ui_out_is_mi_like_p (uiout))
2058 {
2059 ui_out_field_int (uiout, "signal1_pending", signal1_pending);
2060 ui_out_field_fmt (uiout, "signal1", "0x%s", phex_nz (signal1, 4));
2061 ui_out_field_int (uiout, "signal1_type", signal1_type);
2062 ui_out_field_int (uiout, "signal2_pending", signal2_pending);
2063 ui_out_field_fmt (uiout, "signal2", "0x%s", phex_nz (signal2, 4));
2064 ui_out_field_int (uiout, "signal2_type", signal2_type);
2065 }
2066 else
2067 {
2068 if (signal1_pending)
2069 printf_filtered (_("Signal 1 control word 0x%s "), phex (signal1, 4));
2070 else
2071 printf_filtered (_("Signal 1 not pending "));
2072
2073 if (signal1_type)
23d964e7 2074 printf_filtered (_("(Type Or)\n"));
b94c4f7d
UW		 2075 else
2076 printf_filtered (_("(Type Overwrite)\n"));
23d964e7
UW		 2077
2078 if (signal2_pending)
2079 printf_filtered (_("Signal 2 control word 0x%s "), phex (signal2, 4));
2080 else
2081 printf_filtered (_("Signal 2 not pending "));
2082
2083 if (signal2_type)
23d964e7 2084 printf_filtered (_("(Type Or)\n"));
b94c4f7d
UW		 2085 else
2086 printf_filtered (_("(Type Overwrite)\n"));
23d964e7
UW		 2087 }
2088
2089 do_cleanups (chain);
2090}
2091
2092static void
e17a4113 2093info_spu_mailbox_list (gdb_byte *buf, int nr, enum bfd_endian byte_order,
23d964e7
UW		 2094 const char *field, const char *msg)
2095{
2096 struct cleanup *chain;
2097 int i;
2098
2099 if (nr <= 0)
2100 return;
2101
2102 chain = make_cleanup_ui_out_table_begin_end (uiout, 1, nr, "mbox");
2103
2104 ui_out_table_header (uiout, 32, ui_left, field, msg);
2105 ui_out_table_body (uiout);
2106
2107 for (i = 0; i < nr; i++)
2108 {
2109 struct cleanup *val_chain;
2110 ULONGEST val;
2111 val_chain = make_cleanup_ui_out_tuple_begin_end (uiout, "mbox");
e17a4113 2112 val = extract_unsigned_integer (buf + 4*i, 4, byte_order);
23d964e7
UW		 2113 ui_out_field_fmt (uiout, field, "0x%s", phex (val, 4));
2114 do_cleanups (val_chain);
2115
2116 if (!ui_out_is_mi_like_p (uiout))
2117 printf_filtered ("\n");
2118 }
2119
2120 do_cleanups (chain);
2121}
2122
2123static void
2124info_spu_mailbox_command (char *args, int from_tty)
2125{
2126 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2127 struct gdbarch *gdbarch = get_frame_arch (frame);
2128 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2129 struct cleanup *chain;
2130 char annex[32];
2131 gdb_byte buf[1024];
2132 LONGEST len;
2133 int i, id;
2134
e17a4113 2135 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
0391f248
UW		 2136 error (_("\"info spu\" is only supported on the SPU architecture."));
2137
23d964e7
UW		 2138 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2139
2140 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoMailbox");
2141
2142 xsnprintf (annex, sizeof annex, "%d/mbox_info", id);
2143 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2144 buf, 0, sizeof buf);
2145 if (len < 0)
2146 error (_("Could not read mbox_info."));
2147
e17a4113
UW		 2148 info_spu_mailbox_list (buf, len / 4, byte_order,
2149 "mbox", "SPU Outbound Mailbox");
23d964e7
UW		 2150
2151 xsnprintf (annex, sizeof annex, "%d/ibox_info", id);
2152 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2153 buf, 0, sizeof buf);
2154 if (len < 0)
2155 error (_("Could not read ibox_info."));
2156
e17a4113
UW		 2157 info_spu_mailbox_list (buf, len / 4, byte_order,
2158 "ibox", "SPU Outbound Interrupt Mailbox");
23d964e7
UW		 2159
2160 xsnprintf (annex, sizeof annex, "%d/wbox_info", id);
2161 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2162 buf, 0, sizeof buf);
2163 if (len < 0)
2164 error (_("Could not read wbox_info."));
2165
e17a4113
UW		 2166 info_spu_mailbox_list (buf, len / 4, byte_order,
2167 "wbox", "SPU Inbound Mailbox");
23d964e7
UW		 2168
2169 do_cleanups (chain);
2170}
2171
2172static ULONGEST
2173spu_mfc_get_bitfield (ULONGEST word, int first, int last)
2174{
2175 ULONGEST mask = ~(~(ULONGEST)0 << (last - first + 1));
2176 return (word >> (63 - last)) & mask;
2177}
2178
2179static void
e17a4113 2180info_spu_dma_cmdlist (gdb_byte *buf, int nr, enum bfd_endian byte_order)
23d964e7
UW		 2181{
2182 static char *spu_mfc_opcode[256] =
2183 {
2184 /* 00 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2185 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2186 /* 10 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2187 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2188 /* 20 */ "put", "putb", "putf", NULL, "putl", "putlb", "putlf", NULL,
2189 "puts", "putbs", "putfs", NULL, NULL, NULL, NULL, NULL,
2190 /* 30 */ "putr", "putrb", "putrf", NULL, "putrl", "putrlb", "putrlf", NULL,
2191 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2192 /* 40 */ "get", "getb", "getf", NULL, "getl", "getlb", "getlf", NULL,
2193 "gets", "getbs", "getfs", NULL, NULL, NULL, NULL, NULL,
2194 /* 50 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2195 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2196 /* 60 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2197 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2198 /* 70 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2199 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2200 /* 80 */ "sdcrt", "sdcrtst", NULL, NULL, NULL, NULL, NULL, NULL,
2201 NULL, "sdcrz", NULL, NULL, NULL, "sdcrst", NULL, "sdcrf",
2202 /* 90 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2203 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2204 /* a0 */ "sndsig", "sndsigb", "sndsigf", NULL, NULL, NULL, NULL, NULL,
2205 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2206 /* b0 */ "putlluc", NULL, NULL, NULL, "putllc", NULL, NULL, NULL,
2207 "putqlluc", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2208 /* c0 */ "barrier", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2209 "mfceieio", NULL, NULL, NULL, "mfcsync", NULL, NULL, NULL,
2210 /* d0 */ "getllar", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2211 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2212 /* e0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2213 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2214 /* f0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2215 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2216 };
2217
12ab8a60
UW		 2218 int *seq = alloca (nr * sizeof (int));
2219 int done = 0;
23d964e7 2220 struct cleanup *chain;
12ab8a60
UW		 2221 int i, j;
2222
2223
2224 /* Determine sequence in which to display (valid) entries. */
2225 for (i = 0; i < nr; i++)
2226 {
2227 /* Search for the first valid entry all of whose
2228 dependencies are met. */
2229 for (j = 0; j < nr; j++)
2230 {
2231 ULONGEST mfc_cq_dw3;
2232 ULONGEST dependencies;
2233
2234 if (done & (1 << (nr - 1 - j)))
2235 continue;
2236
e17a4113
UW		 2237 mfc_cq_dw3
2238 = extract_unsigned_integer (buf + 32*j + 24,8, byte_order);
12ab8a60
UW		 2239 if (!spu_mfc_get_bitfield (mfc_cq_dw3, 16, 16))
2240 continue;
2241
2242 dependencies = spu_mfc_get_bitfield (mfc_cq_dw3, 0, nr - 1);
2243 if ((dependencies & done) != dependencies)
2244 continue;
2245
2246 seq[i] = j;
2247 done |= 1 << (nr - 1 - j);
2248 break;
2249 }
2250
2251 if (j == nr)
2252 break;
2253 }
2254
2255 nr = i;
2256
23d964e7
UW		 2257
2258 chain = make_cleanup_ui_out_table_begin_end (uiout, 10, nr, "dma_cmd");
2259
2260 ui_out_table_header (uiout, 7, ui_left, "opcode", "Opcode");
2261 ui_out_table_header (uiout, 3, ui_left, "tag", "Tag");
2262 ui_out_table_header (uiout, 3, ui_left, "tid", "TId");
2263 ui_out_table_header (uiout, 3, ui_left, "rid", "RId");
2264 ui_out_table_header (uiout, 18, ui_left, "ea", "EA");
2265 ui_out_table_header (uiout, 7, ui_left, "lsa", "LSA");
2266 ui_out_table_header (uiout, 7, ui_left, "size", "Size");
2267 ui_out_table_header (uiout, 7, ui_left, "lstaddr", "LstAddr");
2268 ui_out_table_header (uiout, 7, ui_left, "lstsize", "LstSize");
2269 ui_out_table_header (uiout, 1, ui_left, "error_p", "E");
2270
2271 ui_out_table_body (uiout);
2272
2273 for (i = 0; i < nr; i++)
2274 {
2275 struct cleanup *cmd_chain;
2276 ULONGEST mfc_cq_dw0;
2277 ULONGEST mfc_cq_dw1;
2278 ULONGEST mfc_cq_dw2;
23d964e7
UW		 2279 int mfc_cmd_opcode, mfc_cmd_tag, rclass_id, tclass_id;
2280 int lsa, size, list_lsa, list_size, mfc_lsa, mfc_size;
2281 ULONGEST mfc_ea;
2282 int list_valid_p, noop_valid_p, qw_valid_p, ea_valid_p, cmd_error_p;
2283
2284 /* Decode contents of MFC Command Queue Context Save/Restore Registers.
2285 See "Cell Broadband Engine Registers V1.3", section 3.3.2.1. */
2286
e17a4113
UW		 2287 mfc_cq_dw0
2288 = extract_unsigned_integer (buf + 32*seq[i], 8, byte_order);
2289 mfc_cq_dw1
2290 = extract_unsigned_integer (buf + 32*seq[i] + 8, 8, byte_order);
2291 mfc_cq_dw2
2292 = extract_unsigned_integer (buf + 32*seq[i] + 16, 8, byte_order);
23d964e7
UW		 2293
2294 list_lsa = spu_mfc_get_bitfield (mfc_cq_dw0, 0, 14);
2295 list_size = spu_mfc_get_bitfield (mfc_cq_dw0, 15, 26);
2296 mfc_cmd_opcode = spu_mfc_get_bitfield (mfc_cq_dw0, 27, 34);
2297 mfc_cmd_tag = spu_mfc_get_bitfield (mfc_cq_dw0, 35, 39);
2298 list_valid_p = spu_mfc_get_bitfield (mfc_cq_dw0, 40, 40);
2299 rclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 41, 43);
2300 tclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 44, 46);
2301
2302 mfc_ea = spu_mfc_get_bitfield (mfc_cq_dw1, 0, 51) << 12
2303 | spu_mfc_get_bitfield (mfc_cq_dw2, 25, 36);
2304
2305 mfc_lsa = spu_mfc_get_bitfield (mfc_cq_dw2, 0, 13);
2306 mfc_size = spu_mfc_get_bitfield (mfc_cq_dw2, 14, 24);
2307 noop_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 37, 37);
2308 qw_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 38, 38);
2309 ea_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 39, 39);
2310 cmd_error_p = spu_mfc_get_bitfield (mfc_cq_dw2, 40, 40);
2311
2312 cmd_chain = make_cleanup_ui_out_tuple_begin_end (uiout, "cmd");
2313
2314 if (spu_mfc_opcode[mfc_cmd_opcode])
2315 ui_out_field_string (uiout, "opcode", spu_mfc_opcode[mfc_cmd_opcode]);
2316 else
2317 ui_out_field_int (uiout, "opcode", mfc_cmd_opcode);
2318
2319 ui_out_field_int (uiout, "tag", mfc_cmd_tag);
2320 ui_out_field_int (uiout, "tid", tclass_id);
2321 ui_out_field_int (uiout, "rid", rclass_id);
2322
2323 if (ea_valid_p)
2324 ui_out_field_fmt (uiout, "ea", "0x%s", phex (mfc_ea, 8));
2325 else
2326 ui_out_field_skip (uiout, "ea");
2327
2328 ui_out_field_fmt (uiout, "lsa", "0x%05x", mfc_lsa << 4);
2329 if (qw_valid_p)
2330 ui_out_field_fmt (uiout, "size", "0x%05x", mfc_size << 4);
2331 else
2332 ui_out_field_fmt (uiout, "size", "0x%05x", mfc_size);
2333
2334 if (list_valid_p)
2335 {
2336 ui_out_field_fmt (uiout, "lstaddr", "0x%05x", list_lsa << 3);
2337 ui_out_field_fmt (uiout, "lstsize", "0x%05x", list_size << 3);
2338 }
2339 else
2340 {
2341 ui_out_field_skip (uiout, "lstaddr");
2342 ui_out_field_skip (uiout, "lstsize");
2343 }
2344
2345 if (cmd_error_p)
2346 ui_out_field_string (uiout, "error_p", "*");
2347 else
2348 ui_out_field_skip (uiout, "error_p");
2349
2350 do_cleanups (cmd_chain);
2351
2352 if (!ui_out_is_mi_like_p (uiout))
2353 printf_filtered ("\n");
2354 }
2355
2356 do_cleanups (chain);
2357}
2358
2359static void
2360info_spu_dma_command (char *args, int from_tty)
2361{
2362 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2363 struct gdbarch *gdbarch = get_frame_arch (frame);
2364 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2365 ULONGEST dma_info_type;
2366 ULONGEST dma_info_mask;
2367 ULONGEST dma_info_status;
2368 ULONGEST dma_info_stall_and_notify;
2369 ULONGEST dma_info_atomic_command_status;
2370 struct cleanup *chain;
2371 char annex[32];
2372 gdb_byte buf[1024];
2373 LONGEST len;
2374 int i, id;
2375
0391f248
UW		 2376 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
2377 error (_("\"info spu\" is only supported on the SPU architecture."));
2378
23d964e7
UW		 2379 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2380
2381 xsnprintf (annex, sizeof annex, "%d/dma_info", id);
2382 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2383 buf, 0, 40 + 16 * 32);
2384 if (len <= 0)
2385 error (_("Could not read dma_info."));
2386
e17a4113
UW		 2387 dma_info_type
2388 = extract_unsigned_integer (buf, 8, byte_order);
2389 dma_info_mask
2390 = extract_unsigned_integer (buf + 8, 8, byte_order);
2391 dma_info_status
2392 = extract_unsigned_integer (buf + 16, 8, byte_order);
2393 dma_info_stall_and_notify
2394 = extract_unsigned_integer (buf + 24, 8, byte_order);
2395 dma_info_atomic_command_status
2396 = extract_unsigned_integer (buf + 32, 8, byte_order);
23d964e7
UW		 2397
2398 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoDMA");
2399
2400 if (ui_out_is_mi_like_p (uiout))
2401 {
2402 ui_out_field_fmt (uiout, "dma_info_type", "0x%s",
2403 phex_nz (dma_info_type, 4));
2404 ui_out_field_fmt (uiout, "dma_info_mask", "0x%s",
2405 phex_nz (dma_info_mask, 4));
2406 ui_out_field_fmt (uiout, "dma_info_status", "0x%s",
2407 phex_nz (dma_info_status, 4));
2408 ui_out_field_fmt (uiout, "dma_info_stall_and_notify", "0x%s",
2409 phex_nz (dma_info_stall_and_notify, 4));
2410 ui_out_field_fmt (uiout, "dma_info_atomic_command_status", "0x%s",
2411 phex_nz (dma_info_atomic_command_status, 4));
2412 }
2413 else
2414 {
8fbde58b 2415 const char *query_msg = _("no query pending");
23d964e7 2416
8fbde58b
UW		 2417 if (dma_info_type & 4)
2418 switch (dma_info_type & 3)
2419 {
2420 case 1: query_msg = _("'any' query pending"); break;
2421 case 2: query_msg = _("'all' query pending"); break;
2422 default: query_msg = _("undefined query type"); break;
2423 }
23d964e7
UW		 2424
2425 printf_filtered (_("Tag-Group Status 0x%s\n"),
2426 phex (dma_info_status, 4));
2427 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
2428 phex (dma_info_mask, 4), query_msg);
2429 printf_filtered (_("Stall-and-Notify 0x%s\n"),
2430 phex (dma_info_stall_and_notify, 4));
2431 printf_filtered (_("Atomic Cmd Status 0x%s\n"),
2432 phex (dma_info_atomic_command_status, 4));
2433 printf_filtered ("\n");
2434 }
2435
e17a4113 2436 info_spu_dma_cmdlist (buf + 40, 16, byte_order);
23d964e7
UW		 2437 do_cleanups (chain);
2438}
2439
2440static void
2441info_spu_proxydma_command (char *args, int from_tty)
2442{
2443 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2444 struct gdbarch *gdbarch = get_frame_arch (frame);
2445 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2446 ULONGEST dma_info_type;
2447 ULONGEST dma_info_mask;
2448 ULONGEST dma_info_status;
2449 struct cleanup *chain;
2450 char annex[32];
2451 gdb_byte buf[1024];
2452 LONGEST len;
2453 int i, id;
2454
e17a4113 2455 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
0391f248
UW		 2456 error (_("\"info spu\" is only supported on the SPU architecture."));
2457
23d964e7
UW		 2458 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2459
2460 xsnprintf (annex, sizeof annex, "%d/proxydma_info", id);
2461 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2462 buf, 0, 24 + 8 * 32);
2463 if (len <= 0)
2464 error (_("Could not read proxydma_info."));
2465
e17a4113
UW		 2466 dma_info_type = extract_unsigned_integer (buf, 8, byte_order);
2467 dma_info_mask = extract_unsigned_integer (buf + 8, 8, byte_order);
2468 dma_info_status = extract_unsigned_integer (buf + 16, 8, byte_order);
23d964e7
UW		 2469
2470 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoProxyDMA");
2471
2472 if (ui_out_is_mi_like_p (uiout))
2473 {
2474 ui_out_field_fmt (uiout, "proxydma_info_type", "0x%s",
2475 phex_nz (dma_info_type, 4));
2476 ui_out_field_fmt (uiout, "proxydma_info_mask", "0x%s",
2477 phex_nz (dma_info_mask, 4));
2478 ui_out_field_fmt (uiout, "proxydma_info_status", "0x%s",
2479 phex_nz (dma_info_status, 4));
2480 }
2481 else
2482 {
2483 const char *query_msg;
2484
8fbde58b 2485 switch (dma_info_type & 3)
23d964e7
UW		 2486 {
2487 case 0: query_msg = _("no query pending"); break;
2488 case 1: query_msg = _("'any' query pending"); break;
2489 case 2: query_msg = _("'all' query pending"); break;
2490 default: query_msg = _("undefined query type"); break;
2491 }
2492
2493 printf_filtered (_("Tag-Group Status 0x%s\n"),
2494 phex (dma_info_status, 4));
2495 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
2496 phex (dma_info_mask, 4), query_msg);
2497 printf_filtered ("\n");
2498 }
2499
e17a4113 2500 info_spu_dma_cmdlist (buf + 24, 8, byte_order);
23d964e7
UW		 2501 do_cleanups (chain);
2502}
2503
2504static void
2505info_spu_command (char *args, int from_tty)
2506{
2507 printf_unfiltered (_("\"info spu\" must be followed by the name of an SPU facility.\n"));
2508 help_list (infospucmdlist, "info spu ", -1, gdb_stdout);
2509}
2510
2511
3285f3fe
UW		 2512/* Root of all "set spu "/"show spu " commands. */
2513
2514static void
2515show_spu_command (char *args, int from_tty)
2516{
2517 help_list (showspucmdlist, "show spu ", all_commands, gdb_stdout);
2518}
2519
2520static void
2521set_spu_command (char *args, int from_tty)
2522{
2523 help_list (setspucmdlist, "set spu ", all_commands, gdb_stdout);
2524}
2525
2526static void
2527show_spu_stop_on_load (struct ui_file *file, int from_tty,
2528 struct cmd_list_element *c, const char *value)
2529{
2530 fprintf_filtered (file, _("Stopping for new SPE threads is %s.\n"),
2531 value);
2532}
2533
ff1a52c6
UW		 2534static void
2535show_spu_auto_flush_cache (struct ui_file *file, int from_tty,
2536 struct cmd_list_element *c, const char *value)
2537{
2538 fprintf_filtered (file, _("Automatic software-cache flush is %s.\n"),
2539 value);
2540}
2541
3285f3fe 2542
771b4502
UW		 2543/* Set up gdbarch struct. */
2544
2545static struct gdbarch *
2546spu_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2547{
2548 struct gdbarch *gdbarch;
794ac428 2549 struct gdbarch_tdep *tdep;
85e747d2
UW		 2550 int id = -1;
2551
2552 /* Which spufs ID was requested as address space? */
2553 if (info.tdep_info)
2554 id = *(int *)info.tdep_info;
2555 /* For objfile architectures of SPU solibs, decode the ID from the name.
2556 This assumes the filename convention employed by solib-spu.c. */
2557 else if (info.abfd)
2558 {
2559 char *name = strrchr (info.abfd->filename, '@');
2560 if (name)
2561 sscanf (name, "@0x%*x <%d>", &id);
2562 }
771b4502 2563
85e747d2
UW		 2564 /* Find a candidate among extant architectures. */
2565 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2566 arches != NULL;
2567 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2568 {
2569 tdep = gdbarch_tdep (arches->gdbarch);
2570 if (tdep && tdep->id == id)
2571 return arches->gdbarch;
2572 }
771b4502 2573
85e747d2 2574 /* None found, so create a new architecture. */
794ac428 2575 tdep = XCALLOC (1, struct gdbarch_tdep);
85e747d2 2576 tdep->id = id;
794ac428 2577 gdbarch = gdbarch_alloc (&info, tdep);
771b4502
UW		 2578
2579 /* Disassembler. */
85e747d2 2580 set_gdbarch_print_insn (gdbarch, gdb_print_insn_spu);
771b4502
UW		 2581
2582 /* Registers. */
2583 set_gdbarch_num_regs (gdbarch, SPU_NUM_REGS);
2584 set_gdbarch_num_pseudo_regs (gdbarch, SPU_NUM_PSEUDO_REGS);
2585 set_gdbarch_sp_regnum (gdbarch, SPU_SP_REGNUM);
2586 set_gdbarch_pc_regnum (gdbarch, SPU_PC_REGNUM);
118dfbaf
UW		 2587 set_gdbarch_read_pc (gdbarch, spu_read_pc);
2588 set_gdbarch_write_pc (gdbarch, spu_write_pc);
771b4502
UW		 2589 set_gdbarch_register_name (gdbarch, spu_register_name);
2590 set_gdbarch_register_type (gdbarch, spu_register_type);
2591 set_gdbarch_pseudo_register_read (gdbarch, spu_pseudo_register_read);
2592 set_gdbarch_pseudo_register_write (gdbarch, spu_pseudo_register_write);
9acbedc0 2593 set_gdbarch_value_from_register (gdbarch, spu_value_from_register);
771b4502
UW		 2594 set_gdbarch_register_reggroup_p (gdbarch, spu_register_reggroup_p);
2595
2596 /* Data types. */
2597 set_gdbarch_char_signed (gdbarch, 0);
2598 set_gdbarch_ptr_bit (gdbarch, 32);
2599 set_gdbarch_addr_bit (gdbarch, 32);
2600 set_gdbarch_short_bit (gdbarch, 16);
2601 set_gdbarch_int_bit (gdbarch, 32);
2602 set_gdbarch_long_bit (gdbarch, 32);
2603 set_gdbarch_long_long_bit (gdbarch, 64);
2604 set_gdbarch_float_bit (gdbarch, 32);
2605 set_gdbarch_double_bit (gdbarch, 64);
2606 set_gdbarch_long_double_bit (gdbarch, 64);
8da61cc4
DJ		 2607 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2608 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2609 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
771b4502 2610
ff1a52c6 2611 /* Address handling. */
85e747d2 2612 set_gdbarch_address_to_pointer (gdbarch, spu_address_to_pointer);
36acd84e
UW		 2613 set_gdbarch_pointer_to_address (gdbarch, spu_pointer_to_address);
2614 set_gdbarch_integer_to_address (gdbarch, spu_integer_to_address);
ff1a52c6
UW		 2615 set_gdbarch_address_class_type_flags (gdbarch, spu_address_class_type_flags);
2616 set_gdbarch_address_class_type_flags_to_name
2617 (gdbarch, spu_address_class_type_flags_to_name);
2618 set_gdbarch_address_class_name_to_type_flags
2619 (gdbarch, spu_address_class_name_to_type_flags);
2620
36acd84e 2621
771b4502 2622 /* Inferior function calls. */
7b3dc0b7
UW		 2623 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
2624 set_gdbarch_frame_align (gdbarch, spu_frame_align);
5141027d 2625 set_gdbarch_frame_red_zone_size (gdbarch, 2000);
87805e63 2626 set_gdbarch_push_dummy_code (gdbarch, spu_push_dummy_code);
771b4502 2627 set_gdbarch_push_dummy_call (gdbarch, spu_push_dummy_call);
8d998b8f 2628 set_gdbarch_dummy_id (gdbarch, spu_dummy_id);
771b4502
UW		 2629 set_gdbarch_return_value (gdbarch, spu_return_value);
2630
2631 /* Frame handling. */
2632 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8d998b8f 2633 frame_unwind_append_unwinder (gdbarch, &spu_frame_unwind);
771b4502
UW		 2634 frame_base_set_default (gdbarch, &spu_frame_base);
2635 set_gdbarch_unwind_pc (gdbarch, spu_unwind_pc);
2636 set_gdbarch_unwind_sp (gdbarch, spu_unwind_sp);
2637 set_gdbarch_virtual_frame_pointer (gdbarch, spu_virtual_frame_pointer);
2638 set_gdbarch_frame_args_skip (gdbarch, 0);
2639 set_gdbarch_skip_prologue (gdbarch, spu_skip_prologue);
fe5febed 2640 set_gdbarch_in_function_epilogue_p (gdbarch, spu_in_function_epilogue_p);
771b4502 2641
cc5f0d61
UW		 2642 /* Cell/B.E. cross-architecture unwinder support. */
2643 frame_unwind_prepend_unwinder (gdbarch, &spu2ppu_unwind);
2644
771b4502
UW		 2645 /* Breakpoints. */
2646 set_gdbarch_decr_pc_after_break (gdbarch, 4);
2647 set_gdbarch_breakpoint_from_pc (gdbarch, spu_breakpoint_from_pc);
2648 set_gdbarch_cannot_step_breakpoint (gdbarch, 1);
2649 set_gdbarch_software_single_step (gdbarch, spu_software_single_step);
6e3f70d7 2650 set_gdbarch_get_longjmp_target (gdbarch, spu_get_longjmp_target);
771b4502 2651
dcf52cd8
UW		 2652 /* Overlays. */
2653 set_gdbarch_overlay_update (gdbarch, spu_overlay_update);
2654
771b4502
UW		 2655 return gdbarch;
2656}
2657
63807e1d
PA		 2658/* Provide a prototype to silence -Wmissing-prototypes. */
2659extern initialize_file_ftype _initialize_spu_tdep;
2660
771b4502
UW		 2661void
2662_initialize_spu_tdep (void)
2663{
2664 register_gdbarch_init (bfd_arch_spu, spu_gdbarch_init);
f2d43c2c 2665
dcf52cd8
UW		 2666 /* Add ourselves to objfile event chain. */
2667 observer_attach_new_objfile (spu_overlay_new_objfile);
2668 spu_overlay_data = register_objfile_data ();
23d964e7 2669
3285f3fe
UW		 2670 /* Install spu stop-on-load handler. */
2671 observer_attach_new_objfile (spu_catch_start);
2672
ff1a52c6
UW		 2673 /* Add ourselves to normal_stop event chain. */
2674 observer_attach_normal_stop (spu_attach_normal_stop);
2675
3285f3fe
UW		 2676 /* Add root prefix command for all "set spu"/"show spu" commands. */
2677 add_prefix_cmd ("spu", no_class, set_spu_command,
2678 _("Various SPU specific commands."),
2679 &setspucmdlist, "set spu ", 0, &setlist);
2680 add_prefix_cmd ("spu", no_class, show_spu_command,
2681 _("Various SPU specific commands."),
2682 &showspucmdlist, "show spu ", 0, &showlist);
2683
2684 /* Toggle whether or not to add a temporary breakpoint at the "main"
2685 function of new SPE contexts. */
2686 add_setshow_boolean_cmd ("stop-on-load", class_support,
2687 &spu_stop_on_load_p, _("\
2688Set whether to stop for new SPE threads."),
2689 _("\
2690Show whether to stop for new SPE threads."),
2691 _("\
2692Use \"on\" to give control to the user when a new SPE thread\n\
2693enters its \"main\" function.\n\
2694Use \"off\" to disable stopping for new SPE threads."),
2695 NULL,
2696 show_spu_stop_on_load,
2697 &setspucmdlist, &showspucmdlist);
2698
ff1a52c6
UW		 2699 /* Toggle whether or not to automatically flush the software-managed
2700 cache whenever SPE execution stops. */
2701 add_setshow_boolean_cmd ("auto-flush-cache", class_support,
2702 &spu_auto_flush_cache_p, _("\
2703Set whether to automatically flush the software-managed cache."),
2704 _("\
2705Show whether to automatically flush the software-managed cache."),
2706 _("\
2707Use \"on\" to automatically flush the software-managed cache\n\
2708whenever SPE execution stops.\n\
2709Use \"off\" to never automatically flush the software-managed cache."),
2710 NULL,
2711 show_spu_auto_flush_cache,
2712 &setspucmdlist, &showspucmdlist);
2713
23d964e7
UW		 2714 /* Add root prefix command for all "info spu" commands. */
2715 add_prefix_cmd ("spu", class_info, info_spu_command,
2716 _("Various SPU specific commands."),
2717 &infospucmdlist, "info spu ", 0, &infolist);
2718
2719 /* Add various "info spu" commands. */
2720 add_cmd ("event", class_info, info_spu_event_command,
2721 _("Display SPU event facility status.\n"),
2722 &infospucmdlist);
2723 add_cmd ("signal", class_info, info_spu_signal_command,
2724 _("Display SPU signal notification facility status.\n"),
2725 &infospucmdlist);
2726 add_cmd ("mailbox", class_info, info_spu_mailbox_command,
2727 _("Display SPU mailbox facility status.\n"),
2728 &infospucmdlist);
2729 add_cmd ("dma", class_info, info_spu_dma_command,
2730 _("Display MFC DMA status.\n"),
2731 &infospucmdlist);
2732 add_cmd ("proxydma", class_info, info_spu_proxydma_command,
2733 _("Display MFC Proxy-DMA status.\n"),
2734 &infospucmdlist);
771b4502 2735}
GDB Binutils - Deliverables
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