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[deliverable/binutils-gdb.git] / gdb / spu-tdep.c
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771b4502 1/* SPU target-dependent code for GDB, the GNU debugger.
9b254dd1 2 Copyright (C) 2006, 2007, 2008 Free Software Foundation, Inc.
771b4502
UW		 3
4 Contributed by Ulrich Weigand <uweigand@de.ibm.com>.
5 Based on a port by Sid Manning <sid@us.ibm.com>.
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
a9762ec7 11 the Free Software Foundation; either version 3 of the License, or
771b4502
UW		 12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
a9762ec7 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
771b4502
UW		 21
22#include "defs.h"
23#include "arch-utils.h"
24#include "gdbtypes.h"
25#include "gdbcmd.h"
26#include "gdbcore.h"
27#include "gdb_string.h"
28#include "gdb_assert.h"
29#include "frame.h"
30#include "frame-unwind.h"
31#include "frame-base.h"
32#include "trad-frame.h"
33#include "symtab.h"
34#include "symfile.h"
35#include "value.h"
36#include "inferior.h"
37#include "dis-asm.h"
38#include "objfiles.h"
39#include "language.h"
40#include "regcache.h"
41#include "reggroups.h"
42#include "floatformat.h"
dcf52cd8 43#include "observer.h"
771b4502
UW		 44
45#include "spu-tdep.h"
46
794ac428
UW		 47
48/* The tdep structure. */
49struct gdbarch_tdep
50{
51 /* SPU-specific vector type. */
52 struct type *spu_builtin_type_vec128;
53};
54
55
f2d43c2c 56/* SPU-specific vector type. */
794ac428
UW		 57static struct type *
58spu_builtin_type_vec128 (struct gdbarch *gdbarch)
59{
60 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
61
62 if (!tdep->spu_builtin_type_vec128)
63 {
64 struct type *t;
65
66 t = init_composite_type ("__spu_builtin_type_vec128", TYPE_CODE_UNION);
67 append_composite_type_field (t, "uint128", builtin_type_int128);
68 append_composite_type_field (t, "v2_int64",
69 init_vector_type (builtin_type_int64, 2));
70 append_composite_type_field (t, "v4_int32",
71 init_vector_type (builtin_type_int32, 4));
72 append_composite_type_field (t, "v8_int16",
73 init_vector_type (builtin_type_int16, 8));
74 append_composite_type_field (t, "v16_int8",
75 init_vector_type (builtin_type_int8, 16));
76 append_composite_type_field (t, "v2_double",
77 init_vector_type (builtin_type_double, 2));
78 append_composite_type_field (t, "v4_float",
79 init_vector_type (builtin_type_float, 4));
80
876cecd0 81 TYPE_VECTOR (t) = 1;
794ac428
UW		 82 TYPE_NAME (t) = "spu_builtin_type_vec128";
83
84 tdep->spu_builtin_type_vec128 = t;
85 }
86
87 return tdep->spu_builtin_type_vec128;
88}
89
771b4502 90
23d964e7
UW		 91/* The list of available "info spu " commands. */
92static struct cmd_list_element *infospucmdlist = NULL;
93
771b4502
UW		 94/* Registers. */
95
96static const char *
d93859e2 97spu_register_name (struct gdbarch *gdbarch, int reg_nr)
771b4502
UW		 98{
99 static char *register_names[] =
100 {
101 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
102 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
103 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
104 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
105 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
106 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
107 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
108 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
109 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
110 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
111 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
112 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
113 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
114 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
115 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
116 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
23d964e7 117 "id", "pc", "sp", "fpscr", "srr0", "lslr", "decr", "decr_status"
771b4502
UW		 118 };
119
120 if (reg_nr < 0)
121 return NULL;
122 if (reg_nr >= sizeof register_names / sizeof *register_names)
123 return NULL;
124
125 return register_names[reg_nr];
126}
127
128static struct type *
129spu_register_type (struct gdbarch *gdbarch, int reg_nr)
130{
131 if (reg_nr < SPU_NUM_GPRS)
794ac428 132 return spu_builtin_type_vec128 (gdbarch);
771b4502
UW		 133
134 switch (reg_nr)
135 {
136 case SPU_ID_REGNUM:
137 return builtin_type_uint32;
138
139 case SPU_PC_REGNUM:
140 return builtin_type_void_func_ptr;
141
142 case SPU_SP_REGNUM:
143 return builtin_type_void_data_ptr;
144
23d964e7
UW		 145 case SPU_FPSCR_REGNUM:
146 return builtin_type_uint128;
147
148 case SPU_SRR0_REGNUM:
149 return builtin_type_uint32;
150
151 case SPU_LSLR_REGNUM:
152 return builtin_type_uint32;
153
154 case SPU_DECR_REGNUM:
155 return builtin_type_uint32;
156
157 case SPU_DECR_STATUS_REGNUM:
158 return builtin_type_uint32;
159
771b4502
UW		 160 default:
161 internal_error (__FILE__, __LINE__, "invalid regnum");
162 }
163}
164
165/* Pseudo registers for preferred slots - stack pointer. */
166
23d964e7
UW		 167static void
168spu_pseudo_register_read_spu (struct regcache *regcache, const char *regname,
169 gdb_byte *buf)
170{
171 gdb_byte reg[32];
172 char annex[32];
173 ULONGEST id;
174
175 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
176 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
177 memset (reg, 0, sizeof reg);
178 target_read (&current_target, TARGET_OBJECT_SPU, annex,
179 reg, 0, sizeof reg);
180
181 store_unsigned_integer (buf, 4, strtoulst (reg, NULL, 16));
182}
183
771b4502
UW		 184static void
185spu_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
186 int regnum, gdb_byte *buf)
187{
188 gdb_byte reg[16];
23d964e7
UW		 189 char annex[32];
190 ULONGEST id;
771b4502
UW		 191
192 switch (regnum)
193 {
194 case SPU_SP_REGNUM:
195 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
196 memcpy (buf, reg, 4);
197 break;
198
23d964e7
UW		 199 case SPU_FPSCR_REGNUM:
200 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
201 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
202 target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
203 break;
204
205 case SPU_SRR0_REGNUM:
206 spu_pseudo_register_read_spu (regcache, "srr0", buf);
207 break;
208
209 case SPU_LSLR_REGNUM:
210 spu_pseudo_register_read_spu (regcache, "lslr", buf);
211 break;
212
213 case SPU_DECR_REGNUM:
214 spu_pseudo_register_read_spu (regcache, "decr", buf);
215 break;
216
217 case SPU_DECR_STATUS_REGNUM:
218 spu_pseudo_register_read_spu (regcache, "decr_status", buf);
219 break;
220
771b4502
UW		 221 default:
222 internal_error (__FILE__, __LINE__, _("invalid regnum"));
223 }
224}
225
23d964e7
UW		 226static void
227spu_pseudo_register_write_spu (struct regcache *regcache, const char *regname,
228 const gdb_byte *buf)
229{
230 gdb_byte reg[32];
231 char annex[32];
232 ULONGEST id;
233
234 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
235 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
236 xsnprintf (reg, sizeof reg, "0x%s",
237 phex_nz (extract_unsigned_integer (buf, 4), 4));
238 target_write (&current_target, TARGET_OBJECT_SPU, annex,
239 reg, 0, strlen (reg));
240}
241
771b4502
UW		 242static void
243spu_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
244 int regnum, const gdb_byte *buf)
245{
246 gdb_byte reg[16];
23d964e7
UW		 247 char annex[32];
248 ULONGEST id;
771b4502
UW		 249
250 switch (regnum)
251 {
252 case SPU_SP_REGNUM:
253 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
254 memcpy (reg, buf, 4);
255 regcache_raw_write (regcache, SPU_RAW_SP_REGNUM, reg);
256 break;
257
23d964e7
UW		 258 case SPU_FPSCR_REGNUM:
259 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
260 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
261 target_write (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
262 break;
263
264 case SPU_SRR0_REGNUM:
265 spu_pseudo_register_write_spu (regcache, "srr0", buf);
266 break;
267
268 case SPU_LSLR_REGNUM:
269 spu_pseudo_register_write_spu (regcache, "lslr", buf);
270 break;
271
272 case SPU_DECR_REGNUM:
273 spu_pseudo_register_write_spu (regcache, "decr", buf);
274 break;
275
276 case SPU_DECR_STATUS_REGNUM:
277 spu_pseudo_register_write_spu (regcache, "decr_status", buf);
278 break;
279
771b4502
UW		 280 default:
281 internal_error (__FILE__, __LINE__, _("invalid regnum"));
282 }
283}
284
285/* Value conversion -- access scalar values at the preferred slot. */
286
9acbedc0
UW		 287static struct value *
288spu_value_from_register (struct type *type, int regnum,
289 struct frame_info *frame)
771b4502 290{
9acbedc0
UW		 291 struct value *value = default_value_from_register (type, regnum, frame);
292 int len = TYPE_LENGTH (type);
771b4502 293
9acbedc0
UW		 294 if (regnum < SPU_NUM_GPRS && len < 16)
295 {
296 int preferred_slot = len < 4 ? 4 - len : 0;
297 set_value_offset (value, preferred_slot);
298 }
771b4502 299
9acbedc0 300 return value;
771b4502
UW		 301}
302
303/* Register groups. */
304
305static int
306spu_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
307 struct reggroup *group)
308{
309 /* Registers displayed via 'info regs'. */
310 if (group == general_reggroup)
311 return 1;
312
313 /* Registers displayed via 'info float'. */
314 if (group == float_reggroup)
315 return 0;
316
317 /* Registers that need to be saved/restored in order to
318 push or pop frames. */
319 if (group == save_reggroup || group == restore_reggroup)
320 return 1;
321
322 return default_register_reggroup_p (gdbarch, regnum, group);
323}
324
36acd84e
UW		 325/* Address conversion. */
326
327static CORE_ADDR
328spu_pointer_to_address (struct type *type, const gdb_byte *buf)
329{
330 ULONGEST addr = extract_unsigned_integer (buf, TYPE_LENGTH (type));
331 ULONGEST lslr = SPU_LS_SIZE - 1; /* Hard-wired LS size. */
332
333 if (target_has_registers && target_has_stack && target_has_memory)
334 lslr = get_frame_register_unsigned (get_selected_frame (NULL),
335 SPU_LSLR_REGNUM);
336
337 return addr & lslr;
338}
339
340static CORE_ADDR
341spu_integer_to_address (struct gdbarch *gdbarch,
342 struct type *type, const gdb_byte *buf)
343{
344 ULONGEST addr = unpack_long (type, buf);
345 ULONGEST lslr = SPU_LS_SIZE - 1; /* Hard-wired LS size. */
346
347 if (target_has_registers && target_has_stack && target_has_memory)
348 lslr = get_frame_register_unsigned (get_selected_frame (NULL),
349 SPU_LSLR_REGNUM);
350
351 return addr & lslr;
352}
353
771b4502
UW		 354
355/* Decoding SPU instructions. */
356
357enum
358 {
359 op_lqd = 0x34,
360 op_lqx = 0x3c4,
361 op_lqa = 0x61,
362 op_lqr = 0x67,
363 op_stqd = 0x24,
364 op_stqx = 0x144,
365 op_stqa = 0x41,
366 op_stqr = 0x47,
367
368 op_il = 0x081,
369 op_ila = 0x21,
370 op_a = 0x0c0,
371 op_ai = 0x1c,
372
373 op_selb = 0x4,
374
375 op_br = 0x64,
376 op_bra = 0x60,
377 op_brsl = 0x66,
378 op_brasl = 0x62,
379 op_brnz = 0x42,
380 op_brz = 0x40,
381 op_brhnz = 0x46,
382 op_brhz = 0x44,
383 op_bi = 0x1a8,
384 op_bisl = 0x1a9,
385 op_biz = 0x128,
386 op_binz = 0x129,
387 op_bihz = 0x12a,
388 op_bihnz = 0x12b,
389 };
390
391static int
392is_rr (unsigned int insn, int op, int *rt, int *ra, int *rb)
393{
394 if ((insn >> 21) == op)
395 {
396 *rt = insn & 127;
397 *ra = (insn >> 7) & 127;
398 *rb = (insn >> 14) & 127;
399 return 1;
400 }
401
402 return 0;
403}
404
405static int
406is_rrr (unsigned int insn, int op, int *rt, int *ra, int *rb, int *rc)
407{
408 if ((insn >> 28) == op)
409 {
410 *rt = (insn >> 21) & 127;
411 *ra = (insn >> 7) & 127;
412 *rb = (insn >> 14) & 127;
413 *rc = insn & 127;
414 return 1;
415 }
416
417 return 0;
418}
419
420static int
421is_ri7 (unsigned int insn, int op, int *rt, int *ra, int *i7)
422{
423 if ((insn >> 21) == op)
424 {
425 *rt = insn & 127;
426 *ra = (insn >> 7) & 127;
427 *i7 = (((insn >> 14) & 127) ^ 0x40) - 0x40;
428 return 1;
429 }
430
431 return 0;
432}
433
434static int
435is_ri10 (unsigned int insn, int op, int *rt, int *ra, int *i10)
436{
437 if ((insn >> 24) == op)
438 {
439 *rt = insn & 127;
440 *ra = (insn >> 7) & 127;
441 *i10 = (((insn >> 14) & 0x3ff) ^ 0x200) - 0x200;
442 return 1;
443 }
444
445 return 0;
446}
447
448static int
449is_ri16 (unsigned int insn, int op, int *rt, int *i16)
450{
451 if ((insn >> 23) == op)
452 {
453 *rt = insn & 127;
454 *i16 = (((insn >> 7) & 0xffff) ^ 0x8000) - 0x8000;
455 return 1;
456 }
457
458 return 0;
459}
460
461static int
462is_ri18 (unsigned int insn, int op, int *rt, int *i18)
463{
464 if ((insn >> 25) == op)
465 {
466 *rt = insn & 127;
467 *i18 = (((insn >> 7) & 0x3ffff) ^ 0x20000) - 0x20000;
468 return 1;
469 }
470
471 return 0;
472}
473
474static int
475is_branch (unsigned int insn, int *offset, int *reg)
476{
477 int rt, i7, i16;
478
479 if (is_ri16 (insn, op_br, &rt, &i16)
480 || is_ri16 (insn, op_brsl, &rt, &i16)
481 || is_ri16 (insn, op_brnz, &rt, &i16)
482 || is_ri16 (insn, op_brz, &rt, &i16)
483 || is_ri16 (insn, op_brhnz, &rt, &i16)
484 || is_ri16 (insn, op_brhz, &rt, &i16))
485 {
486 *reg = SPU_PC_REGNUM;
487 *offset = i16 << 2;
488 return 1;
489 }
490
491 if (is_ri16 (insn, op_bra, &rt, &i16)
492 || is_ri16 (insn, op_brasl, &rt, &i16))
493 {
494 *reg = -1;
495 *offset = i16 << 2;
496 return 1;
497 }
498
499 if (is_ri7 (insn, op_bi, &rt, reg, &i7)
500 || is_ri7 (insn, op_bisl, &rt, reg, &i7)
501 || is_ri7 (insn, op_biz, &rt, reg, &i7)
502 || is_ri7 (insn, op_binz, &rt, reg, &i7)
503 || is_ri7 (insn, op_bihz, &rt, reg, &i7)
504 || is_ri7 (insn, op_bihnz, &rt, reg, &i7))
505 {
506 *offset = 0;
507 return 1;
508 }
509
510 return 0;
511}
512
513
514/* Prolog parsing. */
515
516struct spu_prologue_data
517 {
518 /* Stack frame size. -1 if analysis was unsuccessful. */
519 int size;
520
521 /* How to find the CFA. The CFA is equal to SP at function entry. */
522 int cfa_reg;
523 int cfa_offset;
524
525 /* Offset relative to CFA where a register is saved. -1 if invalid. */
526 int reg_offset[SPU_NUM_GPRS];
527 };
528
529static CORE_ADDR
530spu_analyze_prologue (CORE_ADDR start_pc, CORE_ADDR end_pc,
531 struct spu_prologue_data *data)
532{
533 int found_sp = 0;
534 int found_fp = 0;
535 int found_lr = 0;
536 int reg_immed[SPU_NUM_GPRS];
537 gdb_byte buf[16];
538 CORE_ADDR prolog_pc = start_pc;
539 CORE_ADDR pc;
540 int i;
541
542
543 /* Initialize DATA to default values. */
544 data->size = -1;
545
546 data->cfa_reg = SPU_RAW_SP_REGNUM;
547 data->cfa_offset = 0;
548
549 for (i = 0; i < SPU_NUM_GPRS; i++)
550 data->reg_offset[i] = -1;
551
552 /* Set up REG_IMMED array. This is non-zero for a register if we know its
553 preferred slot currently holds this immediate value. */
554 for (i = 0; i < SPU_NUM_GPRS; i++)
555 reg_immed[i] = 0;
556
557 /* Scan instructions until the first branch.
558
559 The following instructions are important prolog components:
560
561 - The first instruction to set up the stack pointer.
562 - The first instruction to set up the frame pointer.
563 - The first instruction to save the link register.
564
565 We return the instruction after the latest of these three,
566 or the incoming PC if none is found. The first instruction
567 to set up the stack pointer also defines the frame size.
568
569 Note that instructions saving incoming arguments to their stack
570 slots are not counted as important, because they are hard to
571 identify with certainty. This should not matter much, because
572 arguments are relevant only in code compiled with debug data,
573 and in such code the GDB core will advance until the first source
574 line anyway, using SAL data.
575
576 For purposes of stack unwinding, we analyze the following types
577 of instructions in addition:
578
579 - Any instruction adding to the current frame pointer.
580 - Any instruction loading an immediate constant into a register.
581 - Any instruction storing a register onto the stack.
582
583 These are used to compute the CFA and REG_OFFSET output. */
584
585 for (pc = start_pc; pc < end_pc; pc += 4)
586 {
587 unsigned int insn;
588 int rt, ra, rb, rc, immed;
589
590 if (target_read_memory (pc, buf, 4))
591 break;
592 insn = extract_unsigned_integer (buf, 4);
593
594 /* AI is the typical instruction to set up a stack frame.
595 It is also used to initialize the frame pointer. */
596 if (is_ri10 (insn, op_ai, &rt, &ra, &immed))
597 {
598 if (rt == data->cfa_reg && ra == data->cfa_reg)
599 data->cfa_offset -= immed;
600
601 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
602 && !found_sp)
603 {
604 found_sp = 1;
605 prolog_pc = pc + 4;
606
607 data->size = -immed;
608 }
609 else if (rt == SPU_FP_REGNUM && ra == SPU_RAW_SP_REGNUM
610 && !found_fp)
611 {
612 found_fp = 1;
613 prolog_pc = pc + 4;
614
615 data->cfa_reg = SPU_FP_REGNUM;
616 data->cfa_offset -= immed;
617 }
618 }
619
620 /* A is used to set up stack frames of size >= 512 bytes.
621 If we have tracked the contents of the addend register,
622 we can handle this as well. */
623 else if (is_rr (insn, op_a, &rt, &ra, &rb))
624 {
625 if (rt == data->cfa_reg && ra == data->cfa_reg)
626 {
627 if (reg_immed[rb] != 0)
628 data->cfa_offset -= reg_immed[rb];
629 else
630 data->cfa_reg = -1; /* We don't know the CFA any more. */
631 }
632
633 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
634 && !found_sp)
635 {
636 found_sp = 1;
637 prolog_pc = pc + 4;
638
639 if (reg_immed[rb] != 0)
640 data->size = -reg_immed[rb];
641 }
642 }
643
644 /* We need to track IL and ILA used to load immediate constants
645 in case they are later used as input to an A instruction. */
646 else if (is_ri16 (insn, op_il, &rt, &immed))
647 {
648 reg_immed[rt] = immed;
12102450
UW		 649
650 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
651 found_sp = 1;
771b4502
UW		 652 }
653
654 else if (is_ri18 (insn, op_ila, &rt, &immed))
655 {
656 reg_immed[rt] = immed & 0x3ffff;
12102450
UW		 657
658 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
659 found_sp = 1;
771b4502
UW		 660 }
661
662 /* STQD is used to save registers to the stack. */
663 else if (is_ri10 (insn, op_stqd, &rt, &ra, &immed))
664 {
665 if (ra == data->cfa_reg)
666 data->reg_offset[rt] = data->cfa_offset - (immed << 4);
667
668 if (ra == data->cfa_reg && rt == SPU_LR_REGNUM
669 && !found_lr)
670 {
671 found_lr = 1;
672 prolog_pc = pc + 4;
673 }
674 }
675
676 /* _start uses SELB to set up the stack pointer. */
677 else if (is_rrr (insn, op_selb, &rt, &ra, &rb, &rc))
678 {
679 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
680 found_sp = 1;
681 }
682
683 /* We terminate if we find a branch. */
684 else if (is_branch (insn, &immed, &ra))
685 break;
686 }
687
688
689 /* If we successfully parsed until here, and didn't find any instruction
690 modifying SP, we assume we have a frameless function. */
691 if (!found_sp)
692 data->size = 0;
693
694 /* Return cooked instead of raw SP. */
695 if (data->cfa_reg == SPU_RAW_SP_REGNUM)
696 data->cfa_reg = SPU_SP_REGNUM;
697
698 return prolog_pc;
699}
700
701/* Return the first instruction after the prologue starting at PC. */
702static CORE_ADDR
6093d2eb 703spu_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
771b4502
UW		 704{
705 struct spu_prologue_data data;
706 return spu_analyze_prologue (pc, (CORE_ADDR)-1, &data);
707}
708
709/* Return the frame pointer in use at address PC. */
710static void
a54fba4c
MD		 711spu_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc,
712 int *reg, LONGEST *offset)
771b4502
UW		 713{
714 struct spu_prologue_data data;
715 spu_analyze_prologue (pc, (CORE_ADDR)-1, &data);
716
717 if (data.size != -1 && data.cfa_reg != -1)
718 {
719 /* The 'frame pointer' address is CFA minus frame size. */
720 *reg = data.cfa_reg;
721 *offset = data.cfa_offset - data.size;
722 }
723 else
724 {
725 /* ??? We don't really know ... */
726 *reg = SPU_SP_REGNUM;
727 *offset = 0;
728 }
729}
730
fe5febed
UW		 731/* Return true if we are in the function's epilogue, i.e. after the
732 instruction that destroyed the function's stack frame.
733
734 1) scan forward from the point of execution:
735 a) If you find an instruction that modifies the stack pointer
736 or transfers control (except a return), execution is not in
737 an epilogue, return.
738 b) Stop scanning if you find a return instruction or reach the
739 end of the function or reach the hard limit for the size of
740 an epilogue.
741 2) scan backward from the point of execution:
742 a) If you find an instruction that modifies the stack pointer,
743 execution *is* in an epilogue, return.
744 b) Stop scanning if you reach an instruction that transfers
745 control or the beginning of the function or reach the hard
746 limit for the size of an epilogue. */
747
748static int
749spu_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
750{
751 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
752 bfd_byte buf[4];
753 unsigned int insn;
754 int rt, ra, rb, rc, immed;
755
756 /* Find the search limits based on function boundaries and hard limit.
757 We assume the epilogue can be up to 64 instructions long. */
758
759 const int spu_max_epilogue_size = 64 * 4;
760
761 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
762 return 0;
763
764 if (pc - func_start < spu_max_epilogue_size)
765 epilogue_start = func_start;
766 else
767 epilogue_start = pc - spu_max_epilogue_size;
768
769 if (func_end - pc < spu_max_epilogue_size)
770 epilogue_end = func_end;
771 else
772 epilogue_end = pc + spu_max_epilogue_size;
773
774 /* Scan forward until next 'bi $0'. */
775
776 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += 4)
777 {
778 if (target_read_memory (scan_pc, buf, 4))
779 return 0;
780 insn = extract_unsigned_integer (buf, 4);
781
782 if (is_branch (insn, &immed, &ra))
783 {
784 if (immed == 0 && ra == SPU_LR_REGNUM)
785 break;
786
787 return 0;
788 }
789
790 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
791 || is_rr (insn, op_a, &rt, &ra, &rb)
792 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
793 {
794 if (rt == SPU_RAW_SP_REGNUM)
795 return 0;
796 }
797 }
798
799 if (scan_pc >= epilogue_end)
800 return 0;
801
802 /* Scan backward until adjustment to stack pointer (R1). */
803
804 for (scan_pc = pc - 4; scan_pc >= epilogue_start; scan_pc -= 4)
805 {
806 if (target_read_memory (scan_pc, buf, 4))
807 return 0;
808 insn = extract_unsigned_integer (buf, 4);
809
810 if (is_branch (insn, &immed, &ra))
811 return 0;
812
813 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
814 || is_rr (insn, op_a, &rt, &ra, &rb)
815 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
816 {
817 if (rt == SPU_RAW_SP_REGNUM)
818 return 1;
819 }
820 }
821
822 return 0;
823}
824
825
771b4502
UW		 826/* Normal stack frames. */
827
828struct spu_unwind_cache
829{
830 CORE_ADDR func;
831 CORE_ADDR frame_base;
832 CORE_ADDR local_base;
833
834 struct trad_frame_saved_reg *saved_regs;
835};
836
837static struct spu_unwind_cache *
8d998b8f 838spu_frame_unwind_cache (struct frame_info *this_frame,
771b4502
UW		 839 void **this_prologue_cache)
840{
841 struct spu_unwind_cache *info;
842 struct spu_prologue_data data;
dcf52cd8 843 gdb_byte buf[16];
771b4502
UW		 844
845 if (*this_prologue_cache)
846 return *this_prologue_cache;
847
848 info = FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache);
849 *this_prologue_cache = info;
8d998b8f 850 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
771b4502
UW		 851 info->frame_base = 0;
852 info->local_base = 0;
853
854 /* Find the start of the current function, and analyze its prologue. */
8d998b8f 855 info->func = get_frame_func (this_frame);
771b4502
UW		 856 if (info->func == 0)
857 {
858 /* Fall back to using the current PC as frame ID. */
8d998b8f 859 info->func = get_frame_pc (this_frame);
771b4502
UW		 860 data.size = -1;
861 }
862 else
8d998b8f 863 spu_analyze_prologue (info->func, get_frame_pc (this_frame), &data);
771b4502
UW		 864
865
866 /* If successful, use prologue analysis data. */
867 if (data.size != -1 && data.cfa_reg != -1)
868 {
869 CORE_ADDR cfa;
870 int i;
771b4502
UW		 871
872 /* Determine CFA via unwound CFA_REG plus CFA_OFFSET. */
8d998b8f 873 get_frame_register (this_frame, data.cfa_reg, buf);
771b4502
UW		 874 cfa = extract_unsigned_integer (buf, 4) + data.cfa_offset;
875
876 /* Call-saved register slots. */
877 for (i = 0; i < SPU_NUM_GPRS; i++)
878 if (i == SPU_LR_REGNUM
879 || (i >= SPU_SAVED1_REGNUM && i <= SPU_SAVEDN_REGNUM))
880 if (data.reg_offset[i] != -1)
881 info->saved_regs[i].addr = cfa - data.reg_offset[i];
882
771b4502
UW		 883 /* Frame bases. */
884 info->frame_base = cfa;
885 info->local_base = cfa - data.size;
886 }
887
888 /* Otherwise, fall back to reading the backchain link. */
889 else
890 {
cdc9523a
UW		 891 CORE_ADDR reg;
892 LONGEST backchain;
893 int status;
771b4502
UW		 894
895 /* Get the backchain. */
8d998b8f 896 reg = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
cdc9523a 897 status = safe_read_memory_integer (reg, 4, &backchain);
771b4502
UW		 898
899 /* A zero backchain terminates the frame chain. Also, sanity
900 check against the local store size limit. */
cdc9523a 901 if (status && backchain > 0 && backchain < SPU_LS_SIZE)
771b4502
UW		 902 {
903 /* Assume the link register is saved into its slot. */
904 if (backchain + 16 < SPU_LS_SIZE)
905 info->saved_regs[SPU_LR_REGNUM].addr = backchain + 16;
906
771b4502
UW		 907 /* Frame bases. */
908 info->frame_base = backchain;
909 info->local_base = reg;
910 }
911 }
dcf52cd8 912
c4891da7
UW		 913 /* If we didn't find a frame, we cannot determine SP / return address. */
914 if (info->frame_base == 0)
915 return info;
916
dcf52cd8
UW		 917 /* The previous SP is equal to the CFA. */
918 trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM, info->frame_base);
919
0a44cb36
UW		 920 /* Read full contents of the unwound link register in order to
921 be able to determine the return address. */
dcf52cd8
UW		 922 if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM))
923 target_read_memory (info->saved_regs[SPU_LR_REGNUM].addr, buf, 16);
924 else
8d998b8f 925 get_frame_register (this_frame, SPU_LR_REGNUM, buf);
dcf52cd8 926
0a44cb36
UW		 927 /* Normally, the return address is contained in the slot 0 of the
928 link register, and slots 1-3 are zero. For an overlay return,
929 slot 0 contains the address of the overlay manager return stub,
930 slot 1 contains the partition number of the overlay section to
931 be returned to, and slot 2 contains the return address within
932 that section. Return the latter address in that case. */
dcf52cd8
UW		 933 if (extract_unsigned_integer (buf + 8, 4) != 0)
934 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
935 extract_unsigned_integer (buf + 8, 4));
936 else
937 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
938 extract_unsigned_integer (buf, 4));
771b4502
UW		 939
940 return info;
941}
942
943static void
8d998b8f 944spu_frame_this_id (struct frame_info *this_frame,
771b4502
UW		 945 void **this_prologue_cache, struct frame_id *this_id)
946{
947 struct spu_unwind_cache *info =
8d998b8f 948 spu_frame_unwind_cache (this_frame, this_prologue_cache);
771b4502
UW		 949
950 if (info->frame_base == 0)
951 return;
952
953 *this_id = frame_id_build (info->frame_base, info->func);
954}
955
8d998b8f
UW		 956static struct value *
957spu_frame_prev_register (struct frame_info *this_frame,
958 void **this_prologue_cache, int regnum)
771b4502
UW		 959{
960 struct spu_unwind_cache *info
8d998b8f 961 = spu_frame_unwind_cache (this_frame, this_prologue_cache);
771b4502
UW		 962
963 /* Special-case the stack pointer. */
964 if (regnum == SPU_RAW_SP_REGNUM)
965 regnum = SPU_SP_REGNUM;
966
8d998b8f 967 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
771b4502
UW		 968}
969
970static const struct frame_unwind spu_frame_unwind = {
971 NORMAL_FRAME,
972 spu_frame_this_id,
8d998b8f
UW		 973 spu_frame_prev_register,
974 NULL,
975 default_frame_sniffer
771b4502
UW		 976};
977
771b4502 978static CORE_ADDR
8d998b8f 979spu_frame_base_address (struct frame_info *this_frame, void **this_cache)
771b4502
UW		 980{
981 struct spu_unwind_cache *info
8d998b8f 982 = spu_frame_unwind_cache (this_frame, this_cache);
771b4502
UW		 983 return info->local_base;
984}
985
986static const struct frame_base spu_frame_base = {
987 &spu_frame_unwind,
988 spu_frame_base_address,
989 spu_frame_base_address,
990 spu_frame_base_address
991};
992
993static CORE_ADDR
994spu_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
995{
118dfbaf
UW		 996 CORE_ADDR pc = frame_unwind_register_unsigned (next_frame, SPU_PC_REGNUM);
997 /* Mask off interrupt enable bit. */
998 return pc & -4;
771b4502
UW		 999}
1000
1001static CORE_ADDR
1002spu_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1003{
1004 return frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM);
1005}
1006
118dfbaf 1007static CORE_ADDR
61a1198a 1008spu_read_pc (struct regcache *regcache)
118dfbaf 1009{
61a1198a
UW		 1010 ULONGEST pc;
1011 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &pc);
118dfbaf
UW		 1012 /* Mask off interrupt enable bit. */
1013 return pc & -4;
1014}
1015
1016static void
61a1198a 1017spu_write_pc (struct regcache *regcache, CORE_ADDR pc)
118dfbaf
UW		 1018{
1019 /* Keep interrupt enabled state unchanged. */
61a1198a
UW		 1020 ULONGEST old_pc;
1021 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &old_pc);
1022 regcache_cooked_write_unsigned (regcache, SPU_PC_REGNUM,
1023 (pc & -4) | (old_pc & 3));
118dfbaf
UW		 1024}
1025
771b4502
UW		 1026
1027/* Function calling convention. */
1028
7b3dc0b7
UW		 1029static CORE_ADDR
1030spu_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1031{
1032 return sp & ~15;
1033}
1034
87805e63
UW		 1035static CORE_ADDR
1036spu_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
1037 struct value **args, int nargs, struct type *value_type,
1038 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
1039 struct regcache *regcache)
1040{
1041 /* Allocate space sufficient for a breakpoint, keeping the stack aligned. */
1042 sp = (sp - 4) & ~15;
1043 /* Store the address of that breakpoint */
1044 *bp_addr = sp;
1045 /* The call starts at the callee's entry point. */
1046 *real_pc = funaddr;
1047
1048 return sp;
1049}
1050
771b4502
UW		 1051static int
1052spu_scalar_value_p (struct type *type)
1053{
1054 switch (TYPE_CODE (type))
1055 {
1056 case TYPE_CODE_INT:
1057 case TYPE_CODE_ENUM:
1058 case TYPE_CODE_RANGE:
1059 case TYPE_CODE_CHAR:
1060 case TYPE_CODE_BOOL:
1061 case TYPE_CODE_PTR:
1062 case TYPE_CODE_REF:
1063 return TYPE_LENGTH (type) <= 16;
1064
1065 default:
1066 return 0;
1067 }
1068}
1069
1070static void
1071spu_value_to_regcache (struct regcache *regcache, int regnum,
1072 struct type *type, const gdb_byte *in)
1073{
1074 int len = TYPE_LENGTH (type);
1075
1076 if (spu_scalar_value_p (type))
1077 {
1078 int preferred_slot = len < 4 ? 4 - len : 0;
1079 regcache_cooked_write_part (regcache, regnum, preferred_slot, len, in);
1080 }
1081 else
1082 {
1083 while (len >= 16)
1084 {
1085 regcache_cooked_write (regcache, regnum++, in);
1086 in += 16;
1087 len -= 16;
1088 }
1089
1090 if (len > 0)
1091 regcache_cooked_write_part (regcache, regnum, 0, len, in);
1092 }
1093}
1094
1095static void
1096spu_regcache_to_value (struct regcache *regcache, int regnum,
1097 struct type *type, gdb_byte *out)
1098{
1099 int len = TYPE_LENGTH (type);
1100
1101 if (spu_scalar_value_p (type))
1102 {
1103 int preferred_slot = len < 4 ? 4 - len : 0;
1104 regcache_cooked_read_part (regcache, regnum, preferred_slot, len, out);
1105 }
1106 else
1107 {
1108 while (len >= 16)
1109 {
1110 regcache_cooked_read (regcache, regnum++, out);
1111 out += 16;
1112 len -= 16;
1113 }
1114
1115 if (len > 0)
1116 regcache_cooked_read_part (regcache, regnum, 0, len, out);
1117 }
1118}
1119
1120static CORE_ADDR
1121spu_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1122 struct regcache *regcache, CORE_ADDR bp_addr,
1123 int nargs, struct value **args, CORE_ADDR sp,
1124 int struct_return, CORE_ADDR struct_addr)
1125{
9ff3afda 1126 CORE_ADDR sp_delta;
771b4502
UW		 1127 int i;
1128 int regnum = SPU_ARG1_REGNUM;
1129 int stack_arg = -1;
1130 gdb_byte buf[16];
1131
1132 /* Set the return address. */
1133 memset (buf, 0, sizeof buf);
1134 store_unsigned_integer (buf, 4, bp_addr);
1135 regcache_cooked_write (regcache, SPU_LR_REGNUM, buf);
1136
1137 /* If STRUCT_RETURN is true, then the struct return address (in
1138 STRUCT_ADDR) will consume the first argument-passing register.
1139 Both adjust the register count and store that value. */
1140 if (struct_return)
1141 {
1142 memset (buf, 0, sizeof buf);
1143 store_unsigned_integer (buf, 4, struct_addr);
1144 regcache_cooked_write (regcache, regnum++, buf);
1145 }
1146
1147 /* Fill in argument registers. */
1148 for (i = 0; i < nargs; i++)
1149 {
1150 struct value *arg = args[i];
1151 struct type *type = check_typedef (value_type (arg));
1152 const gdb_byte *contents = value_contents (arg);
1153 int len = TYPE_LENGTH (type);
1154 int n_regs = align_up (len, 16) / 16;
1155
1156 /* If the argument doesn't wholly fit into registers, it and
1157 all subsequent arguments go to the stack. */
1158 if (regnum + n_regs - 1 > SPU_ARGN_REGNUM)
1159 {
1160 stack_arg = i;
1161 break;
1162 }
1163
1164 spu_value_to_regcache (regcache, regnum, type, contents);
1165 regnum += n_regs;
1166 }
1167
1168 /* Overflow arguments go to the stack. */
1169 if (stack_arg != -1)
1170 {
1171 CORE_ADDR ap;
1172
1173 /* Allocate all required stack size. */
1174 for (i = stack_arg; i < nargs; i++)
1175 {
1176 struct type *type = check_typedef (value_type (args[i]));
1177 sp -= align_up (TYPE_LENGTH (type), 16);
1178 }
1179
1180 /* Fill in stack arguments. */
1181 ap = sp;
1182 for (i = stack_arg; i < nargs; i++)
1183 {
1184 struct value *arg = args[i];
1185 struct type *type = check_typedef (value_type (arg));
1186 int len = TYPE_LENGTH (type);
1187 int preferred_slot;
1188
1189 if (spu_scalar_value_p (type))
1190 preferred_slot = len < 4 ? 4 - len : 0;
1191 else
1192 preferred_slot = 0;
1193
1194 target_write_memory (ap + preferred_slot, value_contents (arg), len);
1195 ap += align_up (TYPE_LENGTH (type), 16);
1196 }
1197 }
1198
1199 /* Allocate stack frame header. */
1200 sp -= 32;
1201
ee82e879
UW		 1202 /* Store stack back chain. */
1203 regcache_cooked_read (regcache, SPU_RAW_SP_REGNUM, buf);
1204 target_write_memory (sp, buf, 16);
1205
9ff3afda
UW		 1206 /* Finally, update all slots of the SP register. */
1207 sp_delta = sp - extract_unsigned_integer (buf, 4);
1208 for (i = 0; i < 4; i++)
1209 {
1210 CORE_ADDR sp_slot = extract_unsigned_integer (buf + 4*i, 4);
1211 store_unsigned_integer (buf + 4*i, 4, sp_slot + sp_delta);
1212 }
1213 regcache_cooked_write (regcache, SPU_RAW_SP_REGNUM, buf);
771b4502
UW		 1214
1215 return sp;
1216}
1217
1218static struct frame_id
8d998b8f 1219spu_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
771b4502 1220{
8d998b8f
UW		 1221 CORE_ADDR pc = get_frame_register_unsigned (this_frame, SPU_PC_REGNUM);
1222 CORE_ADDR sp = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
1223 return frame_id_build (sp, pc & -4);
771b4502
UW		 1224}
1225
1226/* Function return value access. */
1227
1228static enum return_value_convention
c055b101
CV		 1229spu_return_value (struct gdbarch *gdbarch, struct type *func_type,
1230 struct type *type, struct regcache *regcache,
1231 gdb_byte *out, const gdb_byte *in)
771b4502
UW		 1232{
1233 enum return_value_convention rvc;
1234
1235 if (TYPE_LENGTH (type) <= (SPU_ARGN_REGNUM - SPU_ARG1_REGNUM + 1) * 16)
1236 rvc = RETURN_VALUE_REGISTER_CONVENTION;
1237 else
1238 rvc = RETURN_VALUE_STRUCT_CONVENTION;
1239
1240 if (in)
1241 {
1242 switch (rvc)
1243 {
1244 case RETURN_VALUE_REGISTER_CONVENTION:
1245 spu_value_to_regcache (regcache, SPU_ARG1_REGNUM, type, in);
1246 break;
1247
1248 case RETURN_VALUE_STRUCT_CONVENTION:
1249 error ("Cannot set function return value.");
1250 break;
1251 }
1252 }
1253 else if (out)
1254 {
1255 switch (rvc)
1256 {
1257 case RETURN_VALUE_REGISTER_CONVENTION:
1258 spu_regcache_to_value (regcache, SPU_ARG1_REGNUM, type, out);
1259 break;
1260
1261 case RETURN_VALUE_STRUCT_CONVENTION:
1262 error ("Function return value unknown.");
1263 break;
1264 }
1265 }
1266
1267 return rvc;
1268}
1269
1270
1271/* Breakpoints. */
1272
1273static const gdb_byte *
67d57894 1274spu_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR * pcptr, int *lenptr)
771b4502
UW		 1275{
1276 static const gdb_byte breakpoint[] = { 0x00, 0x00, 0x3f, 0xff };
1277
1278 *lenptr = sizeof breakpoint;
1279 return breakpoint;
1280}
1281
1282
1283/* Software single-stepping support. */
1284
e6590a1b 1285int
0b1b3e42 1286spu_software_single_step (struct frame_info *frame)
771b4502 1287{
e0cd558a
UW		 1288 CORE_ADDR pc, next_pc;
1289 unsigned int insn;
1290 int offset, reg;
1291 gdb_byte buf[4];
771b4502 1292
0b1b3e42 1293 pc = get_frame_pc (frame);
771b4502 1294
e0cd558a
UW		 1295 if (target_read_memory (pc, buf, 4))
1296 return 1;
1297 insn = extract_unsigned_integer (buf, 4);
771b4502 1298
e0cd558a
UW		 1299 /* Next sequential instruction is at PC + 4, except if the current
1300 instruction is a PPE-assisted call, in which case it is at PC + 8.
1301 Wrap around LS limit to be on the safe side. */
1302 if ((insn & 0xffffff00) == 0x00002100)
1303 next_pc = (pc + 8) & (SPU_LS_SIZE - 1);
1304 else
1305 next_pc = (pc + 4) & (SPU_LS_SIZE - 1);
771b4502 1306
e0cd558a 1307 insert_single_step_breakpoint (next_pc);
771b4502 1308
e0cd558a
UW		 1309 if (is_branch (insn, &offset, &reg))
1310 {
1311 CORE_ADDR target = offset;
771b4502 1312
e0cd558a
UW		 1313 if (reg == SPU_PC_REGNUM)
1314 target += pc;
1315 else if (reg != -1)
1316 {
0b1b3e42 1317 get_frame_register_bytes (frame, reg, 0, 4, buf);
e0cd558a 1318 target += extract_unsigned_integer (buf, 4) & -4;
771b4502 1319 }
e0cd558a
UW		 1320
1321 target = target & (SPU_LS_SIZE - 1);
1322 if (target != next_pc)
1323 insert_single_step_breakpoint (target);
771b4502 1324 }
e6590a1b
UW		 1325
1326 return 1;
771b4502
UW		 1327}
1328
dcf52cd8
UW		 1329/* Target overlays for the SPU overlay manager.
1330
1331 See the documentation of simple_overlay_update for how the
1332 interface is supposed to work.
1333
1334 Data structures used by the overlay manager:
1335
1336 struct ovly_table
1337 {
1338 u32 vma;
1339 u32 size;
1340 u32 pos;
1341 u32 buf;
1342 } _ovly_table[]; -- one entry per overlay section
1343
1344 struct ovly_buf_table
1345 {
1346 u32 mapped;
1347 } _ovly_buf_table[]; -- one entry per overlay buffer
1348
1349 _ovly_table should never change.
1350
1351 Both tables are aligned to a 16-byte boundary, the symbols _ovly_table
1352 and _ovly_buf_table are of type STT_OBJECT and their size set to the size
1353 of the respective array. buf in _ovly_table is an index into _ovly_buf_table.
1354
1355 mapped is an index into _ovly_table. Both the mapped and buf indices start
1356 from one to reference the first entry in their respective tables. */
1357
1358/* Using the per-objfile private data mechanism, we store for each
1359 objfile an array of "struct spu_overlay_table" structures, one
1360 for each obj_section of the objfile. This structure holds two
1361 fields, MAPPED_PTR and MAPPED_VAL. If MAPPED_PTR is zero, this
1362 is *not* an overlay section. If it is non-zero, it represents
1363 a target address. The overlay section is mapped iff the target
1364 integer at this location equals MAPPED_VAL. */
1365
1366static const struct objfile_data *spu_overlay_data;
1367
1368struct spu_overlay_table
1369 {
1370 CORE_ADDR mapped_ptr;
1371 CORE_ADDR mapped_val;
1372 };
1373
1374/* Retrieve the overlay table for OBJFILE. If not already cached, read
1375 the _ovly_table data structure from the target and initialize the
1376 spu_overlay_table data structure from it. */
1377static struct spu_overlay_table *
1378spu_get_overlay_table (struct objfile *objfile)
1379{
1380 struct minimal_symbol *ovly_table_msym, *ovly_buf_table_msym;
1381 CORE_ADDR ovly_table_base, ovly_buf_table_base;
1382 unsigned ovly_table_size, ovly_buf_table_size;
1383 struct spu_overlay_table *tbl;
1384 struct obj_section *osect;
1385 char *ovly_table;
1386 int i;
1387
1388 tbl = objfile_data (objfile, spu_overlay_data);
1389 if (tbl)
1390 return tbl;
1391
1392 ovly_table_msym = lookup_minimal_symbol ("_ovly_table", NULL, objfile);
1393 if (!ovly_table_msym)
1394 return NULL;
1395
1396 ovly_buf_table_msym = lookup_minimal_symbol ("_ovly_buf_table", NULL, objfile);
1397 if (!ovly_buf_table_msym)
1398 return NULL;
1399
1400 ovly_table_base = SYMBOL_VALUE_ADDRESS (ovly_table_msym);
1401 ovly_table_size = MSYMBOL_SIZE (ovly_table_msym);
1402
1403 ovly_buf_table_base = SYMBOL_VALUE_ADDRESS (ovly_buf_table_msym);
1404 ovly_buf_table_size = MSYMBOL_SIZE (ovly_buf_table_msym);
1405
1406 ovly_table = xmalloc (ovly_table_size);
1407 read_memory (ovly_table_base, ovly_table, ovly_table_size);
1408
1409 tbl = OBSTACK_CALLOC (&objfile->objfile_obstack,
1410 objfile->sections_end - objfile->sections,
1411 struct spu_overlay_table);
1412
1413 for (i = 0; i < ovly_table_size / 16; i++)
1414 {
1415 CORE_ADDR vma = extract_unsigned_integer (ovly_table + 16*i + 0, 4);
1416 CORE_ADDR size = extract_unsigned_integer (ovly_table + 16*i + 4, 4);
1417 CORE_ADDR pos = extract_unsigned_integer (ovly_table + 16*i + 8, 4);
1418 CORE_ADDR buf = extract_unsigned_integer (ovly_table + 16*i + 12, 4);
1419
1420 if (buf == 0 || (buf - 1) * 4 >= ovly_buf_table_size)
1421 continue;
1422
1423 ALL_OBJFILE_OSECTIONS (objfile, osect)
1424 if (vma == bfd_section_vma (objfile->obfd, osect->the_bfd_section)
1425 && pos == osect->the_bfd_section->filepos)
1426 {
1427 int ndx = osect - objfile->sections;
1428 tbl[ndx].mapped_ptr = ovly_buf_table_base + (buf - 1) * 4;
1429 tbl[ndx].mapped_val = i + 1;
1430 break;
1431 }
1432 }
1433
1434 xfree (ovly_table);
1435 set_objfile_data (objfile, spu_overlay_data, tbl);
1436 return tbl;
1437}
1438
1439/* Read _ovly_buf_table entry from the target to dermine whether
1440 OSECT is currently mapped, and update the mapped state. */
1441static void
1442spu_overlay_update_osect (struct obj_section *osect)
1443{
1444 struct spu_overlay_table *ovly_table;
1445 CORE_ADDR val;
1446
1447 ovly_table = spu_get_overlay_table (osect->objfile);
1448 if (!ovly_table)
1449 return;
1450
1451 ovly_table += osect - osect->objfile->sections;
1452 if (ovly_table->mapped_ptr == 0)
1453 return;
1454
1455 val = read_memory_unsigned_integer (ovly_table->mapped_ptr, 4);
1456 osect->ovly_mapped = (val == ovly_table->mapped_val);
1457}
1458
1459/* If OSECT is NULL, then update all sections' mapped state.
1460 If OSECT is non-NULL, then update only OSECT's mapped state. */
1461static void
1462spu_overlay_update (struct obj_section *osect)
1463{
1464 /* Just one section. */
1465 if (osect)
1466 spu_overlay_update_osect (osect);
1467
1468 /* All sections. */
1469 else
1470 {
1471 struct objfile *objfile;
1472
1473 ALL_OBJSECTIONS (objfile, osect)
714835d5 1474 if (section_is_overlay (osect))
dcf52cd8
UW		 1475 spu_overlay_update_osect (osect);
1476 }
1477}
1478
1479/* Whenever a new objfile is loaded, read the target's _ovly_table.
1480 If there is one, go through all sections and make sure for non-
1481 overlay sections LMA equals VMA, while for overlay sections LMA
1482 is larger than local store size. */
1483static void
1484spu_overlay_new_objfile (struct objfile *objfile)
1485{
1486 struct spu_overlay_table *ovly_table;
1487 struct obj_section *osect;
1488
1489 /* If we've already touched this file, do nothing. */
1490 if (!objfile || objfile_data (objfile, spu_overlay_data) != NULL)
1491 return;
1492
0391f248
UW		 1493 /* Consider only SPU objfiles. */
1494 if (bfd_get_arch (objfile->obfd) != bfd_arch_spu)
1495 return;
1496
dcf52cd8
UW		 1497 /* Check if this objfile has overlays. */
1498 ovly_table = spu_get_overlay_table (objfile);
1499 if (!ovly_table)
1500 return;
1501
1502 /* Now go and fiddle with all the LMAs. */
1503 ALL_OBJFILE_OSECTIONS (objfile, osect)
1504 {
1505 bfd *obfd = objfile->obfd;
1506 asection *bsect = osect->the_bfd_section;
1507 int ndx = osect - objfile->sections;
1508
1509 if (ovly_table[ndx].mapped_ptr == 0)
1510 bfd_section_lma (obfd, bsect) = bfd_section_vma (obfd, bsect);
1511 else
1512 bfd_section_lma (obfd, bsect) = bsect->filepos + SPU_LS_SIZE;
1513 }
1514}
1515
771b4502 1516
23d964e7
UW		 1517/* "info spu" commands. */
1518
1519static void
1520info_spu_event_command (char *args, int from_tty)
1521{
1522 struct frame_info *frame = get_selected_frame (NULL);
1523 ULONGEST event_status = 0;
1524 ULONGEST event_mask = 0;
1525 struct cleanup *chain;
1526 gdb_byte buf[100];
1527 char annex[32];
1528 LONGEST len;
1529 int rc, id;
1530
0391f248
UW		 1531 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
1532 error (_("\"info spu\" is only supported on the SPU architecture."));
1533
23d964e7
UW		 1534 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1535
1536 xsnprintf (annex, sizeof annex, "%d/event_status", id);
1537 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 1538 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 1539 if (len <= 0)
1540 error (_("Could not read event_status."));
9971ac47 1541 buf[len] = '\0';
23d964e7
UW		 1542 event_status = strtoulst (buf, NULL, 16);
1543
1544 xsnprintf (annex, sizeof annex, "%d/event_mask", id);
1545 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 1546 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 1547 if (len <= 0)
1548 error (_("Could not read event_mask."));
9971ac47 1549 buf[len] = '\0';
23d964e7
UW		 1550 event_mask = strtoulst (buf, NULL, 16);
1551
1552 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoEvent");
1553
1554 if (ui_out_is_mi_like_p (uiout))
1555 {
1556 ui_out_field_fmt (uiout, "event_status",
1557 "0x%s", phex_nz (event_status, 4));
1558 ui_out_field_fmt (uiout, "event_mask",
1559 "0x%s", phex_nz (event_mask, 4));
1560 }
1561 else
1562 {
1563 printf_filtered (_("Event Status 0x%s\n"), phex (event_status, 4));
1564 printf_filtered (_("Event Mask 0x%s\n"), phex (event_mask, 4));
1565 }
1566
1567 do_cleanups (chain);
1568}
1569
1570static void
1571info_spu_signal_command (char *args, int from_tty)
1572{
1573 struct frame_info *frame = get_selected_frame (NULL);
1574 ULONGEST signal1 = 0;
1575 ULONGEST signal1_type = 0;
1576 int signal1_pending = 0;
1577 ULONGEST signal2 = 0;
1578 ULONGEST signal2_type = 0;
1579 int signal2_pending = 0;
1580 struct cleanup *chain;
1581 char annex[32];
1582 gdb_byte buf[100];
1583 LONGEST len;
1584 int rc, id;
1585
0391f248
UW		 1586 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
1587 error (_("\"info spu\" is only supported on the SPU architecture."));
1588
23d964e7
UW		 1589 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1590
1591 xsnprintf (annex, sizeof annex, "%d/signal1", id);
1592 len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
1593 if (len < 0)
1594 error (_("Could not read signal1."));
1595 else if (len == 4)
1596 {
1597 signal1 = extract_unsigned_integer (buf, 4);
1598 signal1_pending = 1;
1599 }
1600
1601 xsnprintf (annex, sizeof annex, "%d/signal1_type", id);
1602 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 1603 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 1604 if (len <= 0)
1605 error (_("Could not read signal1_type."));
9971ac47 1606 buf[len] = '\0';
23d964e7
UW		 1607 signal1_type = strtoulst (buf, NULL, 16);
1608
1609 xsnprintf (annex, sizeof annex, "%d/signal2", id);
1610 len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
1611 if (len < 0)
1612 error (_("Could not read signal2."));
1613 else if (len == 4)
1614 {
1615 signal2 = extract_unsigned_integer (buf, 4);
1616 signal2_pending = 1;
1617 }
1618
1619 xsnprintf (annex, sizeof annex, "%d/signal2_type", id);
1620 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 1621 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 1622 if (len <= 0)
1623 error (_("Could not read signal2_type."));
9971ac47 1624 buf[len] = '\0';
23d964e7
UW		 1625 signal2_type = strtoulst (buf, NULL, 16);
1626
1627 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoSignal");
1628
1629 if (ui_out_is_mi_like_p (uiout))
1630 {
1631 ui_out_field_int (uiout, "signal1_pending", signal1_pending);
1632 ui_out_field_fmt (uiout, "signal1", "0x%s", phex_nz (signal1, 4));
1633 ui_out_field_int (uiout, "signal1_type", signal1_type);
1634 ui_out_field_int (uiout, "signal2_pending", signal2_pending);
1635 ui_out_field_fmt (uiout, "signal2", "0x%s", phex_nz (signal2, 4));
1636 ui_out_field_int (uiout, "signal2_type", signal2_type);
1637 }
1638 else
1639 {
1640 if (signal1_pending)
1641 printf_filtered (_("Signal 1 control word 0x%s "), phex (signal1, 4));
1642 else
1643 printf_filtered (_("Signal 1 not pending "));
1644
1645 if (signal1_type)
23d964e7 1646 printf_filtered (_("(Type Or)\n"));
b94c4f7d
UW		 1647 else
1648 printf_filtered (_("(Type Overwrite)\n"));
23d964e7
UW		 1649
1650 if (signal2_pending)
1651 printf_filtered (_("Signal 2 control word 0x%s "), phex (signal2, 4));
1652 else
1653 printf_filtered (_("Signal 2 not pending "));
1654
1655 if (signal2_type)
23d964e7 1656 printf_filtered (_("(Type Or)\n"));
b94c4f7d
UW		 1657 else
1658 printf_filtered (_("(Type Overwrite)\n"));
23d964e7
UW		 1659 }
1660
1661 do_cleanups (chain);
1662}
1663
1664static void
1665info_spu_mailbox_list (gdb_byte *buf, int nr,
1666 const char *field, const char *msg)
1667{
1668 struct cleanup *chain;
1669 int i;
1670
1671 if (nr <= 0)
1672 return;
1673
1674 chain = make_cleanup_ui_out_table_begin_end (uiout, 1, nr, "mbox");
1675
1676 ui_out_table_header (uiout, 32, ui_left, field, msg);
1677 ui_out_table_body (uiout);
1678
1679 for (i = 0; i < nr; i++)
1680 {
1681 struct cleanup *val_chain;
1682 ULONGEST val;
1683 val_chain = make_cleanup_ui_out_tuple_begin_end (uiout, "mbox");
1684 val = extract_unsigned_integer (buf + 4*i, 4);
1685 ui_out_field_fmt (uiout, field, "0x%s", phex (val, 4));
1686 do_cleanups (val_chain);
1687
1688 if (!ui_out_is_mi_like_p (uiout))
1689 printf_filtered ("\n");
1690 }
1691
1692 do_cleanups (chain);
1693}
1694
1695static void
1696info_spu_mailbox_command (char *args, int from_tty)
1697{
1698 struct frame_info *frame = get_selected_frame (NULL);
1699 struct cleanup *chain;
1700 char annex[32];
1701 gdb_byte buf[1024];
1702 LONGEST len;
1703 int i, id;
1704
0391f248
UW		 1705 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
1706 error (_("\"info spu\" is only supported on the SPU architecture."));
1707
23d964e7
UW		 1708 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1709
1710 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoMailbox");
1711
1712 xsnprintf (annex, sizeof annex, "%d/mbox_info", id);
1713 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1714 buf, 0, sizeof buf);
1715 if (len < 0)
1716 error (_("Could not read mbox_info."));
1717
1718 info_spu_mailbox_list (buf, len / 4, "mbox", "SPU Outbound Mailbox");
1719
1720 xsnprintf (annex, sizeof annex, "%d/ibox_info", id);
1721 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1722 buf, 0, sizeof buf);
1723 if (len < 0)
1724 error (_("Could not read ibox_info."));
1725
1726 info_spu_mailbox_list (buf, len / 4, "ibox", "SPU Outbound Interrupt Mailbox");
1727
1728 xsnprintf (annex, sizeof annex, "%d/wbox_info", id);
1729 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1730 buf, 0, sizeof buf);
1731 if (len < 0)
1732 error (_("Could not read wbox_info."));
1733
1734 info_spu_mailbox_list (buf, len / 4, "wbox", "SPU Inbound Mailbox");
1735
1736 do_cleanups (chain);
1737}
1738
1739static ULONGEST
1740spu_mfc_get_bitfield (ULONGEST word, int first, int last)
1741{
1742 ULONGEST mask = ~(~(ULONGEST)0 << (last - first + 1));
1743 return (word >> (63 - last)) & mask;
1744}
1745
1746static void
1747info_spu_dma_cmdlist (gdb_byte *buf, int nr)
1748{
1749 static char *spu_mfc_opcode[256] =
1750 {
1751 /* 00 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1752 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1753 /* 10 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1754 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1755 /* 20 */ "put", "putb", "putf", NULL, "putl", "putlb", "putlf", NULL,
1756 "puts", "putbs", "putfs", NULL, NULL, NULL, NULL, NULL,
1757 /* 30 */ "putr", "putrb", "putrf", NULL, "putrl", "putrlb", "putrlf", NULL,
1758 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1759 /* 40 */ "get", "getb", "getf", NULL, "getl", "getlb", "getlf", NULL,
1760 "gets", "getbs", "getfs", NULL, NULL, NULL, NULL, NULL,
1761 /* 50 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1762 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1763 /* 60 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1764 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1765 /* 70 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1766 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1767 /* 80 */ "sdcrt", "sdcrtst", NULL, NULL, NULL, NULL, NULL, NULL,
1768 NULL, "sdcrz", NULL, NULL, NULL, "sdcrst", NULL, "sdcrf",
1769 /* 90 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1770 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1771 /* a0 */ "sndsig", "sndsigb", "sndsigf", NULL, NULL, NULL, NULL, NULL,
1772 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1773 /* b0 */ "putlluc", NULL, NULL, NULL, "putllc", NULL, NULL, NULL,
1774 "putqlluc", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1775 /* c0 */ "barrier", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1776 "mfceieio", NULL, NULL, NULL, "mfcsync", NULL, NULL, NULL,
1777 /* d0 */ "getllar", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1778 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1779 /* e0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1780 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1781 /* f0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1782 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1783 };
1784
12ab8a60
UW		 1785 int *seq = alloca (nr * sizeof (int));
1786 int done = 0;
23d964e7 1787 struct cleanup *chain;
12ab8a60
UW		 1788 int i, j;
1789
1790
1791 /* Determine sequence in which to display (valid) entries. */
1792 for (i = 0; i < nr; i++)
1793 {
1794 /* Search for the first valid entry all of whose
1795 dependencies are met. */
1796 for (j = 0; j < nr; j++)
1797 {
1798 ULONGEST mfc_cq_dw3;
1799 ULONGEST dependencies;
1800
1801 if (done & (1 << (nr - 1 - j)))
1802 continue;
1803
1804 mfc_cq_dw3 = extract_unsigned_integer (buf + 32*j + 24, 8);
1805 if (!spu_mfc_get_bitfield (mfc_cq_dw3, 16, 16))
1806 continue;
1807
1808 dependencies = spu_mfc_get_bitfield (mfc_cq_dw3, 0, nr - 1);
1809 if ((dependencies & done) != dependencies)
1810 continue;
1811
1812 seq[i] = j;
1813 done |= 1 << (nr - 1 - j);
1814 break;
1815 }
1816
1817 if (j == nr)
1818 break;
1819 }
1820
1821 nr = i;
1822
23d964e7
UW		 1823
1824 chain = make_cleanup_ui_out_table_begin_end (uiout, 10, nr, "dma_cmd");
1825
1826 ui_out_table_header (uiout, 7, ui_left, "opcode", "Opcode");
1827 ui_out_table_header (uiout, 3, ui_left, "tag", "Tag");
1828 ui_out_table_header (uiout, 3, ui_left, "tid", "TId");
1829 ui_out_table_header (uiout, 3, ui_left, "rid", "RId");
1830 ui_out_table_header (uiout, 18, ui_left, "ea", "EA");
1831 ui_out_table_header (uiout, 7, ui_left, "lsa", "LSA");
1832 ui_out_table_header (uiout, 7, ui_left, "size", "Size");
1833 ui_out_table_header (uiout, 7, ui_left, "lstaddr", "LstAddr");
1834 ui_out_table_header (uiout, 7, ui_left, "lstsize", "LstSize");
1835 ui_out_table_header (uiout, 1, ui_left, "error_p", "E");
1836
1837 ui_out_table_body (uiout);
1838
1839 for (i = 0; i < nr; i++)
1840 {
1841 struct cleanup *cmd_chain;
1842 ULONGEST mfc_cq_dw0;
1843 ULONGEST mfc_cq_dw1;
1844 ULONGEST mfc_cq_dw2;
23d964e7
UW		 1845 int mfc_cmd_opcode, mfc_cmd_tag, rclass_id, tclass_id;
1846 int lsa, size, list_lsa, list_size, mfc_lsa, mfc_size;
1847 ULONGEST mfc_ea;
1848 int list_valid_p, noop_valid_p, qw_valid_p, ea_valid_p, cmd_error_p;
1849
1850 /* Decode contents of MFC Command Queue Context Save/Restore Registers.
1851 See "Cell Broadband Engine Registers V1.3", section 3.3.2.1. */
1852
12ab8a60
UW		 1853 mfc_cq_dw0 = extract_unsigned_integer (buf + 32*seq[i], 8);
1854 mfc_cq_dw1 = extract_unsigned_integer (buf + 32*seq[i] + 8, 8);
1855 mfc_cq_dw2 = extract_unsigned_integer (buf + 32*seq[i] + 16, 8);
23d964e7
UW		 1856
1857 list_lsa = spu_mfc_get_bitfield (mfc_cq_dw0, 0, 14);
1858 list_size = spu_mfc_get_bitfield (mfc_cq_dw0, 15, 26);
1859 mfc_cmd_opcode = spu_mfc_get_bitfield (mfc_cq_dw0, 27, 34);
1860 mfc_cmd_tag = spu_mfc_get_bitfield (mfc_cq_dw0, 35, 39);
1861 list_valid_p = spu_mfc_get_bitfield (mfc_cq_dw0, 40, 40);
1862 rclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 41, 43);
1863 tclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 44, 46);
1864
1865 mfc_ea = spu_mfc_get_bitfield (mfc_cq_dw1, 0, 51) << 12
1866 | spu_mfc_get_bitfield (mfc_cq_dw2, 25, 36);
1867
1868 mfc_lsa = spu_mfc_get_bitfield (mfc_cq_dw2, 0, 13);
1869 mfc_size = spu_mfc_get_bitfield (mfc_cq_dw2, 14, 24);
1870 noop_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 37, 37);
1871 qw_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 38, 38);
1872 ea_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 39, 39);
1873 cmd_error_p = spu_mfc_get_bitfield (mfc_cq_dw2, 40, 40);
1874
1875 cmd_chain = make_cleanup_ui_out_tuple_begin_end (uiout, "cmd");
1876
1877 if (spu_mfc_opcode[mfc_cmd_opcode])
1878 ui_out_field_string (uiout, "opcode", spu_mfc_opcode[mfc_cmd_opcode]);
1879 else
1880 ui_out_field_int (uiout, "opcode", mfc_cmd_opcode);
1881
1882 ui_out_field_int (uiout, "tag", mfc_cmd_tag);
1883 ui_out_field_int (uiout, "tid", tclass_id);
1884 ui_out_field_int (uiout, "rid", rclass_id);
1885
1886 if (ea_valid_p)
1887 ui_out_field_fmt (uiout, "ea", "0x%s", phex (mfc_ea, 8));
1888 else
1889 ui_out_field_skip (uiout, "ea");
1890
1891 ui_out_field_fmt (uiout, "lsa", "0x%05x", mfc_lsa << 4);
1892 if (qw_valid_p)
1893 ui_out_field_fmt (uiout, "size", "0x%05x", mfc_size << 4);
1894 else
1895 ui_out_field_fmt (uiout, "size", "0x%05x", mfc_size);
1896
1897 if (list_valid_p)
1898 {
1899 ui_out_field_fmt (uiout, "lstaddr", "0x%05x", list_lsa << 3);
1900 ui_out_field_fmt (uiout, "lstsize", "0x%05x", list_size << 3);
1901 }
1902 else
1903 {
1904 ui_out_field_skip (uiout, "lstaddr");
1905 ui_out_field_skip (uiout, "lstsize");
1906 }
1907
1908 if (cmd_error_p)
1909 ui_out_field_string (uiout, "error_p", "*");
1910 else
1911 ui_out_field_skip (uiout, "error_p");
1912
1913 do_cleanups (cmd_chain);
1914
1915 if (!ui_out_is_mi_like_p (uiout))
1916 printf_filtered ("\n");
1917 }
1918
1919 do_cleanups (chain);
1920}
1921
1922static void
1923info_spu_dma_command (char *args, int from_tty)
1924{
1925 struct frame_info *frame = get_selected_frame (NULL);
1926 ULONGEST dma_info_type;
1927 ULONGEST dma_info_mask;
1928 ULONGEST dma_info_status;
1929 ULONGEST dma_info_stall_and_notify;
1930 ULONGEST dma_info_atomic_command_status;
1931 struct cleanup *chain;
1932 char annex[32];
1933 gdb_byte buf[1024];
1934 LONGEST len;
1935 int i, id;
1936
0391f248
UW		 1937 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
1938 error (_("\"info spu\" is only supported on the SPU architecture."));
1939
23d964e7
UW		 1940 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1941
1942 xsnprintf (annex, sizeof annex, "%d/dma_info", id);
1943 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1944 buf, 0, 40 + 16 * 32);
1945 if (len <= 0)
1946 error (_("Could not read dma_info."));
1947
1948 dma_info_type = extract_unsigned_integer (buf, 8);
1949 dma_info_mask = extract_unsigned_integer (buf + 8, 8);
1950 dma_info_status = extract_unsigned_integer (buf + 16, 8);
1951 dma_info_stall_and_notify = extract_unsigned_integer (buf + 24, 8);
1952 dma_info_atomic_command_status = extract_unsigned_integer (buf + 32, 8);
1953
1954 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoDMA");
1955
1956 if (ui_out_is_mi_like_p (uiout))
1957 {
1958 ui_out_field_fmt (uiout, "dma_info_type", "0x%s",
1959 phex_nz (dma_info_type, 4));
1960 ui_out_field_fmt (uiout, "dma_info_mask", "0x%s",
1961 phex_nz (dma_info_mask, 4));
1962 ui_out_field_fmt (uiout, "dma_info_status", "0x%s",
1963 phex_nz (dma_info_status, 4));
1964 ui_out_field_fmt (uiout, "dma_info_stall_and_notify", "0x%s",
1965 phex_nz (dma_info_stall_and_notify, 4));
1966 ui_out_field_fmt (uiout, "dma_info_atomic_command_status", "0x%s",
1967 phex_nz (dma_info_atomic_command_status, 4));
1968 }
1969 else
1970 {
8fbde58b 1971 const char *query_msg = _("no query pending");
23d964e7 1972
8fbde58b
UW		 1973 if (dma_info_type & 4)
1974 switch (dma_info_type & 3)
1975 {
1976 case 1: query_msg = _("'any' query pending"); break;
1977 case 2: query_msg = _("'all' query pending"); break;
1978 default: query_msg = _("undefined query type"); break;
1979 }
23d964e7
UW		 1980
1981 printf_filtered (_("Tag-Group Status 0x%s\n"),
1982 phex (dma_info_status, 4));
1983 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
1984 phex (dma_info_mask, 4), query_msg);
1985 printf_filtered (_("Stall-and-Notify 0x%s\n"),
1986 phex (dma_info_stall_and_notify, 4));
1987 printf_filtered (_("Atomic Cmd Status 0x%s\n"),
1988 phex (dma_info_atomic_command_status, 4));
1989 printf_filtered ("\n");
1990 }
1991
1992 info_spu_dma_cmdlist (buf + 40, 16);
1993 do_cleanups (chain);
1994}
1995
1996static void
1997info_spu_proxydma_command (char *args, int from_tty)
1998{
1999 struct frame_info *frame = get_selected_frame (NULL);
2000 ULONGEST dma_info_type;
2001 ULONGEST dma_info_mask;
2002 ULONGEST dma_info_status;
2003 struct cleanup *chain;
2004 char annex[32];
2005 gdb_byte buf[1024];
2006 LONGEST len;
2007 int i, id;
2008
0391f248
UW		 2009 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
2010 error (_("\"info spu\" is only supported on the SPU architecture."));
2011
23d964e7
UW		 2012 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2013
2014 xsnprintf (annex, sizeof annex, "%d/proxydma_info", id);
2015 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2016 buf, 0, 24 + 8 * 32);
2017 if (len <= 0)
2018 error (_("Could not read proxydma_info."));
2019
2020 dma_info_type = extract_unsigned_integer (buf, 8);
2021 dma_info_mask = extract_unsigned_integer (buf + 8, 8);
2022 dma_info_status = extract_unsigned_integer (buf + 16, 8);
2023
2024 chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoProxyDMA");
2025
2026 if (ui_out_is_mi_like_p (uiout))
2027 {
2028 ui_out_field_fmt (uiout, "proxydma_info_type", "0x%s",
2029 phex_nz (dma_info_type, 4));
2030 ui_out_field_fmt (uiout, "proxydma_info_mask", "0x%s",
2031 phex_nz (dma_info_mask, 4));
2032 ui_out_field_fmt (uiout, "proxydma_info_status", "0x%s",
2033 phex_nz (dma_info_status, 4));
2034 }
2035 else
2036 {
2037 const char *query_msg;
2038
8fbde58b 2039 switch (dma_info_type & 3)
23d964e7
UW		 2040 {
2041 case 0: query_msg = _("no query pending"); break;
2042 case 1: query_msg = _("'any' query pending"); break;
2043 case 2: query_msg = _("'all' query pending"); break;
2044 default: query_msg = _("undefined query type"); break;
2045 }
2046
2047 printf_filtered (_("Tag-Group Status 0x%s\n"),
2048 phex (dma_info_status, 4));
2049 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
2050 phex (dma_info_mask, 4), query_msg);
2051 printf_filtered ("\n");
2052 }
2053
2054 info_spu_dma_cmdlist (buf + 24, 8);
2055 do_cleanups (chain);
2056}
2057
2058static void
2059info_spu_command (char *args, int from_tty)
2060{
2061 printf_unfiltered (_("\"info spu\" must be followed by the name of an SPU facility.\n"));
2062 help_list (infospucmdlist, "info spu ", -1, gdb_stdout);
2063}
2064
2065
771b4502
UW		 2066/* Set up gdbarch struct. */
2067
2068static struct gdbarch *
2069spu_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2070{
2071 struct gdbarch *gdbarch;
794ac428 2072 struct gdbarch_tdep *tdep;
771b4502
UW		 2073
2074 /* Find a candidate among the list of pre-declared architectures. */
2075 arches = gdbarch_list_lookup_by_info (arches, &info);
2076 if (arches != NULL)
2077 return arches->gdbarch;
2078
2079 /* Is is for us? */
2080 if (info.bfd_arch_info->mach != bfd_mach_spu)
2081 return NULL;
2082
2083 /* Yes, create a new architecture. */
794ac428
UW		 2084 tdep = XCALLOC (1, struct gdbarch_tdep);
2085 gdbarch = gdbarch_alloc (&info, tdep);
771b4502
UW		 2086
2087 /* Disassembler. */
2088 set_gdbarch_print_insn (gdbarch, print_insn_spu);
2089
2090 /* Registers. */
2091 set_gdbarch_num_regs (gdbarch, SPU_NUM_REGS);
2092 set_gdbarch_num_pseudo_regs (gdbarch, SPU_NUM_PSEUDO_REGS);
2093 set_gdbarch_sp_regnum (gdbarch, SPU_SP_REGNUM);
2094 set_gdbarch_pc_regnum (gdbarch, SPU_PC_REGNUM);
118dfbaf
UW		 2095 set_gdbarch_read_pc (gdbarch, spu_read_pc);
2096 set_gdbarch_write_pc (gdbarch, spu_write_pc);
771b4502
UW		 2097 set_gdbarch_register_name (gdbarch, spu_register_name);
2098 set_gdbarch_register_type (gdbarch, spu_register_type);
2099 set_gdbarch_pseudo_register_read (gdbarch, spu_pseudo_register_read);
2100 set_gdbarch_pseudo_register_write (gdbarch, spu_pseudo_register_write);
9acbedc0 2101 set_gdbarch_value_from_register (gdbarch, spu_value_from_register);
771b4502
UW		 2102 set_gdbarch_register_reggroup_p (gdbarch, spu_register_reggroup_p);
2103
2104 /* Data types. */
2105 set_gdbarch_char_signed (gdbarch, 0);
2106 set_gdbarch_ptr_bit (gdbarch, 32);
2107 set_gdbarch_addr_bit (gdbarch, 32);
2108 set_gdbarch_short_bit (gdbarch, 16);
2109 set_gdbarch_int_bit (gdbarch, 32);
2110 set_gdbarch_long_bit (gdbarch, 32);
2111 set_gdbarch_long_long_bit (gdbarch, 64);
2112 set_gdbarch_float_bit (gdbarch, 32);
2113 set_gdbarch_double_bit (gdbarch, 64);
2114 set_gdbarch_long_double_bit (gdbarch, 64);
8da61cc4
DJ		 2115 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2116 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2117 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
771b4502 2118
36acd84e
UW		 2119 /* Address conversion. */
2120 set_gdbarch_pointer_to_address (gdbarch, spu_pointer_to_address);
2121 set_gdbarch_integer_to_address (gdbarch, spu_integer_to_address);
2122
771b4502 2123 /* Inferior function calls. */
7b3dc0b7
UW		 2124 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
2125 set_gdbarch_frame_align (gdbarch, spu_frame_align);
5141027d 2126 set_gdbarch_frame_red_zone_size (gdbarch, 2000);
87805e63 2127 set_gdbarch_push_dummy_code (gdbarch, spu_push_dummy_code);
771b4502 2128 set_gdbarch_push_dummy_call (gdbarch, spu_push_dummy_call);
8d998b8f 2129 set_gdbarch_dummy_id (gdbarch, spu_dummy_id);
771b4502
UW		 2130 set_gdbarch_return_value (gdbarch, spu_return_value);
2131
2132 /* Frame handling. */
2133 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
8d998b8f 2134 frame_unwind_append_unwinder (gdbarch, &spu_frame_unwind);
771b4502
UW		 2135 frame_base_set_default (gdbarch, &spu_frame_base);
2136 set_gdbarch_unwind_pc (gdbarch, spu_unwind_pc);
2137 set_gdbarch_unwind_sp (gdbarch, spu_unwind_sp);
2138 set_gdbarch_virtual_frame_pointer (gdbarch, spu_virtual_frame_pointer);
2139 set_gdbarch_frame_args_skip (gdbarch, 0);
2140 set_gdbarch_skip_prologue (gdbarch, spu_skip_prologue);
fe5febed 2141 set_gdbarch_in_function_epilogue_p (gdbarch, spu_in_function_epilogue_p);
771b4502
UW		 2142
2143 /* Breakpoints. */
2144 set_gdbarch_decr_pc_after_break (gdbarch, 4);
2145 set_gdbarch_breakpoint_from_pc (gdbarch, spu_breakpoint_from_pc);
2146 set_gdbarch_cannot_step_breakpoint (gdbarch, 1);
2147 set_gdbarch_software_single_step (gdbarch, spu_software_single_step);
2148
dcf52cd8
UW		 2149 /* Overlays. */
2150 set_gdbarch_overlay_update (gdbarch, spu_overlay_update);
2151
771b4502
UW		 2152 return gdbarch;
2153}
2154
2155void
2156_initialize_spu_tdep (void)
2157{
2158 register_gdbarch_init (bfd_arch_spu, spu_gdbarch_init);
f2d43c2c 2159
dcf52cd8
UW		 2160 /* Add ourselves to objfile event chain. */
2161 observer_attach_new_objfile (spu_overlay_new_objfile);
2162 spu_overlay_data = register_objfile_data ();
23d964e7
UW		 2163
2164 /* Add root prefix command for all "info spu" commands. */
2165 add_prefix_cmd ("spu", class_info, info_spu_command,
2166 _("Various SPU specific commands."),
2167 &infospucmdlist, "info spu ", 0, &infolist);
2168
2169 /* Add various "info spu" commands. */
2170 add_cmd ("event", class_info, info_spu_event_command,
2171 _("Display SPU event facility status.\n"),
2172 &infospucmdlist);
2173 add_cmd ("signal", class_info, info_spu_signal_command,
2174 _("Display SPU signal notification facility status.\n"),
2175 &infospucmdlist);
2176 add_cmd ("mailbox", class_info, info_spu_mailbox_command,
2177 _("Display SPU mailbox facility status.\n"),
2178 &infospucmdlist);
2179 add_cmd ("dma", class_info, info_spu_dma_command,
2180 _("Display MFC DMA status.\n"),
2181 &infospucmdlist);
2182 add_cmd ("proxydma", class_info, info_spu_proxydma_command,
2183 _("Display MFC Proxy-DMA status.\n"),
2184 &infospucmdlist);
771b4502 2185}
GDB Binutils - Deliverables
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