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771b4502 UW |
1 | /* SPU target-dependent code for GDB, the GNU debugger. |
2 | Copyright (C) 2006 Free Software Foundation, Inc. | |
3 | ||
4 | Contributed by Ulrich Weigand <uweigand@de.ibm.com>. | |
5 | Based on a port by Sid Manning <sid@us.ibm.com>. | |
6 | ||
7 | This file is part of GDB. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 51 Franklin Street, Fifth Floor, | |
22 | Boston, MA 02110-1301, USA. */ | |
23 | ||
24 | #include "defs.h" | |
25 | #include "arch-utils.h" | |
26 | #include "gdbtypes.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
29 | #include "gdb_string.h" | |
30 | #include "gdb_assert.h" | |
31 | #include "frame.h" | |
32 | #include "frame-unwind.h" | |
33 | #include "frame-base.h" | |
34 | #include "trad-frame.h" | |
35 | #include "symtab.h" | |
36 | #include "symfile.h" | |
37 | #include "value.h" | |
38 | #include "inferior.h" | |
39 | #include "dis-asm.h" | |
40 | #include "objfiles.h" | |
41 | #include "language.h" | |
42 | #include "regcache.h" | |
43 | #include "reggroups.h" | |
44 | #include "floatformat.h" | |
45 | ||
46 | #include "spu-tdep.h" | |
47 | ||
48 | ||
49 | /* Registers. */ | |
50 | ||
51 | static const char * | |
52 | spu_register_name (int reg_nr) | |
53 | { | |
54 | static char *register_names[] = | |
55 | { | |
56 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
57 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
58 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
59 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
60 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", | |
61 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", | |
62 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", | |
63 | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", | |
64 | "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71", | |
65 | "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79", | |
66 | "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87", | |
67 | "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95", | |
68 | "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103", | |
69 | "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111", | |
70 | "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119", | |
71 | "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127", | |
72 | "id", "pc", "sp" | |
73 | }; | |
74 | ||
75 | if (reg_nr < 0) | |
76 | return NULL; | |
77 | if (reg_nr >= sizeof register_names / sizeof *register_names) | |
78 | return NULL; | |
79 | ||
80 | return register_names[reg_nr]; | |
81 | } | |
82 | ||
83 | static struct type * | |
84 | spu_register_type (struct gdbarch *gdbarch, int reg_nr) | |
85 | { | |
86 | if (reg_nr < SPU_NUM_GPRS) | |
87 | return builtin_type_vec128; | |
88 | ||
89 | switch (reg_nr) | |
90 | { | |
91 | case SPU_ID_REGNUM: | |
92 | return builtin_type_uint32; | |
93 | ||
94 | case SPU_PC_REGNUM: | |
95 | return builtin_type_void_func_ptr; | |
96 | ||
97 | case SPU_SP_REGNUM: | |
98 | return builtin_type_void_data_ptr; | |
99 | ||
100 | default: | |
101 | internal_error (__FILE__, __LINE__, "invalid regnum"); | |
102 | } | |
103 | } | |
104 | ||
105 | /* Pseudo registers for preferred slots - stack pointer. */ | |
106 | ||
107 | static void | |
108 | spu_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
109 | int regnum, gdb_byte *buf) | |
110 | { | |
111 | gdb_byte reg[16]; | |
112 | ||
113 | switch (regnum) | |
114 | { | |
115 | case SPU_SP_REGNUM: | |
116 | regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg); | |
117 | memcpy (buf, reg, 4); | |
118 | break; | |
119 | ||
120 | default: | |
121 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
122 | } | |
123 | } | |
124 | ||
125 | static void | |
126 | spu_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
127 | int regnum, const gdb_byte *buf) | |
128 | { | |
129 | gdb_byte reg[16]; | |
130 | ||
131 | switch (regnum) | |
132 | { | |
133 | case SPU_SP_REGNUM: | |
134 | regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg); | |
135 | memcpy (reg, buf, 4); | |
136 | regcache_raw_write (regcache, SPU_RAW_SP_REGNUM, reg); | |
137 | break; | |
138 | ||
139 | default: | |
140 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
141 | } | |
142 | } | |
143 | ||
144 | /* Value conversion -- access scalar values at the preferred slot. */ | |
145 | ||
146 | static int | |
147 | spu_convert_register_p (int regno, struct type *type) | |
148 | { | |
149 | return regno < SPU_NUM_GPRS && TYPE_LENGTH (type) < 16; | |
150 | } | |
151 | ||
152 | static void | |
153 | spu_register_to_value (struct frame_info *frame, int regnum, | |
154 | struct type *valtype, gdb_byte *out) | |
155 | { | |
156 | gdb_byte in[16]; | |
157 | int len = TYPE_LENGTH (valtype); | |
158 | int preferred_slot = len < 4 ? 4 - len : 0; | |
159 | gdb_assert (len < 16); | |
160 | ||
161 | get_frame_register (frame, regnum, in); | |
162 | memcpy (out, in + preferred_slot, len); | |
163 | } | |
164 | ||
165 | static void | |
166 | spu_value_to_register (struct frame_info *frame, int regnum, | |
167 | struct type *valtype, const gdb_byte *in) | |
168 | { | |
169 | gdb_byte out[16]; | |
170 | int len = TYPE_LENGTH (valtype); | |
171 | int preferred_slot = len < 4 ? 4 - len : 0; | |
172 | gdb_assert (len < 16); | |
173 | ||
174 | memset (out, 0, 16); | |
175 | memcpy (out + preferred_slot, in, len); | |
176 | put_frame_register (frame, regnum, out); | |
177 | } | |
178 | ||
179 | /* Register groups. */ | |
180 | ||
181 | static int | |
182 | spu_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
183 | struct reggroup *group) | |
184 | { | |
185 | /* Registers displayed via 'info regs'. */ | |
186 | if (group == general_reggroup) | |
187 | return 1; | |
188 | ||
189 | /* Registers displayed via 'info float'. */ | |
190 | if (group == float_reggroup) | |
191 | return 0; | |
192 | ||
193 | /* Registers that need to be saved/restored in order to | |
194 | push or pop frames. */ | |
195 | if (group == save_reggroup || group == restore_reggroup) | |
196 | return 1; | |
197 | ||
198 | return default_register_reggroup_p (gdbarch, regnum, group); | |
199 | } | |
200 | ||
201 | ||
202 | /* Decoding SPU instructions. */ | |
203 | ||
204 | enum | |
205 | { | |
206 | op_lqd = 0x34, | |
207 | op_lqx = 0x3c4, | |
208 | op_lqa = 0x61, | |
209 | op_lqr = 0x67, | |
210 | op_stqd = 0x24, | |
211 | op_stqx = 0x144, | |
212 | op_stqa = 0x41, | |
213 | op_stqr = 0x47, | |
214 | ||
215 | op_il = 0x081, | |
216 | op_ila = 0x21, | |
217 | op_a = 0x0c0, | |
218 | op_ai = 0x1c, | |
219 | ||
220 | op_selb = 0x4, | |
221 | ||
222 | op_br = 0x64, | |
223 | op_bra = 0x60, | |
224 | op_brsl = 0x66, | |
225 | op_brasl = 0x62, | |
226 | op_brnz = 0x42, | |
227 | op_brz = 0x40, | |
228 | op_brhnz = 0x46, | |
229 | op_brhz = 0x44, | |
230 | op_bi = 0x1a8, | |
231 | op_bisl = 0x1a9, | |
232 | op_biz = 0x128, | |
233 | op_binz = 0x129, | |
234 | op_bihz = 0x12a, | |
235 | op_bihnz = 0x12b, | |
236 | }; | |
237 | ||
238 | static int | |
239 | is_rr (unsigned int insn, int op, int *rt, int *ra, int *rb) | |
240 | { | |
241 | if ((insn >> 21) == op) | |
242 | { | |
243 | *rt = insn & 127; | |
244 | *ra = (insn >> 7) & 127; | |
245 | *rb = (insn >> 14) & 127; | |
246 | return 1; | |
247 | } | |
248 | ||
249 | return 0; | |
250 | } | |
251 | ||
252 | static int | |
253 | is_rrr (unsigned int insn, int op, int *rt, int *ra, int *rb, int *rc) | |
254 | { | |
255 | if ((insn >> 28) == op) | |
256 | { | |
257 | *rt = (insn >> 21) & 127; | |
258 | *ra = (insn >> 7) & 127; | |
259 | *rb = (insn >> 14) & 127; | |
260 | *rc = insn & 127; | |
261 | return 1; | |
262 | } | |
263 | ||
264 | return 0; | |
265 | } | |
266 | ||
267 | static int | |
268 | is_ri7 (unsigned int insn, int op, int *rt, int *ra, int *i7) | |
269 | { | |
270 | if ((insn >> 21) == op) | |
271 | { | |
272 | *rt = insn & 127; | |
273 | *ra = (insn >> 7) & 127; | |
274 | *i7 = (((insn >> 14) & 127) ^ 0x40) - 0x40; | |
275 | return 1; | |
276 | } | |
277 | ||
278 | return 0; | |
279 | } | |
280 | ||
281 | static int | |
282 | is_ri10 (unsigned int insn, int op, int *rt, int *ra, int *i10) | |
283 | { | |
284 | if ((insn >> 24) == op) | |
285 | { | |
286 | *rt = insn & 127; | |
287 | *ra = (insn >> 7) & 127; | |
288 | *i10 = (((insn >> 14) & 0x3ff) ^ 0x200) - 0x200; | |
289 | return 1; | |
290 | } | |
291 | ||
292 | return 0; | |
293 | } | |
294 | ||
295 | static int | |
296 | is_ri16 (unsigned int insn, int op, int *rt, int *i16) | |
297 | { | |
298 | if ((insn >> 23) == op) | |
299 | { | |
300 | *rt = insn & 127; | |
301 | *i16 = (((insn >> 7) & 0xffff) ^ 0x8000) - 0x8000; | |
302 | return 1; | |
303 | } | |
304 | ||
305 | return 0; | |
306 | } | |
307 | ||
308 | static int | |
309 | is_ri18 (unsigned int insn, int op, int *rt, int *i18) | |
310 | { | |
311 | if ((insn >> 25) == op) | |
312 | { | |
313 | *rt = insn & 127; | |
314 | *i18 = (((insn >> 7) & 0x3ffff) ^ 0x20000) - 0x20000; | |
315 | return 1; | |
316 | } | |
317 | ||
318 | return 0; | |
319 | } | |
320 | ||
321 | static int | |
322 | is_branch (unsigned int insn, int *offset, int *reg) | |
323 | { | |
324 | int rt, i7, i16; | |
325 | ||
326 | if (is_ri16 (insn, op_br, &rt, &i16) | |
327 | || is_ri16 (insn, op_brsl, &rt, &i16) | |
328 | || is_ri16 (insn, op_brnz, &rt, &i16) | |
329 | || is_ri16 (insn, op_brz, &rt, &i16) | |
330 | || is_ri16 (insn, op_brhnz, &rt, &i16) | |
331 | || is_ri16 (insn, op_brhz, &rt, &i16)) | |
332 | { | |
333 | *reg = SPU_PC_REGNUM; | |
334 | *offset = i16 << 2; | |
335 | return 1; | |
336 | } | |
337 | ||
338 | if (is_ri16 (insn, op_bra, &rt, &i16) | |
339 | || is_ri16 (insn, op_brasl, &rt, &i16)) | |
340 | { | |
341 | *reg = -1; | |
342 | *offset = i16 << 2; | |
343 | return 1; | |
344 | } | |
345 | ||
346 | if (is_ri7 (insn, op_bi, &rt, reg, &i7) | |
347 | || is_ri7 (insn, op_bisl, &rt, reg, &i7) | |
348 | || is_ri7 (insn, op_biz, &rt, reg, &i7) | |
349 | || is_ri7 (insn, op_binz, &rt, reg, &i7) | |
350 | || is_ri7 (insn, op_bihz, &rt, reg, &i7) | |
351 | || is_ri7 (insn, op_bihnz, &rt, reg, &i7)) | |
352 | { | |
353 | *offset = 0; | |
354 | return 1; | |
355 | } | |
356 | ||
357 | return 0; | |
358 | } | |
359 | ||
360 | ||
361 | /* Prolog parsing. */ | |
362 | ||
363 | struct spu_prologue_data | |
364 | { | |
365 | /* Stack frame size. -1 if analysis was unsuccessful. */ | |
366 | int size; | |
367 | ||
368 | /* How to find the CFA. The CFA is equal to SP at function entry. */ | |
369 | int cfa_reg; | |
370 | int cfa_offset; | |
371 | ||
372 | /* Offset relative to CFA where a register is saved. -1 if invalid. */ | |
373 | int reg_offset[SPU_NUM_GPRS]; | |
374 | }; | |
375 | ||
376 | static CORE_ADDR | |
377 | spu_analyze_prologue (CORE_ADDR start_pc, CORE_ADDR end_pc, | |
378 | struct spu_prologue_data *data) | |
379 | { | |
380 | int found_sp = 0; | |
381 | int found_fp = 0; | |
382 | int found_lr = 0; | |
383 | int reg_immed[SPU_NUM_GPRS]; | |
384 | gdb_byte buf[16]; | |
385 | CORE_ADDR prolog_pc = start_pc; | |
386 | CORE_ADDR pc; | |
387 | int i; | |
388 | ||
389 | ||
390 | /* Initialize DATA to default values. */ | |
391 | data->size = -1; | |
392 | ||
393 | data->cfa_reg = SPU_RAW_SP_REGNUM; | |
394 | data->cfa_offset = 0; | |
395 | ||
396 | for (i = 0; i < SPU_NUM_GPRS; i++) | |
397 | data->reg_offset[i] = -1; | |
398 | ||
399 | /* Set up REG_IMMED array. This is non-zero for a register if we know its | |
400 | preferred slot currently holds this immediate value. */ | |
401 | for (i = 0; i < SPU_NUM_GPRS; i++) | |
402 | reg_immed[i] = 0; | |
403 | ||
404 | /* Scan instructions until the first branch. | |
405 | ||
406 | The following instructions are important prolog components: | |
407 | ||
408 | - The first instruction to set up the stack pointer. | |
409 | - The first instruction to set up the frame pointer. | |
410 | - The first instruction to save the link register. | |
411 | ||
412 | We return the instruction after the latest of these three, | |
413 | or the incoming PC if none is found. The first instruction | |
414 | to set up the stack pointer also defines the frame size. | |
415 | ||
416 | Note that instructions saving incoming arguments to their stack | |
417 | slots are not counted as important, because they are hard to | |
418 | identify with certainty. This should not matter much, because | |
419 | arguments are relevant only in code compiled with debug data, | |
420 | and in such code the GDB core will advance until the first source | |
421 | line anyway, using SAL data. | |
422 | ||
423 | For purposes of stack unwinding, we analyze the following types | |
424 | of instructions in addition: | |
425 | ||
426 | - Any instruction adding to the current frame pointer. | |
427 | - Any instruction loading an immediate constant into a register. | |
428 | - Any instruction storing a register onto the stack. | |
429 | ||
430 | These are used to compute the CFA and REG_OFFSET output. */ | |
431 | ||
432 | for (pc = start_pc; pc < end_pc; pc += 4) | |
433 | { | |
434 | unsigned int insn; | |
435 | int rt, ra, rb, rc, immed; | |
436 | ||
437 | if (target_read_memory (pc, buf, 4)) | |
438 | break; | |
439 | insn = extract_unsigned_integer (buf, 4); | |
440 | ||
441 | /* AI is the typical instruction to set up a stack frame. | |
442 | It is also used to initialize the frame pointer. */ | |
443 | if (is_ri10 (insn, op_ai, &rt, &ra, &immed)) | |
444 | { | |
445 | if (rt == data->cfa_reg && ra == data->cfa_reg) | |
446 | data->cfa_offset -= immed; | |
447 | ||
448 | if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM | |
449 | && !found_sp) | |
450 | { | |
451 | found_sp = 1; | |
452 | prolog_pc = pc + 4; | |
453 | ||
454 | data->size = -immed; | |
455 | } | |
456 | else if (rt == SPU_FP_REGNUM && ra == SPU_RAW_SP_REGNUM | |
457 | && !found_fp) | |
458 | { | |
459 | found_fp = 1; | |
460 | prolog_pc = pc + 4; | |
461 | ||
462 | data->cfa_reg = SPU_FP_REGNUM; | |
463 | data->cfa_offset -= immed; | |
464 | } | |
465 | } | |
466 | ||
467 | /* A is used to set up stack frames of size >= 512 bytes. | |
468 | If we have tracked the contents of the addend register, | |
469 | we can handle this as well. */ | |
470 | else if (is_rr (insn, op_a, &rt, &ra, &rb)) | |
471 | { | |
472 | if (rt == data->cfa_reg && ra == data->cfa_reg) | |
473 | { | |
474 | if (reg_immed[rb] != 0) | |
475 | data->cfa_offset -= reg_immed[rb]; | |
476 | else | |
477 | data->cfa_reg = -1; /* We don't know the CFA any more. */ | |
478 | } | |
479 | ||
480 | if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM | |
481 | && !found_sp) | |
482 | { | |
483 | found_sp = 1; | |
484 | prolog_pc = pc + 4; | |
485 | ||
486 | if (reg_immed[rb] != 0) | |
487 | data->size = -reg_immed[rb]; | |
488 | } | |
489 | } | |
490 | ||
491 | /* We need to track IL and ILA used to load immediate constants | |
492 | in case they are later used as input to an A instruction. */ | |
493 | else if (is_ri16 (insn, op_il, &rt, &immed)) | |
494 | { | |
495 | reg_immed[rt] = immed; | |
496 | } | |
497 | ||
498 | else if (is_ri18 (insn, op_ila, &rt, &immed)) | |
499 | { | |
500 | reg_immed[rt] = immed & 0x3ffff; | |
501 | } | |
502 | ||
503 | /* STQD is used to save registers to the stack. */ | |
504 | else if (is_ri10 (insn, op_stqd, &rt, &ra, &immed)) | |
505 | { | |
506 | if (ra == data->cfa_reg) | |
507 | data->reg_offset[rt] = data->cfa_offset - (immed << 4); | |
508 | ||
509 | if (ra == data->cfa_reg && rt == SPU_LR_REGNUM | |
510 | && !found_lr) | |
511 | { | |
512 | found_lr = 1; | |
513 | prolog_pc = pc + 4; | |
514 | } | |
515 | } | |
516 | ||
517 | /* _start uses SELB to set up the stack pointer. */ | |
518 | else if (is_rrr (insn, op_selb, &rt, &ra, &rb, &rc)) | |
519 | { | |
520 | if (rt == SPU_RAW_SP_REGNUM && !found_sp) | |
521 | found_sp = 1; | |
522 | } | |
523 | ||
524 | /* We terminate if we find a branch. */ | |
525 | else if (is_branch (insn, &immed, &ra)) | |
526 | break; | |
527 | } | |
528 | ||
529 | ||
530 | /* If we successfully parsed until here, and didn't find any instruction | |
531 | modifying SP, we assume we have a frameless function. */ | |
532 | if (!found_sp) | |
533 | data->size = 0; | |
534 | ||
535 | /* Return cooked instead of raw SP. */ | |
536 | if (data->cfa_reg == SPU_RAW_SP_REGNUM) | |
537 | data->cfa_reg = SPU_SP_REGNUM; | |
538 | ||
539 | return prolog_pc; | |
540 | } | |
541 | ||
542 | /* Return the first instruction after the prologue starting at PC. */ | |
543 | static CORE_ADDR | |
544 | spu_skip_prologue (CORE_ADDR pc) | |
545 | { | |
546 | struct spu_prologue_data data; | |
547 | return spu_analyze_prologue (pc, (CORE_ADDR)-1, &data); | |
548 | } | |
549 | ||
550 | /* Return the frame pointer in use at address PC. */ | |
551 | static void | |
552 | spu_virtual_frame_pointer (CORE_ADDR pc, int *reg, LONGEST *offset) | |
553 | { | |
554 | struct spu_prologue_data data; | |
555 | spu_analyze_prologue (pc, (CORE_ADDR)-1, &data); | |
556 | ||
557 | if (data.size != -1 && data.cfa_reg != -1) | |
558 | { | |
559 | /* The 'frame pointer' address is CFA minus frame size. */ | |
560 | *reg = data.cfa_reg; | |
561 | *offset = data.cfa_offset - data.size; | |
562 | } | |
563 | else | |
564 | { | |
565 | /* ??? We don't really know ... */ | |
566 | *reg = SPU_SP_REGNUM; | |
567 | *offset = 0; | |
568 | } | |
569 | } | |
570 | ||
571 | /* Normal stack frames. */ | |
572 | ||
573 | struct spu_unwind_cache | |
574 | { | |
575 | CORE_ADDR func; | |
576 | CORE_ADDR frame_base; | |
577 | CORE_ADDR local_base; | |
578 | ||
579 | struct trad_frame_saved_reg *saved_regs; | |
580 | }; | |
581 | ||
582 | static struct spu_unwind_cache * | |
583 | spu_frame_unwind_cache (struct frame_info *next_frame, | |
584 | void **this_prologue_cache) | |
585 | { | |
586 | struct spu_unwind_cache *info; | |
587 | struct spu_prologue_data data; | |
588 | ||
589 | if (*this_prologue_cache) | |
590 | return *this_prologue_cache; | |
591 | ||
592 | info = FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache); | |
593 | *this_prologue_cache = info; | |
594 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
595 | info->frame_base = 0; | |
596 | info->local_base = 0; | |
597 | ||
598 | /* Find the start of the current function, and analyze its prologue. */ | |
599 | info->func = frame_func_unwind (next_frame); | |
600 | if (info->func == 0) | |
601 | { | |
602 | /* Fall back to using the current PC as frame ID. */ | |
603 | info->func = frame_pc_unwind (next_frame); | |
604 | data.size = -1; | |
605 | } | |
606 | else | |
607 | spu_analyze_prologue (info->func, frame_pc_unwind (next_frame), &data); | |
608 | ||
609 | ||
610 | /* If successful, use prologue analysis data. */ | |
611 | if (data.size != -1 && data.cfa_reg != -1) | |
612 | { | |
613 | CORE_ADDR cfa; | |
614 | int i; | |
615 | gdb_byte buf[16]; | |
616 | ||
617 | /* Determine CFA via unwound CFA_REG plus CFA_OFFSET. */ | |
618 | frame_unwind_register (next_frame, data.cfa_reg, buf); | |
619 | cfa = extract_unsigned_integer (buf, 4) + data.cfa_offset; | |
620 | ||
621 | /* Call-saved register slots. */ | |
622 | for (i = 0; i < SPU_NUM_GPRS; i++) | |
623 | if (i == SPU_LR_REGNUM | |
624 | || (i >= SPU_SAVED1_REGNUM && i <= SPU_SAVEDN_REGNUM)) | |
625 | if (data.reg_offset[i] != -1) | |
626 | info->saved_regs[i].addr = cfa - data.reg_offset[i]; | |
627 | ||
628 | /* The previous PC comes from the link register. */ | |
629 | if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM)) | |
630 | info->saved_regs[SPU_PC_REGNUM] = info->saved_regs[SPU_LR_REGNUM]; | |
631 | else | |
632 | info->saved_regs[SPU_PC_REGNUM].realreg = SPU_LR_REGNUM; | |
633 | ||
634 | /* The previous SP is equal to the CFA. */ | |
635 | trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM, cfa); | |
636 | ||
637 | /* Frame bases. */ | |
638 | info->frame_base = cfa; | |
639 | info->local_base = cfa - data.size; | |
640 | } | |
641 | ||
642 | /* Otherwise, fall back to reading the backchain link. */ | |
643 | else | |
644 | { | |
645 | CORE_ADDR reg, backchain; | |
646 | ||
647 | /* Get the backchain. */ | |
648 | reg = frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM); | |
649 | backchain = read_memory_unsigned_integer (reg, 4); | |
650 | ||
651 | /* A zero backchain terminates the frame chain. Also, sanity | |
652 | check against the local store size limit. */ | |
653 | if (backchain != 0 && backchain < SPU_LS_SIZE) | |
654 | { | |
655 | /* Assume the link register is saved into its slot. */ | |
656 | if (backchain + 16 < SPU_LS_SIZE) | |
657 | info->saved_regs[SPU_LR_REGNUM].addr = backchain + 16; | |
658 | ||
659 | /* This will also be the previous PC. */ | |
660 | if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM)) | |
661 | info->saved_regs[SPU_PC_REGNUM] = info->saved_regs[SPU_LR_REGNUM]; | |
662 | else | |
663 | info->saved_regs[SPU_PC_REGNUM].realreg = SPU_LR_REGNUM; | |
664 | ||
665 | /* The previous SP will equal the backchain value. */ | |
666 | trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM, backchain); | |
667 | ||
668 | /* Frame bases. */ | |
669 | info->frame_base = backchain; | |
670 | info->local_base = reg; | |
671 | } | |
672 | } | |
673 | ||
674 | return info; | |
675 | } | |
676 | ||
677 | static void | |
678 | spu_frame_this_id (struct frame_info *next_frame, | |
679 | void **this_prologue_cache, struct frame_id *this_id) | |
680 | { | |
681 | struct spu_unwind_cache *info = | |
682 | spu_frame_unwind_cache (next_frame, this_prologue_cache); | |
683 | ||
684 | if (info->frame_base == 0) | |
685 | return; | |
686 | ||
687 | *this_id = frame_id_build (info->frame_base, info->func); | |
688 | } | |
689 | ||
690 | static void | |
691 | spu_frame_prev_register (struct frame_info *next_frame, | |
692 | void **this_prologue_cache, | |
693 | int regnum, int *optimizedp, | |
694 | enum lval_type *lvalp, CORE_ADDR * addrp, | |
695 | int *realnump, gdb_byte *bufferp) | |
696 | { | |
697 | struct spu_unwind_cache *info | |
698 | = spu_frame_unwind_cache (next_frame, this_prologue_cache); | |
699 | ||
700 | /* Special-case the stack pointer. */ | |
701 | if (regnum == SPU_RAW_SP_REGNUM) | |
702 | regnum = SPU_SP_REGNUM; | |
703 | ||
704 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
705 | optimizedp, lvalp, addrp, realnump, bufferp); | |
706 | } | |
707 | ||
708 | static const struct frame_unwind spu_frame_unwind = { | |
709 | NORMAL_FRAME, | |
710 | spu_frame_this_id, | |
711 | spu_frame_prev_register | |
712 | }; | |
713 | ||
714 | const struct frame_unwind * | |
715 | spu_frame_sniffer (struct frame_info *next_frame) | |
716 | { | |
717 | return &spu_frame_unwind; | |
718 | } | |
719 | ||
720 | static CORE_ADDR | |
721 | spu_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
722 | { | |
723 | struct spu_unwind_cache *info | |
724 | = spu_frame_unwind_cache (next_frame, this_cache); | |
725 | return info->local_base; | |
726 | } | |
727 | ||
728 | static const struct frame_base spu_frame_base = { | |
729 | &spu_frame_unwind, | |
730 | spu_frame_base_address, | |
731 | spu_frame_base_address, | |
732 | spu_frame_base_address | |
733 | }; | |
734 | ||
735 | static CORE_ADDR | |
736 | spu_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
737 | { | |
738 | return frame_unwind_register_unsigned (next_frame, SPU_PC_REGNUM); | |
739 | } | |
740 | ||
741 | static CORE_ADDR | |
742 | spu_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
743 | { | |
744 | return frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM); | |
745 | } | |
746 | ||
747 | ||
748 | /* Function calling convention. */ | |
749 | ||
750 | static int | |
751 | spu_scalar_value_p (struct type *type) | |
752 | { | |
753 | switch (TYPE_CODE (type)) | |
754 | { | |
755 | case TYPE_CODE_INT: | |
756 | case TYPE_CODE_ENUM: | |
757 | case TYPE_CODE_RANGE: | |
758 | case TYPE_CODE_CHAR: | |
759 | case TYPE_CODE_BOOL: | |
760 | case TYPE_CODE_PTR: | |
761 | case TYPE_CODE_REF: | |
762 | return TYPE_LENGTH (type) <= 16; | |
763 | ||
764 | default: | |
765 | return 0; | |
766 | } | |
767 | } | |
768 | ||
769 | static void | |
770 | spu_value_to_regcache (struct regcache *regcache, int regnum, | |
771 | struct type *type, const gdb_byte *in) | |
772 | { | |
773 | int len = TYPE_LENGTH (type); | |
774 | ||
775 | if (spu_scalar_value_p (type)) | |
776 | { | |
777 | int preferred_slot = len < 4 ? 4 - len : 0; | |
778 | regcache_cooked_write_part (regcache, regnum, preferred_slot, len, in); | |
779 | } | |
780 | else | |
781 | { | |
782 | while (len >= 16) | |
783 | { | |
784 | regcache_cooked_write (regcache, regnum++, in); | |
785 | in += 16; | |
786 | len -= 16; | |
787 | } | |
788 | ||
789 | if (len > 0) | |
790 | regcache_cooked_write_part (regcache, regnum, 0, len, in); | |
791 | } | |
792 | } | |
793 | ||
794 | static void | |
795 | spu_regcache_to_value (struct regcache *regcache, int regnum, | |
796 | struct type *type, gdb_byte *out) | |
797 | { | |
798 | int len = TYPE_LENGTH (type); | |
799 | ||
800 | if (spu_scalar_value_p (type)) | |
801 | { | |
802 | int preferred_slot = len < 4 ? 4 - len : 0; | |
803 | regcache_cooked_read_part (regcache, regnum, preferred_slot, len, out); | |
804 | } | |
805 | else | |
806 | { | |
807 | while (len >= 16) | |
808 | { | |
809 | regcache_cooked_read (regcache, regnum++, out); | |
810 | out += 16; | |
811 | len -= 16; | |
812 | } | |
813 | ||
814 | if (len > 0) | |
815 | regcache_cooked_read_part (regcache, regnum, 0, len, out); | |
816 | } | |
817 | } | |
818 | ||
819 | static CORE_ADDR | |
820 | spu_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
821 | struct regcache *regcache, CORE_ADDR bp_addr, | |
822 | int nargs, struct value **args, CORE_ADDR sp, | |
823 | int struct_return, CORE_ADDR struct_addr) | |
824 | { | |
825 | int i; | |
826 | int regnum = SPU_ARG1_REGNUM; | |
827 | int stack_arg = -1; | |
828 | gdb_byte buf[16]; | |
829 | ||
830 | /* Set the return address. */ | |
831 | memset (buf, 0, sizeof buf); | |
832 | store_unsigned_integer (buf, 4, bp_addr); | |
833 | regcache_cooked_write (regcache, SPU_LR_REGNUM, buf); | |
834 | ||
835 | /* If STRUCT_RETURN is true, then the struct return address (in | |
836 | STRUCT_ADDR) will consume the first argument-passing register. | |
837 | Both adjust the register count and store that value. */ | |
838 | if (struct_return) | |
839 | { | |
840 | memset (buf, 0, sizeof buf); | |
841 | store_unsigned_integer (buf, 4, struct_addr); | |
842 | regcache_cooked_write (regcache, regnum++, buf); | |
843 | } | |
844 | ||
845 | /* Fill in argument registers. */ | |
846 | for (i = 0; i < nargs; i++) | |
847 | { | |
848 | struct value *arg = args[i]; | |
849 | struct type *type = check_typedef (value_type (arg)); | |
850 | const gdb_byte *contents = value_contents (arg); | |
851 | int len = TYPE_LENGTH (type); | |
852 | int n_regs = align_up (len, 16) / 16; | |
853 | ||
854 | /* If the argument doesn't wholly fit into registers, it and | |
855 | all subsequent arguments go to the stack. */ | |
856 | if (regnum + n_regs - 1 > SPU_ARGN_REGNUM) | |
857 | { | |
858 | stack_arg = i; | |
859 | break; | |
860 | } | |
861 | ||
862 | spu_value_to_regcache (regcache, regnum, type, contents); | |
863 | regnum += n_regs; | |
864 | } | |
865 | ||
866 | /* Overflow arguments go to the stack. */ | |
867 | if (stack_arg != -1) | |
868 | { | |
869 | CORE_ADDR ap; | |
870 | ||
871 | /* Allocate all required stack size. */ | |
872 | for (i = stack_arg; i < nargs; i++) | |
873 | { | |
874 | struct type *type = check_typedef (value_type (args[i])); | |
875 | sp -= align_up (TYPE_LENGTH (type), 16); | |
876 | } | |
877 | ||
878 | /* Fill in stack arguments. */ | |
879 | ap = sp; | |
880 | for (i = stack_arg; i < nargs; i++) | |
881 | { | |
882 | struct value *arg = args[i]; | |
883 | struct type *type = check_typedef (value_type (arg)); | |
884 | int len = TYPE_LENGTH (type); | |
885 | int preferred_slot; | |
886 | ||
887 | if (spu_scalar_value_p (type)) | |
888 | preferred_slot = len < 4 ? 4 - len : 0; | |
889 | else | |
890 | preferred_slot = 0; | |
891 | ||
892 | target_write_memory (ap + preferred_slot, value_contents (arg), len); | |
893 | ap += align_up (TYPE_LENGTH (type), 16); | |
894 | } | |
895 | } | |
896 | ||
897 | /* Allocate stack frame header. */ | |
898 | sp -= 32; | |
899 | ||
900 | /* Finally, update the SP register. */ | |
901 | regcache_cooked_write_unsigned (regcache, SPU_SP_REGNUM, sp); | |
902 | ||
903 | return sp; | |
904 | } | |
905 | ||
906 | static struct frame_id | |
907 | spu_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
908 | { | |
909 | return frame_id_build (spu_unwind_sp (gdbarch, next_frame), | |
910 | spu_unwind_pc (gdbarch, next_frame)); | |
911 | } | |
912 | ||
913 | /* Function return value access. */ | |
914 | ||
915 | static enum return_value_convention | |
916 | spu_return_value (struct gdbarch *gdbarch, struct type *type, | |
917 | struct regcache *regcache, gdb_byte *out, const gdb_byte *in) | |
918 | { | |
919 | enum return_value_convention rvc; | |
920 | ||
921 | if (TYPE_LENGTH (type) <= (SPU_ARGN_REGNUM - SPU_ARG1_REGNUM + 1) * 16) | |
922 | rvc = RETURN_VALUE_REGISTER_CONVENTION; | |
923 | else | |
924 | rvc = RETURN_VALUE_STRUCT_CONVENTION; | |
925 | ||
926 | if (in) | |
927 | { | |
928 | switch (rvc) | |
929 | { | |
930 | case RETURN_VALUE_REGISTER_CONVENTION: | |
931 | spu_value_to_regcache (regcache, SPU_ARG1_REGNUM, type, in); | |
932 | break; | |
933 | ||
934 | case RETURN_VALUE_STRUCT_CONVENTION: | |
935 | error ("Cannot set function return value."); | |
936 | break; | |
937 | } | |
938 | } | |
939 | else if (out) | |
940 | { | |
941 | switch (rvc) | |
942 | { | |
943 | case RETURN_VALUE_REGISTER_CONVENTION: | |
944 | spu_regcache_to_value (regcache, SPU_ARG1_REGNUM, type, out); | |
945 | break; | |
946 | ||
947 | case RETURN_VALUE_STRUCT_CONVENTION: | |
948 | error ("Function return value unknown."); | |
949 | break; | |
950 | } | |
951 | } | |
952 | ||
953 | return rvc; | |
954 | } | |
955 | ||
956 | ||
957 | /* Breakpoints. */ | |
958 | ||
959 | static const gdb_byte * | |
960 | spu_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr) | |
961 | { | |
962 | static const gdb_byte breakpoint[] = { 0x00, 0x00, 0x3f, 0xff }; | |
963 | ||
964 | *lenptr = sizeof breakpoint; | |
965 | return breakpoint; | |
966 | } | |
967 | ||
968 | ||
969 | /* Software single-stepping support. */ | |
970 | ||
971 | void | |
972 | spu_software_single_step (enum target_signal signal, int insert_breakpoints_p) | |
973 | { | |
974 | if (insert_breakpoints_p) | |
975 | { | |
976 | CORE_ADDR pc, next_pc; | |
977 | unsigned int insn; | |
978 | int offset, reg; | |
979 | gdb_byte buf[4]; | |
980 | ||
981 | regcache_cooked_read (current_regcache, SPU_PC_REGNUM, buf); | |
982 | pc = extract_unsigned_integer (buf, 4); | |
983 | ||
984 | if (target_read_memory (pc, buf, 4)) | |
985 | return; | |
986 | insn = extract_unsigned_integer (buf, 4); | |
987 | ||
988 | /* Next sequential instruction is at PC + 4, except if the current | |
989 | instruction is a PPE-assisted call, in which case it is at PC + 8. | |
990 | Wrap around LS limit to be on the safe side. */ | |
991 | if ((insn & 0xffffff00) == 0x00002100) | |
992 | next_pc = (pc + 8) & (SPU_LS_SIZE - 1) & -4; | |
993 | else | |
994 | next_pc = (pc + 4) & (SPU_LS_SIZE - 1) & -4; | |
995 | ||
996 | insert_single_step_breakpoint (next_pc); | |
997 | ||
998 | if (is_branch (insn, &offset, ®)) | |
999 | { | |
1000 | CORE_ADDR target = offset; | |
1001 | ||
1002 | if (reg == SPU_PC_REGNUM) | |
1003 | target += pc; | |
1004 | else if (reg != -1) | |
1005 | { | |
1006 | regcache_cooked_read_part (current_regcache, reg, 0, 4, buf); | |
1007 | target += extract_unsigned_integer (buf, 4); | |
1008 | } | |
1009 | ||
1010 | target = target & (SPU_LS_SIZE - 1) & -4; | |
1011 | if (target != next_pc) | |
1012 | insert_single_step_breakpoint (target); | |
1013 | } | |
1014 | } | |
1015 | else | |
1016 | remove_single_step_breakpoints (); | |
1017 | } | |
1018 | ||
1019 | ||
1020 | /* Set up gdbarch struct. */ | |
1021 | ||
1022 | static struct gdbarch * | |
1023 | spu_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1024 | { | |
1025 | struct gdbarch *gdbarch; | |
1026 | ||
1027 | /* Find a candidate among the list of pre-declared architectures. */ | |
1028 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1029 | if (arches != NULL) | |
1030 | return arches->gdbarch; | |
1031 | ||
1032 | /* Is is for us? */ | |
1033 | if (info.bfd_arch_info->mach != bfd_mach_spu) | |
1034 | return NULL; | |
1035 | ||
1036 | /* Yes, create a new architecture. */ | |
1037 | gdbarch = gdbarch_alloc (&info, NULL); | |
1038 | ||
1039 | /* Disassembler. */ | |
1040 | set_gdbarch_print_insn (gdbarch, print_insn_spu); | |
1041 | ||
1042 | /* Registers. */ | |
1043 | set_gdbarch_num_regs (gdbarch, SPU_NUM_REGS); | |
1044 | set_gdbarch_num_pseudo_regs (gdbarch, SPU_NUM_PSEUDO_REGS); | |
1045 | set_gdbarch_sp_regnum (gdbarch, SPU_SP_REGNUM); | |
1046 | set_gdbarch_pc_regnum (gdbarch, SPU_PC_REGNUM); | |
1047 | set_gdbarch_register_name (gdbarch, spu_register_name); | |
1048 | set_gdbarch_register_type (gdbarch, spu_register_type); | |
1049 | set_gdbarch_pseudo_register_read (gdbarch, spu_pseudo_register_read); | |
1050 | set_gdbarch_pseudo_register_write (gdbarch, spu_pseudo_register_write); | |
1051 | set_gdbarch_convert_register_p (gdbarch, spu_convert_register_p); | |
1052 | set_gdbarch_register_to_value (gdbarch, spu_register_to_value); | |
1053 | set_gdbarch_value_to_register (gdbarch, spu_value_to_register); | |
1054 | set_gdbarch_register_reggroup_p (gdbarch, spu_register_reggroup_p); | |
1055 | ||
1056 | /* Data types. */ | |
1057 | set_gdbarch_char_signed (gdbarch, 0); | |
1058 | set_gdbarch_ptr_bit (gdbarch, 32); | |
1059 | set_gdbarch_addr_bit (gdbarch, 32); | |
1060 | set_gdbarch_short_bit (gdbarch, 16); | |
1061 | set_gdbarch_int_bit (gdbarch, 32); | |
1062 | set_gdbarch_long_bit (gdbarch, 32); | |
1063 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1064 | set_gdbarch_float_bit (gdbarch, 32); | |
1065 | set_gdbarch_double_bit (gdbarch, 64); | |
1066 | set_gdbarch_long_double_bit (gdbarch, 64); | |
1067 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); | |
1068 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big); | |
1069 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
1070 | ||
1071 | /* Inferior function calls. */ | |
1072 | set_gdbarch_push_dummy_call (gdbarch, spu_push_dummy_call); | |
1073 | set_gdbarch_unwind_dummy_id (gdbarch, spu_unwind_dummy_id); | |
1074 | set_gdbarch_return_value (gdbarch, spu_return_value); | |
1075 | ||
1076 | /* Frame handling. */ | |
1077 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1078 | frame_unwind_append_sniffer (gdbarch, spu_frame_sniffer); | |
1079 | frame_base_set_default (gdbarch, &spu_frame_base); | |
1080 | set_gdbarch_unwind_pc (gdbarch, spu_unwind_pc); | |
1081 | set_gdbarch_unwind_sp (gdbarch, spu_unwind_sp); | |
1082 | set_gdbarch_virtual_frame_pointer (gdbarch, spu_virtual_frame_pointer); | |
1083 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
1084 | set_gdbarch_skip_prologue (gdbarch, spu_skip_prologue); | |
1085 | ||
1086 | /* Breakpoints. */ | |
1087 | set_gdbarch_decr_pc_after_break (gdbarch, 4); | |
1088 | set_gdbarch_breakpoint_from_pc (gdbarch, spu_breakpoint_from_pc); | |
1089 | set_gdbarch_cannot_step_breakpoint (gdbarch, 1); | |
1090 | set_gdbarch_software_single_step (gdbarch, spu_software_single_step); | |
1091 | ||
1092 | return gdbarch; | |
1093 | } | |
1094 | ||
1095 | void | |
1096 | _initialize_spu_tdep (void) | |
1097 | { | |
1098 | register_gdbarch_init (bfd_arch_spu, spu_gdbarch_init); | |
1099 | } |