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Use ui_out_emit_tuple in more places
[deliverable/binutils-gdb.git] / gdb / spu-tdep.c
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771b4502 1/* SPU target-dependent code for GDB, the GNU debugger.
61baf725 2 Copyright (C) 2006-2017 Free Software Foundation, Inc.
771b4502
UW		 3
4 Contributed by Ulrich Weigand <uweigand@de.ibm.com>.
5 Based on a port by Sid Manning <sid@us.ibm.com>.
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
a9762ec7 11 the Free Software Foundation; either version 3 of the License, or
771b4502
UW		 12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
a9762ec7 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
771b4502
UW		 21
22#include "defs.h"
23#include "arch-utils.h"
24#include "gdbtypes.h"
25#include "gdbcmd.h"
26#include "gdbcore.h"
771b4502
UW		 27#include "frame.h"
28#include "frame-unwind.h"
29#include "frame-base.h"
30#include "trad-frame.h"
31#include "symtab.h"
32#include "symfile.h"
33#include "value.h"
34#include "inferior.h"
35#include "dis-asm.h"
e47ad6c0 36#include "disasm.h"
771b4502
UW		 37#include "objfiles.h"
38#include "language.h"
39#include "regcache.h"
40#include "reggroups.h"
41#include "floatformat.h"
3285f3fe 42#include "block.h"
dcf52cd8 43#include "observer.h"
ff1a52c6 44#include "infcall.h"
54fcddd0 45#include "dwarf2.h"
7ce16bd4
UW		 46#include "dwarf2-frame.h"
47#include "ax.h"
771b4502 48#include "spu-tdep.h"
f00aae0f 49#include "location.h"
794ac428 50
3285f3fe
UW		 51/* The list of available "set spu " and "show spu " commands. */
52static struct cmd_list_element *setspucmdlist = NULL;
53static struct cmd_list_element *showspucmdlist = NULL;
54
55/* Whether to stop for new SPE contexts. */
56static int spu_stop_on_load_p = 0;
ff1a52c6
UW		 57/* Whether to automatically flush the SW-managed cache. */
58static int spu_auto_flush_cache_p = 1;
3285f3fe
UW		 59
60
794ac428
UW		 61/* The tdep structure. */
62struct gdbarch_tdep
63{
85e747d2
UW		 64 /* The spufs ID identifying our address space. */
65 int id;
66
794ac428
UW		 67 /* SPU-specific vector type. */
68 struct type *spu_builtin_type_vec128;
69};
70
71
f2d43c2c 72/* SPU-specific vector type. */
794ac428
UW		 73static struct type *
74spu_builtin_type_vec128 (struct gdbarch *gdbarch)
75{
76 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
77
78 if (!tdep->spu_builtin_type_vec128)
79 {
df4df182 80 const struct builtin_type *bt = builtin_type (gdbarch);
794ac428
UW		 81 struct type *t;
82
e9bb382b
UW		 83 t = arch_composite_type (gdbarch,
84 "__spu_builtin_type_vec128", TYPE_CODE_UNION);
df4df182 85 append_composite_type_field (t, "uint128", bt->builtin_int128);
794ac428 86 append_composite_type_field (t, "v2_int64",
df4df182 87 init_vector_type (bt->builtin_int64, 2));
794ac428 88 append_composite_type_field (t, "v4_int32",
df4df182 89 init_vector_type (bt->builtin_int32, 4));
794ac428 90 append_composite_type_field (t, "v8_int16",
df4df182 91 init_vector_type (bt->builtin_int16, 8));
794ac428 92 append_composite_type_field (t, "v16_int8",
df4df182 93 init_vector_type (bt->builtin_int8, 16));
794ac428 94 append_composite_type_field (t, "v2_double",
df4df182 95 init_vector_type (bt->builtin_double, 2));
794ac428 96 append_composite_type_field (t, "v4_float",
df4df182 97 init_vector_type (bt->builtin_float, 4));
794ac428 98
876cecd0 99 TYPE_VECTOR (t) = 1;
794ac428
UW		 100 TYPE_NAME (t) = "spu_builtin_type_vec128";
101
102 tdep->spu_builtin_type_vec128 = t;
103 }
104
105 return tdep->spu_builtin_type_vec128;
106}
107
771b4502 108
23d964e7
UW		 109/* The list of available "info spu " commands. */
110static struct cmd_list_element *infospucmdlist = NULL;
111
771b4502
UW		 112/* Registers. */
113
114static const char *
d93859e2 115spu_register_name (struct gdbarch *gdbarch, int reg_nr)
771b4502 116{
a121b7c1 117 static const char *register_names[] =
771b4502
UW		 118 {
119 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
120 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
121 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
122 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
123 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
124 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
125 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
126 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
127 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
128 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
129 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
130 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
131 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
132 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
133 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
134 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
23d964e7 135 "id", "pc", "sp", "fpscr", "srr0", "lslr", "decr", "decr_status"
771b4502
UW		 136 };
137
138 if (reg_nr < 0)
139 return NULL;
140 if (reg_nr >= sizeof register_names / sizeof *register_names)
141 return NULL;
142
143 return register_names[reg_nr];
144}
145
146static struct type *
147spu_register_type (struct gdbarch *gdbarch, int reg_nr)
148{
149 if (reg_nr < SPU_NUM_GPRS)
794ac428 150 return spu_builtin_type_vec128 (gdbarch);
771b4502
UW		 151
152 switch (reg_nr)
153 {
154 case SPU_ID_REGNUM:
df4df182 155 return builtin_type (gdbarch)->builtin_uint32;
771b4502
UW		 156
157 case SPU_PC_REGNUM:
0dfff4cb 158 return builtin_type (gdbarch)->builtin_func_ptr;
771b4502
UW		 159
160 case SPU_SP_REGNUM:
0dfff4cb 161 return builtin_type (gdbarch)->builtin_data_ptr;
771b4502 162
23d964e7 163 case SPU_FPSCR_REGNUM:
df4df182 164 return builtin_type (gdbarch)->builtin_uint128;
23d964e7
UW		 165
166 case SPU_SRR0_REGNUM:
df4df182 167 return builtin_type (gdbarch)->builtin_uint32;
23d964e7
UW		 168
169 case SPU_LSLR_REGNUM:
df4df182 170 return builtin_type (gdbarch)->builtin_uint32;
23d964e7
UW		 171
172 case SPU_DECR_REGNUM:
df4df182 173 return builtin_type (gdbarch)->builtin_uint32;
23d964e7
UW		 174
175 case SPU_DECR_STATUS_REGNUM:
df4df182 176 return builtin_type (gdbarch)->builtin_uint32;
23d964e7 177
771b4502 178 default:
a73c6dcd 179 internal_error (__FILE__, __LINE__, _("invalid regnum"));
771b4502
UW		 180 }
181}
182
183/* Pseudo registers for preferred slots - stack pointer. */
184
05d1431c 185static enum register_status
23d964e7
UW		 186spu_pseudo_register_read_spu (struct regcache *regcache, const char *regname,
187 gdb_byte *buf)
188{
e17a4113
UW		 189 struct gdbarch *gdbarch = get_regcache_arch (regcache);
190 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
05d1431c 191 enum register_status status;
23d964e7
UW		 192 gdb_byte reg[32];
193 char annex[32];
194 ULONGEST id;
001f13d8 195 ULONGEST ul;
23d964e7 196
05d1431c
PA		 197 status = regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
198 if (status != REG_VALID)
199 return status;
23d964e7
UW		 200 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
201 memset (reg, 0, sizeof reg);
202 target_read (&current_target, TARGET_OBJECT_SPU, annex,
203 reg, 0, sizeof reg);
204
001f13d8
PA		 205 ul = strtoulst ((char *) reg, NULL, 16);
206 store_unsigned_integer (buf, 4, byte_order, ul);
05d1431c 207 return REG_VALID;
23d964e7
UW		 208}
209
05d1431c 210static enum register_status
771b4502
UW		 211spu_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
212 int regnum, gdb_byte *buf)
213{
214 gdb_byte reg[16];
23d964e7
UW		 215 char annex[32];
216 ULONGEST id;
05d1431c 217 enum register_status status;
771b4502
UW		 218
219 switch (regnum)
220 {
221 case SPU_SP_REGNUM:
05d1431c
PA		 222 status = regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
223 if (status != REG_VALID)
224 return status;
771b4502 225 memcpy (buf, reg, 4);
05d1431c 226 return status;
771b4502 227
23d964e7 228 case SPU_FPSCR_REGNUM:
05d1431c
PA		 229 status = regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
230 if (status != REG_VALID)
231 return status;
23d964e7
UW		 232 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
233 target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
05d1431c 234 return status;
23d964e7
UW		 235
236 case SPU_SRR0_REGNUM:
05d1431c 237 return spu_pseudo_register_read_spu (regcache, "srr0", buf);
23d964e7
UW		 238
239 case SPU_LSLR_REGNUM:
05d1431c 240 return spu_pseudo_register_read_spu (regcache, "lslr", buf);
23d964e7
UW		 241
242 case SPU_DECR_REGNUM:
05d1431c 243 return spu_pseudo_register_read_spu (regcache, "decr", buf);
23d964e7
UW		 244
245 case SPU_DECR_STATUS_REGNUM:
05d1431c 246 return spu_pseudo_register_read_spu (regcache, "decr_status", buf);
23d964e7 247
771b4502
UW		 248 default:
249 internal_error (__FILE__, __LINE__, _("invalid regnum"));
250 }
251}
252
23d964e7
UW		 253static void
254spu_pseudo_register_write_spu (struct regcache *regcache, const char *regname,
255 const gdb_byte *buf)
256{
e17a4113
UW		 257 struct gdbarch *gdbarch = get_regcache_arch (regcache);
258 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
001f13d8 259 char reg[32];
23d964e7
UW		 260 char annex[32];
261 ULONGEST id;
262
263 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
264 xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
265 xsnprintf (reg, sizeof reg, "0x%s",
e17a4113 266 phex_nz (extract_unsigned_integer (buf, 4, byte_order), 4));
23d964e7 267 target_write (&current_target, TARGET_OBJECT_SPU, annex,
001f13d8 268 (gdb_byte *) reg, 0, strlen (reg));
23d964e7
UW		 269}
270
771b4502
UW		 271static void
272spu_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
273 int regnum, const gdb_byte *buf)
274{
275 gdb_byte reg[16];
23d964e7
UW		 276 char annex[32];
277 ULONGEST id;
771b4502
UW		 278
279 switch (regnum)
280 {
281 case SPU_SP_REGNUM:
282 regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
283 memcpy (reg, buf, 4);
284 regcache_raw_write (regcache, SPU_RAW_SP_REGNUM, reg);
285 break;
286
23d964e7
UW		 287 case SPU_FPSCR_REGNUM:
288 regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
289 xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
290 target_write (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
291 break;
292
293 case SPU_SRR0_REGNUM:
294 spu_pseudo_register_write_spu (regcache, "srr0", buf);
295 break;
296
297 case SPU_LSLR_REGNUM:
298 spu_pseudo_register_write_spu (regcache, "lslr", buf);
299 break;
300
301 case SPU_DECR_REGNUM:
302 spu_pseudo_register_write_spu (regcache, "decr", buf);
303 break;
304
305 case SPU_DECR_STATUS_REGNUM:
306 spu_pseudo_register_write_spu (regcache, "decr_status", buf);
307 break;
308
771b4502
UW		 309 default:
310 internal_error (__FILE__, __LINE__, _("invalid regnum"));
311 }
312}
313
7ce16bd4
UW		 314static int
315spu_ax_pseudo_register_collect (struct gdbarch *gdbarch,
316 struct agent_expr *ax, int regnum)
317{
318 switch (regnum)
319 {
320 case SPU_SP_REGNUM:
321 ax_reg_mask (ax, SPU_RAW_SP_REGNUM);
322 return 0;
323
324 case SPU_FPSCR_REGNUM:
325 case SPU_SRR0_REGNUM:
326 case SPU_LSLR_REGNUM:
327 case SPU_DECR_REGNUM:
328 case SPU_DECR_STATUS_REGNUM:
329 return -1;
330
331 default:
332 internal_error (__FILE__, __LINE__, _("invalid regnum"));
333 }
334}
335
336static int
337spu_ax_pseudo_register_push_stack (struct gdbarch *gdbarch,
338 struct agent_expr *ax, int regnum)
339{
340 switch (regnum)
341 {
342 case SPU_SP_REGNUM:
343 ax_reg (ax, SPU_RAW_SP_REGNUM);
344 return 0;
345
346 case SPU_FPSCR_REGNUM:
347 case SPU_SRR0_REGNUM:
348 case SPU_LSLR_REGNUM:
349 case SPU_DECR_REGNUM:
350 case SPU_DECR_STATUS_REGNUM:
351 return -1;
352
353 default:
354 internal_error (__FILE__, __LINE__, _("invalid regnum"));
355 }
356}
357
358
771b4502
UW		 359/* Value conversion -- access scalar values at the preferred slot. */
360
9acbedc0 361static struct value *
2ed3c037
UW		 362spu_value_from_register (struct gdbarch *gdbarch, struct type *type,
363 int regnum, struct frame_id frame_id)
771b4502 364{
2ed3c037
UW		 365 struct value *value = default_value_from_register (gdbarch, type,
366 regnum, frame_id);
6b850546 367 LONGEST len = TYPE_LENGTH (type);
771b4502 368
bad43aa5 369 if (regnum < SPU_NUM_GPRS && len < 16)
9acbedc0 370 {
bad43aa5 371 int preferred_slot = len < 4 ? 4 - len : 0;
9acbedc0
UW		 372 set_value_offset (value, preferred_slot);
373 }
771b4502 374
9acbedc0 375 return value;
771b4502
UW		 376}
377
378/* Register groups. */
379
380static int
381spu_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
382 struct reggroup *group)
383{
384 /* Registers displayed via 'info regs'. */
385 if (group == general_reggroup)
386 return 1;
387
388 /* Registers displayed via 'info float'. */
389 if (group == float_reggroup)
390 return 0;
391
392 /* Registers that need to be saved/restored in order to
393 push or pop frames. */
394 if (group == save_reggroup || group == restore_reggroup)
395 return 1;
396
397 return default_register_reggroup_p (gdbarch, regnum, group);
398}
399
7ce16bd4
UW		 400/* DWARF-2 register numbers. */
401
402static int
403spu_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
404{
405 /* Use cooked instead of raw SP. */
406 return (reg == SPU_RAW_SP_REGNUM)? SPU_SP_REGNUM : reg;
407}
408
ff1a52c6
UW		 409
410/* Address handling. */
36acd84e 411
85e747d2
UW		 412static int
413spu_gdbarch_id (struct gdbarch *gdbarch)
414{
415 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
416 int id = tdep->id;
417
418 /* The objfile architecture of a standalone SPU executable does not
b021a221 419 provide an SPU ID. Retrieve it from the objfile's relocated
85e747d2
UW		 420 address range in this special case. */
421 if (id == -1
422 && symfile_objfile && symfile_objfile->obfd
423 && bfd_get_arch (symfile_objfile->obfd) == bfd_arch_spu
424 && symfile_objfile->sections != symfile_objfile->sections_end)
425 id = SPUADDR_SPU (obj_section_addr (symfile_objfile->sections));
426
427 return id;
428}
429
ff1a52c6
UW		 430static int
431spu_address_class_type_flags (int byte_size, int dwarf2_addr_class)
432{
433 if (dwarf2_addr_class == 1)
434 return TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1;
435 else
436 return 0;
437}
438
439static const char *
440spu_address_class_type_flags_to_name (struct gdbarch *gdbarch, int type_flags)
441{
442 if (type_flags & TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1)
443 return "__ea";
444 else
445 return NULL;
446}
447
448static int
449spu_address_class_name_to_type_flags (struct gdbarch *gdbarch,
450 const char *name, int *type_flags_ptr)
451{
452 if (strcmp (name, "__ea") == 0)
453 {
454 *type_flags_ptr = TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1;
455 return 1;
456 }
457 else
458 return 0;
459}
460
85e747d2
UW		 461static void
462spu_address_to_pointer (struct gdbarch *gdbarch,
463 struct type *type, gdb_byte *buf, CORE_ADDR addr)
464{
465 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
466 store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order,
467 SPUADDR_ADDR (addr));
468}
469
36acd84e 470static CORE_ADDR
9898f801
UW		 471spu_pointer_to_address (struct gdbarch *gdbarch,
472 struct type *type, const gdb_byte *buf)
36acd84e 473{
85e747d2 474 int id = spu_gdbarch_id (gdbarch);
e17a4113
UW		 475 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
476 ULONGEST addr
477 = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order);
36acd84e 478
ff1a52c6
UW		 479 /* Do not convert __ea pointers. */
480 if (TYPE_ADDRESS_CLASS_1 (type))
481 return addr;
482
d2ed6730 483 return addr? SPUADDR (id, addr) : 0;
36acd84e
UW		 484}
485
486static CORE_ADDR
487spu_integer_to_address (struct gdbarch *gdbarch,
488 struct type *type, const gdb_byte *buf)
489{
85e747d2 490 int id = spu_gdbarch_id (gdbarch);
36acd84e 491 ULONGEST addr = unpack_long (type, buf);
36acd84e 492
d2ed6730 493 return SPUADDR (id, addr);
36acd84e
UW		 494}
495
771b4502
UW		 496
497/* Decoding SPU instructions. */
498
499enum
500 {
501 op_lqd = 0x34,
502 op_lqx = 0x3c4,
503 op_lqa = 0x61,
504 op_lqr = 0x67,
505 op_stqd = 0x24,
506 op_stqx = 0x144,
507 op_stqa = 0x41,
508 op_stqr = 0x47,
509
510 op_il = 0x081,
511 op_ila = 0x21,
512 op_a = 0x0c0,
513 op_ai = 0x1c,
514
a536c6d7 515 op_selb = 0x8,
771b4502
UW		 516
517 op_br = 0x64,
518 op_bra = 0x60,
519 op_brsl = 0x66,
520 op_brasl = 0x62,
521 op_brnz = 0x42,
522 op_brz = 0x40,
523 op_brhnz = 0x46,
524 op_brhz = 0x44,
525 op_bi = 0x1a8,
526 op_bisl = 0x1a9,
527 op_biz = 0x128,
528 op_binz = 0x129,
529 op_bihz = 0x12a,
530 op_bihnz = 0x12b,
531 };
532
533static int
534is_rr (unsigned int insn, int op, int *rt, int *ra, int *rb)
535{
536 if ((insn >> 21) == op)
537 {
538 *rt = insn & 127;
539 *ra = (insn >> 7) & 127;
540 *rb = (insn >> 14) & 127;
541 return 1;
542 }
543
544 return 0;
545}
546
547static int
548is_rrr (unsigned int insn, int op, int *rt, int *ra, int *rb, int *rc)
549{
550 if ((insn >> 28) == op)
551 {
552 *rt = (insn >> 21) & 127;
553 *ra = (insn >> 7) & 127;
554 *rb = (insn >> 14) & 127;
555 *rc = insn & 127;
556 return 1;
557 }
558
559 return 0;
560}
561
562static int
563is_ri7 (unsigned int insn, int op, int *rt, int *ra, int *i7)
564{
565 if ((insn >> 21) == op)
566 {
567 *rt = insn & 127;
568 *ra = (insn >> 7) & 127;
569 *i7 = (((insn >> 14) & 127) ^ 0x40) - 0x40;
570 return 1;
571 }
572
573 return 0;
574}
575
576static int
577is_ri10 (unsigned int insn, int op, int *rt, int *ra, int *i10)
578{
579 if ((insn >> 24) == op)
580 {
581 *rt = insn & 127;
582 *ra = (insn >> 7) & 127;
583 *i10 = (((insn >> 14) & 0x3ff) ^ 0x200) - 0x200;
584 return 1;
585 }
586
587 return 0;
588}
589
590static int
591is_ri16 (unsigned int insn, int op, int *rt, int *i16)
592{
593 if ((insn >> 23) == op)
594 {
595 *rt = insn & 127;
596 *i16 = (((insn >> 7) & 0xffff) ^ 0x8000) - 0x8000;
597 return 1;
598 }
599
600 return 0;
601}
602
603static int
604is_ri18 (unsigned int insn, int op, int *rt, int *i18)
605{
606 if ((insn >> 25) == op)
607 {
608 *rt = insn & 127;
609 *i18 = (((insn >> 7) & 0x3ffff) ^ 0x20000) - 0x20000;
610 return 1;
611 }
612
613 return 0;
614}
615
616static int
617is_branch (unsigned int insn, int *offset, int *reg)
618{
619 int rt, i7, i16;
620
621 if (is_ri16 (insn, op_br, &rt, &i16)
622 || is_ri16 (insn, op_brsl, &rt, &i16)
623 || is_ri16 (insn, op_brnz, &rt, &i16)
624 || is_ri16 (insn, op_brz, &rt, &i16)
625 || is_ri16 (insn, op_brhnz, &rt, &i16)
626 || is_ri16 (insn, op_brhz, &rt, &i16))
627 {
628 *reg = SPU_PC_REGNUM;
629 *offset = i16 << 2;
630 return 1;
631 }
632
633 if (is_ri16 (insn, op_bra, &rt, &i16)
634 || is_ri16 (insn, op_brasl, &rt, &i16))
635 {
636 *reg = -1;
637 *offset = i16 << 2;
638 return 1;
639 }
640
641 if (is_ri7 (insn, op_bi, &rt, reg, &i7)
642 || is_ri7 (insn, op_bisl, &rt, reg, &i7)
643 || is_ri7 (insn, op_biz, &rt, reg, &i7)
644 || is_ri7 (insn, op_binz, &rt, reg, &i7)
645 || is_ri7 (insn, op_bihz, &rt, reg, &i7)
646 || is_ri7 (insn, op_bihnz, &rt, reg, &i7))
647 {
648 *offset = 0;
649 return 1;
650 }
651
652 return 0;
653}
654
655
656/* Prolog parsing. */
657
658struct spu_prologue_data
659 {
660 /* Stack frame size. -1 if analysis was unsuccessful. */
661 int size;
662
663 /* How to find the CFA. The CFA is equal to SP at function entry. */
664 int cfa_reg;
665 int cfa_offset;
666
667 /* Offset relative to CFA where a register is saved. -1 if invalid. */
668 int reg_offset[SPU_NUM_GPRS];
669 };
670
671static CORE_ADDR
e17a4113
UW		 672spu_analyze_prologue (struct gdbarch *gdbarch,
673 CORE_ADDR start_pc, CORE_ADDR end_pc,
771b4502
UW		 674 struct spu_prologue_data *data)
675{
e17a4113 676 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
771b4502
UW		 677 int found_sp = 0;
678 int found_fp = 0;
679 int found_lr = 0;
ce50d78b 680 int found_bc = 0;
771b4502
UW		 681 int reg_immed[SPU_NUM_GPRS];
682 gdb_byte buf[16];
683 CORE_ADDR prolog_pc = start_pc;
684 CORE_ADDR pc;
685 int i;
686
687
688 /* Initialize DATA to default values. */
689 data->size = -1;
690
691 data->cfa_reg = SPU_RAW_SP_REGNUM;
692 data->cfa_offset = 0;
693
694 for (i = 0; i < SPU_NUM_GPRS; i++)
695 data->reg_offset[i] = -1;
696
697 /* Set up REG_IMMED array. This is non-zero for a register if we know its
698 preferred slot currently holds this immediate value. */
699 for (i = 0; i < SPU_NUM_GPRS; i++)
700 reg_immed[i] = 0;
701
702 /* Scan instructions until the first branch.
703
704 The following instructions are important prolog components:
705
706 - The first instruction to set up the stack pointer.
707 - The first instruction to set up the frame pointer.
708 - The first instruction to save the link register.
ce50d78b 709 - The first instruction to save the backchain.
771b4502 710
ce50d78b 711 We return the instruction after the latest of these four,
771b4502
UW		 712 or the incoming PC if none is found. The first instruction
713 to set up the stack pointer also defines the frame size.
714
715 Note that instructions saving incoming arguments to their stack
716 slots are not counted as important, because they are hard to
717 identify with certainty. This should not matter much, because
718 arguments are relevant only in code compiled with debug data,
719 and in such code the GDB core will advance until the first source
720 line anyway, using SAL data.
721
722 For purposes of stack unwinding, we analyze the following types
723 of instructions in addition:
724
725 - Any instruction adding to the current frame pointer.
726 - Any instruction loading an immediate constant into a register.
727 - Any instruction storing a register onto the stack.
728
729 These are used to compute the CFA and REG_OFFSET output. */
730
731 for (pc = start_pc; pc < end_pc; pc += 4)
732 {
733 unsigned int insn;
734 int rt, ra, rb, rc, immed;
735
736 if (target_read_memory (pc, buf, 4))
737 break;
e17a4113 738 insn = extract_unsigned_integer (buf, 4, byte_order);
771b4502
UW		 739
740 /* AI is the typical instruction to set up a stack frame.
741 It is also used to initialize the frame pointer. */
742 if (is_ri10 (insn, op_ai, &rt, &ra, &immed))
743 {
744 if (rt == data->cfa_reg && ra == data->cfa_reg)
745 data->cfa_offset -= immed;
746
747 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
748 && !found_sp)
749 {
750 found_sp = 1;
751 prolog_pc = pc + 4;
752
753 data->size = -immed;
754 }
755 else if (rt == SPU_FP_REGNUM && ra == SPU_RAW_SP_REGNUM
756 && !found_fp)
757 {
758 found_fp = 1;
759 prolog_pc = pc + 4;
760
761 data->cfa_reg = SPU_FP_REGNUM;
762 data->cfa_offset -= immed;
763 }
764 }
765
766 /* A is used to set up stack frames of size >= 512 bytes.
767 If we have tracked the contents of the addend register,
768 we can handle this as well. */
769 else if (is_rr (insn, op_a, &rt, &ra, &rb))
770 {
771 if (rt == data->cfa_reg && ra == data->cfa_reg)
772 {
773 if (reg_immed[rb] != 0)
774 data->cfa_offset -= reg_immed[rb];
775 else
776 data->cfa_reg = -1; /* We don't know the CFA any more. */
777 }
778
779 if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
780 && !found_sp)
781 {
782 found_sp = 1;
783 prolog_pc = pc + 4;
784
785 if (reg_immed[rb] != 0)
786 data->size = -reg_immed[rb];
787 }
788 }
789
790 /* We need to track IL and ILA used to load immediate constants
791 in case they are later used as input to an A instruction. */
792 else if (is_ri16 (insn, op_il, &rt, &immed))
793 {
794 reg_immed[rt] = immed;
12102450
UW		 795
796 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
797 found_sp = 1;
771b4502
UW		 798 }
799
800 else if (is_ri18 (insn, op_ila, &rt, &immed))
801 {
802 reg_immed[rt] = immed & 0x3ffff;
12102450
UW		 803
804 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
805 found_sp = 1;
771b4502
UW		 806 }
807
808 /* STQD is used to save registers to the stack. */
809 else if (is_ri10 (insn, op_stqd, &rt, &ra, &immed))
810 {
811 if (ra == data->cfa_reg)
812 data->reg_offset[rt] = data->cfa_offset - (immed << 4);
813
814 if (ra == data->cfa_reg && rt == SPU_LR_REGNUM
815 && !found_lr)
816 {
817 found_lr = 1;
818 prolog_pc = pc + 4;
819 }
ce50d78b
UW		 820
821 if (ra == SPU_RAW_SP_REGNUM
822 && (found_sp? immed == 0 : rt == SPU_RAW_SP_REGNUM)
823 && !found_bc)
824 {
825 found_bc = 1;
826 prolog_pc = pc + 4;
827 }
771b4502
UW		 828 }
829
830 /* _start uses SELB to set up the stack pointer. */
831 else if (is_rrr (insn, op_selb, &rt, &ra, &rb, &rc))
832 {
833 if (rt == SPU_RAW_SP_REGNUM && !found_sp)
834 found_sp = 1;
835 }
836
837 /* We terminate if we find a branch. */
838 else if (is_branch (insn, &immed, &ra))
839 break;
840 }
841
842
843 /* If we successfully parsed until here, and didn't find any instruction
844 modifying SP, we assume we have a frameless function. */
845 if (!found_sp)
846 data->size = 0;
847
848 /* Return cooked instead of raw SP. */
849 if (data->cfa_reg == SPU_RAW_SP_REGNUM)
850 data->cfa_reg = SPU_SP_REGNUM;
851
852 return prolog_pc;
853}
854
855/* Return the first instruction after the prologue starting at PC. */
856static CORE_ADDR
6093d2eb 857spu_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
771b4502
UW		 858{
859 struct spu_prologue_data data;
e17a4113 860 return spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data);
771b4502
UW		 861}
862
863/* Return the frame pointer in use at address PC. */
864static void
a54fba4c
MD		 865spu_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc,
866 int *reg, LONGEST *offset)
771b4502
UW		 867{
868 struct spu_prologue_data data;
e17a4113 869 spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data);
771b4502
UW		 870
871 if (data.size != -1 && data.cfa_reg != -1)
872 {
873 /* The 'frame pointer' address is CFA minus frame size. */
874 *reg = data.cfa_reg;
875 *offset = data.cfa_offset - data.size;
876 }
877 else
878 {
c378eb4e 879 /* ??? We don't really know ... */
771b4502
UW		 880 *reg = SPU_SP_REGNUM;
881 *offset = 0;
882 }
883}
884
c9cf6e20 885/* Implement the stack_frame_destroyed_p gdbarch method.
fe5febed
UW		 886
887 1) scan forward from the point of execution:
888 a) If you find an instruction that modifies the stack pointer
889 or transfers control (except a return), execution is not in
890 an epilogue, return.
891 b) Stop scanning if you find a return instruction or reach the
892 end of the function or reach the hard limit for the size of
893 an epilogue.
894 2) scan backward from the point of execution:
895 a) If you find an instruction that modifies the stack pointer,
896 execution *is* in an epilogue, return.
897 b) Stop scanning if you reach an instruction that transfers
898 control or the beginning of the function or reach the hard
899 limit for the size of an epilogue. */
900
901static int
c9cf6e20 902spu_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
fe5febed 903{
e17a4113 904 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
fe5febed
UW		 905 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
906 bfd_byte buf[4];
907 unsigned int insn;
22e048c9 908 int rt, ra, rb, immed;
fe5febed
UW		 909
910 /* Find the search limits based on function boundaries and hard limit.
911 We assume the epilogue can be up to 64 instructions long. */
912
913 const int spu_max_epilogue_size = 64 * 4;
914
915 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
916 return 0;
917
918 if (pc - func_start < spu_max_epilogue_size)
919 epilogue_start = func_start;
920 else
921 epilogue_start = pc - spu_max_epilogue_size;
922
923 if (func_end - pc < spu_max_epilogue_size)
924 epilogue_end = func_end;
925 else
926 epilogue_end = pc + spu_max_epilogue_size;
927
928 /* Scan forward until next 'bi $0'. */
929
930 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += 4)
931 {
932 if (target_read_memory (scan_pc, buf, 4))
933 return 0;
e17a4113 934 insn = extract_unsigned_integer (buf, 4, byte_order);
fe5febed
UW		 935
936 if (is_branch (insn, &immed, &ra))
937 {
938 if (immed == 0 && ra == SPU_LR_REGNUM)
939 break;
940
941 return 0;
942 }
943
944 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
945 || is_rr (insn, op_a, &rt, &ra, &rb)
946 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
947 {
948 if (rt == SPU_RAW_SP_REGNUM)
949 return 0;
950 }
951 }
952
953 if (scan_pc >= epilogue_end)
954 return 0;
955
956 /* Scan backward until adjustment to stack pointer (R1). */
957
958 for (scan_pc = pc - 4; scan_pc >= epilogue_start; scan_pc -= 4)
959 {
960 if (target_read_memory (scan_pc, buf, 4))
961 return 0;
e17a4113 962 insn = extract_unsigned_integer (buf, 4, byte_order);
fe5febed
UW		 963
964 if (is_branch (insn, &immed, &ra))
965 return 0;
966
967 if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
968 || is_rr (insn, op_a, &rt, &ra, &rb)
969 || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
970 {
971 if (rt == SPU_RAW_SP_REGNUM)
972 return 1;
973 }
974 }
975
976 return 0;
977}
978
979
771b4502
UW		 980/* Normal stack frames. */
981
982struct spu_unwind_cache
983{
984 CORE_ADDR func;
985 CORE_ADDR frame_base;
986 CORE_ADDR local_base;
987
988 struct trad_frame_saved_reg *saved_regs;
989};
990
991static struct spu_unwind_cache *
8d998b8f 992spu_frame_unwind_cache (struct frame_info *this_frame,
771b4502
UW		 993 void **this_prologue_cache)
994{
e17a4113 995 struct gdbarch *gdbarch = get_frame_arch (this_frame);
85e747d2 996 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 997 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
771b4502
UW		 998 struct spu_unwind_cache *info;
999 struct spu_prologue_data data;
85e747d2 1000 CORE_ADDR id = tdep->id;
dcf52cd8 1001 gdb_byte buf[16];
771b4502
UW		 1002
1003 if (*this_prologue_cache)
19ba03f4 1004 return (struct spu_unwind_cache *) *this_prologue_cache;
771b4502
UW		 1005
1006 info = FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache);
1007 *this_prologue_cache = info;
8d998b8f 1008 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
771b4502
UW		 1009 info->frame_base = 0;
1010 info->local_base = 0;
1011
1012 /* Find the start of the current function, and analyze its prologue. */
8d998b8f 1013 info->func = get_frame_func (this_frame);
771b4502
UW		 1014 if (info->func == 0)
1015 {
1016 /* Fall back to using the current PC as frame ID. */
8d998b8f 1017 info->func = get_frame_pc (this_frame);
771b4502
UW		 1018 data.size = -1;
1019 }
1020 else
e17a4113
UW		 1021 spu_analyze_prologue (gdbarch, info->func, get_frame_pc (this_frame),
1022 &data);
771b4502
UW		 1023
1024 /* If successful, use prologue analysis data. */
1025 if (data.size != -1 && data.cfa_reg != -1)
1026 {
1027 CORE_ADDR cfa;
1028 int i;
771b4502
UW		 1029
1030 /* Determine CFA via unwound CFA_REG plus CFA_OFFSET. */
8d998b8f 1031 get_frame_register (this_frame, data.cfa_reg, buf);
e17a4113 1032 cfa = extract_unsigned_integer (buf, 4, byte_order) + data.cfa_offset;
85e747d2 1033 cfa = SPUADDR (id, cfa);
771b4502
UW		 1034
1035 /* Call-saved register slots. */
1036 for (i = 0; i < SPU_NUM_GPRS; i++)
1037 if (i == SPU_LR_REGNUM
1038 || (i >= SPU_SAVED1_REGNUM && i <= SPU_SAVEDN_REGNUM))
1039 if (data.reg_offset[i] != -1)
1040 info->saved_regs[i].addr = cfa - data.reg_offset[i];
1041
771b4502
UW		 1042 /* Frame bases. */
1043 info->frame_base = cfa;
1044 info->local_base = cfa - data.size;
1045 }
1046
1047 /* Otherwise, fall back to reading the backchain link. */
1048 else
1049 {
cdc9523a
UW		 1050 CORE_ADDR reg;
1051 LONGEST backchain;
13def385 1052 ULONGEST lslr;
cdc9523a 1053 int status;
771b4502 1054
13def385
UW		 1055 /* Get local store limit. */
1056 lslr = get_frame_register_unsigned (this_frame, SPU_LSLR_REGNUM);
1057 if (!lslr)
1058 lslr = (ULONGEST) -1;
1059
771b4502 1060 /* Get the backchain. */
8d998b8f 1061 reg = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
85e747d2
UW		 1062 status = safe_read_memory_integer (SPUADDR (id, reg), 4, byte_order,
1063 &backchain);
771b4502
UW		 1064
1065 /* A zero backchain terminates the frame chain. Also, sanity
1066 check against the local store size limit. */
13def385 1067 if (status && backchain > 0 && backchain <= lslr)
771b4502
UW		 1068 {
1069 /* Assume the link register is saved into its slot. */
13def385 1070 if (backchain + 16 <= lslr)
c378eb4e
MS		 1071 info->saved_regs[SPU_LR_REGNUM].addr = SPUADDR (id,
1072 backchain + 16);
771b4502 1073
771b4502 1074 /* Frame bases. */
85e747d2
UW		 1075 info->frame_base = SPUADDR (id, backchain);
1076 info->local_base = SPUADDR (id, reg);
771b4502
UW		 1077 }
1078 }
dcf52cd8 1079
c4891da7
UW		 1080 /* If we didn't find a frame, we cannot determine SP / return address. */
1081 if (info->frame_base == 0)
1082 return info;
1083
dcf52cd8 1084 /* The previous SP is equal to the CFA. */
85e747d2
UW		 1085 trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM,
1086 SPUADDR_ADDR (info->frame_base));
dcf52cd8 1087
0a44cb36
UW		 1088 /* Read full contents of the unwound link register in order to
1089 be able to determine the return address. */
dcf52cd8
UW		 1090 if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM))
1091 target_read_memory (info->saved_regs[SPU_LR_REGNUM].addr, buf, 16);
1092 else
8d998b8f 1093 get_frame_register (this_frame, SPU_LR_REGNUM, buf);
dcf52cd8 1094
0a44cb36
UW		 1095 /* Normally, the return address is contained in the slot 0 of the
1096 link register, and slots 1-3 are zero. For an overlay return,
1097 slot 0 contains the address of the overlay manager return stub,
1098 slot 1 contains the partition number of the overlay section to
1099 be returned to, and slot 2 contains the return address within
1100 that section. Return the latter address in that case. */
e17a4113 1101 if (extract_unsigned_integer (buf + 8, 4, byte_order) != 0)
dcf52cd8 1102 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
e17a4113 1103 extract_unsigned_integer (buf + 8, 4, byte_order));
dcf52cd8
UW		 1104 else
1105 trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
e17a4113 1106 extract_unsigned_integer (buf, 4, byte_order));
771b4502
UW		 1107
1108 return info;
1109}
1110
1111static void
8d998b8f 1112spu_frame_this_id (struct frame_info *this_frame,
771b4502
UW		 1113 void **this_prologue_cache, struct frame_id *this_id)
1114{
1115 struct spu_unwind_cache *info =
8d998b8f 1116 spu_frame_unwind_cache (this_frame, this_prologue_cache);
771b4502
UW		 1117
1118 if (info->frame_base == 0)
1119 return;
1120
1121 *this_id = frame_id_build (info->frame_base, info->func);
1122}
1123
8d998b8f
UW		 1124static struct value *
1125spu_frame_prev_register (struct frame_info *this_frame,
1126 void **this_prologue_cache, int regnum)
771b4502
UW		 1127{
1128 struct spu_unwind_cache *info
8d998b8f 1129 = spu_frame_unwind_cache (this_frame, this_prologue_cache);
771b4502
UW		 1130
1131 /* Special-case the stack pointer. */
1132 if (regnum == SPU_RAW_SP_REGNUM)
1133 regnum = SPU_SP_REGNUM;
1134
8d998b8f 1135 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
771b4502
UW		 1136}
1137
1138static const struct frame_unwind spu_frame_unwind = {
1139 NORMAL_FRAME,
8fbca658 1140 default_frame_unwind_stop_reason,
771b4502 1141 spu_frame_this_id,
8d998b8f
UW		 1142 spu_frame_prev_register,
1143 NULL,
1144 default_frame_sniffer
771b4502
UW		 1145};
1146
771b4502 1147static CORE_ADDR
8d998b8f 1148spu_frame_base_address (struct frame_info *this_frame, void **this_cache)
771b4502
UW		 1149{
1150 struct spu_unwind_cache *info
8d998b8f 1151 = spu_frame_unwind_cache (this_frame, this_cache);
771b4502
UW		 1152 return info->local_base;
1153}
1154
1155static const struct frame_base spu_frame_base = {
1156 &spu_frame_unwind,
1157 spu_frame_base_address,
1158 spu_frame_base_address,
1159 spu_frame_base_address
1160};
1161
1162static CORE_ADDR
1163spu_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1164{
85e747d2 1165 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
118dfbaf
UW		 1166 CORE_ADDR pc = frame_unwind_register_unsigned (next_frame, SPU_PC_REGNUM);
1167 /* Mask off interrupt enable bit. */
85e747d2 1168 return SPUADDR (tdep->id, pc & -4);
771b4502
UW		 1169}
1170
1171static CORE_ADDR
1172spu_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1173{
85e747d2
UW		 1174 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1175 CORE_ADDR sp = frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM);
1176 return SPUADDR (tdep->id, sp);
771b4502
UW		 1177}
1178
118dfbaf 1179static CORE_ADDR
61a1198a 1180spu_read_pc (struct regcache *regcache)
118dfbaf 1181{
85e747d2 1182 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
61a1198a
UW		 1183 ULONGEST pc;
1184 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &pc);
118dfbaf 1185 /* Mask off interrupt enable bit. */
85e747d2 1186 return SPUADDR (tdep->id, pc & -4);
118dfbaf
UW		 1187}
1188
1189static void
61a1198a 1190spu_write_pc (struct regcache *regcache, CORE_ADDR pc)
118dfbaf
UW		 1191{
1192 /* Keep interrupt enabled state unchanged. */
61a1198a 1193 ULONGEST old_pc;
30bcb456 1194
61a1198a
UW		 1195 regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &old_pc);
1196 regcache_cooked_write_unsigned (regcache, SPU_PC_REGNUM,
85e747d2 1197 (SPUADDR_ADDR (pc) & -4) | (old_pc & 3));
118dfbaf
UW		 1198}
1199
771b4502 1200
cc5f0d61
UW		 1201/* Cell/B.E. cross-architecture unwinder support. */
1202
1203struct spu2ppu_cache
1204{
1205 struct frame_id frame_id;
1206 struct regcache *regcache;
1207};
1208
1209static struct gdbarch *
1210spu2ppu_prev_arch (struct frame_info *this_frame, void **this_cache)
1211{
19ba03f4 1212 struct spu2ppu_cache *cache = (struct spu2ppu_cache *) *this_cache;
cc5f0d61
UW		 1213 return get_regcache_arch (cache->regcache);
1214}
1215
1216static void
1217spu2ppu_this_id (struct frame_info *this_frame,
1218 void **this_cache, struct frame_id *this_id)
1219{
19ba03f4 1220 struct spu2ppu_cache *cache = (struct spu2ppu_cache *) *this_cache;
cc5f0d61
UW		 1221 *this_id = cache->frame_id;
1222}
1223
1224static struct value *
1225spu2ppu_prev_register (struct frame_info *this_frame,
1226 void **this_cache, int regnum)
1227{
19ba03f4 1228 struct spu2ppu_cache *cache = (struct spu2ppu_cache *) *this_cache;
cc5f0d61
UW		 1229 struct gdbarch *gdbarch = get_regcache_arch (cache->regcache);
1230 gdb_byte *buf;
1231
224c3ddb 1232 buf = (gdb_byte *) alloca (register_size (gdbarch, regnum));
cc5f0d61
UW		 1233 regcache_cooked_read (cache->regcache, regnum, buf);
1234 return frame_unwind_got_bytes (this_frame, regnum, buf);
1235}
1236
1237static int
1238spu2ppu_sniffer (const struct frame_unwind *self,
1239 struct frame_info *this_frame, void **this_prologue_cache)
1240{
1241 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1242 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1243 CORE_ADDR base, func, backchain;
1244 gdb_byte buf[4];
1245
f5656ead 1246 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_spu)
cc5f0d61
UW		 1247 return 0;
1248
1249 base = get_frame_sp (this_frame);
1250 func = get_frame_pc (this_frame);
1251 if (target_read_memory (base, buf, 4))
1252 return 0;
1253 backchain = extract_unsigned_integer (buf, 4, byte_order);
1254
1255 if (!backchain)
1256 {
1257 struct frame_info *fi;
1258
1259 struct spu2ppu_cache *cache
1260 = FRAME_OBSTACK_CALLOC (1, struct spu2ppu_cache);
1261
1262 cache->frame_id = frame_id_build (base + 16, func);
1263
1264 for (fi = get_next_frame (this_frame); fi; fi = get_next_frame (fi))
1265 if (gdbarch_bfd_arch_info (get_frame_arch (fi))->arch != bfd_arch_spu)
1266 break;
1267
1268 if (fi)
1269 {
1270 cache->regcache = frame_save_as_regcache (fi);
1271 *this_prologue_cache = cache;
1272 return 1;
1273 }
1274 else
1275 {
1276 struct regcache *regcache;
f5656ead 1277 regcache = get_thread_arch_regcache (inferior_ptid, target_gdbarch ());
cc5f0d61
UW		 1278 cache->regcache = regcache_dup (regcache);
1279 *this_prologue_cache = cache;
1280 return 1;
1281 }
1282 }
1283
1284 return 0;
1285}
1286
1287static void
1288spu2ppu_dealloc_cache (struct frame_info *self, void *this_cache)
1289{
19ba03f4 1290 struct spu2ppu_cache *cache = (struct spu2ppu_cache *) this_cache;
cc5f0d61
UW		 1291 regcache_xfree (cache->regcache);
1292}
1293
1294static const struct frame_unwind spu2ppu_unwind = {
1295 ARCH_FRAME,
8fbca658 1296 default_frame_unwind_stop_reason,
cc5f0d61
UW		 1297 spu2ppu_this_id,
1298 spu2ppu_prev_register,
1299 NULL,
1300 spu2ppu_sniffer,
1301 spu2ppu_dealloc_cache,
1302 spu2ppu_prev_arch,
1303};
1304
1305
771b4502
UW		 1306/* Function calling convention. */
1307
7b3dc0b7
UW		 1308static CORE_ADDR
1309spu_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1310{
1311 return sp & ~15;
1312}
1313
87805e63
UW		 1314static CORE_ADDR
1315spu_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
1316 struct value **args, int nargs, struct type *value_type,
1317 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
1318 struct regcache *regcache)
1319{
1320 /* Allocate space sufficient for a breakpoint, keeping the stack aligned. */
1321 sp = (sp - 4) & ~15;
1322 /* Store the address of that breakpoint */
1323 *bp_addr = sp;
1324 /* The call starts at the callee's entry point. */
1325 *real_pc = funaddr;
1326
1327 return sp;
1328}
1329
771b4502
UW		 1330static int
1331spu_scalar_value_p (struct type *type)
1332{
1333 switch (TYPE_CODE (type))
1334 {
1335 case TYPE_CODE_INT:
1336 case TYPE_CODE_ENUM:
1337 case TYPE_CODE_RANGE:
1338 case TYPE_CODE_CHAR:
1339 case TYPE_CODE_BOOL:
1340 case TYPE_CODE_PTR:
1341 case TYPE_CODE_REF:
aa006118 1342 case TYPE_CODE_RVALUE_REF:
771b4502
UW		 1343 return TYPE_LENGTH (type) <= 16;
1344
1345 default:
1346 return 0;
1347 }
1348}
1349
1350static void
1351spu_value_to_regcache (struct regcache *regcache, int regnum,
1352 struct type *type, const gdb_byte *in)
1353{
1354 int len = TYPE_LENGTH (type);
1355
1356 if (spu_scalar_value_p (type))
1357 {
1358 int preferred_slot = len < 4 ? 4 - len : 0;
1359 regcache_cooked_write_part (regcache, regnum, preferred_slot, len, in);
1360 }
1361 else
1362 {
1363 while (len >= 16)
1364 {
1365 regcache_cooked_write (regcache, regnum++, in);
1366 in += 16;
1367 len -= 16;
1368 }
1369
1370 if (len > 0)
1371 regcache_cooked_write_part (regcache, regnum, 0, len, in);
1372 }
1373}
1374
1375static void
1376spu_regcache_to_value (struct regcache *regcache, int regnum,
1377 struct type *type, gdb_byte *out)
1378{
1379 int len = TYPE_LENGTH (type);
1380
1381 if (spu_scalar_value_p (type))
1382 {
1383 int preferred_slot = len < 4 ? 4 - len : 0;
1384 regcache_cooked_read_part (regcache, regnum, preferred_slot, len, out);
1385 }
1386 else
1387 {
1388 while (len >= 16)
1389 {
1390 regcache_cooked_read (regcache, regnum++, out);
1391 out += 16;
1392 len -= 16;
1393 }
1394
1395 if (len > 0)
1396 regcache_cooked_read_part (regcache, regnum, 0, len, out);
1397 }
1398}
1399
1400static CORE_ADDR
1401spu_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1402 struct regcache *regcache, CORE_ADDR bp_addr,
1403 int nargs, struct value **args, CORE_ADDR sp,
1404 int struct_return, CORE_ADDR struct_addr)
1405{
e17a4113 1406 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
9ff3afda 1407 CORE_ADDR sp_delta;
771b4502
UW		 1408 int i;
1409 int regnum = SPU_ARG1_REGNUM;
1410 int stack_arg = -1;
1411 gdb_byte buf[16];
1412
1413 /* Set the return address. */
1414 memset (buf, 0, sizeof buf);
85e747d2 1415 store_unsigned_integer (buf, 4, byte_order, SPUADDR_ADDR (bp_addr));
771b4502
UW		 1416 regcache_cooked_write (regcache, SPU_LR_REGNUM, buf);
1417
1418 /* If STRUCT_RETURN is true, then the struct return address (in
1419 STRUCT_ADDR) will consume the first argument-passing register.
1420 Both adjust the register count and store that value. */
1421 if (struct_return)
1422 {
1423 memset (buf, 0, sizeof buf);
85e747d2 1424 store_unsigned_integer (buf, 4, byte_order, SPUADDR_ADDR (struct_addr));
771b4502
UW		 1425 regcache_cooked_write (regcache, regnum++, buf);
1426 }
1427
1428 /* Fill in argument registers. */
1429 for (i = 0; i < nargs; i++)
1430 {
1431 struct value *arg = args[i];
1432 struct type *type = check_typedef (value_type (arg));
1433 const gdb_byte *contents = value_contents (arg);
354ecfd5 1434 int n_regs = align_up (TYPE_LENGTH (type), 16) / 16;
771b4502
UW		 1435
1436 /* If the argument doesn't wholly fit into registers, it and
1437 all subsequent arguments go to the stack. */
1438 if (regnum + n_regs - 1 > SPU_ARGN_REGNUM)
1439 {
1440 stack_arg = i;
1441 break;
1442 }
1443
1444 spu_value_to_regcache (regcache, regnum, type, contents);
1445 regnum += n_regs;
1446 }
1447
1448 /* Overflow arguments go to the stack. */
1449 if (stack_arg != -1)
1450 {
1451 CORE_ADDR ap;
1452
1453 /* Allocate all required stack size. */
1454 for (i = stack_arg; i < nargs; i++)
1455 {
1456 struct type *type = check_typedef (value_type (args[i]));
1457 sp -= align_up (TYPE_LENGTH (type), 16);
1458 }
1459
1460 /* Fill in stack arguments. */
1461 ap = sp;
1462 for (i = stack_arg; i < nargs; i++)
1463 {
1464 struct value *arg = args[i];
1465 struct type *type = check_typedef (value_type (arg));
1466 int len = TYPE_LENGTH (type);
1467 int preferred_slot;
1468
1469 if (spu_scalar_value_p (type))
1470 preferred_slot = len < 4 ? 4 - len : 0;
1471 else
1472 preferred_slot = 0;
1473
1474 target_write_memory (ap + preferred_slot, value_contents (arg), len);
1475 ap += align_up (TYPE_LENGTH (type), 16);
1476 }
1477 }
1478
1479 /* Allocate stack frame header. */
1480 sp -= 32;
1481
ee82e879
UW		 1482 /* Store stack back chain. */
1483 regcache_cooked_read (regcache, SPU_RAW_SP_REGNUM, buf);
1484 target_write_memory (sp, buf, 16);
1485
9ff3afda 1486 /* Finally, update all slots of the SP register. */
e17a4113 1487 sp_delta = sp - extract_unsigned_integer (buf, 4, byte_order);
9ff3afda
UW		 1488 for (i = 0; i < 4; i++)
1489 {
e17a4113
UW		 1490 CORE_ADDR sp_slot = extract_unsigned_integer (buf + 4*i, 4, byte_order);
1491 store_unsigned_integer (buf + 4*i, 4, byte_order, sp_slot + sp_delta);
9ff3afda
UW		 1492 }
1493 regcache_cooked_write (regcache, SPU_RAW_SP_REGNUM, buf);
771b4502
UW		 1494
1495 return sp;
1496}
1497
1498static struct frame_id
8d998b8f 1499spu_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
771b4502 1500{
85e747d2 1501 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
8d998b8f
UW		 1502 CORE_ADDR pc = get_frame_register_unsigned (this_frame, SPU_PC_REGNUM);
1503 CORE_ADDR sp = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
85e747d2 1504 return frame_id_build (SPUADDR (tdep->id, sp), SPUADDR (tdep->id, pc & -4));
771b4502
UW		 1505}
1506
1507/* Function return value access. */
1508
1509static enum return_value_convention
6a3a010b 1510spu_return_value (struct gdbarch *gdbarch, struct value *function,
c055b101
CV		 1511 struct type *type, struct regcache *regcache,
1512 gdb_byte *out, const gdb_byte *in)
771b4502 1513{
6a3a010b 1514 struct type *func_type = function ? value_type (function) : NULL;
771b4502 1515 enum return_value_convention rvc;
54fcddd0
UW		 1516 int opencl_vector = 0;
1517
598cfb71
UW		 1518 if (func_type)
1519 {
1520 func_type = check_typedef (func_type);
1521
1522 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
1523 func_type = check_typedef (TYPE_TARGET_TYPE (func_type));
1524
1525 if (TYPE_CODE (func_type) == TYPE_CODE_FUNC
1526 && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GDB_IBM_OpenCL
1527 && TYPE_CODE (type) == TYPE_CODE_ARRAY
1528 && TYPE_VECTOR (type))
1529 opencl_vector = 1;
1530 }
771b4502
UW		 1531
1532 if (TYPE_LENGTH (type) <= (SPU_ARGN_REGNUM - SPU_ARG1_REGNUM + 1) * 16)
1533 rvc = RETURN_VALUE_REGISTER_CONVENTION;
1534 else
1535 rvc = RETURN_VALUE_STRUCT_CONVENTION;
1536
1537 if (in)
1538 {
1539 switch (rvc)
1540 {
1541 case RETURN_VALUE_REGISTER_CONVENTION:
54fcddd0
UW		 1542 if (opencl_vector && TYPE_LENGTH (type) == 2)
1543 regcache_cooked_write_part (regcache, SPU_ARG1_REGNUM, 2, 2, in);
1544 else
1545 spu_value_to_regcache (regcache, SPU_ARG1_REGNUM, type, in);
771b4502
UW		 1546 break;
1547
1548 case RETURN_VALUE_STRUCT_CONVENTION:
a73c6dcd 1549 error (_("Cannot set function return value."));
771b4502
UW		 1550 break;
1551 }
1552 }
1553 else if (out)
1554 {
1555 switch (rvc)
1556 {
1557 case RETURN_VALUE_REGISTER_CONVENTION:
54fcddd0
UW		 1558 if (opencl_vector && TYPE_LENGTH (type) == 2)
1559 regcache_cooked_read_part (regcache, SPU_ARG1_REGNUM, 2, 2, out);
1560 else
1561 spu_regcache_to_value (regcache, SPU_ARG1_REGNUM, type, out);
771b4502
UW		 1562 break;
1563
1564 case RETURN_VALUE_STRUCT_CONVENTION:
a73c6dcd 1565 error (_("Function return value unknown."));
771b4502
UW		 1566 break;
1567 }
1568 }
1569
1570 return rvc;
1571}
1572
1573
1574/* Breakpoints. */
04180708 1575constexpr gdb_byte spu_break_insn[] = { 0x00, 0x00, 0x3f, 0xff };
771b4502 1576
04180708 1577typedef BP_MANIPULATION (spu_break_insn) spu_breakpoint;
771b4502 1578
d03285ec
UW		 1579static int
1580spu_memory_remove_breakpoint (struct gdbarch *gdbarch,
1581 struct bp_target_info *bp_tgt)
1582{
1583 /* We work around a problem in combined Cell/B.E. debugging here. Consider
1584 that in a combined application, we have some breakpoints inserted in SPU
1585 code, and now the application forks (on the PPU side). GDB common code
1586 will assume that the fork system call copied all breakpoints into the new
1587 process' address space, and that all those copies now need to be removed
1588 (see breakpoint.c:detach_breakpoints).
1589
1590 While this is certainly true for PPU side breakpoints, it is not true
1591 for SPU side breakpoints. fork will clone the SPU context file
1592 descriptors, so that all the existing SPU contexts are in accessible
1593 in the new process. However, the contents of the SPU contexts themselves
1594 are *not* cloned. Therefore the effect of detach_breakpoints is to
1595 remove SPU breakpoints from the *original* SPU context's local store
1596 -- this is not the correct behaviour.
1597
1598 The workaround is to check whether the PID we are asked to remove this
1599 breakpoint from (i.e. ptid_get_pid (inferior_ptid)) is different from the
1600 PID of the current inferior (i.e. current_inferior ()->pid). This is only
1601 true in the context of detach_breakpoints. If so, we simply do nothing.
1602 [ Note that for the fork child process, it does not matter if breakpoints
1603 remain inserted, because those SPU contexts are not runnable anyway --
1604 the Linux kernel allows only the original process to invoke spu_run. */
1605
1606 if (ptid_get_pid (inferior_ptid) != current_inferior ()->pid)
1607 return 0;
1608
1609 return default_memory_remove_breakpoint (gdbarch, bp_tgt);
1610}
1611
771b4502
UW		 1612
1613/* Software single-stepping support. */
1614
a0ff9e1a 1615static std::vector<CORE_ADDR>
f5ea389a 1616spu_software_single_step (struct regcache *regcache)
771b4502 1617{
b2260160 1618 struct gdbarch *gdbarch = get_regcache_arch (regcache);
e17a4113 1619 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e0cd558a
UW		 1620 CORE_ADDR pc, next_pc;
1621 unsigned int insn;
1622 int offset, reg;
1623 gdb_byte buf[4];
13def385 1624 ULONGEST lslr;
a0ff9e1a 1625 std::vector<CORE_ADDR> next_pcs;
771b4502 1626
b2260160 1627 pc = regcache_read_pc (regcache);
771b4502 1628
e0cd558a 1629 if (target_read_memory (pc, buf, 4))
941319d1
YQ		 1630 throw_error (MEMORY_ERROR, _("Could not read instruction at %s."),
1631 paddress (gdbarch, pc));
1632
e17a4113 1633 insn = extract_unsigned_integer (buf, 4, byte_order);
771b4502 1634
13def385 1635 /* Get local store limit. */
b2260160 1636 lslr = regcache_raw_get_unsigned (regcache, SPU_LSLR_REGNUM);
13def385
UW		 1637 if (!lslr)
1638 lslr = (ULONGEST) -1;
1639
e0cd558a
UW		 1640 /* Next sequential instruction is at PC + 4, except if the current
1641 instruction is a PPE-assisted call, in which case it is at PC + 8.
1642 Wrap around LS limit to be on the safe side. */
1643 if ((insn & 0xffffff00) == 0x00002100)
13def385 1644 next_pc = (SPUADDR_ADDR (pc) + 8) & lslr;
e0cd558a 1645 else
13def385 1646 next_pc = (SPUADDR_ADDR (pc) + 4) & lslr;
771b4502 1647
a0ff9e1a 1648 next_pcs.push_back (SPUADDR (SPUADDR_SPU (pc), next_pc));
771b4502 1649
e0cd558a
UW		 1650 if (is_branch (insn, &offset, &reg))
1651 {
1652 CORE_ADDR target = offset;
771b4502 1653
e0cd558a 1654 if (reg == SPU_PC_REGNUM)
85e747d2 1655 target += SPUADDR_ADDR (pc);
e0cd558a 1656 else if (reg != -1)
b2260160 1657 target += regcache_raw_get_unsigned (regcache, reg) & -4;
e0cd558a 1658
13def385 1659 target = target & lslr;
e0cd558a 1660 if (target != next_pc)
a0ff9e1a 1661 next_pcs.push_back (SPUADDR (SPUADDR_SPU (pc), target));
771b4502 1662 }
e6590a1b 1663
93f9a11f 1664 return next_pcs;
771b4502
UW		 1665}
1666
6e3f70d7
UW		 1667
1668/* Longjmp support. */
1669
1670static int
1671spu_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1672{
e17a4113 1673 struct gdbarch *gdbarch = get_frame_arch (frame);
85e747d2 1674 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 1675 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6e3f70d7
UW		 1676 gdb_byte buf[4];
1677 CORE_ADDR jb_addr;
8dccd430 1678 int optim, unavail;
6e3f70d7
UW		 1679
1680 /* Jump buffer is pointed to by the argument register $r3. */
8dccd430
PA		 1681 if (!get_frame_register_bytes (frame, SPU_ARG1_REGNUM, 0, 4, buf,
1682 &optim, &unavail))
1683 return 0;
1684
e17a4113 1685 jb_addr = extract_unsigned_integer (buf, 4, byte_order);
85e747d2 1686 if (target_read_memory (SPUADDR (tdep->id, jb_addr), buf, 4))
6e3f70d7
UW		 1687 return 0;
1688
e17a4113 1689 *pc = extract_unsigned_integer (buf, 4, byte_order);
85e747d2 1690 *pc = SPUADDR (tdep->id, *pc);
6e3f70d7
UW		 1691 return 1;
1692}
1693
1694
85e747d2
UW		 1695/* Disassembler. */
1696
e47ad6c0 1697struct spu_dis_asm_info : disassemble_info
85e747d2 1698{
85e747d2
UW		 1699 int id;
1700};
1701
1702static void
1703spu_dis_asm_print_address (bfd_vma addr, struct disassemble_info *info)
1704{
e47ad6c0
YQ		 1705 struct spu_dis_asm_info *data = (struct spu_dis_asm_info *) info;
1706 gdb_disassembler *di
1707 = static_cast<gdb_disassembler *>(info->application_data);
1708
1709 print_address (di->arch (), SPUADDR (data->id, addr),
19ba03f4 1710 (struct ui_file *) info->stream);
85e747d2
UW		 1711}
1712
1713static int
1714gdb_print_insn_spu (bfd_vma memaddr, struct disassemble_info *info)
1715{
c378eb4e
MS		 1716 /* The opcodes disassembler does 18-bit address arithmetic. Make
1717 sure the SPU ID encoded in the high bits is added back when we
1718 call print_address. */
e47ad6c0 1719 struct spu_dis_asm_info spu_info;
85e747d2 1720
e47ad6c0
YQ		 1721 memcpy (&spu_info, info, sizeof (*info));
1722 spu_info.id = SPUADDR_SPU (memaddr);
85e747d2 1723 spu_info.print_address_func = spu_dis_asm_print_address;
6394c606 1724 return default_print_insn (memaddr, &spu_info);
85e747d2
UW		 1725}
1726
1727
dcf52cd8
UW		 1728/* Target overlays for the SPU overlay manager.
1729
1730 See the documentation of simple_overlay_update for how the
1731 interface is supposed to work.
1732
1733 Data structures used by the overlay manager:
1734
1735 struct ovly_table
1736 {
1737 u32 vma;
1738 u32 size;
1739 u32 pos;
1740 u32 buf;
1741 } _ovly_table[]; -- one entry per overlay section
1742
1743 struct ovly_buf_table
1744 {
1745 u32 mapped;
1746 } _ovly_buf_table[]; -- one entry per overlay buffer
1747
1748 _ovly_table should never change.
1749
c378eb4e
MS		 1750 Both tables are aligned to a 16-byte boundary, the symbols
1751 _ovly_table and _ovly_buf_table are of type STT_OBJECT and their
1752 size set to the size of the respective array. buf in _ovly_table is
1753 an index into _ovly_buf_table.
dcf52cd8 1754
c378eb4e 1755 mapped is an index into _ovly_table. Both the mapped and buf indices start
dcf52cd8
UW		 1756 from one to reference the first entry in their respective tables. */
1757
1758/* Using the per-objfile private data mechanism, we store for each
1759 objfile an array of "struct spu_overlay_table" structures, one
1760 for each obj_section of the objfile. This structure holds two
1761 fields, MAPPED_PTR and MAPPED_VAL. If MAPPED_PTR is zero, this
1762 is *not* an overlay section. If it is non-zero, it represents
1763 a target address. The overlay section is mapped iff the target
1764 integer at this location equals MAPPED_VAL. */
1765
1766static const struct objfile_data *spu_overlay_data;
1767
1768struct spu_overlay_table
1769 {
1770 CORE_ADDR mapped_ptr;
1771 CORE_ADDR mapped_val;
1772 };
1773
1774/* Retrieve the overlay table for OBJFILE. If not already cached, read
1775 the _ovly_table data structure from the target and initialize the
1776 spu_overlay_table data structure from it. */
1777static struct spu_overlay_table *
1778spu_get_overlay_table (struct objfile *objfile)
1779{
e17a4113
UW		 1780 enum bfd_endian byte_order = bfd_big_endian (objfile->obfd)?
1781 BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
3b7344d5 1782 struct bound_minimal_symbol ovly_table_msym, ovly_buf_table_msym;
dcf52cd8
UW		 1783 CORE_ADDR ovly_table_base, ovly_buf_table_base;
1784 unsigned ovly_table_size, ovly_buf_table_size;
1785 struct spu_overlay_table *tbl;
1786 struct obj_section *osect;
948f8e3d 1787 gdb_byte *ovly_table;
dcf52cd8
UW		 1788 int i;
1789
19ba03f4 1790 tbl = (struct spu_overlay_table *) objfile_data (objfile, spu_overlay_data);
dcf52cd8
UW		 1791 if (tbl)
1792 return tbl;
1793
1794 ovly_table_msym = lookup_minimal_symbol ("_ovly_table", NULL, objfile);
3b7344d5 1795 if (!ovly_table_msym.minsym)
dcf52cd8
UW		 1796 return NULL;
1797
c378eb4e
MS		 1798 ovly_buf_table_msym = lookup_minimal_symbol ("_ovly_buf_table",
1799 NULL, objfile);
3b7344d5 1800 if (!ovly_buf_table_msym.minsym)
dcf52cd8
UW		 1801 return NULL;
1802
77e371c0 1803 ovly_table_base = BMSYMBOL_VALUE_ADDRESS (ovly_table_msym);
3b7344d5 1804 ovly_table_size = MSYMBOL_SIZE (ovly_table_msym.minsym);
dcf52cd8 1805
77e371c0 1806 ovly_buf_table_base = BMSYMBOL_VALUE_ADDRESS (ovly_buf_table_msym);
3b7344d5 1807 ovly_buf_table_size = MSYMBOL_SIZE (ovly_buf_table_msym.minsym);
dcf52cd8 1808
224c3ddb 1809 ovly_table = (gdb_byte *) xmalloc (ovly_table_size);
dcf52cd8
UW		 1810 read_memory (ovly_table_base, ovly_table, ovly_table_size);
1811
1812 tbl = OBSTACK_CALLOC (&objfile->objfile_obstack,
1813 objfile->sections_end - objfile->sections,
1814 struct spu_overlay_table);
1815
1816 for (i = 0; i < ovly_table_size / 16; i++)
1817 {
e17a4113
UW		 1818 CORE_ADDR vma = extract_unsigned_integer (ovly_table + 16*i + 0,
1819 4, byte_order);
1820 CORE_ADDR size = extract_unsigned_integer (ovly_table + 16*i + 4,
1821 4, byte_order);
1822 CORE_ADDR pos = extract_unsigned_integer (ovly_table + 16*i + 8,
1823 4, byte_order);
1824 CORE_ADDR buf = extract_unsigned_integer (ovly_table + 16*i + 12,
1825 4, byte_order);
dcf52cd8
UW		 1826
1827 if (buf == 0 || (buf - 1) * 4 >= ovly_buf_table_size)
1828 continue;
1829
1830 ALL_OBJFILE_OSECTIONS (objfile, osect)
1831 if (vma == bfd_section_vma (objfile->obfd, osect->the_bfd_section)
1832 && pos == osect->the_bfd_section->filepos)
1833 {
1834 int ndx = osect - objfile->sections;
1835 tbl[ndx].mapped_ptr = ovly_buf_table_base + (buf - 1) * 4;
1836 tbl[ndx].mapped_val = i + 1;
1837 break;
1838 }
1839 }
1840
1841 xfree (ovly_table);
1842 set_objfile_data (objfile, spu_overlay_data, tbl);
1843 return tbl;
1844}
1845
1846/* Read _ovly_buf_table entry from the target to dermine whether
1847 OSECT is currently mapped, and update the mapped state. */
1848static void
1849spu_overlay_update_osect (struct obj_section *osect)
1850{
e17a4113
UW		 1851 enum bfd_endian byte_order = bfd_big_endian (osect->objfile->obfd)?
1852 BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
dcf52cd8 1853 struct spu_overlay_table *ovly_table;
85e747d2 1854 CORE_ADDR id, val;
dcf52cd8
UW		 1855
1856 ovly_table = spu_get_overlay_table (osect->objfile);
1857 if (!ovly_table)
1858 return;
1859
1860 ovly_table += osect - osect->objfile->sections;
1861 if (ovly_table->mapped_ptr == 0)
1862 return;
1863
85e747d2
UW		 1864 id = SPUADDR_SPU (obj_section_addr (osect));
1865 val = read_memory_unsigned_integer (SPUADDR (id, ovly_table->mapped_ptr),
1866 4, byte_order);
dcf52cd8
UW		 1867 osect->ovly_mapped = (val == ovly_table->mapped_val);
1868}
1869
1870/* If OSECT is NULL, then update all sections' mapped state.
1871 If OSECT is non-NULL, then update only OSECT's mapped state. */
1872static void
1873spu_overlay_update (struct obj_section *osect)
1874{
1875 /* Just one section. */
1876 if (osect)
1877 spu_overlay_update_osect (osect);
1878
1879 /* All sections. */
1880 else
1881 {
1882 struct objfile *objfile;
1883
1884 ALL_OBJSECTIONS (objfile, osect)
714835d5 1885 if (section_is_overlay (osect))
dcf52cd8
UW		 1886 spu_overlay_update_osect (osect);
1887 }
1888}
1889
1890/* Whenever a new objfile is loaded, read the target's _ovly_table.
1891 If there is one, go through all sections and make sure for non-
1892 overlay sections LMA equals VMA, while for overlay sections LMA
d2ed6730 1893 is larger than SPU_OVERLAY_LMA. */
dcf52cd8
UW		 1894static void
1895spu_overlay_new_objfile (struct objfile *objfile)
1896{
1897 struct spu_overlay_table *ovly_table;
1898 struct obj_section *osect;
1899
1900 /* If we've already touched this file, do nothing. */
1901 if (!objfile || objfile_data (objfile, spu_overlay_data) != NULL)
1902 return;
1903
0391f248
UW		 1904 /* Consider only SPU objfiles. */
1905 if (bfd_get_arch (objfile->obfd) != bfd_arch_spu)
1906 return;
1907
dcf52cd8
UW		 1908 /* Check if this objfile has overlays. */
1909 ovly_table = spu_get_overlay_table (objfile);
1910 if (!ovly_table)
1911 return;
1912
1913 /* Now go and fiddle with all the LMAs. */
1914 ALL_OBJFILE_OSECTIONS (objfile, osect)
1915 {
1916 bfd *obfd = objfile->obfd;
1917 asection *bsect = osect->the_bfd_section;
1918 int ndx = osect - objfile->sections;
1919
1920 if (ovly_table[ndx].mapped_ptr == 0)
1921 bfd_section_lma (obfd, bsect) = bfd_section_vma (obfd, bsect);
1922 else
d2ed6730 1923 bfd_section_lma (obfd, bsect) = SPU_OVERLAY_LMA + bsect->filepos;
dcf52cd8
UW		 1924 }
1925}
1926
771b4502 1927
3285f3fe
UW		 1928/* Insert temporary breakpoint on "main" function of newly loaded
1929 SPE context OBJFILE. */
1930static void
1931spu_catch_start (struct objfile *objfile)
1932{
3b7344d5 1933 struct bound_minimal_symbol minsym;
43f3e411 1934 struct compunit_symtab *cust;
3285f3fe 1935 CORE_ADDR pc;
3285f3fe
UW		 1936
1937 /* Do this only if requested by "set spu stop-on-load on". */
1938 if (!spu_stop_on_load_p)
1939 return;
1940
1941 /* Consider only SPU objfiles. */
1942 if (!objfile || bfd_get_arch (objfile->obfd) != bfd_arch_spu)
1943 return;
1944
1945 /* The main objfile is handled differently. */
1946 if (objfile == symfile_objfile)
1947 return;
1948
1949 /* There can be multiple symbols named "main". Search for the
1950 "main" in *this* objfile. */
1951 minsym = lookup_minimal_symbol ("main", NULL, objfile);
3b7344d5 1952 if (!minsym.minsym)
3285f3fe
UW		 1953 return;
1954
1955 /* If we have debugging information, try to use it -- this
1956 will allow us to properly skip the prologue. */
77e371c0 1957 pc = BMSYMBOL_VALUE_ADDRESS (minsym);
43f3e411
DE		 1958 cust
1959 = find_pc_sect_compunit_symtab (pc, MSYMBOL_OBJ_SECTION (minsym.objfile,
1960 minsym.minsym));
1961 if (cust != NULL)
3285f3fe 1962 {
43f3e411 1963 const struct blockvector *bv = COMPUNIT_BLOCKVECTOR (cust);
3285f3fe
UW		 1964 struct block *block = BLOCKVECTOR_BLOCK (bv, GLOBAL_BLOCK);
1965 struct symbol *sym;
1966 struct symtab_and_line sal;
1967
16b2eaa1 1968 sym = block_lookup_symbol (block, "main", VAR_DOMAIN);
3285f3fe
UW		 1969 if (sym)
1970 {
1971 fixup_symbol_section (sym, objfile);
1972 sal = find_function_start_sal (sym, 1);
1973 pc = sal.pc;
1974 }
1975 }
1976
1977 /* Use a numerical address for the set_breakpoint command to avoid having
1978 the breakpoint re-set incorrectly. */
ffc2605c
TT		 1979 event_location_up location = new_address_location (pc, NULL, 0);
1980 create_breakpoint (get_objfile_arch (objfile), location.get (),
d8c09fb5 1981 NULL /* cond_string */, -1 /* thread */,
6a609e58 1982 NULL /* extra_string */,
d8c09fb5 1983 0 /* parse_condition_and_thread */, 1 /* tempflag */,
bddaafad 1984 bp_breakpoint /* type_wanted */,
d8c09fb5
JK		 1985 0 /* ignore_count */,
1986 AUTO_BOOLEAN_FALSE /* pending_break_support */,
931bb47f 1987 &bkpt_breakpoint_ops /* ops */, 0 /* from_tty */,
44f238bb 1988 1 /* enabled */, 0 /* internal */, 0);
3285f3fe
UW		 1989}
1990
1991
ff1a52c6
UW		 1992/* Look up OBJFILE loaded into FRAME's SPU context. */
1993static struct objfile *
1994spu_objfile_from_frame (struct frame_info *frame)
1995{
1996 struct gdbarch *gdbarch = get_frame_arch (frame);
1997 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1998 struct objfile *obj;
1999
2000 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
2001 return NULL;
2002
2003 ALL_OBJFILES (obj)
2004 {
2005 if (obj->sections != obj->sections_end
2006 && SPUADDR_SPU (obj_section_addr (obj->sections)) == tdep->id)
2007 return obj;
2008 }
2009
2010 return NULL;
2011}
2012
2013/* Flush cache for ea pointer access if available. */
2014static void
2015flush_ea_cache (void)
2016{
3b7344d5 2017 struct bound_minimal_symbol msymbol;
ff1a52c6
UW		 2018 struct objfile *obj;
2019
2020 if (!has_stack_frames ())
2021 return;
2022
2023 obj = spu_objfile_from_frame (get_current_frame ());
2024 if (obj == NULL)
2025 return;
2026
2027 /* Lookup inferior function __cache_flush. */
2028 msymbol = lookup_minimal_symbol ("__cache_flush", NULL, obj);
3b7344d5 2029 if (msymbol.minsym != NULL)
ff1a52c6
UW		 2030 {
2031 struct type *type;
2032 CORE_ADDR addr;
2033
2034 type = objfile_type (obj)->builtin_void;
2035 type = lookup_function_type (type);
2036 type = lookup_pointer_type (type);
77e371c0 2037 addr = BMSYMBOL_VALUE_ADDRESS (msymbol);
ff1a52c6 2038
5b9f8a7c 2039 call_function_by_hand (value_from_pointer (type, addr), NULL, 0, NULL);
ff1a52c6
UW		 2040 }
2041}
2042
2043/* This handler is called when the inferior has stopped. If it is stopped in
2044 SPU architecture then flush the ea cache if used. */
2045static void
2046spu_attach_normal_stop (struct bpstats *bs, int print_frame)
2047{
2048 if (!spu_auto_flush_cache_p)
2049 return;
2050
2051 /* Temporarily reset spu_auto_flush_cache_p to avoid recursively
2052 re-entering this function when __cache_flush stops. */
2053 spu_auto_flush_cache_p = 0;
2054 flush_ea_cache ();
2055 spu_auto_flush_cache_p = 1;
2056}
2057
2058
23d964e7
UW		 2059/* "info spu" commands. */
2060
2061static void
2062info_spu_event_command (char *args, int from_tty)
2063{
2064 struct frame_info *frame = get_selected_frame (NULL);
2065 ULONGEST event_status = 0;
2066 ULONGEST event_mask = 0;
23d964e7
UW		 2067 gdb_byte buf[100];
2068 char annex[32];
2069 LONGEST len;
22e048c9 2070 int id;
23d964e7 2071
0391f248
UW		 2072 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
2073 error (_("\"info spu\" is only supported on the SPU architecture."));
2074
23d964e7
UW		 2075 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2076
2077 xsnprintf (annex, sizeof annex, "%d/event_status", id);
2078 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2079 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2080 if (len <= 0)
2081 error (_("Could not read event_status."));
9971ac47 2082 buf[len] = '\0';
001f13d8 2083 event_status = strtoulst ((char *) buf, NULL, 16);
23d964e7
UW		 2084
2085 xsnprintf (annex, sizeof annex, "%d/event_mask", id);
2086 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2087 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2088 if (len <= 0)
2089 error (_("Could not read event_mask."));
9971ac47 2090 buf[len] = '\0';
001f13d8 2091 event_mask = strtoulst ((char *) buf, NULL, 16);
23d964e7 2092
76f9c9cf 2093 ui_out_emit_tuple tuple_emitter (current_uiout, "SPUInfoEvent");
23d964e7 2094
112e8700 2095 if (current_uiout->is_mi_like_p ())
23d964e7 2096 {
112e8700
SM		 2097 current_uiout->field_fmt ("event_status",
2098 "0x%s", phex_nz (event_status, 4));
2099 current_uiout->field_fmt ("event_mask",
2100 "0x%s", phex_nz (event_mask, 4));
23d964e7
UW		 2101 }
2102 else
2103 {
2104 printf_filtered (_("Event Status 0x%s\n"), phex (event_status, 4));
2105 printf_filtered (_("Event Mask 0x%s\n"), phex (event_mask, 4));
2106 }
23d964e7
UW		 2107}
2108
2109static void
2110info_spu_signal_command (char *args, int from_tty)
2111{
2112 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2113 struct gdbarch *gdbarch = get_frame_arch (frame);
2114 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2115 ULONGEST signal1 = 0;
2116 ULONGEST signal1_type = 0;
2117 int signal1_pending = 0;
2118 ULONGEST signal2 = 0;
2119 ULONGEST signal2_type = 0;
2120 int signal2_pending = 0;
23d964e7
UW		 2121 char annex[32];
2122 gdb_byte buf[100];
2123 LONGEST len;
22e048c9 2124 int id;
23d964e7 2125
e17a4113 2126 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
0391f248
UW		 2127 error (_("\"info spu\" is only supported on the SPU architecture."));
2128
23d964e7
UW		 2129 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2130
2131 xsnprintf (annex, sizeof annex, "%d/signal1", id);
2132 len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
2133 if (len < 0)
2134 error (_("Could not read signal1."));
2135 else if (len == 4)
2136 {
e17a4113 2137 signal1 = extract_unsigned_integer (buf, 4, byte_order);
23d964e7
UW		 2138 signal1_pending = 1;
2139 }
2140
2141 xsnprintf (annex, sizeof annex, "%d/signal1_type", id);
2142 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2143 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2144 if (len <= 0)
2145 error (_("Could not read signal1_type."));
9971ac47 2146 buf[len] = '\0';
001f13d8 2147 signal1_type = strtoulst ((char *) buf, NULL, 16);
23d964e7
UW		 2148
2149 xsnprintf (annex, sizeof annex, "%d/signal2", id);
2150 len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
2151 if (len < 0)
2152 error (_("Could not read signal2."));
2153 else if (len == 4)
2154 {
e17a4113 2155 signal2 = extract_unsigned_integer (buf, 4, byte_order);
23d964e7
UW		 2156 signal2_pending = 1;
2157 }
2158
2159 xsnprintf (annex, sizeof annex, "%d/signal2_type", id);
2160 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
9971ac47 2161 buf, 0, (sizeof (buf) - 1));
23d964e7
UW		 2162 if (len <= 0)
2163 error (_("Could not read signal2_type."));
9971ac47 2164 buf[len] = '\0';
001f13d8 2165 signal2_type = strtoulst ((char *) buf, NULL, 16);
23d964e7 2166
76f9c9cf 2167 ui_out_emit_tuple tuple_emitter (current_uiout, "SPUInfoSignal");
23d964e7 2168
112e8700 2169 if (current_uiout->is_mi_like_p ())
23d964e7 2170 {
112e8700
SM		 2171 current_uiout->field_int ("signal1_pending", signal1_pending);
2172 current_uiout->field_fmt ("signal1", "0x%s", phex_nz (signal1, 4));
2173 current_uiout->field_int ("signal1_type", signal1_type);
2174 current_uiout->field_int ("signal2_pending", signal2_pending);
2175 current_uiout->field_fmt ("signal2", "0x%s", phex_nz (signal2, 4));
2176 current_uiout->field_int ("signal2_type", signal2_type);
23d964e7
UW		 2177 }
2178 else
2179 {
2180 if (signal1_pending)
2181 printf_filtered (_("Signal 1 control word 0x%s "), phex (signal1, 4));
2182 else
2183 printf_filtered (_("Signal 1 not pending "));
2184
2185 if (signal1_type)
23d964e7 2186 printf_filtered (_("(Type Or)\n"));
b94c4f7d
UW		 2187 else
2188 printf_filtered (_("(Type Overwrite)\n"));
23d964e7
UW		 2189
2190 if (signal2_pending)
2191 printf_filtered (_("Signal 2 control word 0x%s "), phex (signal2, 4));
2192 else
2193 printf_filtered (_("Signal 2 not pending "));
2194
2195 if (signal2_type)
23d964e7 2196 printf_filtered (_("(Type Or)\n"));
b94c4f7d
UW		 2197 else
2198 printf_filtered (_("(Type Overwrite)\n"));
23d964e7 2199 }
23d964e7
UW		 2200}
2201
2202static void
e17a4113 2203info_spu_mailbox_list (gdb_byte *buf, int nr, enum bfd_endian byte_order,
23d964e7
UW		 2204 const char *field, const char *msg)
2205{
23d964e7
UW		 2206 int i;
2207
2208 if (nr <= 0)
2209 return;
2210
dc9fe180 2211 ui_out_emit_table table_emitter (current_uiout, 1, nr, "mbox");
23d964e7 2212
112e8700
SM		 2213 current_uiout->table_header (32, ui_left, field, msg);
2214 current_uiout->table_body ();
23d964e7
UW		 2215
2216 for (i = 0; i < nr; i++)
2217 {
dc9fe180
TT		 2218 {
2219 ULONGEST val;
2220 ui_out_emit_tuple tuple_emitter (current_uiout, "mbox");
2221 val = extract_unsigned_integer (buf + 4*i, 4, byte_order);
2222 current_uiout->field_fmt (field, "0x%s", phex (val, 4));
2223 }
23d964e7 2224
112e8700 2225 if (!current_uiout->is_mi_like_p ())
23d964e7
UW		 2226 printf_filtered ("\n");
2227 }
23d964e7
UW		 2228}
2229
2230static void
2231info_spu_mailbox_command (char *args, int from_tty)
2232{
2233 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2234 struct gdbarch *gdbarch = get_frame_arch (frame);
2235 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2236 char annex[32];
2237 gdb_byte buf[1024];
2238 LONGEST len;
22e048c9 2239 int id;
23d964e7 2240
e17a4113 2241 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
0391f248
UW		 2242 error (_("\"info spu\" is only supported on the SPU architecture."));
2243
23d964e7
UW		 2244 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2245
76f9c9cf 2246 ui_out_emit_tuple tuple_emitter (current_uiout, "SPUInfoMailbox");
23d964e7
UW		 2247
2248 xsnprintf (annex, sizeof annex, "%d/mbox_info", id);
2249 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2250 buf, 0, sizeof buf);
2251 if (len < 0)
2252 error (_("Could not read mbox_info."));
2253
e17a4113
UW		 2254 info_spu_mailbox_list (buf, len / 4, byte_order,
2255 "mbox", "SPU Outbound Mailbox");
23d964e7
UW		 2256
2257 xsnprintf (annex, sizeof annex, "%d/ibox_info", id);
2258 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2259 buf, 0, sizeof buf);
2260 if (len < 0)
2261 error (_("Could not read ibox_info."));
2262
e17a4113
UW		 2263 info_spu_mailbox_list (buf, len / 4, byte_order,
2264 "ibox", "SPU Outbound Interrupt Mailbox");
23d964e7
UW		 2265
2266 xsnprintf (annex, sizeof annex, "%d/wbox_info", id);
2267 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2268 buf, 0, sizeof buf);
2269 if (len < 0)
2270 error (_("Could not read wbox_info."));
2271
e17a4113
UW		 2272 info_spu_mailbox_list (buf, len / 4, byte_order,
2273 "wbox", "SPU Inbound Mailbox");
23d964e7
UW		 2274}
2275
2276static ULONGEST
2277spu_mfc_get_bitfield (ULONGEST word, int first, int last)
2278{
2279 ULONGEST mask = ~(~(ULONGEST)0 << (last - first + 1));
2280 return (word >> (63 - last)) & mask;
2281}
2282
2283static void
e17a4113 2284info_spu_dma_cmdlist (gdb_byte *buf, int nr, enum bfd_endian byte_order)
23d964e7 2285{
a121b7c1 2286 static const char *spu_mfc_opcode[256] =
23d964e7
UW		 2287 {
2288 /* 00 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2289 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2290 /* 10 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2291 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2292 /* 20 */ "put", "putb", "putf", NULL, "putl", "putlb", "putlf", NULL,
2293 "puts", "putbs", "putfs", NULL, NULL, NULL, NULL, NULL,
2294 /* 30 */ "putr", "putrb", "putrf", NULL, "putrl", "putrlb", "putrlf", NULL,
2295 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2296 /* 40 */ "get", "getb", "getf", NULL, "getl", "getlb", "getlf", NULL,
2297 "gets", "getbs", "getfs", NULL, NULL, NULL, NULL, NULL,
2298 /* 50 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2299 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2300 /* 60 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2301 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2302 /* 70 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2303 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2304 /* 80 */ "sdcrt", "sdcrtst", NULL, NULL, NULL, NULL, NULL, NULL,
2305 NULL, "sdcrz", NULL, NULL, NULL, "sdcrst", NULL, "sdcrf",
2306 /* 90 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2307 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2308 /* a0 */ "sndsig", "sndsigb", "sndsigf", NULL, NULL, NULL, NULL, NULL,
2309 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2310 /* b0 */ "putlluc", NULL, NULL, NULL, "putllc", NULL, NULL, NULL,
2311 "putqlluc", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2312 /* c0 */ "barrier", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2313 "mfceieio", NULL, NULL, NULL, "mfcsync", NULL, NULL, NULL,
2314 /* d0 */ "getllar", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2315 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2316 /* e0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2317 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2318 /* f0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2319 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2320 };
2321
8d749320 2322 int *seq = XALLOCAVEC (int, nr);
12ab8a60 2323 int done = 0;
12ab8a60
UW		 2324 int i, j;
2325
2326
2327 /* Determine sequence in which to display (valid) entries. */
2328 for (i = 0; i < nr; i++)
2329 {
2330 /* Search for the first valid entry all of whose
2331 dependencies are met. */
2332 for (j = 0; j < nr; j++)
2333 {
2334 ULONGEST mfc_cq_dw3;
2335 ULONGEST dependencies;
2336
2337 if (done & (1 << (nr - 1 - j)))
2338 continue;
2339
e17a4113
UW		 2340 mfc_cq_dw3
2341 = extract_unsigned_integer (buf + 32*j + 24,8, byte_order);
12ab8a60
UW		 2342 if (!spu_mfc_get_bitfield (mfc_cq_dw3, 16, 16))
2343 continue;
2344
2345 dependencies = spu_mfc_get_bitfield (mfc_cq_dw3, 0, nr - 1);
2346 if ((dependencies & done) != dependencies)
2347 continue;
2348
2349 seq[i] = j;
2350 done |= 1 << (nr - 1 - j);
2351 break;
2352 }
2353
2354 if (j == nr)
2355 break;
2356 }
2357
2358 nr = i;
2359
23d964e7 2360
dc9fe180 2361 ui_out_emit_table table_emitter (current_uiout, 10, nr, "dma_cmd");
23d964e7 2362
112e8700
SM		 2363 current_uiout->table_header (7, ui_left, "opcode", "Opcode");
2364 current_uiout->table_header (3, ui_left, "tag", "Tag");
2365 current_uiout->table_header (3, ui_left, "tid", "TId");
2366 current_uiout->table_header (3, ui_left, "rid", "RId");
2367 current_uiout->table_header (18, ui_left, "ea", "EA");
2368 current_uiout->table_header (7, ui_left, "lsa", "LSA");
2369 current_uiout->table_header (7, ui_left, "size", "Size");
2370 current_uiout->table_header (7, ui_left, "lstaddr", "LstAddr");
2371 current_uiout->table_header (7, ui_left, "lstsize", "LstSize");
2372 current_uiout->table_header (1, ui_left, "error_p", "E");
23d964e7 2373
112e8700 2374 current_uiout->table_body ();
23d964e7
UW		 2375
2376 for (i = 0; i < nr; i++)
2377 {
23d964e7
UW		 2378 ULONGEST mfc_cq_dw0;
2379 ULONGEST mfc_cq_dw1;
2380 ULONGEST mfc_cq_dw2;
23d964e7 2381 int mfc_cmd_opcode, mfc_cmd_tag, rclass_id, tclass_id;
22e048c9 2382 int list_lsa, list_size, mfc_lsa, mfc_size;
23d964e7 2383 ULONGEST mfc_ea;
870f88f7 2384 int list_valid_p, qw_valid_p, ea_valid_p, cmd_error_p;
23d964e7
UW		 2385
2386 /* Decode contents of MFC Command Queue Context Save/Restore Registers.
2387 See "Cell Broadband Engine Registers V1.3", section 3.3.2.1. */
2388
e17a4113
UW		 2389 mfc_cq_dw0
2390 = extract_unsigned_integer (buf + 32*seq[i], 8, byte_order);
2391 mfc_cq_dw1
2392 = extract_unsigned_integer (buf + 32*seq[i] + 8, 8, byte_order);
2393 mfc_cq_dw2
2394 = extract_unsigned_integer (buf + 32*seq[i] + 16, 8, byte_order);
23d964e7
UW		 2395
2396 list_lsa = spu_mfc_get_bitfield (mfc_cq_dw0, 0, 14);
2397 list_size = spu_mfc_get_bitfield (mfc_cq_dw0, 15, 26);
2398 mfc_cmd_opcode = spu_mfc_get_bitfield (mfc_cq_dw0, 27, 34);
2399 mfc_cmd_tag = spu_mfc_get_bitfield (mfc_cq_dw0, 35, 39);
2400 list_valid_p = spu_mfc_get_bitfield (mfc_cq_dw0, 40, 40);
2401 rclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 41, 43);
2402 tclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 44, 46);
2403
2404 mfc_ea = spu_mfc_get_bitfield (mfc_cq_dw1, 0, 51) << 12
2405 | spu_mfc_get_bitfield (mfc_cq_dw2, 25, 36);
2406
2407 mfc_lsa = spu_mfc_get_bitfield (mfc_cq_dw2, 0, 13);
2408 mfc_size = spu_mfc_get_bitfield (mfc_cq_dw2, 14, 24);
23d964e7
UW		 2409 qw_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 38, 38);
2410 ea_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 39, 39);
2411 cmd_error_p = spu_mfc_get_bitfield (mfc_cq_dw2, 40, 40);
2412
dc9fe180
TT		 2413 {
2414 ui_out_emit_tuple tuple_emitter (current_uiout, "cmd");
23d964e7 2415
dc9fe180
TT		 2416 if (spu_mfc_opcode[mfc_cmd_opcode])
2417 current_uiout->field_string ("opcode", spu_mfc_opcode[mfc_cmd_opcode]);
2418 else
2419 current_uiout->field_int ("opcode", mfc_cmd_opcode);
23d964e7 2420
dc9fe180
TT		 2421 current_uiout->field_int ("tag", mfc_cmd_tag);
2422 current_uiout->field_int ("tid", tclass_id);
2423 current_uiout->field_int ("rid", rclass_id);
23d964e7 2424
dc9fe180
TT		 2425 if (ea_valid_p)
2426 current_uiout->field_fmt ("ea", "0x%s", phex (mfc_ea, 8));
2427 else
2428 current_uiout->field_skip ("ea");
23d964e7 2429
dc9fe180
TT		 2430 current_uiout->field_fmt ("lsa", "0x%05x", mfc_lsa << 4);
2431 if (qw_valid_p)
2432 current_uiout->field_fmt ("size", "0x%05x", mfc_size << 4);
2433 else
2434 current_uiout->field_fmt ("size", "0x%05x", mfc_size);
23d964e7 2435
dc9fe180
TT		 2436 if (list_valid_p)
2437 {
2438 current_uiout->field_fmt ("lstaddr", "0x%05x", list_lsa << 3);
2439 current_uiout->field_fmt ("lstsize", "0x%05x", list_size << 3);
2440 }
2441 else
2442 {
2443 current_uiout->field_skip ("lstaddr");
2444 current_uiout->field_skip ("lstsize");
2445 }
23d964e7 2446
dc9fe180
TT		 2447 if (cmd_error_p)
2448 current_uiout->field_string ("error_p", "*");
2449 else
2450 current_uiout->field_skip ("error_p");
2451 }
23d964e7 2452
112e8700 2453 if (!current_uiout->is_mi_like_p ())
23d964e7
UW		 2454 printf_filtered ("\n");
2455 }
23d964e7
UW		 2456}
2457
2458static void
2459info_spu_dma_command (char *args, int from_tty)
2460{
2461 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2462 struct gdbarch *gdbarch = get_frame_arch (frame);
2463 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2464 ULONGEST dma_info_type;
2465 ULONGEST dma_info_mask;
2466 ULONGEST dma_info_status;
2467 ULONGEST dma_info_stall_and_notify;
2468 ULONGEST dma_info_atomic_command_status;
23d964e7
UW		 2469 char annex[32];
2470 gdb_byte buf[1024];
2471 LONGEST len;
22e048c9 2472 int id;
23d964e7 2473
0391f248
UW		 2474 if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
2475 error (_("\"info spu\" is only supported on the SPU architecture."));
2476
23d964e7
UW		 2477 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2478
2479 xsnprintf (annex, sizeof annex, "%d/dma_info", id);
2480 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2481 buf, 0, 40 + 16 * 32);
2482 if (len <= 0)
2483 error (_("Could not read dma_info."));
2484
e17a4113
UW		 2485 dma_info_type
2486 = extract_unsigned_integer (buf, 8, byte_order);
2487 dma_info_mask
2488 = extract_unsigned_integer (buf + 8, 8, byte_order);
2489 dma_info_status
2490 = extract_unsigned_integer (buf + 16, 8, byte_order);
2491 dma_info_stall_and_notify
2492 = extract_unsigned_integer (buf + 24, 8, byte_order);
2493 dma_info_atomic_command_status
2494 = extract_unsigned_integer (buf + 32, 8, byte_order);
23d964e7 2495
76f9c9cf 2496 ui_out_emit_tuple tuple_emitter (current_uiout, "SPUInfoDMA");
23d964e7 2497
112e8700 2498 if (current_uiout->is_mi_like_p ())
23d964e7 2499 {
112e8700
SM		 2500 current_uiout->field_fmt ("dma_info_type", "0x%s",
2501 phex_nz (dma_info_type, 4));
2502 current_uiout->field_fmt ("dma_info_mask", "0x%s",
2503 phex_nz (dma_info_mask, 4));
2504 current_uiout->field_fmt ("dma_info_status", "0x%s",
2505 phex_nz (dma_info_status, 4));
2506 current_uiout->field_fmt ("dma_info_stall_and_notify", "0x%s",
2507 phex_nz (dma_info_stall_and_notify, 4));
2508 current_uiout->field_fmt ("dma_info_atomic_command_status", "0x%s",
2509 phex_nz (dma_info_atomic_command_status, 4));
23d964e7
UW		 2510 }
2511 else
2512 {
8fbde58b 2513 const char *query_msg = _("no query pending");
23d964e7 2514
8fbde58b
UW		 2515 if (dma_info_type & 4)
2516 switch (dma_info_type & 3)
2517 {
2518 case 1: query_msg = _("'any' query pending"); break;
2519 case 2: query_msg = _("'all' query pending"); break;
2520 default: query_msg = _("undefined query type"); break;
2521 }
23d964e7
UW		 2522
2523 printf_filtered (_("Tag-Group Status 0x%s\n"),
2524 phex (dma_info_status, 4));
2525 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
2526 phex (dma_info_mask, 4), query_msg);
2527 printf_filtered (_("Stall-and-Notify 0x%s\n"),
2528 phex (dma_info_stall_and_notify, 4));
2529 printf_filtered (_("Atomic Cmd Status 0x%s\n"),
2530 phex (dma_info_atomic_command_status, 4));
2531 printf_filtered ("\n");
2532 }
2533
e17a4113 2534 info_spu_dma_cmdlist (buf + 40, 16, byte_order);
23d964e7
UW		 2535}
2536
2537static void
2538info_spu_proxydma_command (char *args, int from_tty)
2539{
2540 struct frame_info *frame = get_selected_frame (NULL);
e17a4113
UW		 2541 struct gdbarch *gdbarch = get_frame_arch (frame);
2542 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
23d964e7
UW		 2543 ULONGEST dma_info_type;
2544 ULONGEST dma_info_mask;
2545 ULONGEST dma_info_status;
23d964e7
UW		 2546 char annex[32];
2547 gdb_byte buf[1024];
2548 LONGEST len;
22e048c9 2549 int id;
23d964e7 2550
e17a4113 2551 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
0391f248
UW		 2552 error (_("\"info spu\" is only supported on the SPU architecture."));
2553
23d964e7
UW		 2554 id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2555
2556 xsnprintf (annex, sizeof annex, "%d/proxydma_info", id);
2557 len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2558 buf, 0, 24 + 8 * 32);
2559 if (len <= 0)
2560 error (_("Could not read proxydma_info."));
2561
e17a4113
UW		 2562 dma_info_type = extract_unsigned_integer (buf, 8, byte_order);
2563 dma_info_mask = extract_unsigned_integer (buf + 8, 8, byte_order);
2564 dma_info_status = extract_unsigned_integer (buf + 16, 8, byte_order);
23d964e7 2565
76f9c9cf 2566 ui_out_emit_tuple tuple_emitter (current_uiout, "SPUInfoProxyDMA");
23d964e7 2567
112e8700 2568 if (current_uiout->is_mi_like_p ())
23d964e7 2569 {
112e8700
SM		 2570 current_uiout->field_fmt ("proxydma_info_type", "0x%s",
2571 phex_nz (dma_info_type, 4));
2572 current_uiout->field_fmt ("proxydma_info_mask", "0x%s",
2573 phex_nz (dma_info_mask, 4));
2574 current_uiout->field_fmt ("proxydma_info_status", "0x%s",
2575 phex_nz (dma_info_status, 4));
23d964e7
UW		 2576 }
2577 else
2578 {
2579 const char *query_msg;
2580
8fbde58b 2581 switch (dma_info_type & 3)
23d964e7
UW		 2582 {
2583 case 0: query_msg = _("no query pending"); break;
2584 case 1: query_msg = _("'any' query pending"); break;
2585 case 2: query_msg = _("'all' query pending"); break;
2586 default: query_msg = _("undefined query type"); break;
2587 }
2588
2589 printf_filtered (_("Tag-Group Status 0x%s\n"),
2590 phex (dma_info_status, 4));
2591 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
2592 phex (dma_info_mask, 4), query_msg);
2593 printf_filtered ("\n");
2594 }
2595
e17a4113 2596 info_spu_dma_cmdlist (buf + 24, 8, byte_order);
23d964e7
UW		 2597}
2598
2599static void
2600info_spu_command (char *args, int from_tty)
2601{
c378eb4e
MS		 2602 printf_unfiltered (_("\"info spu\" must be followed by "
2603 "the name of an SPU facility.\n"));
635c7e8a 2604 help_list (infospucmdlist, "info spu ", all_commands, gdb_stdout);
23d964e7
UW		 2605}
2606
2607
3285f3fe
UW		 2608/* Root of all "set spu "/"show spu " commands. */
2609
2610static void
2611show_spu_command (char *args, int from_tty)
2612{
2613 help_list (showspucmdlist, "show spu ", all_commands, gdb_stdout);
2614}
2615
2616static void
2617set_spu_command (char *args, int from_tty)
2618{
2619 help_list (setspucmdlist, "set spu ", all_commands, gdb_stdout);
2620}
2621
2622static void
2623show_spu_stop_on_load (struct ui_file *file, int from_tty,
2624 struct cmd_list_element *c, const char *value)
2625{
2626 fprintf_filtered (file, _("Stopping for new SPE threads is %s.\n"),
2627 value);
2628}
2629
ff1a52c6
UW		 2630static void
2631show_spu_auto_flush_cache (struct ui_file *file, int from_tty,
2632 struct cmd_list_element *c, const char *value)
2633{
2634 fprintf_filtered (file, _("Automatic software-cache flush is %s.\n"),
2635 value);
2636}
2637
3285f3fe 2638
771b4502
UW		 2639/* Set up gdbarch struct. */
2640
2641static struct gdbarch *
2642spu_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2643{
2644 struct gdbarch *gdbarch;
794ac428 2645 struct gdbarch_tdep *tdep;
85e747d2
UW		 2646 int id = -1;
2647
2648 /* Which spufs ID was requested as address space? */
0dba2a6c
MR		 2649 if (info.id)
2650 id = *info.id;
85e747d2
UW		 2651 /* For objfile architectures of SPU solibs, decode the ID from the name.
2652 This assumes the filename convention employed by solib-spu.c. */
2653 else if (info.abfd)
2654 {
53e78085 2655 const char *name = strrchr (info.abfd->filename, '@');
85e747d2
UW		 2656 if (name)
2657 sscanf (name, "@0x%*x <%d>", &id);
2658 }
771b4502 2659
85e747d2
UW		 2660 /* Find a candidate among extant architectures. */
2661 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2662 arches != NULL;
2663 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2664 {
2665 tdep = gdbarch_tdep (arches->gdbarch);
2666 if (tdep && tdep->id == id)
2667 return arches->gdbarch;
2668 }
771b4502 2669
85e747d2 2670 /* None found, so create a new architecture. */
fc270c35 2671 tdep = XCNEW (struct gdbarch_tdep);
85e747d2 2672 tdep->id = id;
794ac428 2673 gdbarch = gdbarch_alloc (&info, tdep);
771b4502
UW		 2674
2675 /* Disassembler. */
85e747d2 2676 set_gdbarch_print_insn (gdbarch, gdb_print_insn_spu);
771b4502
UW		 2677
2678 /* Registers. */
2679 set_gdbarch_num_regs (gdbarch, SPU_NUM_REGS);
2680 set_gdbarch_num_pseudo_regs (gdbarch, SPU_NUM_PSEUDO_REGS);
2681 set_gdbarch_sp_regnum (gdbarch, SPU_SP_REGNUM);
2682 set_gdbarch_pc_regnum (gdbarch, SPU_PC_REGNUM);
118dfbaf
UW		 2683 set_gdbarch_read_pc (gdbarch, spu_read_pc);
2684 set_gdbarch_write_pc (gdbarch, spu_write_pc);
771b4502
UW		 2685 set_gdbarch_register_name (gdbarch, spu_register_name);
2686 set_gdbarch_register_type (gdbarch, spu_register_type);
2687 set_gdbarch_pseudo_register_read (gdbarch, spu_pseudo_register_read);
2688 set_gdbarch_pseudo_register_write (gdbarch, spu_pseudo_register_write);
9acbedc0 2689 set_gdbarch_value_from_register (gdbarch, spu_value_from_register);
771b4502 2690 set_gdbarch_register_reggroup_p (gdbarch, spu_register_reggroup_p);
7ce16bd4
UW		 2691 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, spu_dwarf_reg_to_regnum);
2692 set_gdbarch_ax_pseudo_register_collect
2693 (gdbarch, spu_ax_pseudo_register_collect);
2694 set_gdbarch_ax_pseudo_register_push_stack
2695 (gdbarch, spu_ax_pseudo_register_push_stack);
771b4502
UW		 2696
2697 /* Data types. */
2698 set_gdbarch_char_signed (gdbarch, 0);
2699 set_gdbarch_ptr_bit (gdbarch, 32);
2700 set_gdbarch_addr_bit (gdbarch, 32);
2701 set_gdbarch_short_bit (gdbarch, 16);
2702 set_gdbarch_int_bit (gdbarch, 32);
2703 set_gdbarch_long_bit (gdbarch, 32);
2704 set_gdbarch_long_long_bit (gdbarch, 64);
2705 set_gdbarch_float_bit (gdbarch, 32);
2706 set_gdbarch_double_bit (gdbarch, 64);
2707 set_gdbarch_long_double_bit (gdbarch, 64);
8da61cc4
DJ		 2708 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2709 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2710 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
771b4502 2711
ff1a52c6 2712 /* Address handling. */
85e747d2 2713 set_gdbarch_address_to_pointer (gdbarch, spu_address_to_pointer);
36acd84e
UW		 2714 set_gdbarch_pointer_to_address (gdbarch, spu_pointer_to_address);
2715 set_gdbarch_integer_to_address (gdbarch, spu_integer_to_address);
ff1a52c6
UW		 2716 set_gdbarch_address_class_type_flags (gdbarch, spu_address_class_type_flags);
2717 set_gdbarch_address_class_type_flags_to_name
2718 (gdbarch, spu_address_class_type_flags_to_name);
2719 set_gdbarch_address_class_name_to_type_flags
2720 (gdbarch, spu_address_class_name_to_type_flags);
2721
36acd84e 2722
771b4502 2723 /* Inferior function calls. */
7b3dc0b7
UW		 2724 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
2725 set_gdbarch_frame_align (gdbarch, spu_frame_align);
5141027d 2726 set_gdbarch_frame_red_zone_size (gdbarch, 2000);
87805e63 2727 set_gdbarch_push_dummy_code (gdbarch, spu_push_dummy_code);
771b4502 2728 set_gdbarch_push_dummy_call (gdbarch, spu_push_dummy_call);
8d998b8f 2729 set_gdbarch_dummy_id (gdbarch, spu_dummy_id);
771b4502
UW		 2730 set_gdbarch_return_value (gdbarch, spu_return_value);
2731
2732 /* Frame handling. */
2733 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
7ce16bd4 2734 dwarf2_append_unwinders (gdbarch);
8d998b8f 2735 frame_unwind_append_unwinder (gdbarch, &spu_frame_unwind);
771b4502
UW		 2736 frame_base_set_default (gdbarch, &spu_frame_base);
2737 set_gdbarch_unwind_pc (gdbarch, spu_unwind_pc);
2738 set_gdbarch_unwind_sp (gdbarch, spu_unwind_sp);
2739 set_gdbarch_virtual_frame_pointer (gdbarch, spu_virtual_frame_pointer);
2740 set_gdbarch_frame_args_skip (gdbarch, 0);
2741 set_gdbarch_skip_prologue (gdbarch, spu_skip_prologue);
c9cf6e20 2742 set_gdbarch_stack_frame_destroyed_p (gdbarch, spu_stack_frame_destroyed_p);
771b4502 2743
cc5f0d61
UW		 2744 /* Cell/B.E. cross-architecture unwinder support. */
2745 frame_unwind_prepend_unwinder (gdbarch, &spu2ppu_unwind);
2746
771b4502
UW		 2747 /* Breakpoints. */
2748 set_gdbarch_decr_pc_after_break (gdbarch, 4);
04180708
YQ		 2749 set_gdbarch_breakpoint_kind_from_pc (gdbarch, spu_breakpoint::kind_from_pc);
2750 set_gdbarch_sw_breakpoint_from_kind (gdbarch, spu_breakpoint::bp_from_kind);
d03285ec 2751 set_gdbarch_memory_remove_breakpoint (gdbarch, spu_memory_remove_breakpoint);
771b4502 2752 set_gdbarch_software_single_step (gdbarch, spu_software_single_step);
6e3f70d7 2753 set_gdbarch_get_longjmp_target (gdbarch, spu_get_longjmp_target);
771b4502 2754
dcf52cd8
UW		 2755 /* Overlays. */
2756 set_gdbarch_overlay_update (gdbarch, spu_overlay_update);
2757
771b4502
UW		 2758 return gdbarch;
2759}
2760
2761void
2762_initialize_spu_tdep (void)
2763{
2764 register_gdbarch_init (bfd_arch_spu, spu_gdbarch_init);
f2d43c2c 2765
dcf52cd8
UW		 2766 /* Add ourselves to objfile event chain. */
2767 observer_attach_new_objfile (spu_overlay_new_objfile);
2768 spu_overlay_data = register_objfile_data ();
23d964e7 2769
3285f3fe
UW		 2770 /* Install spu stop-on-load handler. */
2771 observer_attach_new_objfile (spu_catch_start);
2772
ff1a52c6
UW		 2773 /* Add ourselves to normal_stop event chain. */
2774 observer_attach_normal_stop (spu_attach_normal_stop);
2775
3285f3fe
UW		 2776 /* Add root prefix command for all "set spu"/"show spu" commands. */
2777 add_prefix_cmd ("spu", no_class, set_spu_command,
2778 _("Various SPU specific commands."),
2779 &setspucmdlist, "set spu ", 0, &setlist);
2780 add_prefix_cmd ("spu", no_class, show_spu_command,
2781 _("Various SPU specific commands."),
2782 &showspucmdlist, "show spu ", 0, &showlist);
2783
2784 /* Toggle whether or not to add a temporary breakpoint at the "main"
2785 function of new SPE contexts. */
2786 add_setshow_boolean_cmd ("stop-on-load", class_support,
2787 &spu_stop_on_load_p, _("\
2788Set whether to stop for new SPE threads."),
2789 _("\
2790Show whether to stop for new SPE threads."),
2791 _("\
2792Use \"on\" to give control to the user when a new SPE thread\n\
2793enters its \"main\" function.\n\
2794Use \"off\" to disable stopping for new SPE threads."),
2795 NULL,
2796 show_spu_stop_on_load,
2797 &setspucmdlist, &showspucmdlist);
2798
ff1a52c6
UW		 2799 /* Toggle whether or not to automatically flush the software-managed
2800 cache whenever SPE execution stops. */
2801 add_setshow_boolean_cmd ("auto-flush-cache", class_support,
2802 &spu_auto_flush_cache_p, _("\
2803Set whether to automatically flush the software-managed cache."),
2804 _("\
2805Show whether to automatically flush the software-managed cache."),
2806 _("\
2807Use \"on\" to automatically flush the software-managed cache\n\
2808whenever SPE execution stops.\n\
2809Use \"off\" to never automatically flush the software-managed cache."),
2810 NULL,
2811 show_spu_auto_flush_cache,
2812 &setspucmdlist, &showspucmdlist);
2813
23d964e7
UW		 2814 /* Add root prefix command for all "info spu" commands. */
2815 add_prefix_cmd ("spu", class_info, info_spu_command,
2816 _("Various SPU specific commands."),
2817 &infospucmdlist, "info spu ", 0, &infolist);
2818
2819 /* Add various "info spu" commands. */
2820 add_cmd ("event", class_info, info_spu_event_command,
2821 _("Display SPU event facility status.\n"),
2822 &infospucmdlist);
2823 add_cmd ("signal", class_info, info_spu_signal_command,
2824 _("Display SPU signal notification facility status.\n"),
2825 &infospucmdlist);
2826 add_cmd ("mailbox", class_info, info_spu_mailbox_command,
2827 _("Display SPU mailbox facility status.\n"),
2828 &infospucmdlist);
2829 add_cmd ("dma", class_info, info_spu_dma_command,
2830 _("Display MFC DMA status.\n"),
2831 &infospucmdlist);
2832 add_cmd ("proxydma", class_info, info_spu_proxydma_command,
2833 _("Display MFC Proxy-DMA status.\n"),
2834 &infospucmdlist);
771b4502 2835}
GDB Binutils - Deliverables
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