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1 | /* Helper file for i386 platform. Runtime check for MMX/SSE/SSE2 support. |
2 | ||
0fb0cc75 | 3 | Copyright 2004, 2007, 2008, 2009 Free Software Foundation, Inc. |
83ecb59f JB |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
83ecb59f | 10 | (at your option) any later version. |
a9762ec7 | 11 | |
83ecb59f JB |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
a9762ec7 | 16 | |
83ecb59f | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
83ecb59f JB |
19 | |
20 | /* Used by 20020523-2.c and i386-sse-6.c, and possibly others. */ | |
21 | /* Plagarized from 20020523-2.c. */ | |
22 | /* Plagarized from gcc. */ | |
23 | ||
24 | #define bit_CMOV (1 << 15) | |
25 | #define bit_MMX (1 << 23) | |
26 | #define bit_SSE (1 << 25) | |
27 | #define bit_SSE2 (1 << 26) | |
28 | ||
29 | #ifndef NOINLINE | |
30 | #define NOINLINE __attribute__ ((noinline)) | |
31 | #endif | |
32 | ||
33 | unsigned int i386_cpuid (void) NOINLINE; | |
34 | ||
35 | unsigned int NOINLINE | |
36 | i386_cpuid (void) | |
37 | { | |
38 | int fl1, fl2; | |
39 | ||
40 | #ifndef __x86_64__ | |
41 | /* See if we can use cpuid. On AMD64 we always can. */ | |
42 | __asm__ ("pushfl; pushfl; popl %0; movl %0,%1; xorl %2,%0;" | |
43 | "pushl %0; popfl; pushfl; popl %0; popfl" | |
44 | : "=&r" (fl1), "=&r" (fl2) | |
45 | : "i" (0x00200000)); | |
46 | if (((fl1 ^ fl2) & 0x00200000) == 0) | |
47 | return (0); | |
48 | #endif | |
49 | ||
50 | /* Host supports cpuid. See if cpuid gives capabilities, try | |
51 | CPUID(0). Preserve %ebx and %ecx; cpuid insn clobbers these, we | |
52 | don't need their CPUID values here, and %ebx may be the PIC | |
53 | register. */ | |
54 | #ifdef __x86_64__ | |
55 | __asm__ ("pushq %%rcx; pushq %%rbx; cpuid; popq %%rbx; popq %%rcx" | |
56 | : "=a" (fl1) : "0" (0) : "rdx", "cc"); | |
57 | #else | |
58 | __asm__ ("pushl %%ecx; pushl %%ebx; cpuid; popl %%ebx; popl %%ecx" | |
59 | : "=a" (fl1) : "0" (0) : "edx", "cc"); | |
60 | #endif | |
61 | if (fl1 == 0) | |
62 | return (0); | |
63 | ||
64 | /* Invoke CPUID(1), return %edx; caller can examine bits to | |
65 | determine what's supported. */ | |
66 | #ifdef __x86_64__ | |
67 | __asm__ ("pushq %%rcx; pushq %%rbx; cpuid; popq %%rbx; popq %%rcx" | |
68 | : "=d" (fl2), "=a" (fl1) : "1" (1) : "cc"); | |
69 | #else | |
70 | __asm__ ("pushl %%ecx; pushl %%ebx; cpuid; popl %%ebx; popl %%ecx" | |
71 | : "=d" (fl2), "=a" (fl1) : "1" (1) : "cc"); | |
72 | #endif | |
73 | ||
74 | return fl2; | |
75 | } |