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767a879e AB |
1 | <?xml version="1.0"?> |
2 | <!DOCTYPE target SYSTEM "gdb-target.dtd"> | |
3 | <target> | |
4 | <architecture>riscv</architecture> | |
5 | <feature name="org.gnu.gdb.riscv.cpu"> | |
6 | <reg name="zero" bitsize="64" type="int"/> | |
7 | <reg name="ra" bitsize="64" type="code_ptr"/> | |
8 | <reg name="sp" bitsize="64" type="data_ptr"/> | |
9 | <reg name="gp" bitsize="64" type="data_ptr"/> | |
10 | <reg name="tp" bitsize="64" type="data_ptr"/> | |
11 | <reg name="t0" bitsize="64" type="int"/> | |
12 | <reg name="t1" bitsize="64" type="int"/> | |
13 | <reg name="t2" bitsize="64" type="int"/> | |
14 | <reg name="fp" bitsize="64" type="data_ptr"/> | |
15 | <reg name="s1" bitsize="64" type="int"/> | |
16 | <reg name="a0" bitsize="64" type="int"/> | |
17 | <reg name="a1" bitsize="64" type="int"/> | |
18 | <reg name="a2" bitsize="64" type="int"/> | |
19 | <reg name="a3" bitsize="64" type="int"/> | |
20 | <reg name="a4" bitsize="64" type="int"/> | |
21 | <reg name="a5" bitsize="64" type="int"/> | |
22 | <reg name="a6" bitsize="64" type="int"/> | |
23 | <reg name="a7" bitsize="64" type="int"/> | |
24 | <reg name="s2" bitsize="64" type="int"/> | |
25 | <reg name="s3" bitsize="64" type="int"/> | |
26 | <reg name="s4" bitsize="64" type="int"/> | |
27 | <reg name="s5" bitsize="64" type="int"/> | |
28 | <reg name="s6" bitsize="64" type="int"/> | |
29 | <reg name="s7" bitsize="64" type="int"/> | |
30 | <reg name="s8" bitsize="64" type="int"/> | |
31 | <reg name="s9" bitsize="64" type="int"/> | |
32 | <reg name="s10" bitsize="64" type="int"/> | |
33 | <reg name="s11" bitsize="64" type="int"/> | |
34 | <reg name="t3" bitsize="64" type="int"/> | |
35 | <reg name="t4" bitsize="64" type="int"/> | |
36 | <reg name="t5" bitsize="64" type="int"/> | |
37 | <reg name="t6" bitsize="64" type="int"/> | |
38 | <reg name="pc" bitsize="64" type="code_ptr"/> | |
39 | </feature> | |
40 | <feature name="org.gnu.gdb.riscv.fpu"> | |
41 | <union id="riscv_double"> | |
42 | <field name="float" type="ieee_single"/> | |
43 | <field name="double" type="ieee_double"/> | |
44 | </union> | |
45 | <reg name="ft0" bitsize="64" type="riscv_double"/> | |
46 | <reg name="ft1" bitsize="64" type="riscv_double"/> | |
47 | <reg name="ft2" bitsize="64" type="riscv_double"/> | |
48 | <reg name="ft3" bitsize="64" type="riscv_double"/> | |
49 | <reg name="ft4" bitsize="64" type="riscv_double"/> | |
50 | <reg name="ft5" bitsize="64" type="riscv_double"/> | |
51 | <reg name="ft6" bitsize="64" type="riscv_double"/> | |
52 | <reg name="ft7" bitsize="64" type="riscv_double"/> | |
53 | <reg name="fs0" bitsize="64" type="riscv_double"/> | |
54 | <reg name="fs1" bitsize="64" type="riscv_double"/> | |
55 | <reg name="fa0" bitsize="64" type="riscv_double"/> | |
56 | <reg name="fa1" bitsize="64" type="riscv_double"/> | |
57 | <reg name="fa2" bitsize="64" type="riscv_double"/> | |
58 | <reg name="fa3" bitsize="64" type="riscv_double"/> | |
59 | <reg name="fa4" bitsize="64" type="riscv_double"/> | |
60 | <reg name="fa5" bitsize="64" type="riscv_double"/> | |
61 | <reg name="fa6" bitsize="64" type="riscv_double"/> | |
62 | <reg name="fa7" bitsize="64" type="riscv_double"/> | |
63 | <reg name="fs2" bitsize="64" type="riscv_double"/> | |
64 | <reg name="fs3" bitsize="64" type="riscv_double"/> | |
65 | <reg name="fs4" bitsize="64" type="riscv_double"/> | |
66 | <reg name="fs5" bitsize="64" type="riscv_double"/> | |
67 | <reg name="fs6" bitsize="64" type="riscv_double"/> | |
68 | <reg name="fs7" bitsize="64" type="riscv_double"/> | |
69 | <reg name="fs8" bitsize="64" type="riscv_double"/> | |
70 | <reg name="fs9" bitsize="64" type="riscv_double"/> | |
71 | <reg name="fs10" bitsize="64" type="riscv_double"/> | |
72 | <reg name="fs11" bitsize="64" type="riscv_double"/> | |
73 | <reg name="ft8" bitsize="64" type="riscv_double"/> | |
74 | <reg name="ft9" bitsize="64" type="riscv_double"/> | |
75 | <reg name="ft10" bitsize="64" type="riscv_double"/> | |
76 | <reg name="ft11" bitsize="64" type="riscv_double"/> | |
77 | <!-- The following 3 registers are duplicated. --> | |
78 | <reg name="fflags" bitsize="32" type="int"/> | |
79 | <reg name="frm" bitsize="32" type="int"/> | |
80 | <reg name="fcsr" bitsize="32" type="int"/> | |
81 | </feature> | |
82 | <feature name="org.gnu.gdb.riscv.csr"> | |
83 | <!-- The following 3 registers are duplicated. --> | |
84 | <reg name="fflags" bitsize="32" type="int"/> | |
85 | <reg name="frm" bitsize="32" type="int"/> | |
86 | <reg name="fcsr" bitsize="32" type="int"/> | |
87 | <!-- The following is a CSR unknown to GDB. --> | |
88 | <reg name="unknown_csr" bitsize="32" type="int"/> | |
89 | <!-- The following is now known as 'dscratch0' in the official | |
90 | RISC-V spec, but GDB should NOT rename this register. --> | |
91 | <reg name="dscratch" bitsize="32" type="int"/> | |
92 | </feature> | |
93 | </target> |