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8cd64e00 YQ |
1 | /* Target dependent code for GDB on TI C6x systems. |
2 | ||
618f726f | 3 | Copyright (C) 2010-2016 Free Software Foundation, Inc. |
8cd64e00 YQ |
4 | Contributed by Andrew Jenner <andrew@codesourcery.com> |
5 | Contributed by Yao Qi <yao@codesourcery.com> | |
6 | ||
7 | This file is part of GDB. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | #include "defs.h" | |
23 | #include "frame.h" | |
24 | #include "frame-unwind.h" | |
25 | #include "frame-base.h" | |
26 | #include "trad-frame.h" | |
27 | #include "dwarf2-frame.h" | |
28 | #include "symtab.h" | |
29 | #include "inferior.h" | |
30 | #include "gdbtypes.h" | |
31 | #include "gdbcore.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "target.h" | |
34 | #include "dis-asm.h" | |
35 | #include "regcache.h" | |
36 | #include "value.h" | |
37 | #include "symfile.h" | |
38 | #include "arch-utils.h" | |
39 | #include "floatformat.h" | |
40 | #include "glibc-tdep.h" | |
41 | #include "infcall.h" | |
42 | #include "regset.h" | |
43 | #include "tramp-frame.h" | |
44 | #include "linux-tdep.h" | |
45 | #include "solib.h" | |
46 | #include "objfiles.h" | |
8cd64e00 YQ |
47 | #include "osabi.h" |
48 | #include "tic6x-tdep.h" | |
49 | #include "language.h" | |
50 | #include "target-descriptions.h" | |
325fac50 | 51 | #include <algorithm> |
8cd64e00 YQ |
52 | |
53 | #include "features/tic6x-c64xp.c" | |
54 | #include "features/tic6x-c64x.c" | |
55 | #include "features/tic6x-c62x.c" | |
56 | ||
57 | #define TIC6X_OPCODE_SIZE 4 | |
58 | #define TIC6X_FETCH_PACKET_SIZE 32 | |
59 | ||
60 | #define INST_S_BIT(INST) ((INST >> 1) & 1) | |
61 | #define INST_X_BIT(INST) ((INST >> 12) & 1) | |
62 | ||
85661b1e YQ |
63 | const gdb_byte tic6x_bkpt_illegal_opcode_be[] = { 0x56, 0x45, 0x43, 0x14 }; |
64 | const gdb_byte tic6x_bkpt_illegal_opcode_le[] = { 0x14, 0x43, 0x45, 0x56 }; | |
65 | ||
8cd64e00 YQ |
66 | struct tic6x_unwind_cache |
67 | { | |
68 | /* The frame's base, optionally used by the high-level debug info. */ | |
69 | CORE_ADDR base; | |
70 | ||
71 | /* The previous frame's inner most stack address. Used as this | |
72 | frame ID's stack_addr. */ | |
73 | CORE_ADDR cfa; | |
74 | ||
75 | /* The address of the first instruction in this function */ | |
76 | CORE_ADDR pc; | |
77 | ||
78 | /* Which register holds the return address for the frame. */ | |
79 | int return_regnum; | |
80 | ||
81 | /* The offset of register saved on stack. If register is not saved, the | |
82 | corresponding element is -1. */ | |
83 | CORE_ADDR reg_saved[TIC6X_NUM_CORE_REGS]; | |
84 | }; | |
85 | ||
86 | ||
87 | /* Name of TI C6x core registers. */ | |
88 | static const char *const tic6x_register_names[] = | |
89 | { | |
90 | "A0", "A1", "A2", "A3", /* 0 1 2 3 */ | |
91 | "A4", "A5", "A6", "A7", /* 4 5 6 7 */ | |
92 | "A8", "A9", "A10", "A11", /* 8 9 10 11 */ | |
93 | "A12", "A13", "A14", "A15", /* 12 13 14 15 */ | |
94 | "B0", "B1", "B2", "B3", /* 16 17 18 19 */ | |
95 | "B4", "B5", "B6", "B7", /* 20 21 22 23 */ | |
96 | "B8", "B9", "B10", "B11", /* 24 25 26 27 */ | |
97 | "B12", "B13", "B14", "B15", /* 28 29 30 31 */ | |
98 | "CSR", "PC", /* 32 33 */ | |
99 | }; | |
100 | ||
101 | /* This array maps the arguments to the register number which passes argument | |
102 | in function call according to C6000 ELF ABI. */ | |
103 | static const int arg_regs[] = { 4, 20, 6, 22, 8, 24, 10, 26, 12, 28 }; | |
104 | ||
105 | /* This is the implementation of gdbarch method register_name. */ | |
106 | ||
107 | static const char * | |
108 | tic6x_register_name (struct gdbarch *gdbarch, int regno) | |
109 | { | |
110 | if (regno < 0) | |
111 | return NULL; | |
112 | ||
113 | if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) | |
114 | return tdesc_register_name (gdbarch, regno); | |
115 | else if (regno >= ARRAY_SIZE (tic6x_register_names)) | |
116 | return ""; | |
117 | else | |
118 | return tic6x_register_names[regno]; | |
119 | } | |
120 | ||
121 | /* This is the implementation of gdbarch method register_type. */ | |
122 | ||
123 | static struct type * | |
124 | tic6x_register_type (struct gdbarch *gdbarch, int regno) | |
125 | { | |
126 | ||
127 | if (regno == TIC6X_PC_REGNUM) | |
128 | return builtin_type (gdbarch)->builtin_func_ptr; | |
129 | else | |
130 | return builtin_type (gdbarch)->builtin_uint32; | |
131 | } | |
132 | ||
133 | static void | |
134 | tic6x_setup_default (struct tic6x_unwind_cache *cache) | |
135 | { | |
136 | int i; | |
137 | ||
138 | for (i = 0; i < TIC6X_NUM_CORE_REGS; i++) | |
139 | cache->reg_saved[i] = -1; | |
140 | } | |
141 | ||
142 | static unsigned long tic6x_fetch_instruction (struct gdbarch *, CORE_ADDR); | |
143 | static int tic6x_register_number (int reg, int side, int crosspath); | |
144 | ||
145 | /* Do a full analysis of the prologue at START_PC and update CACHE accordingly. | |
146 | Bail out early if CURRENT_PC is reached. Returns the address of the first | |
147 | instruction after the prologue. */ | |
148 | ||
693be288 | 149 | static CORE_ADDR |
8cd64e00 YQ |
150 | tic6x_analyze_prologue (struct gdbarch *gdbarch, const CORE_ADDR start_pc, |
151 | const CORE_ADDR current_pc, | |
152 | struct tic6x_unwind_cache *cache, | |
153 | struct frame_info *this_frame) | |
154 | { | |
8cd64e00 YQ |
155 | unsigned long inst; |
156 | unsigned int src_reg, base_reg, dst_reg; | |
157 | int i; | |
158 | CORE_ADDR pc = start_pc; | |
159 | CORE_ADDR return_pc = start_pc; | |
160 | int frame_base_offset_to_sp = 0; | |
161 | /* Counter of non-stw instructions after first insn ` sub sp, xxx, sp'. */ | |
162 | int non_stw_insn_counter = 0; | |
163 | ||
164 | if (start_pc >= current_pc) | |
165 | return_pc = current_pc; | |
166 | ||
167 | cache->base = 0; | |
168 | ||
169 | /* The landmarks in prologue is one or two SUB instructions to SP. | |
170 | Instructions on setting up dsbt are in the last part of prologue, if | |
171 | needed. In maxim, prologue can be divided to three parts by two | |
172 | `sub sp, xx, sp' insns. */ | |
173 | ||
174 | /* Step 1: Look for the 1st and 2nd insn `sub sp, xx, sp', in which, the | |
175 | 2nd one is optional. */ | |
176 | while (pc < current_pc) | |
177 | { | |
8cd64e00 YQ |
178 | unsigned long inst = tic6x_fetch_instruction (gdbarch, pc); |
179 | ||
180 | if ((inst & 0x1ffc) == 0x1dc0 || (inst & 0x1ffc) == 0x1bc0 | |
181 | || (inst & 0x0ffc) == 0x9c0) | |
182 | { | |
183 | /* SUBAW/SUBAH/SUB, and src1 is ucst 5. */ | |
184 | unsigned int src2 = tic6x_register_number ((inst >> 18) & 0x1f, | |
185 | INST_S_BIT (inst), 0); | |
186 | unsigned int dst = tic6x_register_number ((inst >> 23) & 0x1f, | |
187 | INST_S_BIT (inst), 0); | |
188 | ||
189 | if (src2 == TIC6X_SP_REGNUM && dst == TIC6X_SP_REGNUM) | |
190 | { | |
191 | /* Extract const from insn SUBAW/SUBAH/SUB, and translate it to | |
192 | offset. The constant offset is decoded in bit 13-17 in all | |
193 | these three kinds of instructions. */ | |
194 | unsigned int ucst5 = (inst >> 13) & 0x1f; | |
195 | ||
196 | if ((inst & 0x1ffc) == 0x1dc0) /* SUBAW */ | |
197 | frame_base_offset_to_sp += ucst5 << 2; | |
198 | else if ((inst & 0x1ffc) == 0x1bc0) /* SUBAH */ | |
199 | frame_base_offset_to_sp += ucst5 << 1; | |
200 | else if ((inst & 0x0ffc) == 0x9c0) /* SUB */ | |
201 | frame_base_offset_to_sp += ucst5; | |
202 | else | |
203 | gdb_assert_not_reached ("unexpected instruction"); | |
204 | ||
205 | return_pc = pc + 4; | |
206 | } | |
207 | } | |
208 | else if ((inst & 0x174) == 0x74) /* stw SRC, *+b15(uconst) */ | |
209 | { | |
210 | /* The y bit determines which file base is read from. */ | |
211 | base_reg = tic6x_register_number ((inst >> 18) & 0x1f, | |
212 | (inst >> 7) & 1, 0); | |
213 | ||
214 | if (base_reg == TIC6X_SP_REGNUM) | |
215 | { | |
216 | src_reg = tic6x_register_number ((inst >> 23) & 0x1f, | |
217 | INST_S_BIT (inst), 0); | |
218 | ||
219 | cache->reg_saved[src_reg] = ((inst >> 13) & 0x1f) << 2; | |
220 | ||
221 | return_pc = pc + 4; | |
222 | } | |
223 | non_stw_insn_counter = 0; | |
224 | } | |
225 | else | |
226 | { | |
227 | non_stw_insn_counter++; | |
228 | /* Following instruction sequence may be emitted in prologue: | |
229 | ||
230 | <+0>: subah .D2 b15,28,b15 | |
231 | <+4>: or .L2X 0,a4,b0 | |
232 | <+8>: || stw .D2T2 b14,*+b15(56) | |
233 | <+12>:[!b0] b .S1 0xe50e4c1c <sleep+220> | |
234 | <+16>:|| stw .D2T1 a10,*+b15(48) | |
235 | <+20>:stw .D2T2 b3,*+b15(52) | |
236 | <+24>:stw .D2T1 a4,*+b15(40) | |
237 | ||
238 | we should look forward for next instruction instead of breaking loop | |
239 | here. So far, we allow almost two sequential non-stw instructions | |
240 | in prologue. */ | |
241 | if (non_stw_insn_counter >= 2) | |
242 | break; | |
243 | } | |
244 | ||
245 | ||
246 | pc += 4; | |
247 | } | |
248 | /* Step 2: Skip insn on setting up dsbt if it is. Usually, it looks like, | |
249 | ldw .D2T2 *+b14(0),b14 */ | |
250 | inst = tic6x_fetch_instruction (gdbarch, pc); | |
251 | /* The s bit determines which file dst will be loaded into, same effect as | |
252 | other places. */ | |
253 | dst_reg = tic6x_register_number ((inst >> 23) & 0x1f, (inst >> 1) & 1, 0); | |
254 | /* The y bit (bit 7), instead of s bit, determines which file base be | |
255 | used. */ | |
256 | base_reg = tic6x_register_number ((inst >> 18) & 0x1f, (inst >> 7) & 1, 0); | |
257 | ||
258 | if ((inst & 0x164) == 0x64 /* ldw */ | |
259 | && dst_reg == TIC6X_DP_REGNUM /* dst is B14 */ | |
260 | && base_reg == TIC6X_DP_REGNUM) /* baseR is B14 */ | |
261 | { | |
262 | return_pc = pc + 4; | |
263 | } | |
264 | ||
265 | if (this_frame) | |
266 | { | |
267 | cache->base = get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM); | |
268 | ||
269 | if (cache->reg_saved[TIC6X_FP_REGNUM] != -1) | |
270 | { | |
271 | /* If the FP now holds an offset from the CFA then this is a frame | |
272 | which uses the frame pointer. */ | |
273 | ||
274 | cache->cfa = get_frame_register_unsigned (this_frame, | |
275 | TIC6X_FP_REGNUM); | |
276 | } | |
277 | else | |
278 | { | |
279 | /* FP doesn't hold an offset from the CFA. If SP still holds an | |
280 | offset from the CFA then we might be in a function which omits | |
281 | the frame pointer. */ | |
282 | ||
283 | cache->cfa = cache->base + frame_base_offset_to_sp; | |
284 | } | |
285 | } | |
286 | ||
287 | /* Adjust all the saved registers such that they contain addresses | |
288 | instead of offsets. */ | |
289 | for (i = 0; i < TIC6X_NUM_CORE_REGS; i++) | |
290 | if (cache->reg_saved[i] != -1) | |
291 | cache->reg_saved[i] = cache->base + cache->reg_saved[i]; | |
292 | ||
293 | return return_pc; | |
294 | } | |
295 | ||
296 | /* This is the implementation of gdbarch method skip_prologue. */ | |
297 | ||
693be288 | 298 | static CORE_ADDR |
8cd64e00 YQ |
299 | tic6x_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
300 | { | |
8cd64e00 YQ |
301 | CORE_ADDR func_addr; |
302 | struct tic6x_unwind_cache cache; | |
303 | ||
304 | /* See if we can determine the end of the prologue via the symbol table. | |
305 | If so, then return either PC, or the PC after the prologue, whichever is | |
306 | greater. */ | |
307 | if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) | |
308 | { | |
309 | CORE_ADDR post_prologue_pc | |
310 | = skip_prologue_using_sal (gdbarch, func_addr); | |
311 | if (post_prologue_pc != 0) | |
325fac50 | 312 | return std::max (start_pc, post_prologue_pc); |
8cd64e00 YQ |
313 | } |
314 | ||
315 | /* Can't determine prologue from the symbol table, need to examine | |
316 | instructions. */ | |
317 | return tic6x_analyze_prologue (gdbarch, start_pc, (CORE_ADDR) -1, &cache, | |
318 | NULL); | |
319 | } | |
320 | ||
321 | /* This is the implementation of gdbarch method breakpiont_from_pc. */ | |
322 | ||
948f8e3d | 323 | static const gdb_byte * |
8cd64e00 YQ |
324 | tic6x_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr, |
325 | int *bp_size) | |
326 | { | |
327 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
328 | ||
329 | *bp_size = 4; | |
330 | ||
331 | if (tdep == NULL || tdep->breakpoint == NULL) | |
332 | { | |
333 | if (BFD_ENDIAN_BIG == gdbarch_byte_order_for_code (gdbarch)) | |
334 | return tic6x_bkpt_illegal_opcode_be; | |
335 | else | |
336 | return tic6x_bkpt_illegal_opcode_le; | |
337 | } | |
338 | else | |
339 | return tdep->breakpoint; | |
340 | } | |
341 | ||
342 | /* This is the implementation of gdbarch method print_insn. */ | |
343 | ||
344 | static int | |
345 | tic6x_print_insn (bfd_vma memaddr, disassemble_info *info) | |
346 | { | |
347 | return print_insn_tic6x (memaddr, info); | |
348 | } | |
349 | ||
350 | static void | |
351 | tic6x_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
352 | struct dwarf2_frame_state_reg *reg, | |
353 | struct frame_info *this_frame) | |
354 | { | |
355 | /* Mark the PC as the destination for the return address. */ | |
356 | if (regnum == gdbarch_pc_regnum (gdbarch)) | |
357 | reg->how = DWARF2_FRAME_REG_RA; | |
358 | ||
359 | /* Mark the stack pointer as the call frame address. */ | |
360 | else if (regnum == gdbarch_sp_regnum (gdbarch)) | |
361 | reg->how = DWARF2_FRAME_REG_CFA; | |
362 | ||
363 | /* The above was taken from the default init_reg in dwarf2-frame.c | |
364 | while the below is c6x specific. */ | |
365 | ||
366 | /* Callee save registers. The ABI designates A10-A15 and B10-B15 as | |
367 | callee-save. */ | |
368 | else if ((regnum >= 10 && regnum <= 15) || (regnum >= 26 && regnum <= 31)) | |
369 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
370 | else | |
371 | /* All other registers are caller-save. */ | |
372 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
373 | } | |
374 | ||
375 | /* This is the implementation of gdbarch method unwind_pc. */ | |
376 | ||
377 | static CORE_ADDR | |
378 | tic6x_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
379 | { | |
380 | gdb_byte buf[8]; | |
381 | ||
382 | frame_unwind_register (next_frame, TIC6X_PC_REGNUM, buf); | |
383 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); | |
384 | } | |
385 | ||
386 | /* This is the implementation of gdbarch method unwind_sp. */ | |
387 | ||
388 | static CORE_ADDR | |
389 | tic6x_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
390 | { | |
391 | return frame_unwind_register_unsigned (this_frame, TIC6X_SP_REGNUM); | |
392 | } | |
393 | ||
394 | ||
395 | /* Frame base handling. */ | |
396 | ||
693be288 | 397 | static struct tic6x_unwind_cache* |
8cd64e00 YQ |
398 | tic6x_frame_unwind_cache (struct frame_info *this_frame, |
399 | void **this_prologue_cache) | |
400 | { | |
401 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
402 | CORE_ADDR current_pc; | |
403 | struct tic6x_unwind_cache *cache; | |
8cd64e00 YQ |
404 | |
405 | if (*this_prologue_cache) | |
19ba03f4 | 406 | return (struct tic6x_unwind_cache *) *this_prologue_cache; |
8cd64e00 YQ |
407 | |
408 | cache = FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache); | |
409 | (*this_prologue_cache) = cache; | |
410 | ||
411 | cache->return_regnum = TIC6X_RA_REGNUM; | |
412 | ||
413 | tic6x_setup_default (cache); | |
414 | ||
415 | cache->pc = get_frame_func (this_frame); | |
416 | current_pc = get_frame_pc (this_frame); | |
417 | ||
418 | /* Prologue analysis does the rest... */ | |
419 | if (cache->pc != 0) | |
420 | tic6x_analyze_prologue (gdbarch, cache->pc, current_pc, cache, this_frame); | |
421 | ||
422 | return cache; | |
423 | } | |
424 | ||
425 | static void | |
426 | tic6x_frame_this_id (struct frame_info *this_frame, void **this_cache, | |
427 | struct frame_id *this_id) | |
428 | { | |
429 | struct tic6x_unwind_cache *cache = | |
430 | tic6x_frame_unwind_cache (this_frame, this_cache); | |
431 | ||
432 | /* This marks the outermost frame. */ | |
433 | if (cache->base == 0) | |
434 | return; | |
435 | ||
436 | (*this_id) = frame_id_build (cache->cfa, cache->pc); | |
437 | } | |
438 | ||
439 | static struct value * | |
440 | tic6x_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
441 | int regnum) | |
442 | { | |
443 | struct tic6x_unwind_cache *cache = | |
444 | tic6x_frame_unwind_cache (this_frame, this_cache); | |
445 | ||
446 | gdb_assert (regnum >= 0); | |
447 | ||
448 | /* The PC of the previous frame is stored in the RA register of | |
449 | the current frame. Frob regnum so that we pull the value from | |
450 | the correct place. */ | |
451 | if (regnum == TIC6X_PC_REGNUM) | |
452 | regnum = cache->return_regnum; | |
453 | ||
454 | if (regnum == TIC6X_SP_REGNUM && cache->cfa) | |
455 | return frame_unwind_got_constant (this_frame, regnum, cache->cfa); | |
456 | ||
457 | /* If we've worked out where a register is stored then load it from | |
458 | there. */ | |
459 | if (regnum < TIC6X_NUM_CORE_REGS && cache->reg_saved[regnum] != -1) | |
460 | return frame_unwind_got_memory (this_frame, regnum, | |
461 | cache->reg_saved[regnum]); | |
462 | ||
463 | return frame_unwind_got_register (this_frame, regnum, regnum); | |
464 | } | |
465 | ||
466 | static CORE_ADDR | |
467 | tic6x_frame_base_address (struct frame_info *this_frame, void **this_cache) | |
468 | { | |
469 | struct tic6x_unwind_cache *info | |
470 | = tic6x_frame_unwind_cache (this_frame, this_cache); | |
471 | return info->base; | |
472 | } | |
473 | ||
474 | static const struct frame_unwind tic6x_frame_unwind = | |
475 | { | |
476 | NORMAL_FRAME, | |
477 | default_frame_unwind_stop_reason, | |
478 | tic6x_frame_this_id, | |
479 | tic6x_frame_prev_register, | |
480 | NULL, | |
481 | default_frame_sniffer | |
482 | }; | |
483 | ||
484 | static const struct frame_base tic6x_frame_base = | |
485 | { | |
486 | &tic6x_frame_unwind, | |
487 | tic6x_frame_base_address, | |
488 | tic6x_frame_base_address, | |
489 | tic6x_frame_base_address | |
490 | }; | |
491 | ||
492 | ||
493 | static struct tic6x_unwind_cache * | |
494 | tic6x_make_stub_cache (struct frame_info *this_frame) | |
495 | { | |
496 | struct tic6x_unwind_cache *cache; | |
497 | ||
498 | cache = FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache); | |
499 | ||
500 | cache->return_regnum = TIC6X_RA_REGNUM; | |
501 | ||
502 | tic6x_setup_default (cache); | |
503 | ||
504 | cache->cfa = get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM); | |
505 | ||
506 | return cache; | |
507 | } | |
508 | ||
509 | static void | |
510 | tic6x_stub_this_id (struct frame_info *this_frame, void **this_cache, | |
511 | struct frame_id *this_id) | |
512 | { | |
513 | struct tic6x_unwind_cache *cache; | |
514 | ||
515 | if (*this_cache == NULL) | |
516 | *this_cache = tic6x_make_stub_cache (this_frame); | |
19ba03f4 | 517 | cache = (struct tic6x_unwind_cache *) *this_cache; |
8cd64e00 YQ |
518 | |
519 | *this_id = frame_id_build (cache->cfa, get_frame_pc (this_frame)); | |
520 | } | |
521 | ||
522 | static int | |
523 | tic6x_stub_unwind_sniffer (const struct frame_unwind *self, | |
524 | struct frame_info *this_frame, | |
525 | void **this_prologue_cache) | |
526 | { | |
527 | CORE_ADDR addr_in_block; | |
528 | ||
529 | addr_in_block = get_frame_address_in_block (this_frame); | |
3e5d3a5a | 530 | if (in_plt_section (addr_in_block)) |
8cd64e00 YQ |
531 | return 1; |
532 | ||
533 | return 0; | |
534 | } | |
535 | ||
536 | static const struct frame_unwind tic6x_stub_unwind = | |
537 | { | |
538 | NORMAL_FRAME, | |
539 | default_frame_unwind_stop_reason, | |
540 | tic6x_stub_this_id, | |
541 | tic6x_frame_prev_register, | |
542 | NULL, | |
543 | tic6x_stub_unwind_sniffer | |
544 | }; | |
545 | ||
546 | /* Return the instruction on address PC. */ | |
547 | ||
548 | static unsigned long | |
549 | tic6x_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR pc) | |
550 | { | |
551 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
552 | return read_memory_unsigned_integer (pc, TIC6X_OPCODE_SIZE, byte_order); | |
553 | } | |
554 | ||
555 | /* Compute the condition of INST if it is a conditional instruction. Always | |
556 | return 1 if INST is not a conditional instruction. */ | |
557 | ||
558 | static int | |
559 | tic6x_condition_true (struct frame_info *frame, unsigned long inst) | |
560 | { | |
561 | int register_number; | |
562 | int register_value; | |
563 | static const int register_numbers[8] = { -1, 16, 17, 18, 1, 2, 0, -1 }; | |
564 | ||
565 | register_number = register_numbers[(inst >> 29) & 7]; | |
566 | if (register_number == -1) | |
567 | return 1; | |
568 | ||
569 | register_value = get_frame_register_signed (frame, register_number); | |
570 | if ((inst & 0x10000000) != 0) | |
571 | return register_value == 0; | |
572 | return register_value != 0; | |
573 | } | |
574 | ||
575 | /* Get the register number by decoding raw bits REG, SIDE, and CROSSPATH in | |
576 | instruction. */ | |
577 | ||
578 | static int | |
579 | tic6x_register_number (int reg, int side, int crosspath) | |
580 | { | |
581 | int r = (reg & 15) | ((crosspath ^ side) << 4); | |
582 | if ((reg & 16) != 0) /* A16 - A31, B16 - B31 */ | |
583 | r += 37; | |
584 | return r; | |
585 | } | |
586 | ||
587 | static int | |
588 | tic6x_extract_signed_field (int value, int low_bit, int bits) | |
589 | { | |
590 | int mask = (1 << bits) - 1; | |
591 | int r = (value >> low_bit) & mask; | |
592 | if ((r & (1 << (bits - 1))) != 0) | |
593 | r -= mask + 1; | |
594 | return r; | |
595 | } | |
596 | ||
597 | /* Determine where to set a single step breakpoint. */ | |
598 | ||
599 | static CORE_ADDR | |
600 | tic6x_get_next_pc (struct frame_info *frame, CORE_ADDR pc) | |
601 | { | |
602 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
603 | unsigned long inst; | |
8cd64e00 YQ |
604 | int register_number; |
605 | int last = 0; | |
606 | ||
607 | do | |
608 | { | |
609 | inst = tic6x_fetch_instruction (gdbarch, pc); | |
610 | ||
611 | last = !(inst & 1); | |
612 | ||
613 | if (inst == TIC6X_INST_SWE) | |
614 | { | |
615 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
616 | ||
617 | if (tdep->syscall_next_pc != NULL) | |
618 | return tdep->syscall_next_pc (frame); | |
619 | } | |
620 | ||
621 | if (tic6x_condition_true (frame, inst)) | |
622 | { | |
623 | if ((inst & 0x0000007c) == 0x00000010) | |
624 | { | |
625 | /* B with displacement */ | |
626 | pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1); | |
627 | pc += tic6x_extract_signed_field (inst, 7, 21) << 2; | |
628 | break; | |
629 | } | |
630 | if ((inst & 0x0f83effc) == 0x00000360) | |
631 | { | |
632 | /* B with register */ | |
633 | ||
634 | register_number = tic6x_register_number ((inst >> 18) & 0x1f, | |
635 | INST_S_BIT (inst), | |
636 | INST_X_BIT (inst)); | |
637 | pc = get_frame_register_unsigned (frame, register_number); | |
638 | break; | |
639 | } | |
640 | if ((inst & 0x00001ffc) == 0x00001020) | |
641 | { | |
642 | /* BDEC */ | |
643 | register_number = tic6x_register_number ((inst >> 23) & 0x1f, | |
644 | INST_S_BIT (inst), 0); | |
645 | if (get_frame_register_signed (frame, register_number) >= 0) | |
646 | { | |
647 | pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1); | |
648 | pc += tic6x_extract_signed_field (inst, 7, 10) << 2; | |
649 | } | |
650 | break; | |
651 | } | |
652 | if ((inst & 0x00001ffc) == 0x00000120) | |
653 | { | |
654 | /* BNOP with displacement */ | |
655 | pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1); | |
656 | pc += tic6x_extract_signed_field (inst, 16, 12) << 2; | |
657 | break; | |
658 | } | |
659 | if ((inst & 0x0f830ffe) == 0x00800362) | |
660 | { | |
661 | /* BNOP with register */ | |
662 | register_number = tic6x_register_number ((inst >> 18) & 0x1f, | |
663 | 1, INST_X_BIT (inst)); | |
664 | pc = get_frame_register_unsigned (frame, register_number); | |
665 | break; | |
666 | } | |
667 | if ((inst & 0x00001ffc) == 0x00000020) | |
668 | { | |
669 | /* BPOS */ | |
670 | register_number = tic6x_register_number ((inst >> 23) & 0x1f, | |
671 | INST_S_BIT (inst), 0); | |
672 | if (get_frame_register_signed (frame, register_number) >= 0) | |
673 | { | |
674 | pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1); | |
675 | pc += tic6x_extract_signed_field (inst, 13, 10) << 2; | |
676 | } | |
677 | break; | |
678 | } | |
679 | if ((inst & 0xf000007c) == 0x10000010) | |
680 | { | |
681 | /* CALLP */ | |
682 | pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1); | |
683 | pc += tic6x_extract_signed_field (inst, 7, 21) << 2; | |
684 | break; | |
685 | } | |
686 | } | |
687 | pc += TIC6X_OPCODE_SIZE; | |
688 | } | |
689 | while (!last); | |
690 | return pc; | |
691 | } | |
692 | ||
693 | /* This is the implementation of gdbarch method software_single_step. */ | |
694 | ||
693be288 | 695 | static int |
8cd64e00 YQ |
696 | tic6x_software_single_step (struct frame_info *frame) |
697 | { | |
698 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
699 | struct address_space *aspace = get_frame_address_space (frame); | |
700 | CORE_ADDR next_pc = tic6x_get_next_pc (frame, get_frame_pc (frame)); | |
701 | ||
702 | insert_single_step_breakpoint (gdbarch, aspace, next_pc); | |
703 | ||
704 | return 1; | |
705 | } | |
706 | ||
707 | /* This is the implementation of gdbarch method frame_align. */ | |
708 | ||
709 | static CORE_ADDR | |
710 | tic6x_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
711 | { | |
712 | return align_down (addr, 8); | |
713 | } | |
714 | ||
8cd64e00 YQ |
715 | /* Given a return value in REGCACHE with a type VALTYPE, extract and copy its |
716 | value into VALBUF. */ | |
717 | ||
718 | static void | |
719 | tic6x_extract_return_value (struct type *valtype, struct regcache *regcache, | |
720 | enum bfd_endian byte_order, gdb_byte *valbuf) | |
721 | { | |
722 | int len = TYPE_LENGTH (valtype); | |
723 | ||
724 | /* pointer types are returned in register A4, | |
725 | up to 32-bit types in A4 | |
726 | up to 64-bit types in A5:A4 */ | |
727 | if (len <= 4) | |
728 | { | |
729 | /* In big-endian, | |
730 | - one-byte structure or union occupies the LSB of single even register. | |
731 | - for two-byte structure or union, the first byte occupies byte 1 of | |
732 | register and the second byte occupies byte 0. | |
733 | so, we read the contents in VAL from the LSBs of register. */ | |
734 | if (len < 3 && byte_order == BFD_ENDIAN_BIG) | |
735 | regcache_cooked_read_part (regcache, TIC6X_A4_REGNUM, 4 - len, len, | |
736 | valbuf); | |
737 | else | |
738 | regcache_cooked_read (regcache, TIC6X_A4_REGNUM, valbuf); | |
739 | } | |
740 | else if (len <= 8) | |
741 | { | |
742 | /* For a 5-8 byte structure or union in big-endian, the first byte | |
743 | occupies byte 3 (the MSB) of the upper (odd) register and the | |
744 | remaining bytes fill the decreasingly significant bytes. 5-7 | |
745 | byte structures or unions have padding in the LSBs of the | |
746 | lower (even) register. */ | |
747 | if (byte_order == BFD_ENDIAN_BIG) | |
748 | { | |
749 | regcache_cooked_read (regcache, TIC6X_A4_REGNUM, valbuf + 4); | |
750 | regcache_cooked_read (regcache, TIC6X_A5_REGNUM, valbuf); | |
751 | } | |
752 | else | |
753 | { | |
754 | regcache_cooked_read (regcache, TIC6X_A4_REGNUM, valbuf); | |
755 | regcache_cooked_read (regcache, TIC6X_A5_REGNUM, valbuf + 4); | |
756 | } | |
757 | } | |
758 | } | |
759 | ||
760 | /* Write into appropriate registers a function return value | |
761 | of type TYPE, given in virtual format. */ | |
762 | ||
763 | static void | |
764 | tic6x_store_return_value (struct type *valtype, struct regcache *regcache, | |
765 | enum bfd_endian byte_order, const gdb_byte *valbuf) | |
766 | { | |
767 | int len = TYPE_LENGTH (valtype); | |
768 | ||
769 | /* return values of up to 8 bytes are returned in A5:A4 */ | |
770 | ||
771 | if (len <= 4) | |
772 | { | |
773 | if (len < 3 && byte_order == BFD_ENDIAN_BIG) | |
774 | regcache_cooked_write_part (regcache, TIC6X_A4_REGNUM, 4 - len, len, | |
775 | valbuf); | |
776 | else | |
777 | regcache_cooked_write (regcache, TIC6X_A4_REGNUM, valbuf); | |
778 | } | |
779 | else if (len <= 8) | |
780 | { | |
781 | if (byte_order == BFD_ENDIAN_BIG) | |
782 | { | |
783 | regcache_cooked_write (regcache, TIC6X_A4_REGNUM, valbuf + 4); | |
784 | regcache_cooked_write (regcache, TIC6X_A5_REGNUM, valbuf); | |
785 | } | |
786 | else | |
787 | { | |
788 | regcache_cooked_write (regcache, TIC6X_A4_REGNUM, valbuf); | |
789 | regcache_cooked_write (regcache, TIC6X_A5_REGNUM, valbuf + 4); | |
790 | } | |
791 | } | |
792 | } | |
793 | ||
794 | /* This is the implementation of gdbarch method return_value. */ | |
795 | ||
796 | static enum return_value_convention | |
6a3a010b | 797 | tic6x_return_value (struct gdbarch *gdbarch, struct value *function, |
8cd64e00 YQ |
798 | struct type *type, struct regcache *regcache, |
799 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
800 | { | |
18648a37 YQ |
801 | /* In C++, when function returns an object, even its size is small |
802 | enough, it stii has to be passed via reference, pointed by register | |
803 | A3. */ | |
804 | if (current_language->la_language == language_cplus) | |
805 | { | |
806 | if (type != NULL) | |
807 | { | |
f168693b | 808 | type = check_typedef (type); |
18648a37 YQ |
809 | if (language_pass_by_reference (type)) |
810 | return RETURN_VALUE_STRUCT_CONVENTION; | |
811 | } | |
812 | } | |
813 | ||
8cd64e00 YQ |
814 | if (TYPE_LENGTH (type) > 8) |
815 | return RETURN_VALUE_STRUCT_CONVENTION; | |
816 | ||
817 | if (readbuf) | |
818 | tic6x_extract_return_value (type, regcache, | |
819 | gdbarch_byte_order (gdbarch), readbuf); | |
820 | if (writebuf) | |
821 | tic6x_store_return_value (type, regcache, | |
822 | gdbarch_byte_order (gdbarch), writebuf); | |
823 | ||
824 | return RETURN_VALUE_REGISTER_CONVENTION; | |
825 | } | |
826 | ||
827 | /* This is the implementation of gdbarch method dummy_id. */ | |
828 | ||
829 | static struct frame_id | |
830 | tic6x_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
831 | { | |
832 | return frame_id_build | |
833 | (get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM), | |
834 | get_frame_pc (this_frame)); | |
835 | } | |
836 | ||
837 | /* Get the alignment requirement of TYPE. */ | |
838 | ||
839 | static int | |
840 | tic6x_arg_type_alignment (struct type *type) | |
841 | { | |
842 | int len = TYPE_LENGTH (check_typedef (type)); | |
843 | enum type_code typecode = TYPE_CODE (check_typedef (type)); | |
844 | ||
845 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
846 | { | |
847 | /* The stack alignment of a structure (and union) passed by value is the | |
848 | smallest power of two greater than or equal to its size. | |
849 | This cannot exceed 8 bytes, which is the largest allowable size for | |
850 | a structure passed by value. */ | |
851 | ||
852 | if (len <= 2) | |
853 | return len; | |
854 | else if (len <= 4) | |
855 | return 4; | |
856 | else if (len <= 8) | |
857 | return 8; | |
858 | else | |
859 | gdb_assert_not_reached ("unexpected length of data"); | |
860 | } | |
861 | else | |
862 | { | |
863 | if (len <= 4) | |
864 | return 4; | |
865 | else if (len == 8) | |
866 | { | |
867 | if (typecode == TYPE_CODE_COMPLEX) | |
868 | return 4; | |
869 | else | |
870 | return 8; | |
871 | } | |
872 | else if (len == 16) | |
873 | { | |
874 | if (typecode == TYPE_CODE_COMPLEX) | |
875 | return 8; | |
876 | else | |
877 | return 16; | |
878 | } | |
879 | else | |
880 | internal_error (__FILE__, __LINE__, _("unexpected length %d of type"), | |
881 | len); | |
882 | } | |
883 | } | |
884 | ||
885 | /* This is the implementation of gdbarch method push_dummy_call. */ | |
886 | ||
887 | static CORE_ADDR | |
888 | tic6x_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
889 | struct regcache *regcache, CORE_ADDR bp_addr, | |
890 | int nargs, struct value **args, CORE_ADDR sp, | |
891 | int struct_return, CORE_ADDR struct_addr) | |
892 | { | |
893 | int argreg = 0; | |
894 | int argnum; | |
8cd64e00 YQ |
895 | int stack_offset = 4; |
896 | int references_offset = 4; | |
897 | CORE_ADDR func_addr = find_function_addr (function, NULL); | |
898 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
899 | struct type *func_type = value_type (function); | |
900 | /* The first arg passed on stack. Mostly the first 10 args are passed by | |
901 | registers. */ | |
902 | int first_arg_on_stack = 10; | |
8cd64e00 | 903 | |
8cd64e00 YQ |
904 | /* Set the return address register to point to the entry point of |
905 | the program, where a breakpoint lies in wait. */ | |
906 | regcache_cooked_write_unsigned (regcache, TIC6X_RA_REGNUM, bp_addr); | |
907 | ||
908 | /* The caller must pass an argument in A3 containing a destination address | |
909 | for the returned value. The callee returns the object by copying it to | |
910 | the address in A3. */ | |
911 | if (struct_return) | |
912 | regcache_cooked_write_unsigned (regcache, 3, struct_addr); | |
8cd64e00 YQ |
913 | |
914 | /* Determine the type of this function. */ | |
915 | func_type = check_typedef (func_type); | |
916 | if (TYPE_CODE (func_type) == TYPE_CODE_PTR) | |
917 | func_type = check_typedef (TYPE_TARGET_TYPE (func_type)); | |
918 | ||
919 | gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC | |
920 | || TYPE_CODE (func_type) == TYPE_CODE_METHOD); | |
921 | ||
922 | /* For a variadic C function, the last explicitly declared argument and all | |
923 | remaining arguments are passed on the stack. */ | |
924 | if (TYPE_VARARGS (func_type)) | |
925 | first_arg_on_stack = TYPE_NFIELDS (func_type) - 1; | |
926 | ||
18648a37 YQ |
927 | /* Now make space on the stack for the args. */ |
928 | for (argnum = 0; argnum < nargs; argnum++) | |
8cd64e00 YQ |
929 | { |
930 | int len = align_up (TYPE_LENGTH (value_type (args[argnum])), 4); | |
931 | if (argnum >= 10 - argreg) | |
932 | references_offset += len; | |
933 | stack_offset += len; | |
934 | } | |
935 | sp -= stack_offset; | |
936 | /* SP should be 8-byte aligned, see C6000 ABI section 4.4.1 | |
937 | Stack Alignment. */ | |
938 | sp = align_down (sp, 8); | |
939 | stack_offset = 4; | |
940 | ||
941 | /* Now load as many as possible of the first arguments into | |
942 | registers, and push the rest onto the stack. Loop through args | |
943 | from first to last. */ | |
18648a37 | 944 | for (argnum = 0; argnum < nargs; argnum++) |
8cd64e00 YQ |
945 | { |
946 | const gdb_byte *val; | |
947 | struct value *arg = args[argnum]; | |
948 | struct type *arg_type = check_typedef (value_type (arg)); | |
949 | int len = TYPE_LENGTH (arg_type); | |
950 | enum type_code typecode = TYPE_CODE (arg_type); | |
951 | ||
952 | val = value_contents (arg); | |
953 | ||
954 | /* Copy the argument to general registers or the stack in | |
955 | register-sized pieces. */ | |
956 | if (argreg < first_arg_on_stack) | |
957 | { | |
958 | if (len <= 4) | |
959 | { | |
960 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
961 | { | |
962 | /* In big-endian, | |
963 | - one-byte structure or union occupies the LSB of single | |
964 | even register. | |
965 | - for two-byte structure or union, the first byte | |
966 | occupies byte 1 of register and the second byte occupies | |
967 | byte 0. | |
968 | so, we write the contents in VAL to the lsp of | |
969 | register. */ | |
970 | if (len < 3 && byte_order == BFD_ENDIAN_BIG) | |
971 | regcache_cooked_write_part (regcache, arg_regs[argreg], | |
972 | 4 - len, len, val); | |
973 | else | |
974 | regcache_cooked_write (regcache, arg_regs[argreg], val); | |
975 | } | |
976 | else | |
977 | { | |
978 | /* The argument is being passed by value in a single | |
979 | register. */ | |
980 | CORE_ADDR regval = extract_unsigned_integer (val, len, | |
981 | byte_order); | |
982 | ||
983 | regcache_cooked_write_unsigned (regcache, arg_regs[argreg], | |
984 | regval); | |
985 | } | |
986 | } | |
987 | else | |
988 | { | |
989 | if (len <= 8) | |
990 | { | |
991 | if (typecode == TYPE_CODE_STRUCT | |
992 | || typecode == TYPE_CODE_UNION) | |
993 | { | |
994 | /* For a 5-8 byte structure or union in big-endian, the | |
995 | first byte occupies byte 3 (the MSB) of the upper (odd) | |
996 | register and the remaining bytes fill the decreasingly | |
997 | significant bytes. 5-7 byte structures or unions have | |
998 | padding in the LSBs of the lower (even) register. */ | |
999 | if (byte_order == BFD_ENDIAN_BIG) | |
1000 | { | |
1001 | regcache_cooked_write (regcache, | |
1002 | arg_regs[argreg] + 1, val); | |
1003 | regcache_cooked_write_part (regcache, | |
1004 | arg_regs[argreg], 0, | |
1005 | len - 4, val + 4); | |
1006 | } | |
1007 | else | |
1008 | { | |
1009 | regcache_cooked_write (regcache, arg_regs[argreg], | |
1010 | val); | |
1011 | regcache_cooked_write_part (regcache, | |
1012 | arg_regs[argreg] + 1, 0, | |
1013 | len - 4, val + 4); | |
1014 | } | |
1015 | } | |
1016 | else | |
1017 | { | |
1018 | /* The argument is being passed by value in a pair of | |
1019 | registers. */ | |
1020 | ULONGEST regval = extract_unsigned_integer (val, len, | |
1021 | byte_order); | |
1022 | ||
1023 | regcache_cooked_write_unsigned (regcache, | |
1024 | arg_regs[argreg], | |
1025 | regval); | |
1026 | regcache_cooked_write_unsigned (regcache, | |
1027 | arg_regs[argreg] + 1, | |
1028 | regval >> 32); | |
1029 | } | |
1030 | } | |
1031 | else | |
1032 | { | |
1033 | /* The argument is being passed by reference in a single | |
1034 | register. */ | |
1035 | CORE_ADDR addr; | |
1036 | ||
1037 | /* It is not necessary to adjust REFERENCES_OFFSET to | |
1038 | 8-byte aligned in some cases, in which 4-byte alignment | |
1039 | is sufficient. For simplicity, we adjust | |
1040 | REFERENCES_OFFSET to 8-byte aligned. */ | |
1041 | references_offset = align_up (references_offset, 8); | |
1042 | ||
1043 | addr = sp + references_offset; | |
1044 | write_memory (addr, val, len); | |
1045 | references_offset += align_up (len, 4); | |
1046 | regcache_cooked_write_unsigned (regcache, arg_regs[argreg], | |
1047 | addr); | |
1048 | } | |
1049 | } | |
1050 | argreg++; | |
1051 | } | |
1052 | else | |
1053 | { | |
1054 | /* The argument is being passed on the stack. */ | |
1055 | CORE_ADDR addr; | |
1056 | ||
1057 | /* There are six different cases of alignment, and these rules can | |
1058 | be found in tic6x_arg_type_alignment: | |
1059 | ||
1060 | 1) 4-byte aligned if size is less than or equal to 4 byte, such | |
1061 | as short, int, struct, union etc. | |
1062 | 2) 8-byte aligned if size is less than or equal to 8-byte, such | |
1063 | as double, long long, | |
1064 | 3) 4-byte aligned if it is of type _Complex float, even its size | |
1065 | is 8-byte. | |
1066 | 4) 8-byte aligned if it is of type _Complex double or _Complex | |
1067 | long double, even its size is 16-byte. Because, the address of | |
1068 | variable is passed as reference. | |
1069 | 5) struct and union larger than 8-byte are passed by reference, so | |
1070 | it is 4-byte aligned. | |
1071 | 6) struct and union of size between 4 byte and 8 byte varies. | |
1072 | alignment of struct variable is the alignment of its first field, | |
1073 | while alignment of union variable is the max of all its fields' | |
1074 | alignment. */ | |
1075 | ||
1076 | if (len <= 4) | |
1077 | ; /* Default is 4-byte aligned. Nothing to be done. */ | |
1078 | else if (len <= 8) | |
1079 | stack_offset = align_up (stack_offset, | |
1080 | tic6x_arg_type_alignment (arg_type)); | |
1081 | else if (len == 16) | |
1082 | { | |
1083 | /* _Complex double or _Complex long double */ | |
1084 | if (typecode == TYPE_CODE_COMPLEX) | |
1085 | { | |
1086 | /* The argument is being passed by reference on stack. */ | |
1087 | CORE_ADDR addr; | |
1088 | references_offset = align_up (references_offset, 8); | |
1089 | ||
1090 | addr = sp + references_offset; | |
1091 | /* Store variable on stack. */ | |
1092 | write_memory (addr, val, len); | |
1093 | ||
1094 | references_offset += align_up (len, 4); | |
1095 | ||
1096 | /* Pass the address of variable on stack as reference. */ | |
1097 | store_unsigned_integer ((gdb_byte *) val, 4, byte_order, | |
1098 | addr); | |
1099 | len = 4; | |
1100 | ||
1101 | } | |
1102 | else | |
1103 | internal_error (__FILE__, __LINE__, | |
1104 | _("unexpected type %d of arg %d"), | |
1105 | typecode, argnum); | |
1106 | } | |
1107 | else | |
1108 | internal_error (__FILE__, __LINE__, | |
1109 | _("unexpected length %d of arg %d"), len, argnum); | |
1110 | ||
1111 | addr = sp + stack_offset; | |
1112 | write_memory (addr, val, len); | |
1113 | stack_offset += align_up (len, 4); | |
1114 | } | |
1115 | } | |
1116 | ||
1117 | regcache_cooked_write_signed (regcache, TIC6X_SP_REGNUM, sp); | |
1118 | ||
1119 | /* Return adjusted stack pointer. */ | |
1120 | return sp; | |
1121 | } | |
1122 | ||
c9cf6e20 | 1123 | /* This is the implementation of gdbarch method stack_frame_destroyed_p. */ |
8cd64e00 YQ |
1124 | |
1125 | static int | |
c9cf6e20 | 1126 | tic6x_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
8cd64e00 YQ |
1127 | { |
1128 | unsigned long inst = tic6x_fetch_instruction (gdbarch, pc); | |
1129 | /* Normally, the epilogue is composed by instruction `b .S2 b3'. */ | |
1130 | if ((inst & 0x0f83effc) == 0x360) | |
1131 | { | |
1132 | unsigned int src2 = tic6x_register_number ((inst >> 18) & 0x1f, | |
1133 | INST_S_BIT (inst), | |
1134 | INST_X_BIT (inst)); | |
1135 | if (src2 == TIC6X_RA_REGNUM) | |
1136 | return 1; | |
1137 | } | |
1138 | ||
1139 | return 0; | |
1140 | } | |
1141 | ||
1142 | /* This is the implementation of gdbarch method get_longjmp_target. */ | |
1143 | ||
1144 | static int | |
1145 | tic6x_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) | |
1146 | { | |
1147 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
1148 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1149 | CORE_ADDR jb_addr; | |
e362b510 | 1150 | gdb_byte buf[4]; |
8cd64e00 YQ |
1151 | |
1152 | /* JMP_BUF is passed by reference in A4. */ | |
1153 | jb_addr = get_frame_register_unsigned (frame, 4); | |
1154 | ||
1155 | /* JMP_BUF contains 13 elements of type int, and return address is stored | |
1156 | in the last slot. */ | |
1157 | if (target_read_memory (jb_addr + 12 * 4, buf, 4)) | |
1158 | return 0; | |
1159 | ||
1160 | *pc = extract_unsigned_integer (buf, 4, byte_order); | |
1161 | ||
1162 | return 1; | |
1163 | } | |
1164 | ||
18648a37 YQ |
1165 | /* This is the implementation of gdbarch method |
1166 | return_in_first_hidden_param_p. */ | |
1167 | ||
1168 | static int | |
1169 | tic6x_return_in_first_hidden_param_p (struct gdbarch *gdbarch, | |
1170 | struct type *type) | |
1171 | { | |
1172 | return 0; | |
1173 | } | |
1174 | ||
8cd64e00 YQ |
1175 | static struct gdbarch * |
1176 | tic6x_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1177 | { | |
1178 | struct gdbarch *gdbarch; | |
1179 | struct gdbarch_tdep *tdep; | |
1180 | struct tdesc_arch_data *tdesc_data = NULL; | |
1181 | const struct target_desc *tdesc = info.target_desc; | |
1182 | int has_gp = 0; | |
1183 | ||
1184 | /* Check any target description for validity. */ | |
1185 | if (tdesc_has_registers (tdesc)) | |
1186 | { | |
1187 | const struct tdesc_feature *feature; | |
1188 | int valid_p, i; | |
1189 | ||
1190 | feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.core"); | |
1191 | ||
1192 | if (feature == NULL) | |
1193 | return NULL; | |
1194 | ||
1195 | tdesc_data = tdesc_data_alloc (); | |
1196 | ||
1197 | valid_p = 1; | |
1198 | for (i = 0; i < 32; i++) /* A0 - A15, B0 - B15 */ | |
1199 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
1200 | tic6x_register_names[i]); | |
1201 | ||
1202 | /* CSR */ | |
1203 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, | |
1204 | tic6x_register_names[TIC6X_CSR_REGNUM]); | |
1205 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, | |
1206 | tic6x_register_names[TIC6X_PC_REGNUM]); | |
1207 | ||
1208 | if (!valid_p) | |
1209 | { | |
1210 | tdesc_data_cleanup (tdesc_data); | |
1211 | return NULL; | |
1212 | } | |
1213 | ||
1214 | feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.gp"); | |
1215 | if (feature) | |
1216 | { | |
1217 | int j = 0; | |
1218 | static const char *const gp[] = | |
1219 | { | |
1220 | "A16", "A17", "A18", "A19", "A20", "A21", "A22", "A23", | |
1221 | "A24", "A25", "A26", "A27", "A28", "A29", "A30", "A31", | |
1222 | "B16", "B17", "B18", "B19", "B20", "B21", "B22", "B23", | |
1223 | "B24", "B25", "B26", "B27", "B28", "B29", "B30", "B31", | |
1224 | }; | |
1225 | ||
1226 | has_gp = 1; | |
1227 | valid_p = 1; | |
1228 | for (j = 0; j < 32; j++) /* A16 - A31, B16 - B31 */ | |
1229 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, | |
1230 | gp[j]); | |
1231 | ||
1232 | if (!valid_p) | |
1233 | { | |
1234 | tdesc_data_cleanup (tdesc_data); | |
1235 | return NULL; | |
1236 | } | |
1237 | } | |
1238 | ||
1239 | feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.c6xp"); | |
1240 | if (feature) | |
1241 | { | |
1242 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "TSR"); | |
1243 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "ILC"); | |
1244 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "RILC"); | |
1245 | ||
1246 | if (!valid_p) | |
1247 | { | |
1248 | tdesc_data_cleanup (tdesc_data); | |
1249 | return NULL; | |
1250 | } | |
1251 | } | |
1252 | ||
1253 | } | |
1254 | ||
1255 | /* Find a candidate among extant architectures. */ | |
1256 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
1257 | arches != NULL; | |
1258 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
1259 | { | |
1260 | tdep = gdbarch_tdep (arches->gdbarch); | |
1261 | ||
1262 | if (has_gp != tdep->has_gp) | |
1263 | continue; | |
1264 | ||
1265 | if (tdep && tdep->breakpoint) | |
1266 | return arches->gdbarch; | |
1267 | } | |
1268 | ||
8d749320 | 1269 | tdep = XCNEW (struct gdbarch_tdep); |
8cd64e00 YQ |
1270 | |
1271 | tdep->has_gp = has_gp; | |
1272 | gdbarch = gdbarch_alloc (&info, tdep); | |
1273 | ||
1274 | /* Data type sizes. */ | |
1275 | set_gdbarch_ptr_bit (gdbarch, 32); | |
1276 | set_gdbarch_addr_bit (gdbarch, 32); | |
1277 | set_gdbarch_short_bit (gdbarch, 16); | |
1278 | set_gdbarch_int_bit (gdbarch, 32); | |
1279 | set_gdbarch_long_bit (gdbarch, 32); | |
1280 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1281 | set_gdbarch_float_bit (gdbarch, 32); | |
1282 | set_gdbarch_double_bit (gdbarch, 64); | |
1283 | ||
1284 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); | |
1285 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
1286 | ||
1287 | /* The register set. */ | |
1288 | set_gdbarch_num_regs (gdbarch, TIC6X_NUM_REGS); | |
1289 | set_gdbarch_sp_regnum (gdbarch, TIC6X_SP_REGNUM); | |
1290 | set_gdbarch_pc_regnum (gdbarch, TIC6X_PC_REGNUM); | |
1291 | ||
1292 | set_gdbarch_register_name (gdbarch, tic6x_register_name); | |
1293 | set_gdbarch_register_type (gdbarch, tic6x_register_type); | |
1294 | ||
1295 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1296 | ||
1297 | set_gdbarch_skip_prologue (gdbarch, tic6x_skip_prologue); | |
1298 | set_gdbarch_breakpoint_from_pc (gdbarch, tic6x_breakpoint_from_pc); | |
1299 | ||
1300 | set_gdbarch_unwind_pc (gdbarch, tic6x_unwind_pc); | |
1301 | set_gdbarch_unwind_sp (gdbarch, tic6x_unwind_sp); | |
1302 | ||
1303 | /* Unwinding. */ | |
1304 | dwarf2_append_unwinders (gdbarch); | |
1305 | ||
1306 | frame_unwind_append_unwinder (gdbarch, &tic6x_stub_unwind); | |
1307 | frame_unwind_append_unwinder (gdbarch, &tic6x_frame_unwind); | |
195abc10 | 1308 | frame_base_set_default (gdbarch, &tic6x_frame_base); |
8cd64e00 YQ |
1309 | |
1310 | dwarf2_frame_set_init_reg (gdbarch, tic6x_dwarf2_frame_init_reg); | |
1311 | ||
1312 | /* Single stepping. */ | |
1313 | set_gdbarch_software_single_step (gdbarch, tic6x_software_single_step); | |
1314 | ||
1315 | set_gdbarch_print_insn (gdbarch, tic6x_print_insn); | |
1316 | ||
1317 | /* Call dummy code. */ | |
1318 | set_gdbarch_frame_align (gdbarch, tic6x_frame_align); | |
1319 | ||
8cd64e00 YQ |
1320 | set_gdbarch_return_value (gdbarch, tic6x_return_value); |
1321 | ||
1322 | set_gdbarch_dummy_id (gdbarch, tic6x_dummy_id); | |
1323 | ||
1324 | /* Enable inferior call support. */ | |
1325 | set_gdbarch_push_dummy_call (gdbarch, tic6x_push_dummy_call); | |
1326 | ||
1327 | set_gdbarch_get_longjmp_target (gdbarch, tic6x_get_longjmp_target); | |
1328 | ||
c9cf6e20 | 1329 | set_gdbarch_stack_frame_destroyed_p (gdbarch, tic6x_stack_frame_destroyed_p); |
8cd64e00 | 1330 | |
18648a37 YQ |
1331 | set_gdbarch_return_in_first_hidden_param_p (gdbarch, |
1332 | tic6x_return_in_first_hidden_param_p); | |
1333 | ||
8cd64e00 YQ |
1334 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1335 | gdbarch_init_osabi (info, gdbarch); | |
1336 | ||
1337 | if (tdesc_data) | |
1338 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); | |
1339 | ||
1340 | return gdbarch; | |
1341 | } | |
1342 | ||
693be288 JK |
1343 | /* -Wmissing-prototypes */ |
1344 | extern initialize_file_ftype _initialize_tic6x_tdep; | |
1345 | ||
8cd64e00 YQ |
1346 | void |
1347 | _initialize_tic6x_tdep (void) | |
1348 | { | |
1349 | register_gdbarch_init (bfd_arch_tic6x, tic6x_gdbarch_init); | |
1350 | ||
1351 | initialize_tdesc_tic6x_c64xp (); | |
1352 | initialize_tdesc_tic6x_c64x (); | |
1353 | initialize_tdesc_tic6x_c62x (); | |
1354 | } |