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8cd64e00 YQ |
1 | /* Target dependent code for GDB on TI C6x systems. |
2 | ||
3 | Copyright (C) 2010, 2011. | |
4 | Free Software Foundation, Inc. | |
5 | Contributed by Andrew Jenner <andrew@codesourcery.com> | |
6 | Contributed by Yao Qi <yao@codesourcery.com> | |
7 | ||
8 | This file is part of GDB. | |
9 | ||
10 | This program is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 3 of the License, or | |
13 | (at your option) any later version. | |
14 | ||
15 | This program is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
22 | ||
23 | #include "defs.h" | |
24 | #include "frame.h" | |
25 | #include "frame-unwind.h" | |
26 | #include "frame-base.h" | |
27 | #include "trad-frame.h" | |
28 | #include "dwarf2-frame.h" | |
29 | #include "symtab.h" | |
30 | #include "inferior.h" | |
31 | #include "gdbtypes.h" | |
32 | #include "gdbcore.h" | |
33 | #include "gdbcmd.h" | |
34 | #include "target.h" | |
35 | #include "dis-asm.h" | |
36 | #include "regcache.h" | |
37 | #include "value.h" | |
38 | #include "symfile.h" | |
39 | #include "arch-utils.h" | |
40 | #include "floatformat.h" | |
41 | #include "glibc-tdep.h" | |
42 | #include "infcall.h" | |
43 | #include "regset.h" | |
44 | #include "tramp-frame.h" | |
45 | #include "linux-tdep.h" | |
46 | #include "solib.h" | |
47 | #include "objfiles.h" | |
48 | #include "gdb_assert.h" | |
49 | #include "osabi.h" | |
50 | #include "tic6x-tdep.h" | |
51 | #include "language.h" | |
52 | #include "target-descriptions.h" | |
53 | ||
54 | #include "features/tic6x-c64xp.c" | |
55 | #include "features/tic6x-c64x.c" | |
56 | #include "features/tic6x-c62x.c" | |
57 | ||
58 | #define TIC6X_OPCODE_SIZE 4 | |
59 | #define TIC6X_FETCH_PACKET_SIZE 32 | |
60 | ||
61 | #define INST_S_BIT(INST) ((INST >> 1) & 1) | |
62 | #define INST_X_BIT(INST) ((INST >> 12) & 1) | |
63 | ||
85661b1e YQ |
64 | const gdb_byte tic6x_bkpt_illegal_opcode_be[] = { 0x56, 0x45, 0x43, 0x14 }; |
65 | const gdb_byte tic6x_bkpt_illegal_opcode_le[] = { 0x14, 0x43, 0x45, 0x56 }; | |
66 | ||
8cd64e00 YQ |
67 | struct tic6x_unwind_cache |
68 | { | |
69 | /* The frame's base, optionally used by the high-level debug info. */ | |
70 | CORE_ADDR base; | |
71 | ||
72 | /* The previous frame's inner most stack address. Used as this | |
73 | frame ID's stack_addr. */ | |
74 | CORE_ADDR cfa; | |
75 | ||
76 | /* The address of the first instruction in this function */ | |
77 | CORE_ADDR pc; | |
78 | ||
79 | /* Which register holds the return address for the frame. */ | |
80 | int return_regnum; | |
81 | ||
82 | /* The offset of register saved on stack. If register is not saved, the | |
83 | corresponding element is -1. */ | |
84 | CORE_ADDR reg_saved[TIC6X_NUM_CORE_REGS]; | |
85 | }; | |
86 | ||
87 | ||
88 | /* Name of TI C6x core registers. */ | |
89 | static const char *const tic6x_register_names[] = | |
90 | { | |
91 | "A0", "A1", "A2", "A3", /* 0 1 2 3 */ | |
92 | "A4", "A5", "A6", "A7", /* 4 5 6 7 */ | |
93 | "A8", "A9", "A10", "A11", /* 8 9 10 11 */ | |
94 | "A12", "A13", "A14", "A15", /* 12 13 14 15 */ | |
95 | "B0", "B1", "B2", "B3", /* 16 17 18 19 */ | |
96 | "B4", "B5", "B6", "B7", /* 20 21 22 23 */ | |
97 | "B8", "B9", "B10", "B11", /* 24 25 26 27 */ | |
98 | "B12", "B13", "B14", "B15", /* 28 29 30 31 */ | |
99 | "CSR", "PC", /* 32 33 */ | |
100 | }; | |
101 | ||
102 | /* This array maps the arguments to the register number which passes argument | |
103 | in function call according to C6000 ELF ABI. */ | |
104 | static const int arg_regs[] = { 4, 20, 6, 22, 8, 24, 10, 26, 12, 28 }; | |
105 | ||
106 | /* This is the implementation of gdbarch method register_name. */ | |
107 | ||
108 | static const char * | |
109 | tic6x_register_name (struct gdbarch *gdbarch, int regno) | |
110 | { | |
111 | if (regno < 0) | |
112 | return NULL; | |
113 | ||
114 | if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) | |
115 | return tdesc_register_name (gdbarch, regno); | |
116 | else if (regno >= ARRAY_SIZE (tic6x_register_names)) | |
117 | return ""; | |
118 | else | |
119 | return tic6x_register_names[regno]; | |
120 | } | |
121 | ||
122 | /* This is the implementation of gdbarch method register_type. */ | |
123 | ||
124 | static struct type * | |
125 | tic6x_register_type (struct gdbarch *gdbarch, int regno) | |
126 | { | |
127 | ||
128 | if (regno == TIC6X_PC_REGNUM) | |
129 | return builtin_type (gdbarch)->builtin_func_ptr; | |
130 | else | |
131 | return builtin_type (gdbarch)->builtin_uint32; | |
132 | } | |
133 | ||
134 | static void | |
135 | tic6x_setup_default (struct tic6x_unwind_cache *cache) | |
136 | { | |
137 | int i; | |
138 | ||
139 | for (i = 0; i < TIC6X_NUM_CORE_REGS; i++) | |
140 | cache->reg_saved[i] = -1; | |
141 | } | |
142 | ||
143 | static unsigned long tic6x_fetch_instruction (struct gdbarch *, CORE_ADDR); | |
144 | static int tic6x_register_number (int reg, int side, int crosspath); | |
145 | ||
146 | /* Do a full analysis of the prologue at START_PC and update CACHE accordingly. | |
147 | Bail out early if CURRENT_PC is reached. Returns the address of the first | |
148 | instruction after the prologue. */ | |
149 | ||
150 | CORE_ADDR | |
151 | tic6x_analyze_prologue (struct gdbarch *gdbarch, const CORE_ADDR start_pc, | |
152 | const CORE_ADDR current_pc, | |
153 | struct tic6x_unwind_cache *cache, | |
154 | struct frame_info *this_frame) | |
155 | { | |
156 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
157 | unsigned long inst; | |
158 | unsigned int src_reg, base_reg, dst_reg; | |
159 | int i; | |
160 | CORE_ADDR pc = start_pc; | |
161 | CORE_ADDR return_pc = start_pc; | |
162 | int frame_base_offset_to_sp = 0; | |
163 | /* Counter of non-stw instructions after first insn ` sub sp, xxx, sp'. */ | |
164 | int non_stw_insn_counter = 0; | |
165 | ||
166 | if (start_pc >= current_pc) | |
167 | return_pc = current_pc; | |
168 | ||
169 | cache->base = 0; | |
170 | ||
171 | /* The landmarks in prologue is one or two SUB instructions to SP. | |
172 | Instructions on setting up dsbt are in the last part of prologue, if | |
173 | needed. In maxim, prologue can be divided to three parts by two | |
174 | `sub sp, xx, sp' insns. */ | |
175 | ||
176 | /* Step 1: Look for the 1st and 2nd insn `sub sp, xx, sp', in which, the | |
177 | 2nd one is optional. */ | |
178 | while (pc < current_pc) | |
179 | { | |
180 | int offset = 0; | |
181 | ||
182 | unsigned long inst = tic6x_fetch_instruction (gdbarch, pc); | |
183 | ||
184 | if ((inst & 0x1ffc) == 0x1dc0 || (inst & 0x1ffc) == 0x1bc0 | |
185 | || (inst & 0x0ffc) == 0x9c0) | |
186 | { | |
187 | /* SUBAW/SUBAH/SUB, and src1 is ucst 5. */ | |
188 | unsigned int src2 = tic6x_register_number ((inst >> 18) & 0x1f, | |
189 | INST_S_BIT (inst), 0); | |
190 | unsigned int dst = tic6x_register_number ((inst >> 23) & 0x1f, | |
191 | INST_S_BIT (inst), 0); | |
192 | ||
193 | if (src2 == TIC6X_SP_REGNUM && dst == TIC6X_SP_REGNUM) | |
194 | { | |
195 | /* Extract const from insn SUBAW/SUBAH/SUB, and translate it to | |
196 | offset. The constant offset is decoded in bit 13-17 in all | |
197 | these three kinds of instructions. */ | |
198 | unsigned int ucst5 = (inst >> 13) & 0x1f; | |
199 | ||
200 | if ((inst & 0x1ffc) == 0x1dc0) /* SUBAW */ | |
201 | frame_base_offset_to_sp += ucst5 << 2; | |
202 | else if ((inst & 0x1ffc) == 0x1bc0) /* SUBAH */ | |
203 | frame_base_offset_to_sp += ucst5 << 1; | |
204 | else if ((inst & 0x0ffc) == 0x9c0) /* SUB */ | |
205 | frame_base_offset_to_sp += ucst5; | |
206 | else | |
207 | gdb_assert_not_reached ("unexpected instruction"); | |
208 | ||
209 | return_pc = pc + 4; | |
210 | } | |
211 | } | |
212 | else if ((inst & 0x174) == 0x74) /* stw SRC, *+b15(uconst) */ | |
213 | { | |
214 | /* The y bit determines which file base is read from. */ | |
215 | base_reg = tic6x_register_number ((inst >> 18) & 0x1f, | |
216 | (inst >> 7) & 1, 0); | |
217 | ||
218 | if (base_reg == TIC6X_SP_REGNUM) | |
219 | { | |
220 | src_reg = tic6x_register_number ((inst >> 23) & 0x1f, | |
221 | INST_S_BIT (inst), 0); | |
222 | ||
223 | cache->reg_saved[src_reg] = ((inst >> 13) & 0x1f) << 2; | |
224 | ||
225 | return_pc = pc + 4; | |
226 | } | |
227 | non_stw_insn_counter = 0; | |
228 | } | |
229 | else | |
230 | { | |
231 | non_stw_insn_counter++; | |
232 | /* Following instruction sequence may be emitted in prologue: | |
233 | ||
234 | <+0>: subah .D2 b15,28,b15 | |
235 | <+4>: or .L2X 0,a4,b0 | |
236 | <+8>: || stw .D2T2 b14,*+b15(56) | |
237 | <+12>:[!b0] b .S1 0xe50e4c1c <sleep+220> | |
238 | <+16>:|| stw .D2T1 a10,*+b15(48) | |
239 | <+20>:stw .D2T2 b3,*+b15(52) | |
240 | <+24>:stw .D2T1 a4,*+b15(40) | |
241 | ||
242 | we should look forward for next instruction instead of breaking loop | |
243 | here. So far, we allow almost two sequential non-stw instructions | |
244 | in prologue. */ | |
245 | if (non_stw_insn_counter >= 2) | |
246 | break; | |
247 | } | |
248 | ||
249 | ||
250 | pc += 4; | |
251 | } | |
252 | /* Step 2: Skip insn on setting up dsbt if it is. Usually, it looks like, | |
253 | ldw .D2T2 *+b14(0),b14 */ | |
254 | inst = tic6x_fetch_instruction (gdbarch, pc); | |
255 | /* The s bit determines which file dst will be loaded into, same effect as | |
256 | other places. */ | |
257 | dst_reg = tic6x_register_number ((inst >> 23) & 0x1f, (inst >> 1) & 1, 0); | |
258 | /* The y bit (bit 7), instead of s bit, determines which file base be | |
259 | used. */ | |
260 | base_reg = tic6x_register_number ((inst >> 18) & 0x1f, (inst >> 7) & 1, 0); | |
261 | ||
262 | if ((inst & 0x164) == 0x64 /* ldw */ | |
263 | && dst_reg == TIC6X_DP_REGNUM /* dst is B14 */ | |
264 | && base_reg == TIC6X_DP_REGNUM) /* baseR is B14 */ | |
265 | { | |
266 | return_pc = pc + 4; | |
267 | } | |
268 | ||
269 | if (this_frame) | |
270 | { | |
271 | cache->base = get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM); | |
272 | ||
273 | if (cache->reg_saved[TIC6X_FP_REGNUM] != -1) | |
274 | { | |
275 | /* If the FP now holds an offset from the CFA then this is a frame | |
276 | which uses the frame pointer. */ | |
277 | ||
278 | cache->cfa = get_frame_register_unsigned (this_frame, | |
279 | TIC6X_FP_REGNUM); | |
280 | } | |
281 | else | |
282 | { | |
283 | /* FP doesn't hold an offset from the CFA. If SP still holds an | |
284 | offset from the CFA then we might be in a function which omits | |
285 | the frame pointer. */ | |
286 | ||
287 | cache->cfa = cache->base + frame_base_offset_to_sp; | |
288 | } | |
289 | } | |
290 | ||
291 | /* Adjust all the saved registers such that they contain addresses | |
292 | instead of offsets. */ | |
293 | for (i = 0; i < TIC6X_NUM_CORE_REGS; i++) | |
294 | if (cache->reg_saved[i] != -1) | |
295 | cache->reg_saved[i] = cache->base + cache->reg_saved[i]; | |
296 | ||
297 | return return_pc; | |
298 | } | |
299 | ||
300 | /* This is the implementation of gdbarch method skip_prologue. */ | |
301 | ||
302 | CORE_ADDR | |
303 | tic6x_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) | |
304 | { | |
305 | CORE_ADDR limit_pc; | |
306 | CORE_ADDR func_addr; | |
307 | struct tic6x_unwind_cache cache; | |
308 | ||
309 | /* See if we can determine the end of the prologue via the symbol table. | |
310 | If so, then return either PC, or the PC after the prologue, whichever is | |
311 | greater. */ | |
312 | if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) | |
313 | { | |
314 | CORE_ADDR post_prologue_pc | |
315 | = skip_prologue_using_sal (gdbarch, func_addr); | |
316 | if (post_prologue_pc != 0) | |
317 | return max (start_pc, post_prologue_pc); | |
318 | } | |
319 | ||
320 | /* Can't determine prologue from the symbol table, need to examine | |
321 | instructions. */ | |
322 | return tic6x_analyze_prologue (gdbarch, start_pc, (CORE_ADDR) -1, &cache, | |
323 | NULL); | |
324 | } | |
325 | ||
326 | /* This is the implementation of gdbarch method breakpiont_from_pc. */ | |
327 | ||
328 | const unsigned char* | |
329 | tic6x_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr, | |
330 | int *bp_size) | |
331 | { | |
332 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
333 | ||
334 | *bp_size = 4; | |
335 | ||
336 | if (tdep == NULL || tdep->breakpoint == NULL) | |
337 | { | |
338 | if (BFD_ENDIAN_BIG == gdbarch_byte_order_for_code (gdbarch)) | |
339 | return tic6x_bkpt_illegal_opcode_be; | |
340 | else | |
341 | return tic6x_bkpt_illegal_opcode_le; | |
342 | } | |
343 | else | |
344 | return tdep->breakpoint; | |
345 | } | |
346 | ||
347 | /* This is the implementation of gdbarch method print_insn. */ | |
348 | ||
349 | static int | |
350 | tic6x_print_insn (bfd_vma memaddr, disassemble_info *info) | |
351 | { | |
352 | return print_insn_tic6x (memaddr, info); | |
353 | } | |
354 | ||
355 | static void | |
356 | tic6x_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
357 | struct dwarf2_frame_state_reg *reg, | |
358 | struct frame_info *this_frame) | |
359 | { | |
360 | /* Mark the PC as the destination for the return address. */ | |
361 | if (regnum == gdbarch_pc_regnum (gdbarch)) | |
362 | reg->how = DWARF2_FRAME_REG_RA; | |
363 | ||
364 | /* Mark the stack pointer as the call frame address. */ | |
365 | else if (regnum == gdbarch_sp_regnum (gdbarch)) | |
366 | reg->how = DWARF2_FRAME_REG_CFA; | |
367 | ||
368 | /* The above was taken from the default init_reg in dwarf2-frame.c | |
369 | while the below is c6x specific. */ | |
370 | ||
371 | /* Callee save registers. The ABI designates A10-A15 and B10-B15 as | |
372 | callee-save. */ | |
373 | else if ((regnum >= 10 && regnum <= 15) || (regnum >= 26 && regnum <= 31)) | |
374 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
375 | else | |
376 | /* All other registers are caller-save. */ | |
377 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
378 | } | |
379 | ||
380 | /* This is the implementation of gdbarch method unwind_pc. */ | |
381 | ||
382 | static CORE_ADDR | |
383 | tic6x_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
384 | { | |
385 | gdb_byte buf[8]; | |
386 | ||
387 | frame_unwind_register (next_frame, TIC6X_PC_REGNUM, buf); | |
388 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); | |
389 | } | |
390 | ||
391 | /* This is the implementation of gdbarch method unwind_sp. */ | |
392 | ||
393 | static CORE_ADDR | |
394 | tic6x_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
395 | { | |
396 | return frame_unwind_register_unsigned (this_frame, TIC6X_SP_REGNUM); | |
397 | } | |
398 | ||
399 | ||
400 | /* Frame base handling. */ | |
401 | ||
402 | struct tic6x_unwind_cache* | |
403 | tic6x_frame_unwind_cache (struct frame_info *this_frame, | |
404 | void **this_prologue_cache) | |
405 | { | |
406 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
407 | CORE_ADDR current_pc; | |
408 | struct tic6x_unwind_cache *cache; | |
409 | int i; | |
410 | ||
411 | if (*this_prologue_cache) | |
412 | return *this_prologue_cache; | |
413 | ||
414 | cache = FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache); | |
415 | (*this_prologue_cache) = cache; | |
416 | ||
417 | cache->return_regnum = TIC6X_RA_REGNUM; | |
418 | ||
419 | tic6x_setup_default (cache); | |
420 | ||
421 | cache->pc = get_frame_func (this_frame); | |
422 | current_pc = get_frame_pc (this_frame); | |
423 | ||
424 | /* Prologue analysis does the rest... */ | |
425 | if (cache->pc != 0) | |
426 | tic6x_analyze_prologue (gdbarch, cache->pc, current_pc, cache, this_frame); | |
427 | ||
428 | return cache; | |
429 | } | |
430 | ||
431 | static void | |
432 | tic6x_frame_this_id (struct frame_info *this_frame, void **this_cache, | |
433 | struct frame_id *this_id) | |
434 | { | |
435 | struct tic6x_unwind_cache *cache = | |
436 | tic6x_frame_unwind_cache (this_frame, this_cache); | |
437 | ||
438 | /* This marks the outermost frame. */ | |
439 | if (cache->base == 0) | |
440 | return; | |
441 | ||
442 | (*this_id) = frame_id_build (cache->cfa, cache->pc); | |
443 | } | |
444 | ||
445 | static struct value * | |
446 | tic6x_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
447 | int regnum) | |
448 | { | |
449 | struct tic6x_unwind_cache *cache = | |
450 | tic6x_frame_unwind_cache (this_frame, this_cache); | |
451 | ||
452 | gdb_assert (regnum >= 0); | |
453 | ||
454 | /* The PC of the previous frame is stored in the RA register of | |
455 | the current frame. Frob regnum so that we pull the value from | |
456 | the correct place. */ | |
457 | if (regnum == TIC6X_PC_REGNUM) | |
458 | regnum = cache->return_regnum; | |
459 | ||
460 | if (regnum == TIC6X_SP_REGNUM && cache->cfa) | |
461 | return frame_unwind_got_constant (this_frame, regnum, cache->cfa); | |
462 | ||
463 | /* If we've worked out where a register is stored then load it from | |
464 | there. */ | |
465 | if (regnum < TIC6X_NUM_CORE_REGS && cache->reg_saved[regnum] != -1) | |
466 | return frame_unwind_got_memory (this_frame, regnum, | |
467 | cache->reg_saved[regnum]); | |
468 | ||
469 | return frame_unwind_got_register (this_frame, regnum, regnum); | |
470 | } | |
471 | ||
472 | static CORE_ADDR | |
473 | tic6x_frame_base_address (struct frame_info *this_frame, void **this_cache) | |
474 | { | |
475 | struct tic6x_unwind_cache *info | |
476 | = tic6x_frame_unwind_cache (this_frame, this_cache); | |
477 | return info->base; | |
478 | } | |
479 | ||
480 | static const struct frame_unwind tic6x_frame_unwind = | |
481 | { | |
482 | NORMAL_FRAME, | |
483 | default_frame_unwind_stop_reason, | |
484 | tic6x_frame_this_id, | |
485 | tic6x_frame_prev_register, | |
486 | NULL, | |
487 | default_frame_sniffer | |
488 | }; | |
489 | ||
490 | static const struct frame_base tic6x_frame_base = | |
491 | { | |
492 | &tic6x_frame_unwind, | |
493 | tic6x_frame_base_address, | |
494 | tic6x_frame_base_address, | |
495 | tic6x_frame_base_address | |
496 | }; | |
497 | ||
498 | ||
499 | static struct tic6x_unwind_cache * | |
500 | tic6x_make_stub_cache (struct frame_info *this_frame) | |
501 | { | |
502 | struct tic6x_unwind_cache *cache; | |
503 | ||
504 | cache = FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache); | |
505 | ||
506 | cache->return_regnum = TIC6X_RA_REGNUM; | |
507 | ||
508 | tic6x_setup_default (cache); | |
509 | ||
510 | cache->cfa = get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM); | |
511 | ||
512 | return cache; | |
513 | } | |
514 | ||
515 | static void | |
516 | tic6x_stub_this_id (struct frame_info *this_frame, void **this_cache, | |
517 | struct frame_id *this_id) | |
518 | { | |
519 | struct tic6x_unwind_cache *cache; | |
520 | ||
521 | if (*this_cache == NULL) | |
522 | *this_cache = tic6x_make_stub_cache (this_frame); | |
523 | cache = *this_cache; | |
524 | ||
525 | *this_id = frame_id_build (cache->cfa, get_frame_pc (this_frame)); | |
526 | } | |
527 | ||
528 | static int | |
529 | tic6x_stub_unwind_sniffer (const struct frame_unwind *self, | |
530 | struct frame_info *this_frame, | |
531 | void **this_prologue_cache) | |
532 | { | |
533 | CORE_ADDR addr_in_block; | |
534 | ||
535 | addr_in_block = get_frame_address_in_block (this_frame); | |
536 | if (in_plt_section (addr_in_block, NULL)) | |
537 | return 1; | |
538 | ||
539 | return 0; | |
540 | } | |
541 | ||
542 | static const struct frame_unwind tic6x_stub_unwind = | |
543 | { | |
544 | NORMAL_FRAME, | |
545 | default_frame_unwind_stop_reason, | |
546 | tic6x_stub_this_id, | |
547 | tic6x_frame_prev_register, | |
548 | NULL, | |
549 | tic6x_stub_unwind_sniffer | |
550 | }; | |
551 | ||
552 | /* Return the instruction on address PC. */ | |
553 | ||
554 | static unsigned long | |
555 | tic6x_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR pc) | |
556 | { | |
557 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
558 | return read_memory_unsigned_integer (pc, TIC6X_OPCODE_SIZE, byte_order); | |
559 | } | |
560 | ||
561 | /* Compute the condition of INST if it is a conditional instruction. Always | |
562 | return 1 if INST is not a conditional instruction. */ | |
563 | ||
564 | static int | |
565 | tic6x_condition_true (struct frame_info *frame, unsigned long inst) | |
566 | { | |
567 | int register_number; | |
568 | int register_value; | |
569 | static const int register_numbers[8] = { -1, 16, 17, 18, 1, 2, 0, -1 }; | |
570 | ||
571 | register_number = register_numbers[(inst >> 29) & 7]; | |
572 | if (register_number == -1) | |
573 | return 1; | |
574 | ||
575 | register_value = get_frame_register_signed (frame, register_number); | |
576 | if ((inst & 0x10000000) != 0) | |
577 | return register_value == 0; | |
578 | return register_value != 0; | |
579 | } | |
580 | ||
581 | /* Get the register number by decoding raw bits REG, SIDE, and CROSSPATH in | |
582 | instruction. */ | |
583 | ||
584 | static int | |
585 | tic6x_register_number (int reg, int side, int crosspath) | |
586 | { | |
587 | int r = (reg & 15) | ((crosspath ^ side) << 4); | |
588 | if ((reg & 16) != 0) /* A16 - A31, B16 - B31 */ | |
589 | r += 37; | |
590 | return r; | |
591 | } | |
592 | ||
593 | static int | |
594 | tic6x_extract_signed_field (int value, int low_bit, int bits) | |
595 | { | |
596 | int mask = (1 << bits) - 1; | |
597 | int r = (value >> low_bit) & mask; | |
598 | if ((r & (1 << (bits - 1))) != 0) | |
599 | r -= mask + 1; | |
600 | return r; | |
601 | } | |
602 | ||
603 | /* Determine where to set a single step breakpoint. */ | |
604 | ||
605 | static CORE_ADDR | |
606 | tic6x_get_next_pc (struct frame_info *frame, CORE_ADDR pc) | |
607 | { | |
608 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
609 | unsigned long inst; | |
610 | int offset; | |
611 | int register_number; | |
612 | int last = 0; | |
613 | ||
614 | do | |
615 | { | |
616 | inst = tic6x_fetch_instruction (gdbarch, pc); | |
617 | ||
618 | last = !(inst & 1); | |
619 | ||
620 | if (inst == TIC6X_INST_SWE) | |
621 | { | |
622 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
623 | ||
624 | if (tdep->syscall_next_pc != NULL) | |
625 | return tdep->syscall_next_pc (frame); | |
626 | } | |
627 | ||
628 | if (tic6x_condition_true (frame, inst)) | |
629 | { | |
630 | if ((inst & 0x0000007c) == 0x00000010) | |
631 | { | |
632 | /* B with displacement */ | |
633 | pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1); | |
634 | pc += tic6x_extract_signed_field (inst, 7, 21) << 2; | |
635 | break; | |
636 | } | |
637 | if ((inst & 0x0f83effc) == 0x00000360) | |
638 | { | |
639 | /* B with register */ | |
640 | ||
641 | register_number = tic6x_register_number ((inst >> 18) & 0x1f, | |
642 | INST_S_BIT (inst), | |
643 | INST_X_BIT (inst)); | |
644 | pc = get_frame_register_unsigned (frame, register_number); | |
645 | break; | |
646 | } | |
647 | if ((inst & 0x00001ffc) == 0x00001020) | |
648 | { | |
649 | /* BDEC */ | |
650 | register_number = tic6x_register_number ((inst >> 23) & 0x1f, | |
651 | INST_S_BIT (inst), 0); | |
652 | if (get_frame_register_signed (frame, register_number) >= 0) | |
653 | { | |
654 | pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1); | |
655 | pc += tic6x_extract_signed_field (inst, 7, 10) << 2; | |
656 | } | |
657 | break; | |
658 | } | |
659 | if ((inst & 0x00001ffc) == 0x00000120) | |
660 | { | |
661 | /* BNOP with displacement */ | |
662 | pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1); | |
663 | pc += tic6x_extract_signed_field (inst, 16, 12) << 2; | |
664 | break; | |
665 | } | |
666 | if ((inst & 0x0f830ffe) == 0x00800362) | |
667 | { | |
668 | /* BNOP with register */ | |
669 | register_number = tic6x_register_number ((inst >> 18) & 0x1f, | |
670 | 1, INST_X_BIT (inst)); | |
671 | pc = get_frame_register_unsigned (frame, register_number); | |
672 | break; | |
673 | } | |
674 | if ((inst & 0x00001ffc) == 0x00000020) | |
675 | { | |
676 | /* BPOS */ | |
677 | register_number = tic6x_register_number ((inst >> 23) & 0x1f, | |
678 | INST_S_BIT (inst), 0); | |
679 | if (get_frame_register_signed (frame, register_number) >= 0) | |
680 | { | |
681 | pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1); | |
682 | pc += tic6x_extract_signed_field (inst, 13, 10) << 2; | |
683 | } | |
684 | break; | |
685 | } | |
686 | if ((inst & 0xf000007c) == 0x10000010) | |
687 | { | |
688 | /* CALLP */ | |
689 | pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1); | |
690 | pc += tic6x_extract_signed_field (inst, 7, 21) << 2; | |
691 | break; | |
692 | } | |
693 | } | |
694 | pc += TIC6X_OPCODE_SIZE; | |
695 | } | |
696 | while (!last); | |
697 | return pc; | |
698 | } | |
699 | ||
700 | /* This is the implementation of gdbarch method software_single_step. */ | |
701 | ||
702 | int | |
703 | tic6x_software_single_step (struct frame_info *frame) | |
704 | { | |
705 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
706 | struct address_space *aspace = get_frame_address_space (frame); | |
707 | CORE_ADDR next_pc = tic6x_get_next_pc (frame, get_frame_pc (frame)); | |
708 | ||
709 | insert_single_step_breakpoint (gdbarch, aspace, next_pc); | |
710 | ||
711 | return 1; | |
712 | } | |
713 | ||
714 | /* This is the implementation of gdbarch method frame_align. */ | |
715 | ||
716 | static CORE_ADDR | |
717 | tic6x_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
718 | { | |
719 | return align_down (addr, 8); | |
720 | } | |
721 | ||
722 | /* This is the implementation of gdbarch method register_to_value. */ | |
723 | ||
724 | static int | |
725 | tic6x_register_to_value (struct frame_info *frame, int regnum, | |
726 | struct type *type, gdb_byte * to, | |
727 | int *optimizedp, int *unavailablep) | |
728 | { | |
729 | get_frame_register (frame, regnum, (char *) to); | |
730 | *optimizedp = *unavailablep = 0; | |
731 | return 1; | |
732 | } | |
733 | ||
734 | /* This is the implementation of gdbarch method value_to_register. */ | |
735 | ||
736 | static void | |
737 | tic6x_value_to_register (struct frame_info *frame, int regnum, | |
738 | struct type *type, const gdb_byte *from) | |
739 | { | |
740 | put_frame_register (frame, regnum, from); | |
741 | } | |
742 | ||
743 | /* Given a return value in REGCACHE with a type VALTYPE, extract and copy its | |
744 | value into VALBUF. */ | |
745 | ||
746 | static void | |
747 | tic6x_extract_return_value (struct type *valtype, struct regcache *regcache, | |
748 | enum bfd_endian byte_order, gdb_byte *valbuf) | |
749 | { | |
750 | int len = TYPE_LENGTH (valtype); | |
751 | ||
752 | /* pointer types are returned in register A4, | |
753 | up to 32-bit types in A4 | |
754 | up to 64-bit types in A5:A4 */ | |
755 | if (len <= 4) | |
756 | { | |
757 | /* In big-endian, | |
758 | - one-byte structure or union occupies the LSB of single even register. | |
759 | - for two-byte structure or union, the first byte occupies byte 1 of | |
760 | register and the second byte occupies byte 0. | |
761 | so, we read the contents in VAL from the LSBs of register. */ | |
762 | if (len < 3 && byte_order == BFD_ENDIAN_BIG) | |
763 | regcache_cooked_read_part (regcache, TIC6X_A4_REGNUM, 4 - len, len, | |
764 | valbuf); | |
765 | else | |
766 | regcache_cooked_read (regcache, TIC6X_A4_REGNUM, valbuf); | |
767 | } | |
768 | else if (len <= 8) | |
769 | { | |
770 | /* For a 5-8 byte structure or union in big-endian, the first byte | |
771 | occupies byte 3 (the MSB) of the upper (odd) register and the | |
772 | remaining bytes fill the decreasingly significant bytes. 5-7 | |
773 | byte structures or unions have padding in the LSBs of the | |
774 | lower (even) register. */ | |
775 | if (byte_order == BFD_ENDIAN_BIG) | |
776 | { | |
777 | regcache_cooked_read (regcache, TIC6X_A4_REGNUM, valbuf + 4); | |
778 | regcache_cooked_read (regcache, TIC6X_A5_REGNUM, valbuf); | |
779 | } | |
780 | else | |
781 | { | |
782 | regcache_cooked_read (regcache, TIC6X_A4_REGNUM, valbuf); | |
783 | regcache_cooked_read (regcache, TIC6X_A5_REGNUM, valbuf + 4); | |
784 | } | |
785 | } | |
786 | } | |
787 | ||
788 | /* Write into appropriate registers a function return value | |
789 | of type TYPE, given in virtual format. */ | |
790 | ||
791 | static void | |
792 | tic6x_store_return_value (struct type *valtype, struct regcache *regcache, | |
793 | enum bfd_endian byte_order, const gdb_byte *valbuf) | |
794 | { | |
795 | int len = TYPE_LENGTH (valtype); | |
796 | ||
797 | /* return values of up to 8 bytes are returned in A5:A4 */ | |
798 | ||
799 | if (len <= 4) | |
800 | { | |
801 | if (len < 3 && byte_order == BFD_ENDIAN_BIG) | |
802 | regcache_cooked_write_part (regcache, TIC6X_A4_REGNUM, 4 - len, len, | |
803 | valbuf); | |
804 | else | |
805 | regcache_cooked_write (regcache, TIC6X_A4_REGNUM, valbuf); | |
806 | } | |
807 | else if (len <= 8) | |
808 | { | |
809 | if (byte_order == BFD_ENDIAN_BIG) | |
810 | { | |
811 | regcache_cooked_write (regcache, TIC6X_A4_REGNUM, valbuf + 4); | |
812 | regcache_cooked_write (regcache, TIC6X_A5_REGNUM, valbuf); | |
813 | } | |
814 | else | |
815 | { | |
816 | regcache_cooked_write (regcache, TIC6X_A4_REGNUM, valbuf); | |
817 | regcache_cooked_write (regcache, TIC6X_A5_REGNUM, valbuf + 4); | |
818 | } | |
819 | } | |
820 | } | |
821 | ||
822 | /* This is the implementation of gdbarch method return_value. */ | |
823 | ||
824 | static enum return_value_convention | |
825 | tic6x_return_value (struct gdbarch *gdbarch, struct type *func_type, | |
826 | struct type *type, struct regcache *regcache, | |
827 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
828 | { | |
829 | if (TYPE_LENGTH (type) > 8) | |
830 | return RETURN_VALUE_STRUCT_CONVENTION; | |
831 | ||
832 | if (readbuf) | |
833 | tic6x_extract_return_value (type, regcache, | |
834 | gdbarch_byte_order (gdbarch), readbuf); | |
835 | if (writebuf) | |
836 | tic6x_store_return_value (type, regcache, | |
837 | gdbarch_byte_order (gdbarch), writebuf); | |
838 | ||
839 | return RETURN_VALUE_REGISTER_CONVENTION; | |
840 | } | |
841 | ||
842 | /* This is the implementation of gdbarch method dummy_id. */ | |
843 | ||
844 | static struct frame_id | |
845 | tic6x_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
846 | { | |
847 | return frame_id_build | |
848 | (get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM), | |
849 | get_frame_pc (this_frame)); | |
850 | } | |
851 | ||
852 | /* Get the alignment requirement of TYPE. */ | |
853 | ||
854 | static int | |
855 | tic6x_arg_type_alignment (struct type *type) | |
856 | { | |
857 | int len = TYPE_LENGTH (check_typedef (type)); | |
858 | enum type_code typecode = TYPE_CODE (check_typedef (type)); | |
859 | ||
860 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
861 | { | |
862 | /* The stack alignment of a structure (and union) passed by value is the | |
863 | smallest power of two greater than or equal to its size. | |
864 | This cannot exceed 8 bytes, which is the largest allowable size for | |
865 | a structure passed by value. */ | |
866 | ||
867 | if (len <= 2) | |
868 | return len; | |
869 | else if (len <= 4) | |
870 | return 4; | |
871 | else if (len <= 8) | |
872 | return 8; | |
873 | else | |
874 | gdb_assert_not_reached ("unexpected length of data"); | |
875 | } | |
876 | else | |
877 | { | |
878 | if (len <= 4) | |
879 | return 4; | |
880 | else if (len == 8) | |
881 | { | |
882 | if (typecode == TYPE_CODE_COMPLEX) | |
883 | return 4; | |
884 | else | |
885 | return 8; | |
886 | } | |
887 | else if (len == 16) | |
888 | { | |
889 | if (typecode == TYPE_CODE_COMPLEX) | |
890 | return 8; | |
891 | else | |
892 | return 16; | |
893 | } | |
894 | else | |
895 | internal_error (__FILE__, __LINE__, _("unexpected length %d of type"), | |
896 | len); | |
897 | } | |
898 | } | |
899 | ||
900 | /* This is the implementation of gdbarch method push_dummy_call. */ | |
901 | ||
902 | static CORE_ADDR | |
903 | tic6x_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
904 | struct regcache *regcache, CORE_ADDR bp_addr, | |
905 | int nargs, struct value **args, CORE_ADDR sp, | |
906 | int struct_return, CORE_ADDR struct_addr) | |
907 | { | |
908 | int argreg = 0; | |
909 | int argnum; | |
910 | int len = 0; | |
911 | int stack_offset = 4; | |
912 | int references_offset = 4; | |
913 | CORE_ADDR func_addr = find_function_addr (function, NULL); | |
914 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
915 | struct type *func_type = value_type (function); | |
916 | /* The first arg passed on stack. Mostly the first 10 args are passed by | |
917 | registers. */ | |
918 | int first_arg_on_stack = 10; | |
919 | /* If this inf-call is a cpp method call, and return value is passed by | |
920 | reference, this flag is set to 1, otherwise set to 0. We need this flag | |
921 | because computation of the return location in | |
922 | infcall.c:call_function_by_hand is wrong for C6000 ELF ABI. In | |
923 | call_function_by_hand, the language is considered first, and then | |
924 | target ABI is considered. If language_pass_by_reference returns true, | |
925 | the return location is passed as the first parameter to the function, | |
926 | which is conflict with C6000 ELF ABI. If this flag is true, we should | |
927 | adjust args and return locations accordingly to comply with C6000 ELF | |
928 | ABI. */ | |
929 | int cplus_return_struct_by_reference = 0; | |
930 | ||
931 | if (current_language->la_language == language_cplus) | |
932 | { | |
933 | struct type *values_type; | |
934 | ||
935 | find_function_addr (function, &values_type); | |
936 | ||
937 | if (values_type) | |
938 | { | |
939 | CHECK_TYPEDEF (values_type); | |
940 | if (language_pass_by_reference (values_type)) | |
941 | cplus_return_struct_by_reference = 1; | |
942 | } | |
943 | ||
944 | } | |
945 | /* Set the return address register to point to the entry point of | |
946 | the program, where a breakpoint lies in wait. */ | |
947 | regcache_cooked_write_unsigned (regcache, TIC6X_RA_REGNUM, bp_addr); | |
948 | ||
949 | /* The caller must pass an argument in A3 containing a destination address | |
950 | for the returned value. The callee returns the object by copying it to | |
951 | the address in A3. */ | |
952 | if (struct_return) | |
953 | regcache_cooked_write_unsigned (regcache, 3, struct_addr); | |
954 | else if (cplus_return_struct_by_reference) | |
955 | /* When cplus_return_struct_by_reference is 1, means local variable | |
956 | lang_struct_return in call_function_by_hand is 1, so struct is | |
957 | returned by reference, even STRUCT_RETURN is 0. Note that STRUCT_ADDR | |
958 | is still valid in this case. */ | |
959 | regcache_cooked_write_unsigned (regcache, 3, struct_addr); | |
960 | ||
961 | /* Determine the type of this function. */ | |
962 | func_type = check_typedef (func_type); | |
963 | if (TYPE_CODE (func_type) == TYPE_CODE_PTR) | |
964 | func_type = check_typedef (TYPE_TARGET_TYPE (func_type)); | |
965 | ||
966 | gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC | |
967 | || TYPE_CODE (func_type) == TYPE_CODE_METHOD); | |
968 | ||
969 | /* For a variadic C function, the last explicitly declared argument and all | |
970 | remaining arguments are passed on the stack. */ | |
971 | if (TYPE_VARARGS (func_type)) | |
972 | first_arg_on_stack = TYPE_NFIELDS (func_type) - 1; | |
973 | ||
974 | /* Now make space on the stack for the args. If | |
975 | cplus_return_struct_by_reference is 1, means GDB pass an extra parameter | |
976 | in ARGS, which is useless here, skip it. */ | |
977 | for (argnum = cplus_return_struct_by_reference; argnum < nargs; argnum++) | |
978 | { | |
979 | int len = align_up (TYPE_LENGTH (value_type (args[argnum])), 4); | |
980 | if (argnum >= 10 - argreg) | |
981 | references_offset += len; | |
982 | stack_offset += len; | |
983 | } | |
984 | sp -= stack_offset; | |
985 | /* SP should be 8-byte aligned, see C6000 ABI section 4.4.1 | |
986 | Stack Alignment. */ | |
987 | sp = align_down (sp, 8); | |
988 | stack_offset = 4; | |
989 | ||
990 | /* Now load as many as possible of the first arguments into | |
991 | registers, and push the rest onto the stack. Loop through args | |
992 | from first to last. */ | |
993 | for (argnum = cplus_return_struct_by_reference; argnum < nargs; argnum++) | |
994 | { | |
995 | const gdb_byte *val; | |
996 | struct value *arg = args[argnum]; | |
997 | struct type *arg_type = check_typedef (value_type (arg)); | |
998 | int len = TYPE_LENGTH (arg_type); | |
999 | enum type_code typecode = TYPE_CODE (arg_type); | |
1000 | ||
1001 | val = value_contents (arg); | |
1002 | ||
1003 | /* Copy the argument to general registers or the stack in | |
1004 | register-sized pieces. */ | |
1005 | if (argreg < first_arg_on_stack) | |
1006 | { | |
1007 | if (len <= 4) | |
1008 | { | |
1009 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
1010 | { | |
1011 | /* In big-endian, | |
1012 | - one-byte structure or union occupies the LSB of single | |
1013 | even register. | |
1014 | - for two-byte structure or union, the first byte | |
1015 | occupies byte 1 of register and the second byte occupies | |
1016 | byte 0. | |
1017 | so, we write the contents in VAL to the lsp of | |
1018 | register. */ | |
1019 | if (len < 3 && byte_order == BFD_ENDIAN_BIG) | |
1020 | regcache_cooked_write_part (regcache, arg_regs[argreg], | |
1021 | 4 - len, len, val); | |
1022 | else | |
1023 | regcache_cooked_write (regcache, arg_regs[argreg], val); | |
1024 | } | |
1025 | else | |
1026 | { | |
1027 | /* The argument is being passed by value in a single | |
1028 | register. */ | |
1029 | CORE_ADDR regval = extract_unsigned_integer (val, len, | |
1030 | byte_order); | |
1031 | ||
1032 | regcache_cooked_write_unsigned (regcache, arg_regs[argreg], | |
1033 | regval); | |
1034 | } | |
1035 | } | |
1036 | else | |
1037 | { | |
1038 | if (len <= 8) | |
1039 | { | |
1040 | if (typecode == TYPE_CODE_STRUCT | |
1041 | || typecode == TYPE_CODE_UNION) | |
1042 | { | |
1043 | /* For a 5-8 byte structure or union in big-endian, the | |
1044 | first byte occupies byte 3 (the MSB) of the upper (odd) | |
1045 | register and the remaining bytes fill the decreasingly | |
1046 | significant bytes. 5-7 byte structures or unions have | |
1047 | padding in the LSBs of the lower (even) register. */ | |
1048 | if (byte_order == BFD_ENDIAN_BIG) | |
1049 | { | |
1050 | regcache_cooked_write (regcache, | |
1051 | arg_regs[argreg] + 1, val); | |
1052 | regcache_cooked_write_part (regcache, | |
1053 | arg_regs[argreg], 0, | |
1054 | len - 4, val + 4); | |
1055 | } | |
1056 | else | |
1057 | { | |
1058 | regcache_cooked_write (regcache, arg_regs[argreg], | |
1059 | val); | |
1060 | regcache_cooked_write_part (regcache, | |
1061 | arg_regs[argreg] + 1, 0, | |
1062 | len - 4, val + 4); | |
1063 | } | |
1064 | } | |
1065 | else | |
1066 | { | |
1067 | /* The argument is being passed by value in a pair of | |
1068 | registers. */ | |
1069 | ULONGEST regval = extract_unsigned_integer (val, len, | |
1070 | byte_order); | |
1071 | ||
1072 | regcache_cooked_write_unsigned (regcache, | |
1073 | arg_regs[argreg], | |
1074 | regval); | |
1075 | regcache_cooked_write_unsigned (regcache, | |
1076 | arg_regs[argreg] + 1, | |
1077 | regval >> 32); | |
1078 | } | |
1079 | } | |
1080 | else | |
1081 | { | |
1082 | /* The argument is being passed by reference in a single | |
1083 | register. */ | |
1084 | CORE_ADDR addr; | |
1085 | ||
1086 | /* It is not necessary to adjust REFERENCES_OFFSET to | |
1087 | 8-byte aligned in some cases, in which 4-byte alignment | |
1088 | is sufficient. For simplicity, we adjust | |
1089 | REFERENCES_OFFSET to 8-byte aligned. */ | |
1090 | references_offset = align_up (references_offset, 8); | |
1091 | ||
1092 | addr = sp + references_offset; | |
1093 | write_memory (addr, val, len); | |
1094 | references_offset += align_up (len, 4); | |
1095 | regcache_cooked_write_unsigned (regcache, arg_regs[argreg], | |
1096 | addr); | |
1097 | } | |
1098 | } | |
1099 | argreg++; | |
1100 | } | |
1101 | else | |
1102 | { | |
1103 | /* The argument is being passed on the stack. */ | |
1104 | CORE_ADDR addr; | |
1105 | ||
1106 | /* There are six different cases of alignment, and these rules can | |
1107 | be found in tic6x_arg_type_alignment: | |
1108 | ||
1109 | 1) 4-byte aligned if size is less than or equal to 4 byte, such | |
1110 | as short, int, struct, union etc. | |
1111 | 2) 8-byte aligned if size is less than or equal to 8-byte, such | |
1112 | as double, long long, | |
1113 | 3) 4-byte aligned if it is of type _Complex float, even its size | |
1114 | is 8-byte. | |
1115 | 4) 8-byte aligned if it is of type _Complex double or _Complex | |
1116 | long double, even its size is 16-byte. Because, the address of | |
1117 | variable is passed as reference. | |
1118 | 5) struct and union larger than 8-byte are passed by reference, so | |
1119 | it is 4-byte aligned. | |
1120 | 6) struct and union of size between 4 byte and 8 byte varies. | |
1121 | alignment of struct variable is the alignment of its first field, | |
1122 | while alignment of union variable is the max of all its fields' | |
1123 | alignment. */ | |
1124 | ||
1125 | if (len <= 4) | |
1126 | ; /* Default is 4-byte aligned. Nothing to be done. */ | |
1127 | else if (len <= 8) | |
1128 | stack_offset = align_up (stack_offset, | |
1129 | tic6x_arg_type_alignment (arg_type)); | |
1130 | else if (len == 16) | |
1131 | { | |
1132 | /* _Complex double or _Complex long double */ | |
1133 | if (typecode == TYPE_CODE_COMPLEX) | |
1134 | { | |
1135 | /* The argument is being passed by reference on stack. */ | |
1136 | CORE_ADDR addr; | |
1137 | references_offset = align_up (references_offset, 8); | |
1138 | ||
1139 | addr = sp + references_offset; | |
1140 | /* Store variable on stack. */ | |
1141 | write_memory (addr, val, len); | |
1142 | ||
1143 | references_offset += align_up (len, 4); | |
1144 | ||
1145 | /* Pass the address of variable on stack as reference. */ | |
1146 | store_unsigned_integer ((gdb_byte *) val, 4, byte_order, | |
1147 | addr); | |
1148 | len = 4; | |
1149 | ||
1150 | } | |
1151 | else | |
1152 | internal_error (__FILE__, __LINE__, | |
1153 | _("unexpected type %d of arg %d"), | |
1154 | typecode, argnum); | |
1155 | } | |
1156 | else | |
1157 | internal_error (__FILE__, __LINE__, | |
1158 | _("unexpected length %d of arg %d"), len, argnum); | |
1159 | ||
1160 | addr = sp + stack_offset; | |
1161 | write_memory (addr, val, len); | |
1162 | stack_offset += align_up (len, 4); | |
1163 | } | |
1164 | } | |
1165 | ||
1166 | regcache_cooked_write_signed (regcache, TIC6X_SP_REGNUM, sp); | |
1167 | ||
1168 | /* Return adjusted stack pointer. */ | |
1169 | return sp; | |
1170 | } | |
1171 | ||
1172 | /* This is the implementation of gdbarch method in_function_epilogue_p. */ | |
1173 | ||
1174 | static int | |
1175 | tic6x_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1176 | { | |
1177 | unsigned long inst = tic6x_fetch_instruction (gdbarch, pc); | |
1178 | /* Normally, the epilogue is composed by instruction `b .S2 b3'. */ | |
1179 | if ((inst & 0x0f83effc) == 0x360) | |
1180 | { | |
1181 | unsigned int src2 = tic6x_register_number ((inst >> 18) & 0x1f, | |
1182 | INST_S_BIT (inst), | |
1183 | INST_X_BIT (inst)); | |
1184 | if (src2 == TIC6X_RA_REGNUM) | |
1185 | return 1; | |
1186 | } | |
1187 | ||
1188 | return 0; | |
1189 | } | |
1190 | ||
1191 | /* This is the implementation of gdbarch method get_longjmp_target. */ | |
1192 | ||
1193 | static int | |
1194 | tic6x_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) | |
1195 | { | |
1196 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
1197 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1198 | CORE_ADDR jb_addr; | |
1199 | char buf[4]; | |
1200 | ||
1201 | /* JMP_BUF is passed by reference in A4. */ | |
1202 | jb_addr = get_frame_register_unsigned (frame, 4); | |
1203 | ||
1204 | /* JMP_BUF contains 13 elements of type int, and return address is stored | |
1205 | in the last slot. */ | |
1206 | if (target_read_memory (jb_addr + 12 * 4, buf, 4)) | |
1207 | return 0; | |
1208 | ||
1209 | *pc = extract_unsigned_integer (buf, 4, byte_order); | |
1210 | ||
1211 | return 1; | |
1212 | } | |
1213 | ||
1214 | static struct gdbarch * | |
1215 | tic6x_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1216 | { | |
1217 | struct gdbarch *gdbarch; | |
1218 | struct gdbarch_tdep *tdep; | |
1219 | struct tdesc_arch_data *tdesc_data = NULL; | |
1220 | const struct target_desc *tdesc = info.target_desc; | |
1221 | int has_gp = 0; | |
1222 | ||
1223 | /* Check any target description for validity. */ | |
1224 | if (tdesc_has_registers (tdesc)) | |
1225 | { | |
1226 | const struct tdesc_feature *feature; | |
1227 | int valid_p, i; | |
1228 | ||
1229 | feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.core"); | |
1230 | ||
1231 | if (feature == NULL) | |
1232 | return NULL; | |
1233 | ||
1234 | tdesc_data = tdesc_data_alloc (); | |
1235 | ||
1236 | valid_p = 1; | |
1237 | for (i = 0; i < 32; i++) /* A0 - A15, B0 - B15 */ | |
1238 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
1239 | tic6x_register_names[i]); | |
1240 | ||
1241 | /* CSR */ | |
1242 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, | |
1243 | tic6x_register_names[TIC6X_CSR_REGNUM]); | |
1244 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, | |
1245 | tic6x_register_names[TIC6X_PC_REGNUM]); | |
1246 | ||
1247 | if (!valid_p) | |
1248 | { | |
1249 | tdesc_data_cleanup (tdesc_data); | |
1250 | return NULL; | |
1251 | } | |
1252 | ||
1253 | feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.gp"); | |
1254 | if (feature) | |
1255 | { | |
1256 | int j = 0; | |
1257 | static const char *const gp[] = | |
1258 | { | |
1259 | "A16", "A17", "A18", "A19", "A20", "A21", "A22", "A23", | |
1260 | "A24", "A25", "A26", "A27", "A28", "A29", "A30", "A31", | |
1261 | "B16", "B17", "B18", "B19", "B20", "B21", "B22", "B23", | |
1262 | "B24", "B25", "B26", "B27", "B28", "B29", "B30", "B31", | |
1263 | }; | |
1264 | ||
1265 | has_gp = 1; | |
1266 | valid_p = 1; | |
1267 | for (j = 0; j < 32; j++) /* A16 - A31, B16 - B31 */ | |
1268 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, | |
1269 | gp[j]); | |
1270 | ||
1271 | if (!valid_p) | |
1272 | { | |
1273 | tdesc_data_cleanup (tdesc_data); | |
1274 | return NULL; | |
1275 | } | |
1276 | } | |
1277 | ||
1278 | feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.c6xp"); | |
1279 | if (feature) | |
1280 | { | |
1281 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "TSR"); | |
1282 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "ILC"); | |
1283 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i++, "RILC"); | |
1284 | ||
1285 | if (!valid_p) | |
1286 | { | |
1287 | tdesc_data_cleanup (tdesc_data); | |
1288 | return NULL; | |
1289 | } | |
1290 | } | |
1291 | ||
1292 | } | |
1293 | ||
1294 | /* Find a candidate among extant architectures. */ | |
1295 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
1296 | arches != NULL; | |
1297 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
1298 | { | |
1299 | tdep = gdbarch_tdep (arches->gdbarch); | |
1300 | ||
1301 | if (has_gp != tdep->has_gp) | |
1302 | continue; | |
1303 | ||
1304 | if (tdep && tdep->breakpoint) | |
1305 | return arches->gdbarch; | |
1306 | } | |
1307 | ||
1308 | tdep = xcalloc (1, sizeof (struct gdbarch_tdep)); | |
1309 | ||
1310 | tdep->has_gp = has_gp; | |
1311 | gdbarch = gdbarch_alloc (&info, tdep); | |
1312 | ||
1313 | /* Data type sizes. */ | |
1314 | set_gdbarch_ptr_bit (gdbarch, 32); | |
1315 | set_gdbarch_addr_bit (gdbarch, 32); | |
1316 | set_gdbarch_short_bit (gdbarch, 16); | |
1317 | set_gdbarch_int_bit (gdbarch, 32); | |
1318 | set_gdbarch_long_bit (gdbarch, 32); | |
1319 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1320 | set_gdbarch_float_bit (gdbarch, 32); | |
1321 | set_gdbarch_double_bit (gdbarch, 64); | |
1322 | ||
1323 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); | |
1324 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
1325 | ||
1326 | /* The register set. */ | |
1327 | set_gdbarch_num_regs (gdbarch, TIC6X_NUM_REGS); | |
1328 | set_gdbarch_sp_regnum (gdbarch, TIC6X_SP_REGNUM); | |
1329 | set_gdbarch_pc_regnum (gdbarch, TIC6X_PC_REGNUM); | |
1330 | ||
1331 | set_gdbarch_register_name (gdbarch, tic6x_register_name); | |
1332 | set_gdbarch_register_type (gdbarch, tic6x_register_type); | |
1333 | ||
1334 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1335 | ||
1336 | set_gdbarch_skip_prologue (gdbarch, tic6x_skip_prologue); | |
1337 | set_gdbarch_breakpoint_from_pc (gdbarch, tic6x_breakpoint_from_pc); | |
1338 | ||
1339 | set_gdbarch_unwind_pc (gdbarch, tic6x_unwind_pc); | |
1340 | set_gdbarch_unwind_sp (gdbarch, tic6x_unwind_sp); | |
1341 | ||
1342 | /* Unwinding. */ | |
1343 | dwarf2_append_unwinders (gdbarch); | |
1344 | ||
1345 | frame_unwind_append_unwinder (gdbarch, &tic6x_stub_unwind); | |
1346 | frame_unwind_append_unwinder (gdbarch, &tic6x_frame_unwind); | |
1347 | ||
1348 | dwarf2_frame_set_init_reg (gdbarch, tic6x_dwarf2_frame_init_reg); | |
1349 | ||
1350 | /* Single stepping. */ | |
1351 | set_gdbarch_software_single_step (gdbarch, tic6x_software_single_step); | |
1352 | ||
1353 | set_gdbarch_print_insn (gdbarch, tic6x_print_insn); | |
1354 | ||
1355 | /* Call dummy code. */ | |
1356 | set_gdbarch_frame_align (gdbarch, tic6x_frame_align); | |
1357 | ||
1358 | set_gdbarch_register_to_value (gdbarch, tic6x_register_to_value); | |
1359 | set_gdbarch_value_to_register (gdbarch, tic6x_value_to_register); | |
1360 | ||
1361 | set_gdbarch_return_value (gdbarch, tic6x_return_value); | |
1362 | ||
1363 | set_gdbarch_dummy_id (gdbarch, tic6x_dummy_id); | |
1364 | ||
1365 | /* Enable inferior call support. */ | |
1366 | set_gdbarch_push_dummy_call (gdbarch, tic6x_push_dummy_call); | |
1367 | ||
1368 | set_gdbarch_get_longjmp_target (gdbarch, tic6x_get_longjmp_target); | |
1369 | ||
1370 | set_gdbarch_in_function_epilogue_p (gdbarch, tic6x_in_function_epilogue_p); | |
1371 | ||
1372 | /* Hook in ABI-specific overrides, if they have been registered. */ | |
1373 | gdbarch_init_osabi (info, gdbarch); | |
1374 | ||
1375 | if (tdesc_data) | |
1376 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); | |
1377 | ||
1378 | return gdbarch; | |
1379 | } | |
1380 | ||
1381 | void | |
1382 | _initialize_tic6x_tdep (void) | |
1383 | { | |
1384 | register_gdbarch_init (bfd_arch_tic6x, tic6x_gdbarch_init); | |
1385 | ||
1386 | initialize_tdesc_tic6x_c64xp (); | |
1387 | initialize_tdesc_tic6x_c64x (); | |
1388 | initialize_tdesc_tic6x_c62x (); | |
1389 | } |