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[deliverable/binutils-gdb.git] / gdb / tilegx-tdep.c
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ade64f0e
PA		 1/* Target-dependent code for the Tilera TILE-Gx processor.
2
618f726f 3 Copyright (C) 2012-2016 Free Software Foundation, Inc.
ade64f0e
PA		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20#include "defs.h"
21#include "frame.h"
22#include "frame-base.h"
23#include "frame-unwind.h"
24#include "dwarf2-frame.h"
25#include "trad-frame.h"
26#include "symtab.h"
27#include "gdbtypes.h"
28#include "gdbcmd.h"
29#include "gdbcore.h"
30#include "value.h"
31#include "dis-asm.h"
32#include "inferior.h"
ade64f0e
PA		 33#include "arch-utils.h"
34#include "floatformat.h"
35#include "regcache.h"
36#include "regset.h"
37#include "doublest.h"
38#include "osabi.h"
39#include "linux-tdep.h"
40#include "objfiles.h"
41#include "solib-svr4.h"
ade64f0e
PA		 42#include "tilegx-tdep.h"
43#include "opcode/tilegx.h"
325fac50 44#include <algorithm>
ade64f0e
PA		 45
46struct tilegx_frame_cache
47{
48 /* Base address. */
49 CORE_ADDR base;
50 /* Function start. */
51 CORE_ADDR start_pc;
52
53 /* Table of saved registers. */
54 struct trad_frame_saved_reg *saved_regs;
55};
56
57/* Register state values used by analyze_prologue. */
58enum reverse_state
59 {
60 REVERSE_STATE_REGISTER,
61 REVERSE_STATE_VALUE,
62 REVERSE_STATE_UNKNOWN
63 };
64
65/* Register state used by analyze_prologue(). */
66struct tilegx_reverse_regs
67{
68 LONGEST value;
69 enum reverse_state state;
70};
71
72static const struct tilegx_reverse_regs
73template_reverse_regs[TILEGX_NUM_PHYS_REGS] =
74 {
75 { TILEGX_R0_REGNUM, REVERSE_STATE_REGISTER },
76 { TILEGX_R1_REGNUM, REVERSE_STATE_REGISTER },
77 { TILEGX_R2_REGNUM, REVERSE_STATE_REGISTER },
78 { TILEGX_R3_REGNUM, REVERSE_STATE_REGISTER },
79 { TILEGX_R4_REGNUM, REVERSE_STATE_REGISTER },
80 { TILEGX_R5_REGNUM, REVERSE_STATE_REGISTER },
81 { TILEGX_R6_REGNUM, REVERSE_STATE_REGISTER },
82 { TILEGX_R7_REGNUM, REVERSE_STATE_REGISTER },
83 { TILEGX_R8_REGNUM, REVERSE_STATE_REGISTER },
84 { TILEGX_R9_REGNUM, REVERSE_STATE_REGISTER },
85 { TILEGX_R10_REGNUM, REVERSE_STATE_REGISTER },
86 { TILEGX_R11_REGNUM, REVERSE_STATE_REGISTER },
87 { TILEGX_R12_REGNUM, REVERSE_STATE_REGISTER },
88 { TILEGX_R13_REGNUM, REVERSE_STATE_REGISTER },
89 { TILEGX_R14_REGNUM, REVERSE_STATE_REGISTER },
90 { TILEGX_R15_REGNUM, REVERSE_STATE_REGISTER },
91 { TILEGX_R16_REGNUM, REVERSE_STATE_REGISTER },
92 { TILEGX_R17_REGNUM, REVERSE_STATE_REGISTER },
93 { TILEGX_R18_REGNUM, REVERSE_STATE_REGISTER },
94 { TILEGX_R19_REGNUM, REVERSE_STATE_REGISTER },
95 { TILEGX_R20_REGNUM, REVERSE_STATE_REGISTER },
96 { TILEGX_R21_REGNUM, REVERSE_STATE_REGISTER },
97 { TILEGX_R22_REGNUM, REVERSE_STATE_REGISTER },
98 { TILEGX_R23_REGNUM, REVERSE_STATE_REGISTER },
99 { TILEGX_R24_REGNUM, REVERSE_STATE_REGISTER },
100 { TILEGX_R25_REGNUM, REVERSE_STATE_REGISTER },
101 { TILEGX_R26_REGNUM, REVERSE_STATE_REGISTER },
102 { TILEGX_R27_REGNUM, REVERSE_STATE_REGISTER },
103 { TILEGX_R28_REGNUM, REVERSE_STATE_REGISTER },
104 { TILEGX_R29_REGNUM, REVERSE_STATE_REGISTER },
105 { TILEGX_R30_REGNUM, REVERSE_STATE_REGISTER },
106 { TILEGX_R31_REGNUM, REVERSE_STATE_REGISTER },
107 { TILEGX_R32_REGNUM, REVERSE_STATE_REGISTER },
108 { TILEGX_R33_REGNUM, REVERSE_STATE_REGISTER },
109 { TILEGX_R34_REGNUM, REVERSE_STATE_REGISTER },
110 { TILEGX_R35_REGNUM, REVERSE_STATE_REGISTER },
111 { TILEGX_R36_REGNUM, REVERSE_STATE_REGISTER },
112 { TILEGX_R37_REGNUM, REVERSE_STATE_REGISTER },
113 { TILEGX_R38_REGNUM, REVERSE_STATE_REGISTER },
114 { TILEGX_R39_REGNUM, REVERSE_STATE_REGISTER },
115 { TILEGX_R40_REGNUM, REVERSE_STATE_REGISTER },
116 { TILEGX_R41_REGNUM, REVERSE_STATE_REGISTER },
117 { TILEGX_R42_REGNUM, REVERSE_STATE_REGISTER },
118 { TILEGX_R43_REGNUM, REVERSE_STATE_REGISTER },
119 { TILEGX_R44_REGNUM, REVERSE_STATE_REGISTER },
120 { TILEGX_R45_REGNUM, REVERSE_STATE_REGISTER },
121 { TILEGX_R46_REGNUM, REVERSE_STATE_REGISTER },
122 { TILEGX_R47_REGNUM, REVERSE_STATE_REGISTER },
123 { TILEGX_R48_REGNUM, REVERSE_STATE_REGISTER },
124 { TILEGX_R49_REGNUM, REVERSE_STATE_REGISTER },
125 { TILEGX_R50_REGNUM, REVERSE_STATE_REGISTER },
126 { TILEGX_R51_REGNUM, REVERSE_STATE_REGISTER },
127 { TILEGX_R52_REGNUM, REVERSE_STATE_REGISTER },
128 { TILEGX_TP_REGNUM, REVERSE_STATE_REGISTER },
129 { TILEGX_SP_REGNUM, REVERSE_STATE_REGISTER },
130 { TILEGX_LR_REGNUM, REVERSE_STATE_REGISTER },
131 { 0, REVERSE_STATE_UNKNOWN },
132 { 0, REVERSE_STATE_UNKNOWN },
133 { 0, REVERSE_STATE_UNKNOWN },
134 { 0, REVERSE_STATE_UNKNOWN },
135 { 0, REVERSE_STATE_UNKNOWN },
136 { 0, REVERSE_STATE_UNKNOWN },
137 { 0, REVERSE_STATE_UNKNOWN },
138 { TILEGX_ZERO_REGNUM, REVERSE_STATE_VALUE }
139 };
140
141/* Implement the "register_name" gdbarch method. */
142
143static const char *
144tilegx_register_name (struct gdbarch *gdbarch, int regnum)
145{
146 static const char *const register_names[TILEGX_NUM_REGS] =
147 {
148 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
149 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
150 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
151 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
152 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
153 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
154 "r48", "r49", "r50", "r51", "r52", "tp", "sp", "lr",
155 "sn", "idn0", "idn1", "udn0", "udn1", "udn2", "udn3", "zero",
4aaf2503 156 "pc", "faultnum",
ade64f0e
PA		 157 };
158
159 if (regnum < 0 || regnum >= TILEGX_NUM_REGS)
160 internal_error (__FILE__, __LINE__,
161 "tilegx_register_name: invalid register number %d",
162 regnum);
163
164 return register_names[regnum];
165}
166
167/* This is the implementation of gdbarch method register_type. */
168
169static struct type *
170tilegx_register_type (struct gdbarch *gdbarch, int regnum)
171{
172 if (regnum == TILEGX_PC_REGNUM)
173 return builtin_type (gdbarch)->builtin_func_ptr;
174 else
175 return builtin_type (gdbarch)->builtin_uint64;
176}
177
178/* This is the implementation of gdbarch method dwarf2_reg_to_regnum. */
179
180static int
181tilegx_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
182{
183 return num;
184}
185
186/* Makes the decision of whether a given type is a scalar type.
187 Scalar types are returned in the registers r2-r11 as they fit. */
188
189static int
190tilegx_type_is_scalar (struct type *t)
191{
192 return (TYPE_CODE(t) != TYPE_CODE_STRUCT
193 && TYPE_CODE(t) != TYPE_CODE_UNION
194 && TYPE_CODE(t) != TYPE_CODE_ARRAY);
195}
196
197/* Returns non-zero if the given struct type will be returned using
198 a special convention, rather than the normal function return method.
199 Used in the context of the "return" command, and target function
200 calls from the debugger. */
201
202static int
203tilegx_use_struct_convention (struct type *type)
204{
205 /* Only scalars which fit in R0 - R9 can be returned in registers.
206 Otherwise, they are returned via a pointer passed in R0. */
207 return (!tilegx_type_is_scalar (type)
208 && (TYPE_LENGTH (type) > (1 + TILEGX_R9_REGNUM - TILEGX_R0_REGNUM)
209 * tilegx_reg_size));
210}
211
212/* Find a function's return value in the appropriate registers (in
213 REGCACHE), and copy it into VALBUF. */
214
215static void
216tilegx_extract_return_value (struct type *type, struct regcache *regcache,
217 gdb_byte *valbuf)
218{
219 int len = TYPE_LENGTH (type);
220 int i, regnum = TILEGX_R0_REGNUM;
221
222 for (i = 0; i < len; i += tilegx_reg_size)
223 regcache_raw_read (regcache, regnum++, valbuf + i);
224}
225
226/* Copy the function return value from VALBUF into the proper
227 location for a function return.
228 Called only in the context of the "return" command. */
229
230static void
231tilegx_store_return_value (struct type *type, struct regcache *regcache,
232 const void *valbuf)
233{
234 if (TYPE_LENGTH (type) < tilegx_reg_size)
235 {
236 /* Add leading zeros to the (little-endian) value. */
237 gdb_byte buf[tilegx_reg_size] = { 0 };
238
239 memcpy (buf, valbuf, TYPE_LENGTH (type));
240 regcache_raw_write (regcache, TILEGX_R0_REGNUM, buf);
241 }
242 else
243 {
244 int len = TYPE_LENGTH (type);
245 int i, regnum = TILEGX_R0_REGNUM;
246
247 for (i = 0; i < len; i += tilegx_reg_size)
248 regcache_raw_write (regcache, regnum++, (gdb_byte *) valbuf + i);
249 }
250}
251
252/* This is the implementation of gdbarch method return_value. */
253
254static enum return_value_convention
255tilegx_return_value (struct gdbarch *gdbarch, struct value *function,
256 struct type *type, struct regcache *regcache,
257 gdb_byte *readbuf, const gdb_byte *writebuf)
258{
259 if (tilegx_use_struct_convention (type))
260 return RETURN_VALUE_STRUCT_CONVENTION;
261 if (writebuf)
262 tilegx_store_return_value (type, regcache, writebuf);
263 else if (readbuf)
264 tilegx_extract_return_value (type, regcache, readbuf);
265 return RETURN_VALUE_REGISTER_CONVENTION;
266}
267
268/* This is the implementation of gdbarch method frame_align. */
269
270static CORE_ADDR
271tilegx_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
272{
273 return addr & -8;
274}
275
276
277/* Implement the "push_dummy_call" gdbarch method. */
278
279static CORE_ADDR
280tilegx_push_dummy_call (struct gdbarch *gdbarch,
281 struct value *function,
282 struct regcache *regcache,
283 CORE_ADDR bp_addr, int nargs,
284 struct value **args,
285 CORE_ADDR sp, int struct_return,
286 CORE_ADDR struct_addr)
287{
288 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
289 CORE_ADDR stack_dest = sp;
290 int argreg = TILEGX_R0_REGNUM;
291 int i, j;
870f88f7 292 int typelen, slacklen;
bc23a956 293 static const gdb_byte four_zero_words[16] = { 0 };
ade64f0e
PA		 294
295 /* If struct_return is 1, then the struct return address will
296 consume one argument-passing register. */
297 if (struct_return)
298 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
299
300 /* Arguments are passed in R0 - R9, and as soon as an argument
301 will not fit completely in the remaining registers, then it,
302 and all remaining arguments, are put on the stack. */
303 for (i = 0; i < nargs && argreg <= TILEGX_R9_REGNUM; i++)
304 {
305 const gdb_byte *val;
306 typelen = TYPE_LENGTH (value_enclosing_type (args[i]));
307
308 if (typelen > (TILEGX_R9_REGNUM - argreg + 1) * tilegx_reg_size)
309 break;
310
311 /* Put argument into registers wordwise. */
312 val = value_contents (args[i]);
313 for (j = 0; j < typelen; j += tilegx_reg_size)
314 {
315 /* ISSUE: Why special handling for "typelen = 4x + 1"?
316 I don't ever see "typelen" values except 4 and 8. */
317 int n = (typelen - j == 1) ? 1 : tilegx_reg_size;
318 ULONGEST w = extract_unsigned_integer (val + j, n, byte_order);
319
320 regcache_cooked_write_unsigned (regcache, argreg++, w);
321 }
322 }
323
324 /* Align SP. */
325 stack_dest = tilegx_frame_align (gdbarch, stack_dest);
326
ade64f0e
PA		 327 /* Loop backwards through remaining arguments and push them on
328 the stack, word aligned. */
329 for (j = nargs - 1; j >= i; j--)
330 {
331 gdb_byte *val;
ecfb0d68
SP		 332 struct cleanup *back_to;
333 const gdb_byte *contents = value_contents (args[j]);
ade64f0e
PA		 334
335 typelen = TYPE_LENGTH (value_enclosing_type (args[j]));
bc23a956 336 slacklen = align_up (typelen, 8) - typelen;
224c3ddb 337 val = (gdb_byte *) xmalloc (typelen + slacklen);
ecfb0d68
SP		 338 back_to = make_cleanup (xfree, val);
339 memcpy (val, contents, typelen);
ade64f0e
PA		 340 memset (val + typelen, 0, slacklen);
341
342 /* Now write data to the stack. The stack grows downwards. */
343 stack_dest -= typelen + slacklen;
344 write_memory (stack_dest, val, typelen + slacklen);
ecfb0d68 345 do_cleanups (back_to);
ade64f0e
PA		 346 }
347
bc23a956
WL		 348 /* Add 16 bytes for linkage space to the stack. */
349 stack_dest = stack_dest - 16;
350 write_memory (stack_dest, four_zero_words, 16);
ade64f0e
PA		 351
352 /* Update stack pointer. */
353 regcache_cooked_write_unsigned (regcache, TILEGX_SP_REGNUM, stack_dest);
354
355 /* Set the return address register to point to the entry point of
356 the program, where a breakpoint lies in wait. */
357 regcache_cooked_write_unsigned (regcache, TILEGX_LR_REGNUM, bp_addr);
358
359 return stack_dest;
360}
361
362
363/* Decode the instructions within the given address range.
364 Decide when we must have reached the end of the function prologue.
365 If a frame_info pointer is provided, fill in its saved_regs etc.
366 Returns the address of the first instruction after the prologue.
367 NOTE: This is often called with start_addr being the start of some
368 function, and end_addr being the current PC. */
369
370static CORE_ADDR
371tilegx_analyze_prologue (struct gdbarch* gdbarch,
372 CORE_ADDR start_addr, CORE_ADDR end_addr,
373 struct tilegx_frame_cache *cache,
374 struct frame_info *next_frame)
375{
376 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
377 CORE_ADDR next_addr;
378 CORE_ADDR prolog_end = end_addr;
ade64f0e
PA		 379 gdb_byte instbuf[32 * TILEGX_BUNDLE_SIZE_IN_BYTES];
380 CORE_ADDR instbuf_start;
381 unsigned int instbuf_size;
382 int status;
383 bfd_uint64_t bundle;
384 struct tilegx_decoded_instruction
385 decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE];
386 int num_insns;
387 struct tilegx_reverse_regs reverse_frame[TILEGX_NUM_PHYS_REGS];
388 struct tilegx_reverse_regs
389 new_reverse_frame[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE];
390 int dest_regs[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE];
3361b059 391 int reverse_frame_valid, prolog_done, branch_seen, lr_saved_on_stack_p;
ade64f0e
PA		 392 LONGEST prev_sp_value;
393 int i, j;
394
395 if (start_addr >= end_addr
396 || (start_addr % TILEGX_BUNDLE_ALIGNMENT_IN_BYTES) != 0)
397 return end_addr;
398
399 /* Initialize the reverse frame. This maps the CURRENT frame's
400 registers to the outer frame's registers (the frame on the
401 stack goes the other way). */
402 memcpy (&reverse_frame, &template_reverse_regs, sizeof (reverse_frame));
403
404 prolog_done = 0;
405 branch_seen = 0;
406 prev_sp_value = 0;
3361b059 407 lr_saved_on_stack_p = 0;
ade64f0e
PA		 408
409 /* To cut down on round-trip overhead, we fetch multiple bundles
410 at once. These variables describe the range of memory we have
411 prefetched. */
412 instbuf_start = 0;
413 instbuf_size = 0;
414
415 for (next_addr = start_addr;
416 next_addr < end_addr;
417 next_addr += TILEGX_BUNDLE_SIZE_IN_BYTES)
418 {
419 /* Retrieve the next instruction. */
420 if (next_addr - instbuf_start >= instbuf_size)
421 {
422 /* Figure out how many bytes to fetch. Don't span a page
423 boundary since that might cause an unnecessary memory
424 error. */
425 unsigned int size_on_same_page = 4096 - (next_addr & 4095);
426
427 instbuf_size = sizeof instbuf;
428
429 if (instbuf_size > size_on_same_page)
430 instbuf_size = size_on_same_page;
d79e58d8 431
325fac50
PA		 432 instbuf_size = std::min ((CORE_ADDR) instbuf_size,
433 (end_addr - next_addr));
ade64f0e
PA		 434 instbuf_start = next_addr;
435
436 status = safe_frame_unwind_memory (next_frame, instbuf_start,
437 instbuf, instbuf_size);
438 if (status == 0)
f486487f 439 memory_error (TARGET_XFER_E_IO, next_addr);
ade64f0e
PA		 440 }
441
442 reverse_frame_valid = 0;
443
444 bundle = extract_unsigned_integer (&instbuf[next_addr - instbuf_start],
445 8, byte_order);
446
447 num_insns = parse_insn_tilegx (bundle, next_addr, decoded);
448
449 for (i = 0; i < num_insns; i++)
450 {
451 struct tilegx_decoded_instruction *this_insn = &decoded[i];
452 int64_t *operands = (int64_t *) this_insn->operand_values;
453 const struct tilegx_opcode *opcode = this_insn->opcode;
454
455 switch (opcode->mnemonic)
456 {
457 case TILEGX_OPC_ST:
458 if (cache
459 && reverse_frame[operands[0]].state == REVERSE_STATE_VALUE
460 && reverse_frame[operands[1]].state
461 == REVERSE_STATE_REGISTER)
462 {
463 LONGEST saved_address = reverse_frame[operands[0]].value;
464 unsigned saved_register
465 = (unsigned) reverse_frame[operands[1]].value;
466
467 /* realreg >= 0 and addr != -1 indicates that the
468 value of saved_register is in memory location
469 saved_address. The value of realreg is not
470 meaningful in this case but it must be >= 0.
471 See trad-frame.h. */
472 cache->saved_regs[saved_register].realreg = saved_register;
473 cache->saved_regs[saved_register].addr = saved_address;
3361b059
WL		 474 }
475 else if (cache
476 && (operands[0] == TILEGX_SP_REGNUM)
477 && (operands[1] == TILEGX_LR_REGNUM))
478 lr_saved_on_stack_p = 1;
ade64f0e
PA		 479 break;
480 case TILEGX_OPC_ADDI:
481 case TILEGX_OPC_ADDLI:
482 if (cache
483 && operands[0] == TILEGX_SP_REGNUM
484 && operands[1] == TILEGX_SP_REGNUM
485 && reverse_frame[operands[1]].state == REVERSE_STATE_REGISTER)
486 {
487 /* Special case. We're fixing up the stack frame. */
488 uint64_t hopefully_sp
489 = (unsigned) reverse_frame[operands[1]].value;
490 short op2_as_short = (short) operands[2];
491 signed char op2_as_char = (signed char) operands[2];
492
493 /* Fix up the sign-extension. */
494 if (opcode->mnemonic == TILEGX_OPC_ADDI)
495 op2_as_short = op2_as_char;
496 prev_sp_value = (cache->saved_regs[hopefully_sp].addr
497 - op2_as_short);
498
499 new_reverse_frame[i].state = REVERSE_STATE_VALUE;
500 new_reverse_frame[i].value
501 = cache->saved_regs[hopefully_sp].addr;
502 trad_frame_set_value (cache->saved_regs,
503 hopefully_sp, prev_sp_value);
504 }
505 else
506 {
507 short op2_as_short = (short) operands[2];
508 signed char op2_as_char = (signed char) operands[2];
509
510 /* Fix up the sign-extension. */
511 if (opcode->mnemonic == TILEGX_OPC_ADDI)
512 op2_as_short = op2_as_char;
513
514 new_reverse_frame[i] = reverse_frame[operands[1]];
515 if (new_reverse_frame[i].state == REVERSE_STATE_VALUE)
516 new_reverse_frame[i].value += op2_as_short;
517 else
518 new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN;
519 }
520 reverse_frame_valid |= 1 << i;
521 dest_regs[i] = operands[0];
522 break;
523 case TILEGX_OPC_ADD:
524 if (reverse_frame[operands[1]].state == REVERSE_STATE_VALUE
525 && reverse_frame[operands[2]].state == REVERSE_STATE_VALUE)
526 {
527 /* We have values -- we can do this. */
528 new_reverse_frame[i] = reverse_frame[operands[2]];
529 new_reverse_frame[i].value
530 += reverse_frame[operands[i]].value;
531 }
532 else
533 {
534 /* We don't know anything about the values. Punt. */
535 new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN;
536 }
537 reverse_frame_valid |= 1 << i;
538 dest_regs[i] = operands[0];
539 break;
540 case TILEGX_OPC_MOVE:
541 new_reverse_frame[i] = reverse_frame[operands[1]];
542 reverse_frame_valid |= 1 << i;
543 dest_regs[i] = operands[0];
544 break;
545 case TILEGX_OPC_MOVEI:
546 case TILEGX_OPC_MOVELI:
547 new_reverse_frame[i].state = REVERSE_STATE_VALUE;
548 new_reverse_frame[i].value = operands[1];
549 reverse_frame_valid |= 1 << i;
550 dest_regs[i] = operands[0];
551 break;
552 case TILEGX_OPC_ORI:
553 if (reverse_frame[operands[1]].state == REVERSE_STATE_VALUE)
554 {
555 /* We have a value in A -- we can do this. */
556 new_reverse_frame[i] = reverse_frame[operands[1]];
557 new_reverse_frame[i].value
558 = reverse_frame[operands[1]].value | operands[2];
559 }
560 else if (operands[2] == 0)
561 {
562 /* This is a move. */
563 new_reverse_frame[i] = reverse_frame[operands[1]];
564 }
565 else
566 {
567 /* We don't know anything about the values. Punt. */
568 new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN;
569 }
570 reverse_frame_valid |= 1 << i;
571 dest_regs[i] = operands[0];
572 break;
573 case TILEGX_OPC_OR:
574 if (reverse_frame[operands[1]].state == REVERSE_STATE_VALUE
575 && reverse_frame[operands[1]].value == 0)
576 {
577 /* This is a move. */
578 new_reverse_frame[i] = reverse_frame[operands[2]];
579 }
580 else if (reverse_frame[operands[2]].state == REVERSE_STATE_VALUE
581 && reverse_frame[operands[2]].value == 0)
582 {
583 /* This is a move. */
584 new_reverse_frame[i] = reverse_frame[operands[1]];
585 }
586 else
587 {
588 /* We don't know anything about the values. Punt. */
589 new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN;
590 }
591 reverse_frame_valid |= 1 << i;
592 dest_regs[i] = operands[0];
593 break;
594 case TILEGX_OPC_SUB:
595 if (reverse_frame[operands[1]].state == REVERSE_STATE_VALUE
596 && reverse_frame[operands[2]].state == REVERSE_STATE_VALUE)
597 {
598 /* We have values -- we can do this. */
599 new_reverse_frame[i] = reverse_frame[operands[1]];
600 new_reverse_frame[i].value
601 -= reverse_frame[operands[2]].value;
602 }
603 else
604 {
605 /* We don't know anything about the values. Punt. */
606 new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN;
607 }
608 reverse_frame_valid |= 1 << i;
609 dest_regs[i] = operands[0];
610 break;
611
612 case TILEGX_OPC_FNOP:
613 case TILEGX_OPC_INFO:
614 case TILEGX_OPC_INFOL:
615 /* Nothing to see here, move on.
616 Note that real NOP is treated as a 'real' instruction
617 because someone must have intended that it be there.
618 It therefore terminates the prolog. */
619 break;
620
621 case TILEGX_OPC_J:
622 case TILEGX_OPC_JAL:
623
624 case TILEGX_OPC_BEQZ:
625 case TILEGX_OPC_BEQZT:
626 case TILEGX_OPC_BGEZ:
627 case TILEGX_OPC_BGEZT:
628 case TILEGX_OPC_BGTZ:
629 case TILEGX_OPC_BGTZT:
630 case TILEGX_OPC_BLBC:
631 case TILEGX_OPC_BLBCT:
632 case TILEGX_OPC_BLBS:
633 case TILEGX_OPC_BLBST:
634 case TILEGX_OPC_BLEZ:
635 case TILEGX_OPC_BLEZT:
636 case TILEGX_OPC_BLTZ:
637 case TILEGX_OPC_BLTZT:
638 case TILEGX_OPC_BNEZ:
639 case TILEGX_OPC_BNEZT:
640
641 case TILEGX_OPC_IRET:
642 case TILEGX_OPC_JALR:
643 case TILEGX_OPC_JALRP:
644 case TILEGX_OPC_JR:
645 case TILEGX_OPC_JRP:
646 case TILEGX_OPC_SWINT0:
647 case TILEGX_OPC_SWINT1:
648 case TILEGX_OPC_SWINT2:
649 case TILEGX_OPC_SWINT3:
650 /* We're really done -- this is a branch. */
651 branch_seen = 1;
652 prolog_done = 1;
653 break;
654 default:
655 /* We don't know or care what this instruction is.
656 All we know is that it isn't part of a prolog, and if
657 there's a destination register, we're trashing it. */
658 prolog_done = 1;
659 for (j = 0; j < opcode->num_operands; j++)
660 {
661 if (this_insn->operands[j]->is_dest_reg)
662 {
663 dest_regs[i] = operands[j];
664 new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN;
665 reverse_frame_valid |= 1 << i;
666 break;
667 }
668 }
669 break;
670 }
671 }
672
673 /* Now update the reverse frames. */
674 for (i = 0; i < num_insns; i++)
675 {
676 /* ISSUE: Does this properly handle "network" registers? */
677 if ((reverse_frame_valid & (1 << i))
678 && dest_regs[i] != TILEGX_ZERO_REGNUM)
679 reverse_frame[dest_regs[i]] = new_reverse_frame[i];
680 }
681
682 if (prev_sp_value != 0)
683 {
684 /* GCC uses R52 as a frame pointer. Have we seen "move r52, sp"? */
685 if (reverse_frame[TILEGX_R52_REGNUM].state == REVERSE_STATE_REGISTER
686 && reverse_frame[TILEGX_R52_REGNUM].value == TILEGX_SP_REGNUM)
687 {
688 reverse_frame[TILEGX_R52_REGNUM].state = REVERSE_STATE_VALUE;
689 reverse_frame[TILEGX_R52_REGNUM].value = prev_sp_value;
690 }
691
692 prev_sp_value = 0;
693 }
694
695 if (prolog_done && prolog_end == end_addr)
696 {
697 /* We found non-prolog code. As such, _this_ instruction
698 is the one after the prolog. We keep processing, because
699 there may be more prolog code in there, but this is what
700 we'll return. */
701 /* ISSUE: There may not have actually been a prologue, and
702 we may have simply skipped some random instructions. */
703 prolog_end = next_addr;
704 }
705 if (branch_seen)
706 {
707 /* We saw a branch. The prolog absolutely must be over. */
708 break;
709 }
710 }
711
712 if (prolog_end == end_addr && cache)
713 {
714 /* We may have terminated the prolog early, and we're certainly
715 at THIS point right now. It's possible that the values of
716 registers we need are currently actually in other registers
717 (and haven't been written to memory yet). Go find them. */
718 for (i = 0; i < TILEGX_NUM_PHYS_REGS; i++)
719 {
720 if (reverse_frame[i].state == REVERSE_STATE_REGISTER
721 && reverse_frame[i].value != i)
722 {
723 unsigned saved_register = (unsigned) reverse_frame[i].value;
724
725 cache->saved_regs[saved_register].realreg = i;
726 cache->saved_regs[saved_register].addr = (LONGEST) -1;
727 }
728 }
729 }
730
3361b059
WL		 731 if (lr_saved_on_stack_p)
732 {
733 cache->saved_regs[TILEGX_LR_REGNUM].realreg = TILEGX_LR_REGNUM;
734 cache->saved_regs[TILEGX_LR_REGNUM].addr =
735 cache->saved_regs[TILEGX_SP_REGNUM].addr;
736 }
737
ade64f0e
PA		 738 return prolog_end;
739}
740
741/* This is the implementation of gdbarch method skip_prologue. */
742
743static CORE_ADDR
3e9d5130 744tilegx_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
ade64f0e 745{
d79e58d8
JW		 746 CORE_ADDR func_start, end_pc;
747 struct obj_section *s;
ade64f0e
PA		 748
749 /* This is the preferred method, find the end of the prologue by
750 using the debugging information. */
3e9d5130 751 if (find_pc_partial_function (start_pc, NULL, &func_start, NULL))
ade64f0e 752 {
3e9d5130
WL		 753 CORE_ADDR post_prologue_pc
754 = skip_prologue_using_sal (gdbarch, func_start);
ade64f0e 755
3e9d5130 756 if (post_prologue_pc != 0)
325fac50 757 return std::max (start_pc, post_prologue_pc);
ade64f0e
PA		 758 }
759
d79e58d8
JW		 760 /* Don't straddle a section boundary. */
761 s = find_pc_section (start_pc);
762 end_pc = start_pc + 8 * TILEGX_BUNDLE_SIZE_IN_BYTES;
763 if (s != NULL)
325fac50 764 end_pc = std::min (end_pc, obj_section_endaddr (s));
d79e58d8 765
ade64f0e
PA		 766 /* Otherwise, try to skip prologue the hard way. */
767 return tilegx_analyze_prologue (gdbarch,
3e9d5130 768 start_pc,
d79e58d8 769 end_pc,
ade64f0e
PA		 770 NULL, NULL);
771}
772
c9cf6e20 773/* This is the implementation of gdbarch method stack_frame_destroyed_p. */
ade64f0e
PA		 774
775static int
c9cf6e20 776tilegx_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
ade64f0e
PA		 777{
778 CORE_ADDR func_addr = 0, func_end = 0;
779
780 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
781 {
ade64f0e
PA		 782 CORE_ADDR addr = func_end - TILEGX_BUNDLE_SIZE_IN_BYTES;
783
784 /* FIXME: Find the actual epilogue. */
785 /* HACK: Just assume the final bundle is the "ret" instruction". */
786 if (pc > addr)
787 return 1;
788 }
789 return 0;
790}
791
61d8bd0e
JW		 792/* This is the implementation of gdbarch method get_longjmp_target. */
793
794static int
795tilegx_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
796{
797 struct gdbarch *gdbarch = get_frame_arch (frame);
798 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
799 CORE_ADDR jb_addr;
800 gdb_byte buf[8];
801
802 jb_addr = get_frame_register_unsigned (frame, TILEGX_R0_REGNUM);
803
804 /* TileGX jmp_buf contains 32 elements of type __uint_reg_t which
805 has a size of 8 bytes. The return address is stored in the 25th
806 slot. */
807 if (target_read_memory (jb_addr + 25 * 8, buf, 8))
808 return 0;
809
810 *pc = extract_unsigned_integer (buf, 8, byte_order);
811
812 return 1;
813}
814
4aaf2503
WL		 815/* by assigning the 'faultnum' reg in kernel pt_regs with this value,
816 kernel do_signal will not check r0. see tilegx kernel/signal.c
817 for details. */
818#define INT_SWINT_1_SIGRETURN (~0)
819
820/* Implement the "write_pc" gdbarch method. */
821
822static void
823tilegx_write_pc (struct regcache *regcache, CORE_ADDR pc)
824{
825 regcache_cooked_write_unsigned (regcache, TILEGX_PC_REGNUM, pc);
826
827 /* We must be careful with modifying the program counter. If we
828 just interrupted a system call, the kernel might try to restart
829 it when we resume the inferior. On restarting the system call,
830 the kernel will try backing up the program counter even though it
831 no longer points at the system call. This typically results in a
832 SIGSEGV or SIGILL. We can prevent this by writing INT_SWINT_1_SIGRETURN
833 in the "faultnum" pseudo-register.
834
835 Note that "faultnum" is saved when setting up a dummy call frame.
836 This means that it is properly restored when that frame is
837 popped, and that the interrupted system call will be restarted
838 when we resume the inferior on return from a function call from
839 within GDB. In all other cases the system call will not be
840 restarted. */
841 regcache_cooked_write_unsigned (regcache, TILEGX_FAULTNUM_REGNUM,
842 INT_SWINT_1_SIGRETURN);
843}
844
ade64f0e
PA		 845/* This is the implementation of gdbarch method breakpoint_from_pc. */
846
847static const unsigned char *
848tilegx_breakpoint_from_pc (struct gdbarch *gdbarch,
849 CORE_ADDR *pcptr, int *lenptr)
850{
851 /* 64-bit pattern for a { bpt ; nop } bundle. */
852 static const unsigned char breakpoint[] =
853 { 0x00, 0x50, 0x48, 0x51, 0xae, 0x44, 0x6a, 0x28 };
854
855 *lenptr = sizeof (breakpoint);
856 return breakpoint;
857}
858
859/* Normal frames. */
860
861static struct tilegx_frame_cache *
862tilegx_frame_cache (struct frame_info *this_frame, void **this_cache)
863{
864 struct gdbarch *gdbarch = get_frame_arch (this_frame);
865 struct tilegx_frame_cache *cache;
866 CORE_ADDR current_pc;
ade64f0e
PA		 867
868 if (*this_cache)
19ba03f4 869 return (struct tilegx_frame_cache *) *this_cache;
ade64f0e
PA		 870
871 cache = FRAME_OBSTACK_ZALLOC (struct tilegx_frame_cache);
872 *this_cache = cache;
873 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
874 cache->base = 0;
875 cache->start_pc = get_frame_func (this_frame);
876 current_pc = get_frame_pc (this_frame);
877
878 cache->base = get_frame_register_unsigned (this_frame, TILEGX_SP_REGNUM);
879 trad_frame_set_value (cache->saved_regs, TILEGX_SP_REGNUM, cache->base);
880
ade64f0e
PA		 881 if (cache->start_pc)
882 tilegx_analyze_prologue (gdbarch, cache->start_pc, current_pc,
883 cache, this_frame);
884
3361b059
WL		 885 cache->saved_regs[TILEGX_PC_REGNUM] = cache->saved_regs[TILEGX_LR_REGNUM];
886
ade64f0e
PA		 887 return cache;
888}
889
890/* Retrieve the value of REGNUM in FRAME. */
891
892static struct value*
893tilegx_frame_prev_register (struct frame_info *this_frame,
894 void **this_cache,
895 int regnum)
896{
897 struct tilegx_frame_cache *info =
898 tilegx_frame_cache (this_frame, this_cache);
899
900 return trad_frame_get_prev_register (this_frame, info->saved_regs,
901 regnum);
902}
903
904/* Build frame id. */
905
906static void
907tilegx_frame_this_id (struct frame_info *this_frame, void **this_cache,
908 struct frame_id *this_id)
909{
910 struct tilegx_frame_cache *info =
911 tilegx_frame_cache (this_frame, this_cache);
912
913 /* This marks the outermost frame. */
914 if (info->base == 0)
915 return;
916
917 (*this_id) = frame_id_build (info->base, info->start_pc);
918}
919
920static CORE_ADDR
921tilegx_frame_base_address (struct frame_info *this_frame, void **this_cache)
922{
923 struct tilegx_frame_cache *cache =
924 tilegx_frame_cache (this_frame, this_cache);
925
926 return cache->base;
927}
928
929static const struct frame_unwind tilegx_frame_unwind = {
930 NORMAL_FRAME,
931 default_frame_unwind_stop_reason,
932 tilegx_frame_this_id,
933 tilegx_frame_prev_register,
934 NULL, /* const struct frame_data *unwind_data */
935 default_frame_sniffer, /* frame_sniffer_ftype *sniffer */
936 NULL /* frame_prev_pc_ftype *prev_pc */
937};
938
939static const struct frame_base tilegx_frame_base = {
940 &tilegx_frame_unwind,
941 tilegx_frame_base_address,
942 tilegx_frame_base_address,
943 tilegx_frame_base_address
944};
945
946static CORE_ADDR
947tilegx_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
948{
949 return frame_unwind_register_unsigned (next_frame, TILEGX_SP_REGNUM);
950}
951
952static CORE_ADDR
953tilegx_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
954{
955 return frame_unwind_register_unsigned (next_frame, TILEGX_PC_REGNUM);
956}
957
958static struct frame_id
959tilegx_unwind_dummy_id (struct gdbarch *gdbarch,
960 struct frame_info *this_frame)
961{
962 CORE_ADDR sp;
963
964 sp = get_frame_register_unsigned (this_frame, TILEGX_SP_REGNUM);
965 return frame_id_build (sp, get_frame_pc (this_frame));
966}
967
968
969/* We cannot read/write the "special" registers. */
970
971static int
972tilegx_cannot_reference_register (struct gdbarch *gdbarch, int regno)
973{
974 if (regno >= 0 && regno < TILEGX_NUM_EASY_REGS)
975 return 0;
4aaf2503
WL		 976 else if (regno == TILEGX_PC_REGNUM
977 || regno == TILEGX_FAULTNUM_REGNUM)
ade64f0e
PA		 978 return 0;
979 else
980 return 1;
981}
982
983static struct gdbarch *
984tilegx_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
985{
986 struct gdbarch *gdbarch;
987 int arch_size = 64;
988
989 /* Handle arch_size == 32 or 64. Default to 64. */
990 if (info.abfd)
991 arch_size = bfd_get_arch_size (info.abfd);
992
993 /* Try to find a pre-existing architecture. */
994 for (arches = gdbarch_list_lookup_by_info (arches, &info);
995 arches != NULL;
996 arches = gdbarch_list_lookup_by_info (arches->next, &info))
997 {
998 /* We only have two flavors -- just make sure arch_size matches. */
999 if (gdbarch_ptr_bit (arches->gdbarch) == arch_size)
1000 return (arches->gdbarch);
1001 }
1002
1003 gdbarch = gdbarch_alloc (&info, NULL);
1004
1005 /* Basic register fields and methods, datatype sizes and stuff. */
1006
1007 /* There are 64 physical registers which can be referenced by
1008 instructions (although only 56 of them can actually be
1009 debugged) and 1 magic register (the PC). The other three
1010 magic registers (ex1, syscall, orig_r0) which are known to
1011 "ptrace" are ignored by "gdb". Note that we simply pretend
1012 that there are 65 registers, and no "pseudo registers". */
1013 set_gdbarch_num_regs (gdbarch, TILEGX_NUM_REGS);
1014 set_gdbarch_num_pseudo_regs (gdbarch, 0);
1015
1016 set_gdbarch_sp_regnum (gdbarch, TILEGX_SP_REGNUM);
1017 set_gdbarch_pc_regnum (gdbarch, TILEGX_PC_REGNUM);
1018
1019 set_gdbarch_register_name (gdbarch, tilegx_register_name);
1020 set_gdbarch_register_type (gdbarch, tilegx_register_type);
1021
ade64f0e
PA		 1022 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
1023 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1024 set_gdbarch_long_bit (gdbarch, arch_size);
1025 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1026
1027 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1028 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1029 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1030
1031 set_gdbarch_ptr_bit (gdbarch, arch_size);
1032 set_gdbarch_addr_bit (gdbarch, arch_size);
1033
1034 set_gdbarch_cannot_fetch_register (gdbarch,
1035 tilegx_cannot_reference_register);
1036 set_gdbarch_cannot_store_register (gdbarch,
1037 tilegx_cannot_reference_register);
1038
1039 /* Stack grows down. */
1040 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1041
1042 /* Frame Info. */
1043 set_gdbarch_unwind_sp (gdbarch, tilegx_unwind_sp);
1044 set_gdbarch_unwind_pc (gdbarch, tilegx_unwind_pc);
1045 set_gdbarch_dummy_id (gdbarch, tilegx_unwind_dummy_id);
1046 set_gdbarch_frame_align (gdbarch, tilegx_frame_align);
1047 frame_base_set_default (gdbarch, &tilegx_frame_base);
1048
1049 set_gdbarch_skip_prologue (gdbarch, tilegx_skip_prologue);
1050
c9cf6e20 1051 set_gdbarch_stack_frame_destroyed_p (gdbarch, tilegx_stack_frame_destroyed_p);
ade64f0e
PA		 1052
1053 /* Map debug registers into internal register numbers. */
1054 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, tilegx_dwarf2_reg_to_regnum);
1055
1056 /* These values and methods are used when gdb calls a target function. */
1057 set_gdbarch_push_dummy_call (gdbarch, tilegx_push_dummy_call);
61d8bd0e 1058 set_gdbarch_get_longjmp_target (gdbarch, tilegx_get_longjmp_target);
4aaf2503 1059 set_gdbarch_write_pc (gdbarch, tilegx_write_pc);
ade64f0e
PA		 1060 set_gdbarch_breakpoint_from_pc (gdbarch, tilegx_breakpoint_from_pc);
1061 set_gdbarch_return_value (gdbarch, tilegx_return_value);
1062
1063 set_gdbarch_print_insn (gdbarch, print_insn_tilegx);
1064
1065 gdbarch_init_osabi (info, gdbarch);
1066
1067 dwarf2_append_unwinders (gdbarch);
1068 frame_unwind_append_unwinder (gdbarch, &tilegx_frame_unwind);
1069
1070 return gdbarch;
1071}
1072
1073/* Provide a prototype to silence -Wmissing-prototypes. */
1074extern initialize_file_ftype _initialize_tilegx_tdep;
1075
1076void
1077_initialize_tilegx_tdep (void)
1078{
1079 register_gdbarch_init (bfd_arch_tilegx, tilegx_gdbarch_init);
1080}
GDB Binutils - Deliverables
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