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2012-03-09 Hafiz Abid Qadeer <abidh@codesourcery.com>
[deliverable/binutils-gdb.git] / gdb / tilegx-tdep.c
CommitLineData
ade64f0e
PA		 1/* Target-dependent code for the Tilera TILE-Gx processor.
2
8acc9f48 3 Copyright (C) 2012-2013 Free Software Foundation, Inc.
ade64f0e
PA		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20#include "defs.h"
21#include "frame.h"
22#include "frame-base.h"
23#include "frame-unwind.h"
24#include "dwarf2-frame.h"
25#include "trad-frame.h"
26#include "symtab.h"
27#include "gdbtypes.h"
28#include "gdbcmd.h"
29#include "gdbcore.h"
30#include "value.h"
31#include "dis-asm.h"
32#include "inferior.h"
33#include "gdb_string.h"
34#include "gdb_assert.h"
35#include "arch-utils.h"
36#include "floatformat.h"
37#include "regcache.h"
38#include "regset.h"
39#include "doublest.h"
40#include "osabi.h"
41#include "linux-tdep.h"
42#include "objfiles.h"
43#include "solib-svr4.h"
44#include "symtab.h"
45#include "tilegx-tdep.h"
46#include "opcode/tilegx.h"
47
48struct tilegx_frame_cache
49{
50 /* Base address. */
51 CORE_ADDR base;
52 /* Function start. */
53 CORE_ADDR start_pc;
54
55 /* Table of saved registers. */
56 struct trad_frame_saved_reg *saved_regs;
57};
58
59/* Register state values used by analyze_prologue. */
60enum reverse_state
61 {
62 REVERSE_STATE_REGISTER,
63 REVERSE_STATE_VALUE,
64 REVERSE_STATE_UNKNOWN
65 };
66
67/* Register state used by analyze_prologue(). */
68struct tilegx_reverse_regs
69{
70 LONGEST value;
71 enum reverse_state state;
72};
73
74static const struct tilegx_reverse_regs
75template_reverse_regs[TILEGX_NUM_PHYS_REGS] =
76 {
77 { TILEGX_R0_REGNUM, REVERSE_STATE_REGISTER },
78 { TILEGX_R1_REGNUM, REVERSE_STATE_REGISTER },
79 { TILEGX_R2_REGNUM, REVERSE_STATE_REGISTER },
80 { TILEGX_R3_REGNUM, REVERSE_STATE_REGISTER },
81 { TILEGX_R4_REGNUM, REVERSE_STATE_REGISTER },
82 { TILEGX_R5_REGNUM, REVERSE_STATE_REGISTER },
83 { TILEGX_R6_REGNUM, REVERSE_STATE_REGISTER },
84 { TILEGX_R7_REGNUM, REVERSE_STATE_REGISTER },
85 { TILEGX_R8_REGNUM, REVERSE_STATE_REGISTER },
86 { TILEGX_R9_REGNUM, REVERSE_STATE_REGISTER },
87 { TILEGX_R10_REGNUM, REVERSE_STATE_REGISTER },
88 { TILEGX_R11_REGNUM, REVERSE_STATE_REGISTER },
89 { TILEGX_R12_REGNUM, REVERSE_STATE_REGISTER },
90 { TILEGX_R13_REGNUM, REVERSE_STATE_REGISTER },
91 { TILEGX_R14_REGNUM, REVERSE_STATE_REGISTER },
92 { TILEGX_R15_REGNUM, REVERSE_STATE_REGISTER },
93 { TILEGX_R16_REGNUM, REVERSE_STATE_REGISTER },
94 { TILEGX_R17_REGNUM, REVERSE_STATE_REGISTER },
95 { TILEGX_R18_REGNUM, REVERSE_STATE_REGISTER },
96 { TILEGX_R19_REGNUM, REVERSE_STATE_REGISTER },
97 { TILEGX_R20_REGNUM, REVERSE_STATE_REGISTER },
98 { TILEGX_R21_REGNUM, REVERSE_STATE_REGISTER },
99 { TILEGX_R22_REGNUM, REVERSE_STATE_REGISTER },
100 { TILEGX_R23_REGNUM, REVERSE_STATE_REGISTER },
101 { TILEGX_R24_REGNUM, REVERSE_STATE_REGISTER },
102 { TILEGX_R25_REGNUM, REVERSE_STATE_REGISTER },
103 { TILEGX_R26_REGNUM, REVERSE_STATE_REGISTER },
104 { TILEGX_R27_REGNUM, REVERSE_STATE_REGISTER },
105 { TILEGX_R28_REGNUM, REVERSE_STATE_REGISTER },
106 { TILEGX_R29_REGNUM, REVERSE_STATE_REGISTER },
107 { TILEGX_R30_REGNUM, REVERSE_STATE_REGISTER },
108 { TILEGX_R31_REGNUM, REVERSE_STATE_REGISTER },
109 { TILEGX_R32_REGNUM, REVERSE_STATE_REGISTER },
110 { TILEGX_R33_REGNUM, REVERSE_STATE_REGISTER },
111 { TILEGX_R34_REGNUM, REVERSE_STATE_REGISTER },
112 { TILEGX_R35_REGNUM, REVERSE_STATE_REGISTER },
113 { TILEGX_R36_REGNUM, REVERSE_STATE_REGISTER },
114 { TILEGX_R37_REGNUM, REVERSE_STATE_REGISTER },
115 { TILEGX_R38_REGNUM, REVERSE_STATE_REGISTER },
116 { TILEGX_R39_REGNUM, REVERSE_STATE_REGISTER },
117 { TILEGX_R40_REGNUM, REVERSE_STATE_REGISTER },
118 { TILEGX_R41_REGNUM, REVERSE_STATE_REGISTER },
119 { TILEGX_R42_REGNUM, REVERSE_STATE_REGISTER },
120 { TILEGX_R43_REGNUM, REVERSE_STATE_REGISTER },
121 { TILEGX_R44_REGNUM, REVERSE_STATE_REGISTER },
122 { TILEGX_R45_REGNUM, REVERSE_STATE_REGISTER },
123 { TILEGX_R46_REGNUM, REVERSE_STATE_REGISTER },
124 { TILEGX_R47_REGNUM, REVERSE_STATE_REGISTER },
125 { TILEGX_R48_REGNUM, REVERSE_STATE_REGISTER },
126 { TILEGX_R49_REGNUM, REVERSE_STATE_REGISTER },
127 { TILEGX_R50_REGNUM, REVERSE_STATE_REGISTER },
128 { TILEGX_R51_REGNUM, REVERSE_STATE_REGISTER },
129 { TILEGX_R52_REGNUM, REVERSE_STATE_REGISTER },
130 { TILEGX_TP_REGNUM, REVERSE_STATE_REGISTER },
131 { TILEGX_SP_REGNUM, REVERSE_STATE_REGISTER },
132 { TILEGX_LR_REGNUM, REVERSE_STATE_REGISTER },
133 { 0, REVERSE_STATE_UNKNOWN },
134 { 0, REVERSE_STATE_UNKNOWN },
135 { 0, REVERSE_STATE_UNKNOWN },
136 { 0, REVERSE_STATE_UNKNOWN },
137 { 0, REVERSE_STATE_UNKNOWN },
138 { 0, REVERSE_STATE_UNKNOWN },
139 { 0, REVERSE_STATE_UNKNOWN },
140 { TILEGX_ZERO_REGNUM, REVERSE_STATE_VALUE }
141 };
142
143/* Implement the "register_name" gdbarch method. */
144
145static const char *
146tilegx_register_name (struct gdbarch *gdbarch, int regnum)
147{
148 static const char *const register_names[TILEGX_NUM_REGS] =
149 {
150 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
151 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
152 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
153 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
154 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
155 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
156 "r48", "r49", "r50", "r51", "r52", "tp", "sp", "lr",
157 "sn", "idn0", "idn1", "udn0", "udn1", "udn2", "udn3", "zero",
4aaf2503 158 "pc", "faultnum",
ade64f0e
PA		 159 };
160
161 if (regnum < 0 || regnum >= TILEGX_NUM_REGS)
162 internal_error (__FILE__, __LINE__,
163 "tilegx_register_name: invalid register number %d",
164 regnum);
165
166 return register_names[regnum];
167}
168
169/* This is the implementation of gdbarch method register_type. */
170
171static struct type *
172tilegx_register_type (struct gdbarch *gdbarch, int regnum)
173{
174 if (regnum == TILEGX_PC_REGNUM)
175 return builtin_type (gdbarch)->builtin_func_ptr;
176 else
177 return builtin_type (gdbarch)->builtin_uint64;
178}
179
180/* This is the implementation of gdbarch method dwarf2_reg_to_regnum. */
181
182static int
183tilegx_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
184{
185 return num;
186}
187
188/* Makes the decision of whether a given type is a scalar type.
189 Scalar types are returned in the registers r2-r11 as they fit. */
190
191static int
192tilegx_type_is_scalar (struct type *t)
193{
194 return (TYPE_CODE(t) != TYPE_CODE_STRUCT
195 && TYPE_CODE(t) != TYPE_CODE_UNION
196 && TYPE_CODE(t) != TYPE_CODE_ARRAY);
197}
198
199/* Returns non-zero if the given struct type will be returned using
200 a special convention, rather than the normal function return method.
201 Used in the context of the "return" command, and target function
202 calls from the debugger. */
203
204static int
205tilegx_use_struct_convention (struct type *type)
206{
207 /* Only scalars which fit in R0 - R9 can be returned in registers.
208 Otherwise, they are returned via a pointer passed in R0. */
209 return (!tilegx_type_is_scalar (type)
210 && (TYPE_LENGTH (type) > (1 + TILEGX_R9_REGNUM - TILEGX_R0_REGNUM)
211 * tilegx_reg_size));
212}
213
214/* Find a function's return value in the appropriate registers (in
215 REGCACHE), and copy it into VALBUF. */
216
217static void
218tilegx_extract_return_value (struct type *type, struct regcache *regcache,
219 gdb_byte *valbuf)
220{
221 int len = TYPE_LENGTH (type);
222 int i, regnum = TILEGX_R0_REGNUM;
223
224 for (i = 0; i < len; i += tilegx_reg_size)
225 regcache_raw_read (regcache, regnum++, valbuf + i);
226}
227
228/* Copy the function return value from VALBUF into the proper
229 location for a function return.
230 Called only in the context of the "return" command. */
231
232static void
233tilegx_store_return_value (struct type *type, struct regcache *regcache,
234 const void *valbuf)
235{
236 if (TYPE_LENGTH (type) < tilegx_reg_size)
237 {
238 /* Add leading zeros to the (little-endian) value. */
239 gdb_byte buf[tilegx_reg_size] = { 0 };
240
241 memcpy (buf, valbuf, TYPE_LENGTH (type));
242 regcache_raw_write (regcache, TILEGX_R0_REGNUM, buf);
243 }
244 else
245 {
246 int len = TYPE_LENGTH (type);
247 int i, regnum = TILEGX_R0_REGNUM;
248
249 for (i = 0; i < len; i += tilegx_reg_size)
250 regcache_raw_write (regcache, regnum++, (gdb_byte *) valbuf + i);
251 }
252}
253
254/* This is the implementation of gdbarch method return_value. */
255
256static enum return_value_convention
257tilegx_return_value (struct gdbarch *gdbarch, struct value *function,
258 struct type *type, struct regcache *regcache,
259 gdb_byte *readbuf, const gdb_byte *writebuf)
260{
261 if (tilegx_use_struct_convention (type))
262 return RETURN_VALUE_STRUCT_CONVENTION;
263 if (writebuf)
264 tilegx_store_return_value (type, regcache, writebuf);
265 else if (readbuf)
266 tilegx_extract_return_value (type, regcache, readbuf);
267 return RETURN_VALUE_REGISTER_CONVENTION;
268}
269
270/* This is the implementation of gdbarch method frame_align. */
271
272static CORE_ADDR
273tilegx_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
274{
275 return addr & -8;
276}
277
278
279/* Implement the "push_dummy_call" gdbarch method. */
280
281static CORE_ADDR
282tilegx_push_dummy_call (struct gdbarch *gdbarch,
283 struct value *function,
284 struct regcache *regcache,
285 CORE_ADDR bp_addr, int nargs,
286 struct value **args,
287 CORE_ADDR sp, int struct_return,
288 CORE_ADDR struct_addr)
289{
290 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
291 CORE_ADDR stack_dest = sp;
292 int argreg = TILEGX_R0_REGNUM;
293 int i, j;
294 int typelen, slacklen, alignlen;
bc23a956 295 static const gdb_byte four_zero_words[16] = { 0 };
ade64f0e
PA		 296
297 /* If struct_return is 1, then the struct return address will
298 consume one argument-passing register. */
299 if (struct_return)
300 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
301
302 /* Arguments are passed in R0 - R9, and as soon as an argument
303 will not fit completely in the remaining registers, then it,
304 and all remaining arguments, are put on the stack. */
305 for (i = 0; i < nargs && argreg <= TILEGX_R9_REGNUM; i++)
306 {
307 const gdb_byte *val;
308 typelen = TYPE_LENGTH (value_enclosing_type (args[i]));
309
310 if (typelen > (TILEGX_R9_REGNUM - argreg + 1) * tilegx_reg_size)
311 break;
312
313 /* Put argument into registers wordwise. */
314 val = value_contents (args[i]);
315 for (j = 0; j < typelen; j += tilegx_reg_size)
316 {
317 /* ISSUE: Why special handling for "typelen = 4x + 1"?
318 I don't ever see "typelen" values except 4 and 8. */
319 int n = (typelen - j == 1) ? 1 : tilegx_reg_size;
320 ULONGEST w = extract_unsigned_integer (val + j, n, byte_order);
321
322 regcache_cooked_write_unsigned (regcache, argreg++, w);
323 }
324 }
325
326 /* Align SP. */
327 stack_dest = tilegx_frame_align (gdbarch, stack_dest);
328
ade64f0e
PA		 329 /* Loop backwards through remaining arguments and push them on
330 the stack, word aligned. */
331 for (j = nargs - 1; j >= i; j--)
332 {
333 gdb_byte *val;
ecfb0d68
SP		 334 struct cleanup *back_to;
335 const gdb_byte *contents = value_contents (args[j]);
ade64f0e
PA		 336
337 typelen = TYPE_LENGTH (value_enclosing_type (args[j]));
bc23a956 338 slacklen = align_up (typelen, 8) - typelen;
ecfb0d68
SP		 339 val = xmalloc (typelen + slacklen);
340 back_to = make_cleanup (xfree, val);
341 memcpy (val, contents, typelen);
ade64f0e
PA		 342 memset (val + typelen, 0, slacklen);
343
344 /* Now write data to the stack. The stack grows downwards. */
345 stack_dest -= typelen + slacklen;
346 write_memory (stack_dest, val, typelen + slacklen);
ecfb0d68 347 do_cleanups (back_to);
ade64f0e
PA		 348 }
349
bc23a956
WL		 350 /* Add 16 bytes for linkage space to the stack. */
351 stack_dest = stack_dest - 16;
352 write_memory (stack_dest, four_zero_words, 16);
ade64f0e
PA		 353
354 /* Update stack pointer. */
355 regcache_cooked_write_unsigned (regcache, TILEGX_SP_REGNUM, stack_dest);
356
357 /* Set the return address register to point to the entry point of
358 the program, where a breakpoint lies in wait. */
359 regcache_cooked_write_unsigned (regcache, TILEGX_LR_REGNUM, bp_addr);
360
361 return stack_dest;
362}
363
364
365/* Decode the instructions within the given address range.
366 Decide when we must have reached the end of the function prologue.
367 If a frame_info pointer is provided, fill in its saved_regs etc.
368 Returns the address of the first instruction after the prologue.
369 NOTE: This is often called with start_addr being the start of some
370 function, and end_addr being the current PC. */
371
372static CORE_ADDR
373tilegx_analyze_prologue (struct gdbarch* gdbarch,
374 CORE_ADDR start_addr, CORE_ADDR end_addr,
375 struct tilegx_frame_cache *cache,
376 struct frame_info *next_frame)
377{
378 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
379 CORE_ADDR next_addr;
380 CORE_ADDR prolog_end = end_addr;
381 ULONGEST inst, inst2;
382 LONGEST offset;
383 int regnum;
384 gdb_byte instbuf[32 * TILEGX_BUNDLE_SIZE_IN_BYTES];
385 CORE_ADDR instbuf_start;
386 unsigned int instbuf_size;
387 int status;
388 bfd_uint64_t bundle;
389 struct tilegx_decoded_instruction
390 decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE];
391 int num_insns;
392 struct tilegx_reverse_regs reverse_frame[TILEGX_NUM_PHYS_REGS];
393 struct tilegx_reverse_regs
394 new_reverse_frame[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE];
395 int dest_regs[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE];
3361b059 396 int reverse_frame_valid, prolog_done, branch_seen, lr_saved_on_stack_p;
ade64f0e
PA		 397 LONGEST prev_sp_value;
398 int i, j;
399
400 if (start_addr >= end_addr
401 || (start_addr % TILEGX_BUNDLE_ALIGNMENT_IN_BYTES) != 0)
402 return end_addr;
403
404 /* Initialize the reverse frame. This maps the CURRENT frame's
405 registers to the outer frame's registers (the frame on the
406 stack goes the other way). */
407 memcpy (&reverse_frame, &template_reverse_regs, sizeof (reverse_frame));
408
409 prolog_done = 0;
410 branch_seen = 0;
411 prev_sp_value = 0;
3361b059 412 lr_saved_on_stack_p = 0;
ade64f0e
PA		 413
414 /* To cut down on round-trip overhead, we fetch multiple bundles
415 at once. These variables describe the range of memory we have
416 prefetched. */
417 instbuf_start = 0;
418 instbuf_size = 0;
419
420 for (next_addr = start_addr;
421 next_addr < end_addr;
422 next_addr += TILEGX_BUNDLE_SIZE_IN_BYTES)
423 {
424 /* Retrieve the next instruction. */
425 if (next_addr - instbuf_start >= instbuf_size)
426 {
427 /* Figure out how many bytes to fetch. Don't span a page
428 boundary since that might cause an unnecessary memory
429 error. */
430 unsigned int size_on_same_page = 4096 - (next_addr & 4095);
431
432 instbuf_size = sizeof instbuf;
433
434 if (instbuf_size > size_on_same_page)
435 instbuf_size = size_on_same_page;
d79e58d8
JW		 436
437 instbuf_size = min (instbuf_size, (end_addr - next_addr));
ade64f0e
PA		 438 instbuf_start = next_addr;
439
440 status = safe_frame_unwind_memory (next_frame, instbuf_start,
441 instbuf, instbuf_size);
442 if (status == 0)
443 memory_error (status, next_addr);
444 }
445
446 reverse_frame_valid = 0;
447
448 bundle = extract_unsigned_integer (&instbuf[next_addr - instbuf_start],
449 8, byte_order);
450
451 num_insns = parse_insn_tilegx (bundle, next_addr, decoded);
452
453 for (i = 0; i < num_insns; i++)
454 {
455 struct tilegx_decoded_instruction *this_insn = &decoded[i];
456 int64_t *operands = (int64_t *) this_insn->operand_values;
457 const struct tilegx_opcode *opcode = this_insn->opcode;
458
459 switch (opcode->mnemonic)
460 {
461 case TILEGX_OPC_ST:
462 if (cache
463 && reverse_frame[operands[0]].state == REVERSE_STATE_VALUE
464 && reverse_frame[operands[1]].state
465 == REVERSE_STATE_REGISTER)
466 {
467 LONGEST saved_address = reverse_frame[operands[0]].value;
468 unsigned saved_register
469 = (unsigned) reverse_frame[operands[1]].value;
470
471 /* realreg >= 0 and addr != -1 indicates that the
472 value of saved_register is in memory location
473 saved_address. The value of realreg is not
474 meaningful in this case but it must be >= 0.
475 See trad-frame.h. */
476 cache->saved_regs[saved_register].realreg = saved_register;
477 cache->saved_regs[saved_register].addr = saved_address;
3361b059
WL		 478 }
479 else if (cache
480 && (operands[0] == TILEGX_SP_REGNUM)
481 && (operands[1] == TILEGX_LR_REGNUM))
482 lr_saved_on_stack_p = 1;
ade64f0e
PA		 483 break;
484 case TILEGX_OPC_ADDI:
485 case TILEGX_OPC_ADDLI:
486 if (cache
487 && operands[0] == TILEGX_SP_REGNUM
488 && operands[1] == TILEGX_SP_REGNUM
489 && reverse_frame[operands[1]].state == REVERSE_STATE_REGISTER)
490 {
491 /* Special case. We're fixing up the stack frame. */
492 uint64_t hopefully_sp
493 = (unsigned) reverse_frame[operands[1]].value;
494 short op2_as_short = (short) operands[2];
495 signed char op2_as_char = (signed char) operands[2];
496
497 /* Fix up the sign-extension. */
498 if (opcode->mnemonic == TILEGX_OPC_ADDI)
499 op2_as_short = op2_as_char;
500 prev_sp_value = (cache->saved_regs[hopefully_sp].addr
501 - op2_as_short);
502
503 new_reverse_frame[i].state = REVERSE_STATE_VALUE;
504 new_reverse_frame[i].value
505 = cache->saved_regs[hopefully_sp].addr;
506 trad_frame_set_value (cache->saved_regs,
507 hopefully_sp, prev_sp_value);
508 }
509 else
510 {
511 short op2_as_short = (short) operands[2];
512 signed char op2_as_char = (signed char) operands[2];
513
514 /* Fix up the sign-extension. */
515 if (opcode->mnemonic == TILEGX_OPC_ADDI)
516 op2_as_short = op2_as_char;
517
518 new_reverse_frame[i] = reverse_frame[operands[1]];
519 if (new_reverse_frame[i].state == REVERSE_STATE_VALUE)
520 new_reverse_frame[i].value += op2_as_short;
521 else
522 new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN;
523 }
524 reverse_frame_valid |= 1 << i;
525 dest_regs[i] = operands[0];
526 break;
527 case TILEGX_OPC_ADD:
528 if (reverse_frame[operands[1]].state == REVERSE_STATE_VALUE
529 && reverse_frame[operands[2]].state == REVERSE_STATE_VALUE)
530 {
531 /* We have values -- we can do this. */
532 new_reverse_frame[i] = reverse_frame[operands[2]];
533 new_reverse_frame[i].value
534 += reverse_frame[operands[i]].value;
535 }
536 else
537 {
538 /* We don't know anything about the values. Punt. */
539 new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN;
540 }
541 reverse_frame_valid |= 1 << i;
542 dest_regs[i] = operands[0];
543 break;
544 case TILEGX_OPC_MOVE:
545 new_reverse_frame[i] = reverse_frame[operands[1]];
546 reverse_frame_valid |= 1 << i;
547 dest_regs[i] = operands[0];
548 break;
549 case TILEGX_OPC_MOVEI:
550 case TILEGX_OPC_MOVELI:
551 new_reverse_frame[i].state = REVERSE_STATE_VALUE;
552 new_reverse_frame[i].value = operands[1];
553 reverse_frame_valid |= 1 << i;
554 dest_regs[i] = operands[0];
555 break;
556 case TILEGX_OPC_ORI:
557 if (reverse_frame[operands[1]].state == REVERSE_STATE_VALUE)
558 {
559 /* We have a value in A -- we can do this. */
560 new_reverse_frame[i] = reverse_frame[operands[1]];
561 new_reverse_frame[i].value
562 = reverse_frame[operands[1]].value | operands[2];
563 }
564 else if (operands[2] == 0)
565 {
566 /* This is a move. */
567 new_reverse_frame[i] = reverse_frame[operands[1]];
568 }
569 else
570 {
571 /* We don't know anything about the values. Punt. */
572 new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN;
573 }
574 reverse_frame_valid |= 1 << i;
575 dest_regs[i] = operands[0];
576 break;
577 case TILEGX_OPC_OR:
578 if (reverse_frame[operands[1]].state == REVERSE_STATE_VALUE
579 && reverse_frame[operands[1]].value == 0)
580 {
581 /* This is a move. */
582 new_reverse_frame[i] = reverse_frame[operands[2]];
583 }
584 else if (reverse_frame[operands[2]].state == REVERSE_STATE_VALUE
585 && reverse_frame[operands[2]].value == 0)
586 {
587 /* This is a move. */
588 new_reverse_frame[i] = reverse_frame[operands[1]];
589 }
590 else
591 {
592 /* We don't know anything about the values. Punt. */
593 new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN;
594 }
595 reverse_frame_valid |= 1 << i;
596 dest_regs[i] = operands[0];
597 break;
598 case TILEGX_OPC_SUB:
599 if (reverse_frame[operands[1]].state == REVERSE_STATE_VALUE
600 && reverse_frame[operands[2]].state == REVERSE_STATE_VALUE)
601 {
602 /* We have values -- we can do this. */
603 new_reverse_frame[i] = reverse_frame[operands[1]];
604 new_reverse_frame[i].value
605 -= reverse_frame[operands[2]].value;
606 }
607 else
608 {
609 /* We don't know anything about the values. Punt. */
610 new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN;
611 }
612 reverse_frame_valid |= 1 << i;
613 dest_regs[i] = operands[0];
614 break;
615
616 case TILEGX_OPC_FNOP:
617 case TILEGX_OPC_INFO:
618 case TILEGX_OPC_INFOL:
619 /* Nothing to see here, move on.
620 Note that real NOP is treated as a 'real' instruction
621 because someone must have intended that it be there.
622 It therefore terminates the prolog. */
623 break;
624
625 case TILEGX_OPC_J:
626 case TILEGX_OPC_JAL:
627
628 case TILEGX_OPC_BEQZ:
629 case TILEGX_OPC_BEQZT:
630 case TILEGX_OPC_BGEZ:
631 case TILEGX_OPC_BGEZT:
632 case TILEGX_OPC_BGTZ:
633 case TILEGX_OPC_BGTZT:
634 case TILEGX_OPC_BLBC:
635 case TILEGX_OPC_BLBCT:
636 case TILEGX_OPC_BLBS:
637 case TILEGX_OPC_BLBST:
638 case TILEGX_OPC_BLEZ:
639 case TILEGX_OPC_BLEZT:
640 case TILEGX_OPC_BLTZ:
641 case TILEGX_OPC_BLTZT:
642 case TILEGX_OPC_BNEZ:
643 case TILEGX_OPC_BNEZT:
644
645 case TILEGX_OPC_IRET:
646 case TILEGX_OPC_JALR:
647 case TILEGX_OPC_JALRP:
648 case TILEGX_OPC_JR:
649 case TILEGX_OPC_JRP:
650 case TILEGX_OPC_SWINT0:
651 case TILEGX_OPC_SWINT1:
652 case TILEGX_OPC_SWINT2:
653 case TILEGX_OPC_SWINT3:
654 /* We're really done -- this is a branch. */
655 branch_seen = 1;
656 prolog_done = 1;
657 break;
658 default:
659 /* We don't know or care what this instruction is.
660 All we know is that it isn't part of a prolog, and if
661 there's a destination register, we're trashing it. */
662 prolog_done = 1;
663 for (j = 0; j < opcode->num_operands; j++)
664 {
665 if (this_insn->operands[j]->is_dest_reg)
666 {
667 dest_regs[i] = operands[j];
668 new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN;
669 reverse_frame_valid |= 1 << i;
670 break;
671 }
672 }
673 break;
674 }
675 }
676
677 /* Now update the reverse frames. */
678 for (i = 0; i < num_insns; i++)
679 {
680 /* ISSUE: Does this properly handle "network" registers? */
681 if ((reverse_frame_valid & (1 << i))
682 && dest_regs[i] != TILEGX_ZERO_REGNUM)
683 reverse_frame[dest_regs[i]] = new_reverse_frame[i];
684 }
685
686 if (prev_sp_value != 0)
687 {
688 /* GCC uses R52 as a frame pointer. Have we seen "move r52, sp"? */
689 if (reverse_frame[TILEGX_R52_REGNUM].state == REVERSE_STATE_REGISTER
690 && reverse_frame[TILEGX_R52_REGNUM].value == TILEGX_SP_REGNUM)
691 {
692 reverse_frame[TILEGX_R52_REGNUM].state = REVERSE_STATE_VALUE;
693 reverse_frame[TILEGX_R52_REGNUM].value = prev_sp_value;
694 }
695
696 prev_sp_value = 0;
697 }
698
699 if (prolog_done && prolog_end == end_addr)
700 {
701 /* We found non-prolog code. As such, _this_ instruction
702 is the one after the prolog. We keep processing, because
703 there may be more prolog code in there, but this is what
704 we'll return. */
705 /* ISSUE: There may not have actually been a prologue, and
706 we may have simply skipped some random instructions. */
707 prolog_end = next_addr;
708 }
709 if (branch_seen)
710 {
711 /* We saw a branch. The prolog absolutely must be over. */
712 break;
713 }
714 }
715
716 if (prolog_end == end_addr && cache)
717 {
718 /* We may have terminated the prolog early, and we're certainly
719 at THIS point right now. It's possible that the values of
720 registers we need are currently actually in other registers
721 (and haven't been written to memory yet). Go find them. */
722 for (i = 0; i < TILEGX_NUM_PHYS_REGS; i++)
723 {
724 if (reverse_frame[i].state == REVERSE_STATE_REGISTER
725 && reverse_frame[i].value != i)
726 {
727 unsigned saved_register = (unsigned) reverse_frame[i].value;
728
729 cache->saved_regs[saved_register].realreg = i;
730 cache->saved_regs[saved_register].addr = (LONGEST) -1;
731 }
732 }
733 }
734
3361b059
WL		 735 if (lr_saved_on_stack_p)
736 {
737 cache->saved_regs[TILEGX_LR_REGNUM].realreg = TILEGX_LR_REGNUM;
738 cache->saved_regs[TILEGX_LR_REGNUM].addr =
739 cache->saved_regs[TILEGX_SP_REGNUM].addr;
740 }
741
ade64f0e
PA		 742 return prolog_end;
743}
744
745/* This is the implementation of gdbarch method skip_prologue. */
746
747static CORE_ADDR
3e9d5130 748tilegx_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
ade64f0e 749{
d79e58d8
JW		 750 CORE_ADDR func_start, end_pc;
751 struct obj_section *s;
ade64f0e
PA		 752
753 /* This is the preferred method, find the end of the prologue by
754 using the debugging information. */
3e9d5130 755 if (find_pc_partial_function (start_pc, NULL, &func_start, NULL))
ade64f0e 756 {
3e9d5130
WL		 757 CORE_ADDR post_prologue_pc
758 = skip_prologue_using_sal (gdbarch, func_start);
ade64f0e 759
3e9d5130
WL		 760 if (post_prologue_pc != 0)
761 return max (start_pc, post_prologue_pc);
ade64f0e
PA		 762 }
763
d79e58d8
JW		 764 /* Don't straddle a section boundary. */
765 s = find_pc_section (start_pc);
766 end_pc = start_pc + 8 * TILEGX_BUNDLE_SIZE_IN_BYTES;
767 if (s != NULL)
768 end_pc = min (end_pc, obj_section_endaddr (s));
769
ade64f0e
PA		 770 /* Otherwise, try to skip prologue the hard way. */
771 return tilegx_analyze_prologue (gdbarch,
3e9d5130 772 start_pc,
d79e58d8 773 end_pc,
ade64f0e
PA		 774 NULL, NULL);
775}
776
777/* This is the implementation of gdbarch method in_function_epilogue_p. */
778
779static int
780tilegx_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
781{
782 CORE_ADDR func_addr = 0, func_end = 0;
783
784 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
785 {
786 ULONGEST inst, inst2;
787 CORE_ADDR addr = func_end - TILEGX_BUNDLE_SIZE_IN_BYTES;
788
789 /* FIXME: Find the actual epilogue. */
790 /* HACK: Just assume the final bundle is the "ret" instruction". */
791 if (pc > addr)
792 return 1;
793 }
794 return 0;
795}
796
61d8bd0e
JW		 797/* This is the implementation of gdbarch method get_longjmp_target. */
798
799static int
800tilegx_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
801{
802 struct gdbarch *gdbarch = get_frame_arch (frame);
803 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
804 CORE_ADDR jb_addr;
805 gdb_byte buf[8];
806
807 jb_addr = get_frame_register_unsigned (frame, TILEGX_R0_REGNUM);
808
809 /* TileGX jmp_buf contains 32 elements of type __uint_reg_t which
810 has a size of 8 bytes. The return address is stored in the 25th
811 slot. */
812 if (target_read_memory (jb_addr + 25 * 8, buf, 8))
813 return 0;
814
815 *pc = extract_unsigned_integer (buf, 8, byte_order);
816
817 return 1;
818}
819
4aaf2503
WL		 820/* by assigning the 'faultnum' reg in kernel pt_regs with this value,
821 kernel do_signal will not check r0. see tilegx kernel/signal.c
822 for details. */
823#define INT_SWINT_1_SIGRETURN (~0)
824
825/* Implement the "write_pc" gdbarch method. */
826
827static void
828tilegx_write_pc (struct regcache *regcache, CORE_ADDR pc)
829{
830 regcache_cooked_write_unsigned (regcache, TILEGX_PC_REGNUM, pc);
831
832 /* We must be careful with modifying the program counter. If we
833 just interrupted a system call, the kernel might try to restart
834 it when we resume the inferior. On restarting the system call,
835 the kernel will try backing up the program counter even though it
836 no longer points at the system call. This typically results in a
837 SIGSEGV or SIGILL. We can prevent this by writing INT_SWINT_1_SIGRETURN
838 in the "faultnum" pseudo-register.
839
840 Note that "faultnum" is saved when setting up a dummy call frame.
841 This means that it is properly restored when that frame is
842 popped, and that the interrupted system call will be restarted
843 when we resume the inferior on return from a function call from
844 within GDB. In all other cases the system call will not be
845 restarted. */
846 regcache_cooked_write_unsigned (regcache, TILEGX_FAULTNUM_REGNUM,
847 INT_SWINT_1_SIGRETURN);
848}
849
ade64f0e
PA		 850/* This is the implementation of gdbarch method breakpoint_from_pc. */
851
852static const unsigned char *
853tilegx_breakpoint_from_pc (struct gdbarch *gdbarch,
854 CORE_ADDR *pcptr, int *lenptr)
855{
856 /* 64-bit pattern for a { bpt ; nop } bundle. */
857 static const unsigned char breakpoint[] =
858 { 0x00, 0x50, 0x48, 0x51, 0xae, 0x44, 0x6a, 0x28 };
859
860 *lenptr = sizeof (breakpoint);
861 return breakpoint;
862}
863
864/* Normal frames. */
865
866static struct tilegx_frame_cache *
867tilegx_frame_cache (struct frame_info *this_frame, void **this_cache)
868{
869 struct gdbarch *gdbarch = get_frame_arch (this_frame);
870 struct tilegx_frame_cache *cache;
871 CORE_ADDR current_pc;
872 int i;
873
874 if (*this_cache)
875 return *this_cache;
876
877 cache = FRAME_OBSTACK_ZALLOC (struct tilegx_frame_cache);
878 *this_cache = cache;
879 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
880 cache->base = 0;
881 cache->start_pc = get_frame_func (this_frame);
882 current_pc = get_frame_pc (this_frame);
883
884 cache->base = get_frame_register_unsigned (this_frame, TILEGX_SP_REGNUM);
885 trad_frame_set_value (cache->saved_regs, TILEGX_SP_REGNUM, cache->base);
886
ade64f0e
PA		 887 if (cache->start_pc)
888 tilegx_analyze_prologue (gdbarch, cache->start_pc, current_pc,
889 cache, this_frame);
890
3361b059
WL		 891 cache->saved_regs[TILEGX_PC_REGNUM] = cache->saved_regs[TILEGX_LR_REGNUM];
892
ade64f0e
PA		 893 return cache;
894}
895
896/* Retrieve the value of REGNUM in FRAME. */
897
898static struct value*
899tilegx_frame_prev_register (struct frame_info *this_frame,
900 void **this_cache,
901 int regnum)
902{
903 struct tilegx_frame_cache *info =
904 tilegx_frame_cache (this_frame, this_cache);
905
906 return trad_frame_get_prev_register (this_frame, info->saved_regs,
907 regnum);
908}
909
910/* Build frame id. */
911
912static void
913tilegx_frame_this_id (struct frame_info *this_frame, void **this_cache,
914 struct frame_id *this_id)
915{
916 struct tilegx_frame_cache *info =
917 tilegx_frame_cache (this_frame, this_cache);
918
919 /* This marks the outermost frame. */
920 if (info->base == 0)
921 return;
922
923 (*this_id) = frame_id_build (info->base, info->start_pc);
924}
925
926static CORE_ADDR
927tilegx_frame_base_address (struct frame_info *this_frame, void **this_cache)
928{
929 struct tilegx_frame_cache *cache =
930 tilegx_frame_cache (this_frame, this_cache);
931
932 return cache->base;
933}
934
935static const struct frame_unwind tilegx_frame_unwind = {
936 NORMAL_FRAME,
937 default_frame_unwind_stop_reason,
938 tilegx_frame_this_id,
939 tilegx_frame_prev_register,
940 NULL, /* const struct frame_data *unwind_data */
941 default_frame_sniffer, /* frame_sniffer_ftype *sniffer */
942 NULL /* frame_prev_pc_ftype *prev_pc */
943};
944
945static const struct frame_base tilegx_frame_base = {
946 &tilegx_frame_unwind,
947 tilegx_frame_base_address,
948 tilegx_frame_base_address,
949 tilegx_frame_base_address
950};
951
952static CORE_ADDR
953tilegx_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
954{
955 return frame_unwind_register_unsigned (next_frame, TILEGX_SP_REGNUM);
956}
957
958static CORE_ADDR
959tilegx_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
960{
961 return frame_unwind_register_unsigned (next_frame, TILEGX_PC_REGNUM);
962}
963
964static struct frame_id
965tilegx_unwind_dummy_id (struct gdbarch *gdbarch,
966 struct frame_info *this_frame)
967{
968 CORE_ADDR sp;
969
970 sp = get_frame_register_unsigned (this_frame, TILEGX_SP_REGNUM);
971 return frame_id_build (sp, get_frame_pc (this_frame));
972}
973
974
975/* We cannot read/write the "special" registers. */
976
977static int
978tilegx_cannot_reference_register (struct gdbarch *gdbarch, int regno)
979{
980 if (regno >= 0 && regno < TILEGX_NUM_EASY_REGS)
981 return 0;
4aaf2503
WL		 982 else if (regno == TILEGX_PC_REGNUM
983 || regno == TILEGX_FAULTNUM_REGNUM)
ade64f0e
PA		 984 return 0;
985 else
986 return 1;
987}
988
989static struct gdbarch *
990tilegx_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
991{
992 struct gdbarch *gdbarch;
993 int arch_size = 64;
994
995 /* Handle arch_size == 32 or 64. Default to 64. */
996 if (info.abfd)
997 arch_size = bfd_get_arch_size (info.abfd);
998
999 /* Try to find a pre-existing architecture. */
1000 for (arches = gdbarch_list_lookup_by_info (arches, &info);
1001 arches != NULL;
1002 arches = gdbarch_list_lookup_by_info (arches->next, &info))
1003 {
1004 /* We only have two flavors -- just make sure arch_size matches. */
1005 if (gdbarch_ptr_bit (arches->gdbarch) == arch_size)
1006 return (arches->gdbarch);
1007 }
1008
1009 gdbarch = gdbarch_alloc (&info, NULL);
1010
1011 /* Basic register fields and methods, datatype sizes and stuff. */
1012
1013 /* There are 64 physical registers which can be referenced by
1014 instructions (although only 56 of them can actually be
1015 debugged) and 1 magic register (the PC). The other three
1016 magic registers (ex1, syscall, orig_r0) which are known to
1017 "ptrace" are ignored by "gdb". Note that we simply pretend
1018 that there are 65 registers, and no "pseudo registers". */
1019 set_gdbarch_num_regs (gdbarch, TILEGX_NUM_REGS);
1020 set_gdbarch_num_pseudo_regs (gdbarch, 0);
1021
1022 set_gdbarch_sp_regnum (gdbarch, TILEGX_SP_REGNUM);
1023 set_gdbarch_pc_regnum (gdbarch, TILEGX_PC_REGNUM);
1024
1025 set_gdbarch_register_name (gdbarch, tilegx_register_name);
1026 set_gdbarch_register_type (gdbarch, tilegx_register_type);
1027
ade64f0e
PA		 1028 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
1029 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1030 set_gdbarch_long_bit (gdbarch, arch_size);
1031 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1032
1033 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1034 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1035 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1036
1037 set_gdbarch_ptr_bit (gdbarch, arch_size);
1038 set_gdbarch_addr_bit (gdbarch, arch_size);
1039
1040 set_gdbarch_cannot_fetch_register (gdbarch,
1041 tilegx_cannot_reference_register);
1042 set_gdbarch_cannot_store_register (gdbarch,
1043 tilegx_cannot_reference_register);
1044
1045 /* Stack grows down. */
1046 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1047
1048 /* Frame Info. */
1049 set_gdbarch_unwind_sp (gdbarch, tilegx_unwind_sp);
1050 set_gdbarch_unwind_pc (gdbarch, tilegx_unwind_pc);
1051 set_gdbarch_dummy_id (gdbarch, tilegx_unwind_dummy_id);
1052 set_gdbarch_frame_align (gdbarch, tilegx_frame_align);
1053 frame_base_set_default (gdbarch, &tilegx_frame_base);
1054
1055 set_gdbarch_skip_prologue (gdbarch, tilegx_skip_prologue);
1056
1057 set_gdbarch_in_function_epilogue_p (gdbarch,
1058 tilegx_in_function_epilogue_p);
1059
1060 /* Map debug registers into internal register numbers. */
1061 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, tilegx_dwarf2_reg_to_regnum);
1062
1063 /* These values and methods are used when gdb calls a target function. */
1064 set_gdbarch_push_dummy_call (gdbarch, tilegx_push_dummy_call);
61d8bd0e 1065 set_gdbarch_get_longjmp_target (gdbarch, tilegx_get_longjmp_target);
4aaf2503 1066 set_gdbarch_write_pc (gdbarch, tilegx_write_pc);
ade64f0e
PA		 1067 set_gdbarch_breakpoint_from_pc (gdbarch, tilegx_breakpoint_from_pc);
1068 set_gdbarch_return_value (gdbarch, tilegx_return_value);
1069
1070 set_gdbarch_print_insn (gdbarch, print_insn_tilegx);
1071
1072 gdbarch_init_osabi (info, gdbarch);
1073
1074 dwarf2_append_unwinders (gdbarch);
1075 frame_unwind_append_unwinder (gdbarch, &tilegx_frame_unwind);
1076
1077 return gdbarch;
1078}
1079
1080/* Provide a prototype to silence -Wmissing-prototypes. */
1081extern initialize_file_ftype _initialize_tilegx_tdep;
1082
1083void
1084_initialize_tilegx_tdep (void)
1085{
1086 register_gdbarch_init (bfd_arch_tilegx, tilegx_gdbarch_init);
1087}
GDB Binutils - Deliverables
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