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ade64f0e PA |
1 | /* Target-dependent code for the Tilera TILE-Gx processor. |
2 | ||
ecd75fc8 | 3 | Copyright (C) 2012-2014 Free Software Foundation, Inc. |
ade64f0e PA |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #include "defs.h" | |
21 | #include "frame.h" | |
22 | #include "frame-base.h" | |
23 | #include "frame-unwind.h" | |
24 | #include "dwarf2-frame.h" | |
25 | #include "trad-frame.h" | |
26 | #include "symtab.h" | |
27 | #include "gdbtypes.h" | |
28 | #include "gdbcmd.h" | |
29 | #include "gdbcore.h" | |
30 | #include "value.h" | |
31 | #include "dis-asm.h" | |
32 | #include "inferior.h" | |
0e9f083f | 33 | #include <string.h> |
ade64f0e PA |
34 | #include "gdb_assert.h" |
35 | #include "arch-utils.h" | |
36 | #include "floatformat.h" | |
37 | #include "regcache.h" | |
38 | #include "regset.h" | |
39 | #include "doublest.h" | |
40 | #include "osabi.h" | |
41 | #include "linux-tdep.h" | |
42 | #include "objfiles.h" | |
43 | #include "solib-svr4.h" | |
ade64f0e PA |
44 | #include "tilegx-tdep.h" |
45 | #include "opcode/tilegx.h" | |
46 | ||
47 | struct tilegx_frame_cache | |
48 | { | |
49 | /* Base address. */ | |
50 | CORE_ADDR base; | |
51 | /* Function start. */ | |
52 | CORE_ADDR start_pc; | |
53 | ||
54 | /* Table of saved registers. */ | |
55 | struct trad_frame_saved_reg *saved_regs; | |
56 | }; | |
57 | ||
58 | /* Register state values used by analyze_prologue. */ | |
59 | enum reverse_state | |
60 | { | |
61 | REVERSE_STATE_REGISTER, | |
62 | REVERSE_STATE_VALUE, | |
63 | REVERSE_STATE_UNKNOWN | |
64 | }; | |
65 | ||
66 | /* Register state used by analyze_prologue(). */ | |
67 | struct tilegx_reverse_regs | |
68 | { | |
69 | LONGEST value; | |
70 | enum reverse_state state; | |
71 | }; | |
72 | ||
73 | static const struct tilegx_reverse_regs | |
74 | template_reverse_regs[TILEGX_NUM_PHYS_REGS] = | |
75 | { | |
76 | { TILEGX_R0_REGNUM, REVERSE_STATE_REGISTER }, | |
77 | { TILEGX_R1_REGNUM, REVERSE_STATE_REGISTER }, | |
78 | { TILEGX_R2_REGNUM, REVERSE_STATE_REGISTER }, | |
79 | { TILEGX_R3_REGNUM, REVERSE_STATE_REGISTER }, | |
80 | { TILEGX_R4_REGNUM, REVERSE_STATE_REGISTER }, | |
81 | { TILEGX_R5_REGNUM, REVERSE_STATE_REGISTER }, | |
82 | { TILEGX_R6_REGNUM, REVERSE_STATE_REGISTER }, | |
83 | { TILEGX_R7_REGNUM, REVERSE_STATE_REGISTER }, | |
84 | { TILEGX_R8_REGNUM, REVERSE_STATE_REGISTER }, | |
85 | { TILEGX_R9_REGNUM, REVERSE_STATE_REGISTER }, | |
86 | { TILEGX_R10_REGNUM, REVERSE_STATE_REGISTER }, | |
87 | { TILEGX_R11_REGNUM, REVERSE_STATE_REGISTER }, | |
88 | { TILEGX_R12_REGNUM, REVERSE_STATE_REGISTER }, | |
89 | { TILEGX_R13_REGNUM, REVERSE_STATE_REGISTER }, | |
90 | { TILEGX_R14_REGNUM, REVERSE_STATE_REGISTER }, | |
91 | { TILEGX_R15_REGNUM, REVERSE_STATE_REGISTER }, | |
92 | { TILEGX_R16_REGNUM, REVERSE_STATE_REGISTER }, | |
93 | { TILEGX_R17_REGNUM, REVERSE_STATE_REGISTER }, | |
94 | { TILEGX_R18_REGNUM, REVERSE_STATE_REGISTER }, | |
95 | { TILEGX_R19_REGNUM, REVERSE_STATE_REGISTER }, | |
96 | { TILEGX_R20_REGNUM, REVERSE_STATE_REGISTER }, | |
97 | { TILEGX_R21_REGNUM, REVERSE_STATE_REGISTER }, | |
98 | { TILEGX_R22_REGNUM, REVERSE_STATE_REGISTER }, | |
99 | { TILEGX_R23_REGNUM, REVERSE_STATE_REGISTER }, | |
100 | { TILEGX_R24_REGNUM, REVERSE_STATE_REGISTER }, | |
101 | { TILEGX_R25_REGNUM, REVERSE_STATE_REGISTER }, | |
102 | { TILEGX_R26_REGNUM, REVERSE_STATE_REGISTER }, | |
103 | { TILEGX_R27_REGNUM, REVERSE_STATE_REGISTER }, | |
104 | { TILEGX_R28_REGNUM, REVERSE_STATE_REGISTER }, | |
105 | { TILEGX_R29_REGNUM, REVERSE_STATE_REGISTER }, | |
106 | { TILEGX_R30_REGNUM, REVERSE_STATE_REGISTER }, | |
107 | { TILEGX_R31_REGNUM, REVERSE_STATE_REGISTER }, | |
108 | { TILEGX_R32_REGNUM, REVERSE_STATE_REGISTER }, | |
109 | { TILEGX_R33_REGNUM, REVERSE_STATE_REGISTER }, | |
110 | { TILEGX_R34_REGNUM, REVERSE_STATE_REGISTER }, | |
111 | { TILEGX_R35_REGNUM, REVERSE_STATE_REGISTER }, | |
112 | { TILEGX_R36_REGNUM, REVERSE_STATE_REGISTER }, | |
113 | { TILEGX_R37_REGNUM, REVERSE_STATE_REGISTER }, | |
114 | { TILEGX_R38_REGNUM, REVERSE_STATE_REGISTER }, | |
115 | { TILEGX_R39_REGNUM, REVERSE_STATE_REGISTER }, | |
116 | { TILEGX_R40_REGNUM, REVERSE_STATE_REGISTER }, | |
117 | { TILEGX_R41_REGNUM, REVERSE_STATE_REGISTER }, | |
118 | { TILEGX_R42_REGNUM, REVERSE_STATE_REGISTER }, | |
119 | { TILEGX_R43_REGNUM, REVERSE_STATE_REGISTER }, | |
120 | { TILEGX_R44_REGNUM, REVERSE_STATE_REGISTER }, | |
121 | { TILEGX_R45_REGNUM, REVERSE_STATE_REGISTER }, | |
122 | { TILEGX_R46_REGNUM, REVERSE_STATE_REGISTER }, | |
123 | { TILEGX_R47_REGNUM, REVERSE_STATE_REGISTER }, | |
124 | { TILEGX_R48_REGNUM, REVERSE_STATE_REGISTER }, | |
125 | { TILEGX_R49_REGNUM, REVERSE_STATE_REGISTER }, | |
126 | { TILEGX_R50_REGNUM, REVERSE_STATE_REGISTER }, | |
127 | { TILEGX_R51_REGNUM, REVERSE_STATE_REGISTER }, | |
128 | { TILEGX_R52_REGNUM, REVERSE_STATE_REGISTER }, | |
129 | { TILEGX_TP_REGNUM, REVERSE_STATE_REGISTER }, | |
130 | { TILEGX_SP_REGNUM, REVERSE_STATE_REGISTER }, | |
131 | { TILEGX_LR_REGNUM, REVERSE_STATE_REGISTER }, | |
132 | { 0, REVERSE_STATE_UNKNOWN }, | |
133 | { 0, REVERSE_STATE_UNKNOWN }, | |
134 | { 0, REVERSE_STATE_UNKNOWN }, | |
135 | { 0, REVERSE_STATE_UNKNOWN }, | |
136 | { 0, REVERSE_STATE_UNKNOWN }, | |
137 | { 0, REVERSE_STATE_UNKNOWN }, | |
138 | { 0, REVERSE_STATE_UNKNOWN }, | |
139 | { TILEGX_ZERO_REGNUM, REVERSE_STATE_VALUE } | |
140 | }; | |
141 | ||
142 | /* Implement the "register_name" gdbarch method. */ | |
143 | ||
144 | static const char * | |
145 | tilegx_register_name (struct gdbarch *gdbarch, int regnum) | |
146 | { | |
147 | static const char *const register_names[TILEGX_NUM_REGS] = | |
148 | { | |
149 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
150 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
151 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
152 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
153 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", | |
154 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", | |
155 | "r48", "r49", "r50", "r51", "r52", "tp", "sp", "lr", | |
156 | "sn", "idn0", "idn1", "udn0", "udn1", "udn2", "udn3", "zero", | |
4aaf2503 | 157 | "pc", "faultnum", |
ade64f0e PA |
158 | }; |
159 | ||
160 | if (regnum < 0 || regnum >= TILEGX_NUM_REGS) | |
161 | internal_error (__FILE__, __LINE__, | |
162 | "tilegx_register_name: invalid register number %d", | |
163 | regnum); | |
164 | ||
165 | return register_names[regnum]; | |
166 | } | |
167 | ||
168 | /* This is the implementation of gdbarch method register_type. */ | |
169 | ||
170 | static struct type * | |
171 | tilegx_register_type (struct gdbarch *gdbarch, int regnum) | |
172 | { | |
173 | if (regnum == TILEGX_PC_REGNUM) | |
174 | return builtin_type (gdbarch)->builtin_func_ptr; | |
175 | else | |
176 | return builtin_type (gdbarch)->builtin_uint64; | |
177 | } | |
178 | ||
179 | /* This is the implementation of gdbarch method dwarf2_reg_to_regnum. */ | |
180 | ||
181 | static int | |
182 | tilegx_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num) | |
183 | { | |
184 | return num; | |
185 | } | |
186 | ||
187 | /* Makes the decision of whether a given type is a scalar type. | |
188 | Scalar types are returned in the registers r2-r11 as they fit. */ | |
189 | ||
190 | static int | |
191 | tilegx_type_is_scalar (struct type *t) | |
192 | { | |
193 | return (TYPE_CODE(t) != TYPE_CODE_STRUCT | |
194 | && TYPE_CODE(t) != TYPE_CODE_UNION | |
195 | && TYPE_CODE(t) != TYPE_CODE_ARRAY); | |
196 | } | |
197 | ||
198 | /* Returns non-zero if the given struct type will be returned using | |
199 | a special convention, rather than the normal function return method. | |
200 | Used in the context of the "return" command, and target function | |
201 | calls from the debugger. */ | |
202 | ||
203 | static int | |
204 | tilegx_use_struct_convention (struct type *type) | |
205 | { | |
206 | /* Only scalars which fit in R0 - R9 can be returned in registers. | |
207 | Otherwise, they are returned via a pointer passed in R0. */ | |
208 | return (!tilegx_type_is_scalar (type) | |
209 | && (TYPE_LENGTH (type) > (1 + TILEGX_R9_REGNUM - TILEGX_R0_REGNUM) | |
210 | * tilegx_reg_size)); | |
211 | } | |
212 | ||
213 | /* Find a function's return value in the appropriate registers (in | |
214 | REGCACHE), and copy it into VALBUF. */ | |
215 | ||
216 | static void | |
217 | tilegx_extract_return_value (struct type *type, struct regcache *regcache, | |
218 | gdb_byte *valbuf) | |
219 | { | |
220 | int len = TYPE_LENGTH (type); | |
221 | int i, regnum = TILEGX_R0_REGNUM; | |
222 | ||
223 | for (i = 0; i < len; i += tilegx_reg_size) | |
224 | regcache_raw_read (regcache, regnum++, valbuf + i); | |
225 | } | |
226 | ||
227 | /* Copy the function return value from VALBUF into the proper | |
228 | location for a function return. | |
229 | Called only in the context of the "return" command. */ | |
230 | ||
231 | static void | |
232 | tilegx_store_return_value (struct type *type, struct regcache *regcache, | |
233 | const void *valbuf) | |
234 | { | |
235 | if (TYPE_LENGTH (type) < tilegx_reg_size) | |
236 | { | |
237 | /* Add leading zeros to the (little-endian) value. */ | |
238 | gdb_byte buf[tilegx_reg_size] = { 0 }; | |
239 | ||
240 | memcpy (buf, valbuf, TYPE_LENGTH (type)); | |
241 | regcache_raw_write (regcache, TILEGX_R0_REGNUM, buf); | |
242 | } | |
243 | else | |
244 | { | |
245 | int len = TYPE_LENGTH (type); | |
246 | int i, regnum = TILEGX_R0_REGNUM; | |
247 | ||
248 | for (i = 0; i < len; i += tilegx_reg_size) | |
249 | regcache_raw_write (regcache, regnum++, (gdb_byte *) valbuf + i); | |
250 | } | |
251 | } | |
252 | ||
253 | /* This is the implementation of gdbarch method return_value. */ | |
254 | ||
255 | static enum return_value_convention | |
256 | tilegx_return_value (struct gdbarch *gdbarch, struct value *function, | |
257 | struct type *type, struct regcache *regcache, | |
258 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
259 | { | |
260 | if (tilegx_use_struct_convention (type)) | |
261 | return RETURN_VALUE_STRUCT_CONVENTION; | |
262 | if (writebuf) | |
263 | tilegx_store_return_value (type, regcache, writebuf); | |
264 | else if (readbuf) | |
265 | tilegx_extract_return_value (type, regcache, readbuf); | |
266 | return RETURN_VALUE_REGISTER_CONVENTION; | |
267 | } | |
268 | ||
269 | /* This is the implementation of gdbarch method frame_align. */ | |
270 | ||
271 | static CORE_ADDR | |
272 | tilegx_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
273 | { | |
274 | return addr & -8; | |
275 | } | |
276 | ||
277 | ||
278 | /* Implement the "push_dummy_call" gdbarch method. */ | |
279 | ||
280 | static CORE_ADDR | |
281 | tilegx_push_dummy_call (struct gdbarch *gdbarch, | |
282 | struct value *function, | |
283 | struct regcache *regcache, | |
284 | CORE_ADDR bp_addr, int nargs, | |
285 | struct value **args, | |
286 | CORE_ADDR sp, int struct_return, | |
287 | CORE_ADDR struct_addr) | |
288 | { | |
289 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
290 | CORE_ADDR stack_dest = sp; | |
291 | int argreg = TILEGX_R0_REGNUM; | |
292 | int i, j; | |
293 | int typelen, slacklen, alignlen; | |
bc23a956 | 294 | static const gdb_byte four_zero_words[16] = { 0 }; |
ade64f0e PA |
295 | |
296 | /* If struct_return is 1, then the struct return address will | |
297 | consume one argument-passing register. */ | |
298 | if (struct_return) | |
299 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); | |
300 | ||
301 | /* Arguments are passed in R0 - R9, and as soon as an argument | |
302 | will not fit completely in the remaining registers, then it, | |
303 | and all remaining arguments, are put on the stack. */ | |
304 | for (i = 0; i < nargs && argreg <= TILEGX_R9_REGNUM; i++) | |
305 | { | |
306 | const gdb_byte *val; | |
307 | typelen = TYPE_LENGTH (value_enclosing_type (args[i])); | |
308 | ||
309 | if (typelen > (TILEGX_R9_REGNUM - argreg + 1) * tilegx_reg_size) | |
310 | break; | |
311 | ||
312 | /* Put argument into registers wordwise. */ | |
313 | val = value_contents (args[i]); | |
314 | for (j = 0; j < typelen; j += tilegx_reg_size) | |
315 | { | |
316 | /* ISSUE: Why special handling for "typelen = 4x + 1"? | |
317 | I don't ever see "typelen" values except 4 and 8. */ | |
318 | int n = (typelen - j == 1) ? 1 : tilegx_reg_size; | |
319 | ULONGEST w = extract_unsigned_integer (val + j, n, byte_order); | |
320 | ||
321 | regcache_cooked_write_unsigned (regcache, argreg++, w); | |
322 | } | |
323 | } | |
324 | ||
325 | /* Align SP. */ | |
326 | stack_dest = tilegx_frame_align (gdbarch, stack_dest); | |
327 | ||
ade64f0e PA |
328 | /* Loop backwards through remaining arguments and push them on |
329 | the stack, word aligned. */ | |
330 | for (j = nargs - 1; j >= i; j--) | |
331 | { | |
332 | gdb_byte *val; | |
ecfb0d68 SP |
333 | struct cleanup *back_to; |
334 | const gdb_byte *contents = value_contents (args[j]); | |
ade64f0e PA |
335 | |
336 | typelen = TYPE_LENGTH (value_enclosing_type (args[j])); | |
bc23a956 | 337 | slacklen = align_up (typelen, 8) - typelen; |
ecfb0d68 SP |
338 | val = xmalloc (typelen + slacklen); |
339 | back_to = make_cleanup (xfree, val); | |
340 | memcpy (val, contents, typelen); | |
ade64f0e PA |
341 | memset (val + typelen, 0, slacklen); |
342 | ||
343 | /* Now write data to the stack. The stack grows downwards. */ | |
344 | stack_dest -= typelen + slacklen; | |
345 | write_memory (stack_dest, val, typelen + slacklen); | |
ecfb0d68 | 346 | do_cleanups (back_to); |
ade64f0e PA |
347 | } |
348 | ||
bc23a956 WL |
349 | /* Add 16 bytes for linkage space to the stack. */ |
350 | stack_dest = stack_dest - 16; | |
351 | write_memory (stack_dest, four_zero_words, 16); | |
ade64f0e PA |
352 | |
353 | /* Update stack pointer. */ | |
354 | regcache_cooked_write_unsigned (regcache, TILEGX_SP_REGNUM, stack_dest); | |
355 | ||
356 | /* Set the return address register to point to the entry point of | |
357 | the program, where a breakpoint lies in wait. */ | |
358 | regcache_cooked_write_unsigned (regcache, TILEGX_LR_REGNUM, bp_addr); | |
359 | ||
360 | return stack_dest; | |
361 | } | |
362 | ||
363 | ||
364 | /* Decode the instructions within the given address range. | |
365 | Decide when we must have reached the end of the function prologue. | |
366 | If a frame_info pointer is provided, fill in its saved_regs etc. | |
367 | Returns the address of the first instruction after the prologue. | |
368 | NOTE: This is often called with start_addr being the start of some | |
369 | function, and end_addr being the current PC. */ | |
370 | ||
371 | static CORE_ADDR | |
372 | tilegx_analyze_prologue (struct gdbarch* gdbarch, | |
373 | CORE_ADDR start_addr, CORE_ADDR end_addr, | |
374 | struct tilegx_frame_cache *cache, | |
375 | struct frame_info *next_frame) | |
376 | { | |
377 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
378 | CORE_ADDR next_addr; | |
379 | CORE_ADDR prolog_end = end_addr; | |
380 | ULONGEST inst, inst2; | |
381 | LONGEST offset; | |
382 | int regnum; | |
383 | gdb_byte instbuf[32 * TILEGX_BUNDLE_SIZE_IN_BYTES]; | |
384 | CORE_ADDR instbuf_start; | |
385 | unsigned int instbuf_size; | |
386 | int status; | |
387 | bfd_uint64_t bundle; | |
388 | struct tilegx_decoded_instruction | |
389 | decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE]; | |
390 | int num_insns; | |
391 | struct tilegx_reverse_regs reverse_frame[TILEGX_NUM_PHYS_REGS]; | |
392 | struct tilegx_reverse_regs | |
393 | new_reverse_frame[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE]; | |
394 | int dest_regs[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE]; | |
3361b059 | 395 | int reverse_frame_valid, prolog_done, branch_seen, lr_saved_on_stack_p; |
ade64f0e PA |
396 | LONGEST prev_sp_value; |
397 | int i, j; | |
398 | ||
399 | if (start_addr >= end_addr | |
400 | || (start_addr % TILEGX_BUNDLE_ALIGNMENT_IN_BYTES) != 0) | |
401 | return end_addr; | |
402 | ||
403 | /* Initialize the reverse frame. This maps the CURRENT frame's | |
404 | registers to the outer frame's registers (the frame on the | |
405 | stack goes the other way). */ | |
406 | memcpy (&reverse_frame, &template_reverse_regs, sizeof (reverse_frame)); | |
407 | ||
408 | prolog_done = 0; | |
409 | branch_seen = 0; | |
410 | prev_sp_value = 0; | |
3361b059 | 411 | lr_saved_on_stack_p = 0; |
ade64f0e PA |
412 | |
413 | /* To cut down on round-trip overhead, we fetch multiple bundles | |
414 | at once. These variables describe the range of memory we have | |
415 | prefetched. */ | |
416 | instbuf_start = 0; | |
417 | instbuf_size = 0; | |
418 | ||
419 | for (next_addr = start_addr; | |
420 | next_addr < end_addr; | |
421 | next_addr += TILEGX_BUNDLE_SIZE_IN_BYTES) | |
422 | { | |
423 | /* Retrieve the next instruction. */ | |
424 | if (next_addr - instbuf_start >= instbuf_size) | |
425 | { | |
426 | /* Figure out how many bytes to fetch. Don't span a page | |
427 | boundary since that might cause an unnecessary memory | |
428 | error. */ | |
429 | unsigned int size_on_same_page = 4096 - (next_addr & 4095); | |
430 | ||
431 | instbuf_size = sizeof instbuf; | |
432 | ||
433 | if (instbuf_size > size_on_same_page) | |
434 | instbuf_size = size_on_same_page; | |
d79e58d8 JW |
435 | |
436 | instbuf_size = min (instbuf_size, (end_addr - next_addr)); | |
ade64f0e PA |
437 | instbuf_start = next_addr; |
438 | ||
439 | status = safe_frame_unwind_memory (next_frame, instbuf_start, | |
440 | instbuf, instbuf_size); | |
441 | if (status == 0) | |
442 | memory_error (status, next_addr); | |
443 | } | |
444 | ||
445 | reverse_frame_valid = 0; | |
446 | ||
447 | bundle = extract_unsigned_integer (&instbuf[next_addr - instbuf_start], | |
448 | 8, byte_order); | |
449 | ||
450 | num_insns = parse_insn_tilegx (bundle, next_addr, decoded); | |
451 | ||
452 | for (i = 0; i < num_insns; i++) | |
453 | { | |
454 | struct tilegx_decoded_instruction *this_insn = &decoded[i]; | |
455 | int64_t *operands = (int64_t *) this_insn->operand_values; | |
456 | const struct tilegx_opcode *opcode = this_insn->opcode; | |
457 | ||
458 | switch (opcode->mnemonic) | |
459 | { | |
460 | case TILEGX_OPC_ST: | |
461 | if (cache | |
462 | && reverse_frame[operands[0]].state == REVERSE_STATE_VALUE | |
463 | && reverse_frame[operands[1]].state | |
464 | == REVERSE_STATE_REGISTER) | |
465 | { | |
466 | LONGEST saved_address = reverse_frame[operands[0]].value; | |
467 | unsigned saved_register | |
468 | = (unsigned) reverse_frame[operands[1]].value; | |
469 | ||
470 | /* realreg >= 0 and addr != -1 indicates that the | |
471 | value of saved_register is in memory location | |
472 | saved_address. The value of realreg is not | |
473 | meaningful in this case but it must be >= 0. | |
474 | See trad-frame.h. */ | |
475 | cache->saved_regs[saved_register].realreg = saved_register; | |
476 | cache->saved_regs[saved_register].addr = saved_address; | |
3361b059 WL |
477 | } |
478 | else if (cache | |
479 | && (operands[0] == TILEGX_SP_REGNUM) | |
480 | && (operands[1] == TILEGX_LR_REGNUM)) | |
481 | lr_saved_on_stack_p = 1; | |
ade64f0e PA |
482 | break; |
483 | case TILEGX_OPC_ADDI: | |
484 | case TILEGX_OPC_ADDLI: | |
485 | if (cache | |
486 | && operands[0] == TILEGX_SP_REGNUM | |
487 | && operands[1] == TILEGX_SP_REGNUM | |
488 | && reverse_frame[operands[1]].state == REVERSE_STATE_REGISTER) | |
489 | { | |
490 | /* Special case. We're fixing up the stack frame. */ | |
491 | uint64_t hopefully_sp | |
492 | = (unsigned) reverse_frame[operands[1]].value; | |
493 | short op2_as_short = (short) operands[2]; | |
494 | signed char op2_as_char = (signed char) operands[2]; | |
495 | ||
496 | /* Fix up the sign-extension. */ | |
497 | if (opcode->mnemonic == TILEGX_OPC_ADDI) | |
498 | op2_as_short = op2_as_char; | |
499 | prev_sp_value = (cache->saved_regs[hopefully_sp].addr | |
500 | - op2_as_short); | |
501 | ||
502 | new_reverse_frame[i].state = REVERSE_STATE_VALUE; | |
503 | new_reverse_frame[i].value | |
504 | = cache->saved_regs[hopefully_sp].addr; | |
505 | trad_frame_set_value (cache->saved_regs, | |
506 | hopefully_sp, prev_sp_value); | |
507 | } | |
508 | else | |
509 | { | |
510 | short op2_as_short = (short) operands[2]; | |
511 | signed char op2_as_char = (signed char) operands[2]; | |
512 | ||
513 | /* Fix up the sign-extension. */ | |
514 | if (opcode->mnemonic == TILEGX_OPC_ADDI) | |
515 | op2_as_short = op2_as_char; | |
516 | ||
517 | new_reverse_frame[i] = reverse_frame[operands[1]]; | |
518 | if (new_reverse_frame[i].state == REVERSE_STATE_VALUE) | |
519 | new_reverse_frame[i].value += op2_as_short; | |
520 | else | |
521 | new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN; | |
522 | } | |
523 | reverse_frame_valid |= 1 << i; | |
524 | dest_regs[i] = operands[0]; | |
525 | break; | |
526 | case TILEGX_OPC_ADD: | |
527 | if (reverse_frame[operands[1]].state == REVERSE_STATE_VALUE | |
528 | && reverse_frame[operands[2]].state == REVERSE_STATE_VALUE) | |
529 | { | |
530 | /* We have values -- we can do this. */ | |
531 | new_reverse_frame[i] = reverse_frame[operands[2]]; | |
532 | new_reverse_frame[i].value | |
533 | += reverse_frame[operands[i]].value; | |
534 | } | |
535 | else | |
536 | { | |
537 | /* We don't know anything about the values. Punt. */ | |
538 | new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN; | |
539 | } | |
540 | reverse_frame_valid |= 1 << i; | |
541 | dest_regs[i] = operands[0]; | |
542 | break; | |
543 | case TILEGX_OPC_MOVE: | |
544 | new_reverse_frame[i] = reverse_frame[operands[1]]; | |
545 | reverse_frame_valid |= 1 << i; | |
546 | dest_regs[i] = operands[0]; | |
547 | break; | |
548 | case TILEGX_OPC_MOVEI: | |
549 | case TILEGX_OPC_MOVELI: | |
550 | new_reverse_frame[i].state = REVERSE_STATE_VALUE; | |
551 | new_reverse_frame[i].value = operands[1]; | |
552 | reverse_frame_valid |= 1 << i; | |
553 | dest_regs[i] = operands[0]; | |
554 | break; | |
555 | case TILEGX_OPC_ORI: | |
556 | if (reverse_frame[operands[1]].state == REVERSE_STATE_VALUE) | |
557 | { | |
558 | /* We have a value in A -- we can do this. */ | |
559 | new_reverse_frame[i] = reverse_frame[operands[1]]; | |
560 | new_reverse_frame[i].value | |
561 | = reverse_frame[operands[1]].value | operands[2]; | |
562 | } | |
563 | else if (operands[2] == 0) | |
564 | { | |
565 | /* This is a move. */ | |
566 | new_reverse_frame[i] = reverse_frame[operands[1]]; | |
567 | } | |
568 | else | |
569 | { | |
570 | /* We don't know anything about the values. Punt. */ | |
571 | new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN; | |
572 | } | |
573 | reverse_frame_valid |= 1 << i; | |
574 | dest_regs[i] = operands[0]; | |
575 | break; | |
576 | case TILEGX_OPC_OR: | |
577 | if (reverse_frame[operands[1]].state == REVERSE_STATE_VALUE | |
578 | && reverse_frame[operands[1]].value == 0) | |
579 | { | |
580 | /* This is a move. */ | |
581 | new_reverse_frame[i] = reverse_frame[operands[2]]; | |
582 | } | |
583 | else if (reverse_frame[operands[2]].state == REVERSE_STATE_VALUE | |
584 | && reverse_frame[operands[2]].value == 0) | |
585 | { | |
586 | /* This is a move. */ | |
587 | new_reverse_frame[i] = reverse_frame[operands[1]]; | |
588 | } | |
589 | else | |
590 | { | |
591 | /* We don't know anything about the values. Punt. */ | |
592 | new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN; | |
593 | } | |
594 | reverse_frame_valid |= 1 << i; | |
595 | dest_regs[i] = operands[0]; | |
596 | break; | |
597 | case TILEGX_OPC_SUB: | |
598 | if (reverse_frame[operands[1]].state == REVERSE_STATE_VALUE | |
599 | && reverse_frame[operands[2]].state == REVERSE_STATE_VALUE) | |
600 | { | |
601 | /* We have values -- we can do this. */ | |
602 | new_reverse_frame[i] = reverse_frame[operands[1]]; | |
603 | new_reverse_frame[i].value | |
604 | -= reverse_frame[operands[2]].value; | |
605 | } | |
606 | else | |
607 | { | |
608 | /* We don't know anything about the values. Punt. */ | |
609 | new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN; | |
610 | } | |
611 | reverse_frame_valid |= 1 << i; | |
612 | dest_regs[i] = operands[0]; | |
613 | break; | |
614 | ||
615 | case TILEGX_OPC_FNOP: | |
616 | case TILEGX_OPC_INFO: | |
617 | case TILEGX_OPC_INFOL: | |
618 | /* Nothing to see here, move on. | |
619 | Note that real NOP is treated as a 'real' instruction | |
620 | because someone must have intended that it be there. | |
621 | It therefore terminates the prolog. */ | |
622 | break; | |
623 | ||
624 | case TILEGX_OPC_J: | |
625 | case TILEGX_OPC_JAL: | |
626 | ||
627 | case TILEGX_OPC_BEQZ: | |
628 | case TILEGX_OPC_BEQZT: | |
629 | case TILEGX_OPC_BGEZ: | |
630 | case TILEGX_OPC_BGEZT: | |
631 | case TILEGX_OPC_BGTZ: | |
632 | case TILEGX_OPC_BGTZT: | |
633 | case TILEGX_OPC_BLBC: | |
634 | case TILEGX_OPC_BLBCT: | |
635 | case TILEGX_OPC_BLBS: | |
636 | case TILEGX_OPC_BLBST: | |
637 | case TILEGX_OPC_BLEZ: | |
638 | case TILEGX_OPC_BLEZT: | |
639 | case TILEGX_OPC_BLTZ: | |
640 | case TILEGX_OPC_BLTZT: | |
641 | case TILEGX_OPC_BNEZ: | |
642 | case TILEGX_OPC_BNEZT: | |
643 | ||
644 | case TILEGX_OPC_IRET: | |
645 | case TILEGX_OPC_JALR: | |
646 | case TILEGX_OPC_JALRP: | |
647 | case TILEGX_OPC_JR: | |
648 | case TILEGX_OPC_JRP: | |
649 | case TILEGX_OPC_SWINT0: | |
650 | case TILEGX_OPC_SWINT1: | |
651 | case TILEGX_OPC_SWINT2: | |
652 | case TILEGX_OPC_SWINT3: | |
653 | /* We're really done -- this is a branch. */ | |
654 | branch_seen = 1; | |
655 | prolog_done = 1; | |
656 | break; | |
657 | default: | |
658 | /* We don't know or care what this instruction is. | |
659 | All we know is that it isn't part of a prolog, and if | |
660 | there's a destination register, we're trashing it. */ | |
661 | prolog_done = 1; | |
662 | for (j = 0; j < opcode->num_operands; j++) | |
663 | { | |
664 | if (this_insn->operands[j]->is_dest_reg) | |
665 | { | |
666 | dest_regs[i] = operands[j]; | |
667 | new_reverse_frame[i].state = REVERSE_STATE_UNKNOWN; | |
668 | reverse_frame_valid |= 1 << i; | |
669 | break; | |
670 | } | |
671 | } | |
672 | break; | |
673 | } | |
674 | } | |
675 | ||
676 | /* Now update the reverse frames. */ | |
677 | for (i = 0; i < num_insns; i++) | |
678 | { | |
679 | /* ISSUE: Does this properly handle "network" registers? */ | |
680 | if ((reverse_frame_valid & (1 << i)) | |
681 | && dest_regs[i] != TILEGX_ZERO_REGNUM) | |
682 | reverse_frame[dest_regs[i]] = new_reverse_frame[i]; | |
683 | } | |
684 | ||
685 | if (prev_sp_value != 0) | |
686 | { | |
687 | /* GCC uses R52 as a frame pointer. Have we seen "move r52, sp"? */ | |
688 | if (reverse_frame[TILEGX_R52_REGNUM].state == REVERSE_STATE_REGISTER | |
689 | && reverse_frame[TILEGX_R52_REGNUM].value == TILEGX_SP_REGNUM) | |
690 | { | |
691 | reverse_frame[TILEGX_R52_REGNUM].state = REVERSE_STATE_VALUE; | |
692 | reverse_frame[TILEGX_R52_REGNUM].value = prev_sp_value; | |
693 | } | |
694 | ||
695 | prev_sp_value = 0; | |
696 | } | |
697 | ||
698 | if (prolog_done && prolog_end == end_addr) | |
699 | { | |
700 | /* We found non-prolog code. As such, _this_ instruction | |
701 | is the one after the prolog. We keep processing, because | |
702 | there may be more prolog code in there, but this is what | |
703 | we'll return. */ | |
704 | /* ISSUE: There may not have actually been a prologue, and | |
705 | we may have simply skipped some random instructions. */ | |
706 | prolog_end = next_addr; | |
707 | } | |
708 | if (branch_seen) | |
709 | { | |
710 | /* We saw a branch. The prolog absolutely must be over. */ | |
711 | break; | |
712 | } | |
713 | } | |
714 | ||
715 | if (prolog_end == end_addr && cache) | |
716 | { | |
717 | /* We may have terminated the prolog early, and we're certainly | |
718 | at THIS point right now. It's possible that the values of | |
719 | registers we need are currently actually in other registers | |
720 | (and haven't been written to memory yet). Go find them. */ | |
721 | for (i = 0; i < TILEGX_NUM_PHYS_REGS; i++) | |
722 | { | |
723 | if (reverse_frame[i].state == REVERSE_STATE_REGISTER | |
724 | && reverse_frame[i].value != i) | |
725 | { | |
726 | unsigned saved_register = (unsigned) reverse_frame[i].value; | |
727 | ||
728 | cache->saved_regs[saved_register].realreg = i; | |
729 | cache->saved_regs[saved_register].addr = (LONGEST) -1; | |
730 | } | |
731 | } | |
732 | } | |
733 | ||
3361b059 WL |
734 | if (lr_saved_on_stack_p) |
735 | { | |
736 | cache->saved_regs[TILEGX_LR_REGNUM].realreg = TILEGX_LR_REGNUM; | |
737 | cache->saved_regs[TILEGX_LR_REGNUM].addr = | |
738 | cache->saved_regs[TILEGX_SP_REGNUM].addr; | |
739 | } | |
740 | ||
ade64f0e PA |
741 | return prolog_end; |
742 | } | |
743 | ||
744 | /* This is the implementation of gdbarch method skip_prologue. */ | |
745 | ||
746 | static CORE_ADDR | |
3e9d5130 | 747 | tilegx_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
ade64f0e | 748 | { |
d79e58d8 JW |
749 | CORE_ADDR func_start, end_pc; |
750 | struct obj_section *s; | |
ade64f0e PA |
751 | |
752 | /* This is the preferred method, find the end of the prologue by | |
753 | using the debugging information. */ | |
3e9d5130 | 754 | if (find_pc_partial_function (start_pc, NULL, &func_start, NULL)) |
ade64f0e | 755 | { |
3e9d5130 WL |
756 | CORE_ADDR post_prologue_pc |
757 | = skip_prologue_using_sal (gdbarch, func_start); | |
ade64f0e | 758 | |
3e9d5130 WL |
759 | if (post_prologue_pc != 0) |
760 | return max (start_pc, post_prologue_pc); | |
ade64f0e PA |
761 | } |
762 | ||
d79e58d8 JW |
763 | /* Don't straddle a section boundary. */ |
764 | s = find_pc_section (start_pc); | |
765 | end_pc = start_pc + 8 * TILEGX_BUNDLE_SIZE_IN_BYTES; | |
766 | if (s != NULL) | |
767 | end_pc = min (end_pc, obj_section_endaddr (s)); | |
768 | ||
ade64f0e PA |
769 | /* Otherwise, try to skip prologue the hard way. */ |
770 | return tilegx_analyze_prologue (gdbarch, | |
3e9d5130 | 771 | start_pc, |
d79e58d8 | 772 | end_pc, |
ade64f0e PA |
773 | NULL, NULL); |
774 | } | |
775 | ||
776 | /* This is the implementation of gdbarch method in_function_epilogue_p. */ | |
777 | ||
778 | static int | |
779 | tilegx_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
780 | { | |
781 | CORE_ADDR func_addr = 0, func_end = 0; | |
782 | ||
783 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
784 | { | |
785 | ULONGEST inst, inst2; | |
786 | CORE_ADDR addr = func_end - TILEGX_BUNDLE_SIZE_IN_BYTES; | |
787 | ||
788 | /* FIXME: Find the actual epilogue. */ | |
789 | /* HACK: Just assume the final bundle is the "ret" instruction". */ | |
790 | if (pc > addr) | |
791 | return 1; | |
792 | } | |
793 | return 0; | |
794 | } | |
795 | ||
61d8bd0e JW |
796 | /* This is the implementation of gdbarch method get_longjmp_target. */ |
797 | ||
798 | static int | |
799 | tilegx_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) | |
800 | { | |
801 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
802 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
803 | CORE_ADDR jb_addr; | |
804 | gdb_byte buf[8]; | |
805 | ||
806 | jb_addr = get_frame_register_unsigned (frame, TILEGX_R0_REGNUM); | |
807 | ||
808 | /* TileGX jmp_buf contains 32 elements of type __uint_reg_t which | |
809 | has a size of 8 bytes. The return address is stored in the 25th | |
810 | slot. */ | |
811 | if (target_read_memory (jb_addr + 25 * 8, buf, 8)) | |
812 | return 0; | |
813 | ||
814 | *pc = extract_unsigned_integer (buf, 8, byte_order); | |
815 | ||
816 | return 1; | |
817 | } | |
818 | ||
4aaf2503 WL |
819 | /* by assigning the 'faultnum' reg in kernel pt_regs with this value, |
820 | kernel do_signal will not check r0. see tilegx kernel/signal.c | |
821 | for details. */ | |
822 | #define INT_SWINT_1_SIGRETURN (~0) | |
823 | ||
824 | /* Implement the "write_pc" gdbarch method. */ | |
825 | ||
826 | static void | |
827 | tilegx_write_pc (struct regcache *regcache, CORE_ADDR pc) | |
828 | { | |
829 | regcache_cooked_write_unsigned (regcache, TILEGX_PC_REGNUM, pc); | |
830 | ||
831 | /* We must be careful with modifying the program counter. If we | |
832 | just interrupted a system call, the kernel might try to restart | |
833 | it when we resume the inferior. On restarting the system call, | |
834 | the kernel will try backing up the program counter even though it | |
835 | no longer points at the system call. This typically results in a | |
836 | SIGSEGV or SIGILL. We can prevent this by writing INT_SWINT_1_SIGRETURN | |
837 | in the "faultnum" pseudo-register. | |
838 | ||
839 | Note that "faultnum" is saved when setting up a dummy call frame. | |
840 | This means that it is properly restored when that frame is | |
841 | popped, and that the interrupted system call will be restarted | |
842 | when we resume the inferior on return from a function call from | |
843 | within GDB. In all other cases the system call will not be | |
844 | restarted. */ | |
845 | regcache_cooked_write_unsigned (regcache, TILEGX_FAULTNUM_REGNUM, | |
846 | INT_SWINT_1_SIGRETURN); | |
847 | } | |
848 | ||
ade64f0e PA |
849 | /* This is the implementation of gdbarch method breakpoint_from_pc. */ |
850 | ||
851 | static const unsigned char * | |
852 | tilegx_breakpoint_from_pc (struct gdbarch *gdbarch, | |
853 | CORE_ADDR *pcptr, int *lenptr) | |
854 | { | |
855 | /* 64-bit pattern for a { bpt ; nop } bundle. */ | |
856 | static const unsigned char breakpoint[] = | |
857 | { 0x00, 0x50, 0x48, 0x51, 0xae, 0x44, 0x6a, 0x28 }; | |
858 | ||
859 | *lenptr = sizeof (breakpoint); | |
860 | return breakpoint; | |
861 | } | |
862 | ||
863 | /* Normal frames. */ | |
864 | ||
865 | static struct tilegx_frame_cache * | |
866 | tilegx_frame_cache (struct frame_info *this_frame, void **this_cache) | |
867 | { | |
868 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
869 | struct tilegx_frame_cache *cache; | |
870 | CORE_ADDR current_pc; | |
871 | int i; | |
872 | ||
873 | if (*this_cache) | |
874 | return *this_cache; | |
875 | ||
876 | cache = FRAME_OBSTACK_ZALLOC (struct tilegx_frame_cache); | |
877 | *this_cache = cache; | |
878 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
879 | cache->base = 0; | |
880 | cache->start_pc = get_frame_func (this_frame); | |
881 | current_pc = get_frame_pc (this_frame); | |
882 | ||
883 | cache->base = get_frame_register_unsigned (this_frame, TILEGX_SP_REGNUM); | |
884 | trad_frame_set_value (cache->saved_regs, TILEGX_SP_REGNUM, cache->base); | |
885 | ||
ade64f0e PA |
886 | if (cache->start_pc) |
887 | tilegx_analyze_prologue (gdbarch, cache->start_pc, current_pc, | |
888 | cache, this_frame); | |
889 | ||
3361b059 WL |
890 | cache->saved_regs[TILEGX_PC_REGNUM] = cache->saved_regs[TILEGX_LR_REGNUM]; |
891 | ||
ade64f0e PA |
892 | return cache; |
893 | } | |
894 | ||
895 | /* Retrieve the value of REGNUM in FRAME. */ | |
896 | ||
897 | static struct value* | |
898 | tilegx_frame_prev_register (struct frame_info *this_frame, | |
899 | void **this_cache, | |
900 | int regnum) | |
901 | { | |
902 | struct tilegx_frame_cache *info = | |
903 | tilegx_frame_cache (this_frame, this_cache); | |
904 | ||
905 | return trad_frame_get_prev_register (this_frame, info->saved_regs, | |
906 | regnum); | |
907 | } | |
908 | ||
909 | /* Build frame id. */ | |
910 | ||
911 | static void | |
912 | tilegx_frame_this_id (struct frame_info *this_frame, void **this_cache, | |
913 | struct frame_id *this_id) | |
914 | { | |
915 | struct tilegx_frame_cache *info = | |
916 | tilegx_frame_cache (this_frame, this_cache); | |
917 | ||
918 | /* This marks the outermost frame. */ | |
919 | if (info->base == 0) | |
920 | return; | |
921 | ||
922 | (*this_id) = frame_id_build (info->base, info->start_pc); | |
923 | } | |
924 | ||
925 | static CORE_ADDR | |
926 | tilegx_frame_base_address (struct frame_info *this_frame, void **this_cache) | |
927 | { | |
928 | struct tilegx_frame_cache *cache = | |
929 | tilegx_frame_cache (this_frame, this_cache); | |
930 | ||
931 | return cache->base; | |
932 | } | |
933 | ||
934 | static const struct frame_unwind tilegx_frame_unwind = { | |
935 | NORMAL_FRAME, | |
936 | default_frame_unwind_stop_reason, | |
937 | tilegx_frame_this_id, | |
938 | tilegx_frame_prev_register, | |
939 | NULL, /* const struct frame_data *unwind_data */ | |
940 | default_frame_sniffer, /* frame_sniffer_ftype *sniffer */ | |
941 | NULL /* frame_prev_pc_ftype *prev_pc */ | |
942 | }; | |
943 | ||
944 | static const struct frame_base tilegx_frame_base = { | |
945 | &tilegx_frame_unwind, | |
946 | tilegx_frame_base_address, | |
947 | tilegx_frame_base_address, | |
948 | tilegx_frame_base_address | |
949 | }; | |
950 | ||
951 | static CORE_ADDR | |
952 | tilegx_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
953 | { | |
954 | return frame_unwind_register_unsigned (next_frame, TILEGX_SP_REGNUM); | |
955 | } | |
956 | ||
957 | static CORE_ADDR | |
958 | tilegx_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
959 | { | |
960 | return frame_unwind_register_unsigned (next_frame, TILEGX_PC_REGNUM); | |
961 | } | |
962 | ||
963 | static struct frame_id | |
964 | tilegx_unwind_dummy_id (struct gdbarch *gdbarch, | |
965 | struct frame_info *this_frame) | |
966 | { | |
967 | CORE_ADDR sp; | |
968 | ||
969 | sp = get_frame_register_unsigned (this_frame, TILEGX_SP_REGNUM); | |
970 | return frame_id_build (sp, get_frame_pc (this_frame)); | |
971 | } | |
972 | ||
973 | ||
974 | /* We cannot read/write the "special" registers. */ | |
975 | ||
976 | static int | |
977 | tilegx_cannot_reference_register (struct gdbarch *gdbarch, int regno) | |
978 | { | |
979 | if (regno >= 0 && regno < TILEGX_NUM_EASY_REGS) | |
980 | return 0; | |
4aaf2503 WL |
981 | else if (regno == TILEGX_PC_REGNUM |
982 | || regno == TILEGX_FAULTNUM_REGNUM) | |
ade64f0e PA |
983 | return 0; |
984 | else | |
985 | return 1; | |
986 | } | |
987 | ||
988 | static struct gdbarch * | |
989 | tilegx_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
990 | { | |
991 | struct gdbarch *gdbarch; | |
992 | int arch_size = 64; | |
993 | ||
994 | /* Handle arch_size == 32 or 64. Default to 64. */ | |
995 | if (info.abfd) | |
996 | arch_size = bfd_get_arch_size (info.abfd); | |
997 | ||
998 | /* Try to find a pre-existing architecture. */ | |
999 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
1000 | arches != NULL; | |
1001 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
1002 | { | |
1003 | /* We only have two flavors -- just make sure arch_size matches. */ | |
1004 | if (gdbarch_ptr_bit (arches->gdbarch) == arch_size) | |
1005 | return (arches->gdbarch); | |
1006 | } | |
1007 | ||
1008 | gdbarch = gdbarch_alloc (&info, NULL); | |
1009 | ||
1010 | /* Basic register fields and methods, datatype sizes and stuff. */ | |
1011 | ||
1012 | /* There are 64 physical registers which can be referenced by | |
1013 | instructions (although only 56 of them can actually be | |
1014 | debugged) and 1 magic register (the PC). The other three | |
1015 | magic registers (ex1, syscall, orig_r0) which are known to | |
1016 | "ptrace" are ignored by "gdb". Note that we simply pretend | |
1017 | that there are 65 registers, and no "pseudo registers". */ | |
1018 | set_gdbarch_num_regs (gdbarch, TILEGX_NUM_REGS); | |
1019 | set_gdbarch_num_pseudo_regs (gdbarch, 0); | |
1020 | ||
1021 | set_gdbarch_sp_regnum (gdbarch, TILEGX_SP_REGNUM); | |
1022 | set_gdbarch_pc_regnum (gdbarch, TILEGX_PC_REGNUM); | |
1023 | ||
1024 | set_gdbarch_register_name (gdbarch, tilegx_register_name); | |
1025 | set_gdbarch_register_type (gdbarch, tilegx_register_type); | |
1026 | ||
ade64f0e PA |
1027 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
1028 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1029 | set_gdbarch_long_bit (gdbarch, arch_size); | |
1030 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
1031 | ||
1032 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1033 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
1034 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
1035 | ||
1036 | set_gdbarch_ptr_bit (gdbarch, arch_size); | |
1037 | set_gdbarch_addr_bit (gdbarch, arch_size); | |
1038 | ||
1039 | set_gdbarch_cannot_fetch_register (gdbarch, | |
1040 | tilegx_cannot_reference_register); | |
1041 | set_gdbarch_cannot_store_register (gdbarch, | |
1042 | tilegx_cannot_reference_register); | |
1043 | ||
1044 | /* Stack grows down. */ | |
1045 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1046 | ||
1047 | /* Frame Info. */ | |
1048 | set_gdbarch_unwind_sp (gdbarch, tilegx_unwind_sp); | |
1049 | set_gdbarch_unwind_pc (gdbarch, tilegx_unwind_pc); | |
1050 | set_gdbarch_dummy_id (gdbarch, tilegx_unwind_dummy_id); | |
1051 | set_gdbarch_frame_align (gdbarch, tilegx_frame_align); | |
1052 | frame_base_set_default (gdbarch, &tilegx_frame_base); | |
1053 | ||
1054 | set_gdbarch_skip_prologue (gdbarch, tilegx_skip_prologue); | |
1055 | ||
1056 | set_gdbarch_in_function_epilogue_p (gdbarch, | |
1057 | tilegx_in_function_epilogue_p); | |
1058 | ||
1059 | /* Map debug registers into internal register numbers. */ | |
1060 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, tilegx_dwarf2_reg_to_regnum); | |
1061 | ||
1062 | /* These values and methods are used when gdb calls a target function. */ | |
1063 | set_gdbarch_push_dummy_call (gdbarch, tilegx_push_dummy_call); | |
61d8bd0e | 1064 | set_gdbarch_get_longjmp_target (gdbarch, tilegx_get_longjmp_target); |
4aaf2503 | 1065 | set_gdbarch_write_pc (gdbarch, tilegx_write_pc); |
ade64f0e PA |
1066 | set_gdbarch_breakpoint_from_pc (gdbarch, tilegx_breakpoint_from_pc); |
1067 | set_gdbarch_return_value (gdbarch, tilegx_return_value); | |
1068 | ||
1069 | set_gdbarch_print_insn (gdbarch, print_insn_tilegx); | |
1070 | ||
1071 | gdbarch_init_osabi (info, gdbarch); | |
1072 | ||
1073 | dwarf2_append_unwinders (gdbarch); | |
1074 | frame_unwind_append_unwinder (gdbarch, &tilegx_frame_unwind); | |
1075 | ||
1076 | return gdbarch; | |
1077 | } | |
1078 | ||
1079 | /* Provide a prototype to silence -Wmissing-prototypes. */ | |
1080 | extern initialize_file_ftype _initialize_tilegx_tdep; | |
1081 | ||
1082 | void | |
1083 | _initialize_tilegx_tdep (void) | |
1084 | { | |
1085 | register_gdbarch_init (bfd_arch_tilegx, tilegx_gdbarch_init); | |
1086 | } |