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53e95fcf | 1 | /* Target-dependent code for the x86-64 for GDB, the GNU debugger. |
ce0eebec | 2 | |
51603483 | 3 | Copyright 2001, 2002, 2003 Free Software Foundation, Inc. |
53e95fcf JS |
4 | Contributed by Jiri Smid, SuSE Labs. |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
22 | ||
23 | #include "defs.h" | |
c4f35dd8 MK |
24 | #include "arch-utils.h" |
25 | #include "block.h" | |
26 | #include "dummy-frame.h" | |
27 | #include "frame.h" | |
28 | #include "frame-base.h" | |
29 | #include "frame-unwind.h" | |
53e95fcf | 30 | #include "inferior.h" |
53e95fcf | 31 | #include "gdbcmd.h" |
c4f35dd8 MK |
32 | #include "gdbcore.h" |
33 | #include "objfiles.h" | |
53e95fcf | 34 | #include "regcache.h" |
2c261fae | 35 | #include "regset.h" |
53e95fcf | 36 | #include "symfile.h" |
c4f35dd8 | 37 | |
82dbc5f7 | 38 | #include "gdb_assert.h" |
c4f35dd8 MK |
39 | |
40 | #include "x86-64-tdep.h" | |
41 | #include "i387-tdep.h" | |
53e95fcf | 42 | |
402ecd56 | 43 | /* Register information. */ |
c4f35dd8 MK |
44 | |
45 | struct x86_64_register_info | |
de220d0f | 46 | { |
de220d0f ML |
47 | char *name; |
48 | struct type **type; | |
49 | }; | |
53e95fcf | 50 | |
c4f35dd8 MK |
51 | static struct x86_64_register_info x86_64_register_info[] = |
52 | { | |
53 | { "rax", &builtin_type_int64 }, | |
54 | { "rbx", &builtin_type_int64 }, | |
55 | { "rcx", &builtin_type_int64 }, | |
56 | { "rdx", &builtin_type_int64 }, | |
57 | { "rsi", &builtin_type_int64 }, | |
58 | { "rdi", &builtin_type_int64 }, | |
59 | { "rbp", &builtin_type_void_data_ptr }, | |
60 | { "rsp", &builtin_type_void_data_ptr }, | |
61 | ||
62 | /* %r8 is indeed register number 8. */ | |
63 | { "r8", &builtin_type_int64 }, | |
64 | { "r9", &builtin_type_int64 }, | |
65 | { "r10", &builtin_type_int64 }, | |
66 | { "r11", &builtin_type_int64 }, | |
67 | { "r12", &builtin_type_int64 }, | |
68 | { "r13", &builtin_type_int64 }, | |
69 | { "r14", &builtin_type_int64 }, | |
70 | { "r15", &builtin_type_int64 }, | |
71 | { "rip", &builtin_type_void_func_ptr }, | |
72 | { "eflags", &builtin_type_int32 }, | |
73 | { "ds", &builtin_type_int32 }, | |
74 | { "es", &builtin_type_int32 }, | |
75 | { "fs", &builtin_type_int32 }, | |
76 | { "gs", &builtin_type_int32 }, | |
77 | ||
78 | /* %st0 is register number 22. */ | |
79 | { "st0", &builtin_type_i387_ext }, | |
80 | { "st1", &builtin_type_i387_ext }, | |
81 | { "st2", &builtin_type_i387_ext }, | |
82 | { "st3", &builtin_type_i387_ext }, | |
83 | { "st4", &builtin_type_i387_ext }, | |
84 | { "st5", &builtin_type_i387_ext }, | |
85 | { "st6", &builtin_type_i387_ext }, | |
86 | { "st7", &builtin_type_i387_ext }, | |
87 | { "fctrl", &builtin_type_int32 }, | |
88 | { "fstat", &builtin_type_int32 }, | |
89 | { "ftag", &builtin_type_int32 }, | |
90 | { "fiseg", &builtin_type_int32 }, | |
91 | { "fioff", &builtin_type_int32 }, | |
92 | { "foseg", &builtin_type_int32 }, | |
93 | { "fooff", &builtin_type_int32 }, | |
94 | { "fop", &builtin_type_int32 }, | |
95 | ||
96 | /* %xmm0 is register number 38. */ | |
97 | { "xmm0", &builtin_type_v4sf }, | |
98 | { "xmm1", &builtin_type_v4sf }, | |
99 | { "xmm2", &builtin_type_v4sf }, | |
100 | { "xmm3", &builtin_type_v4sf }, | |
101 | { "xmm4", &builtin_type_v4sf }, | |
102 | { "xmm5", &builtin_type_v4sf }, | |
103 | { "xmm6", &builtin_type_v4sf }, | |
104 | { "xmm7", &builtin_type_v4sf }, | |
105 | { "xmm8", &builtin_type_v4sf }, | |
106 | { "xmm9", &builtin_type_v4sf }, | |
107 | { "xmm10", &builtin_type_v4sf }, | |
108 | { "xmm11", &builtin_type_v4sf }, | |
109 | { "xmm12", &builtin_type_v4sf }, | |
110 | { "xmm13", &builtin_type_v4sf }, | |
111 | { "xmm14", &builtin_type_v4sf }, | |
112 | { "xmm15", &builtin_type_v4sf }, | |
113 | { "mxcsr", &builtin_type_int32 } | |
0e04a514 ML |
114 | }; |
115 | ||
c4f35dd8 MK |
116 | /* Total number of registers. */ |
117 | #define X86_64_NUM_REGS \ | |
118 | (sizeof (x86_64_register_info) / sizeof (x86_64_register_info[0])) | |
de220d0f | 119 | |
c4f35dd8 | 120 | /* Return the name of register REGNUM. */ |
b6779aa2 | 121 | |
c4f35dd8 MK |
122 | static const char * |
123 | x86_64_register_name (int regnum) | |
53e95fcf | 124 | { |
c4f35dd8 MK |
125 | if (regnum >= 0 && regnum < X86_64_NUM_REGS) |
126 | return x86_64_register_info[regnum].name; | |
53e95fcf | 127 | |
c4f35dd8 | 128 | return NULL; |
53e95fcf JS |
129 | } |
130 | ||
131 | /* Return the GDB type object for the "standard" data type of data in | |
c4f35dd8 | 132 | register REGNUM. */ |
53e95fcf | 133 | |
c4f35dd8 MK |
134 | static struct type * |
135 | x86_64_register_type (struct gdbarch *gdbarch, int regnum) | |
53e95fcf | 136 | { |
c4f35dd8 | 137 | gdb_assert (regnum >= 0 && regnum < X86_64_NUM_REGS); |
4657573b | 138 | |
c4f35dd8 | 139 | return *x86_64_register_info[regnum].type; |
53e95fcf JS |
140 | } |
141 | ||
c4f35dd8 MK |
142 | /* DWARF Register Number Mapping as defined in the System V psABI, |
143 | section 3.6. */ | |
53e95fcf | 144 | |
c4f35dd8 | 145 | static int x86_64_dwarf_regmap[] = |
0e04a514 | 146 | { |
c4f35dd8 | 147 | /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */ |
f82b2acd | 148 | X86_64_RAX_REGNUM, X86_64_RDX_REGNUM, 2, 1, |
c4f35dd8 MK |
149 | 4, X86_64_RDI_REGNUM, |
150 | ||
151 | /* Frame Pointer Register RBP. */ | |
152 | X86_64_RBP_REGNUM, | |
153 | ||
154 | /* Stack Pointer Register RSP. */ | |
155 | X86_64_RSP_REGNUM, | |
156 | ||
157 | /* Extended Integer Registers 8 - 15. */ | |
158 | 8, 9, 10, 11, 12, 13, 14, 15, | |
159 | ||
160 | /* Return Address RA. Not mapped. */ | |
161 | -1, | |
162 | ||
163 | /* SSE Registers 0 - 7. */ | |
164 | X86_64_XMM0_REGNUM + 0, X86_64_XMM1_REGNUM, | |
165 | X86_64_XMM0_REGNUM + 2, X86_64_XMM0_REGNUM + 3, | |
166 | X86_64_XMM0_REGNUM + 4, X86_64_XMM0_REGNUM + 5, | |
167 | X86_64_XMM0_REGNUM + 6, X86_64_XMM0_REGNUM + 7, | |
168 | ||
169 | /* Extended SSE Registers 8 - 15. */ | |
170 | X86_64_XMM0_REGNUM + 8, X86_64_XMM0_REGNUM + 9, | |
171 | X86_64_XMM0_REGNUM + 10, X86_64_XMM0_REGNUM + 11, | |
172 | X86_64_XMM0_REGNUM + 12, X86_64_XMM0_REGNUM + 13, | |
173 | X86_64_XMM0_REGNUM + 14, X86_64_XMM0_REGNUM + 15, | |
174 | ||
175 | /* Floating Point Registers 0-7. */ | |
f82b2acd | 176 | X86_64_ST0_REGNUM + 0, X86_64_ST0_REGNUM + 1, |
c4f35dd8 MK |
177 | X86_64_ST0_REGNUM + 2, X86_64_ST0_REGNUM + 3, |
178 | X86_64_ST0_REGNUM + 4, X86_64_ST0_REGNUM + 5, | |
179 | X86_64_ST0_REGNUM + 6, X86_64_ST0_REGNUM + 7 | |
180 | }; | |
0e04a514 | 181 | |
c4f35dd8 MK |
182 | static const int x86_64_dwarf_regmap_len = |
183 | (sizeof (x86_64_dwarf_regmap) / sizeof (x86_64_dwarf_regmap[0])); | |
0e04a514 | 184 | |
c4f35dd8 MK |
185 | /* Convert DWARF register number REG to the appropriate register |
186 | number used by GDB. */ | |
26abbdc4 | 187 | |
c4f35dd8 MK |
188 | static int |
189 | x86_64_dwarf_reg_to_regnum (int reg) | |
53e95fcf | 190 | { |
c4f35dd8 | 191 | int regnum = -1; |
53e95fcf | 192 | |
c4f35dd8 MK |
193 | if (reg >= 0 || reg < x86_64_dwarf_regmap_len) |
194 | regnum = x86_64_dwarf_regmap[reg]; | |
53e95fcf | 195 | |
c4f35dd8 MK |
196 | if (regnum == -1) |
197 | warning ("Unmapped DWARF Register #%d encountered\n", reg); | |
198 | ||
199 | return regnum; | |
53e95fcf | 200 | } |
d532c08f MK |
201 | |
202 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
203 | needs any special handling. */ | |
204 | ||
205 | static int | |
206 | x86_64_convert_register_p (int regnum, struct type *type) | |
207 | { | |
208 | return i386_fp_regnum_p (regnum); | |
209 | } | |
53e95fcf JS |
210 | \f |
211 | ||
212 | /* The returning of values is done according to the special algorithm. | |
c4f35dd8 MK |
213 | Some types are returned in registers an some (big structures) in |
214 | memory. See the System V psABI for details. */ | |
53e95fcf JS |
215 | |
216 | #define MAX_CLASSES 4 | |
217 | ||
218 | enum x86_64_reg_class | |
219 | { | |
220 | X86_64_NO_CLASS, | |
221 | X86_64_INTEGER_CLASS, | |
222 | X86_64_INTEGERSI_CLASS, | |
223 | X86_64_SSE_CLASS, | |
224 | X86_64_SSESF_CLASS, | |
225 | X86_64_SSEDF_CLASS, | |
226 | X86_64_SSEUP_CLASS, | |
227 | X86_64_X87_CLASS, | |
228 | X86_64_X87UP_CLASS, | |
229 | X86_64_MEMORY_CLASS | |
230 | }; | |
231 | ||
232 | /* Return the union class of CLASS1 and CLASS2. | |
c4f35dd8 | 233 | See the System V psABI for details. */ |
53e95fcf JS |
234 | |
235 | static enum x86_64_reg_class | |
236 | merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2) | |
237 | { | |
c4f35dd8 | 238 | /* Rule (a): If both classes are equal, this is the resulting class. */ |
53e95fcf JS |
239 | if (class1 == class2) |
240 | return class1; | |
241 | ||
c4f35dd8 | 242 | /* Rule (b): If one of the classes is NO_CLASS, the resulting class |
26abbdc4 | 243 | is the other class. */ |
53e95fcf JS |
244 | if (class1 == X86_64_NO_CLASS) |
245 | return class2; | |
246 | if (class2 == X86_64_NO_CLASS) | |
247 | return class1; | |
248 | ||
c4f35dd8 | 249 | /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */ |
53e95fcf JS |
250 | if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS) |
251 | return X86_64_MEMORY_CLASS; | |
252 | ||
c4f35dd8 | 253 | /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */ |
53e95fcf JS |
254 | if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS) |
255 | || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS)) | |
256 | return X86_64_INTEGERSI_CLASS; | |
257 | if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS | |
258 | || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS) | |
259 | return X86_64_INTEGER_CLASS; | |
260 | ||
c4f35dd8 MK |
261 | /* Rule (e): If one of the classes is X87 or X87UP class, MEMORY is |
262 | used as class. */ | |
53e95fcf JS |
263 | if (class1 == X86_64_X87_CLASS || class1 == X86_64_X87UP_CLASS |
264 | || class2 == X86_64_X87_CLASS || class2 == X86_64_X87UP_CLASS) | |
265 | return X86_64_MEMORY_CLASS; | |
266 | ||
c4f35dd8 | 267 | /* Rule (f): Otherwise class SSE is used. */ |
53e95fcf JS |
268 | return X86_64_SSE_CLASS; |
269 | } | |
270 | ||
26abbdc4 MK |
271 | /* Classify the argument type. CLASSES will be filled by the register |
272 | class used to pass each word of the operand. The number of words | |
273 | is returned. In case the parameter should be passed in memory, 0 | |
274 | is returned. As a special case for zero sized containers, | |
275 | classes[0] will be NO_CLASS and 1 is returned. | |
53e95fcf | 276 | |
c4f35dd8 | 277 | See the System V psABI for details. */ |
53e95fcf JS |
278 | |
279 | static int | |
280 | classify_argument (struct type *type, | |
281 | enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset) | |
282 | { | |
283 | int bytes = TYPE_LENGTH (type); | |
284 | int words = (bytes + 8 - 1) / 8; | |
285 | ||
286 | switch (TYPE_CODE (type)) | |
287 | { | |
288 | case TYPE_CODE_ARRAY: | |
289 | case TYPE_CODE_STRUCT: | |
290 | case TYPE_CODE_UNION: | |
291 | { | |
292 | int i; | |
293 | enum x86_64_reg_class subclasses[MAX_CLASSES]; | |
294 | ||
295 | /* On x86-64 we pass structures larger than 16 bytes on the stack. */ | |
296 | if (bytes > 16) | |
297 | return 0; | |
298 | ||
299 | for (i = 0; i < words; i++) | |
300 | classes[i] = X86_64_NO_CLASS; | |
301 | ||
26abbdc4 MK |
302 | /* Zero sized arrays or structures are NO_CLASS. We return 0 |
303 | to signalize memory class, so handle it as special case. */ | |
53e95fcf JS |
304 | if (!words) |
305 | { | |
306 | classes[0] = X86_64_NO_CLASS; | |
307 | return 1; | |
308 | } | |
309 | switch (TYPE_CODE (type)) | |
310 | { | |
311 | case TYPE_CODE_STRUCT: | |
312 | { | |
313 | int j; | |
0004e5a2 | 314 | for (j = 0; j < TYPE_NFIELDS (type); ++j) |
53e95fcf | 315 | { |
0004e5a2 | 316 | int num = classify_argument (TYPE_FIELDS (type)[j].type, |
53e95fcf | 317 | subclasses, |
8dda9770 ML |
318 | (TYPE_FIELDS (type)[j].loc. |
319 | bitpos + bit_offset) % 256); | |
53e95fcf JS |
320 | if (!num) |
321 | return 0; | |
322 | for (i = 0; i < num; i++) | |
323 | { | |
324 | int pos = | |
8dda9770 ML |
325 | (TYPE_FIELDS (type)[j].loc.bitpos + |
326 | bit_offset) / 8 / 8; | |
53e95fcf JS |
327 | classes[i + pos] = |
328 | merge_classes (subclasses[i], classes[i + pos]); | |
329 | } | |
330 | } | |
331 | } | |
332 | break; | |
333 | case TYPE_CODE_ARRAY: | |
334 | { | |
335 | int num; | |
336 | ||
0004e5a2 | 337 | num = classify_argument (TYPE_TARGET_TYPE (type), |
53e95fcf JS |
338 | subclasses, bit_offset); |
339 | if (!num) | |
340 | return 0; | |
341 | ||
342 | /* The partial classes are now full classes. */ | |
343 | if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4) | |
344 | subclasses[0] = X86_64_SSE_CLASS; | |
345 | if (subclasses[0] == X86_64_INTEGERSI_CLASS && bytes != 4) | |
346 | subclasses[0] = X86_64_INTEGER_CLASS; | |
347 | ||
348 | for (i = 0; i < words; i++) | |
349 | classes[i] = subclasses[i % num]; | |
350 | } | |
351 | break; | |
352 | case TYPE_CODE_UNION: | |
353 | { | |
354 | int j; | |
355 | { | |
0004e5a2 | 356 | for (j = 0; j < TYPE_NFIELDS (type); ++j) |
53e95fcf JS |
357 | { |
358 | int num; | |
0004e5a2 | 359 | num = classify_argument (TYPE_FIELDS (type)[j].type, |
53e95fcf JS |
360 | subclasses, bit_offset); |
361 | if (!num) | |
362 | return 0; | |
363 | for (i = 0; i < num; i++) | |
364 | classes[i] = merge_classes (subclasses[i], classes[i]); | |
365 | } | |
366 | } | |
367 | } | |
368 | break; | |
4657573b ML |
369 | default: |
370 | break; | |
53e95fcf JS |
371 | } |
372 | /* Final merger cleanup. */ | |
373 | for (i = 0; i < words; i++) | |
374 | { | |
375 | /* If one class is MEMORY, everything should be passed in | |
376 | memory. */ | |
377 | if (classes[i] == X86_64_MEMORY_CLASS) | |
378 | return 0; | |
379 | ||
380 | /* The X86_64_SSEUP_CLASS should be always preceeded by | |
381 | X86_64_SSE_CLASS. */ | |
382 | if (classes[i] == X86_64_SSEUP_CLASS | |
383 | && (i == 0 || classes[i - 1] != X86_64_SSE_CLASS)) | |
384 | classes[i] = X86_64_SSE_CLASS; | |
385 | ||
26abbdc4 | 386 | /* X86_64_X87UP_CLASS should be preceeded by X86_64_X87_CLASS. */ |
53e95fcf JS |
387 | if (classes[i] == X86_64_X87UP_CLASS |
388 | && (i == 0 || classes[i - 1] != X86_64_X87_CLASS)) | |
389 | classes[i] = X86_64_SSE_CLASS; | |
390 | } | |
391 | return words; | |
392 | } | |
393 | break; | |
394 | case TYPE_CODE_FLT: | |
395 | switch (bytes) | |
396 | { | |
397 | case 4: | |
398 | if (!(bit_offset % 64)) | |
399 | classes[0] = X86_64_SSESF_CLASS; | |
400 | else | |
401 | classes[0] = X86_64_SSE_CLASS; | |
402 | return 1; | |
403 | case 8: | |
404 | classes[0] = X86_64_SSEDF_CLASS; | |
405 | return 1; | |
406 | case 16: | |
407 | classes[0] = X86_64_X87_CLASS; | |
408 | classes[1] = X86_64_X87UP_CLASS; | |
409 | return 2; | |
410 | } | |
411 | break; | |
50c46a0d EZ |
412 | case TYPE_CODE_ENUM: |
413 | case TYPE_CODE_REF: | |
53e95fcf JS |
414 | case TYPE_CODE_INT: |
415 | case TYPE_CODE_PTR: | |
416 | switch (bytes) | |
417 | { | |
418 | case 1: | |
419 | case 2: | |
420 | case 4: | |
421 | case 8: | |
422 | if (bytes * 8 + bit_offset <= 32) | |
423 | classes[0] = X86_64_INTEGERSI_CLASS; | |
424 | else | |
425 | classes[0] = X86_64_INTEGER_CLASS; | |
426 | return 1; | |
427 | case 16: | |
428 | classes[0] = classes[1] = X86_64_INTEGER_CLASS; | |
429 | return 2; | |
430 | default: | |
431 | break; | |
432 | } | |
433 | case TYPE_CODE_VOID: | |
434 | return 0; | |
8dda9770 | 435 | default: /* Avoid warning. */ |
4657573b | 436 | break; |
53e95fcf | 437 | } |
ce0eebec AC |
438 | internal_error (__FILE__, __LINE__, |
439 | "classify_argument: unknown argument type"); | |
53e95fcf JS |
440 | } |
441 | ||
26abbdc4 MK |
442 | /* Examine the argument and set *INT_NREGS and *SSE_NREGS to the |
443 | number of registers required based on the information passed in | |
444 | CLASSES. Return 0 if parameter should be passed in memory. */ | |
53e95fcf JS |
445 | |
446 | static int | |
447 | examine_argument (enum x86_64_reg_class classes[MAX_CLASSES], | |
448 | int n, int *int_nregs, int *sse_nregs) | |
449 | { | |
450 | *int_nregs = 0; | |
451 | *sse_nregs = 0; | |
452 | if (!n) | |
453 | return 0; | |
454 | for (n--; n >= 0; n--) | |
455 | switch (classes[n]) | |
456 | { | |
457 | case X86_64_INTEGER_CLASS: | |
458 | case X86_64_INTEGERSI_CLASS: | |
459 | (*int_nregs)++; | |
460 | break; | |
461 | case X86_64_SSE_CLASS: | |
462 | case X86_64_SSESF_CLASS: | |
463 | case X86_64_SSEDF_CLASS: | |
464 | (*sse_nregs)++; | |
465 | break; | |
466 | case X86_64_NO_CLASS: | |
467 | case X86_64_SSEUP_CLASS: | |
468 | case X86_64_X87_CLASS: | |
469 | case X86_64_X87UP_CLASS: | |
470 | break; | |
471 | case X86_64_MEMORY_CLASS: | |
ce0eebec AC |
472 | internal_error (__FILE__, __LINE__, |
473 | "examine_argument: unexpected memory class"); | |
53e95fcf JS |
474 | } |
475 | return 1; | |
476 | } | |
477 | ||
478 | #define RET_INT_REGS 2 | |
479 | #define RET_SSE_REGS 2 | |
480 | ||
481 | /* Check if the structure in value_type is returned in registers or in | |
26abbdc4 MK |
482 | memory. If this function returns 1, GDB will call |
483 | STORE_STRUCT_RETURN and EXTRACT_STRUCT_VALUE_ADDRESS else | |
484 | STORE_RETURN_VALUE and EXTRACT_RETURN_VALUE will be used. */ | |
c4f35dd8 MK |
485 | |
486 | static int | |
53e95fcf JS |
487 | x86_64_use_struct_convention (int gcc_p, struct type *value_type) |
488 | { | |
489 | enum x86_64_reg_class class[MAX_CLASSES]; | |
490 | int n = classify_argument (value_type, class, 0); | |
491 | int needed_intregs; | |
492 | int needed_sseregs; | |
493 | ||
494 | return (!n || | |
495 | !examine_argument (class, n, &needed_intregs, &needed_sseregs) || | |
496 | needed_intregs > RET_INT_REGS || needed_sseregs > RET_SSE_REGS); | |
497 | } | |
498 | ||
53e95fcf JS |
499 | /* Extract from an array REGBUF containing the (raw) register state, a |
500 | function return value of TYPE, and copy that, in virtual format, | |
501 | into VALBUF. */ | |
502 | ||
c4f35dd8 | 503 | static void |
48037ead ML |
504 | x86_64_extract_return_value (struct type *type, struct regcache *regcache, |
505 | void *valbuf) | |
53e95fcf JS |
506 | { |
507 | enum x86_64_reg_class class[MAX_CLASSES]; | |
508 | int n = classify_argument (type, class, 0); | |
509 | int needed_intregs; | |
510 | int needed_sseregs; | |
511 | int intreg = 0; | |
512 | int ssereg = 0; | |
513 | int offset = 0; | |
c4f35dd8 MK |
514 | int ret_int_r[RET_INT_REGS] = { X86_64_RAX_REGNUM, X86_64_RDX_REGNUM }; |
515 | int ret_sse_r[RET_SSE_REGS] = { X86_64_XMM0_REGNUM, X86_64_XMM1_REGNUM }; | |
53e95fcf JS |
516 | |
517 | if (!n || | |
518 | !examine_argument (class, n, &needed_intregs, &needed_sseregs) || | |
519 | needed_intregs > RET_INT_REGS || needed_sseregs > RET_SSE_REGS) | |
520 | { /* memory class */ | |
521 | CORE_ADDR addr; | |
c4f35dd8 | 522 | regcache_cooked_read (regcache, X86_64_RAX_REGNUM, &addr); |
53e95fcf JS |
523 | read_memory (addr, valbuf, TYPE_LENGTH (type)); |
524 | return; | |
525 | } | |
526 | else | |
527 | { | |
528 | int i; | |
529 | for (i = 0; i < n; i++) | |
530 | { | |
531 | switch (class[i]) | |
532 | { | |
533 | case X86_64_NO_CLASS: | |
534 | break; | |
535 | case X86_64_INTEGER_CLASS: | |
48037ead ML |
536 | regcache_cooked_read (regcache, ret_int_r[(intreg + 1) / 2], |
537 | (char *) valbuf + offset); | |
53e95fcf JS |
538 | offset += 8; |
539 | intreg += 2; | |
540 | break; | |
541 | case X86_64_INTEGERSI_CLASS: | |
48037ead ML |
542 | regcache_cooked_read_part (regcache, ret_int_r[intreg / 2], |
543 | 0, 4, (char *) valbuf + offset); | |
53e95fcf JS |
544 | offset += 8; |
545 | intreg++; | |
546 | break; | |
547 | case X86_64_SSEDF_CLASS: | |
548 | case X86_64_SSESF_CLASS: | |
549 | case X86_64_SSE_CLASS: | |
48037ead ML |
550 | regcache_cooked_read_part (regcache, |
551 | ret_sse_r[(ssereg + 1) / 2], 0, 8, | |
552 | (char *) valbuf + offset); | |
53e95fcf JS |
553 | offset += 8; |
554 | ssereg += 2; | |
555 | break; | |
556 | case X86_64_SSEUP_CLASS: | |
48037ead ML |
557 | regcache_cooked_read_part (regcache, ret_sse_r[ssereg / 2], |
558 | 0, 8, (char *) valbuf + offset); | |
53e95fcf JS |
559 | offset += 8; |
560 | ssereg++; | |
561 | break; | |
562 | case X86_64_X87_CLASS: | |
c4f35dd8 | 563 | regcache_cooked_read_part (regcache, X86_64_ST0_REGNUM, |
48037ead | 564 | 0, 8, (char *) valbuf + offset); |
53e95fcf JS |
565 | offset += 8; |
566 | break; | |
567 | case X86_64_X87UP_CLASS: | |
c4f35dd8 | 568 | regcache_cooked_read_part (regcache, X86_64_ST0_REGNUM, |
48037ead | 569 | 8, 2, (char *) valbuf + offset); |
53e95fcf JS |
570 | offset += 8; |
571 | break; | |
572 | case X86_64_MEMORY_CLASS: | |
573 | default: | |
574 | internal_error (__FILE__, __LINE__, | |
575 | "Unexpected argument class"); | |
576 | } | |
577 | } | |
578 | } | |
579 | } | |
580 | ||
53e95fcf | 581 | #define INT_REGS 6 |
c4f35dd8 | 582 | #define SSE_REGS 8 |
53e95fcf | 583 | |
c4f35dd8 MK |
584 | static CORE_ADDR |
585 | x86_64_push_arguments (struct regcache *regcache, int nargs, | |
586 | struct value **args, CORE_ADDR sp) | |
53e95fcf JS |
587 | { |
588 | int intreg = 0; | |
589 | int ssereg = 0; | |
c1da67ba AJ |
590 | /* For varargs functions we have to pass the total number of SSE |
591 | registers used in %rax. So, let's count this number. */ | |
8ffd9b1b AJ |
592 | int total_sse_args = 0; |
593 | /* Once an SSE/int argument is passed on the stack, all subsequent | |
594 | arguments are passed there. */ | |
595 | int sse_stack = 0; | |
596 | int int_stack = 0; | |
c1da67ba | 597 | unsigned total_sp; |
53e95fcf | 598 | int i; |
8ffd9b1b | 599 | char buf[8]; |
c4f35dd8 MK |
600 | static int int_parameter_registers[INT_REGS] = |
601 | { | |
602 | X86_64_RDI_REGNUM, 4, /* %rdi, %rsi */ | |
603 | X86_64_RDX_REGNUM, 2, /* %rdx, %rcx */ | |
604 | 8, 9 /* %r8, %r9 */ | |
ce0eebec | 605 | }; |
c4f35dd8 MK |
606 | /* %xmm0 - %xmm7 */ |
607 | static int sse_parameter_registers[SSE_REGS] = | |
608 | { | |
609 | X86_64_XMM0_REGNUM + 0, X86_64_XMM1_REGNUM, | |
610 | X86_64_XMM0_REGNUM + 2, X86_64_XMM0_REGNUM + 3, | |
611 | X86_64_XMM0_REGNUM + 4, X86_64_XMM0_REGNUM + 5, | |
612 | X86_64_XMM0_REGNUM + 6, X86_64_XMM0_REGNUM + 7, | |
ce0eebec AC |
613 | }; |
614 | int stack_values_count = 0; | |
82dbc5f7 | 615 | int *stack_values; |
e9f30c21 | 616 | stack_values = alloca (nargs * sizeof (int)); |
fd83bada | 617 | |
53e95fcf JS |
618 | for (i = 0; i < nargs; i++) |
619 | { | |
620 | enum x86_64_reg_class class[MAX_CLASSES]; | |
621 | int n = classify_argument (args[i]->type, class, 0); | |
622 | int needed_intregs; | |
623 | int needed_sseregs; | |
624 | ||
625 | if (!n || | |
8ffd9b1b | 626 | !examine_argument (class, n, &needed_intregs, &needed_sseregs)) |
ce0eebec AC |
627 | { /* memory class */ |
628 | stack_values[stack_values_count++] = i; | |
53e95fcf JS |
629 | } |
630 | else | |
631 | { | |
632 | int j; | |
6b53acc6 | 633 | int offset = 0; |
8ffd9b1b AJ |
634 | |
635 | if (intreg / 2 + needed_intregs > INT_REGS) | |
636 | int_stack = 1; | |
637 | if (ssereg / 2 + needed_sseregs > SSE_REGS) | |
638 | sse_stack = 1; | |
c1da67ba AJ |
639 | if (!sse_stack) |
640 | total_sse_args += needed_sseregs; | |
8ffd9b1b | 641 | |
53e95fcf JS |
642 | for (j = 0; j < n; j++) |
643 | { | |
53e95fcf JS |
644 | switch (class[j]) |
645 | { | |
646 | case X86_64_NO_CLASS: | |
647 | break; | |
648 | case X86_64_INTEGER_CLASS: | |
8ffd9b1b AJ |
649 | if (int_stack) |
650 | stack_values[stack_values_count++] = i; | |
651 | else | |
652 | { | |
653 | regcache_cooked_write | |
654 | (regcache, int_parameter_registers[(intreg + 1) / 2], | |
655 | VALUE_CONTENTS_ALL (args[i]) + offset); | |
656 | offset += 8; | |
657 | intreg += 2; | |
658 | } | |
53e95fcf JS |
659 | break; |
660 | case X86_64_INTEGERSI_CLASS: | |
8ffd9b1b AJ |
661 | if (int_stack) |
662 | stack_values[stack_values_count++] = i; | |
663 | else | |
664 | { | |
665 | LONGEST val = extract_signed_integer | |
666 | (VALUE_CONTENTS_ALL (args[i]) + offset, 4); | |
667 | regcache_cooked_write_signed | |
668 | (regcache, int_parameter_registers[intreg / 2], val); | |
669 | ||
670 | offset += 8; | |
671 | intreg++; | |
672 | } | |
673 | break; | |
53e95fcf JS |
674 | case X86_64_SSEDF_CLASS: |
675 | case X86_64_SSESF_CLASS: | |
676 | case X86_64_SSE_CLASS: | |
8ffd9b1b AJ |
677 | if (sse_stack) |
678 | stack_values[stack_values_count++] = i; | |
679 | else | |
680 | { | |
681 | regcache_cooked_write | |
682 | (regcache, sse_parameter_registers[(ssereg + 1) / 2], | |
683 | VALUE_CONTENTS_ALL (args[i]) + offset); | |
684 | offset += 8; | |
685 | ssereg += 2; | |
686 | } | |
53e95fcf JS |
687 | break; |
688 | case X86_64_SSEUP_CLASS: | |
8ffd9b1b AJ |
689 | if (sse_stack) |
690 | stack_values[stack_values_count++] = i; | |
691 | else | |
692 | { | |
693 | regcache_cooked_write | |
694 | (regcache, sse_parameter_registers[ssereg / 2], | |
695 | VALUE_CONTENTS_ALL (args[i]) + offset); | |
696 | offset += 8; | |
697 | ssereg++; | |
698 | } | |
53e95fcf JS |
699 | break; |
700 | case X86_64_X87_CLASS: | |
53e95fcf | 701 | case X86_64_MEMORY_CLASS: |
ce0eebec | 702 | stack_values[stack_values_count++] = i; |
82dbc5f7 AC |
703 | break; |
704 | case X86_64_X87UP_CLASS: | |
53e95fcf JS |
705 | break; |
706 | default: | |
707 | internal_error (__FILE__, __LINE__, | |
708 | "Unexpected argument class"); | |
709 | } | |
710 | intreg += intreg % 2; | |
711 | ssereg += ssereg % 2; | |
712 | } | |
713 | } | |
714 | } | |
c4f35dd8 | 715 | |
c1da67ba AJ |
716 | /* We have to make sure that the stack is 16-byte aligned after the |
717 | setup. Let's calculate size of arguments first, align stack and | |
718 | then fill in the arguments. */ | |
719 | total_sp = 0; | |
720 | for (i = 0; i < stack_values_count; i++) | |
721 | { | |
722 | struct value *arg = args[stack_values[i]]; | |
723 | int len = TYPE_LENGTH (VALUE_ENCLOSING_TYPE (arg)); | |
724 | total_sp += (len + 7) & ~7; | |
725 | } | |
726 | /* total_sp is now a multiple of 8, if it is not a multiple of 16, | |
727 | change the stack pointer so that it will be afterwards correctly | |
728 | aligned. */ | |
729 | if (total_sp & 15) | |
730 | sp -= 8; | |
731 | ||
c4f35dd8 | 732 | /* Push any remaining arguments onto the stack. */ |
82dbc5f7 AC |
733 | while (--stack_values_count >= 0) |
734 | { | |
e9f30c21 | 735 | struct value *arg = args[stack_values[stack_values_count]]; |
82dbc5f7 | 736 | int len = TYPE_LENGTH (VALUE_ENCLOSING_TYPE (arg)); |
c4f35dd8 | 737 | |
c1da67ba | 738 | /* Make sure the stack is 8-byte-aligned. */ |
c4f35dd8 | 739 | sp -= (len + 7) & ~7; |
82dbc5f7 AC |
740 | write_memory (sp, VALUE_CONTENTS_ALL (arg), len); |
741 | } | |
c4f35dd8 | 742 | |
8ffd9b1b AJ |
743 | /* Write number of SSE type arguments to RAX to take care of varargs |
744 | functions. */ | |
745 | store_unsigned_integer (buf, 8, total_sse_args); | |
746 | regcache_cooked_write (regcache, X86_64_RAX_REGNUM, buf); | |
747 | ||
53e95fcf JS |
748 | return sp; |
749 | } | |
750 | ||
751 | /* Write into the appropriate registers a function return value stored | |
752 | in VALBUF of type TYPE, given in virtual format. */ | |
c4f35dd8 MK |
753 | |
754 | static void | |
48037ead ML |
755 | x86_64_store_return_value (struct type *type, struct regcache *regcache, |
756 | const void *valbuf) | |
53e95fcf JS |
757 | { |
758 | int len = TYPE_LENGTH (type); | |
759 | ||
8ffd9b1b | 760 | /* First handle long doubles. */ |
54e74f72 | 761 | if (TYPE_CODE_FLT == TYPE_CODE (type) && len == 16) |
53e95fcf | 762 | { |
c4f35dd8 | 763 | ULONGEST fstat; |
f783586b | 764 | char buf[I386_MAX_REGISTER_SIZE]; |
c4f35dd8 MK |
765 | |
766 | /* Returning floating-point values is a bit tricky. Apart from | |
767 | storing the return value in %st(0), we have to simulate the | |
768 | state of the FPU at function return point. */ | |
769 | ||
770 | /* Convert the value found in VALBUF to the extended | |
771 | floating-point format used by the FPU. This is probably | |
772 | not exactly how it would happen on the target itself, but | |
773 | it is the best we can do. */ | |
774 | convert_typed_floating (valbuf, type, buf, builtin_type_i387_ext); | |
775 | regcache_raw_write (regcache, X86_64_ST0_REGNUM, buf); | |
776 | ||
777 | /* Set the top of the floating-point register stack to 7. The | |
778 | actual value doesn't really matter, but 7 is what a normal | |
779 | function return would end up with if the program started out | |
780 | with a freshly initialized FPU. */ | |
781 | regcache_raw_read_unsigned (regcache, FSTAT_REGNUM, &fstat); | |
782 | fstat |= (7 << 11); | |
783 | regcache_raw_write_unsigned (regcache, FSTAT_REGNUM, fstat); | |
784 | ||
785 | /* Mark %st(1) through %st(7) as empty. Since we set the top of | |
786 | the floating-point register stack to 7, the appropriate value | |
787 | for the tag word is 0x3fff. */ | |
788 | regcache_raw_write_unsigned (regcache, FTAG_REGNUM, 0x3fff); | |
53e95fcf | 789 | } |
8ffd9b1b AJ |
790 | else if (TYPE_CODE_FLT == TYPE_CODE (type)) |
791 | { | |
792 | /* Handle double and float variables. */ | |
249de4f6 MK |
793 | regcache_cooked_write_part (regcache, X86_64_XMM0_REGNUM, |
794 | 0, len, valbuf); | |
8ffd9b1b AJ |
795 | } |
796 | /* XXX: What about complex floating point types? */ | |
53e95fcf JS |
797 | else |
798 | { | |
ae53de43 MK |
799 | int low_size = register_size (current_gdbarch, X86_64_RAX_REGNUM); |
800 | int high_size = register_size (current_gdbarch, X86_64_RDX_REGNUM); | |
53e95fcf JS |
801 | |
802 | if (len <= low_size) | |
48037ead | 803 | regcache_cooked_write_part (regcache, 0, 0, len, valbuf); |
53e95fcf JS |
804 | else if (len <= (low_size + high_size)) |
805 | { | |
48037ead ML |
806 | regcache_cooked_write_part (regcache, 0, 0, low_size, valbuf); |
807 | regcache_cooked_write_part (regcache, 1, 0, | |
808 | len - low_size, | |
809 | (const char *) valbuf + low_size); | |
53e95fcf JS |
810 | } |
811 | else | |
812 | internal_error (__FILE__, __LINE__, | |
813 | "Cannot store return value of %d bytes long.", len); | |
814 | } | |
815 | } | |
816 | \f | |
817 | ||
c4f35dd8 | 818 | static CORE_ADDR |
10f93086 MK |
819 | x86_64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
820 | struct regcache *regcache, CORE_ADDR bp_addr, | |
821 | int nargs, struct value **args, CORE_ADDR sp, | |
822 | int struct_return, CORE_ADDR struct_addr) | |
53e95fcf | 823 | { |
c4f35dd8 MK |
824 | char buf[8]; |
825 | ||
826 | /* Pass arguments. */ | |
827 | sp = x86_64_push_arguments (regcache, nargs, args, sp); | |
828 | ||
829 | /* Pass "hidden" argument". */ | |
830 | if (struct_return) | |
831 | { | |
832 | store_unsigned_integer (buf, 8, struct_addr); | |
833 | regcache_cooked_write (regcache, X86_64_RDI_REGNUM, buf); | |
834 | } | |
835 | ||
836 | /* Store return address. */ | |
837 | sp -= 8; | |
10f93086 | 838 | store_unsigned_integer (buf, 8, bp_addr); |
c4f35dd8 MK |
839 | write_memory (sp, buf, 8); |
840 | ||
841 | /* Finally, update the stack pointer... */ | |
842 | store_unsigned_integer (buf, 8, sp); | |
843 | regcache_cooked_write (regcache, X86_64_RSP_REGNUM, buf); | |
844 | ||
845 | /* ...and fake a frame pointer. */ | |
846 | regcache_cooked_write (regcache, X86_64_RBP_REGNUM, buf); | |
847 | ||
3e210248 | 848 | return sp + 16; |
53e95fcf | 849 | } |
c4f35dd8 MK |
850 | \f |
851 | ||
852 | /* The maximum number of saved registers. This should include %rip. */ | |
2b5e0749 | 853 | #define X86_64_NUM_SAVED_REGS X86_64_NUM_GREGS |
c4f35dd8 MK |
854 | |
855 | struct x86_64_frame_cache | |
856 | { | |
857 | /* Base address. */ | |
858 | CORE_ADDR base; | |
859 | CORE_ADDR sp_offset; | |
860 | CORE_ADDR pc; | |
861 | ||
862 | /* Saved registers. */ | |
863 | CORE_ADDR saved_regs[X86_64_NUM_SAVED_REGS]; | |
864 | CORE_ADDR saved_sp; | |
865 | ||
866 | /* Do we have a frame? */ | |
867 | int frameless_p; | |
868 | }; | |
8dda9770 | 869 | |
c4f35dd8 MK |
870 | /* Allocate and initialize a frame cache. */ |
871 | ||
872 | static struct x86_64_frame_cache * | |
873 | x86_64_alloc_frame_cache (void) | |
8dda9770 | 874 | { |
c4f35dd8 MK |
875 | struct x86_64_frame_cache *cache; |
876 | int i; | |
877 | ||
878 | cache = FRAME_OBSTACK_ZALLOC (struct x86_64_frame_cache); | |
8dda9770 | 879 | |
c4f35dd8 MK |
880 | /* Base address. */ |
881 | cache->base = 0; | |
882 | cache->sp_offset = -8; | |
883 | cache->pc = 0; | |
884 | ||
885 | /* Saved registers. We initialize these to -1 since zero is a valid | |
886 | offset (that's where %rbp is supposed to be stored). */ | |
887 | for (i = 0; i < X86_64_NUM_SAVED_REGS; i++) | |
888 | cache->saved_regs[i] = -1; | |
889 | cache->saved_sp = 0; | |
890 | ||
891 | /* Frameless until proven otherwise. */ | |
892 | cache->frameless_p = 1; | |
893 | ||
894 | return cache; | |
8dda9770 | 895 | } |
53e95fcf | 896 | |
c4f35dd8 MK |
897 | /* Do a limited analysis of the prologue at PC and update CACHE |
898 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
899 | address where the analysis stopped. | |
900 | ||
901 | We will handle only functions beginning with: | |
902 | ||
903 | pushq %rbp 0x55 | |
904 | movq %rsp, %rbp 0x48 0x89 0xe5 | |
905 | ||
906 | Any function that doesn't start with this sequence will be assumed | |
907 | to have no prologue and thus no valid frame pointer in %rbp. */ | |
908 | ||
909 | static CORE_ADDR | |
910 | x86_64_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, | |
911 | struct x86_64_frame_cache *cache) | |
53e95fcf | 912 | { |
c4f35dd8 MK |
913 | static unsigned char proto[3] = { 0x48, 0x89, 0xe5 }; |
914 | unsigned char buf[3]; | |
915 | unsigned char op; | |
916 | ||
917 | if (current_pc <= pc) | |
918 | return current_pc; | |
919 | ||
920 | op = read_memory_unsigned_integer (pc, 1); | |
921 | ||
922 | if (op == 0x55) /* pushq %rbp */ | |
923 | { | |
924 | /* Take into account that we've executed the `pushq %rbp' that | |
925 | starts this instruction sequence. */ | |
926 | cache->saved_regs[X86_64_RBP_REGNUM] = 0; | |
927 | cache->sp_offset += 8; | |
928 | ||
929 | /* If that's all, return now. */ | |
930 | if (current_pc <= pc + 1) | |
931 | return current_pc; | |
932 | ||
933 | /* Check for `movq %rsp, %rbp'. */ | |
934 | read_memory (pc + 1, buf, 3); | |
935 | if (memcmp (buf, proto, 3) != 0) | |
936 | return pc + 1; | |
937 | ||
938 | /* OK, we actually have a frame. */ | |
939 | cache->frameless_p = 0; | |
940 | return pc + 4; | |
941 | } | |
942 | ||
943 | return pc; | |
53e95fcf JS |
944 | } |
945 | ||
c4f35dd8 MK |
946 | /* Return PC of first real instruction. */ |
947 | ||
948 | static CORE_ADDR | |
949 | x86_64_skip_prologue (CORE_ADDR start_pc) | |
53e95fcf | 950 | { |
c4f35dd8 MK |
951 | struct x86_64_frame_cache cache; |
952 | CORE_ADDR pc; | |
953 | ||
954 | pc = x86_64_analyze_prologue (start_pc, 0xffffffffffffffff, &cache); | |
955 | if (cache.frameless_p) | |
956 | return start_pc; | |
957 | ||
958 | return pc; | |
53e95fcf | 959 | } |
c4f35dd8 | 960 | \f |
53e95fcf | 961 | |
c4f35dd8 MK |
962 | /* Normal frames. */ |
963 | ||
964 | static struct x86_64_frame_cache * | |
965 | x86_64_frame_cache (struct frame_info *next_frame, void **this_cache) | |
6d686a84 | 966 | { |
c4f35dd8 MK |
967 | struct x86_64_frame_cache *cache; |
968 | char buf[8]; | |
6d686a84 | 969 | int i; |
6d686a84 | 970 | |
c4f35dd8 MK |
971 | if (*this_cache) |
972 | return *this_cache; | |
6d686a84 | 973 | |
c4f35dd8 MK |
974 | cache = x86_64_alloc_frame_cache (); |
975 | *this_cache = cache; | |
976 | ||
977 | frame_unwind_register (next_frame, X86_64_RBP_REGNUM, buf); | |
978 | cache->base = extract_unsigned_integer (buf, 8); | |
979 | if (cache->base == 0) | |
980 | return cache; | |
981 | ||
982 | /* For normal frames, %rip is stored at 8(%rbp). */ | |
983 | cache->saved_regs[X86_64_RIP_REGNUM] = 8; | |
984 | ||
985 | cache->pc = frame_func_unwind (next_frame); | |
986 | if (cache->pc != 0) | |
987 | x86_64_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache); | |
988 | ||
989 | if (cache->frameless_p) | |
990 | { | |
991 | /* We didn't find a valid frame, which means that CACHE->base | |
992 | currently holds the frame pointer for our calling frame. If | |
993 | we're at the start of a function, or somewhere half-way its | |
994 | prologue, the function's frame probably hasn't been fully | |
995 | setup yet. Try to reconstruct the base address for the stack | |
996 | frame by looking at the stack pointer. For truly "frameless" | |
997 | functions this might work too. */ | |
998 | ||
999 | frame_unwind_register (next_frame, X86_64_RSP_REGNUM, buf); | |
1000 | cache->base = extract_unsigned_integer (buf, 8) + cache->sp_offset; | |
1001 | } | |
1002 | ||
1003 | /* Now that we have the base address for the stack frame we can | |
1004 | calculate the value of %rsp in the calling frame. */ | |
1005 | cache->saved_sp = cache->base + 16; | |
1006 | ||
1007 | /* Adjust all the saved registers such that they contain addresses | |
1008 | instead of offsets. */ | |
1009 | for (i = 0; i < X86_64_NUM_SAVED_REGS; i++) | |
1010 | if (cache->saved_regs[i] != -1) | |
1011 | cache->saved_regs[i] += cache->base; | |
1012 | ||
1013 | return cache; | |
6d686a84 ML |
1014 | } |
1015 | ||
c4f35dd8 MK |
1016 | static void |
1017 | x86_64_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
1018 | struct frame_id *this_id) | |
1019 | { | |
1020 | struct x86_64_frame_cache *cache = | |
1021 | x86_64_frame_cache (next_frame, this_cache); | |
1022 | ||
1023 | /* This marks the outermost frame. */ | |
1024 | if (cache->base == 0) | |
1025 | return; | |
1026 | ||
1027 | (*this_id) = frame_id_build (cache->base + 16, cache->pc); | |
1028 | } | |
e76e1718 | 1029 | |
c4f35dd8 MK |
1030 | static void |
1031 | x86_64_frame_prev_register (struct frame_info *next_frame, void **this_cache, | |
1032 | int regnum, int *optimizedp, | |
1033 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1034 | int *realnump, void *valuep) | |
53e95fcf | 1035 | { |
c4f35dd8 MK |
1036 | struct x86_64_frame_cache *cache = |
1037 | x86_64_frame_cache (next_frame, this_cache); | |
e76e1718 | 1038 | |
c4f35dd8 | 1039 | gdb_assert (regnum >= 0); |
b1ab997b | 1040 | |
c4f35dd8 MK |
1041 | if (regnum == SP_REGNUM && cache->saved_sp) |
1042 | { | |
1043 | *optimizedp = 0; | |
1044 | *lvalp = not_lval; | |
1045 | *addrp = 0; | |
1046 | *realnump = -1; | |
1047 | if (valuep) | |
1048 | { | |
1049 | /* Store the value. */ | |
1050 | store_unsigned_integer (valuep, 8, cache->saved_sp); | |
1051 | } | |
1052 | return; | |
1053 | } | |
e76e1718 | 1054 | |
c4f35dd8 MK |
1055 | if (regnum < X86_64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
1056 | { | |
1057 | *optimizedp = 0; | |
1058 | *lvalp = lval_memory; | |
1059 | *addrp = cache->saved_regs[regnum]; | |
1060 | *realnump = -1; | |
1061 | if (valuep) | |
1062 | { | |
1063 | /* Read the value in from memory. */ | |
1064 | read_memory (*addrp, valuep, | |
1065 | register_size (current_gdbarch, regnum)); | |
1066 | } | |
1067 | return; | |
1068 | } | |
e76e1718 | 1069 | |
c4f35dd8 MK |
1070 | frame_register_unwind (next_frame, regnum, |
1071 | optimizedp, lvalp, addrp, realnump, valuep); | |
1072 | } | |
e76e1718 | 1073 | |
c4f35dd8 MK |
1074 | static const struct frame_unwind x86_64_frame_unwind = |
1075 | { | |
1076 | NORMAL_FRAME, | |
1077 | x86_64_frame_this_id, | |
1078 | x86_64_frame_prev_register | |
1079 | }; | |
e76e1718 | 1080 | |
c4f35dd8 | 1081 | static const struct frame_unwind * |
336d1bba | 1082 | x86_64_frame_sniffer (struct frame_info *next_frame) |
c4f35dd8 MK |
1083 | { |
1084 | return &x86_64_frame_unwind; | |
1085 | } | |
1086 | \f | |
e76e1718 | 1087 | |
c4f35dd8 MK |
1088 | /* Signal trampolines. */ |
1089 | ||
1090 | /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and | |
1091 | 64-bit variants. This would require using identical frame caches | |
1092 | on both platforms. */ | |
1093 | ||
1094 | static struct x86_64_frame_cache * | |
1095 | x86_64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache) | |
1096 | { | |
1097 | struct x86_64_frame_cache *cache; | |
1098 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1099 | CORE_ADDR addr; | |
1100 | char buf[8]; | |
2b5e0749 | 1101 | int i; |
c4f35dd8 MK |
1102 | |
1103 | if (*this_cache) | |
1104 | return *this_cache; | |
1105 | ||
1106 | cache = x86_64_alloc_frame_cache (); | |
1107 | ||
1108 | frame_unwind_register (next_frame, X86_64_RSP_REGNUM, buf); | |
1109 | cache->base = extract_unsigned_integer (buf, 8) - 8; | |
1110 | ||
1111 | addr = tdep->sigcontext_addr (next_frame); | |
2b5e0749 MK |
1112 | gdb_assert (tdep->sc_reg_offset); |
1113 | gdb_assert (tdep->sc_num_regs <= X86_64_NUM_SAVED_REGS); | |
1114 | for (i = 0; i < tdep->sc_num_regs; i++) | |
1115 | if (tdep->sc_reg_offset[i] != -1) | |
1116 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; | |
c4f35dd8 MK |
1117 | |
1118 | *this_cache = cache; | |
1119 | return cache; | |
53e95fcf JS |
1120 | } |
1121 | ||
c4f35dd8 MK |
1122 | static void |
1123 | x86_64_sigtramp_frame_this_id (struct frame_info *next_frame, | |
1124 | void **this_cache, struct frame_id *this_id) | |
1125 | { | |
1126 | struct x86_64_frame_cache *cache = | |
1127 | x86_64_sigtramp_frame_cache (next_frame, this_cache); | |
1128 | ||
1129 | (*this_id) = frame_id_build (cache->base + 16, frame_pc_unwind (next_frame)); | |
1130 | } | |
1131 | ||
1132 | static void | |
1133 | x86_64_sigtramp_frame_prev_register (struct frame_info *next_frame, | |
1134 | void **this_cache, | |
1135 | int regnum, int *optimizedp, | |
1136 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1137 | int *realnump, void *valuep) | |
1138 | { | |
1139 | /* Make sure we've initialized the cache. */ | |
1140 | x86_64_sigtramp_frame_cache (next_frame, this_cache); | |
1141 | ||
1142 | x86_64_frame_prev_register (next_frame, this_cache, regnum, | |
1143 | optimizedp, lvalp, addrp, realnump, valuep); | |
1144 | } | |
1145 | ||
1146 | static const struct frame_unwind x86_64_sigtramp_frame_unwind = | |
1147 | { | |
1148 | SIGTRAMP_FRAME, | |
1149 | x86_64_sigtramp_frame_this_id, | |
1150 | x86_64_sigtramp_frame_prev_register | |
1151 | }; | |
1152 | ||
1153 | static const struct frame_unwind * | |
336d1bba | 1154 | x86_64_sigtramp_frame_sniffer (struct frame_info *next_frame) |
c4f35dd8 | 1155 | { |
336d1bba | 1156 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
c4f35dd8 MK |
1157 | char *name; |
1158 | ||
1159 | find_pc_partial_function (pc, &name, NULL, NULL); | |
1160 | if (PC_IN_SIGTRAMP (pc, name)) | |
1c3545ae MK |
1161 | { |
1162 | gdb_assert (gdbarch_tdep (current_gdbarch)->sigcontext_addr); | |
1163 | ||
1164 | return &x86_64_sigtramp_frame_unwind; | |
1165 | } | |
c4f35dd8 MK |
1166 | |
1167 | return NULL; | |
1168 | } | |
1169 | \f | |
1170 | ||
1171 | static CORE_ADDR | |
1172 | x86_64_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
1173 | { | |
1174 | struct x86_64_frame_cache *cache = | |
1175 | x86_64_frame_cache (next_frame, this_cache); | |
1176 | ||
1177 | return cache->base; | |
1178 | } | |
1179 | ||
1180 | static const struct frame_base x86_64_frame_base = | |
1181 | { | |
1182 | &x86_64_frame_unwind, | |
1183 | x86_64_frame_base_address, | |
1184 | x86_64_frame_base_address, | |
1185 | x86_64_frame_base_address | |
1186 | }; | |
1187 | ||
166f4c7b | 1188 | static struct frame_id |
c4f35dd8 | 1189 | x86_64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) |
166f4c7b | 1190 | { |
c4f35dd8 MK |
1191 | char buf[8]; |
1192 | CORE_ADDR fp; | |
1193 | ||
1194 | frame_unwind_register (next_frame, X86_64_RBP_REGNUM, buf); | |
1195 | fp = extract_unsigned_integer (buf, 8); | |
1196 | ||
1197 | return frame_id_build (fp + 16, frame_pc_unwind (next_frame)); | |
166f4c7b ML |
1198 | } |
1199 | ||
8b148df9 AC |
1200 | /* 16 byte align the SP per frame requirements. */ |
1201 | ||
1202 | static CORE_ADDR | |
1203 | x86_64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
1204 | { | |
1205 | return sp & -(CORE_ADDR)16; | |
1206 | } | |
473f17b0 MK |
1207 | \f |
1208 | ||
1209 | /* Supply register REGNUM from the floating-point register set REGSET | |
1210 | to register cache REGCACHE. If REGNUM is -1, do this for all | |
1211 | registers in REGSET. */ | |
1212 | ||
1213 | static void | |
1214 | x86_64_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
1215 | int regnum, const void *fpregs, size_t len) | |
1216 | { | |
1217 | const struct gdbarch_tdep *tdep = regset->descr; | |
1218 | ||
1219 | gdb_assert (len == tdep->sizeof_fpregset); | |
1220 | x86_64_supply_fxsave (regcache, regnum, fpregs); | |
1221 | } | |
8b148df9 | 1222 | |
c6b33596 MK |
1223 | /* Return the appropriate register set for the core section identified |
1224 | by SECT_NAME and SECT_SIZE. */ | |
1225 | ||
1226 | static const struct regset * | |
1227 | x86_64_regset_from_core_section (struct gdbarch *gdbarch, | |
1228 | const char *sect_name, size_t sect_size) | |
1229 | { | |
1230 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1231 | ||
1232 | if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) | |
1233 | { | |
1234 | if (tdep->fpregset == NULL) | |
1235 | { | |
1236 | tdep->fpregset = XMALLOC (struct regset); | |
1237 | tdep->fpregset->descr = tdep; | |
1238 | tdep->fpregset->supply_regset = x86_64_supply_fpregset; | |
1239 | } | |
1240 | ||
1241 | return tdep->fpregset; | |
1242 | } | |
1243 | ||
1244 | return i386_regset_from_core_section (gdbarch, sect_name, sect_size); | |
1245 | } | |
1246 | \f | |
1247 | ||
2213a65d | 1248 | void |
0c1a73d6 | 1249 | x86_64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
53e95fcf | 1250 | { |
0c1a73d6 | 1251 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
53e95fcf | 1252 | |
473f17b0 MK |
1253 | /* AMD64 generally uses `fxsave' instead of `fsave' for saving its |
1254 | floating-point registers. */ | |
1255 | tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE; | |
1256 | ||
5716833c MK |
1257 | /* AMD64 has an FPU and 16 SSE registers. */ |
1258 | tdep->st0_regnum = X86_64_ST0_REGNUM; | |
0c1a73d6 | 1259 | tdep->num_xmm_regs = 16; |
53e95fcf | 1260 | |
0c1a73d6 | 1261 | /* This is what all the fuss is about. */ |
53e95fcf JS |
1262 | set_gdbarch_long_bit (gdbarch, 64); |
1263 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1264 | set_gdbarch_ptr_bit (gdbarch, 64); | |
1265 | ||
b83b026c MK |
1266 | /* In contrast to the i386, on the x86-64 a `long double' actually |
1267 | takes up 128 bits, even though it's still based on the i387 | |
1268 | extended floating-point format which has only 80 significant bits. */ | |
1269 | set_gdbarch_long_double_bit (gdbarch, 128); | |
1270 | ||
53e95fcf | 1271 | set_gdbarch_num_regs (gdbarch, X86_64_NUM_REGS); |
c4f35dd8 MK |
1272 | set_gdbarch_register_name (gdbarch, x86_64_register_name); |
1273 | set_gdbarch_register_type (gdbarch, x86_64_register_type); | |
b83b026c MK |
1274 | |
1275 | /* Register numbers of various important registers. */ | |
c4f35dd8 MK |
1276 | set_gdbarch_sp_regnum (gdbarch, X86_64_RSP_REGNUM); /* %rsp */ |
1277 | set_gdbarch_pc_regnum (gdbarch, X86_64_RIP_REGNUM); /* %rip */ | |
1278 | set_gdbarch_ps_regnum (gdbarch, X86_64_EFLAGS_REGNUM); /* %eflags */ | |
1279 | set_gdbarch_fp0_regnum (gdbarch, X86_64_ST0_REGNUM); /* %st(0) */ | |
b83b026c MK |
1280 | |
1281 | /* The "default" register numbering scheme for the x86-64 is | |
c4f35dd8 MK |
1282 | referred to as the "DWARF Register Number Mapping" in the System |
1283 | V psABI. The preferred debugging format for all known x86-64 | |
1284 | targets is actually DWARF2, and GCC doesn't seem to support DWARF | |
1285 | (that is DWARF-1), but we provide the same mapping just in case. | |
1286 | This mapping is also used for stabs, which GCC does support. */ | |
1287 | set_gdbarch_stab_reg_to_regnum (gdbarch, x86_64_dwarf_reg_to_regnum); | |
1288 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, x86_64_dwarf_reg_to_regnum); | |
1289 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, x86_64_dwarf_reg_to_regnum); | |
de220d0f | 1290 | |
c4f35dd8 MK |
1291 | /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to |
1292 | be in use on any of the supported x86-64 targets. */ | |
53e95fcf | 1293 | |
c4f35dd8 MK |
1294 | /* Call dummy code. */ |
1295 | set_gdbarch_push_dummy_call (gdbarch, x86_64_push_dummy_call); | |
8b148df9 AC |
1296 | set_gdbarch_frame_align (gdbarch, x86_64_frame_align); |
1297 | set_gdbarch_frame_red_zone_size (gdbarch, 128); | |
53e95fcf | 1298 | |
d532c08f MK |
1299 | set_gdbarch_convert_register_p (gdbarch, x86_64_convert_register_p); |
1300 | set_gdbarch_register_to_value (gdbarch, i387_register_to_value); | |
1301 | set_gdbarch_value_to_register (gdbarch, i387_value_to_register); | |
1302 | ||
48037ead | 1303 | set_gdbarch_extract_return_value (gdbarch, x86_64_extract_return_value); |
48037ead | 1304 | set_gdbarch_store_return_value (gdbarch, x86_64_store_return_value); |
b83b026c MK |
1305 | /* Override, since this is handled by x86_64_extract_return_value. */ |
1306 | set_gdbarch_extract_struct_value_address (gdbarch, NULL); | |
1307 | set_gdbarch_use_struct_convention (gdbarch, x86_64_use_struct_convention); | |
53e95fcf | 1308 | |
b83b026c | 1309 | set_gdbarch_skip_prologue (gdbarch, x86_64_skip_prologue); |
53e95fcf | 1310 | |
c4f35dd8 | 1311 | /* Avoid wiring in the MMX registers for now. */ |
2213a65d | 1312 | set_gdbarch_num_pseudo_regs (gdbarch, 0); |
5716833c | 1313 | tdep->mm0_regnum = -1; |
2213a65d | 1314 | |
c4f35dd8 | 1315 | set_gdbarch_unwind_dummy_id (gdbarch, x86_64_unwind_dummy_id); |
53e95fcf | 1316 | |
b83b026c MK |
1317 | /* FIXME: kettenis/20021026: This is ELF-specific. Fine for now, |
1318 | since all supported x86-64 targets are ELF, but that might change | |
1319 | in the future. */ | |
8a8ab2b9 | 1320 | set_gdbarch_in_solib_call_trampoline (gdbarch, in_plt_section); |
c4f35dd8 | 1321 | |
336d1bba AC |
1322 | frame_unwind_append_sniffer (gdbarch, x86_64_sigtramp_frame_sniffer); |
1323 | frame_unwind_append_sniffer (gdbarch, x86_64_frame_sniffer); | |
c4f35dd8 | 1324 | frame_base_set_default (gdbarch, &x86_64_frame_base); |
c6b33596 MK |
1325 | |
1326 | /* If we have a register mapping, enable the generic core file support. */ | |
1327 | if (tdep->gregset_reg_offset) | |
1328 | set_gdbarch_regset_from_core_section (gdbarch, | |
1329 | x86_64_regset_from_core_section); | |
c4f35dd8 MK |
1330 | } |
1331 | \f | |
1332 | ||
5716833c | 1333 | #define I387_ST0_REGNUM X86_64_ST0_REGNUM |
c4f35dd8 | 1334 | |
41d041d6 MK |
1335 | /* The 64-bit FXSAVE format differs from the 32-bit format in the |
1336 | sense that the instruction pointer and data pointer are simply | |
1337 | 64-bit offsets into the code segment and the data segment instead | |
1338 | of a selector offset pair. The functions below store the upper 32 | |
1339 | bits of these pointers (instead of just the 16-bits of the segment | |
1340 | selector). */ | |
1341 | ||
1342 | /* Fill register REGNUM in REGCACHE with the appropriate | |
0485f6ad MK |
1343 | floating-point or SSE register value from *FXSAVE. If REGNUM is |
1344 | -1, do this for all registers. This function masks off any of the | |
1345 | reserved bits in *FXSAVE. */ | |
c4f35dd8 MK |
1346 | |
1347 | void | |
41d041d6 MK |
1348 | x86_64_supply_fxsave (struct regcache *regcache, int regnum, |
1349 | const void *fxsave) | |
c4f35dd8 | 1350 | { |
41d041d6 | 1351 | i387_supply_fxsave (regcache, regnum, fxsave); |
c4f35dd8 MK |
1352 | |
1353 | if (fxsave) | |
1354 | { | |
41d041d6 MK |
1355 | const char *regs = fxsave; |
1356 | ||
0485f6ad | 1357 | if (regnum == -1 || regnum == I387_FISEG_REGNUM) |
41d041d6 | 1358 | regcache_raw_supply (regcache, I387_FISEG_REGNUM, regs + 12); |
0485f6ad | 1359 | if (regnum == -1 || regnum == I387_FOSEG_REGNUM) |
41d041d6 | 1360 | regcache_raw_supply (regcache, I387_FOSEG_REGNUM, regs + 20); |
c4f35dd8 | 1361 | } |
0c1a73d6 MK |
1362 | } |
1363 | ||
c4f35dd8 | 1364 | /* Fill register REGNUM (if it is a floating-point or SSE register) in |
0485f6ad | 1365 | *FXSAVE with the value in GDB's register cache. If REGNUM is -1, do |
c4f35dd8 MK |
1366 | this for all registers. This function doesn't touch any of the |
1367 | reserved bits in *FXSAVE. */ | |
1368 | ||
53e95fcf | 1369 | void |
c4f35dd8 | 1370 | x86_64_fill_fxsave (char *fxsave, int regnum) |
53e95fcf | 1371 | { |
c4f35dd8 | 1372 | i387_fill_fxsave (fxsave, regnum); |
53e95fcf | 1373 | |
c4f35dd8 | 1374 | if (regnum == -1 || regnum == I387_FISEG_REGNUM) |
088ce440 | 1375 | regcache_collect (I387_FISEG_REGNUM, fxsave + 12); |
c4f35dd8 | 1376 | if (regnum == -1 || regnum == I387_FOSEG_REGNUM) |
088ce440 | 1377 | regcache_collect (I387_FOSEG_REGNUM, fxsave + 20); |
53e95fcf | 1378 | } |