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* config/obj-elf.c (elf_frob_symbol): Report S_SET_SIZE symbol
[deliverable/binutils-gdb.git] / gdb / xtensa-tdep.c
CommitLineData
ca3bf3bd
DJ		 1/* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
2
7b6bb8da 3 Copyright (C) 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2011
0fb0cc75 4 Free Software Foundation, Inc.
ca3bf3bd
DJ		 5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
a9762ec7 10 the Free Software Foundation; either version 3 of the License, or
ca3bf3bd
DJ		 11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
a9762ec7 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
ca3bf3bd
DJ		 20
21#include "defs.h"
22#include "frame.h"
ee967b5f 23#include "solib-svr4.h"
ca3bf3bd
DJ		 24#include "symtab.h"
25#include "symfile.h"
26#include "objfiles.h"
27#include "gdbtypes.h"
28#include "gdbcore.h"
29#include "value.h"
30#include "dis-asm.h"
31#include "inferior.h"
32#include "floatformat.h"
33#include "regcache.h"
34#include "reggroups.h"
35#include "regset.h"
36
37#include "dummy-frame.h"
fa8f86ff 38#include "dwarf2.h"
ca3bf3bd
DJ		 39#include "dwarf2-frame.h"
40#include "dwarf2loc.h"
41#include "frame.h"
42#include "frame-base.h"
43#include "frame-unwind.h"
44
45#include "arch-utils.h"
46#include "gdbarch.h"
47#include "remote.h"
48#include "serial.h"
49
50#include "command.h"
51#include "gdbcmd.h"
52#include "gdb_assert.h"
53
bdb4c075 54#include "xtensa-isa.h"
ca3bf3bd 55#include "xtensa-tdep.h"
94a0e877 56#include "xtensa-config.h"
ca3bf3bd
DJ		 57
58
59static int xtensa_debug_level = 0;
60
61#define DEBUGWARN(args...) \
62 if (xtensa_debug_level > 0) \
63 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
64
65#define DEBUGINFO(args...) \
66 if (xtensa_debug_level > 1) \
67 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
68
69#define DEBUGTRACE(args...) \
70 if (xtensa_debug_level > 2) \
71 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
72
73#define DEBUGVERB(args...) \
74 if (xtensa_debug_level > 3) \
75 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
76
77
78/* According to the ABI, the SP must be aligned to 16-byte boundaries. */
ca3bf3bd
DJ		 79#define SP_ALIGNMENT 16
80
81
bdb4c075
MG		 82/* On Windowed ABI, we use a6 through a11 for passing arguments
83 to a function called by GDB because CALL4 is used. */
bdb4c075
MG		 84#define ARGS_NUM_REGS 6
85#define REGISTER_SIZE 4
ca3bf3bd 86
ca3bf3bd 87
bdb4c075
MG		 88/* Extract the call size from the return address or PS register. */
89#define PS_CALLINC_SHIFT 16
90#define PS_CALLINC_MASK 0x00030000
91#define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
92#define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
ca3bf3bd 93
98689b25
MG		 94/* On TX, hardware can be configured without Exception Option.
95 There is no PS register in this case. Inside XT-GDB, let us treat
96 it as a virtual read-only register always holding the same value. */
97#define TX_PS 0x20
98
bdb4c075 99/* ABI-independent macros. */
91d8eb23
MD		 100#define ARG_NOF(gdbarch) \
101 (gdbarch_tdep (gdbarch)->call_abi \
102 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
103#define ARG_1ST(gdbarch) \
104 (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \
94a0e877 105 ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \
91d8eb23 106 : (gdbarch_tdep (gdbarch)->a0_base + 6))
ca3bf3bd 107
ca3bf3bd
DJ		 108/* XTENSA_IS_ENTRY tests whether the first byte of an instruction
109 indicates that the instruction is an ENTRY instruction. */
110
91d8eb23
MD		 111#define XTENSA_IS_ENTRY(gdbarch, op1) \
112 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
4c6b5505 113 ? ((op1) == 0x6c) : ((op1) == 0x36))
ca3bf3bd 114
bdb4c075 115#define XTENSA_ENTRY_LENGTH 3
ca3bf3bd
DJ		 116
117/* windowing_enabled() returns true, if windowing is enabled.
118 WOE must be set to 1; EXCM to 0.
119 Note: We assume that EXCM is always 0 for XEA1. */
120
bdb4c075
MG		 121#define PS_WOE (1<<18)
122#define PS_EXC (1<<4)
123
b801de47 124static int
98689b25
MG		 125windowing_enabled (struct gdbarch *gdbarch, unsigned int ps)
126{
127 /* If we know CALL0 ABI is set explicitly, say it is Call0. */
128 if (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only)
129 return 0;
130
131 return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0);
132}
133
581e13c1
MS		 134/* Convert a live A-register number to the corresponding AR-register
135 number. */
91d8eb23 136static int
ee967b5f 137arreg_number (struct gdbarch *gdbarch, int a_regnum, ULONGEST wb)
91d8eb23
MD		 138{
139 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
ee967b5f 140 int arreg;
91d8eb23 141
ee967b5f
MG		 142 arreg = a_regnum - tdep->a0_base;
143 arreg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT;
144 arreg &= tdep->num_aregs - 1;
91d8eb23 145
ee967b5f
MG		 146 return arreg + tdep->ar_base;
147}
148
149/* Convert a live AR-register number to the corresponding A-register order
150 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
151static int
152areg_number (struct gdbarch *gdbarch, int ar_regnum, unsigned int wb)
153{
154 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
155 int areg;
156
157 areg = ar_regnum - tdep->ar_base;
158 if (areg < 0 || areg >= tdep->num_aregs)
159 return -1;
160 areg = (areg - wb * 4) & (tdep->num_aregs - 1);
161 return (areg > 15) ? -1 : areg;
91d8eb23
MD		 162}
163
68d6df83 164/* Read Xtensa register directly from the hardware. */
b801de47 165static unsigned long
08b9c608
MG		 166xtensa_read_register (int regnum)
167{
168 ULONGEST value;
169
170 regcache_raw_read_unsigned (get_current_regcache (), regnum, &value);
171 return (unsigned long) value;
172}
173
68d6df83 174/* Write Xtensa register directly to the hardware. */
b801de47 175static void
08b9c608
MG		 176xtensa_write_register (int regnum, ULONGEST value)
177{
178 regcache_raw_write_unsigned (get_current_regcache (), regnum, value);
179}
180
ca3bf3bd
DJ		 181/* Return the window size of the previous call to the function from which we
182 have just returned.
183
184 This function is used to extract the return value after a called function
bdb4c075 185 has returned to the caller. On Xtensa, the register that holds the return
ca3bf3bd
DJ		 186 value (from the perspective of the caller) depends on what call
187 instruction was used. For now, we are assuming that the call instruction
188 precedes the current address, so we simply analyze the call instruction.
189 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
190 method to call the inferior function. */
191
192static int
91d8eb23 193extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc)
ca3bf3bd 194{
e17a4113 195 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
bdb4c075 196 int winsize = 4;
ca3bf3bd 197 int insn;
ff7a4c00 198 gdb_byte buf[4];
ca3bf3bd
DJ		 199
200 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc);
201
202 /* Read the previous instruction (should be a call[x]{4|8|12}. */
203 read_memory (pc-3, buf, 3);
e17a4113 204 insn = extract_unsigned_integer (buf, 3, byte_order);
ca3bf3bd
DJ		 205
206 /* Decode call instruction:
207 Little Endian
208 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
209 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
210 Big Endian
211 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
212 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
213
e17a4113 214 if (byte_order == BFD_ENDIAN_LITTLE)
ca3bf3bd
DJ		 215 {
216 if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0))
bdb4c075 217 winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */
ca3bf3bd
DJ		 218 }
219 else
220 {
221 if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03))
bdb4c075 222 winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */
ca3bf3bd
DJ		 223 }
224 return winsize;
225}
226
227
228/* REGISTER INFORMATION */
229
08b9c608
MG		 230/* Find register by name. */
231static int
232xtensa_find_register_by_name (struct gdbarch *gdbarch, char *name)
233{
234 int i;
235
236 for (i = 0; i < gdbarch_num_regs (gdbarch)
237 + gdbarch_num_pseudo_regs (gdbarch);
238 i++)
239
240 if (strcasecmp (gdbarch_tdep (gdbarch)->regmap[i].name, name) == 0)
241 return i;
242
243 return -1;
244}
245
ca3bf3bd 246/* Returns the name of a register. */
ca3bf3bd 247static const char *
d93859e2 248xtensa_register_name (struct gdbarch *gdbarch, int regnum)
ca3bf3bd
DJ		 249{
250 /* Return the name stored in the register map. */
d93859e2
UW		 251 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
252 + gdbarch_num_pseudo_regs (gdbarch))
253 return gdbarch_tdep (gdbarch)->regmap[regnum].name;
ca3bf3bd 254
ca3bf3bd
DJ		 255 internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum);
256 return 0;
257}
258
ca3bf3bd
DJ		 259/* Return the type of a register. Create a new type, if necessary. */
260
ca3bf3bd
DJ		 261static struct type *
262xtensa_register_type (struct gdbarch *gdbarch, int regnum)
263{
df4df182
UW		 264 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
265
ca3bf3bd 266 /* Return signed integer for ARx and Ax registers. */
df4df182
UW		 267 if ((regnum >= tdep->ar_base
268 && regnum < tdep->ar_base + tdep->num_aregs)
269 || (regnum >= tdep->a0_base
270 && regnum < tdep->a0_base + 16))
0dfff4cb 271 return builtin_type (gdbarch)->builtin_int;
ca3bf3bd 272
6b50c0b0 273 if (regnum == gdbarch_pc_regnum (gdbarch)
df4df182 274 || regnum == tdep->a0_base + 1)
fde6c819 275 return builtin_type (gdbarch)->builtin_data_ptr;
ca3bf3bd
DJ		 276
277 /* Return the stored type for all other registers. */
6b50c0b0
UW		 278 else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
279 + gdbarch_num_pseudo_regs (gdbarch))
ca3bf3bd 280 {
df4df182 281 xtensa_register_t* reg = &tdep->regmap[regnum];
ca3bf3bd 282
bdb4c075 283 /* Set ctype for this register (only the first time). */
ca3bf3bd
DJ		 284
285 if (reg->ctype == 0)
286 {
287 struct ctype_cache *tp;
288 int size = reg->byte_size;
289
bdb4c075
MG		 290 /* We always use the memory representation,
291 even if the register width is smaller. */
ca3bf3bd
DJ		 292 switch (size)
293 {
294 case 1:
df4df182 295 reg->ctype = builtin_type (gdbarch)->builtin_uint8;
ca3bf3bd
DJ		 296 break;
297
298 case 2:
df4df182 299 reg->ctype = builtin_type (gdbarch)->builtin_uint16;
ca3bf3bd
DJ		 300 break;
301
302 case 4:
df4df182 303 reg->ctype = builtin_type (gdbarch)->builtin_uint32;
ca3bf3bd
DJ		 304 break;
305
306 case 8:
df4df182 307 reg->ctype = builtin_type (gdbarch)->builtin_uint64;
ca3bf3bd
DJ		 308 break;
309
310 case 16:
df4df182 311 reg->ctype = builtin_type (gdbarch)->builtin_uint128;
ca3bf3bd
DJ		 312 break;
313
314 default:
df4df182 315 for (tp = tdep->type_entries; tp != NULL; tp = tp->next)
ca3bf3bd
DJ		 316 if (tp->size == size)
317 break;
318
319 if (tp == NULL)
320 {
321 char *name = xmalloc (16);
322 tp = xmalloc (sizeof (struct ctype_cache));
df4df182
UW		 323 tp->next = tdep->type_entries;
324 tdep->type_entries = tp;
ca3bf3bd
DJ		 325 tp->size = size;
326
327 sprintf (name, "int%d", size * 8);
e9bb382b
UW		 328 tp->virtual_type
329 = arch_integer_type (gdbarch, size * 8, 1, xstrdup (name));
ca3bf3bd
DJ		 330 }
331
332 reg->ctype = tp->virtual_type;
333 }
334 }
335 return reg->ctype;
336 }
337
ca3bf3bd
DJ		 338 internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum);
339 return 0;
340}
341
342
bdb4c075 343/* Return the 'local' register number for stubs, dwarf2, etc.
ca3bf3bd
DJ		 344 The debugging information enumerates registers starting from 0 for A0
345 to n for An. So, we only have to add the base number for A0. */
346
347static int
d3f73121 348xtensa_reg_to_regnum (struct gdbarch *gdbarch, int regnum)
ca3bf3bd
DJ		 349{
350 int i;
351
352 if (regnum >= 0 && regnum < 16)
d3f73121 353 return gdbarch_tdep (gdbarch)->a0_base + regnum;
ca3bf3bd 354
f57d151a 355 for (i = 0;
d3f73121 356 i < gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
f57d151a 357 i++)
d3f73121 358 if (regnum == gdbarch_tdep (gdbarch)->regmap[i].target_number)
ca3bf3bd
DJ		 359 return i;
360
ca3bf3bd
DJ		 361 internal_error (__FILE__, __LINE__,
362 _("invalid dwarf/stabs register number %d"), regnum);
363 return 0;
364}
365
366
bdb4c075
MG		 367/* Write the bits of a masked register to the various registers.
368 Only the masked areas of these registers are modified; the other
369 fields are untouched. The size of masked registers is always less
370 than or equal to 32 bits. */
ca3bf3bd
DJ		 371
372static void
9c9acae0
UW		 373xtensa_register_write_masked (struct regcache *regcache,
374 xtensa_register_t *reg, const gdb_byte *buffer)
ca3bf3bd
DJ		 375{
376 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
ca3bf3bd
DJ		 377 const xtensa_mask_t *mask = reg->mask;
378
379 int shift = 0; /* Shift for next mask (mod 32). */
380 int start, size; /* Start bit and size of current mask. */
381
382 unsigned int *ptr = value;
383 unsigned int regval, m, mem = 0;
384
385 int bytesize = reg->byte_size;
386 int bitsize = bytesize * 8;
387 int i, r;
388
389 DEBUGTRACE ("xtensa_register_write_masked ()\n");
390
391 /* Copy the masked register to host byte-order. */
6b50c0b0 392 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
ca3bf3bd
DJ		 393 for (i = 0; i < bytesize; i++)
394 {
395 mem >>= 8;
396 mem |= (buffer[bytesize - i - 1] << 24);
397 if ((i & 3) == 3)
398 *ptr++ = mem;
399 }
400 else
401 for (i = 0; i < bytesize; i++)
402 {
403 mem >>= 8;
404 mem |= (buffer[i] << 24);
405 if ((i & 3) == 3)
406 *ptr++ = mem;
407 }
408
409 /* We might have to shift the final value:
410 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
411 bytesize & 3 == x -> shift (4-x) * 8. */
412
413 *ptr = mem >> (((0 - bytesize) & 3) * 8);
414 ptr = value;
415 mem = *ptr;
416
417 /* Write the bits to the masked areas of the other registers. */
418 for (i = 0; i < mask->count; i++)
419 {
420 start = mask->mask[i].bit_start;
421 size = mask->mask[i].bit_size;
422 regval = mem >> shift;
423
424 if ((shift += size) > bitsize)
425 error (_("size of all masks is larger than the register"));
426
427 if (shift >= 32)
428 {
429 mem = *(++ptr);
430 shift -= 32;
431 bitsize -= 32;
432
433 if (shift > 0)
434 regval |= mem << (size - shift);
435 }
436
437 /* Make sure we have a valid register. */
438 r = mask->mask[i].reg_num;
439 if (r >= 0 && size > 0)
440 {
441 /* Don't overwrite the unmasked areas. */
9c9acae0
UW		 442 ULONGEST old_val;
443 regcache_cooked_read_unsigned (regcache, r, &old_val);
ca3bf3bd
DJ		 444 m = 0xffffffff >> (32 - size) << start;
445 regval <<= start;
9c9acae0
UW		 446 regval = (regval & m) | (old_val & ~m);
447 regcache_cooked_write_unsigned (regcache, r, regval);
ca3bf3bd
DJ		 448 }
449 }
450}
451
452
bdb4c075
MG		 453/* Read a tie state or mapped registers. Read the masked areas
454 of the registers and assemble them into a single value. */
ca3bf3bd
DJ		 455
456static void
9c9acae0
UW		 457xtensa_register_read_masked (struct regcache *regcache,
458 xtensa_register_t *reg, gdb_byte *buffer)
ca3bf3bd
DJ		 459{
460 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
ca3bf3bd
DJ		 461 const xtensa_mask_t *mask = reg->mask;
462
463 int shift = 0;
464 int start, size;
465
466 unsigned int *ptr = value;
467 unsigned int regval, mem = 0;
468
469 int bytesize = reg->byte_size;
470 int bitsize = bytesize * 8;
471 int i;
472
473 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
474 reg->name == 0 ? "" : reg->name);
475
476 /* Assemble the register from the masked areas of other registers. */
477 for (i = 0; i < mask->count; i++)
478 {
479 int r = mask->mask[i].reg_num;
9c9acae0
UW		 480 if (r >= 0)
481 {
482 ULONGEST val;
483 regcache_cooked_read_unsigned (regcache, r, &val);
484 regval = (unsigned int) val;
485 }
486 else
487 regval = 0;
488
ca3bf3bd
DJ		 489 start = mask->mask[i].bit_start;
490 size = mask->mask[i].bit_size;
491
492 regval >>= start;
493
494 if (size < 32)
495 regval &= (0xffffffff >> (32 - size));
496
497 mem |= regval << shift;
498
499 if ((shift += size) > bitsize)
500 error (_("size of all masks is larger than the register"));
501
502 if (shift >= 32)
503 {
504 *ptr++ = mem;
505 bitsize -= 32;
506 shift -= 32;
507
508 if (shift == 0)
509 mem = 0;
510 else
511 mem = regval >> (size - shift);
512 }
513 }
514
515 if (shift > 0)
516 *ptr = mem;
517
518 /* Copy value to target byte order. */
519 ptr = value;
520 mem = *ptr;
521
6b50c0b0 522 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
ca3bf3bd
DJ		 523 for (i = 0; i < bytesize; i++)
524 {
525 if ((i & 3) == 0)
526 mem = *ptr++;
527 buffer[bytesize - i - 1] = mem & 0xff;
528 mem >>= 8;
529 }
530 else
531 for (i = 0; i < bytesize; i++)
532 {
533 if ((i & 3) == 0)
534 mem = *ptr++;
535 buffer[i] = mem & 0xff;
536 mem >>= 8;
537 }
538}
539
540
541/* Read pseudo registers. */
542
543static void
544xtensa_pseudo_register_read (struct gdbarch *gdbarch,
545 struct regcache *regcache,
546 int regnum,
547 gdb_byte *buffer)
548{
e17a4113
UW		 549 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
550
ca3bf3bd 551 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
d93859e2 552 regnum, xtensa_register_name (gdbarch, regnum));
ca3bf3bd 553
6b50c0b0 554 if (regnum == gdbarch_num_regs (gdbarch)
94a0e877 555 + gdbarch_num_pseudo_regs (gdbarch) - 1)
6b50c0b0 556 regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
ca3bf3bd 557
bdb4c075 558 /* Read aliases a0..a15, if this is a Windowed ABI. */
6b50c0b0 559 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
94a0e877 560 && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
6b50c0b0 561 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
ca3bf3bd 562 {
ff7a4c00 563 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
ca3bf3bd 564
6b50c0b0 565 regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
ee967b5f 566 regnum = arreg_number (gdbarch, regnum,
e17a4113 567 extract_unsigned_integer (buf, 4, byte_order));
ca3bf3bd
DJ		 568 }
569
bdb4c075 570 /* We can always read non-pseudo registers. */
6b50c0b0 571 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
ca3bf3bd
DJ		 572 regcache_raw_read (regcache, regnum, buffer);
573
94a0e877
MG		 574
575 /* We have to find out how to deal with priveleged registers.
576 Let's treat them as pseudo-registers, but we cannot read/write them. */
577
578 else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
579 {
580 buffer[0] = (gdb_byte)0;
581 buffer[1] = (gdb_byte)0;
582 buffer[2] = (gdb_byte)0;
583 buffer[3] = (gdb_byte)0;
584 }
ca3bf3bd 585 /* Pseudo registers. */
f57d151a 586 else if (regnum >= 0
6b50c0b0
UW		 587 && regnum < gdbarch_num_regs (gdbarch)
588 + gdbarch_num_pseudo_regs (gdbarch))
ca3bf3bd 589 {
6b50c0b0 590 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
ca3bf3bd 591 xtensa_register_type_t type = reg->type;
6b50c0b0 592 int flags = gdbarch_tdep (gdbarch)->target_flags;
ca3bf3bd 593
bdb4c075 594 /* We cannot read Unknown or Unmapped registers. */
ca3bf3bd
DJ		 595 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
596 {
597 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
598 {
599 warning (_("cannot read register %s"),
d93859e2 600 xtensa_register_name (gdbarch, regnum));
ca3bf3bd
DJ		 601 return;
602 }
603 }
604
605 /* Some targets cannot read TIE register files. */
606 else if (type == xtRegisterTypeTieRegfile)
607 {
608 /* Use 'fetch' to get register? */
609 if (flags & xtTargetFlagsUseFetchStore)
610 {
611 warning (_("cannot read register"));
612 return;
613 }
614
615 /* On some targets (esp. simulators), we can always read the reg. */
616 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
617 {
618 warning (_("cannot read register"));
619 return;
620 }
621 }
622
623 /* We can always read mapped registers. */
624 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
625 {
9c9acae0 626 xtensa_register_read_masked (regcache, reg, buffer);
ca3bf3bd
DJ		 627 return;
628 }
629
630 /* Assume that we can read the register. */
631 regcache_raw_read (regcache, regnum, buffer);
632 }
ca3bf3bd
DJ		 633 else
634 internal_error (__FILE__, __LINE__,
635 _("invalid register number %d"), regnum);
636}
637
638
639/* Write pseudo registers. */
640
641static void
642xtensa_pseudo_register_write (struct gdbarch *gdbarch,
643 struct regcache *regcache,
644 int regnum,
645 const gdb_byte *buffer)
646{
e17a4113
UW		 647 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
648
ca3bf3bd 649 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
d93859e2 650 regnum, xtensa_register_name (gdbarch, regnum));
ca3bf3bd 651
6b50c0b0 652 if (regnum == gdbarch_num_regs (gdbarch)
94a0e877 653 + gdbarch_num_pseudo_regs (gdbarch) -1)
6b50c0b0 654 regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
ca3bf3bd 655
bdb4c075 656 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
6b50c0b0 657 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
94a0e877 658 && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
6b50c0b0 659 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
ca3bf3bd 660 {
ff7a4c00 661 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
ca3bf3bd
DJ		 662 unsigned int wb;
663
304fe255 664 regcache_raw_read (regcache,
6b50c0b0 665 gdbarch_tdep (gdbarch)->wb_regnum, buf);
ee967b5f 666 regnum = arreg_number (gdbarch, regnum,
e17a4113 667 extract_unsigned_integer (buf, 4, byte_order));
ca3bf3bd
DJ		 668 }
669
670 /* We can always write 'core' registers.
671 Note: We might have converted Ax->ARy. */
6b50c0b0 672 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
ca3bf3bd
DJ		 673 regcache_raw_write (regcache, regnum, buffer);
674
94a0e877
MG		 675 /* We have to find out how to deal with priveleged registers.
676 Let's treat them as pseudo-registers, but we cannot read/write them. */
677
678 else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
679 {
680 return;
681 }
ca3bf3bd 682 /* Pseudo registers. */
f57d151a 683 else if (regnum >= 0
6b50c0b0
UW		 684 && regnum < gdbarch_num_regs (gdbarch)
685 + gdbarch_num_pseudo_regs (gdbarch))
ca3bf3bd 686 {
6b50c0b0 687 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
ca3bf3bd 688 xtensa_register_type_t type = reg->type;
6b50c0b0 689 int flags = gdbarch_tdep (gdbarch)->target_flags;
ca3bf3bd 690
bdb4c075
MG		 691 /* On most targets, we cannot write registers
692 of type "Unknown" or "Unmapped". */
ca3bf3bd
DJ		 693 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
694 {
695 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
696 {
697 warning (_("cannot write register %s"),
d93859e2 698 xtensa_register_name (gdbarch, regnum));
ca3bf3bd
DJ		 699 return;
700 }
701 }
702
703 /* Some targets cannot read TIE register files. */
704 else if (type == xtRegisterTypeTieRegfile)
705 {
706 /* Use 'store' to get register? */
707 if (flags & xtTargetFlagsUseFetchStore)
708 {
709 warning (_("cannot write register"));
710 return;
711 }
712
713 /* On some targets (esp. simulators), we can always write
714 the register. */
ca3bf3bd
DJ		 715 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
716 {
717 warning (_("cannot write register"));
718 return;
719 }
720 }
721
722 /* We can always write mapped registers. */
723 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
724 {
9c9acae0 725 xtensa_register_write_masked (regcache, reg, buffer);
ca3bf3bd
DJ		 726 return;
727 }
728
729 /* Assume that we can write the register. */
730 regcache_raw_write (regcache, regnum, buffer);
731 }
ca3bf3bd
DJ		 732 else
733 internal_error (__FILE__, __LINE__,
734 _("invalid register number %d"), regnum);
735}
736
ca3bf3bd
DJ		 737static struct reggroup *xtensa_ar_reggroup;
738static struct reggroup *xtensa_user_reggroup;
739static struct reggroup *xtensa_vectra_reggroup;
7b871568 740static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR];
ca3bf3bd
DJ		 741
742static void
743xtensa_init_reggroups (void)
744{
98689b25
MG		 745 int i;
746 char cpname[] = "cp0";
747
ca3bf3bd
DJ		 748 xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP);
749 xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP);
750 xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP);
ca3bf3bd 751
98689b25
MG		 752 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
753 {
b801de47 754 cpname[2] = '0' + i;
98689b25
MG		 755 xtensa_cp[i] = reggroup_new (cpname, USER_REGGROUP);
756 }
7b871568 757}
ca3bf3bd
DJ		 758
759static void
760xtensa_add_reggroups (struct gdbarch *gdbarch)
761{
7b871568
MG		 762 int i;
763
764 /* Predefined groups. */
ca3bf3bd
DJ		 765 reggroup_add (gdbarch, all_reggroup);
766 reggroup_add (gdbarch, save_reggroup);
767 reggroup_add (gdbarch, restore_reggroup);
768 reggroup_add (gdbarch, system_reggroup);
7b871568
MG		 769 reggroup_add (gdbarch, vector_reggroup);
770 reggroup_add (gdbarch, general_reggroup);
771 reggroup_add (gdbarch, float_reggroup);
772
773 /* Xtensa-specific groups. */
774 reggroup_add (gdbarch, xtensa_ar_reggroup);
775 reggroup_add (gdbarch, xtensa_user_reggroup);
776 reggroup_add (gdbarch, xtensa_vectra_reggroup);
ca3bf3bd 777
7b871568
MG		 778 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
779 reggroup_add (gdbarch, xtensa_cp[i]);
ca3bf3bd
DJ		 780}
781
7b871568
MG		 782static int
783xtensa_coprocessor_register_group (struct reggroup *group)
784{
785 int i;
786
787 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
788 if (group == xtensa_cp[i])
789 return i;
790
791 return -1;
792}
ca3bf3bd
DJ		 793
794#define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
795 | XTENSA_REGISTER_FLAGS_WRITABLE \
796 | XTENSA_REGISTER_FLAGS_VOLATILE)
797
798#define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
799 | XTENSA_REGISTER_FLAGS_WRITABLE)
800
801static int
802xtensa_register_reggroup_p (struct gdbarch *gdbarch,
803 int regnum,
804 struct reggroup *group)
805{
6b50c0b0 806 xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
ca3bf3bd
DJ		 807 xtensa_register_type_t type = reg->type;
808 xtensa_register_group_t rg = reg->group;
7b871568 809 int cp_number;
ca3bf3bd 810
57041825
MG		 811 if (group == save_reggroup)
812 /* Every single register should be included into the list of registers
813 to be watched for changes while using -data-list-changed-registers. */
814 return 1;
815
ca3bf3bd
DJ		 816 /* First, skip registers that are not visible to this target
817 (unknown and unmapped registers when not using ISS). */
818
819 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
820 return 0;
821 if (group == all_reggroup)
822 return 1;
823 if (group == xtensa_ar_reggroup)
824 return rg & xtRegisterGroupAddrReg;
825 if (group == xtensa_user_reggroup)
826 return rg & xtRegisterGroupUser;
827 if (group == float_reggroup)
828 return rg & xtRegisterGroupFloat;
829 if (group == general_reggroup)
830 return rg & xtRegisterGroupGeneral;
ca3bf3bd
DJ		 831 if (group == system_reggroup)
832 return rg & xtRegisterGroupState;
833 if (group == vector_reggroup || group == xtensa_vectra_reggroup)
834 return rg & xtRegisterGroupVectra;
57041825 835 if (group == restore_reggroup)
6b50c0b0 836 return (regnum < gdbarch_num_regs (gdbarch)
ca3bf3bd 837 && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID);
7b871568
MG		 838 if ((cp_number = xtensa_coprocessor_register_group (group)) >= 0)
839 return rg & (xtRegisterGroupCP0 << cp_number);
ca3bf3bd
DJ		 840 else
841 return 1;
842}
843
844
ca3bf3bd
DJ		 845/* Supply register REGNUM from the buffer specified by GREGS and LEN
846 in the general-purpose register set REGSET to register cache
bdb4c075 847 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
ca3bf3bd
DJ		 848
849static void
850xtensa_supply_gregset (const struct regset *regset,
851 struct regcache *rc,
852 int regnum,
853 const void *gregs,
854 size_t len)
855{
856 const xtensa_elf_gregset_t *regs = gregs;
6b50c0b0 857 struct gdbarch *gdbarch = get_regcache_arch (rc);
ca3bf3bd
DJ		 858 int i;
859
cce7e648 860 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum);
ca3bf3bd 861
6b50c0b0
UW		 862 if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1)
863 regcache_raw_supply (rc, gdbarch_pc_regnum (gdbarch), (char *) &regs->pc);
864 if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1)
865 regcache_raw_supply (rc, gdbarch_ps_regnum (gdbarch), (char *) &regs->ps);
866 if (regnum == gdbarch_tdep (gdbarch)->wb_regnum || regnum == -1)
867 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->wb_regnum,
304fe255 868 (char *) &regs->windowbase);
6b50c0b0
UW		 869 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum || regnum == -1)
870 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ws_regnum,
304fe255 871 (char *) &regs->windowstart);
6b50c0b0
UW		 872 if (regnum == gdbarch_tdep (gdbarch)->lbeg_regnum || regnum == -1)
873 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lbeg_regnum,
304fe255 874 (char *) &regs->lbeg);
6b50c0b0
UW		 875 if (regnum == gdbarch_tdep (gdbarch)->lend_regnum || regnum == -1)
876 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lend_regnum,
304fe255 877 (char *) &regs->lend);
6b50c0b0
UW		 878 if (regnum == gdbarch_tdep (gdbarch)->lcount_regnum || regnum == -1)
879 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lcount_regnum,
304fe255 880 (char *) &regs->lcount);
6b50c0b0
UW		 881 if (regnum == gdbarch_tdep (gdbarch)->sar_regnum || regnum == -1)
882 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->sar_regnum,
304fe255 883 (char *) &regs->sar);
6b50c0b0
UW		 884 if (regnum >=gdbarch_tdep (gdbarch)->ar_base
885 && regnum < gdbarch_tdep (gdbarch)->ar_base
886 + gdbarch_tdep (gdbarch)->num_aregs)
304fe255
UW		 887 regcache_raw_supply (rc, regnum,
888 (char *) &regs->ar[regnum - gdbarch_tdep
6b50c0b0 889 (gdbarch)->ar_base]);
ca3bf3bd
DJ		 890 else if (regnum == -1)
891 {
6b50c0b0
UW		 892 for (i = 0; i < gdbarch_tdep (gdbarch)->num_aregs; ++i)
893 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ar_base + i,
304fe255 894 (char *) &regs->ar[i]);
ca3bf3bd
DJ		 895 }
896}
897
898
899/* Xtensa register set. */
900
901static struct regset
902xtensa_gregset =
903{
904 NULL,
905 xtensa_supply_gregset
906};
907
908
bdb4c075
MG		 909/* Return the appropriate register set for the core
910 section identified by SECT_NAME and SECT_SIZE. */
ca3bf3bd
DJ		 911
912static const struct regset *
913xtensa_regset_from_core_section (struct gdbarch *core_arch,
914 const char *sect_name,
915 size_t sect_size)
916{
917 DEBUGTRACE ("xtensa_regset_from_core_section "
cce7e648 918 "(..., sect_name==\"%s\", sect_size==%x)\n",
ec20a626 919 sect_name, (unsigned int) sect_size);
ca3bf3bd
DJ		 920
921 if (strcmp (sect_name, ".reg") == 0
922 && sect_size >= sizeof(xtensa_elf_gregset_t))
923 return &xtensa_gregset;
924
925 return NULL;
926}
927
928
bdb4c075 929/* Handling frames. */
ca3bf3bd 930
bdb4c075
MG		 931/* Number of registers to save in case of Windowed ABI. */
932#define XTENSA_NUM_SAVED_AREGS 12
ca3bf3bd 933
bdb4c075
MG		 934/* Frame cache part for Windowed ABI. */
935typedef struct xtensa_windowed_frame_cache
ca3bf3bd 936{
ee967b5f
MG		 937 int wb; /* WINDOWBASE of the previous frame. */
938 int callsize; /* Call size of this frame. */
08b9c608
MG		 939 int ws; /* WINDOWSTART of the previous frame. It keeps track of
940 life windows only. If there is no bit set for the
941 window, that means it had been already spilled
942 because of window overflow. */
943
944 /* Addresses of spilled A-registers.
945 AREGS[i] == -1, if corresponding AR is alive. */
ca3bf3bd 946 CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS];
bdb4c075
MG		 947} xtensa_windowed_frame_cache_t;
948
949/* Call0 ABI Definitions. */
950
581e13c1
MS		 951#define C0_MAXOPDS 3 /* Maximum number of operands for prologue
952 analysis. */
bdb4c075
MG		 953#define C0_NREGS 16 /* Number of A-registers to track. */
954#define C0_CLESV 12 /* Callee-saved registers are here and up. */
955#define C0_SP 1 /* Register used as SP. */
956#define C0_FP 15 /* Register used as FP. */
957#define C0_RA 0 /* Register used as return address. */
958#define C0_ARGS 2 /* Register used as first arg/retval. */
959#define C0_NARGS 6 /* Number of A-regs for args/retvals. */
960
961/* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
962 A-register where the current content of the reg came from (in terms
963 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
964 mean that the orignal content of the register was saved to the stack.
965 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
966 know where SP will end up until the entire prologue has been analyzed. */
967
968#define C0_CONST -1 /* fr_reg value if register contains a constant. */
969#define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
970#define C0_NOSTK -1 /* to_stk value if register has not been stored. */
971
972extern xtensa_isa xtensa_default_isa;
973
974typedef struct xtensa_c0reg
975{
dbab50de
MG		 976 int fr_reg; /* original register from which register content
977 is derived, or C0_CONST, or C0_INEXP. */
978 int fr_ofs; /* constant offset from reg, or immediate value. */
979 int to_stk; /* offset from original SP to register (4-byte aligned),
980 or C0_NOSTK if register has not been saved. */
bdb4c075
MG		 981} xtensa_c0reg_t;
982
bdb4c075
MG		 983/* Frame cache part for Call0 ABI. */
984typedef struct xtensa_call0_frame_cache
985{
dbab50de
MG		 986 int c0_frmsz; /* Stack frame size. */
987 int c0_hasfp; /* Current frame uses frame pointer. */
988 int fp_regnum; /* A-register used as FP. */
989 int c0_fp; /* Actual value of frame pointer. */
990 int c0_fpalign; /* Dinamic adjustment for the stack
991 pointer. It's an AND mask. Zero,
992 if alignment was not adjusted. */
993 int c0_old_sp; /* In case of dynamic adjustment, it is
994 a register holding unaligned sp.
995 C0_INEXP, when undefined. */
996 int c0_sp_ofs; /* If "c0_old_sp" was spilled it's a
997 stack offset. C0_NOSTK otherwise. */
998
999 xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */
bdb4c075
MG		 1000} xtensa_call0_frame_cache_t;
1001
1002typedef struct xtensa_frame_cache
1003{
ee967b5f 1004 CORE_ADDR base; /* Stack pointer of this frame. */
08b9c608
MG		 1005 CORE_ADDR pc; /* PC of this frame at the function entry point. */
1006 CORE_ADDR ra; /* The raw return address of this frame. */
1007 CORE_ADDR ps; /* The PS register of the previous (older) frame. */
1008 CORE_ADDR prev_sp; /* Stack Pointer of the previous (older) frame. */
bdb4c075
MG		 1009 int call0; /* It's a call0 framework (else windowed). */
1010 union
1011 {
1012 xtensa_windowed_frame_cache_t wd; /* call0 == false. */
1013 xtensa_call0_frame_cache_t c0; /* call0 == true. */
1014 };
ca3bf3bd
DJ		 1015} xtensa_frame_cache_t;
1016
1017
1018static struct xtensa_frame_cache *
bdb4c075 1019xtensa_alloc_frame_cache (int windowed)
ca3bf3bd
DJ		 1020{
1021 xtensa_frame_cache_t *cache;
1022 int i;
1023
1024 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
1025
1026 cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t);
1027
1028 cache->base = 0;
1029 cache->pc = 0;
1030 cache->ra = 0;
ca3bf3bd 1031 cache->ps = 0;
ca3bf3bd 1032 cache->prev_sp = 0;
bdb4c075
MG		 1033 cache->call0 = !windowed;
1034 if (cache->call0)
1035 {
1036 cache->c0.c0_frmsz = -1;
1037 cache->c0.c0_hasfp = 0;
1038 cache->c0.fp_regnum = -1;
1039 cache->c0.c0_fp = -1;
dbab50de
MG		 1040 cache->c0.c0_fpalign = 0;
1041 cache->c0.c0_old_sp = C0_INEXP;
1042 cache->c0.c0_sp_ofs = C0_NOSTK;
ca3bf3bd 1043
bdb4c075
MG		 1044 for (i = 0; i < C0_NREGS; i++)
1045 {
1046 cache->c0.c0_rt[i].fr_reg = i;
1047 cache->c0.c0_rt[i].fr_ofs = 0;
1048 cache->c0.c0_rt[i].to_stk = C0_NOSTK;
1049 }
1050 }
1051 else
1052 {
1053 cache->wd.wb = 0;
ee967b5f 1054 cache->wd.ws = 0;
bdb4c075 1055 cache->wd.callsize = -1;
ca3bf3bd 1056
bdb4c075
MG		 1057 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
1058 cache->wd.aregs[i] = -1;
1059 }
ca3bf3bd
DJ		 1060 return cache;
1061}
1062
1063
1064static CORE_ADDR
1065xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
1066{
1067 return address & ~15;
1068}
1069
1070
1071static CORE_ADDR
1072xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1073{
ff7a4c00 1074 gdb_byte buf[8];
0dfff4cb 1075 CORE_ADDR pc;
ca3bf3bd 1076
a74ce742
PM		 1077 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n",
1078 host_address_to_string (next_frame));
ca3bf3bd 1079
6b50c0b0 1080 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
0dfff4cb 1081 pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
ca3bf3bd 1082
0dfff4cb 1083 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc);
ca3bf3bd 1084
0dfff4cb 1085 return pc;
ca3bf3bd
DJ		 1086}
1087
1088
1089static struct frame_id
5142f611 1090xtensa_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
ca3bf3bd
DJ		 1091{
1092 CORE_ADDR pc, fp;
ca3bf3bd 1093
5142f611 1094 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
ca3bf3bd 1095
5142f611
MG		 1096 pc = get_frame_pc (this_frame);
1097 fp = get_frame_register_unsigned
1098 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
ca3bf3bd
DJ		 1099
1100 /* Make dummy frame ID unique by adding a constant. */
bdb4c075 1101 return frame_id_build (fp + SP_ALIGNMENT, pc);
ca3bf3bd
DJ		 1102}
1103
08b9c608
MG		 1104/* Returns true, if instruction to execute next is unique to Xtensa Window
1105 Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */
1106
1107static int
1108xtensa_window_interrupt_insn (struct gdbarch *gdbarch, CORE_ADDR pc)
1109{
1110 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1111 unsigned int insn = read_memory_integer (pc, 4, byte_order);
1112 unsigned int code;
1113
1114 if (byte_order == BFD_ENDIAN_BIG)
1115 {
1116 /* Check, if this is L32E or S32E. */
1117 code = insn & 0xf000ff00;
1118 if ((code == 0x00009000) || (code == 0x00009400))
1119 return 1;
1120 /* Check, if this is RFWU or RFWO. */
1121 code = insn & 0xffffff00;
1122 return ((code == 0x00430000) || (code == 0x00530000));
1123 }
1124 else
1125 {
1126 /* Check, if this is L32E or S32E. */
1127 code = insn & 0x00ff000f;
1128 if ((code == 0x090000) || (code == 0x490000))
1129 return 1;
1130 /* Check, if this is RFWU or RFWO. */
1131 code = insn & 0x00ffffff;
1132 return ((code == 0x00003400) || (code == 0x00003500));
1133 }
1134}
1135
ee967b5f
MG		 1136/* Returns the best guess about which register is a frame pointer
1137 for the function containing CURRENT_PC. */
1138
d4709618
MG		 1139#define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1140#define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */
ee967b5f
MG		 1141
1142static unsigned int
1143xtensa_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR current_pc)
1144{
1145#define RETURN_FP goto done
1146
1147 unsigned int fp_regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
1148 CORE_ADDR start_addr;
1149 xtensa_isa isa;
1150 xtensa_insnbuf ins, slot;
1151 char ibuf[XTENSA_ISA_BSZ];
1152 CORE_ADDR ia, bt, ba;
1153 xtensa_format ifmt;
1154 int ilen, islots, is;
1155 xtensa_opcode opc;
1156 const char *opcname;
1157
1158 find_pc_partial_function (current_pc, NULL, &start_addr, NULL);
1159 if (start_addr == 0)
1160 return fp_regnum;
1161
1162 if (!xtensa_default_isa)
1163 xtensa_default_isa = xtensa_isa_init (0, 0);
1164 isa = xtensa_default_isa;
1165 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
1166 ins = xtensa_insnbuf_alloc (isa);
1167 slot = xtensa_insnbuf_alloc (isa);
1168 ba = 0;
1169
1170 for (ia = start_addr, bt = ia; ia < current_pc ; ia += ilen)
1171 {
1172 if (ia + xtensa_isa_maxlength (isa) > bt)
1173 {
1174 ba = ia;
1175 bt = (ba + XTENSA_ISA_BSZ) < current_pc
1176 ? ba + XTENSA_ISA_BSZ : current_pc;
d4709618
MG		 1177 if (target_read_memory (ba, ibuf, bt - ba) != 0)
1178 RETURN_FP;
ee967b5f
MG		 1179 }
1180
1181 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
1182 ifmt = xtensa_format_decode (isa, ins);
1183 if (ifmt == XTENSA_UNDEFINED)
1184 RETURN_FP;
1185 ilen = xtensa_format_length (isa, ifmt);
1186 if (ilen == XTENSA_UNDEFINED)
1187 RETURN_FP;
1188 islots = xtensa_format_num_slots (isa, ifmt);
1189 if (islots == XTENSA_UNDEFINED)
1190 RETURN_FP;
1191
1192 for (is = 0; is < islots; ++is)
1193 {
1194 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
1195 RETURN_FP;
1196
1197 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
1198 if (opc == XTENSA_UNDEFINED)
1199 RETURN_FP;
1200
1201 opcname = xtensa_opcode_name (isa, opc);
1202
1203 if (strcasecmp (opcname, "mov.n") == 0
1204 || strcasecmp (opcname, "or") == 0)
1205 {
1206 unsigned int register_operand;
1207
1208 /* Possible candidate for setting frame pointer
581e13c1 1209 from A1. This is what we are looking for. */
ee967b5f
MG		 1210
1211 if (xtensa_operand_get_field (isa, opc, 1, ifmt,
1212 is, slot, &register_operand) != 0)
1213 RETURN_FP;
1214 if (xtensa_operand_decode (isa, opc, 1, &register_operand) != 0)
1215 RETURN_FP;
1216 if (register_operand == 1) /* Mov{.n} FP A1. */
1217 {
1218 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot,
1219 &register_operand) != 0)
1220 RETURN_FP;
1221 if (xtensa_operand_decode (isa, opc, 0,
1222 &register_operand) != 0)
1223 RETURN_FP;
1224
581e13c1
MS		 1225 fp_regnum
1226 = gdbarch_tdep (gdbarch)->a0_base + register_operand;
ee967b5f
MG		 1227 RETURN_FP;
1228 }
1229 }
1230
1231 if (
1232 /* We have problems decoding the memory. */
1233 opcname == NULL
1234 || strcasecmp (opcname, "ill") == 0
1235 || strcasecmp (opcname, "ill.n") == 0
1236 /* Hit planted breakpoint. */
1237 || strcasecmp (opcname, "break") == 0
1238 || strcasecmp (opcname, "break.n") == 0
1239 /* Flow control instructions finish prologue. */
1240 || xtensa_opcode_is_branch (isa, opc) > 0
1241 || xtensa_opcode_is_jump (isa, opc) > 0
1242 || xtensa_opcode_is_loop (isa, opc) > 0
1243 || xtensa_opcode_is_call (isa, opc) > 0
1244 || strcasecmp (opcname, "simcall") == 0
1245 || strcasecmp (opcname, "syscall") == 0)
1246 /* Can not continue analysis. */
1247 RETURN_FP;
1248 }
1249 }
1250done:
1251 xtensa_insnbuf_free(isa, slot);
1252 xtensa_insnbuf_free(isa, ins);
1253 return fp_regnum;
1254}
1255
bdb4c075
MG		 1256/* The key values to identify the frame using "cache" are
1257
ee967b5f 1258 cache->base = SP (or best guess about FP) of this frame;
bdb4c075 1259 cache->pc = entry-PC (entry point of the frame function);
581e13c1 1260 cache->prev_sp = SP of the previous frame. */
bdb4c075
MG		 1261
1262static void
5142f611 1263call0_frame_cache (struct frame_info *this_frame,
dbab50de 1264 xtensa_frame_cache_t *cache, CORE_ADDR pc);
ca3bf3bd 1265
08b9c608
MG		 1266static void
1267xtensa_window_interrupt_frame_cache (struct frame_info *this_frame,
1268 xtensa_frame_cache_t *cache,
1269 CORE_ADDR pc);
1270
ca3bf3bd 1271static struct xtensa_frame_cache *
5142f611 1272xtensa_frame_cache (struct frame_info *this_frame, void **this_cache)
ca3bf3bd
DJ		 1273{
1274 xtensa_frame_cache_t *cache;
ca3bf3bd 1275 CORE_ADDR ra, wb, ws, pc, sp, ps;
5142f611 1276 struct gdbarch *gdbarch = get_frame_arch (this_frame);
e17a4113 1277 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
ee967b5f 1278 unsigned int fp_regnum;
98689b25 1279 int windowed, ps_regnum;
ca3bf3bd 1280
ca3bf3bd
DJ		 1281 if (*this_cache)
1282 return *this_cache;
1283
98689b25
MG		 1284 pc = get_frame_register_unsigned (this_frame, gdbarch_pc_regnum (gdbarch));
1285 ps_regnum = gdbarch_ps_regnum (gdbarch);
68d6df83
MG		 1286 ps = (ps_regnum >= 0
1287 ? get_frame_register_unsigned (this_frame, ps_regnum) : TX_PS);
98689b25
MG		 1288
1289 windowed = windowing_enabled (gdbarch, ps);
bdb4c075 1290
ca3bf3bd 1291 /* Get pristine xtensa-frame. */
bdb4c075 1292 cache = xtensa_alloc_frame_cache (windowed);
ca3bf3bd
DJ		 1293 *this_cache = cache;
1294
bdb4c075 1295 if (windowed)
ca3bf3bd 1296 {
98689b25
MG		 1297 char op1;
1298
bdb4c075 1299 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
5142f611
MG		 1300 wb = get_frame_register_unsigned (this_frame,
1301 gdbarch_tdep (gdbarch)->wb_regnum);
1302 ws = get_frame_register_unsigned (this_frame,
1303 gdbarch_tdep (gdbarch)->ws_regnum);
ca3bf3bd 1304
e17a4113 1305 op1 = read_memory_integer (pc, 1, byte_order);
91d8eb23 1306 if (XTENSA_IS_ENTRY (gdbarch, op1))
ca3bf3bd 1307 {
bdb4c075 1308 int callinc = CALLINC (ps);
5142f611
MG		 1309 ra = get_frame_register_unsigned
1310 (this_frame, gdbarch_tdep (gdbarch)->a0_base + callinc * 4);
bdb4c075
MG		 1311
1312 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1313 cache->wd.callsize = 0;
1314 cache->wd.wb = wb;
1315 cache->wd.ws = ws;
5142f611
MG		 1316 cache->prev_sp = get_frame_register_unsigned
1317 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
ee967b5f
MG		 1318
1319 /* This only can be the outermost frame since we are
1320 just about to execute ENTRY. SP hasn't been set yet.
1321 We can assume any frame size, because it does not
1322 matter, and, let's fake frame base in cache. */
98689b25 1323 cache->base = cache->prev_sp - 16;
ee967b5f
MG		 1324
1325 cache->pc = pc;
1326 cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
1327 cache->ps = (ps & ~PS_CALLINC_MASK)
1328 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1329
1330 return cache;
bdb4c075
MG		 1331 }
1332 else
1333 {
ee967b5f 1334 fp_regnum = xtensa_scan_prologue (gdbarch, pc);
5142f611
MG		 1335 ra = get_frame_register_unsigned (this_frame,
1336 gdbarch_tdep (gdbarch)->a0_base);
bdb4c075 1337 cache->wd.callsize = WINSIZE (ra);
304fe255 1338 cache->wd.wb = (wb - cache->wd.callsize / 4)
6b50c0b0 1339 & (gdbarch_tdep (gdbarch)->num_aregs / 4 - 1);
bdb4c075 1340 cache->wd.ws = ws & ~(1 << wb);
ca3bf3bd 1341
5142f611 1342 cache->pc = get_frame_func (this_frame);
f6402f18 1343 cache->ra = (pc & 0xc0000000) | (ra & 0x3fffffff);
ee967b5f
MG		 1344 cache->ps = (ps & ~PS_CALLINC_MASK)
1345 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1346 }
bdb4c075
MG		 1347
1348 if (cache->wd.ws == 0)
ca3bf3bd 1349 {
bdb4c075 1350 int i;
ca3bf3bd 1351
bdb4c075 1352 /* Set A0...A3. */
5142f611
MG		 1353 sp = get_frame_register_unsigned
1354 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1) - 16;
bdb4c075
MG		 1355
1356 for (i = 0; i < 4; i++, sp += 4)
1357 {
1358 cache->wd.aregs[i] = sp;
1359 }
ca3bf3bd 1360
bdb4c075 1361 if (cache->wd.callsize > 4)
ca3bf3bd 1362 {
bdb4c075 1363 /* Set A4...A7/A11. */
ee967b5f
MG		 1364 /* Get the SP of the frame previous to the previous one.
1365 To achieve this, we have to dereference SP twice. */
e17a4113
UW		 1366 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
1367 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
bdb4c075
MG		 1368 sp -= cache->wd.callsize * 4;
1369
ee967b5f 1370 for ( i = 4; i < cache->wd.callsize; i++, sp += 4)
bdb4c075
MG		 1371 {
1372 cache->wd.aregs[i] = sp;
1373 }
ca3bf3bd
DJ		 1374 }
1375 }
ca3bf3bd 1376
bdb4c075 1377 if ((cache->prev_sp == 0) && ( ra != 0 ))
08b9c608
MG		 1378 /* If RA is equal to 0 this frame is an outermost frame. Leave
1379 cache->prev_sp unchanged marking the boundary of the frame stack. */
ca3bf3bd 1380 {
ee967b5f 1381 if ((cache->wd.ws & (1 << cache->wd.wb)) == 0)
bdb4c075
MG		 1382 {
1383 /* Register window overflow already happened.
1384 We can read caller's SP from the proper spill loction. */
5142f611
MG		 1385 sp = get_frame_register_unsigned
1386 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
e17a4113 1387 cache->prev_sp = read_memory_integer (sp - 12, 4, byte_order);
bdb4c075
MG		 1388 }
1389 else
1390 {
1391 /* Read caller's frame SP directly from the previous window. */
ee967b5f 1392 int regnum = arreg_number
91d8eb23 1393 (gdbarch, gdbarch_tdep (gdbarch)->a0_base + 1,
304fe255 1394 cache->wd.wb);
ca3bf3bd 1395
08b9c608 1396 cache->prev_sp = xtensa_read_register (regnum);
bdb4c075 1397 }
ca3bf3bd
DJ		 1398 }
1399 }
08b9c608
MG		 1400 else if (xtensa_window_interrupt_insn (gdbarch, pc))
1401 {
1402 /* Execution stopped inside Xtensa Window Interrupt Handler. */
1403
1404 xtensa_window_interrupt_frame_cache (this_frame, cache, pc);
1405 /* Everything was set already, including cache->base. */
1406 return cache;
1407 }
bdb4c075
MG		 1408 else /* Call0 framework. */
1409 {
dbab50de 1410 call0_frame_cache (this_frame, cache, pc);
ee967b5f 1411 fp_regnum = cache->c0.fp_regnum;
bdb4c075 1412 }
ca3bf3bd 1413
5142f611 1414 cache->base = get_frame_register_unsigned (this_frame, fp_regnum);
ca3bf3bd 1415
ca3bf3bd
DJ		 1416 return cache;
1417}
1418
dbab50de
MG		 1419static int xtensa_session_once_reported = 1;
1420
1421/* Report a problem with prologue analysis while doing backtracing.
1422 But, do it only once to avoid annoyng repeated messages. */
1423
4e6ca6d5
MG		 1424static void
1425warning_once (void)
dbab50de
MG		 1426{
1427 if (xtensa_session_once_reported == 0)
1428 warning (_("\
1429\nUnrecognised function prologue. Stack trace cannot be resolved. \
1430This message will not be repeated in this session.\n"));
1431
1432 xtensa_session_once_reported = 1;
1433}
1434
1435
ca3bf3bd 1436static void
5142f611 1437xtensa_frame_this_id (struct frame_info *this_frame,
ca3bf3bd
DJ		 1438 void **this_cache,
1439 struct frame_id *this_id)
1440{
1441 struct xtensa_frame_cache *cache =
5142f611 1442 xtensa_frame_cache (this_frame, this_cache);
ca3bf3bd
DJ		 1443
1444 if (cache->prev_sp == 0)
1445 return;
1446
5142f611 1447 (*this_id) = frame_id_build (cache->prev_sp, cache->pc);
bdb4c075 1448}
ca3bf3bd 1449
5142f611
MG		 1450static struct value *
1451xtensa_frame_prev_register (struct frame_info *this_frame,
ca3bf3bd 1452 void **this_cache,
5142f611 1453 int regnum)
ca3bf3bd 1454{
5142f611
MG		 1455 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1456 struct xtensa_frame_cache *cache;
1457 ULONGEST saved_reg = 0;
ca3bf3bd
DJ		 1458 int done = 1;
1459
5142f611
MG		 1460 if (*this_cache == NULL)
1461 *this_cache = xtensa_frame_cache (this_frame, this_cache);
1462 cache = *this_cache;
ca3bf3bd 1463
6b50c0b0 1464 if (regnum ==gdbarch_pc_regnum (gdbarch))
bdb4c075 1465 saved_reg = cache->ra;
6b50c0b0 1466 else if (regnum == gdbarch_tdep (gdbarch)->a0_base + 1)
bdb4c075
MG		 1467 saved_reg = cache->prev_sp;
1468 else if (!cache->call0)
ca3bf3bd 1469 {
6b50c0b0 1470 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum)
ee967b5f 1471 saved_reg = cache->wd.ws;
6b50c0b0 1472 else if (regnum == gdbarch_tdep (gdbarch)->wb_regnum)
bdb4c075 1473 saved_reg = cache->wd.wb;
6b50c0b0 1474 else if (regnum == gdbarch_ps_regnum (gdbarch))
bdb4c075 1475 saved_reg = cache->ps;
ca3bf3bd 1476 else
bdb4c075 1477 done = 0;
ca3bf3bd 1478 }
ca3bf3bd
DJ		 1479 else
1480 done = 0;
1481
1482 if (done)
5142f611 1483 return frame_unwind_got_constant (this_frame, regnum, saved_reg);
ca3bf3bd 1484
bdb4c075 1485 if (!cache->call0) /* Windowed ABI. */
ca3bf3bd 1486 {
ee967b5f
MG		 1487 /* Convert A-register numbers to AR-register numbers,
1488 if we deal with A-register. */
94a0e877 1489 if (regnum >= gdbarch_tdep (gdbarch)->a0_base
6b50c0b0 1490 && regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)
ee967b5f 1491 regnum = arreg_number (gdbarch, regnum, cache->wd.wb);
ca3bf3bd 1492
ee967b5f 1493 /* Check, if we deal with AR-register saved on stack. */
6b50c0b0
UW		 1494 if (regnum >= gdbarch_tdep (gdbarch)->ar_base
1495 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1496 + gdbarch_tdep (gdbarch)->num_aregs))
bdb4c075 1497 {
ee967b5f 1498 int areg = areg_number (gdbarch, regnum, cache->wd.wb);
ca3bf3bd 1499
bdb4c075
MG		 1500 if (areg >= 0
1501 && areg < XTENSA_NUM_SAVED_AREGS
1502 && cache->wd.aregs[areg] != -1)
5142f611
MG		 1503 return frame_unwind_got_memory (this_frame, regnum,
1504 cache->wd.aregs[areg]);
ca3bf3bd
DJ		 1505 }
1506 }
bdb4c075
MG		 1507 else /* Call0 ABI. */
1508 {
6b50c0b0
UW		 1509 int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base
1510 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
304fe255 1511 + C0_NREGS))
6b50c0b0 1512 ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum;
ca3bf3bd 1513
bdb4c075
MG		 1514 if (reg < C0_NREGS)
1515 {
1516 CORE_ADDR spe;
1517 int stkofs;
1518
1519 /* If register was saved in the prologue, retrieve it. */
1520 stkofs = cache->c0.c0_rt[reg].to_stk;
1521 if (stkofs != C0_NOSTK)
1522 {
1523 /* Determine SP on entry based on FP. */
1524 spe = cache->c0.c0_fp
1525 - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
5142f611 1526
581e13c1
MS		 1527 return frame_unwind_got_memory (this_frame, regnum,
1528 spe + stkofs);
bdb4c075
MG		 1529 }
1530 }
1531 }
1532
1533 /* All other registers have been either saved to
1534 the stack or are still alive in the processor. */
ca3bf3bd 1535
5142f611 1536 return frame_unwind_got_register (this_frame, regnum, regnum);
ca3bf3bd
DJ		 1537}
1538
1539
1540static const struct frame_unwind
5142f611 1541xtensa_unwind =
ca3bf3bd
DJ		 1542{
1543 NORMAL_FRAME,
1544 xtensa_frame_this_id,
5142f611
MG		 1545 xtensa_frame_prev_register,
1546 NULL,
1547 default_frame_sniffer
ca3bf3bd
DJ		 1548};
1549
ca3bf3bd 1550static CORE_ADDR
5142f611 1551xtensa_frame_base_address (struct frame_info *this_frame, void **this_cache)
ca3bf3bd
DJ		 1552{
1553 struct xtensa_frame_cache *cache =
5142f611 1554 xtensa_frame_cache (this_frame, this_cache);
ca3bf3bd
DJ		 1555
1556 return cache->base;
1557}
1558
1559static const struct frame_base
1560xtensa_frame_base =
1561{
5142f611 1562 &xtensa_unwind,
ca3bf3bd
DJ		 1563 xtensa_frame_base_address,
1564 xtensa_frame_base_address,
1565 xtensa_frame_base_address
1566};
1567
1568
1569static void
1570xtensa_extract_return_value (struct type *type,
1571 struct regcache *regcache,
1572 void *dst)
1573{
6b50c0b0 1574 struct gdbarch *gdbarch = get_regcache_arch (regcache);
ca3bf3bd
DJ		 1575 bfd_byte *valbuf = dst;
1576 int len = TYPE_LENGTH (type);
1577 ULONGEST pc, wb;
1578 int callsize, areg;
1579 int offset = 0;
1580
1581 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1582
1583 gdb_assert(len > 0);
1584
6b50c0b0 1585 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
bdb4c075
MG		 1586 {
1587 /* First, we have to find the caller window in the register file. */
6b50c0b0 1588 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
91d8eb23 1589 callsize = extract_call_winsize (gdbarch, pc);
ca3bf3bd 1590
bdb4c075
MG		 1591 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1592 if (len > (callsize > 8 ? 8 : 16))
1593 internal_error (__FILE__, __LINE__,
581e13c1
MS		 1594 _("cannot extract return value of %d bytes long"),
1595 len);
ca3bf3bd 1596
bdb4c075
MG		 1597 /* Get the register offset of the return
1598 register (A2) in the caller window. */
304fe255 1599 regcache_raw_read_unsigned
6b50c0b0 1600 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
ee967b5f 1601 areg = arreg_number (gdbarch,
91d8eb23 1602 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
bdb4c075
MG		 1603 }
1604 else
1605 {
1606 /* No windowing hardware - Call0 ABI. */
94a0e877 1607 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
bdb4c075 1608 }
ca3bf3bd
DJ		 1609
1610 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len);
1611
6b50c0b0 1612 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
ca3bf3bd
DJ		 1613 offset = 4 - len;
1614
1615 for (; len > 0; len -= 4, areg++, valbuf += 4)
1616 {
1617 if (len < 4)
1618 regcache_raw_read_part (regcache, areg, offset, len, valbuf);
1619 else
1620 regcache_raw_read (regcache, areg, valbuf);
1621 }
1622}
1623
1624
1625static void
1626xtensa_store_return_value (struct type *type,
1627 struct regcache *regcache,
1628 const void *dst)
1629{
6b50c0b0 1630 struct gdbarch *gdbarch = get_regcache_arch (regcache);
ca3bf3bd
DJ		 1631 const bfd_byte *valbuf = dst;
1632 unsigned int areg;
1633 ULONGEST pc, wb;
1634 int callsize;
1635 int len = TYPE_LENGTH (type);
1636 int offset = 0;
1637
1638 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1639
6b50c0b0 1640 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
bdb4c075 1641 {
6b50c0b0
UW		 1642 regcache_raw_read_unsigned
1643 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1644 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
91d8eb23 1645 callsize = extract_call_winsize (gdbarch, pc);
ca3bf3bd 1646
bdb4c075
MG		 1647 if (len > (callsize > 8 ? 8 : 16))
1648 internal_error (__FILE__, __LINE__,
1649 _("unimplemented for this length: %d"),
1650 TYPE_LENGTH (type));
ee967b5f
MG		 1651 areg = arreg_number (gdbarch,
1652 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
ca3bf3bd 1653
bdb4c075 1654 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
ca3bf3bd 1655 callsize, (int) wb);
bdb4c075
MG		 1656 }
1657 else
1658 {
94a0e877 1659 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
bdb4c075 1660 }
ca3bf3bd 1661
6b50c0b0 1662 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
ca3bf3bd
DJ		 1663 offset = 4 - len;
1664
ca3bf3bd
DJ		 1665 for (; len > 0; len -= 4, areg++, valbuf += 4)
1666 {
1667 if (len < 4)
1668 regcache_raw_write_part (regcache, areg, offset, len, valbuf);
1669 else
1670 regcache_raw_write (regcache, areg, valbuf);
1671 }
1672}
1673
1674
bdb4c075 1675static enum return_value_convention
ca3bf3bd 1676xtensa_return_value (struct gdbarch *gdbarch,
c055b101 1677 struct type *func_type,
ca3bf3bd
DJ		 1678 struct type *valtype,
1679 struct regcache *regcache,
1680 gdb_byte *readbuf,
1681 const gdb_byte *writebuf)
1682{
bdb4c075 1683 /* Structures up to 16 bytes are returned in registers. */
ca3bf3bd
DJ		 1684
1685 int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1686 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1687 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1688 && TYPE_LENGTH (valtype) > 16);
1689
1690 if (struct_return)
1691 return RETURN_VALUE_STRUCT_CONVENTION;
1692
1693 DEBUGTRACE ("xtensa_return_value(...)\n");
1694
1695 if (writebuf != NULL)
1696 {
1697 xtensa_store_return_value (valtype, regcache, writebuf);
1698 }
1699
1700 if (readbuf != NULL)
1701 {
1702 gdb_assert (!struct_return);
1703 xtensa_extract_return_value (valtype, regcache, readbuf);
1704 }
1705 return RETURN_VALUE_REGISTER_CONVENTION;
1706}
1707
1708
1709/* DUMMY FRAME */
1710
1711static CORE_ADDR
1712xtensa_push_dummy_call (struct gdbarch *gdbarch,
1713 struct value *function,
1714 struct regcache *regcache,
1715 CORE_ADDR bp_addr,
1716 int nargs,
1717 struct value **args,
1718 CORE_ADDR sp,
1719 int struct_return,
1720 CORE_ADDR struct_addr)
1721{
e17a4113 1722 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
ca3bf3bd
DJ		 1723 int i;
1724 int size, onstack_size;
ff7a4c00 1725 gdb_byte *buf = (gdb_byte *) alloca (16);
ca3bf3bd
DJ		 1726 CORE_ADDR ra, ps;
1727 struct argument_info
1728 {
1729 const bfd_byte *contents;
1730 int length;
1731 int onstack; /* onstack == 0 => in reg */
1732 int align; /* alignment */
1733 union
1734 {
581e13c1
MS		 1735 int offset; /* stack offset if on stack. */
1736 int regno; /* regno if in register. */
ca3bf3bd
DJ		 1737 } u;
1738 };
1739
1740 struct argument_info *arg_info =
1741 (struct argument_info *) alloca (nargs * sizeof (struct argument_info));
1742
1743 CORE_ADDR osp = sp;
1744
1745 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1746
1747 if (xtensa_debug_level > 3)
1748 {
1749 int i;
1750 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs);
1751 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1752 "struct_addr=0x%x\n",
1753 (int) sp, (int) struct_return, (int) struct_addr);
1754
1755 for (i = 0; i < nargs; i++)
1756 {
1757 struct value *arg = args[i];
1758 struct type *arg_type = check_typedef (value_type (arg));
3329c4b5
PM		 1759 fprintf_unfiltered (gdb_stdlog, "%2d: %s %3d ", i,
1760 host_address_to_string (arg),
1761 TYPE_LENGTH (arg_type));
ca3bf3bd
DJ		 1762 switch (TYPE_CODE (arg_type))
1763 {
1764 case TYPE_CODE_INT:
1765 fprintf_unfiltered (gdb_stdlog, "int");
1766 break;
1767 case TYPE_CODE_STRUCT:
1768 fprintf_unfiltered (gdb_stdlog, "struct");
1769 break;
1770 default:
1771 fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type));
1772 break;
1773 }
3329c4b5
PM		 1774 fprintf_unfiltered (gdb_stdlog, " %s\n",
1775 host_address_to_string (value_contents (arg)));
ca3bf3bd
DJ		 1776 }
1777 }
1778
1779 /* First loop: collect information.
1780 Cast into type_long. (This shouldn't happen often for C because
1781 GDB already does this earlier.) It's possible that GDB could
1782 do it all the time but it's harmless to leave this code here. */
1783
1784 size = 0;
1785 onstack_size = 0;
1786 i = 0;
1787
1788 if (struct_return)
1789 size = REGISTER_SIZE;
1790
1791 for (i = 0; i < nargs; i++)
1792 {
1793 struct argument_info *info = &arg_info[i];
1794 struct value *arg = args[i];
1795 struct type *arg_type = check_typedef (value_type (arg));
1796
1797 switch (TYPE_CODE (arg_type))
1798 {
1799 case TYPE_CODE_INT:
1800 case TYPE_CODE_BOOL:
1801 case TYPE_CODE_CHAR:
1802 case TYPE_CODE_RANGE:
1803 case TYPE_CODE_ENUM:
1804
1805 /* Cast argument to long if necessary as the mask does it too. */
0dfff4cb
UW		 1806 if (TYPE_LENGTH (arg_type)
1807 < TYPE_LENGTH (builtin_type (gdbarch)->builtin_long))
ca3bf3bd 1808 {
0dfff4cb 1809 arg_type = builtin_type (gdbarch)->builtin_long;
ca3bf3bd
DJ		 1810 arg = value_cast (arg_type, arg);
1811 }
bdb4c075
MG		 1812 /* Aligment is equal to the type length for the basic types. */
1813 info->align = TYPE_LENGTH (arg_type);
ca3bf3bd
DJ		 1814 break;
1815
1816 case TYPE_CODE_FLT:
1817
1818 /* Align doubles correctly. */
0dfff4cb
UW		 1819 if (TYPE_LENGTH (arg_type)
1820 == TYPE_LENGTH (builtin_type (gdbarch)->builtin_double))
1821 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_double);
ca3bf3bd 1822 else
0dfff4cb 1823 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long);
ca3bf3bd
DJ		 1824 break;
1825
1826 case TYPE_CODE_STRUCT:
1827 default:
0dfff4cb 1828 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long);
ca3bf3bd
DJ		 1829 break;
1830 }
1831 info->length = TYPE_LENGTH (arg_type);
1832 info->contents = value_contents (arg);
1833
1834 /* Align size and onstack_size. */
1835 size = (size + info->align - 1) & ~(info->align - 1);
1836 onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1);
1837
91d8eb23 1838 if (size + info->length > REGISTER_SIZE * ARG_NOF (gdbarch))
ca3bf3bd
DJ		 1839 {
1840 info->onstack = 1;
1841 info->u.offset = onstack_size;
1842 onstack_size += info->length;
1843 }
1844 else
1845 {
1846 info->onstack = 0;
91d8eb23 1847 info->u.regno = ARG_1ST (gdbarch) + size / REGISTER_SIZE;
ca3bf3bd
DJ		 1848 }
1849 size += info->length;
1850 }
1851
1852 /* Adjust the stack pointer and align it. */
1853 sp = align_down (sp - onstack_size, SP_ALIGNMENT);
1854
bdb4c075 1855 /* Simulate MOVSP, if Windowed ABI. */
6b50c0b0 1856 if ((gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
304fe255 1857 && (sp != osp))
ca3bf3bd
DJ		 1858 {
1859 read_memory (osp - 16, buf, 16);
1860 write_memory (sp - 16, buf, 16);
1861 }
1862
1863 /* Second Loop: Load arguments. */
1864
1865 if (struct_return)
1866 {
e17a4113 1867 store_unsigned_integer (buf, REGISTER_SIZE, byte_order, struct_addr);
91d8eb23 1868 regcache_cooked_write (regcache, ARG_1ST (gdbarch), buf);
ca3bf3bd
DJ		 1869 }
1870
1871 for (i = 0; i < nargs; i++)
1872 {
1873 struct argument_info *info = &arg_info[i];
1874
1875 if (info->onstack)
1876 {
1877 int n = info->length;
1878 CORE_ADDR offset = sp + info->u.offset;
1879
1880 /* Odd-sized structs are aligned to the lower side of a memory
1881 word in big-endian mode and require a shift. This only
1882 applies for structures smaller than one word. */
1883
4c6b5505 1884 if (n < REGISTER_SIZE
6b50c0b0 1885 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
ca3bf3bd
DJ		 1886 offset += (REGISTER_SIZE - n);
1887
1888 write_memory (offset, info->contents, info->length);
1889
1890 }
1891 else
1892 {
1893 int n = info->length;
1894 const bfd_byte *cp = info->contents;
1895 int r = info->u.regno;
1896
1897 /* Odd-sized structs are aligned to the lower side of registers in
1898 big-endian mode and require a shift. The odd-sized leftover will
1899 be at the end. Note that this is only true for structures smaller
1900 than REGISTER_SIZE; for larger odd-sized structures the excess
1901 will be left-aligned in the register on both endiannesses. */
1902
e17a4113 1903 if (n < REGISTER_SIZE && byte_order == BFD_ENDIAN_BIG)
ca3bf3bd 1904 {
e17a4113
UW		 1905 ULONGEST v;
1906 v = extract_unsigned_integer (cp, REGISTER_SIZE, byte_order);
ca3bf3bd
DJ		 1907 v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT);
1908
e17a4113 1909 store_unsigned_integer (buf, REGISTER_SIZE, byte_order, v);
ca3bf3bd
DJ		 1910 regcache_cooked_write (regcache, r, buf);
1911
1912 cp += REGISTER_SIZE;
1913 n -= REGISTER_SIZE;
1914 r++;
1915 }
1916 else
1917 while (n > 0)
1918 {
ca3bf3bd
DJ		 1919 regcache_cooked_write (regcache, r, cp);
1920
ca3bf3bd
DJ		 1921 cp += REGISTER_SIZE;
1922 n -= REGISTER_SIZE;
1923 r++;
1924 }
1925 }
1926 }
1927
ca3bf3bd 1928 /* Set the return address of dummy frame to the dummy address.
bdb4c075 1929 The return address for the current function (in A0) is
ca3bf3bd
DJ		 1930 saved in the dummy frame, so we can savely overwrite A0 here. */
1931
6b50c0b0 1932 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
bdb4c075 1933 {
98689b25 1934 ULONGEST val;
68d6df83 1935
bdb4c075 1936 ra = (bp_addr & 0x3fffffff) | 0x40000000;
98689b25
MG		 1937 regcache_raw_read_unsigned (regcache, gdbarch_ps_regnum (gdbarch), &val);
1938 ps = (unsigned long) val & ~0x00030000;
304fe255 1939 regcache_cooked_write_unsigned
6b50c0b0 1940 (regcache, gdbarch_tdep (gdbarch)->a0_base + 4, ra);
bdb4c075 1941 regcache_cooked_write_unsigned (regcache,
6b50c0b0 1942 gdbarch_ps_regnum (gdbarch),
bdb4c075 1943 ps | 0x00010000);
94a0e877
MG		 1944
1945 /* All the registers have been saved. After executing
1946 dummy call, they all will be restored. So it's safe
1947 to modify WINDOWSTART register to make it look like there
1948 is only one register window corresponding to WINDOWEBASE. */
1949
1950 regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
e17a4113
UW		 1951 regcache_cooked_write_unsigned
1952 (regcache, gdbarch_tdep (gdbarch)->ws_regnum,
1953 1 << extract_unsigned_integer (buf, 4, byte_order));
bdb4c075
MG		 1954 }
1955 else
1956 {
1957 /* Simulate CALL0: write RA into A0 register. */
304fe255 1958 regcache_cooked_write_unsigned
94a0e877 1959 (regcache, gdbarch_tdep (gdbarch)->a0_base, bp_addr);
bdb4c075 1960 }
ca3bf3bd
DJ		 1961
1962 /* Set new stack pointer and return it. */
304fe255 1963 regcache_cooked_write_unsigned (regcache,
6b50c0b0 1964 gdbarch_tdep (gdbarch)->a0_base + 1, sp);
ca3bf3bd
DJ		 1965 /* Make dummy frame ID unique by adding a constant. */
1966 return sp + SP_ALIGNMENT;
1967}
1968
1969
1970/* Return a breakpoint for the current location of PC. We always use
1971 the density version if we have density instructions (regardless of the
1972 current instruction at PC), and use regular instructions otherwise. */
1973
1974#define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1975#define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1976#define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1977#define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1978
bdb4c075 1979static const unsigned char *
67d57894
MD		 1980xtensa_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
1981 int *lenptr)
ca3bf3bd 1982{
ff7a4c00
MG		 1983 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
1984 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
1985 static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT;
1986 static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT;
ca3bf3bd
DJ		 1987
1988 DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr);
1989
67d57894 1990 if (gdbarch_tdep (gdbarch)->isa_use_density_instructions)
ca3bf3bd 1991 {
67d57894 1992 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
ca3bf3bd
DJ		 1993 {
1994 *lenptr = sizeof (density_big_breakpoint);
1995 return density_big_breakpoint;
1996 }
1997 else
1998 {
1999 *lenptr = sizeof (density_little_breakpoint);
2000 return density_little_breakpoint;
2001 }
2002 }
2003 else
2004 {
67d57894 2005 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
ca3bf3bd
DJ		 2006 {
2007 *lenptr = sizeof (big_breakpoint);
2008 return big_breakpoint;
2009 }
2010 else
2011 {
2012 *lenptr = sizeof (little_breakpoint);
2013 return little_breakpoint;
2014 }
2015 }
2016}
2017
bdb4c075
MG		 2018/* Call0 ABI support routines. */
2019
f976a05d
MG		 2020/* Return true, if PC points to "ret" or "ret.n". */
2021
2022static int
2023call0_ret (CORE_ADDR start_pc, CORE_ADDR finish_pc)
2024{
2025#define RETURN_RET goto done
2026 xtensa_isa isa;
2027 xtensa_insnbuf ins, slot;
2028 char ibuf[XTENSA_ISA_BSZ];
2029 CORE_ADDR ia, bt, ba;
2030 xtensa_format ifmt;
2031 int ilen, islots, is;
2032 xtensa_opcode opc;
2033 const char *opcname;
2034 int found_ret = 0;
2035
2036 isa = xtensa_default_isa;
2037 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2038 ins = xtensa_insnbuf_alloc (isa);
2039 slot = xtensa_insnbuf_alloc (isa);
2040 ba = 0;
2041
2042 for (ia = start_pc, bt = ia; ia < finish_pc ; ia += ilen)
2043 {
2044 if (ia + xtensa_isa_maxlength (isa) > bt)
2045 {
2046 ba = ia;
2047 bt = (ba + XTENSA_ISA_BSZ) < finish_pc
2048 ? ba + XTENSA_ISA_BSZ : finish_pc;
2049 if (target_read_memory (ba, ibuf, bt - ba) != 0 )
2050 RETURN_RET;
2051 }
2052
2053 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2054 ifmt = xtensa_format_decode (isa, ins);
2055 if (ifmt == XTENSA_UNDEFINED)
2056 RETURN_RET;
2057 ilen = xtensa_format_length (isa, ifmt);
2058 if (ilen == XTENSA_UNDEFINED)
2059 RETURN_RET;
2060 islots = xtensa_format_num_slots (isa, ifmt);
2061 if (islots == XTENSA_UNDEFINED)
2062 RETURN_RET;
2063
2064 for (is = 0; is < islots; ++is)
2065 {
2066 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
2067 RETURN_RET;
2068
2069 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2070 if (opc == XTENSA_UNDEFINED)
2071 RETURN_RET;
2072
2073 opcname = xtensa_opcode_name (isa, opc);
2074
2075 if ((strcasecmp (opcname, "ret.n") == 0)
2076 || (strcasecmp (opcname, "ret") == 0))
2077 {
2078 found_ret = 1;
2079 RETURN_RET;
2080 }
2081 }
2082 }
2083 done:
2084 xtensa_insnbuf_free(isa, slot);
2085 xtensa_insnbuf_free(isa, ins);
2086 return found_ret;
2087}
2088
bdb4c075
MG		 2089/* Call0 opcode class. Opcodes are preclassified according to what they
2090 mean for Call0 prologue analysis, and their number of significant operands.
2091 The purpose of this is to simplify prologue analysis by separating
2092 instruction decoding (libisa) from the semantics of prologue analysis. */
2093
68d6df83
MG		 2094typedef enum
2095{
bdb4c075
MG		 2096 c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */
2097 c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */
2098 c0opc_flow, /* Flow control insn. */
2099 c0opc_entry, /* ENTRY indicates non-Call0 prologue. */
2100 c0opc_break, /* Debugger software breakpoints. */
2101 c0opc_add, /* Adding two registers. */
2102 c0opc_addi, /* Adding a register and an immediate. */
dbab50de 2103 c0opc_and, /* Bitwise "and"-ing two registers. */
bdb4c075
MG		 2104 c0opc_sub, /* Subtracting a register from a register. */
2105 c0opc_mov, /* Moving a register to a register. */
2106 c0opc_movi, /* Moving an immediate to a register. */
2107 c0opc_l32r, /* Loading a literal. */
08b9c608
MG		 2108 c0opc_s32i, /* Storing word at fixed offset from a base register. */
2109 c0opc_rwxsr, /* RSR, WRS, or XSR instructions. */
2110 c0opc_l32e, /* L32E instruction. */
2111 c0opc_s32e, /* S32E instruction. */
2112 c0opc_rfwo, /* RFWO instruction. */
2113 c0opc_rfwu, /* RFWU instruction. */
bdb4c075
MG		 2114 c0opc_NrOf /* Number of opcode classifications. */
2115} xtensa_insn_kind;
2116
08b9c608
MG		 2117/* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */
2118
2119static int
2120rwx_special_register (const char *opcname)
2121{
2122 char ch = *opcname++;
2123
2124 if ((ch != 'r') && (ch != 'w') && (ch != 'x'))
2125 return 0;
2126 if (*opcname++ != 's')
2127 return 0;
2128 if (*opcname++ != 'r')
2129 return 0;
2130 if (*opcname++ != '.')
2131 return 0;
2132
2133 return 1;
2134}
bdb4c075
MG		 2135
2136/* Classify an opcode based on what it means for Call0 prologue analysis. */
2137
2138static xtensa_insn_kind
2139call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc)
2140{
2141 const char *opcname;
2142 xtensa_insn_kind opclass = c0opc_uninteresting;
2143
2144 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc);
2145
2146 /* Get opcode name and handle special classifications. */
2147
2148 opcname = xtensa_opcode_name (isa, opc);
2149
2150 if (opcname == NULL
2151 || strcasecmp (opcname, "ill") == 0
2152 || strcasecmp (opcname, "ill.n") == 0)
2153 opclass = c0opc_illegal;
2154 else if (strcasecmp (opcname, "break") == 0
2155 || strcasecmp (opcname, "break.n") == 0)
2156 opclass = c0opc_break;
2157 else if (strcasecmp (opcname, "entry") == 0)
2158 opclass = c0opc_entry;
08b9c608
MG		 2159 else if (strcasecmp (opcname, "rfwo") == 0)
2160 opclass = c0opc_rfwo;
2161 else if (strcasecmp (opcname, "rfwu") == 0)
2162 opclass = c0opc_rfwu;
bdb4c075
MG		 2163 else if (xtensa_opcode_is_branch (isa, opc) > 0
2164 || xtensa_opcode_is_jump (isa, opc) > 0
2165 || xtensa_opcode_is_loop (isa, opc) > 0
2166 || xtensa_opcode_is_call (isa, opc) > 0
2167 || strcasecmp (opcname, "simcall") == 0
2168 || strcasecmp (opcname, "syscall") == 0)
2169 opclass = c0opc_flow;
2170
2171 /* Also, classify specific opcodes that need to be tracked. */
2172 else if (strcasecmp (opcname, "add") == 0
2173 || strcasecmp (opcname, "add.n") == 0)
2174 opclass = c0opc_add;
dbab50de
MG		 2175 else if (strcasecmp (opcname, "and") == 0)
2176 opclass = c0opc_and;
bdb4c075
MG		 2177 else if (strcasecmp (opcname, "addi") == 0
2178 || strcasecmp (opcname, "addi.n") == 0
2179 || strcasecmp (opcname, "addmi") == 0)
2180 opclass = c0opc_addi;
2181 else if (strcasecmp (opcname, "sub") == 0)
2182 opclass = c0opc_sub;
2183 else if (strcasecmp (opcname, "mov.n") == 0
2184 || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */
2185 opclass = c0opc_mov;
2186 else if (strcasecmp (opcname, "movi") == 0
2187 || strcasecmp (opcname, "movi.n") == 0)
2188 opclass = c0opc_movi;
2189 else if (strcasecmp (opcname, "l32r") == 0)
2190 opclass = c0opc_l32r;
2191 else if (strcasecmp (opcname, "s32i") == 0
2192 || strcasecmp (opcname, "s32i.n") == 0)
2193 opclass = c0opc_s32i;
08b9c608
MG		 2194 else if (strcasecmp (opcname, "l32e") == 0)
2195 opclass = c0opc_l32e;
2196 else if (strcasecmp (opcname, "s32e") == 0)
2197 opclass = c0opc_s32e;
2198 else if (rwx_special_register (opcname))
2199 opclass = c0opc_rwxsr;
bdb4c075
MG		 2200
2201 return opclass;
2202}
2203
2204/* Tracks register movement/mutation for a given operation, which may
2205 be within a bundle. Updates the destination register tracking info
2206 accordingly. The pc is needed only for pc-relative load instructions
2207 (eg. l32r). The SP register number is needed to identify stores to
dbab50de
MG		 2208 the stack frame. Returns 0, if analysis was succesfull, non-zero
2209 otherwise. */
bdb4c075 2210
dbab50de
MG		 2211static int
2212call0_track_op (struct gdbarch *gdbarch, xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
bdb4c075 2213 xtensa_insn_kind opclass, int nods, unsigned odv[],
dbab50de 2214 CORE_ADDR pc, int spreg, xtensa_frame_cache_t *cache)
bdb4c075 2215{
e17a4113 2216 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
dbab50de 2217 unsigned litbase, litaddr, litval;
bdb4c075
MG		 2218
2219 switch (opclass)
2220 {
2221 case c0opc_addi:
2222 /* 3 operands: dst, src, imm. */
2223 gdb_assert (nods == 3);
2224 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2225 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2];
2226 break;
2227 case c0opc_add:
2228 /* 3 operands: dst, src1, src2. */
08b9c608 2229 gdb_assert (nods == 3);
bdb4c075
MG		 2230 if (src[odv[1]].fr_reg == C0_CONST)
2231 {
2232 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
2233 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs;
2234 }
2235 else if (src[odv[2]].fr_reg == C0_CONST)
2236 {
2237 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2238 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs;
2239 }
2240 else dst[odv[0]].fr_reg = C0_INEXP;
2241 break;
dbab50de
MG		 2242 case c0opc_and:
2243 /* 3 operands: dst, src1, src2. */
2244 gdb_assert (nods == 3);
2245 if (cache->c0.c0_fpalign == 0)
2246 {
2247 /* Handle dynamic stack alignment. */
2248 if ((src[odv[0]].fr_reg == spreg) && (src[odv[1]].fr_reg == spreg))
2249 {
2250 if (src[odv[2]].fr_reg == C0_CONST)
2251 cache->c0.c0_fpalign = src[odv[2]].fr_ofs;
2252 break;
2253 }
2254 else if ((src[odv[0]].fr_reg == spreg)
2255 && (src[odv[2]].fr_reg == spreg))
2256 {
2257 if (src[odv[1]].fr_reg == C0_CONST)
2258 cache->c0.c0_fpalign = src[odv[1]].fr_ofs;
2259 break;
2260 }
2261 /* else fall through. */
2262 }
2263 if (src[odv[1]].fr_reg == C0_CONST)
2264 {
2265 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
2266 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs & src[odv[1]].fr_ofs;
2267 }
2268 else if (src[odv[2]].fr_reg == C0_CONST)
2269 {
2270 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2271 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs & src[odv[2]].fr_ofs;
2272 }
2273 else dst[odv[0]].fr_reg = C0_INEXP;
2274 break;
bdb4c075
MG		 2275 case c0opc_sub:
2276 /* 3 operands: dst, src1, src2. */
2277 gdb_assert (nods == 3);
2278 if (src[odv[2]].fr_reg == C0_CONST)
2279 {
2280 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2281 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs;
2282 }
2283 else dst[odv[0]].fr_reg = C0_INEXP;
2284 break;
2285 case c0opc_mov:
2286 /* 2 operands: dst, src [, src]. */
2287 gdb_assert (nods == 2);
dbab50de
MG		 2288 /* First, check if it's a special case of saving unaligned SP
2289 to a spare register in case of dynamic stack adjustment.
2290 But, only do it one time. The second time could be initializing
2291 frame pointer. We don't want to overwrite the first one. */
2292 if ((odv[1] == spreg) && (cache->c0.c0_old_sp == C0_INEXP))
2293 cache->c0.c0_old_sp = odv[0];
2294
bdb4c075
MG		 2295 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2296 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs;
2297 break;
2298 case c0opc_movi:
2299 /* 2 operands: dst, imm. */
2300 gdb_assert (nods == 2);
2301 dst[odv[0]].fr_reg = C0_CONST;
2302 dst[odv[0]].fr_ofs = odv[1];
2303 break;
2304 case c0opc_l32r:
2305 /* 2 operands: dst, literal offset. */
2306 gdb_assert (nods == 2);
dbab50de
MG		 2307 /* litbase = xtensa_get_litbase (pc); can be also used. */
2308 litbase = (gdbarch_tdep (gdbarch)->litbase_regnum == -1)
2309 ? 0 : xtensa_read_register
2310 (gdbarch_tdep (gdbarch)->litbase_regnum);
bdb4c075
MG		 2311 litaddr = litbase & 1
2312 ? (litbase & ~1) + (signed)odv[1]
2313 : (pc + 3 + (signed)odv[1]) & ~3;
e17a4113 2314 litval = read_memory_integer (litaddr, 4, byte_order);
bdb4c075
MG		 2315 dst[odv[0]].fr_reg = C0_CONST;
2316 dst[odv[0]].fr_ofs = litval;
2317 break;
2318 case c0opc_s32i:
2319 /* 3 operands: value, base, offset. */
2320 gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS);
dbab50de
MG		 2321 /* First, check if it's a spill for saved unaligned SP,
2322 when dynamic stack adjustment was applied to this frame. */
2323 if ((cache->c0.c0_fpalign != 0) /* Dynamic stack adjustment. */
2324 && (odv[1] == spreg) /* SP usage indicates spill. */
2325 && (odv[0] == cache->c0.c0_old_sp)) /* Old SP register spilled. */
2326 cache->c0.c0_sp_ofs = odv[2];
2327
bdb4c075
MG		 2328 if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */
2329 && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */
2330 && src[odv[0]].fr_reg >= 0 /* Value is from a register. */
2331 && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */
2332 && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */
2333 {
2334 /* ISA encoding guarantees alignment. But, check it anyway. */
2335 gdb_assert ((odv[2] & 3) == 0);
2336 dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2];
2337 }
2338 break;
dbab50de
MG		 2339 /* If we end up inside Window Overflow / Underflow interrupt handler
2340 report an error because these handlers should have been handled
2341 already in a different way. */
2342 case c0opc_l32e:
2343 case c0opc_s32e:
2344 case c0opc_rfwo:
2345 case c0opc_rfwu:
2346 return 1;
bdb4c075 2347 default:
dbab50de 2348 return 1;
bdb4c075 2349 }
dbab50de 2350 return 0;
bdb4c075
MG		 2351}
2352
dbab50de 2353/* Analyze prologue of the function at start address to determine if it uses
bdb4c075 2354 the Call0 ABI, and if so track register moves and linear modifications
dbab50de
MG		 2355 in the prologue up to the PC or just beyond the prologue, whichever is
2356 first. An 'entry' instruction indicates non-Call0 ABI and the end of the
2357 prologue. The prologue may overlap non-prologue instructions but is
2358 guaranteed to end by the first flow-control instruction (jump, branch,
2359 call or return). Since an optimized function may move information around
2360 and change the stack frame arbitrarily during the prologue, the information
2361 is guaranteed valid only at the point in the function indicated by the PC.
bdb4c075
MG		 2362 May be used to skip the prologue or identify the ABI, w/o tracking.
2363
2364 Returns: Address of first instruction after prologue, or PC (whichever
2365 is first), or 0, if decoding failed (in libisa).
2366 Input args:
2367 start Start address of function/prologue.
2368 pc Program counter to stop at. Use 0 to continue to end of prologue.
2369 If 0, avoids infinite run-on in corrupt code memory by bounding
2370 the scan to the end of the function if that can be determined.
dbab50de 2371 nregs Number of general registers to track.
bdb4c075 2372 InOut args:
dbab50de 2373 cache Xtensa frame cache.
bdb4c075
MG		 2374
2375 Note that these may produce useful results even if decoding fails
2376 because they begin with default assumptions that analysis may change. */
2377
2378static CORE_ADDR
e17a4113 2379call0_analyze_prologue (struct gdbarch *gdbarch,
dbab50de
MG		 2380 CORE_ADDR start, CORE_ADDR pc,
2381 int nregs, xtensa_frame_cache_t *cache)
bdb4c075
MG		 2382{
2383 CORE_ADDR ia; /* Current insn address in prologue. */
2384 CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
2385 CORE_ADDR bt; /* Current address at top+1 of insn buffer. */
2ff5e605 2386 char ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue. */
bdb4c075
MG		 2387 xtensa_isa isa; /* libisa ISA handle. */
2388 xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */
2389 xtensa_format ifmt; /* libisa instruction format. */
2390 int ilen, islots, is; /* Instruction length, nbr slots, current slot. */
2391 xtensa_opcode opc; /* Opcode in current slot. */
2392 xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */
2393 int nods; /* Opcode number of operands. */
2394 unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */
2395 xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */
2396 int j; /* General loop counter. */
2397 int fail = 0; /* Set non-zero and exit, if decoding fails. */
2398 CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */
2399 CORE_ADDR end_pc; /* The PC for the lust function insn. */
2400
2401 struct symtab_and_line prologue_sal;
2402
2403 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2404 (int)start, (int)pc);
2405
2406 /* Try to limit the scan to the end of the function if a non-zero pc
2407 arg was not supplied to avoid probing beyond the end of valid memory.
2408 If memory is full of garbage that classifies as c0opc_uninteresting.
2409 If this fails (eg. if no symbols) pc ends up 0 as it was.
2410 Intialize the Call0 frame and register tracking info.
2411 Assume it's Call0 until an 'entry' instruction is encountered.
2412 Assume we may be in the prologue until we hit a flow control instr. */
2413
2414 rtmp = NULL;
8179e739 2415 body_pc = UINT_MAX;
bdb4c075
MG		 2416 end_pc = 0;
2417
2418 /* Find out, if we have an information about the prologue from DWARF. */
2419 prologue_sal = find_pc_line (start, 0);
2420 if (prologue_sal.line != 0) /* Found debug info. */
2421 body_pc = prologue_sal.end;
2422
2423 /* If we are going to analyze the prologue in general without knowing about
2424 the current PC, make the best assumtion for the end of the prologue. */
2425 if (pc == 0)
2426 {
2427 find_pc_partial_function (start, 0, NULL, &end_pc);
2428 body_pc = min (end_pc, body_pc);
2429 }
2430 else
2431 body_pc = min (pc, body_pc);
2432
dbab50de
MG		 2433 cache->call0 = 1;
2434 rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t));
bdb4c075 2435
94a0e877
MG		 2436 if (!xtensa_default_isa)
2437 xtensa_default_isa = xtensa_isa_init (0, 0);
bdb4c075 2438 isa = xtensa_default_isa;
2ff5e605 2439 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
bdb4c075
MG		 2440 ins = xtensa_insnbuf_alloc (isa);
2441 slot = xtensa_insnbuf_alloc (isa);
2442
2443 for (ia = start, bt = ia; ia < body_pc ; ia += ilen)
2444 {
2445 /* (Re)fill instruction buffer from memory if necessary, but do not
2446 read memory beyond PC to be sure we stay within text section
2447 (this protection only works if a non-zero pc is supplied). */
2448
2449 if (ia + xtensa_isa_maxlength (isa) > bt)
2450 {
2451 ba = ia;
2ff5e605 2452 bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ : body_pc;
dbab50de
MG		 2453 if (target_read_memory (ba, ibuf, bt - ba) != 0 )
2454 error (_("Unable to read target memory ..."));
bdb4c075
MG		 2455 }
2456
2457 /* Decode format information. */
2458
2459 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2460 ifmt = xtensa_format_decode (isa, ins);
2461 if (ifmt == XTENSA_UNDEFINED)
2462 {
2463 fail = 1;
2464 goto done;
2465 }
2466 ilen = xtensa_format_length (isa, ifmt);
2467 if (ilen == XTENSA_UNDEFINED)
2468 {
2469 fail = 1;
2470 goto done;
2471 }
2472 islots = xtensa_format_num_slots (isa, ifmt);
2473 if (islots == XTENSA_UNDEFINED)
2474 {
2475 fail = 1;
2476 goto done;
2477 }
2478
2479 /* Analyze a bundle or a single instruction, using a snapshot of
2480 the register tracking info as input for the entire bundle so that
2481 register changes do not take effect within this bundle. */
ca3bf3bd 2482
bdb4c075 2483 for (j = 0; j < nregs; ++j)
dbab50de 2484 rtmp[j] = cache->c0.c0_rt[j];
bdb4c075
MG		 2485
2486 for (is = 0; is < islots; ++is)
2487 {
2488 /* Decode a slot and classify the opcode. */
2489
2490 fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot);
2491 if (fail)
2492 goto done;
2493
2494 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
dbab50de 2495 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
bdb4c075
MG		 2496 (unsigned)ia, opc);
2497 if (opc == XTENSA_UNDEFINED)
2498 opclass = c0opc_illegal;
2499 else
2500 opclass = call0_classify_opcode (isa, opc);
2501
2502 /* Decide whether to track this opcode, ignore it, or bail out. */
2503
2504 switch (opclass)
2505 {
2506 case c0opc_illegal:
2507 case c0opc_break:
2508 fail = 1;
2509 goto done;
2510
2511 case c0opc_uninteresting:
2512 continue;
2513
dbab50de
MG		 2514 case c0opc_flow: /* Flow control instructions stop analysis. */
2515 case c0opc_rwxsr: /* RSR, WSR, XSR instructions stop analysis. */
bdb4c075
MG		 2516 goto done;
2517
2518 case c0opc_entry:
dbab50de 2519 cache->call0 = 0;
bdb4c075
MG		 2520 ia += ilen; /* Skip over 'entry' insn. */
2521 goto done;
2522
2523 default:
dbab50de 2524 cache->call0 = 1;
bdb4c075
MG		 2525 }
2526
2527 /* Only expected opcodes should get this far. */
bdb4c075
MG		 2528
2529 /* Extract and decode the operands. */
2530 nods = xtensa_opcode_num_operands (isa, opc);
2531 if (nods == XTENSA_UNDEFINED)
2532 {
2533 fail = 1;
2534 goto done;
2535 }
2536
2537 for (j = 0; j < nods && j < C0_MAXOPDS; ++j)
2538 {
2539 fail = xtensa_operand_get_field (isa, opc, j, ifmt,
2540 is, slot, &odv[j]);
2541 if (fail)
2542 goto done;
2543
2544 fail = xtensa_operand_decode (isa, opc, j, &odv[j]);
2545 if (fail)
2546 goto done;
2547 }
2548
2549 /* Check operands to verify use of 'mov' assembler macro. */
2550 if (opclass == c0opc_mov && nods == 3)
2551 {
2552 if (odv[2] == odv[1])
dbab50de
MG		 2553 {
2554 nods = 2;
2555 if ((odv[0] == 1) && (odv[1] != 1))
2556 /* OR A1, An, An , where n != 1.
2557 This means we are inside epilogue already. */
2558 goto done;
2559 }
bdb4c075
MG		 2560 else
2561 {
2562 opclass = c0opc_uninteresting;
2563 continue;
2564 }
2565 }
2566
2567 /* Track register movement and modification for this operation. */
dbab50de
MG		 2568 fail = call0_track_op (gdbarch, cache->c0.c0_rt, rtmp,
2569 opclass, nods, odv, ia, 1, cache);
2570 if (fail)
2571 goto done;
bdb4c075
MG		 2572 }
2573 }
2574done:
2575 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2576 (unsigned)ia, fail ? "failed" : "succeeded");
2577 xtensa_insnbuf_free(isa, slot);
2578 xtensa_insnbuf_free(isa, ins);
d4709618 2579 return fail ? XTENSA_ISA_BADPC : ia;
bdb4c075
MG		 2580}
2581
5142f611 2582/* Initialize frame cache for the current frame in CALL0 ABI. */
bdb4c075
MG		 2583
2584static void
5142f611 2585call0_frame_cache (struct frame_info *this_frame,
dbab50de 2586 xtensa_frame_cache_t *cache, CORE_ADDR pc)
bdb4c075 2587{
5142f611 2588 struct gdbarch *gdbarch = get_frame_arch (this_frame);
e17a4113 2589 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
bdb4c075
MG		 2590 CORE_ADDR start_pc; /* The beginning of the function. */
2591 CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */
2592 CORE_ADDR sp, fp, ra;
dbab50de 2593 int fp_regnum = C0_SP, c0_hasfp = 0, c0_frmsz = 0, prev_sp = 0, to_stk;
bdb4c075 2594
dbab50de
MG		 2595 sp = get_frame_register_unsigned
2596 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
2597 fp = sp; /* Assume FP == SP until proven otherwise. */
2598
bdb4c075
MG		 2599 /* Find the beginning of the prologue of the function containing the PC
2600 and analyze it up to the PC or the end of the prologue. */
2601
2602 if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
2603 {
dbab50de 2604 body_pc = call0_analyze_prologue (gdbarch, start_pc, pc, C0_NREGS, cache);
d4709618
MG		 2605
2606 if (body_pc == XTENSA_ISA_BADPC)
dbab50de
MG		 2607 {
2608 warning_once ();
2609 ra = 0;
2610 goto finish_frame_analysis;
2611 }
bdb4c075
MG		 2612 }
2613
bdb4c075
MG		 2614 /* Get the frame information and FP (if used) at the current PC.
2615 If PC is in the prologue, the prologue analysis is more reliable
dbab50de
MG		 2616 than DWARF info. We don't not know for sure, if PC is in the prologue,
2617 but we do know no calls have yet taken place, so we can almost
bdb4c075
MG		 2618 certainly rely on the prologue analysis. */
2619
2620 if (body_pc <= pc)
2621 {
2622 /* Prologue analysis was successful up to the PC.
2623 It includes the cases when PC == START_PC. */
2624 c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP;
2625 /* c0_hasfp == true means there is a frame pointer because
2626 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2627 was derived from SP. Otherwise, it would be C0_FP. */
2628 fp_regnum = c0_hasfp ? C0_FP : C0_SP;
2629 c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs;
6b50c0b0 2630 fp_regnum += gdbarch_tdep (gdbarch)->a0_base;
bdb4c075
MG		 2631 }
2632 else /* No data from the prologue analysis. */
2633 {
2634 c0_hasfp = 0;
6b50c0b0 2635 fp_regnum = gdbarch_tdep (gdbarch)->a0_base + C0_SP;
bdb4c075
MG		 2636 c0_frmsz = 0;
2637 start_pc = pc;
2638 }
2639
dbab50de
MG		 2640 if (cache->c0.c0_fpalign)
2641 {
2642 /* This frame has a special prologue with a dynamic stack adjustment
2643 to force an alignment, which is bigger than standard 16 bytes. */
2644
2645 CORE_ADDR unaligned_sp;
2646
2647 if (cache->c0.c0_old_sp == C0_INEXP)
2648 /* This can't be. Prologue code should be consistent.
2649 Unaligned stack pointer should be saved in a spare register. */
2650 {
2651 warning_once ();
2652 ra = 0;
2653 goto finish_frame_analysis;
2654 }
2655
2656 if (cache->c0.c0_sp_ofs == C0_NOSTK)
2657 /* Saved unaligned value of SP is kept in a register. */
2658 unaligned_sp = get_frame_register_unsigned
2659 (this_frame, gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_old_sp);
2660 else
2661 /* Get the value from stack. */
2662 unaligned_sp = (CORE_ADDR)
2663 read_memory_integer (fp + cache->c0.c0_sp_ofs, 4, byte_order);
2664
2665 prev_sp = unaligned_sp + c0_frmsz;
2666 }
2667 else
2668 prev_sp = fp + c0_frmsz;
bdb4c075
MG		 2669
2670 /* Frame size from debug info or prologue tracking does not account for
2671 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2672 if (c0_hasfp)
2673 {
5142f611 2674 fp = get_frame_register_unsigned (this_frame, fp_regnum);
bdb4c075 2675
bdb4c075
MG		 2676 /* Update the stack frame size. */
2677 c0_frmsz += fp - sp;
2678 }
2679
2680 /* Get the return address (RA) from the stack if saved,
2681 or try to get it from a register. */
2682
2683 to_stk = cache->c0.c0_rt[C0_RA].to_stk;
2684 if (to_stk != C0_NOSTK)
2685 ra = (CORE_ADDR)
e17a4113
UW		 2686 read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk,
2687 4, byte_order);
bdb4c075
MG		 2688
2689 else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST
2690 && cache->c0.c0_rt[C0_RA].fr_ofs == 0)
2691 {
dbab50de
MG		 2692 /* Special case for terminating backtrace at a function that wants to
2693 be seen as the outermost one. Such a function will clear it's RA (A0)
2694 register to 0 in the prologue instead of saving its original value. */
bdb4c075
MG		 2695 ra = 0;
2696 }
2697 else
2698 {
dbab50de
MG		 2699 /* RA was copied to another register or (before any function call) may
2700 still be in the original RA register. This is not always reliable:
2701 even in a leaf function, register tracking stops after prologue, and
2702 even in prologue, non-prologue instructions (not tracked) may overwrite
2703 RA or any register it was copied to. If likely in prologue or before
2704 any call, use retracking info and hope for the best (compiler should
2705 have saved RA in stack if not in a leaf function). If not in prologue,
2706 too bad. */
bdb4c075
MG		 2707
2708 int i;
2709 for (i = 0;
2710 (i < C0_NREGS) &&
2711 (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA);
2712 ++i);
2713 if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA)
2714 i = C0_RA;
5142f611 2715 if (i < C0_NREGS)
bdb4c075 2716 {
5142f611
MG		 2717 ra = get_frame_register_unsigned
2718 (this_frame,
2719 gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_rt[i].fr_reg);
bdb4c075
MG		 2720 }
2721 else ra = 0;
2722 }
2723
dbab50de 2724 finish_frame_analysis:
bdb4c075
MG		 2725 cache->pc = start_pc;
2726 cache->ra = ra;
2727 /* RA == 0 marks the outermost frame. Do not go past it. */
2728 cache->prev_sp = (ra != 0) ? prev_sp : 0;
2729 cache->c0.fp_regnum = fp_regnum;
2730 cache->c0.c0_frmsz = c0_frmsz;
2731 cache->c0.c0_hasfp = c0_hasfp;
2732 cache->c0.c0_fp = fp;
2733}
2734
08b9c608
MG		 2735static CORE_ADDR a0_saved;
2736static CORE_ADDR a7_saved;
2737static CORE_ADDR a11_saved;
2738static int a0_was_saved;
2739static int a7_was_saved;
2740static int a11_was_saved;
2741
68d6df83 2742/* Simulate L32E instruction: AT <-- ref (AS + offset). */
08b9c608
MG		 2743static void
2744execute_l32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
2745{
2746 int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb);
2747 int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb);
2748 CORE_ADDR addr = xtensa_read_register (asreg) + offset;
2749 unsigned int spilled_value
2750 = read_memory_unsigned_integer (addr, 4, gdbarch_byte_order (gdbarch));
2751
2752 if ((at == 0) && !a0_was_saved)
2753 {
2754 a0_saved = xtensa_read_register (atreg);
2755 a0_was_saved = 1;
2756 }
2757 else if ((at == 7) && !a7_was_saved)
2758 {
2759 a7_saved = xtensa_read_register (atreg);
2760 a7_was_saved = 1;
2761 }
2762 else if ((at == 11) && !a11_was_saved)
2763 {
2764 a11_saved = xtensa_read_register (atreg);
2765 a11_was_saved = 1;
2766 }
2767
2768 xtensa_write_register (atreg, spilled_value);
2769}
2770
68d6df83 2771/* Simulate S32E instruction: AT --> ref (AS + offset). */
08b9c608
MG		 2772static void
2773execute_s32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
2774{
2775 int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb);
2776 int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb);
2777 CORE_ADDR addr = xtensa_read_register (asreg) + offset;
2778 ULONGEST spilled_value = xtensa_read_register (atreg);
2779
2780 write_memory_unsigned_integer (addr, 4,
2781 gdbarch_byte_order (gdbarch),
2782 spilled_value);
2783}
2784
2785#define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200
2786
68d6df83
MG		 2787typedef enum
2788{
08b9c608
MG		 2789 xtWindowOverflow,
2790 xtWindowUnderflow,
2791 xtNoExceptionHandler
2792} xtensa_exception_handler_t;
2793
68d6df83 2794/* Execute instruction stream from current PC until hitting RFWU or RFWO.
08b9c608
MG		 2795 Return type of Xtensa Window Interrupt Handler on success. */
2796static xtensa_exception_handler_t
2797execute_code (struct gdbarch *gdbarch, CORE_ADDR current_pc, CORE_ADDR wb)
2798{
2799 xtensa_isa isa;
2800 xtensa_insnbuf ins, slot;
2801 char ibuf[XTENSA_ISA_BSZ];
2802 CORE_ADDR ia, bt, ba;
2803 xtensa_format ifmt;
2804 int ilen, islots, is;
2805 xtensa_opcode opc;
2806 int insn_num = 0;
2807 int fail = 0;
2808 void (*func) (struct gdbarch *, int, int, int, CORE_ADDR);
2809
2810 int at, as, offset;
2811 int num_operands;
2812
2813 /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */
2814 int WindowUnderflow12 = (current_pc & 0x1ff) >= 0x140;
2815
2816 isa = xtensa_default_isa;
2817 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2818 ins = xtensa_insnbuf_alloc (isa);
2819 slot = xtensa_insnbuf_alloc (isa);
2820 ba = 0;
2821 ia = current_pc;
2822 bt = ia;
2823
2824 a0_was_saved = 0;
2825 a7_was_saved = 0;
2826 a11_was_saved = 0;
2827
2828 while (insn_num++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN)
2829 {
2830 if (ia + xtensa_isa_maxlength (isa) > bt)
2831 {
2832 ba = ia;
2833 bt = (ba + XTENSA_ISA_BSZ);
2834 if (target_read_memory (ba, ibuf, bt - ba) != 0)
2835 return xtNoExceptionHandler;
2836 }
2837 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2838 ifmt = xtensa_format_decode (isa, ins);
2839 if (ifmt == XTENSA_UNDEFINED)
2840 return xtNoExceptionHandler;
2841 ilen = xtensa_format_length (isa, ifmt);
2842 if (ilen == XTENSA_UNDEFINED)
2843 return xtNoExceptionHandler;
2844 islots = xtensa_format_num_slots (isa, ifmt);
2845 if (islots == XTENSA_UNDEFINED)
2846 return xtNoExceptionHandler;
2847 for (is = 0; is < islots; ++is)
2848 {
2849 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
2850 return xtNoExceptionHandler;
2851 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2852 if (opc == XTENSA_UNDEFINED)
2853 return xtNoExceptionHandler;
2854 switch (call0_classify_opcode (isa, opc))
2855 {
2856 case c0opc_illegal:
2857 case c0opc_flow:
2858 case c0opc_entry:
2859 case c0opc_break:
2860 /* We expect none of them here. */
2861 return xtNoExceptionHandler;
2862 case c0opc_l32e:
2863 func = execute_l32e;
2864 break;
2865 case c0opc_s32e:
2866 func = execute_s32e;
2867 break;
2868 case c0opc_rfwo: /* RFWO. */
2869 /* Here, we return from WindowOverflow handler and,
2870 if we stopped at the very beginning, which means
2871 A0 was saved, we have to restore it now. */
2872 if (a0_was_saved)
2873 {
2874 int arreg = arreg_number (gdbarch,
2875 gdbarch_tdep (gdbarch)->a0_base,
2876 wb);
2877 xtensa_write_register (arreg, a0_saved);
2878 }
2879 return xtWindowOverflow;
2880 case c0opc_rfwu: /* RFWU. */
2881 /* Here, we return from WindowUnderflow handler.
2882 Let's see if either A7 or A11 has to be restored. */
2883 if (WindowUnderflow12)
2884 {
2885 if (a11_was_saved)
2886 {
2887 int arreg = arreg_number (gdbarch,
2888 gdbarch_tdep (gdbarch)->a0_base + 11,
2889 wb);
2890 xtensa_write_register (arreg, a11_saved);
2891 }
2892 }
2893 else if (a7_was_saved)
2894 {
2895 int arreg = arreg_number (gdbarch,
2896 gdbarch_tdep (gdbarch)->a0_base + 7,
2897 wb);
2898 xtensa_write_register (arreg, a7_saved);
2899 }
2900 return xtWindowUnderflow;
2901 default: /* Simply skip this insns. */
2902 continue;
2903 }
2904
2905 /* Decode arguments for L32E / S32E and simulate their execution. */
2906 if ( xtensa_opcode_num_operands (isa, opc) != 3 )
2907 return xtNoExceptionHandler;
2908 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, &at))
2909 return xtNoExceptionHandler;
2910 if (xtensa_operand_decode (isa, opc, 0, &at))
2911 return xtNoExceptionHandler;
2912 if (xtensa_operand_get_field (isa, opc, 1, ifmt, is, slot, &as))
2913 return xtNoExceptionHandler;
2914 if (xtensa_operand_decode (isa, opc, 1, &as))
2915 return xtNoExceptionHandler;
2916 if (xtensa_operand_get_field (isa, opc, 2, ifmt, is, slot, &offset))
2917 return xtNoExceptionHandler;
2918 if (xtensa_operand_decode (isa, opc, 2, &offset))
2919 return xtNoExceptionHandler;
2920
2921 (*func) (gdbarch, at, as, offset, wb);
2922 }
2923
2924 ia += ilen;
2925 }
2926 return xtNoExceptionHandler;
2927}
2928
2929/* Handle Window Overflow / Underflow exception frames. */
2930
2931static void
2932xtensa_window_interrupt_frame_cache (struct frame_info *this_frame,
2933 xtensa_frame_cache_t *cache,
2934 CORE_ADDR pc)
2935{
2936 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2937 CORE_ADDR ps, wb, ws, ra;
2938 int epc1_regnum, i, regnum;
2939 xtensa_exception_handler_t eh_type;
2940
2941 /* Read PS, WB, and WS from the hardware. Note that PS register
2942 must be present, if Windowed ABI is supported. */
2943 ps = xtensa_read_register (gdbarch_ps_regnum (gdbarch));
2944 wb = xtensa_read_register (gdbarch_tdep (gdbarch)->wb_regnum);
2945 ws = xtensa_read_register (gdbarch_tdep (gdbarch)->ws_regnum);
2946
2947 /* Execute all the remaining instructions from Window Interrupt Handler
2948 by simulating them on the remote protocol level. On return, set the
2949 type of Xtensa Window Interrupt Handler, or report an error. */
2950 eh_type = execute_code (gdbarch, pc, wb);
2951 if (eh_type == xtNoExceptionHandler)
2952 error (_("\
2953Unable to decode Xtensa Window Interrupt Handler's code."));
2954
2955 cache->ps = ps ^ PS_EXC; /* Clear the exception bit in PS. */
2956 cache->call0 = 0; /* It's Windowed ABI. */
2957
2958 /* All registers for the cached frame will be alive. */
2959 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
2960 cache->wd.aregs[i] = -1;
2961
2962 if (eh_type == xtWindowOverflow)
2963 cache->wd.ws = ws ^ (1 << wb);
2964 else /* eh_type == xtWindowUnderflow. */
2965 cache->wd.ws = ws | (1 << wb);
2966
2967 cache->wd.wb = (ps & 0xf00) >> 8; /* Set WB to OWB. */
2968 regnum = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base,
2969 cache->wd.wb);
2970 ra = xtensa_read_register (regnum);
2971 cache->wd.callsize = WINSIZE (ra);
2972 cache->prev_sp = xtensa_read_register (regnum + 1);
2973 /* Set regnum to a frame pointer of the frame being cached. */
2974 regnum = xtensa_scan_prologue (gdbarch, pc);
2975 regnum = arreg_number (gdbarch,
2976 gdbarch_tdep (gdbarch)->a0_base + regnum,
2977 cache->wd.wb);
2978 cache->base = get_frame_register_unsigned (this_frame, regnum);
2979
2980 /* Read PC of interrupted function from EPC1 register. */
2981 epc1_regnum = xtensa_find_register_by_name (gdbarch,"epc1");
2982 if (epc1_regnum < 0)
2983 error(_("Unable to read Xtensa register EPC1"));
2984 cache->ra = xtensa_read_register (epc1_regnum);
2985 cache->pc = get_frame_func (this_frame);
2986}
2987
bdb4c075
MG		 2988
2989/* Skip function prologue.
2990
2991 Return the pc of the first instruction after prologue. GDB calls this to
2992 find the address of the first line of the function or (if there is no line
2993 number information) to skip the prologue for planting breakpoints on
2994 function entries. Use debug info (if present) or prologue analysis to skip
2995 the prologue to achieve reliable debugging behavior. For windowed ABI,
2996 only the 'entry' instruction is skipped. It is not strictly necessary to
2997 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2998 backtrace at any point in the prologue, however certain potential hazards
2999 are avoided and a more "normal" debugging experience is ensured by
3000 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
3001 For example, if we don't skip the prologue:
3002 - Some args may not yet have been saved to the stack where the debug
3003 info expects to find them (true anyway when only 'entry' is skipped);
3004 - Software breakpoints ('break' instrs) may not have been unplanted
3005 when the prologue analysis is done on initializing the frame cache,
3006 and breaks in the prologue will throw off the analysis.
ca3bf3bd
DJ		 3007
3008 If we have debug info ( line-number info, in particular ) we simply skip
3009 the code associated with the first function line effectively skipping
bdb4c075 3010 the prologue code. It works even in cases like
ca3bf3bd
DJ		 3011
3012 int main()
3013 { int local_var = 1;
3014 ....
3015 }
3016
3017 because, for this source code, both Xtensa compilers will generate two
3018 separate entries ( with the same line number ) in dwarf line-number
3019 section to make sure there is a boundary between the prologue code and
3020 the rest of the function.
3021
bdb4c075
MG		 3022 If there is no debug info, we need to analyze the code. */
3023
3024/* #define DONT_SKIP_PROLOGUE */
ca3bf3bd 3025
63807e1d 3026static CORE_ADDR
6093d2eb 3027xtensa_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
ca3bf3bd 3028{
bdb4c075
MG		 3029 struct symtab_and_line prologue_sal;
3030 CORE_ADDR body_pc;
3031
ca3bf3bd
DJ		 3032 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc);
3033
bdb4c075
MG		 3034#if DONT_SKIP_PROLOGUE
3035 return start_pc;
3036#endif
3037
3038 /* Try to find first body line from debug info. */
3039
3040 prologue_sal = find_pc_line (start_pc, 0);
3041 if (prologue_sal.line != 0) /* Found debug info. */
ca3bf3bd 3042 {
f976a05d
MG		 3043 /* In Call0, it is possible to have a function with only one instruction
3044 ('ret') resulting from a one-line optimized function that does nothing.
3045 In that case, prologue_sal.end may actually point to the start of the
3046 next function in the text section, causing a breakpoint to be set at
3047 the wrong place. Check, if the end address is within a different
3048 function, and if so return the start PC. We know we have symbol
3049 information. */
ca3bf3bd 3050
bdb4c075
MG		 3051 CORE_ADDR end_func;
3052
f976a05d
MG		 3053 if ((gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only)
3054 && call0_ret (start_pc, prologue_sal.end))
3055 return start_pc;
3056
bdb4c075
MG		 3057 find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL);
3058 if (end_func != start_pc)
ca3bf3bd
DJ		 3059 return start_pc;
3060
bdb4c075 3061 return prologue_sal.end;
ca3bf3bd 3062 }
ca3bf3bd 3063
bdb4c075 3064 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
dbab50de
MG		 3065 body_pc = call0_analyze_prologue (gdbarch, start_pc, 0, 0,
3066 xtensa_alloc_frame_cache (0));
bdb4c075
MG		 3067 return body_pc != 0 ? body_pc : start_pc;
3068}
ca3bf3bd
DJ		 3069
3070/* Verify the current configuration. */
ca3bf3bd
DJ		 3071static void
3072xtensa_verify_config (struct gdbarch *gdbarch)
3073{
3074 struct ui_file *log;
3075 struct cleanup *cleanups;
3076 struct gdbarch_tdep *tdep;
759ef836 3077 long length;
ca3bf3bd
DJ		 3078 char *buf;
3079
3080 tdep = gdbarch_tdep (gdbarch);
3081 log = mem_fileopen ();
3082 cleanups = make_cleanup_ui_file_delete (log);
3083
3084 /* Verify that we got a reasonable number of AREGS. */
3085 if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs)
bdb4c075
MG		 3086 fprintf_unfiltered (log, _("\
3087\n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
3088 tdep->num_aregs);
ca3bf3bd
DJ		 3089
3090 /* Verify that certain registers exist. */
bdb4c075 3091
ca3bf3bd 3092 if (tdep->pc_regnum == -1)
bdb4c075
MG		 3093 fprintf_unfiltered (log, _("\n\tpc_regnum: No PC register"));
3094 if (tdep->isa_use_exceptions && tdep->ps_regnum == -1)
3095 fprintf_unfiltered (log, _("\n\tps_regnum: No PS register"));
3096
3097 if (tdep->isa_use_windowed_registers)
3098 {
3099 if (tdep->wb_regnum == -1)
3100 fprintf_unfiltered (log, _("\n\twb_regnum: No WB register"));
3101 if (tdep->ws_regnum == -1)
3102 fprintf_unfiltered (log, _("\n\tws_regnum: No WS register"));
3103 if (tdep->ar_base == -1)
3104 fprintf_unfiltered (log, _("\n\tar_base: No AR registers"));
3105 }
3106
ca3bf3bd 3107 if (tdep->a0_base == -1)
bdb4c075 3108 fprintf_unfiltered (log, _("\n\ta0_base: No Ax registers"));
ca3bf3bd 3109
759ef836 3110 buf = ui_file_xstrdup (log, &length);
ca3bf3bd 3111 make_cleanup (xfree, buf);
759ef836 3112 if (length > 0)
ca3bf3bd
DJ		 3113 internal_error (__FILE__, __LINE__,
3114 _("the following are invalid: %s"), buf);
3115 do_cleanups (cleanups);
3116}
3117
94a0e877
MG		 3118
3119/* Derive specific register numbers from the array of registers. */
3120
63807e1d 3121static void
94a0e877
MG		 3122xtensa_derive_tdep (struct gdbarch_tdep *tdep)
3123{
3124 xtensa_register_t* rmap;
3125 int n, max_size = 4;
3126
3127 tdep->num_regs = 0;
3128 tdep->num_nopriv_regs = 0;
3129
3130/* Special registers 0..255 (core). */
3131#define XTENSA_DBREGN_SREG(n) (0x0200+(n))
3132
3133 for (rmap = tdep->regmap, n = 0; rmap->target_number != -1; n++, rmap++)
3134 {
3135 if (rmap->target_number == 0x0020)
3136 tdep->pc_regnum = n;
3137 else if (rmap->target_number == 0x0100)
3138 tdep->ar_base = n;
3139 else if (rmap->target_number == 0x0000)
3140 tdep->a0_base = n;
3141 else if (rmap->target_number == XTENSA_DBREGN_SREG(72))
3142 tdep->wb_regnum = n;
3143 else if (rmap->target_number == XTENSA_DBREGN_SREG(73))
3144 tdep->ws_regnum = n;
3145 else if (rmap->target_number == XTENSA_DBREGN_SREG(233))
3146 tdep->debugcause_regnum = n;
3147 else if (rmap->target_number == XTENSA_DBREGN_SREG(232))
3148 tdep->exccause_regnum = n;
3149 else if (rmap->target_number == XTENSA_DBREGN_SREG(238))
3150 tdep->excvaddr_regnum = n;
3151 else if (rmap->target_number == XTENSA_DBREGN_SREG(0))
3152 tdep->lbeg_regnum = n;
3153 else if (rmap->target_number == XTENSA_DBREGN_SREG(1))
3154 tdep->lend_regnum = n;
3155 else if (rmap->target_number == XTENSA_DBREGN_SREG(2))
3156 tdep->lcount_regnum = n;
3157 else if (rmap->target_number == XTENSA_DBREGN_SREG(3))
3158 tdep->sar_regnum = n;
3159 else if (rmap->target_number == XTENSA_DBREGN_SREG(5))
3160 tdep->litbase_regnum = n;
3161 else if (rmap->target_number == XTENSA_DBREGN_SREG(230))
3162 tdep->ps_regnum = n;
3163#if 0
3164 else if (rmap->target_number == XTENSA_DBREGN_SREG(226))
3165 tdep->interrupt_regnum = n;
3166 else if (rmap->target_number == XTENSA_DBREGN_SREG(227))
3167 tdep->interrupt2_regnum = n;
3168 else if (rmap->target_number == XTENSA_DBREGN_SREG(224))
3169 tdep->cpenable_regnum = n;
3170#endif
3171
3172 if (rmap->byte_size > max_size)
3173 max_size = rmap->byte_size;
3174 if (rmap->mask != 0 && tdep->num_regs == 0)
3175 tdep->num_regs = n;
3176 /* Find out out how to deal with priveleged registers.
3177
3178 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
3179 && tdep->num_nopriv_regs == 0)
3180 tdep->num_nopriv_regs = n;
3181 */
3182 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
3183 && tdep->num_regs == 0)
3184 tdep->num_regs = n;
3185 }
3186
3187 /* Number of pseudo registers. */
3188 tdep->num_pseudo_regs = n - tdep->num_regs;
3189
3190 /* Empirically determined maximum sizes. */
3191 tdep->max_register_raw_size = max_size;
3192 tdep->max_register_virtual_size = max_size;
3193}
3194
ca3bf3bd
DJ		 3195/* Module "constructor" function. */
3196
94a0e877
MG		 3197extern struct gdbarch_tdep xtensa_tdep;
3198
ca3bf3bd
DJ		 3199static struct gdbarch *
3200xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3201{
3202 struct gdbarch_tdep *tdep;
3203 struct gdbarch *gdbarch;
3204 struct xtensa_abi_handler *abi_handler;
3205
3206 DEBUGTRACE ("gdbarch_init()\n");
3207
3208 /* We have to set the byte order before we call gdbarch_alloc. */
94a0e877 3209 info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
ca3bf3bd 3210
94a0e877 3211 tdep = &xtensa_tdep;
ca3bf3bd 3212 gdbarch = gdbarch_alloc (&info, tdep);
94a0e877 3213 xtensa_derive_tdep (tdep);
ca3bf3bd
DJ		 3214
3215 /* Verify our configuration. */
3216 xtensa_verify_config (gdbarch);
dbab50de 3217 xtensa_session_once_reported = 0;
ca3bf3bd 3218
bdb4c075 3219 /* Pseudo-Register read/write. */
ca3bf3bd
DJ		 3220 set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read);
3221 set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write);
3222
3223 /* Set target information. */
3224 set_gdbarch_num_regs (gdbarch, tdep->num_regs);
3225 set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs);
3226 set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1);
3227 set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum);
3228 set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum);
3229
ba2b1c56 3230 /* Renumber registers for known formats (stabs and dwarf2). */
ca3bf3bd 3231 set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
ca3bf3bd
DJ		 3232 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
3233
3234 /* We provide our own function to get register information. */
3235 set_gdbarch_register_name (gdbarch, xtensa_register_name);
3236 set_gdbarch_register_type (gdbarch, xtensa_register_type);
3237
581e13c1 3238 /* To call functions from GDB using dummy frame. */
ca3bf3bd
DJ		 3239 set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call);
3240
3241 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
3242
3243 set_gdbarch_return_value (gdbarch, xtensa_return_value);
3244
3245 /* Advance PC across any prologue instructions to reach "real" code. */
3246 set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue);
3247
3248 /* Stack grows downward. */
3249 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3250
3251 /* Set breakpoints. */
3252 set_gdbarch_breakpoint_from_pc (gdbarch, xtensa_breakpoint_from_pc);
3253
3254 /* After breakpoint instruction or illegal instruction, pc still
3255 points at break instruction, so don't decrement. */
3256 set_gdbarch_decr_pc_after_break (gdbarch, 0);
3257
3258 /* We don't skip args. */
3259 set_gdbarch_frame_args_skip (gdbarch, 0);
3260
3261 set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc);
3262
3263 set_gdbarch_frame_align (gdbarch, xtensa_frame_align);
3264
5142f611 3265 set_gdbarch_dummy_id (gdbarch, xtensa_dummy_id);
ca3bf3bd
DJ		 3266
3267 /* Frame handling. */
3268 frame_base_set_default (gdbarch, &xtensa_frame_base);
5142f611
MG		 3269 frame_unwind_append_unwinder (gdbarch, &xtensa_unwind);
3270 dwarf2_append_unwinders (gdbarch);
ca3bf3bd
DJ		 3271
3272 set_gdbarch_print_insn (gdbarch, print_insn_xtensa);
3273
3274 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3275
3276 xtensa_add_reggroups (gdbarch);
3277 set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p);
3278
3279 set_gdbarch_regset_from_core_section (gdbarch,
3280 xtensa_regset_from_core_section);
3281
ee967b5f
MG		 3282 set_solib_svr4_fetch_link_map_offsets
3283 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
3284
ca3bf3bd
DJ		 3285 return gdbarch;
3286}
3287
ca3bf3bd 3288static void
6b50c0b0 3289xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
ca3bf3bd
DJ		 3290{
3291 error (_("xtensa_dump_tdep(): not implemented"));
3292}
3293
63807e1d
PA		 3294/* Provide a prototype to silence -Wmissing-prototypes. */
3295extern initialize_file_ftype _initialize_xtensa_tdep;
3296
ca3bf3bd
DJ		 3297void
3298_initialize_xtensa_tdep (void)
3299{
3300 struct cmd_list_element *c;
3301
3302 gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep);
3303 xtensa_init_reggroups ();
3304
3305 add_setshow_zinteger_cmd ("xtensa",
3306 class_maintenance,
581e13c1
MS		 3307 &xtensa_debug_level,
3308 _("Set Xtensa debugging."),
3309 _("Show Xtensa debugging."), _("\
ca3bf3bd
DJ		 3310When non-zero, Xtensa-specific debugging is enabled. \
3311Can be 1, 2, 3, or 4 indicating the level of debugging."),
3312 NULL,
3313 NULL,
3314 &setdebuglist, &showdebuglist);
3315}
GDB Binutils - Deliverables
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