Commit | Line | Data |
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ca3bf3bd DJ |
1 | /* Target-dependent code for the Xtensa port of GDB, the GNU debugger. |
2 | ||
0fb0cc75 JB |
3 | Copyright (C) 2003, 2005, 2006, 2007, 2008, 2009 |
4 | Free Software Foundation, Inc. | |
ca3bf3bd DJ |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
ca3bf3bd DJ |
11 | (at your option) any later version. |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
ca3bf3bd DJ |
20 | |
21 | #include "defs.h" | |
22 | #include "frame.h" | |
ee967b5f | 23 | #include "solib-svr4.h" |
ca3bf3bd DJ |
24 | #include "symtab.h" |
25 | #include "symfile.h" | |
26 | #include "objfiles.h" | |
27 | #include "gdbtypes.h" | |
28 | #include "gdbcore.h" | |
29 | #include "value.h" | |
30 | #include "dis-asm.h" | |
31 | #include "inferior.h" | |
32 | #include "floatformat.h" | |
33 | #include "regcache.h" | |
34 | #include "reggroups.h" | |
35 | #include "regset.h" | |
36 | ||
37 | #include "dummy-frame.h" | |
38 | #include "elf/dwarf2.h" | |
39 | #include "dwarf2-frame.h" | |
40 | #include "dwarf2loc.h" | |
41 | #include "frame.h" | |
42 | #include "frame-base.h" | |
43 | #include "frame-unwind.h" | |
44 | ||
45 | #include "arch-utils.h" | |
46 | #include "gdbarch.h" | |
47 | #include "remote.h" | |
48 | #include "serial.h" | |
49 | ||
50 | #include "command.h" | |
51 | #include "gdbcmd.h" | |
52 | #include "gdb_assert.h" | |
53 | ||
bdb4c075 | 54 | #include "xtensa-isa.h" |
ca3bf3bd | 55 | #include "xtensa-tdep.h" |
94a0e877 | 56 | #include "xtensa-config.h" |
ca3bf3bd DJ |
57 | |
58 | ||
59 | static int xtensa_debug_level = 0; | |
60 | ||
61 | #define DEBUGWARN(args...) \ | |
62 | if (xtensa_debug_level > 0) \ | |
63 | fprintf_unfiltered (gdb_stdlog, "(warn ) " args) | |
64 | ||
65 | #define DEBUGINFO(args...) \ | |
66 | if (xtensa_debug_level > 1) \ | |
67 | fprintf_unfiltered (gdb_stdlog, "(info ) " args) | |
68 | ||
69 | #define DEBUGTRACE(args...) \ | |
70 | if (xtensa_debug_level > 2) \ | |
71 | fprintf_unfiltered (gdb_stdlog, "(trace) " args) | |
72 | ||
73 | #define DEBUGVERB(args...) \ | |
74 | if (xtensa_debug_level > 3) \ | |
75 | fprintf_unfiltered (gdb_stdlog, "(verb ) " args) | |
76 | ||
77 | ||
78 | /* According to the ABI, the SP must be aligned to 16-byte boundaries. */ | |
ca3bf3bd DJ |
79 | #define SP_ALIGNMENT 16 |
80 | ||
81 | ||
bdb4c075 MG |
82 | /* On Windowed ABI, we use a6 through a11 for passing arguments |
83 | to a function called by GDB because CALL4 is used. */ | |
bdb4c075 MG |
84 | #define ARGS_NUM_REGS 6 |
85 | #define REGISTER_SIZE 4 | |
ca3bf3bd | 86 | |
ca3bf3bd | 87 | |
bdb4c075 MG |
88 | /* Extract the call size from the return address or PS register. */ |
89 | #define PS_CALLINC_SHIFT 16 | |
90 | #define PS_CALLINC_MASK 0x00030000 | |
91 | #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT) | |
92 | #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3)) | |
ca3bf3bd | 93 | |
bdb4c075 | 94 | /* ABI-independent macros. */ |
91d8eb23 MD |
95 | #define ARG_NOF(gdbarch) \ |
96 | (gdbarch_tdep (gdbarch)->call_abi \ | |
97 | == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS)) | |
98 | #define ARG_1ST(gdbarch) \ | |
99 | (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \ | |
94a0e877 | 100 | ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \ |
91d8eb23 | 101 | : (gdbarch_tdep (gdbarch)->a0_base + 6)) |
ca3bf3bd | 102 | |
ca3bf3bd DJ |
103 | /* XTENSA_IS_ENTRY tests whether the first byte of an instruction |
104 | indicates that the instruction is an ENTRY instruction. */ | |
105 | ||
91d8eb23 MD |
106 | #define XTENSA_IS_ENTRY(gdbarch, op1) \ |
107 | ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \ | |
4c6b5505 | 108 | ? ((op1) == 0x6c) : ((op1) == 0x36)) |
ca3bf3bd | 109 | |
bdb4c075 | 110 | #define XTENSA_ENTRY_LENGTH 3 |
ca3bf3bd DJ |
111 | |
112 | /* windowing_enabled() returns true, if windowing is enabled. | |
113 | WOE must be set to 1; EXCM to 0. | |
114 | Note: We assume that EXCM is always 0 for XEA1. */ | |
115 | ||
bdb4c075 MG |
116 | #define PS_WOE (1<<18) |
117 | #define PS_EXC (1<<4) | |
118 | ||
ee967b5f | 119 | /* Convert a live A-register number to the corresponding AR-register number. */ |
91d8eb23 | 120 | static int |
ee967b5f | 121 | arreg_number (struct gdbarch *gdbarch, int a_regnum, ULONGEST wb) |
91d8eb23 MD |
122 | { |
123 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
ee967b5f | 124 | int arreg; |
91d8eb23 | 125 | |
ee967b5f MG |
126 | arreg = a_regnum - tdep->a0_base; |
127 | arreg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT; | |
128 | arreg &= tdep->num_aregs - 1; | |
91d8eb23 | 129 | |
ee967b5f MG |
130 | return arreg + tdep->ar_base; |
131 | } | |
132 | ||
133 | /* Convert a live AR-register number to the corresponding A-register order | |
134 | number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */ | |
135 | static int | |
136 | areg_number (struct gdbarch *gdbarch, int ar_regnum, unsigned int wb) | |
137 | { | |
138 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
139 | int areg; | |
140 | ||
141 | areg = ar_regnum - tdep->ar_base; | |
142 | if (areg < 0 || areg >= tdep->num_aregs) | |
143 | return -1; | |
144 | areg = (areg - wb * 4) & (tdep->num_aregs - 1); | |
145 | return (areg > 15) ? -1 : areg; | |
91d8eb23 MD |
146 | } |
147 | ||
ca3bf3bd DJ |
148 | static inline int |
149 | windowing_enabled (CORE_ADDR ps) | |
150 | { | |
bdb4c075 | 151 | return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0); |
ca3bf3bd DJ |
152 | } |
153 | ||
154 | /* Return the window size of the previous call to the function from which we | |
155 | have just returned. | |
156 | ||
157 | This function is used to extract the return value after a called function | |
bdb4c075 | 158 | has returned to the caller. On Xtensa, the register that holds the return |
ca3bf3bd DJ |
159 | value (from the perspective of the caller) depends on what call |
160 | instruction was used. For now, we are assuming that the call instruction | |
161 | precedes the current address, so we simply analyze the call instruction. | |
162 | If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4' | |
163 | method to call the inferior function. */ | |
164 | ||
165 | static int | |
91d8eb23 | 166 | extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc) |
ca3bf3bd | 167 | { |
bdb4c075 | 168 | int winsize = 4; |
ca3bf3bd | 169 | int insn; |
ff7a4c00 | 170 | gdb_byte buf[4]; |
ca3bf3bd DJ |
171 | |
172 | DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc); | |
173 | ||
174 | /* Read the previous instruction (should be a call[x]{4|8|12}. */ | |
175 | read_memory (pc-3, buf, 3); | |
176 | insn = extract_unsigned_integer (buf, 3); | |
177 | ||
178 | /* Decode call instruction: | |
179 | Little Endian | |
180 | call{0,4,8,12} OFFSET || {00,01,10,11} || 0101 | |
181 | callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000 | |
182 | Big Endian | |
183 | call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET | |
184 | callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */ | |
185 | ||
91d8eb23 | 186 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
ca3bf3bd DJ |
187 | { |
188 | if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0)) | |
bdb4c075 | 189 | winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */ |
ca3bf3bd DJ |
190 | } |
191 | else | |
192 | { | |
193 | if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03)) | |
bdb4c075 | 194 | winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */ |
ca3bf3bd DJ |
195 | } |
196 | return winsize; | |
197 | } | |
198 | ||
199 | ||
200 | /* REGISTER INFORMATION */ | |
201 | ||
202 | /* Returns the name of a register. */ | |
ca3bf3bd | 203 | static const char * |
d93859e2 | 204 | xtensa_register_name (struct gdbarch *gdbarch, int regnum) |
ca3bf3bd DJ |
205 | { |
206 | /* Return the name stored in the register map. */ | |
d93859e2 UW |
207 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch) |
208 | + gdbarch_num_pseudo_regs (gdbarch)) | |
209 | return gdbarch_tdep (gdbarch)->regmap[regnum].name; | |
ca3bf3bd | 210 | |
ca3bf3bd DJ |
211 | internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum); |
212 | return 0; | |
213 | } | |
214 | ||
ca3bf3bd DJ |
215 | /* Return the type of a register. Create a new type, if necessary. */ |
216 | ||
217 | static struct ctype_cache | |
218 | { | |
219 | struct ctype_cache *next; | |
220 | int size; | |
221 | struct type *virtual_type; | |
222 | } *type_entries = NULL; | |
223 | ||
224 | static struct type * | |
225 | xtensa_register_type (struct gdbarch *gdbarch, int regnum) | |
226 | { | |
227 | /* Return signed integer for ARx and Ax registers. */ | |
6b50c0b0 UW |
228 | if ((regnum >= gdbarch_tdep (gdbarch)->ar_base |
229 | && regnum < gdbarch_tdep (gdbarch)->ar_base | |
230 | + gdbarch_tdep (gdbarch)->num_aregs) | |
231 | || (regnum >= gdbarch_tdep (gdbarch)->a0_base | |
232 | && regnum < gdbarch_tdep (gdbarch)->a0_base + 16)) | |
0dfff4cb | 233 | return builtin_type (gdbarch)->builtin_int; |
ca3bf3bd | 234 | |
6b50c0b0 UW |
235 | if (regnum == gdbarch_pc_regnum (gdbarch) |
236 | || regnum == gdbarch_tdep (gdbarch)->a0_base + 1) | |
fde6c819 | 237 | return builtin_type (gdbarch)->builtin_data_ptr; |
ca3bf3bd DJ |
238 | |
239 | /* Return the stored type for all other registers. */ | |
6b50c0b0 UW |
240 | else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch) |
241 | + gdbarch_num_pseudo_regs (gdbarch)) | |
ca3bf3bd | 242 | { |
6b50c0b0 | 243 | xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; |
ca3bf3bd | 244 | |
bdb4c075 | 245 | /* Set ctype for this register (only the first time). */ |
ca3bf3bd DJ |
246 | |
247 | if (reg->ctype == 0) | |
248 | { | |
249 | struct ctype_cache *tp; | |
250 | int size = reg->byte_size; | |
251 | ||
bdb4c075 MG |
252 | /* We always use the memory representation, |
253 | even if the register width is smaller. */ | |
ca3bf3bd DJ |
254 | switch (size) |
255 | { | |
256 | case 1: | |
257 | reg->ctype = builtin_type_uint8; | |
258 | break; | |
259 | ||
260 | case 2: | |
261 | reg->ctype = builtin_type_uint16; | |
262 | break; | |
263 | ||
264 | case 4: | |
265 | reg->ctype = builtin_type_uint32; | |
266 | break; | |
267 | ||
268 | case 8: | |
269 | reg->ctype = builtin_type_uint64; | |
270 | break; | |
271 | ||
272 | case 16: | |
273 | reg->ctype = builtin_type_uint128; | |
274 | break; | |
275 | ||
276 | default: | |
277 | for (tp = type_entries; tp != NULL; tp = tp->next) | |
278 | if (tp->size == size) | |
279 | break; | |
280 | ||
281 | if (tp == NULL) | |
282 | { | |
283 | char *name = xmalloc (16); | |
284 | tp = xmalloc (sizeof (struct ctype_cache)); | |
285 | tp->next = type_entries; | |
286 | type_entries = tp; | |
287 | tp->size = size; | |
288 | ||
289 | sprintf (name, "int%d", size * 8); | |
290 | tp->virtual_type = init_type (TYPE_CODE_INT, size, | |
291 | TYPE_FLAG_UNSIGNED, name, | |
292 | NULL); | |
293 | } | |
294 | ||
295 | reg->ctype = tp->virtual_type; | |
296 | } | |
297 | } | |
298 | return reg->ctype; | |
299 | } | |
300 | ||
ca3bf3bd DJ |
301 | internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum); |
302 | return 0; | |
303 | } | |
304 | ||
305 | ||
bdb4c075 | 306 | /* Return the 'local' register number for stubs, dwarf2, etc. |
ca3bf3bd DJ |
307 | The debugging information enumerates registers starting from 0 for A0 |
308 | to n for An. So, we only have to add the base number for A0. */ | |
309 | ||
310 | static int | |
d3f73121 | 311 | xtensa_reg_to_regnum (struct gdbarch *gdbarch, int regnum) |
ca3bf3bd DJ |
312 | { |
313 | int i; | |
314 | ||
315 | if (regnum >= 0 && regnum < 16) | |
d3f73121 | 316 | return gdbarch_tdep (gdbarch)->a0_base + regnum; |
ca3bf3bd | 317 | |
f57d151a | 318 | for (i = 0; |
d3f73121 | 319 | i < gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
f57d151a | 320 | i++) |
d3f73121 | 321 | if (regnum == gdbarch_tdep (gdbarch)->regmap[i].target_number) |
ca3bf3bd DJ |
322 | return i; |
323 | ||
ca3bf3bd DJ |
324 | internal_error (__FILE__, __LINE__, |
325 | _("invalid dwarf/stabs register number %d"), regnum); | |
326 | return 0; | |
327 | } | |
328 | ||
329 | ||
bdb4c075 MG |
330 | /* Write the bits of a masked register to the various registers. |
331 | Only the masked areas of these registers are modified; the other | |
332 | fields are untouched. The size of masked registers is always less | |
333 | than or equal to 32 bits. */ | |
ca3bf3bd DJ |
334 | |
335 | static void | |
9c9acae0 UW |
336 | xtensa_register_write_masked (struct regcache *regcache, |
337 | xtensa_register_t *reg, const gdb_byte *buffer) | |
ca3bf3bd DJ |
338 | { |
339 | unsigned int value[(MAX_REGISTER_SIZE + 3) / 4]; | |
ca3bf3bd DJ |
340 | const xtensa_mask_t *mask = reg->mask; |
341 | ||
342 | int shift = 0; /* Shift for next mask (mod 32). */ | |
343 | int start, size; /* Start bit and size of current mask. */ | |
344 | ||
345 | unsigned int *ptr = value; | |
346 | unsigned int regval, m, mem = 0; | |
347 | ||
348 | int bytesize = reg->byte_size; | |
349 | int bitsize = bytesize * 8; | |
350 | int i, r; | |
351 | ||
352 | DEBUGTRACE ("xtensa_register_write_masked ()\n"); | |
353 | ||
354 | /* Copy the masked register to host byte-order. */ | |
6b50c0b0 | 355 | if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
356 | for (i = 0; i < bytesize; i++) |
357 | { | |
358 | mem >>= 8; | |
359 | mem |= (buffer[bytesize - i - 1] << 24); | |
360 | if ((i & 3) == 3) | |
361 | *ptr++ = mem; | |
362 | } | |
363 | else | |
364 | for (i = 0; i < bytesize; i++) | |
365 | { | |
366 | mem >>= 8; | |
367 | mem |= (buffer[i] << 24); | |
368 | if ((i & 3) == 3) | |
369 | *ptr++ = mem; | |
370 | } | |
371 | ||
372 | /* We might have to shift the final value: | |
373 | bytesize & 3 == 0 -> nothing to do, we use the full 32 bits, | |
374 | bytesize & 3 == x -> shift (4-x) * 8. */ | |
375 | ||
376 | *ptr = mem >> (((0 - bytesize) & 3) * 8); | |
377 | ptr = value; | |
378 | mem = *ptr; | |
379 | ||
380 | /* Write the bits to the masked areas of the other registers. */ | |
381 | for (i = 0; i < mask->count; i++) | |
382 | { | |
383 | start = mask->mask[i].bit_start; | |
384 | size = mask->mask[i].bit_size; | |
385 | regval = mem >> shift; | |
386 | ||
387 | if ((shift += size) > bitsize) | |
388 | error (_("size of all masks is larger than the register")); | |
389 | ||
390 | if (shift >= 32) | |
391 | { | |
392 | mem = *(++ptr); | |
393 | shift -= 32; | |
394 | bitsize -= 32; | |
395 | ||
396 | if (shift > 0) | |
397 | regval |= mem << (size - shift); | |
398 | } | |
399 | ||
400 | /* Make sure we have a valid register. */ | |
401 | r = mask->mask[i].reg_num; | |
402 | if (r >= 0 && size > 0) | |
403 | { | |
404 | /* Don't overwrite the unmasked areas. */ | |
9c9acae0 UW |
405 | ULONGEST old_val; |
406 | regcache_cooked_read_unsigned (regcache, r, &old_val); | |
ca3bf3bd DJ |
407 | m = 0xffffffff >> (32 - size) << start; |
408 | regval <<= start; | |
9c9acae0 UW |
409 | regval = (regval & m) | (old_val & ~m); |
410 | regcache_cooked_write_unsigned (regcache, r, regval); | |
ca3bf3bd DJ |
411 | } |
412 | } | |
413 | } | |
414 | ||
415 | ||
bdb4c075 MG |
416 | /* Read a tie state or mapped registers. Read the masked areas |
417 | of the registers and assemble them into a single value. */ | |
ca3bf3bd DJ |
418 | |
419 | static void | |
9c9acae0 UW |
420 | xtensa_register_read_masked (struct regcache *regcache, |
421 | xtensa_register_t *reg, gdb_byte *buffer) | |
ca3bf3bd DJ |
422 | { |
423 | unsigned int value[(MAX_REGISTER_SIZE + 3) / 4]; | |
ca3bf3bd DJ |
424 | const xtensa_mask_t *mask = reg->mask; |
425 | ||
426 | int shift = 0; | |
427 | int start, size; | |
428 | ||
429 | unsigned int *ptr = value; | |
430 | unsigned int regval, mem = 0; | |
431 | ||
432 | int bytesize = reg->byte_size; | |
433 | int bitsize = bytesize * 8; | |
434 | int i; | |
435 | ||
436 | DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n", | |
437 | reg->name == 0 ? "" : reg->name); | |
438 | ||
439 | /* Assemble the register from the masked areas of other registers. */ | |
440 | for (i = 0; i < mask->count; i++) | |
441 | { | |
442 | int r = mask->mask[i].reg_num; | |
9c9acae0 UW |
443 | if (r >= 0) |
444 | { | |
445 | ULONGEST val; | |
446 | regcache_cooked_read_unsigned (regcache, r, &val); | |
447 | regval = (unsigned int) val; | |
448 | } | |
449 | else | |
450 | regval = 0; | |
451 | ||
ca3bf3bd DJ |
452 | start = mask->mask[i].bit_start; |
453 | size = mask->mask[i].bit_size; | |
454 | ||
455 | regval >>= start; | |
456 | ||
457 | if (size < 32) | |
458 | regval &= (0xffffffff >> (32 - size)); | |
459 | ||
460 | mem |= regval << shift; | |
461 | ||
462 | if ((shift += size) > bitsize) | |
463 | error (_("size of all masks is larger than the register")); | |
464 | ||
465 | if (shift >= 32) | |
466 | { | |
467 | *ptr++ = mem; | |
468 | bitsize -= 32; | |
469 | shift -= 32; | |
470 | ||
471 | if (shift == 0) | |
472 | mem = 0; | |
473 | else | |
474 | mem = regval >> (size - shift); | |
475 | } | |
476 | } | |
477 | ||
478 | if (shift > 0) | |
479 | *ptr = mem; | |
480 | ||
481 | /* Copy value to target byte order. */ | |
482 | ptr = value; | |
483 | mem = *ptr; | |
484 | ||
6b50c0b0 | 485 | if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
486 | for (i = 0; i < bytesize; i++) |
487 | { | |
488 | if ((i & 3) == 0) | |
489 | mem = *ptr++; | |
490 | buffer[bytesize - i - 1] = mem & 0xff; | |
491 | mem >>= 8; | |
492 | } | |
493 | else | |
494 | for (i = 0; i < bytesize; i++) | |
495 | { | |
496 | if ((i & 3) == 0) | |
497 | mem = *ptr++; | |
498 | buffer[i] = mem & 0xff; | |
499 | mem >>= 8; | |
500 | } | |
501 | } | |
502 | ||
503 | ||
504 | /* Read pseudo registers. */ | |
505 | ||
506 | static void | |
507 | xtensa_pseudo_register_read (struct gdbarch *gdbarch, | |
508 | struct regcache *regcache, | |
509 | int regnum, | |
510 | gdb_byte *buffer) | |
511 | { | |
512 | DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n", | |
d93859e2 | 513 | regnum, xtensa_register_name (gdbarch, regnum)); |
ca3bf3bd | 514 | |
6b50c0b0 | 515 | if (regnum == gdbarch_num_regs (gdbarch) |
94a0e877 | 516 | + gdbarch_num_pseudo_regs (gdbarch) - 1) |
6b50c0b0 | 517 | regnum = gdbarch_tdep (gdbarch)->a0_base + 1; |
ca3bf3bd | 518 | |
bdb4c075 | 519 | /* Read aliases a0..a15, if this is a Windowed ABI. */ |
6b50c0b0 | 520 | if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers |
94a0e877 | 521 | && (regnum >= gdbarch_tdep (gdbarch)->a0_base) |
6b50c0b0 | 522 | && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)) |
ca3bf3bd | 523 | { |
ff7a4c00 | 524 | gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE); |
ca3bf3bd | 525 | |
6b50c0b0 | 526 | regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf); |
ee967b5f MG |
527 | regnum = arreg_number (gdbarch, regnum, |
528 | extract_unsigned_integer (buf, 4)); | |
ca3bf3bd DJ |
529 | } |
530 | ||
bdb4c075 | 531 | /* We can always read non-pseudo registers. */ |
6b50c0b0 | 532 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) |
ca3bf3bd DJ |
533 | regcache_raw_read (regcache, regnum, buffer); |
534 | ||
94a0e877 MG |
535 | |
536 | /* We have to find out how to deal with priveleged registers. | |
537 | Let's treat them as pseudo-registers, but we cannot read/write them. */ | |
538 | ||
539 | else if (regnum < gdbarch_tdep (gdbarch)->a0_base) | |
540 | { | |
541 | buffer[0] = (gdb_byte)0; | |
542 | buffer[1] = (gdb_byte)0; | |
543 | buffer[2] = (gdb_byte)0; | |
544 | buffer[3] = (gdb_byte)0; | |
545 | } | |
ca3bf3bd | 546 | /* Pseudo registers. */ |
f57d151a | 547 | else if (regnum >= 0 |
6b50c0b0 UW |
548 | && regnum < gdbarch_num_regs (gdbarch) |
549 | + gdbarch_num_pseudo_regs (gdbarch)) | |
ca3bf3bd | 550 | { |
6b50c0b0 | 551 | xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; |
ca3bf3bd | 552 | xtensa_register_type_t type = reg->type; |
6b50c0b0 | 553 | int flags = gdbarch_tdep (gdbarch)->target_flags; |
ca3bf3bd | 554 | |
bdb4c075 | 555 | /* We cannot read Unknown or Unmapped registers. */ |
ca3bf3bd DJ |
556 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) |
557 | { | |
558 | if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
559 | { | |
560 | warning (_("cannot read register %s"), | |
d93859e2 | 561 | xtensa_register_name (gdbarch, regnum)); |
ca3bf3bd DJ |
562 | return; |
563 | } | |
564 | } | |
565 | ||
566 | /* Some targets cannot read TIE register files. */ | |
567 | else if (type == xtRegisterTypeTieRegfile) | |
568 | { | |
569 | /* Use 'fetch' to get register? */ | |
570 | if (flags & xtTargetFlagsUseFetchStore) | |
571 | { | |
572 | warning (_("cannot read register")); | |
573 | return; | |
574 | } | |
575 | ||
576 | /* On some targets (esp. simulators), we can always read the reg. */ | |
577 | else if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
578 | { | |
579 | warning (_("cannot read register")); | |
580 | return; | |
581 | } | |
582 | } | |
583 | ||
584 | /* We can always read mapped registers. */ | |
585 | else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState) | |
586 | { | |
9c9acae0 | 587 | xtensa_register_read_masked (regcache, reg, buffer); |
ca3bf3bd DJ |
588 | return; |
589 | } | |
590 | ||
591 | /* Assume that we can read the register. */ | |
592 | regcache_raw_read (regcache, regnum, buffer); | |
593 | } | |
ca3bf3bd DJ |
594 | else |
595 | internal_error (__FILE__, __LINE__, | |
596 | _("invalid register number %d"), regnum); | |
597 | } | |
598 | ||
599 | ||
600 | /* Write pseudo registers. */ | |
601 | ||
602 | static void | |
603 | xtensa_pseudo_register_write (struct gdbarch *gdbarch, | |
604 | struct regcache *regcache, | |
605 | int regnum, | |
606 | const gdb_byte *buffer) | |
607 | { | |
608 | DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n", | |
d93859e2 | 609 | regnum, xtensa_register_name (gdbarch, regnum)); |
ca3bf3bd | 610 | |
6b50c0b0 | 611 | if (regnum == gdbarch_num_regs (gdbarch) |
94a0e877 | 612 | + gdbarch_num_pseudo_regs (gdbarch) -1) |
6b50c0b0 | 613 | regnum = gdbarch_tdep (gdbarch)->a0_base + 1; |
ca3bf3bd | 614 | |
bdb4c075 | 615 | /* Renumber register, if aliase a0..a15 on Windowed ABI. */ |
6b50c0b0 | 616 | if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers |
94a0e877 | 617 | && (regnum >= gdbarch_tdep (gdbarch)->a0_base) |
6b50c0b0 | 618 | && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)) |
ca3bf3bd | 619 | { |
ff7a4c00 | 620 | gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE); |
ca3bf3bd DJ |
621 | unsigned int wb; |
622 | ||
304fe255 | 623 | regcache_raw_read (regcache, |
6b50c0b0 | 624 | gdbarch_tdep (gdbarch)->wb_regnum, buf); |
ee967b5f MG |
625 | regnum = arreg_number (gdbarch, regnum, |
626 | extract_unsigned_integer (buf, 4)); | |
ca3bf3bd DJ |
627 | } |
628 | ||
629 | /* We can always write 'core' registers. | |
630 | Note: We might have converted Ax->ARy. */ | |
6b50c0b0 | 631 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) |
ca3bf3bd DJ |
632 | regcache_raw_write (regcache, regnum, buffer); |
633 | ||
94a0e877 MG |
634 | /* We have to find out how to deal with priveleged registers. |
635 | Let's treat them as pseudo-registers, but we cannot read/write them. */ | |
636 | ||
637 | else if (regnum < gdbarch_tdep (gdbarch)->a0_base) | |
638 | { | |
639 | return; | |
640 | } | |
ca3bf3bd | 641 | /* Pseudo registers. */ |
f57d151a | 642 | else if (regnum >= 0 |
6b50c0b0 UW |
643 | && regnum < gdbarch_num_regs (gdbarch) |
644 | + gdbarch_num_pseudo_regs (gdbarch)) | |
ca3bf3bd | 645 | { |
6b50c0b0 | 646 | xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; |
ca3bf3bd | 647 | xtensa_register_type_t type = reg->type; |
6b50c0b0 | 648 | int flags = gdbarch_tdep (gdbarch)->target_flags; |
ca3bf3bd | 649 | |
bdb4c075 MG |
650 | /* On most targets, we cannot write registers |
651 | of type "Unknown" or "Unmapped". */ | |
ca3bf3bd DJ |
652 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) |
653 | { | |
654 | if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
655 | { | |
656 | warning (_("cannot write register %s"), | |
d93859e2 | 657 | xtensa_register_name (gdbarch, regnum)); |
ca3bf3bd DJ |
658 | return; |
659 | } | |
660 | } | |
661 | ||
662 | /* Some targets cannot read TIE register files. */ | |
663 | else if (type == xtRegisterTypeTieRegfile) | |
664 | { | |
665 | /* Use 'store' to get register? */ | |
666 | if (flags & xtTargetFlagsUseFetchStore) | |
667 | { | |
668 | warning (_("cannot write register")); | |
669 | return; | |
670 | } | |
671 | ||
672 | /* On some targets (esp. simulators), we can always write | |
673 | the register. */ | |
ca3bf3bd DJ |
674 | else if ((flags & xtTargetFlagsNonVisibleRegs) == 0) |
675 | { | |
676 | warning (_("cannot write register")); | |
677 | return; | |
678 | } | |
679 | } | |
680 | ||
681 | /* We can always write mapped registers. */ | |
682 | else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState) | |
683 | { | |
9c9acae0 | 684 | xtensa_register_write_masked (regcache, reg, buffer); |
ca3bf3bd DJ |
685 | return; |
686 | } | |
687 | ||
688 | /* Assume that we can write the register. */ | |
689 | regcache_raw_write (regcache, regnum, buffer); | |
690 | } | |
ca3bf3bd DJ |
691 | else |
692 | internal_error (__FILE__, __LINE__, | |
693 | _("invalid register number %d"), regnum); | |
694 | } | |
695 | ||
ca3bf3bd DJ |
696 | static struct reggroup *xtensa_ar_reggroup; |
697 | static struct reggroup *xtensa_user_reggroup; | |
698 | static struct reggroup *xtensa_vectra_reggroup; | |
7b871568 | 699 | static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR]; |
ca3bf3bd DJ |
700 | |
701 | static void | |
702 | xtensa_init_reggroups (void) | |
703 | { | |
704 | xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP); | |
705 | xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP); | |
706 | xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP); | |
ca3bf3bd | 707 | |
7b871568 MG |
708 | xtensa_cp[0] = reggroup_new ("cp0", USER_REGGROUP); |
709 | xtensa_cp[1] = reggroup_new ("cp1", USER_REGGROUP); | |
710 | xtensa_cp[2] = reggroup_new ("cp2", USER_REGGROUP); | |
711 | xtensa_cp[3] = reggroup_new ("cp3", USER_REGGROUP); | |
712 | xtensa_cp[4] = reggroup_new ("cp4", USER_REGGROUP); | |
713 | xtensa_cp[5] = reggroup_new ("cp5", USER_REGGROUP); | |
714 | xtensa_cp[6] = reggroup_new ("cp6", USER_REGGROUP); | |
715 | xtensa_cp[7] = reggroup_new ("cp7", USER_REGGROUP); | |
716 | } | |
ca3bf3bd DJ |
717 | |
718 | static void | |
719 | xtensa_add_reggroups (struct gdbarch *gdbarch) | |
720 | { | |
7b871568 MG |
721 | int i; |
722 | ||
723 | /* Predefined groups. */ | |
ca3bf3bd DJ |
724 | reggroup_add (gdbarch, all_reggroup); |
725 | reggroup_add (gdbarch, save_reggroup); | |
726 | reggroup_add (gdbarch, restore_reggroup); | |
727 | reggroup_add (gdbarch, system_reggroup); | |
7b871568 MG |
728 | reggroup_add (gdbarch, vector_reggroup); |
729 | reggroup_add (gdbarch, general_reggroup); | |
730 | reggroup_add (gdbarch, float_reggroup); | |
731 | ||
732 | /* Xtensa-specific groups. */ | |
733 | reggroup_add (gdbarch, xtensa_ar_reggroup); | |
734 | reggroup_add (gdbarch, xtensa_user_reggroup); | |
735 | reggroup_add (gdbarch, xtensa_vectra_reggroup); | |
ca3bf3bd | 736 | |
7b871568 MG |
737 | for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++) |
738 | reggroup_add (gdbarch, xtensa_cp[i]); | |
ca3bf3bd DJ |
739 | } |
740 | ||
7b871568 MG |
741 | static int |
742 | xtensa_coprocessor_register_group (struct reggroup *group) | |
743 | { | |
744 | int i; | |
745 | ||
746 | for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++) | |
747 | if (group == xtensa_cp[i]) | |
748 | return i; | |
749 | ||
750 | return -1; | |
751 | } | |
ca3bf3bd DJ |
752 | |
753 | #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \ | |
754 | | XTENSA_REGISTER_FLAGS_WRITABLE \ | |
755 | | XTENSA_REGISTER_FLAGS_VOLATILE) | |
756 | ||
757 | #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \ | |
758 | | XTENSA_REGISTER_FLAGS_WRITABLE) | |
759 | ||
760 | static int | |
761 | xtensa_register_reggroup_p (struct gdbarch *gdbarch, | |
762 | int regnum, | |
763 | struct reggroup *group) | |
764 | { | |
6b50c0b0 | 765 | xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; |
ca3bf3bd DJ |
766 | xtensa_register_type_t type = reg->type; |
767 | xtensa_register_group_t rg = reg->group; | |
7b871568 | 768 | int cp_number; |
ca3bf3bd DJ |
769 | |
770 | /* First, skip registers that are not visible to this target | |
771 | (unknown and unmapped registers when not using ISS). */ | |
772 | ||
773 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) | |
774 | return 0; | |
775 | if (group == all_reggroup) | |
776 | return 1; | |
777 | if (group == xtensa_ar_reggroup) | |
778 | return rg & xtRegisterGroupAddrReg; | |
779 | if (group == xtensa_user_reggroup) | |
780 | return rg & xtRegisterGroupUser; | |
781 | if (group == float_reggroup) | |
782 | return rg & xtRegisterGroupFloat; | |
783 | if (group == general_reggroup) | |
784 | return rg & xtRegisterGroupGeneral; | |
785 | if (group == float_reggroup) | |
786 | return rg & xtRegisterGroupFloat; | |
787 | if (group == system_reggroup) | |
788 | return rg & xtRegisterGroupState; | |
789 | if (group == vector_reggroup || group == xtensa_vectra_reggroup) | |
790 | return rg & xtRegisterGroupVectra; | |
791 | if (group == save_reggroup || group == restore_reggroup) | |
6b50c0b0 | 792 | return (regnum < gdbarch_num_regs (gdbarch) |
ca3bf3bd | 793 | && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID); |
7b871568 MG |
794 | if ((cp_number = xtensa_coprocessor_register_group (group)) >= 0) |
795 | return rg & (xtRegisterGroupCP0 << cp_number); | |
ca3bf3bd DJ |
796 | else |
797 | return 1; | |
798 | } | |
799 | ||
800 | ||
ca3bf3bd DJ |
801 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
802 | in the general-purpose register set REGSET to register cache | |
bdb4c075 | 803 | REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */ |
ca3bf3bd DJ |
804 | |
805 | static void | |
806 | xtensa_supply_gregset (const struct regset *regset, | |
807 | struct regcache *rc, | |
808 | int regnum, | |
809 | const void *gregs, | |
810 | size_t len) | |
811 | { | |
812 | const xtensa_elf_gregset_t *regs = gregs; | |
6b50c0b0 | 813 | struct gdbarch *gdbarch = get_regcache_arch (rc); |
ca3bf3bd DJ |
814 | int i; |
815 | ||
816 | DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...) \n", regnum); | |
817 | ||
6b50c0b0 UW |
818 | if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1) |
819 | regcache_raw_supply (rc, gdbarch_pc_regnum (gdbarch), (char *) ®s->pc); | |
820 | if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1) | |
821 | regcache_raw_supply (rc, gdbarch_ps_regnum (gdbarch), (char *) ®s->ps); | |
822 | if (regnum == gdbarch_tdep (gdbarch)->wb_regnum || regnum == -1) | |
823 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->wb_regnum, | |
304fe255 | 824 | (char *) ®s->windowbase); |
6b50c0b0 UW |
825 | if (regnum == gdbarch_tdep (gdbarch)->ws_regnum || regnum == -1) |
826 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ws_regnum, | |
304fe255 | 827 | (char *) ®s->windowstart); |
6b50c0b0 UW |
828 | if (regnum == gdbarch_tdep (gdbarch)->lbeg_regnum || regnum == -1) |
829 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lbeg_regnum, | |
304fe255 | 830 | (char *) ®s->lbeg); |
6b50c0b0 UW |
831 | if (regnum == gdbarch_tdep (gdbarch)->lend_regnum || regnum == -1) |
832 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lend_regnum, | |
304fe255 | 833 | (char *) ®s->lend); |
6b50c0b0 UW |
834 | if (regnum == gdbarch_tdep (gdbarch)->lcount_regnum || regnum == -1) |
835 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lcount_regnum, | |
304fe255 | 836 | (char *) ®s->lcount); |
6b50c0b0 UW |
837 | if (regnum == gdbarch_tdep (gdbarch)->sar_regnum || regnum == -1) |
838 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->sar_regnum, | |
304fe255 | 839 | (char *) ®s->sar); |
6b50c0b0 UW |
840 | if (regnum >=gdbarch_tdep (gdbarch)->ar_base |
841 | && regnum < gdbarch_tdep (gdbarch)->ar_base | |
842 | + gdbarch_tdep (gdbarch)->num_aregs) | |
304fe255 UW |
843 | regcache_raw_supply (rc, regnum, |
844 | (char *) ®s->ar[regnum - gdbarch_tdep | |
6b50c0b0 | 845 | (gdbarch)->ar_base]); |
ca3bf3bd DJ |
846 | else if (regnum == -1) |
847 | { | |
6b50c0b0 UW |
848 | for (i = 0; i < gdbarch_tdep (gdbarch)->num_aregs; ++i) |
849 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ar_base + i, | |
304fe255 | 850 | (char *) ®s->ar[i]); |
ca3bf3bd DJ |
851 | } |
852 | } | |
853 | ||
854 | ||
855 | /* Xtensa register set. */ | |
856 | ||
857 | static struct regset | |
858 | xtensa_gregset = | |
859 | { | |
860 | NULL, | |
861 | xtensa_supply_gregset | |
862 | }; | |
863 | ||
864 | ||
bdb4c075 MG |
865 | /* Return the appropriate register set for the core |
866 | section identified by SECT_NAME and SECT_SIZE. */ | |
ca3bf3bd DJ |
867 | |
868 | static const struct regset * | |
869 | xtensa_regset_from_core_section (struct gdbarch *core_arch, | |
870 | const char *sect_name, | |
871 | size_t sect_size) | |
872 | { | |
873 | DEBUGTRACE ("xtensa_regset_from_core_section " | |
874 | "(..., sect_name==\"%s\", sect_size==%x) \n", | |
ec20a626 | 875 | sect_name, (unsigned int) sect_size); |
ca3bf3bd DJ |
876 | |
877 | if (strcmp (sect_name, ".reg") == 0 | |
878 | && sect_size >= sizeof(xtensa_elf_gregset_t)) | |
879 | return &xtensa_gregset; | |
880 | ||
881 | return NULL; | |
882 | } | |
883 | ||
884 | ||
bdb4c075 | 885 | /* Handling frames. */ |
ca3bf3bd | 886 | |
bdb4c075 MG |
887 | /* Number of registers to save in case of Windowed ABI. */ |
888 | #define XTENSA_NUM_SAVED_AREGS 12 | |
ca3bf3bd | 889 | |
bdb4c075 MG |
890 | /* Frame cache part for Windowed ABI. */ |
891 | typedef struct xtensa_windowed_frame_cache | |
ca3bf3bd | 892 | { |
ee967b5f MG |
893 | int wb; /* WINDOWBASE of the previous frame. */ |
894 | int callsize; /* Call size of this frame. */ | |
895 | int ws; /* WINDOWSTART of the previous frame. It keeps track of | |
896 | life windows only. If there is no bit set for the | |
897 | window, that means it had been already spilled | |
898 | because of window overflow. */ | |
899 | ||
900 | /* Spilled A-registers from the previous frame. | |
901 | AREGS[i] == -1, if corresponding AR is alive. */ | |
ca3bf3bd | 902 | CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS]; |
bdb4c075 MG |
903 | } xtensa_windowed_frame_cache_t; |
904 | ||
905 | /* Call0 ABI Definitions. */ | |
906 | ||
907 | #define C0_MAXOPDS 3 /* Maximum number of operands for prologue analysis. */ | |
908 | #define C0_NREGS 16 /* Number of A-registers to track. */ | |
909 | #define C0_CLESV 12 /* Callee-saved registers are here and up. */ | |
910 | #define C0_SP 1 /* Register used as SP. */ | |
911 | #define C0_FP 15 /* Register used as FP. */ | |
912 | #define C0_RA 0 /* Register used as return address. */ | |
913 | #define C0_ARGS 2 /* Register used as first arg/retval. */ | |
914 | #define C0_NARGS 6 /* Number of A-regs for args/retvals. */ | |
915 | ||
916 | /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each | |
917 | A-register where the current content of the reg came from (in terms | |
918 | of an original reg and a constant). Negative values of c0_rt[n].fp_reg | |
919 | mean that the orignal content of the register was saved to the stack. | |
920 | c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't | |
921 | know where SP will end up until the entire prologue has been analyzed. */ | |
922 | ||
923 | #define C0_CONST -1 /* fr_reg value if register contains a constant. */ | |
924 | #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */ | |
925 | #define C0_NOSTK -1 /* to_stk value if register has not been stored. */ | |
926 | ||
927 | extern xtensa_isa xtensa_default_isa; | |
928 | ||
929 | typedef struct xtensa_c0reg | |
930 | { | |
931 | int fr_reg; /* original register from which register content | |
932 | is derived, or C0_CONST, or C0_INEXP. */ | |
933 | int fr_ofs; /* constant offset from reg, or immediate value. */ | |
934 | int to_stk; /* offset from original SP to register (4-byte aligned), | |
935 | or C0_NOSTK if register has not been saved. */ | |
936 | } xtensa_c0reg_t; | |
937 | ||
938 | ||
939 | /* Frame cache part for Call0 ABI. */ | |
940 | typedef struct xtensa_call0_frame_cache | |
941 | { | |
942 | int c0_frmsz; /* Stack frame size. */ | |
943 | int c0_hasfp; /* Current frame uses frame pointer. */ | |
944 | int fp_regnum; /* A-register used as FP. */ | |
945 | int c0_fp; /* Actual value of frame pointer. */ | |
946 | xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */ | |
947 | } xtensa_call0_frame_cache_t; | |
948 | ||
949 | typedef struct xtensa_frame_cache | |
950 | { | |
ee967b5f | 951 | CORE_ADDR base; /* Stack pointer of this frame. */ |
bdb4c075 | 952 | CORE_ADDR pc; /* PC at the entry point to the function. */ |
ee967b5f | 953 | CORE_ADDR ra; /* The raw return address (without CALLINC). */ |
9f61f19b | 954 | CORE_ADDR ps; /* The PS register of this frame. */ |
ee967b5f | 955 | CORE_ADDR prev_sp; /* Stack Pointer of the previous frame. */ |
bdb4c075 MG |
956 | int call0; /* It's a call0 framework (else windowed). */ |
957 | union | |
958 | { | |
959 | xtensa_windowed_frame_cache_t wd; /* call0 == false. */ | |
960 | xtensa_call0_frame_cache_t c0; /* call0 == true. */ | |
961 | }; | |
ca3bf3bd DJ |
962 | } xtensa_frame_cache_t; |
963 | ||
964 | ||
965 | static struct xtensa_frame_cache * | |
bdb4c075 | 966 | xtensa_alloc_frame_cache (int windowed) |
ca3bf3bd DJ |
967 | { |
968 | xtensa_frame_cache_t *cache; | |
969 | int i; | |
970 | ||
971 | DEBUGTRACE ("xtensa_alloc_frame_cache ()\n"); | |
972 | ||
973 | cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t); | |
974 | ||
975 | cache->base = 0; | |
976 | cache->pc = 0; | |
977 | cache->ra = 0; | |
ca3bf3bd | 978 | cache->ps = 0; |
ca3bf3bd | 979 | cache->prev_sp = 0; |
bdb4c075 MG |
980 | cache->call0 = !windowed; |
981 | if (cache->call0) | |
982 | { | |
983 | cache->c0.c0_frmsz = -1; | |
984 | cache->c0.c0_hasfp = 0; | |
985 | cache->c0.fp_regnum = -1; | |
986 | cache->c0.c0_fp = -1; | |
ca3bf3bd | 987 | |
bdb4c075 MG |
988 | for (i = 0; i < C0_NREGS; i++) |
989 | { | |
990 | cache->c0.c0_rt[i].fr_reg = i; | |
991 | cache->c0.c0_rt[i].fr_ofs = 0; | |
992 | cache->c0.c0_rt[i].to_stk = C0_NOSTK; | |
993 | } | |
994 | } | |
995 | else | |
996 | { | |
997 | cache->wd.wb = 0; | |
ee967b5f | 998 | cache->wd.ws = 0; |
bdb4c075 | 999 | cache->wd.callsize = -1; |
ca3bf3bd | 1000 | |
bdb4c075 MG |
1001 | for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++) |
1002 | cache->wd.aregs[i] = -1; | |
1003 | } | |
ca3bf3bd DJ |
1004 | return cache; |
1005 | } | |
1006 | ||
1007 | ||
1008 | static CORE_ADDR | |
1009 | xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) | |
1010 | { | |
1011 | return address & ~15; | |
1012 | } | |
1013 | ||
1014 | ||
1015 | static CORE_ADDR | |
1016 | xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1017 | { | |
ff7a4c00 | 1018 | gdb_byte buf[8]; |
0dfff4cb | 1019 | CORE_ADDR pc; |
ca3bf3bd | 1020 | |
a74ce742 PM |
1021 | DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n", |
1022 | host_address_to_string (next_frame)); | |
ca3bf3bd | 1023 | |
6b50c0b0 | 1024 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1025 | pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
ca3bf3bd | 1026 | |
0dfff4cb | 1027 | DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc); |
ca3bf3bd | 1028 | |
0dfff4cb | 1029 | return pc; |
ca3bf3bd DJ |
1030 | } |
1031 | ||
1032 | ||
1033 | static struct frame_id | |
5142f611 | 1034 | xtensa_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
ca3bf3bd DJ |
1035 | { |
1036 | CORE_ADDR pc, fp; | |
ca3bf3bd | 1037 | |
5142f611 | 1038 | /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */ |
ca3bf3bd | 1039 | |
5142f611 MG |
1040 | pc = get_frame_pc (this_frame); |
1041 | fp = get_frame_register_unsigned | |
1042 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1); | |
ca3bf3bd DJ |
1043 | |
1044 | /* Make dummy frame ID unique by adding a constant. */ | |
bdb4c075 | 1045 | return frame_id_build (fp + SP_ALIGNMENT, pc); |
ca3bf3bd DJ |
1046 | } |
1047 | ||
ee967b5f MG |
1048 | /* Returns the best guess about which register is a frame pointer |
1049 | for the function containing CURRENT_PC. */ | |
1050 | ||
1051 | #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */ | |
1052 | ||
1053 | static unsigned int | |
1054 | xtensa_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR current_pc) | |
1055 | { | |
1056 | #define RETURN_FP goto done | |
1057 | ||
1058 | unsigned int fp_regnum = gdbarch_tdep (gdbarch)->a0_base + 1; | |
1059 | CORE_ADDR start_addr; | |
1060 | xtensa_isa isa; | |
1061 | xtensa_insnbuf ins, slot; | |
1062 | char ibuf[XTENSA_ISA_BSZ]; | |
1063 | CORE_ADDR ia, bt, ba; | |
1064 | xtensa_format ifmt; | |
1065 | int ilen, islots, is; | |
1066 | xtensa_opcode opc; | |
1067 | const char *opcname; | |
1068 | ||
1069 | find_pc_partial_function (current_pc, NULL, &start_addr, NULL); | |
1070 | if (start_addr == 0) | |
1071 | return fp_regnum; | |
1072 | ||
1073 | if (!xtensa_default_isa) | |
1074 | xtensa_default_isa = xtensa_isa_init (0, 0); | |
1075 | isa = xtensa_default_isa; | |
1076 | gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); | |
1077 | ins = xtensa_insnbuf_alloc (isa); | |
1078 | slot = xtensa_insnbuf_alloc (isa); | |
1079 | ba = 0; | |
1080 | ||
1081 | for (ia = start_addr, bt = ia; ia < current_pc ; ia += ilen) | |
1082 | { | |
1083 | if (ia + xtensa_isa_maxlength (isa) > bt) | |
1084 | { | |
1085 | ba = ia; | |
1086 | bt = (ba + XTENSA_ISA_BSZ) < current_pc | |
1087 | ? ba + XTENSA_ISA_BSZ : current_pc; | |
1088 | read_memory (ba, ibuf, bt - ba); | |
1089 | } | |
1090 | ||
1091 | xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); | |
1092 | ifmt = xtensa_format_decode (isa, ins); | |
1093 | if (ifmt == XTENSA_UNDEFINED) | |
1094 | RETURN_FP; | |
1095 | ilen = xtensa_format_length (isa, ifmt); | |
1096 | if (ilen == XTENSA_UNDEFINED) | |
1097 | RETURN_FP; | |
1098 | islots = xtensa_format_num_slots (isa, ifmt); | |
1099 | if (islots == XTENSA_UNDEFINED) | |
1100 | RETURN_FP; | |
1101 | ||
1102 | for (is = 0; is < islots; ++is) | |
1103 | { | |
1104 | if (xtensa_format_get_slot (isa, ifmt, is, ins, slot)) | |
1105 | RETURN_FP; | |
1106 | ||
1107 | opc = xtensa_opcode_decode (isa, ifmt, is, slot); | |
1108 | if (opc == XTENSA_UNDEFINED) | |
1109 | RETURN_FP; | |
1110 | ||
1111 | opcname = xtensa_opcode_name (isa, opc); | |
1112 | ||
1113 | if (strcasecmp (opcname, "mov.n") == 0 | |
1114 | || strcasecmp (opcname, "or") == 0) | |
1115 | { | |
1116 | unsigned int register_operand; | |
1117 | ||
1118 | /* Possible candidate for setting frame pointer | |
1119 | from A1. This is what we are looking for. */ | |
1120 | ||
1121 | if (xtensa_operand_get_field (isa, opc, 1, ifmt, | |
1122 | is, slot, ®ister_operand) != 0) | |
1123 | RETURN_FP; | |
1124 | if (xtensa_operand_decode (isa, opc, 1, ®ister_operand) != 0) | |
1125 | RETURN_FP; | |
1126 | if (register_operand == 1) /* Mov{.n} FP A1. */ | |
1127 | { | |
1128 | if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, | |
1129 | ®ister_operand) != 0) | |
1130 | RETURN_FP; | |
1131 | if (xtensa_operand_decode (isa, opc, 0, | |
1132 | ®ister_operand) != 0) | |
1133 | RETURN_FP; | |
1134 | ||
1135 | fp_regnum = gdbarch_tdep (gdbarch)->a0_base + register_operand; | |
1136 | RETURN_FP; | |
1137 | } | |
1138 | } | |
1139 | ||
1140 | if ( | |
1141 | /* We have problems decoding the memory. */ | |
1142 | opcname == NULL | |
1143 | || strcasecmp (opcname, "ill") == 0 | |
1144 | || strcasecmp (opcname, "ill.n") == 0 | |
1145 | /* Hit planted breakpoint. */ | |
1146 | || strcasecmp (opcname, "break") == 0 | |
1147 | || strcasecmp (opcname, "break.n") == 0 | |
1148 | /* Flow control instructions finish prologue. */ | |
1149 | || xtensa_opcode_is_branch (isa, opc) > 0 | |
1150 | || xtensa_opcode_is_jump (isa, opc) > 0 | |
1151 | || xtensa_opcode_is_loop (isa, opc) > 0 | |
1152 | || xtensa_opcode_is_call (isa, opc) > 0 | |
1153 | || strcasecmp (opcname, "simcall") == 0 | |
1154 | || strcasecmp (opcname, "syscall") == 0) | |
1155 | /* Can not continue analysis. */ | |
1156 | RETURN_FP; | |
1157 | } | |
1158 | } | |
1159 | done: | |
1160 | xtensa_insnbuf_free(isa, slot); | |
1161 | xtensa_insnbuf_free(isa, ins); | |
1162 | return fp_regnum; | |
1163 | } | |
1164 | ||
bdb4c075 MG |
1165 | /* The key values to identify the frame using "cache" are |
1166 | ||
ee967b5f | 1167 | cache->base = SP (or best guess about FP) of this frame; |
bdb4c075 MG |
1168 | cache->pc = entry-PC (entry point of the frame function); |
1169 | cache->prev_sp = SP of the previous frame. | |
1170 | */ | |
1171 | ||
1172 | static void | |
5142f611 | 1173 | call0_frame_cache (struct frame_info *this_frame, |
bdb4c075 | 1174 | xtensa_frame_cache_t *cache, |
9f61f19b | 1175 | CORE_ADDR pc, CORE_ADDR litbase); |
ca3bf3bd DJ |
1176 | |
1177 | static struct xtensa_frame_cache * | |
5142f611 | 1178 | xtensa_frame_cache (struct frame_info *this_frame, void **this_cache) |
ca3bf3bd DJ |
1179 | { |
1180 | xtensa_frame_cache_t *cache; | |
ca3bf3bd | 1181 | CORE_ADDR ra, wb, ws, pc, sp, ps; |
5142f611 | 1182 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
ee967b5f | 1183 | unsigned int fp_regnum; |
ca3bf3bd | 1184 | char op1; |
bdb4c075 | 1185 | int windowed; |
ca3bf3bd | 1186 | |
ca3bf3bd DJ |
1187 | if (*this_cache) |
1188 | return *this_cache; | |
1189 | ||
9f61f19b MG |
1190 | ps = get_frame_register_unsigned (this_frame, gdbarch_ps_regnum (gdbarch)); |
1191 | windowed = windowing_enabled (ps); | |
bdb4c075 | 1192 | |
ca3bf3bd | 1193 | /* Get pristine xtensa-frame. */ |
bdb4c075 | 1194 | cache = xtensa_alloc_frame_cache (windowed); |
ca3bf3bd DJ |
1195 | *this_cache = cache; |
1196 | ||
9f61f19b | 1197 | pc = get_frame_register_unsigned (this_frame, gdbarch_pc_regnum (gdbarch)); |
ca3bf3bd | 1198 | |
bdb4c075 | 1199 | if (windowed) |
ca3bf3bd | 1200 | { |
bdb4c075 | 1201 | /* Get WINDOWBASE, WINDOWSTART, and PS registers. */ |
5142f611 MG |
1202 | wb = get_frame_register_unsigned (this_frame, |
1203 | gdbarch_tdep (gdbarch)->wb_regnum); | |
1204 | ws = get_frame_register_unsigned (this_frame, | |
1205 | gdbarch_tdep (gdbarch)->ws_regnum); | |
ca3bf3bd | 1206 | |
bdb4c075 | 1207 | op1 = read_memory_integer (pc, 1); |
91d8eb23 | 1208 | if (XTENSA_IS_ENTRY (gdbarch, op1)) |
ca3bf3bd | 1209 | { |
bdb4c075 | 1210 | int callinc = CALLINC (ps); |
5142f611 MG |
1211 | ra = get_frame_register_unsigned |
1212 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + callinc * 4); | |
bdb4c075 MG |
1213 | |
1214 | /* ENTRY hasn't been executed yet, therefore callsize is still 0. */ | |
1215 | cache->wd.callsize = 0; | |
1216 | cache->wd.wb = wb; | |
1217 | cache->wd.ws = ws; | |
5142f611 MG |
1218 | cache->prev_sp = get_frame_register_unsigned |
1219 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1); | |
ee967b5f MG |
1220 | |
1221 | /* This only can be the outermost frame since we are | |
1222 | just about to execute ENTRY. SP hasn't been set yet. | |
1223 | We can assume any frame size, because it does not | |
1224 | matter, and, let's fake frame base in cache. */ | |
1225 | cache->base = cache->prev_sp + 16; | |
1226 | ||
1227 | cache->pc = pc; | |
1228 | cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff); | |
1229 | cache->ps = (ps & ~PS_CALLINC_MASK) | |
1230 | | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT); | |
1231 | ||
1232 | return cache; | |
bdb4c075 MG |
1233 | } |
1234 | else | |
1235 | { | |
ee967b5f | 1236 | fp_regnum = xtensa_scan_prologue (gdbarch, pc); |
5142f611 MG |
1237 | ra = get_frame_register_unsigned (this_frame, |
1238 | gdbarch_tdep (gdbarch)->a0_base); | |
bdb4c075 | 1239 | cache->wd.callsize = WINSIZE (ra); |
304fe255 | 1240 | cache->wd.wb = (wb - cache->wd.callsize / 4) |
6b50c0b0 | 1241 | & (gdbarch_tdep (gdbarch)->num_aregs / 4 - 1); |
bdb4c075 | 1242 | cache->wd.ws = ws & ~(1 << wb); |
ca3bf3bd | 1243 | |
5142f611 | 1244 | cache->pc = get_frame_func (this_frame); |
ee967b5f MG |
1245 | cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff); |
1246 | cache->ps = (ps & ~PS_CALLINC_MASK) | |
1247 | | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT); | |
1248 | } | |
bdb4c075 MG |
1249 | |
1250 | if (cache->wd.ws == 0) | |
ca3bf3bd | 1251 | { |
bdb4c075 | 1252 | int i; |
ca3bf3bd | 1253 | |
bdb4c075 | 1254 | /* Set A0...A3. */ |
5142f611 MG |
1255 | sp = get_frame_register_unsigned |
1256 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1) - 16; | |
bdb4c075 MG |
1257 | |
1258 | for (i = 0; i < 4; i++, sp += 4) | |
1259 | { | |
1260 | cache->wd.aregs[i] = sp; | |
1261 | } | |
ca3bf3bd | 1262 | |
bdb4c075 | 1263 | if (cache->wd.callsize > 4) |
ca3bf3bd | 1264 | { |
bdb4c075 | 1265 | /* Set A4...A7/A11. */ |
ee967b5f MG |
1266 | /* Get the SP of the frame previous to the previous one. |
1267 | To achieve this, we have to dereference SP twice. */ | |
bdb4c075 | 1268 | sp = (CORE_ADDR) read_memory_integer (sp - 12, 4); |
94a0e877 | 1269 | sp = (CORE_ADDR) read_memory_integer (sp - 12, 4); |
bdb4c075 MG |
1270 | sp -= cache->wd.callsize * 4; |
1271 | ||
ee967b5f | 1272 | for ( i = 4; i < cache->wd.callsize; i++, sp += 4) |
bdb4c075 MG |
1273 | { |
1274 | cache->wd.aregs[i] = sp; | |
1275 | } | |
ca3bf3bd DJ |
1276 | } |
1277 | } | |
ca3bf3bd | 1278 | |
bdb4c075 MG |
1279 | if ((cache->prev_sp == 0) && ( ra != 0 )) |
1280 | /* If RA is equal to 0 this frame is an outermost frame. Leave | |
1281 | cache->prev_sp unchanged marking the boundary of the frame stack. */ | |
ca3bf3bd | 1282 | { |
ee967b5f | 1283 | if ((cache->wd.ws & (1 << cache->wd.wb)) == 0) |
bdb4c075 MG |
1284 | { |
1285 | /* Register window overflow already happened. | |
1286 | We can read caller's SP from the proper spill loction. */ | |
5142f611 MG |
1287 | sp = get_frame_register_unsigned |
1288 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1); | |
ee967b5f | 1289 | cache->prev_sp = read_memory_integer (sp - 12, 4); |
bdb4c075 MG |
1290 | } |
1291 | else | |
1292 | { | |
1293 | /* Read caller's frame SP directly from the previous window. */ | |
ee967b5f | 1294 | int regnum = arreg_number |
91d8eb23 | 1295 | (gdbarch, gdbarch_tdep (gdbarch)->a0_base + 1, |
304fe255 | 1296 | cache->wd.wb); |
ca3bf3bd | 1297 | |
9f61f19b | 1298 | cache->prev_sp = get_frame_register_unsigned (this_frame, regnum); |
bdb4c075 | 1299 | } |
ca3bf3bd DJ |
1300 | } |
1301 | } | |
bdb4c075 MG |
1302 | else /* Call0 framework. */ |
1303 | { | |
9f61f19b MG |
1304 | unsigned int litbase_regnum = gdbarch_tdep (gdbarch)->litbase_regnum; |
1305 | CORE_ADDR litbase = (litbase_regnum == -1) | |
1306 | ? 0 : get_frame_register_unsigned (this_frame, litbase_regnum); | |
1307 | ||
1308 | call0_frame_cache (this_frame, cache, pc, litbase); | |
ee967b5f | 1309 | fp_regnum = cache->c0.fp_regnum; |
bdb4c075 | 1310 | } |
ca3bf3bd | 1311 | |
5142f611 | 1312 | cache->base = get_frame_register_unsigned (this_frame, fp_regnum); |
ca3bf3bd | 1313 | |
ca3bf3bd DJ |
1314 | return cache; |
1315 | } | |
1316 | ||
ca3bf3bd | 1317 | static void |
5142f611 | 1318 | xtensa_frame_this_id (struct frame_info *this_frame, |
ca3bf3bd DJ |
1319 | void **this_cache, |
1320 | struct frame_id *this_id) | |
1321 | { | |
1322 | struct xtensa_frame_cache *cache = | |
5142f611 | 1323 | xtensa_frame_cache (this_frame, this_cache); |
ca3bf3bd DJ |
1324 | |
1325 | if (cache->prev_sp == 0) | |
1326 | return; | |
1327 | ||
5142f611 | 1328 | (*this_id) = frame_id_build (cache->prev_sp, cache->pc); |
bdb4c075 | 1329 | } |
ca3bf3bd | 1330 | |
5142f611 MG |
1331 | static struct value * |
1332 | xtensa_frame_prev_register (struct frame_info *this_frame, | |
ca3bf3bd | 1333 | void **this_cache, |
5142f611 | 1334 | int regnum) |
ca3bf3bd | 1335 | { |
5142f611 MG |
1336 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1337 | struct xtensa_frame_cache *cache; | |
1338 | ULONGEST saved_reg = 0; | |
ca3bf3bd DJ |
1339 | int done = 1; |
1340 | ||
5142f611 MG |
1341 | if (*this_cache == NULL) |
1342 | *this_cache = xtensa_frame_cache (this_frame, this_cache); | |
1343 | cache = *this_cache; | |
ca3bf3bd | 1344 | |
6b50c0b0 | 1345 | if (regnum ==gdbarch_pc_regnum (gdbarch)) |
bdb4c075 | 1346 | saved_reg = cache->ra; |
6b50c0b0 | 1347 | else if (regnum == gdbarch_tdep (gdbarch)->a0_base + 1) |
bdb4c075 MG |
1348 | saved_reg = cache->prev_sp; |
1349 | else if (!cache->call0) | |
ca3bf3bd | 1350 | { |
6b50c0b0 | 1351 | if (regnum == gdbarch_tdep (gdbarch)->ws_regnum) |
ee967b5f | 1352 | saved_reg = cache->wd.ws; |
6b50c0b0 | 1353 | else if (regnum == gdbarch_tdep (gdbarch)->wb_regnum) |
bdb4c075 | 1354 | saved_reg = cache->wd.wb; |
6b50c0b0 | 1355 | else if (regnum == gdbarch_ps_regnum (gdbarch)) |
bdb4c075 | 1356 | saved_reg = cache->ps; |
ca3bf3bd | 1357 | else |
bdb4c075 | 1358 | done = 0; |
ca3bf3bd | 1359 | } |
ca3bf3bd DJ |
1360 | else |
1361 | done = 0; | |
1362 | ||
1363 | if (done) | |
5142f611 | 1364 | return frame_unwind_got_constant (this_frame, regnum, saved_reg); |
ca3bf3bd | 1365 | |
bdb4c075 | 1366 | if (!cache->call0) /* Windowed ABI. */ |
ca3bf3bd | 1367 | { |
ee967b5f MG |
1368 | /* Convert A-register numbers to AR-register numbers, |
1369 | if we deal with A-register. */ | |
94a0e877 | 1370 | if (regnum >= gdbarch_tdep (gdbarch)->a0_base |
6b50c0b0 | 1371 | && regnum <= gdbarch_tdep (gdbarch)->a0_base + 15) |
ee967b5f | 1372 | regnum = arreg_number (gdbarch, regnum, cache->wd.wb); |
ca3bf3bd | 1373 | |
ee967b5f | 1374 | /* Check, if we deal with AR-register saved on stack. */ |
6b50c0b0 UW |
1375 | if (regnum >= gdbarch_tdep (gdbarch)->ar_base |
1376 | && regnum <= (gdbarch_tdep (gdbarch)->ar_base | |
1377 | + gdbarch_tdep (gdbarch)->num_aregs)) | |
bdb4c075 | 1378 | { |
ee967b5f | 1379 | int areg = areg_number (gdbarch, regnum, cache->wd.wb); |
ca3bf3bd | 1380 | |
bdb4c075 MG |
1381 | if (areg >= 0 |
1382 | && areg < XTENSA_NUM_SAVED_AREGS | |
1383 | && cache->wd.aregs[areg] != -1) | |
5142f611 MG |
1384 | return frame_unwind_got_memory (this_frame, regnum, |
1385 | cache->wd.aregs[areg]); | |
ca3bf3bd DJ |
1386 | } |
1387 | } | |
bdb4c075 MG |
1388 | else /* Call0 ABI. */ |
1389 | { | |
6b50c0b0 UW |
1390 | int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base |
1391 | && regnum <= (gdbarch_tdep (gdbarch)->ar_base | |
304fe255 | 1392 | + C0_NREGS)) |
6b50c0b0 | 1393 | ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum; |
ca3bf3bd | 1394 | |
bdb4c075 MG |
1395 | if (reg < C0_NREGS) |
1396 | { | |
1397 | CORE_ADDR spe; | |
1398 | int stkofs; | |
1399 | ||
1400 | /* If register was saved in the prologue, retrieve it. */ | |
1401 | stkofs = cache->c0.c0_rt[reg].to_stk; | |
1402 | if (stkofs != C0_NOSTK) | |
1403 | { | |
1404 | /* Determine SP on entry based on FP. */ | |
1405 | spe = cache->c0.c0_fp | |
1406 | - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs; | |
5142f611 MG |
1407 | |
1408 | return frame_unwind_got_memory (this_frame, regnum, spe + stkofs); | |
bdb4c075 MG |
1409 | } |
1410 | } | |
1411 | } | |
1412 | ||
1413 | /* All other registers have been either saved to | |
1414 | the stack or are still alive in the processor. */ | |
ca3bf3bd | 1415 | |
5142f611 | 1416 | return frame_unwind_got_register (this_frame, regnum, regnum); |
ca3bf3bd DJ |
1417 | } |
1418 | ||
1419 | ||
1420 | static const struct frame_unwind | |
5142f611 | 1421 | xtensa_unwind = |
ca3bf3bd DJ |
1422 | { |
1423 | NORMAL_FRAME, | |
1424 | xtensa_frame_this_id, | |
5142f611 MG |
1425 | xtensa_frame_prev_register, |
1426 | NULL, | |
1427 | default_frame_sniffer | |
ca3bf3bd DJ |
1428 | }; |
1429 | ||
ca3bf3bd | 1430 | static CORE_ADDR |
5142f611 | 1431 | xtensa_frame_base_address (struct frame_info *this_frame, void **this_cache) |
ca3bf3bd DJ |
1432 | { |
1433 | struct xtensa_frame_cache *cache = | |
5142f611 | 1434 | xtensa_frame_cache (this_frame, this_cache); |
ca3bf3bd DJ |
1435 | |
1436 | return cache->base; | |
1437 | } | |
1438 | ||
1439 | static const struct frame_base | |
1440 | xtensa_frame_base = | |
1441 | { | |
5142f611 | 1442 | &xtensa_unwind, |
ca3bf3bd DJ |
1443 | xtensa_frame_base_address, |
1444 | xtensa_frame_base_address, | |
1445 | xtensa_frame_base_address | |
1446 | }; | |
1447 | ||
1448 | ||
1449 | static void | |
1450 | xtensa_extract_return_value (struct type *type, | |
1451 | struct regcache *regcache, | |
1452 | void *dst) | |
1453 | { | |
6b50c0b0 | 1454 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
ca3bf3bd DJ |
1455 | bfd_byte *valbuf = dst; |
1456 | int len = TYPE_LENGTH (type); | |
1457 | ULONGEST pc, wb; | |
1458 | int callsize, areg; | |
1459 | int offset = 0; | |
1460 | ||
1461 | DEBUGTRACE ("xtensa_extract_return_value (...)\n"); | |
1462 | ||
1463 | gdb_assert(len > 0); | |
1464 | ||
6b50c0b0 | 1465 | if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
bdb4c075 MG |
1466 | { |
1467 | /* First, we have to find the caller window in the register file. */ | |
6b50c0b0 | 1468 | regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc); |
91d8eb23 | 1469 | callsize = extract_call_winsize (gdbarch, pc); |
ca3bf3bd | 1470 | |
bdb4c075 MG |
1471 | /* On Xtensa, we can return up to 4 words (or 2 for call12). */ |
1472 | if (len > (callsize > 8 ? 8 : 16)) | |
1473 | internal_error (__FILE__, __LINE__, | |
1474 | _("cannot extract return value of %d bytes long"), len); | |
ca3bf3bd | 1475 | |
bdb4c075 MG |
1476 | /* Get the register offset of the return |
1477 | register (A2) in the caller window. */ | |
304fe255 | 1478 | regcache_raw_read_unsigned |
6b50c0b0 | 1479 | (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb); |
ee967b5f | 1480 | areg = arreg_number (gdbarch, |
91d8eb23 | 1481 | gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb); |
bdb4c075 MG |
1482 | } |
1483 | else | |
1484 | { | |
1485 | /* No windowing hardware - Call0 ABI. */ | |
94a0e877 | 1486 | areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS; |
bdb4c075 | 1487 | } |
ca3bf3bd DJ |
1488 | |
1489 | DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len); | |
1490 | ||
6b50c0b0 | 1491 | if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1492 | offset = 4 - len; |
1493 | ||
1494 | for (; len > 0; len -= 4, areg++, valbuf += 4) | |
1495 | { | |
1496 | if (len < 4) | |
1497 | regcache_raw_read_part (regcache, areg, offset, len, valbuf); | |
1498 | else | |
1499 | regcache_raw_read (regcache, areg, valbuf); | |
1500 | } | |
1501 | } | |
1502 | ||
1503 | ||
1504 | static void | |
1505 | xtensa_store_return_value (struct type *type, | |
1506 | struct regcache *regcache, | |
1507 | const void *dst) | |
1508 | { | |
6b50c0b0 | 1509 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
ca3bf3bd DJ |
1510 | const bfd_byte *valbuf = dst; |
1511 | unsigned int areg; | |
1512 | ULONGEST pc, wb; | |
1513 | int callsize; | |
1514 | int len = TYPE_LENGTH (type); | |
1515 | int offset = 0; | |
1516 | ||
1517 | DEBUGTRACE ("xtensa_store_return_value (...)\n"); | |
1518 | ||
6b50c0b0 | 1519 | if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
bdb4c075 | 1520 | { |
6b50c0b0 UW |
1521 | regcache_raw_read_unsigned |
1522 | (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb); | |
1523 | regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc); | |
91d8eb23 | 1524 | callsize = extract_call_winsize (gdbarch, pc); |
ca3bf3bd | 1525 | |
bdb4c075 MG |
1526 | if (len > (callsize > 8 ? 8 : 16)) |
1527 | internal_error (__FILE__, __LINE__, | |
1528 | _("unimplemented for this length: %d"), | |
1529 | TYPE_LENGTH (type)); | |
ee967b5f MG |
1530 | areg = arreg_number (gdbarch, |
1531 | gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb); | |
ca3bf3bd | 1532 | |
bdb4c075 | 1533 | DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n", |
ca3bf3bd | 1534 | callsize, (int) wb); |
bdb4c075 MG |
1535 | } |
1536 | else | |
1537 | { | |
94a0e877 | 1538 | areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS; |
bdb4c075 | 1539 | } |
ca3bf3bd | 1540 | |
6b50c0b0 | 1541 | if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1542 | offset = 4 - len; |
1543 | ||
ca3bf3bd DJ |
1544 | for (; len > 0; len -= 4, areg++, valbuf += 4) |
1545 | { | |
1546 | if (len < 4) | |
1547 | regcache_raw_write_part (regcache, areg, offset, len, valbuf); | |
1548 | else | |
1549 | regcache_raw_write (regcache, areg, valbuf); | |
1550 | } | |
1551 | } | |
1552 | ||
1553 | ||
bdb4c075 | 1554 | static enum return_value_convention |
ca3bf3bd | 1555 | xtensa_return_value (struct gdbarch *gdbarch, |
c055b101 | 1556 | struct type *func_type, |
ca3bf3bd DJ |
1557 | struct type *valtype, |
1558 | struct regcache *regcache, | |
1559 | gdb_byte *readbuf, | |
1560 | const gdb_byte *writebuf) | |
1561 | { | |
bdb4c075 | 1562 | /* Structures up to 16 bytes are returned in registers. */ |
ca3bf3bd DJ |
1563 | |
1564 | int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT | |
1565 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
1566 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
1567 | && TYPE_LENGTH (valtype) > 16); | |
1568 | ||
1569 | if (struct_return) | |
1570 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1571 | ||
1572 | DEBUGTRACE ("xtensa_return_value(...)\n"); | |
1573 | ||
1574 | if (writebuf != NULL) | |
1575 | { | |
1576 | xtensa_store_return_value (valtype, regcache, writebuf); | |
1577 | } | |
1578 | ||
1579 | if (readbuf != NULL) | |
1580 | { | |
1581 | gdb_assert (!struct_return); | |
1582 | xtensa_extract_return_value (valtype, regcache, readbuf); | |
1583 | } | |
1584 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1585 | } | |
1586 | ||
1587 | ||
1588 | /* DUMMY FRAME */ | |
1589 | ||
1590 | static CORE_ADDR | |
1591 | xtensa_push_dummy_call (struct gdbarch *gdbarch, | |
1592 | struct value *function, | |
1593 | struct regcache *regcache, | |
1594 | CORE_ADDR bp_addr, | |
1595 | int nargs, | |
1596 | struct value **args, | |
1597 | CORE_ADDR sp, | |
1598 | int struct_return, | |
1599 | CORE_ADDR struct_addr) | |
1600 | { | |
1601 | int i; | |
1602 | int size, onstack_size; | |
ff7a4c00 | 1603 | gdb_byte *buf = (gdb_byte *) alloca (16); |
ca3bf3bd DJ |
1604 | CORE_ADDR ra, ps; |
1605 | struct argument_info | |
1606 | { | |
1607 | const bfd_byte *contents; | |
1608 | int length; | |
1609 | int onstack; /* onstack == 0 => in reg */ | |
1610 | int align; /* alignment */ | |
1611 | union | |
1612 | { | |
1613 | int offset; /* stack offset if on stack */ | |
1614 | int regno; /* regno if in register */ | |
1615 | } u; | |
1616 | }; | |
1617 | ||
1618 | struct argument_info *arg_info = | |
1619 | (struct argument_info *) alloca (nargs * sizeof (struct argument_info)); | |
1620 | ||
1621 | CORE_ADDR osp = sp; | |
1622 | ||
1623 | DEBUGTRACE ("xtensa_push_dummy_call (...)\n"); | |
1624 | ||
1625 | if (xtensa_debug_level > 3) | |
1626 | { | |
1627 | int i; | |
1628 | DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs); | |
1629 | DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, " | |
1630 | "struct_addr=0x%x\n", | |
1631 | (int) sp, (int) struct_return, (int) struct_addr); | |
1632 | ||
1633 | for (i = 0; i < nargs; i++) | |
1634 | { | |
1635 | struct value *arg = args[i]; | |
1636 | struct type *arg_type = check_typedef (value_type (arg)); | |
ec20a626 UW |
1637 | fprintf_unfiltered (gdb_stdlog, "%2d: 0x%lx %3d ", |
1638 | i, (unsigned long) arg, TYPE_LENGTH (arg_type)); | |
ca3bf3bd DJ |
1639 | switch (TYPE_CODE (arg_type)) |
1640 | { | |
1641 | case TYPE_CODE_INT: | |
1642 | fprintf_unfiltered (gdb_stdlog, "int"); | |
1643 | break; | |
1644 | case TYPE_CODE_STRUCT: | |
1645 | fprintf_unfiltered (gdb_stdlog, "struct"); | |
1646 | break; | |
1647 | default: | |
1648 | fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type)); | |
1649 | break; | |
1650 | } | |
ec20a626 UW |
1651 | fprintf_unfiltered (gdb_stdlog, " 0x%lx\n", |
1652 | (unsigned long) value_contents (arg)); | |
ca3bf3bd DJ |
1653 | } |
1654 | } | |
1655 | ||
1656 | /* First loop: collect information. | |
1657 | Cast into type_long. (This shouldn't happen often for C because | |
1658 | GDB already does this earlier.) It's possible that GDB could | |
1659 | do it all the time but it's harmless to leave this code here. */ | |
1660 | ||
1661 | size = 0; | |
1662 | onstack_size = 0; | |
1663 | i = 0; | |
1664 | ||
1665 | if (struct_return) | |
1666 | size = REGISTER_SIZE; | |
1667 | ||
1668 | for (i = 0; i < nargs; i++) | |
1669 | { | |
1670 | struct argument_info *info = &arg_info[i]; | |
1671 | struct value *arg = args[i]; | |
1672 | struct type *arg_type = check_typedef (value_type (arg)); | |
1673 | ||
1674 | switch (TYPE_CODE (arg_type)) | |
1675 | { | |
1676 | case TYPE_CODE_INT: | |
1677 | case TYPE_CODE_BOOL: | |
1678 | case TYPE_CODE_CHAR: | |
1679 | case TYPE_CODE_RANGE: | |
1680 | case TYPE_CODE_ENUM: | |
1681 | ||
1682 | /* Cast argument to long if necessary as the mask does it too. */ | |
0dfff4cb UW |
1683 | if (TYPE_LENGTH (arg_type) |
1684 | < TYPE_LENGTH (builtin_type (gdbarch)->builtin_long)) | |
ca3bf3bd | 1685 | { |
0dfff4cb | 1686 | arg_type = builtin_type (gdbarch)->builtin_long; |
ca3bf3bd DJ |
1687 | arg = value_cast (arg_type, arg); |
1688 | } | |
bdb4c075 MG |
1689 | /* Aligment is equal to the type length for the basic types. */ |
1690 | info->align = TYPE_LENGTH (arg_type); | |
ca3bf3bd DJ |
1691 | break; |
1692 | ||
1693 | case TYPE_CODE_FLT: | |
1694 | ||
1695 | /* Align doubles correctly. */ | |
0dfff4cb UW |
1696 | if (TYPE_LENGTH (arg_type) |
1697 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_double)) | |
1698 | info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_double); | |
ca3bf3bd | 1699 | else |
0dfff4cb | 1700 | info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long); |
ca3bf3bd DJ |
1701 | break; |
1702 | ||
1703 | case TYPE_CODE_STRUCT: | |
1704 | default: | |
0dfff4cb | 1705 | info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long); |
ca3bf3bd DJ |
1706 | break; |
1707 | } | |
1708 | info->length = TYPE_LENGTH (arg_type); | |
1709 | info->contents = value_contents (arg); | |
1710 | ||
1711 | /* Align size and onstack_size. */ | |
1712 | size = (size + info->align - 1) & ~(info->align - 1); | |
1713 | onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1); | |
1714 | ||
91d8eb23 | 1715 | if (size + info->length > REGISTER_SIZE * ARG_NOF (gdbarch)) |
ca3bf3bd DJ |
1716 | { |
1717 | info->onstack = 1; | |
1718 | info->u.offset = onstack_size; | |
1719 | onstack_size += info->length; | |
1720 | } | |
1721 | else | |
1722 | { | |
1723 | info->onstack = 0; | |
91d8eb23 | 1724 | info->u.regno = ARG_1ST (gdbarch) + size / REGISTER_SIZE; |
ca3bf3bd DJ |
1725 | } |
1726 | size += info->length; | |
1727 | } | |
1728 | ||
1729 | /* Adjust the stack pointer and align it. */ | |
1730 | sp = align_down (sp - onstack_size, SP_ALIGNMENT); | |
1731 | ||
bdb4c075 | 1732 | /* Simulate MOVSP, if Windowed ABI. */ |
6b50c0b0 | 1733 | if ((gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
304fe255 | 1734 | && (sp != osp)) |
ca3bf3bd DJ |
1735 | { |
1736 | read_memory (osp - 16, buf, 16); | |
1737 | write_memory (sp - 16, buf, 16); | |
1738 | } | |
1739 | ||
1740 | /* Second Loop: Load arguments. */ | |
1741 | ||
1742 | if (struct_return) | |
1743 | { | |
1744 | store_unsigned_integer (buf, REGISTER_SIZE, struct_addr); | |
91d8eb23 | 1745 | regcache_cooked_write (regcache, ARG_1ST (gdbarch), buf); |
ca3bf3bd DJ |
1746 | } |
1747 | ||
1748 | for (i = 0; i < nargs; i++) | |
1749 | { | |
1750 | struct argument_info *info = &arg_info[i]; | |
1751 | ||
1752 | if (info->onstack) | |
1753 | { | |
1754 | int n = info->length; | |
1755 | CORE_ADDR offset = sp + info->u.offset; | |
1756 | ||
1757 | /* Odd-sized structs are aligned to the lower side of a memory | |
1758 | word in big-endian mode and require a shift. This only | |
1759 | applies for structures smaller than one word. */ | |
1760 | ||
4c6b5505 | 1761 | if (n < REGISTER_SIZE |
6b50c0b0 | 1762 | && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1763 | offset += (REGISTER_SIZE - n); |
1764 | ||
1765 | write_memory (offset, info->contents, info->length); | |
1766 | ||
1767 | } | |
1768 | else | |
1769 | { | |
1770 | int n = info->length; | |
1771 | const bfd_byte *cp = info->contents; | |
1772 | int r = info->u.regno; | |
1773 | ||
1774 | /* Odd-sized structs are aligned to the lower side of registers in | |
1775 | big-endian mode and require a shift. The odd-sized leftover will | |
1776 | be at the end. Note that this is only true for structures smaller | |
1777 | than REGISTER_SIZE; for larger odd-sized structures the excess | |
1778 | will be left-aligned in the register on both endiannesses. */ | |
1779 | ||
4c6b5505 | 1780 | if (n < REGISTER_SIZE |
6b50c0b0 | 1781 | && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1782 | { |
1783 | ULONGEST v = extract_unsigned_integer (cp, REGISTER_SIZE); | |
1784 | v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT); | |
1785 | ||
1786 | store_unsigned_integer (buf, REGISTER_SIZE, v); | |
1787 | regcache_cooked_write (regcache, r, buf); | |
1788 | ||
1789 | cp += REGISTER_SIZE; | |
1790 | n -= REGISTER_SIZE; | |
1791 | r++; | |
1792 | } | |
1793 | else | |
1794 | while (n > 0) | |
1795 | { | |
ca3bf3bd DJ |
1796 | regcache_cooked_write (regcache, r, cp); |
1797 | ||
ca3bf3bd DJ |
1798 | cp += REGISTER_SIZE; |
1799 | n -= REGISTER_SIZE; | |
1800 | r++; | |
1801 | } | |
1802 | } | |
1803 | } | |
1804 | ||
ca3bf3bd | 1805 | /* Set the return address of dummy frame to the dummy address. |
bdb4c075 | 1806 | The return address for the current function (in A0) is |
ca3bf3bd DJ |
1807 | saved in the dummy frame, so we can savely overwrite A0 here. */ |
1808 | ||
6b50c0b0 | 1809 | if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
bdb4c075 MG |
1810 | { |
1811 | ra = (bp_addr & 0x3fffffff) | 0x40000000; | |
6b50c0b0 | 1812 | regcache_raw_read (regcache, gdbarch_ps_regnum (gdbarch), buf); |
bdb4c075 | 1813 | ps = extract_unsigned_integer (buf, 4) & ~0x00030000; |
304fe255 | 1814 | regcache_cooked_write_unsigned |
6b50c0b0 | 1815 | (regcache, gdbarch_tdep (gdbarch)->a0_base + 4, ra); |
bdb4c075 | 1816 | regcache_cooked_write_unsigned (regcache, |
6b50c0b0 | 1817 | gdbarch_ps_regnum (gdbarch), |
bdb4c075 | 1818 | ps | 0x00010000); |
94a0e877 MG |
1819 | |
1820 | /* All the registers have been saved. After executing | |
1821 | dummy call, they all will be restored. So it's safe | |
1822 | to modify WINDOWSTART register to make it look like there | |
1823 | is only one register window corresponding to WINDOWEBASE. */ | |
1824 | ||
1825 | regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf); | |
1826 | regcache_cooked_write_unsigned (regcache, | |
1827 | gdbarch_tdep (gdbarch)->ws_regnum, | |
1828 | 1 << extract_unsigned_integer (buf, 4)); | |
bdb4c075 MG |
1829 | } |
1830 | else | |
1831 | { | |
1832 | /* Simulate CALL0: write RA into A0 register. */ | |
304fe255 | 1833 | regcache_cooked_write_unsigned |
94a0e877 | 1834 | (regcache, gdbarch_tdep (gdbarch)->a0_base, bp_addr); |
bdb4c075 | 1835 | } |
ca3bf3bd DJ |
1836 | |
1837 | /* Set new stack pointer and return it. */ | |
304fe255 | 1838 | regcache_cooked_write_unsigned (regcache, |
6b50c0b0 | 1839 | gdbarch_tdep (gdbarch)->a0_base + 1, sp); |
ca3bf3bd DJ |
1840 | /* Make dummy frame ID unique by adding a constant. */ |
1841 | return sp + SP_ALIGNMENT; | |
1842 | } | |
1843 | ||
1844 | ||
1845 | /* Return a breakpoint for the current location of PC. We always use | |
1846 | the density version if we have density instructions (regardless of the | |
1847 | current instruction at PC), and use regular instructions otherwise. */ | |
1848 | ||
1849 | #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 } | |
1850 | #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 } | |
1851 | #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f } | |
1852 | #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 } | |
1853 | ||
bdb4c075 | 1854 | static const unsigned char * |
67d57894 MD |
1855 | xtensa_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, |
1856 | int *lenptr) | |
ca3bf3bd | 1857 | { |
ff7a4c00 MG |
1858 | static unsigned char big_breakpoint[] = BIG_BREAKPOINT; |
1859 | static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT; | |
1860 | static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT; | |
1861 | static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT; | |
ca3bf3bd DJ |
1862 | |
1863 | DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr); | |
1864 | ||
67d57894 | 1865 | if (gdbarch_tdep (gdbarch)->isa_use_density_instructions) |
ca3bf3bd | 1866 | { |
67d57894 | 1867 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1868 | { |
1869 | *lenptr = sizeof (density_big_breakpoint); | |
1870 | return density_big_breakpoint; | |
1871 | } | |
1872 | else | |
1873 | { | |
1874 | *lenptr = sizeof (density_little_breakpoint); | |
1875 | return density_little_breakpoint; | |
1876 | } | |
1877 | } | |
1878 | else | |
1879 | { | |
67d57894 | 1880 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1881 | { |
1882 | *lenptr = sizeof (big_breakpoint); | |
1883 | return big_breakpoint; | |
1884 | } | |
1885 | else | |
1886 | { | |
1887 | *lenptr = sizeof (little_breakpoint); | |
1888 | return little_breakpoint; | |
1889 | } | |
1890 | } | |
1891 | } | |
1892 | ||
bdb4c075 MG |
1893 | /* Call0 ABI support routines. */ |
1894 | ||
1895 | /* Call0 opcode class. Opcodes are preclassified according to what they | |
1896 | mean for Call0 prologue analysis, and their number of significant operands. | |
1897 | The purpose of this is to simplify prologue analysis by separating | |
1898 | instruction decoding (libisa) from the semantics of prologue analysis. */ | |
1899 | ||
1900 | typedef enum { | |
1901 | c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */ | |
1902 | c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */ | |
1903 | c0opc_flow, /* Flow control insn. */ | |
1904 | c0opc_entry, /* ENTRY indicates non-Call0 prologue. */ | |
1905 | c0opc_break, /* Debugger software breakpoints. */ | |
1906 | c0opc_add, /* Adding two registers. */ | |
1907 | c0opc_addi, /* Adding a register and an immediate. */ | |
1908 | c0opc_sub, /* Subtracting a register from a register. */ | |
1909 | c0opc_mov, /* Moving a register to a register. */ | |
1910 | c0opc_movi, /* Moving an immediate to a register. */ | |
1911 | c0opc_l32r, /* Loading a literal. */ | |
1912 | c0opc_s32i, /* Storing word at fixed offset from a base register. */ | |
1913 | c0opc_NrOf /* Number of opcode classifications. */ | |
1914 | } xtensa_insn_kind; | |
1915 | ||
1916 | ||
1917 | /* Classify an opcode based on what it means for Call0 prologue analysis. */ | |
1918 | ||
1919 | static xtensa_insn_kind | |
1920 | call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc) | |
1921 | { | |
1922 | const char *opcname; | |
1923 | xtensa_insn_kind opclass = c0opc_uninteresting; | |
1924 | ||
1925 | DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc); | |
1926 | ||
1927 | /* Get opcode name and handle special classifications. */ | |
1928 | ||
1929 | opcname = xtensa_opcode_name (isa, opc); | |
1930 | ||
1931 | if (opcname == NULL | |
1932 | || strcasecmp (opcname, "ill") == 0 | |
1933 | || strcasecmp (opcname, "ill.n") == 0) | |
1934 | opclass = c0opc_illegal; | |
1935 | else if (strcasecmp (opcname, "break") == 0 | |
1936 | || strcasecmp (opcname, "break.n") == 0) | |
1937 | opclass = c0opc_break; | |
1938 | else if (strcasecmp (opcname, "entry") == 0) | |
1939 | opclass = c0opc_entry; | |
1940 | else if (xtensa_opcode_is_branch (isa, opc) > 0 | |
1941 | || xtensa_opcode_is_jump (isa, opc) > 0 | |
1942 | || xtensa_opcode_is_loop (isa, opc) > 0 | |
1943 | || xtensa_opcode_is_call (isa, opc) > 0 | |
1944 | || strcasecmp (opcname, "simcall") == 0 | |
1945 | || strcasecmp (opcname, "syscall") == 0) | |
1946 | opclass = c0opc_flow; | |
1947 | ||
1948 | /* Also, classify specific opcodes that need to be tracked. */ | |
1949 | else if (strcasecmp (opcname, "add") == 0 | |
1950 | || strcasecmp (opcname, "add.n") == 0) | |
1951 | opclass = c0opc_add; | |
1952 | else if (strcasecmp (opcname, "addi") == 0 | |
1953 | || strcasecmp (opcname, "addi.n") == 0 | |
1954 | || strcasecmp (opcname, "addmi") == 0) | |
1955 | opclass = c0opc_addi; | |
1956 | else if (strcasecmp (opcname, "sub") == 0) | |
1957 | opclass = c0opc_sub; | |
1958 | else if (strcasecmp (opcname, "mov.n") == 0 | |
1959 | || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */ | |
1960 | opclass = c0opc_mov; | |
1961 | else if (strcasecmp (opcname, "movi") == 0 | |
1962 | || strcasecmp (opcname, "movi.n") == 0) | |
1963 | opclass = c0opc_movi; | |
1964 | else if (strcasecmp (opcname, "l32r") == 0) | |
1965 | opclass = c0opc_l32r; | |
1966 | else if (strcasecmp (opcname, "s32i") == 0 | |
1967 | || strcasecmp (opcname, "s32i.n") == 0) | |
1968 | opclass = c0opc_s32i; | |
1969 | ||
1970 | return opclass; | |
1971 | } | |
1972 | ||
1973 | /* Tracks register movement/mutation for a given operation, which may | |
1974 | be within a bundle. Updates the destination register tracking info | |
1975 | accordingly. The pc is needed only for pc-relative load instructions | |
1976 | (eg. l32r). The SP register number is needed to identify stores to | |
1977 | the stack frame. */ | |
1978 | ||
1979 | static void | |
1980 | call0_track_op (xtensa_c0reg_t dst[], xtensa_c0reg_t src[], | |
1981 | xtensa_insn_kind opclass, int nods, unsigned odv[], | |
9f61f19b | 1982 | CORE_ADDR pc, CORE_ADDR litbase, int spreg) |
bdb4c075 | 1983 | { |
9f61f19b | 1984 | unsigned litaddr, litval; |
bdb4c075 MG |
1985 | |
1986 | switch (opclass) | |
1987 | { | |
1988 | case c0opc_addi: | |
1989 | /* 3 operands: dst, src, imm. */ | |
1990 | gdb_assert (nods == 3); | |
1991 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
1992 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2]; | |
1993 | break; | |
1994 | case c0opc_add: | |
1995 | /* 3 operands: dst, src1, src2. */ | |
1996 | gdb_assert (nods == 3); | |
1997 | if (src[odv[1]].fr_reg == C0_CONST) | |
1998 | { | |
1999 | dst[odv[0]].fr_reg = src[odv[2]].fr_reg; | |
2000 | dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs; | |
2001 | } | |
2002 | else if (src[odv[2]].fr_reg == C0_CONST) | |
2003 | { | |
2004 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
2005 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs; | |
2006 | } | |
2007 | else dst[odv[0]].fr_reg = C0_INEXP; | |
2008 | break; | |
2009 | case c0opc_sub: | |
2010 | /* 3 operands: dst, src1, src2. */ | |
2011 | gdb_assert (nods == 3); | |
2012 | if (src[odv[2]].fr_reg == C0_CONST) | |
2013 | { | |
2014 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
2015 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs; | |
2016 | } | |
2017 | else dst[odv[0]].fr_reg = C0_INEXP; | |
2018 | break; | |
2019 | case c0opc_mov: | |
2020 | /* 2 operands: dst, src [, src]. */ | |
2021 | gdb_assert (nods == 2); | |
2022 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
2023 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs; | |
2024 | break; | |
2025 | case c0opc_movi: | |
2026 | /* 2 operands: dst, imm. */ | |
2027 | gdb_assert (nods == 2); | |
2028 | dst[odv[0]].fr_reg = C0_CONST; | |
2029 | dst[odv[0]].fr_ofs = odv[1]; | |
2030 | break; | |
2031 | case c0opc_l32r: | |
2032 | /* 2 operands: dst, literal offset. */ | |
2033 | gdb_assert (nods == 2); | |
bdb4c075 MG |
2034 | litaddr = litbase & 1 |
2035 | ? (litbase & ~1) + (signed)odv[1] | |
2036 | : (pc + 3 + (signed)odv[1]) & ~3; | |
2037 | litval = read_memory_integer(litaddr, 4); | |
2038 | dst[odv[0]].fr_reg = C0_CONST; | |
2039 | dst[odv[0]].fr_ofs = litval; | |
2040 | break; | |
2041 | case c0opc_s32i: | |
2042 | /* 3 operands: value, base, offset. */ | |
2043 | gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS); | |
2044 | if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */ | |
2045 | && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */ | |
2046 | && src[odv[0]].fr_reg >= 0 /* Value is from a register. */ | |
2047 | && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */ | |
2048 | && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */ | |
2049 | { | |
2050 | /* ISA encoding guarantees alignment. But, check it anyway. */ | |
2051 | gdb_assert ((odv[2] & 3) == 0); | |
2052 | dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2]; | |
2053 | } | |
2054 | break; | |
2055 | default: | |
2056 | gdb_assert (0); | |
2057 | } | |
2058 | } | |
2059 | ||
2060 | /* Analyze prologue of the function at start address to determine if it uses | |
2061 | the Call0 ABI, and if so track register moves and linear modifications | |
2062 | in the prologue up to the PC or just beyond the prologue, whichever is first. | |
2063 | An 'entry' instruction indicates non-Call0 ABI and the end of the prologue. | |
2064 | The prologue may overlap non-prologue instructions but is guaranteed to end | |
2065 | by the first flow-control instruction (jump, branch, call or return). | |
2066 | Since an optimized function may move information around and change the | |
2067 | stack frame arbitrarily during the prologue, the information is guaranteed | |
2068 | valid only at the point in the function indicated by the PC. | |
2069 | May be used to skip the prologue or identify the ABI, w/o tracking. | |
2070 | ||
2071 | Returns: Address of first instruction after prologue, or PC (whichever | |
2072 | is first), or 0, if decoding failed (in libisa). | |
2073 | Input args: | |
2074 | start Start address of function/prologue. | |
2075 | pc Program counter to stop at. Use 0 to continue to end of prologue. | |
2076 | If 0, avoids infinite run-on in corrupt code memory by bounding | |
2077 | the scan to the end of the function if that can be determined. | |
2078 | nregs Number of general registers to track (size of rt[] array). | |
2079 | InOut args: | |
2080 | rt[] Array[nregs] of xtensa_c0reg structures for register tracking info. | |
2081 | If NULL, registers are not tracked. | |
2082 | Output args: | |
2083 | call0 If != NULL, *call0 is set non-zero if Call0 ABI used, else 0 | |
2084 | (more accurately, non-zero until 'entry' insn is encountered). | |
2085 | ||
2086 | Note that these may produce useful results even if decoding fails | |
2087 | because they begin with default assumptions that analysis may change. */ | |
2088 | ||
2089 | static CORE_ADDR | |
9f61f19b | 2090 | call0_analyze_prologue (CORE_ADDR start, CORE_ADDR pc, CORE_ADDR litbase, |
bdb4c075 MG |
2091 | int nregs, xtensa_c0reg_t rt[], int *call0) |
2092 | { | |
2093 | CORE_ADDR ia; /* Current insn address in prologue. */ | |
2094 | CORE_ADDR ba = 0; /* Current address at base of insn buffer. */ | |
2095 | CORE_ADDR bt; /* Current address at top+1 of insn buffer. */ | |
2ff5e605 | 2096 | char ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue. */ |
bdb4c075 MG |
2097 | xtensa_isa isa; /* libisa ISA handle. */ |
2098 | xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */ | |
2099 | xtensa_format ifmt; /* libisa instruction format. */ | |
2100 | int ilen, islots, is; /* Instruction length, nbr slots, current slot. */ | |
2101 | xtensa_opcode opc; /* Opcode in current slot. */ | |
2102 | xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */ | |
2103 | int nods; /* Opcode number of operands. */ | |
2104 | unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */ | |
2105 | xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */ | |
2106 | int j; /* General loop counter. */ | |
2107 | int fail = 0; /* Set non-zero and exit, if decoding fails. */ | |
2108 | CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */ | |
2109 | CORE_ADDR end_pc; /* The PC for the lust function insn. */ | |
2110 | ||
2111 | struct symtab_and_line prologue_sal; | |
2112 | ||
2113 | DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n", | |
2114 | (int)start, (int)pc); | |
2115 | ||
2116 | /* Try to limit the scan to the end of the function if a non-zero pc | |
2117 | arg was not supplied to avoid probing beyond the end of valid memory. | |
2118 | If memory is full of garbage that classifies as c0opc_uninteresting. | |
2119 | If this fails (eg. if no symbols) pc ends up 0 as it was. | |
2120 | Intialize the Call0 frame and register tracking info. | |
2121 | Assume it's Call0 until an 'entry' instruction is encountered. | |
2122 | Assume we may be in the prologue until we hit a flow control instr. */ | |
2123 | ||
2124 | rtmp = NULL; | |
2125 | body_pc = INT_MAX; | |
2126 | end_pc = 0; | |
2127 | ||
2128 | /* Find out, if we have an information about the prologue from DWARF. */ | |
2129 | prologue_sal = find_pc_line (start, 0); | |
2130 | if (prologue_sal.line != 0) /* Found debug info. */ | |
2131 | body_pc = prologue_sal.end; | |
2132 | ||
2133 | /* If we are going to analyze the prologue in general without knowing about | |
2134 | the current PC, make the best assumtion for the end of the prologue. */ | |
2135 | if (pc == 0) | |
2136 | { | |
2137 | find_pc_partial_function (start, 0, NULL, &end_pc); | |
2138 | body_pc = min (end_pc, body_pc); | |
2139 | } | |
2140 | else | |
2141 | body_pc = min (pc, body_pc); | |
2142 | ||
2143 | if (call0 != NULL) | |
2144 | *call0 = 1; | |
2145 | ||
2146 | if (rt != NULL) | |
2147 | { | |
2148 | rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t)); | |
2149 | /* rt is already initialized in xtensa_alloc_frame_cache(). */ | |
2150 | } | |
2151 | else nregs = 0; | |
2152 | ||
94a0e877 MG |
2153 | if (!xtensa_default_isa) |
2154 | xtensa_default_isa = xtensa_isa_init (0, 0); | |
bdb4c075 | 2155 | isa = xtensa_default_isa; |
2ff5e605 | 2156 | gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); |
bdb4c075 MG |
2157 | ins = xtensa_insnbuf_alloc (isa); |
2158 | slot = xtensa_insnbuf_alloc (isa); | |
2159 | ||
2160 | for (ia = start, bt = ia; ia < body_pc ; ia += ilen) | |
2161 | { | |
2162 | /* (Re)fill instruction buffer from memory if necessary, but do not | |
2163 | read memory beyond PC to be sure we stay within text section | |
2164 | (this protection only works if a non-zero pc is supplied). */ | |
2165 | ||
2166 | if (ia + xtensa_isa_maxlength (isa) > bt) | |
2167 | { | |
2168 | ba = ia; | |
2ff5e605 | 2169 | bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ : body_pc; |
bdb4c075 MG |
2170 | read_memory (ba, ibuf, bt - ba); |
2171 | } | |
2172 | ||
2173 | /* Decode format information. */ | |
2174 | ||
2175 | xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); | |
2176 | ifmt = xtensa_format_decode (isa, ins); | |
2177 | if (ifmt == XTENSA_UNDEFINED) | |
2178 | { | |
2179 | fail = 1; | |
2180 | goto done; | |
2181 | } | |
2182 | ilen = xtensa_format_length (isa, ifmt); | |
2183 | if (ilen == XTENSA_UNDEFINED) | |
2184 | { | |
2185 | fail = 1; | |
2186 | goto done; | |
2187 | } | |
2188 | islots = xtensa_format_num_slots (isa, ifmt); | |
2189 | if (islots == XTENSA_UNDEFINED) | |
2190 | { | |
2191 | fail = 1; | |
2192 | goto done; | |
2193 | } | |
2194 | ||
2195 | /* Analyze a bundle or a single instruction, using a snapshot of | |
2196 | the register tracking info as input for the entire bundle so that | |
2197 | register changes do not take effect within this bundle. */ | |
ca3bf3bd | 2198 | |
bdb4c075 MG |
2199 | for (j = 0; j < nregs; ++j) |
2200 | rtmp[j] = rt[j]; | |
2201 | ||
2202 | for (is = 0; is < islots; ++is) | |
2203 | { | |
2204 | /* Decode a slot and classify the opcode. */ | |
2205 | ||
2206 | fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot); | |
2207 | if (fail) | |
2208 | goto done; | |
2209 | ||
2210 | opc = xtensa_opcode_decode (isa, ifmt, is, slot); | |
2211 | DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n", | |
2212 | (unsigned)ia, opc); | |
2213 | if (opc == XTENSA_UNDEFINED) | |
2214 | opclass = c0opc_illegal; | |
2215 | else | |
2216 | opclass = call0_classify_opcode (isa, opc); | |
2217 | ||
2218 | /* Decide whether to track this opcode, ignore it, or bail out. */ | |
2219 | ||
2220 | switch (opclass) | |
2221 | { | |
2222 | case c0opc_illegal: | |
2223 | case c0opc_break: | |
2224 | fail = 1; | |
2225 | goto done; | |
2226 | ||
2227 | case c0opc_uninteresting: | |
2228 | continue; | |
2229 | ||
2230 | case c0opc_flow: | |
2231 | goto done; | |
2232 | ||
2233 | case c0opc_entry: | |
2234 | if (call0 != NULL) | |
2235 | *call0 = 0; | |
2236 | ia += ilen; /* Skip over 'entry' insn. */ | |
2237 | goto done; | |
2238 | ||
2239 | default: | |
2240 | if (call0 != NULL) | |
2241 | *call0 = 1; | |
2242 | } | |
2243 | ||
2244 | /* Only expected opcodes should get this far. */ | |
2245 | if (rt == NULL) | |
2246 | continue; | |
2247 | ||
2248 | /* Extract and decode the operands. */ | |
2249 | nods = xtensa_opcode_num_operands (isa, opc); | |
2250 | if (nods == XTENSA_UNDEFINED) | |
2251 | { | |
2252 | fail = 1; | |
2253 | goto done; | |
2254 | } | |
2255 | ||
2256 | for (j = 0; j < nods && j < C0_MAXOPDS; ++j) | |
2257 | { | |
2258 | fail = xtensa_operand_get_field (isa, opc, j, ifmt, | |
2259 | is, slot, &odv[j]); | |
2260 | if (fail) | |
2261 | goto done; | |
2262 | ||
2263 | fail = xtensa_operand_decode (isa, opc, j, &odv[j]); | |
2264 | if (fail) | |
2265 | goto done; | |
2266 | } | |
2267 | ||
2268 | /* Check operands to verify use of 'mov' assembler macro. */ | |
2269 | if (opclass == c0opc_mov && nods == 3) | |
2270 | { | |
2271 | if (odv[2] == odv[1]) | |
2272 | nods = 2; | |
2273 | else | |
2274 | { | |
2275 | opclass = c0opc_uninteresting; | |
2276 | continue; | |
2277 | } | |
2278 | } | |
2279 | ||
2280 | /* Track register movement and modification for this operation. */ | |
9f61f19b | 2281 | call0_track_op (rt, rtmp, opclass, nods, odv, ia, litbase, 1); |
bdb4c075 MG |
2282 | } |
2283 | } | |
2284 | done: | |
2285 | DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n", | |
2286 | (unsigned)ia, fail ? "failed" : "succeeded"); | |
2287 | xtensa_insnbuf_free(isa, slot); | |
2288 | xtensa_insnbuf_free(isa, ins); | |
2289 | return fail ? 0 : ia; | |
2290 | } | |
2291 | ||
5142f611 | 2292 | /* Initialize frame cache for the current frame in CALL0 ABI. */ |
bdb4c075 MG |
2293 | |
2294 | static void | |
5142f611 | 2295 | call0_frame_cache (struct frame_info *this_frame, |
9f61f19b | 2296 | xtensa_frame_cache_t *cache, CORE_ADDR pc, CORE_ADDR litbase) |
bdb4c075 | 2297 | { |
5142f611 | 2298 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
bdb4c075 MG |
2299 | CORE_ADDR start_pc; /* The beginning of the function. */ |
2300 | CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */ | |
2301 | CORE_ADDR sp, fp, ra; | |
2302 | int fp_regnum, c0_hasfp, c0_frmsz, prev_sp, to_stk; | |
2303 | ||
2304 | /* Find the beginning of the prologue of the function containing the PC | |
2305 | and analyze it up to the PC or the end of the prologue. */ | |
2306 | ||
2307 | if (find_pc_partial_function (pc, NULL, &start_pc, NULL)) | |
2308 | { | |
9f61f19b | 2309 | body_pc = call0_analyze_prologue (start_pc, pc, litbase, C0_NREGS, |
bdb4c075 MG |
2310 | &cache->c0.c0_rt[0], |
2311 | &cache->call0); | |
2312 | } | |
2313 | ||
5142f611 MG |
2314 | sp = get_frame_register_unsigned |
2315 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1); | |
bdb4c075 MG |
2316 | fp = sp; /* Assume FP == SP until proven otherwise. */ |
2317 | ||
2318 | /* Get the frame information and FP (if used) at the current PC. | |
2319 | If PC is in the prologue, the prologue analysis is more reliable | |
2320 | than DWARF info. We don't not know for sure if PC is in the prologue, | |
2321 | but we know no calls have yet taken place, so we can almost | |
2322 | certainly rely on the prologue analysis. */ | |
2323 | ||
2324 | if (body_pc <= pc) | |
2325 | { | |
2326 | /* Prologue analysis was successful up to the PC. | |
2327 | It includes the cases when PC == START_PC. */ | |
2328 | c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP; | |
2329 | /* c0_hasfp == true means there is a frame pointer because | |
2330 | we analyzed the prologue and found that cache->c0.c0_rt[C0_FP] | |
2331 | was derived from SP. Otherwise, it would be C0_FP. */ | |
2332 | fp_regnum = c0_hasfp ? C0_FP : C0_SP; | |
2333 | c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs; | |
6b50c0b0 | 2334 | fp_regnum += gdbarch_tdep (gdbarch)->a0_base; |
bdb4c075 MG |
2335 | } |
2336 | else /* No data from the prologue analysis. */ | |
2337 | { | |
2338 | c0_hasfp = 0; | |
6b50c0b0 | 2339 | fp_regnum = gdbarch_tdep (gdbarch)->a0_base + C0_SP; |
bdb4c075 MG |
2340 | c0_frmsz = 0; |
2341 | start_pc = pc; | |
2342 | } | |
2343 | ||
2344 | prev_sp = fp + c0_frmsz; | |
2345 | ||
2346 | /* Frame size from debug info or prologue tracking does not account for | |
2347 | alloca() and other dynamic allocations. Adjust frame size by FP - SP. */ | |
2348 | if (c0_hasfp) | |
2349 | { | |
5142f611 | 2350 | fp = get_frame_register_unsigned (this_frame, fp_regnum); |
bdb4c075 MG |
2351 | |
2352 | /* Recalculate previous SP. */ | |
2353 | prev_sp = fp + c0_frmsz; | |
2354 | /* Update the stack frame size. */ | |
2355 | c0_frmsz += fp - sp; | |
2356 | } | |
2357 | ||
2358 | /* Get the return address (RA) from the stack if saved, | |
2359 | or try to get it from a register. */ | |
2360 | ||
2361 | to_stk = cache->c0.c0_rt[C0_RA].to_stk; | |
2362 | if (to_stk != C0_NOSTK) | |
2363 | ra = (CORE_ADDR) | |
2364 | read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk, 4); | |
2365 | ||
2366 | else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST | |
2367 | && cache->c0.c0_rt[C0_RA].fr_ofs == 0) | |
2368 | { | |
2369 | /* Special case for terminating backtrace at a function that wants to | |
2370 | be seen as the outermost. Such a function will clear it's RA (A0) | |
2371 | register to 0 in the prologue instead of saving its original value. */ | |
2372 | ra = 0; | |
2373 | } | |
2374 | else | |
2375 | { | |
2376 | /* RA was copied to another register or (before any function call) may | |
2377 | still be in the original RA register. This is not always reliable: | |
2378 | even in a leaf function, register tracking stops after prologue, and | |
2379 | even in prologue, non-prologue instructions (not tracked) may overwrite | |
2380 | RA or any register it was copied to. If likely in prologue or before | |
2381 | any call, use retracking info and hope for the best (compiler should | |
2382 | have saved RA in stack if not in a leaf function). If not in prologue, | |
2383 | too bad. */ | |
2384 | ||
2385 | int i; | |
2386 | for (i = 0; | |
2387 | (i < C0_NREGS) && | |
2388 | (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA); | |
2389 | ++i); | |
2390 | if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA) | |
2391 | i = C0_RA; | |
5142f611 | 2392 | if (i < C0_NREGS) |
bdb4c075 | 2393 | { |
5142f611 MG |
2394 | ra = get_frame_register_unsigned |
2395 | (this_frame, | |
2396 | gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_rt[i].fr_reg); | |
bdb4c075 MG |
2397 | } |
2398 | else ra = 0; | |
2399 | } | |
2400 | ||
2401 | cache->pc = start_pc; | |
2402 | cache->ra = ra; | |
2403 | /* RA == 0 marks the outermost frame. Do not go past it. */ | |
2404 | cache->prev_sp = (ra != 0) ? prev_sp : 0; | |
2405 | cache->c0.fp_regnum = fp_regnum; | |
2406 | cache->c0.c0_frmsz = c0_frmsz; | |
2407 | cache->c0.c0_hasfp = c0_hasfp; | |
2408 | cache->c0.c0_fp = fp; | |
2409 | } | |
2410 | ||
2411 | ||
2412 | /* Skip function prologue. | |
2413 | ||
2414 | Return the pc of the first instruction after prologue. GDB calls this to | |
2415 | find the address of the first line of the function or (if there is no line | |
2416 | number information) to skip the prologue for planting breakpoints on | |
2417 | function entries. Use debug info (if present) or prologue analysis to skip | |
2418 | the prologue to achieve reliable debugging behavior. For windowed ABI, | |
2419 | only the 'entry' instruction is skipped. It is not strictly necessary to | |
2420 | skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to | |
2421 | backtrace at any point in the prologue, however certain potential hazards | |
2422 | are avoided and a more "normal" debugging experience is ensured by | |
2423 | skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG). | |
2424 | For example, if we don't skip the prologue: | |
2425 | - Some args may not yet have been saved to the stack where the debug | |
2426 | info expects to find them (true anyway when only 'entry' is skipped); | |
2427 | - Software breakpoints ('break' instrs) may not have been unplanted | |
2428 | when the prologue analysis is done on initializing the frame cache, | |
2429 | and breaks in the prologue will throw off the analysis. | |
ca3bf3bd DJ |
2430 | |
2431 | If we have debug info ( line-number info, in particular ) we simply skip | |
2432 | the code associated with the first function line effectively skipping | |
bdb4c075 | 2433 | the prologue code. It works even in cases like |
ca3bf3bd DJ |
2434 | |
2435 | int main() | |
2436 | { int local_var = 1; | |
2437 | .... | |
2438 | } | |
2439 | ||
2440 | because, for this source code, both Xtensa compilers will generate two | |
2441 | separate entries ( with the same line number ) in dwarf line-number | |
2442 | section to make sure there is a boundary between the prologue code and | |
2443 | the rest of the function. | |
2444 | ||
bdb4c075 MG |
2445 | If there is no debug info, we need to analyze the code. */ |
2446 | ||
2447 | /* #define DONT_SKIP_PROLOGUE */ | |
ca3bf3bd | 2448 | |
63807e1d | 2449 | static CORE_ADDR |
6093d2eb | 2450 | xtensa_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
ca3bf3bd | 2451 | { |
bdb4c075 MG |
2452 | struct symtab_and_line prologue_sal; |
2453 | CORE_ADDR body_pc; | |
2454 | ||
ca3bf3bd DJ |
2455 | DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc); |
2456 | ||
bdb4c075 MG |
2457 | #if DONT_SKIP_PROLOGUE |
2458 | return start_pc; | |
2459 | #endif | |
2460 | ||
2461 | /* Try to find first body line from debug info. */ | |
2462 | ||
2463 | prologue_sal = find_pc_line (start_pc, 0); | |
2464 | if (prologue_sal.line != 0) /* Found debug info. */ | |
ca3bf3bd | 2465 | { |
bdb4c075 MG |
2466 | /* In Call0, it is possible to have a function with only one instruction |
2467 | ('ret') resulting from a 1-line optimized function that does nothing. | |
2468 | In that case, prologue_sal.end may actually point to the start of the | |
2469 | next function in the text section, causing a breakpoint to be set at | |
2470 | the wrong place. Check if the end address is in a different function, | |
2471 | and if so return the start PC. We know we have symbol info. */ | |
ca3bf3bd | 2472 | |
bdb4c075 MG |
2473 | CORE_ADDR end_func; |
2474 | ||
2475 | find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL); | |
2476 | if (end_func != start_pc) | |
ca3bf3bd DJ |
2477 | return start_pc; |
2478 | ||
bdb4c075 | 2479 | return prologue_sal.end; |
ca3bf3bd | 2480 | } |
ca3bf3bd | 2481 | |
bdb4c075 | 2482 | /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */ |
9f61f19b | 2483 | body_pc = call0_analyze_prologue(start_pc, 0, 0, 0, NULL, NULL); |
bdb4c075 MG |
2484 | return body_pc != 0 ? body_pc : start_pc; |
2485 | } | |
ca3bf3bd DJ |
2486 | |
2487 | /* Verify the current configuration. */ | |
ca3bf3bd DJ |
2488 | static void |
2489 | xtensa_verify_config (struct gdbarch *gdbarch) | |
2490 | { | |
2491 | struct ui_file *log; | |
2492 | struct cleanup *cleanups; | |
2493 | struct gdbarch_tdep *tdep; | |
2494 | long dummy; | |
2495 | char *buf; | |
2496 | ||
2497 | tdep = gdbarch_tdep (gdbarch); | |
2498 | log = mem_fileopen (); | |
2499 | cleanups = make_cleanup_ui_file_delete (log); | |
2500 | ||
2501 | /* Verify that we got a reasonable number of AREGS. */ | |
2502 | if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs) | |
bdb4c075 MG |
2503 | fprintf_unfiltered (log, _("\ |
2504 | \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"), | |
2505 | tdep->num_aregs); | |
ca3bf3bd DJ |
2506 | |
2507 | /* Verify that certain registers exist. */ | |
bdb4c075 | 2508 | |
ca3bf3bd | 2509 | if (tdep->pc_regnum == -1) |
bdb4c075 MG |
2510 | fprintf_unfiltered (log, _("\n\tpc_regnum: No PC register")); |
2511 | if (tdep->isa_use_exceptions && tdep->ps_regnum == -1) | |
2512 | fprintf_unfiltered (log, _("\n\tps_regnum: No PS register")); | |
2513 | ||
2514 | if (tdep->isa_use_windowed_registers) | |
2515 | { | |
2516 | if (tdep->wb_regnum == -1) | |
2517 | fprintf_unfiltered (log, _("\n\twb_regnum: No WB register")); | |
2518 | if (tdep->ws_regnum == -1) | |
2519 | fprintf_unfiltered (log, _("\n\tws_regnum: No WS register")); | |
2520 | if (tdep->ar_base == -1) | |
2521 | fprintf_unfiltered (log, _("\n\tar_base: No AR registers")); | |
2522 | } | |
2523 | ||
ca3bf3bd | 2524 | if (tdep->a0_base == -1) |
bdb4c075 | 2525 | fprintf_unfiltered (log, _("\n\ta0_base: No Ax registers")); |
ca3bf3bd DJ |
2526 | |
2527 | buf = ui_file_xstrdup (log, &dummy); | |
2528 | make_cleanup (xfree, buf); | |
2529 | if (strlen (buf) > 0) | |
2530 | internal_error (__FILE__, __LINE__, | |
2531 | _("the following are invalid: %s"), buf); | |
2532 | do_cleanups (cleanups); | |
2533 | } | |
2534 | ||
94a0e877 MG |
2535 | |
2536 | /* Derive specific register numbers from the array of registers. */ | |
2537 | ||
63807e1d | 2538 | static void |
94a0e877 MG |
2539 | xtensa_derive_tdep (struct gdbarch_tdep *tdep) |
2540 | { | |
2541 | xtensa_register_t* rmap; | |
2542 | int n, max_size = 4; | |
2543 | ||
2544 | tdep->num_regs = 0; | |
2545 | tdep->num_nopriv_regs = 0; | |
2546 | ||
2547 | /* Special registers 0..255 (core). */ | |
2548 | #define XTENSA_DBREGN_SREG(n) (0x0200+(n)) | |
2549 | ||
2550 | for (rmap = tdep->regmap, n = 0; rmap->target_number != -1; n++, rmap++) | |
2551 | { | |
2552 | if (rmap->target_number == 0x0020) | |
2553 | tdep->pc_regnum = n; | |
2554 | else if (rmap->target_number == 0x0100) | |
2555 | tdep->ar_base = n; | |
2556 | else if (rmap->target_number == 0x0000) | |
2557 | tdep->a0_base = n; | |
2558 | else if (rmap->target_number == XTENSA_DBREGN_SREG(72)) | |
2559 | tdep->wb_regnum = n; | |
2560 | else if (rmap->target_number == XTENSA_DBREGN_SREG(73)) | |
2561 | tdep->ws_regnum = n; | |
2562 | else if (rmap->target_number == XTENSA_DBREGN_SREG(233)) | |
2563 | tdep->debugcause_regnum = n; | |
2564 | else if (rmap->target_number == XTENSA_DBREGN_SREG(232)) | |
2565 | tdep->exccause_regnum = n; | |
2566 | else if (rmap->target_number == XTENSA_DBREGN_SREG(238)) | |
2567 | tdep->excvaddr_regnum = n; | |
2568 | else if (rmap->target_number == XTENSA_DBREGN_SREG(0)) | |
2569 | tdep->lbeg_regnum = n; | |
2570 | else if (rmap->target_number == XTENSA_DBREGN_SREG(1)) | |
2571 | tdep->lend_regnum = n; | |
2572 | else if (rmap->target_number == XTENSA_DBREGN_SREG(2)) | |
2573 | tdep->lcount_regnum = n; | |
2574 | else if (rmap->target_number == XTENSA_DBREGN_SREG(3)) | |
2575 | tdep->sar_regnum = n; | |
2576 | else if (rmap->target_number == XTENSA_DBREGN_SREG(5)) | |
2577 | tdep->litbase_regnum = n; | |
2578 | else if (rmap->target_number == XTENSA_DBREGN_SREG(230)) | |
2579 | tdep->ps_regnum = n; | |
2580 | #if 0 | |
2581 | else if (rmap->target_number == XTENSA_DBREGN_SREG(226)) | |
2582 | tdep->interrupt_regnum = n; | |
2583 | else if (rmap->target_number == XTENSA_DBREGN_SREG(227)) | |
2584 | tdep->interrupt2_regnum = n; | |
2585 | else if (rmap->target_number == XTENSA_DBREGN_SREG(224)) | |
2586 | tdep->cpenable_regnum = n; | |
2587 | #endif | |
2588 | ||
2589 | if (rmap->byte_size > max_size) | |
2590 | max_size = rmap->byte_size; | |
2591 | if (rmap->mask != 0 && tdep->num_regs == 0) | |
2592 | tdep->num_regs = n; | |
2593 | /* Find out out how to deal with priveleged registers. | |
2594 | ||
2595 | if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0 | |
2596 | && tdep->num_nopriv_regs == 0) | |
2597 | tdep->num_nopriv_regs = n; | |
2598 | */ | |
2599 | if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0 | |
2600 | && tdep->num_regs == 0) | |
2601 | tdep->num_regs = n; | |
2602 | } | |
2603 | ||
2604 | /* Number of pseudo registers. */ | |
2605 | tdep->num_pseudo_regs = n - tdep->num_regs; | |
2606 | ||
2607 | /* Empirically determined maximum sizes. */ | |
2608 | tdep->max_register_raw_size = max_size; | |
2609 | tdep->max_register_virtual_size = max_size; | |
2610 | } | |
2611 | ||
ca3bf3bd DJ |
2612 | /* Module "constructor" function. */ |
2613 | ||
94a0e877 MG |
2614 | extern struct gdbarch_tdep xtensa_tdep; |
2615 | ||
ca3bf3bd DJ |
2616 | static struct gdbarch * |
2617 | xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2618 | { | |
2619 | struct gdbarch_tdep *tdep; | |
2620 | struct gdbarch *gdbarch; | |
2621 | struct xtensa_abi_handler *abi_handler; | |
2622 | ||
2623 | DEBUGTRACE ("gdbarch_init()\n"); | |
2624 | ||
2625 | /* We have to set the byte order before we call gdbarch_alloc. */ | |
94a0e877 | 2626 | info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE; |
ca3bf3bd | 2627 | |
94a0e877 | 2628 | tdep = &xtensa_tdep; |
ca3bf3bd | 2629 | gdbarch = gdbarch_alloc (&info, tdep); |
94a0e877 | 2630 | xtensa_derive_tdep (tdep); |
ca3bf3bd DJ |
2631 | |
2632 | /* Verify our configuration. */ | |
2633 | xtensa_verify_config (gdbarch); | |
2634 | ||
bdb4c075 | 2635 | /* Pseudo-Register read/write. */ |
ca3bf3bd DJ |
2636 | set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read); |
2637 | set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write); | |
2638 | ||
2639 | /* Set target information. */ | |
2640 | set_gdbarch_num_regs (gdbarch, tdep->num_regs); | |
2641 | set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs); | |
2642 | set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1); | |
2643 | set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum); | |
2644 | set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum); | |
2645 | ||
ba2b1c56 | 2646 | /* Renumber registers for known formats (stabs and dwarf2). */ |
ca3bf3bd | 2647 | set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); |
ca3bf3bd DJ |
2648 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); |
2649 | ||
2650 | /* We provide our own function to get register information. */ | |
2651 | set_gdbarch_register_name (gdbarch, xtensa_register_name); | |
2652 | set_gdbarch_register_type (gdbarch, xtensa_register_type); | |
2653 | ||
2654 | /* To call functions from GDB using dummy frame */ | |
2655 | set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call); | |
2656 | ||
2657 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); | |
2658 | ||
2659 | set_gdbarch_return_value (gdbarch, xtensa_return_value); | |
2660 | ||
2661 | /* Advance PC across any prologue instructions to reach "real" code. */ | |
2662 | set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue); | |
2663 | ||
2664 | /* Stack grows downward. */ | |
2665 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2666 | ||
2667 | /* Set breakpoints. */ | |
2668 | set_gdbarch_breakpoint_from_pc (gdbarch, xtensa_breakpoint_from_pc); | |
2669 | ||
2670 | /* After breakpoint instruction or illegal instruction, pc still | |
2671 | points at break instruction, so don't decrement. */ | |
2672 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
2673 | ||
2674 | /* We don't skip args. */ | |
2675 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
2676 | ||
2677 | set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc); | |
2678 | ||
2679 | set_gdbarch_frame_align (gdbarch, xtensa_frame_align); | |
2680 | ||
5142f611 | 2681 | set_gdbarch_dummy_id (gdbarch, xtensa_dummy_id); |
ca3bf3bd DJ |
2682 | |
2683 | /* Frame handling. */ | |
2684 | frame_base_set_default (gdbarch, &xtensa_frame_base); | |
5142f611 MG |
2685 | frame_unwind_append_unwinder (gdbarch, &xtensa_unwind); |
2686 | dwarf2_append_unwinders (gdbarch); | |
ca3bf3bd DJ |
2687 | |
2688 | set_gdbarch_print_insn (gdbarch, print_insn_xtensa); | |
2689 | ||
2690 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
2691 | ||
2692 | xtensa_add_reggroups (gdbarch); | |
2693 | set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p); | |
2694 | ||
2695 | set_gdbarch_regset_from_core_section (gdbarch, | |
2696 | xtensa_regset_from_core_section); | |
2697 | ||
ee967b5f MG |
2698 | set_solib_svr4_fetch_link_map_offsets |
2699 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); | |
2700 | ||
ca3bf3bd DJ |
2701 | return gdbarch; |
2702 | } | |
2703 | ||
ca3bf3bd | 2704 | static void |
6b50c0b0 | 2705 | xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
ca3bf3bd DJ |
2706 | { |
2707 | error (_("xtensa_dump_tdep(): not implemented")); | |
2708 | } | |
2709 | ||
63807e1d PA |
2710 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
2711 | extern initialize_file_ftype _initialize_xtensa_tdep; | |
2712 | ||
ca3bf3bd DJ |
2713 | void |
2714 | _initialize_xtensa_tdep (void) | |
2715 | { | |
2716 | struct cmd_list_element *c; | |
2717 | ||
2718 | gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep); | |
2719 | xtensa_init_reggroups (); | |
2720 | ||
2721 | add_setshow_zinteger_cmd ("xtensa", | |
2722 | class_maintenance, | |
2723 | &xtensa_debug_level, _("\ | |
2724 | Set Xtensa debugging."), _("\ | |
2725 | Show Xtensa debugging."), _("\ | |
2726 | When non-zero, Xtensa-specific debugging is enabled. \ | |
2727 | Can be 1, 2, 3, or 4 indicating the level of debugging."), | |
2728 | NULL, | |
2729 | NULL, | |
2730 | &setdebuglist, &showdebuglist); | |
2731 | } |