Commit | Line | Data |
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ca3bf3bd DJ |
1 | /* Target-dependent code for the Xtensa port of GDB, the GNU debugger. |
2 | ||
6aba47ca | 3 | Copyright (C) 2003, 2005, 2006, 2007 Free Software Foundation, Inc. |
ca3bf3bd DJ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
ca3bf3bd DJ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
ca3bf3bd DJ |
19 | |
20 | #include "defs.h" | |
21 | #include "frame.h" | |
22 | #include "symtab.h" | |
23 | #include "symfile.h" | |
24 | #include "objfiles.h" | |
25 | #include "gdbtypes.h" | |
26 | #include "gdbcore.h" | |
27 | #include "value.h" | |
28 | #include "dis-asm.h" | |
29 | #include "inferior.h" | |
30 | #include "floatformat.h" | |
31 | #include "regcache.h" | |
32 | #include "reggroups.h" | |
33 | #include "regset.h" | |
34 | ||
35 | #include "dummy-frame.h" | |
36 | #include "elf/dwarf2.h" | |
37 | #include "dwarf2-frame.h" | |
38 | #include "dwarf2loc.h" | |
39 | #include "frame.h" | |
40 | #include "frame-base.h" | |
41 | #include "frame-unwind.h" | |
42 | ||
43 | #include "arch-utils.h" | |
44 | #include "gdbarch.h" | |
45 | #include "remote.h" | |
46 | #include "serial.h" | |
47 | ||
48 | #include "command.h" | |
49 | #include "gdbcmd.h" | |
50 | #include "gdb_assert.h" | |
51 | ||
bdb4c075 | 52 | #include "xtensa-isa.h" |
ca3bf3bd DJ |
53 | #include "xtensa-tdep.h" |
54 | ||
55 | ||
56 | static int xtensa_debug_level = 0; | |
57 | ||
58 | #define DEBUGWARN(args...) \ | |
59 | if (xtensa_debug_level > 0) \ | |
60 | fprintf_unfiltered (gdb_stdlog, "(warn ) " args) | |
61 | ||
62 | #define DEBUGINFO(args...) \ | |
63 | if (xtensa_debug_level > 1) \ | |
64 | fprintf_unfiltered (gdb_stdlog, "(info ) " args) | |
65 | ||
66 | #define DEBUGTRACE(args...) \ | |
67 | if (xtensa_debug_level > 2) \ | |
68 | fprintf_unfiltered (gdb_stdlog, "(trace) " args) | |
69 | ||
70 | #define DEBUGVERB(args...) \ | |
71 | if (xtensa_debug_level > 3) \ | |
72 | fprintf_unfiltered (gdb_stdlog, "(verb ) " args) | |
73 | ||
74 | ||
75 | /* According to the ABI, the SP must be aligned to 16-byte boundaries. */ | |
ca3bf3bd DJ |
76 | #define SP_ALIGNMENT 16 |
77 | ||
78 | ||
bdb4c075 MG |
79 | /* On Windowed ABI, we use a6 through a11 for passing arguments |
80 | to a function called by GDB because CALL4 is used. */ | |
bdb4c075 MG |
81 | #define ARGS_NUM_REGS 6 |
82 | #define REGISTER_SIZE 4 | |
ca3bf3bd | 83 | |
ca3bf3bd | 84 | |
bdb4c075 MG |
85 | /* Extract the call size from the return address or PS register. */ |
86 | #define PS_CALLINC_SHIFT 16 | |
87 | #define PS_CALLINC_MASK 0x00030000 | |
88 | #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT) | |
89 | #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3)) | |
ca3bf3bd | 90 | |
bdb4c075 | 91 | /* ABI-independent macros. */ |
91d8eb23 MD |
92 | #define ARG_NOF(gdbarch) \ |
93 | (gdbarch_tdep (gdbarch)->call_abi \ | |
94 | == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS)) | |
95 | #define ARG_1ST(gdbarch) \ | |
96 | (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \ | |
97 | ? (gdbarch_tdep (gdbarch)->a0_base + 0) + C0_ARGS \ | |
98 | : (gdbarch_tdep (gdbarch)->a0_base + 6)) | |
ca3bf3bd DJ |
99 | |
100 | extern struct gdbarch_tdep *xtensa_config_tdep (struct gdbarch_info *); | |
101 | extern int xtensa_config_byte_order (struct gdbarch_info *); | |
102 | ||
103 | ||
104 | /* XTENSA_IS_ENTRY tests whether the first byte of an instruction | |
105 | indicates that the instruction is an ENTRY instruction. */ | |
106 | ||
91d8eb23 MD |
107 | #define XTENSA_IS_ENTRY(gdbarch, op1) \ |
108 | ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \ | |
4c6b5505 | 109 | ? ((op1) == 0x6c) : ((op1) == 0x36)) |
ca3bf3bd | 110 | |
bdb4c075 | 111 | #define XTENSA_ENTRY_LENGTH 3 |
ca3bf3bd DJ |
112 | |
113 | /* windowing_enabled() returns true, if windowing is enabled. | |
114 | WOE must be set to 1; EXCM to 0. | |
115 | Note: We assume that EXCM is always 0 for XEA1. */ | |
116 | ||
bdb4c075 MG |
117 | #define PS_WOE (1<<18) |
118 | #define PS_EXC (1<<4) | |
119 | ||
91d8eb23 MD |
120 | /* Convert a live Ax register number to the corresponding Areg number. */ |
121 | static int | |
122 | areg_number (struct gdbarch *gdbarch, int regnum, ULONGEST wb) | |
123 | { | |
124 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
125 | int areg; | |
126 | ||
127 | areg = regnum - tdep->a0_base; | |
128 | areg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT; | |
129 | areg &= tdep->num_aregs - 1; | |
130 | ||
131 | return areg + tdep->ar_base; | |
132 | } | |
133 | ||
ca3bf3bd DJ |
134 | static inline int |
135 | windowing_enabled (CORE_ADDR ps) | |
136 | { | |
bdb4c075 | 137 | return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0); |
ca3bf3bd DJ |
138 | } |
139 | ||
140 | /* Return the window size of the previous call to the function from which we | |
141 | have just returned. | |
142 | ||
143 | This function is used to extract the return value after a called function | |
bdb4c075 | 144 | has returned to the caller. On Xtensa, the register that holds the return |
ca3bf3bd DJ |
145 | value (from the perspective of the caller) depends on what call |
146 | instruction was used. For now, we are assuming that the call instruction | |
147 | precedes the current address, so we simply analyze the call instruction. | |
148 | If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4' | |
149 | method to call the inferior function. */ | |
150 | ||
151 | static int | |
91d8eb23 | 152 | extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc) |
ca3bf3bd | 153 | { |
bdb4c075 | 154 | int winsize = 4; |
ca3bf3bd | 155 | int insn; |
ff7a4c00 | 156 | gdb_byte buf[4]; |
ca3bf3bd DJ |
157 | |
158 | DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc); | |
159 | ||
160 | /* Read the previous instruction (should be a call[x]{4|8|12}. */ | |
161 | read_memory (pc-3, buf, 3); | |
162 | insn = extract_unsigned_integer (buf, 3); | |
163 | ||
164 | /* Decode call instruction: | |
165 | Little Endian | |
166 | call{0,4,8,12} OFFSET || {00,01,10,11} || 0101 | |
167 | callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000 | |
168 | Big Endian | |
169 | call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET | |
170 | callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */ | |
171 | ||
91d8eb23 | 172 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
ca3bf3bd DJ |
173 | { |
174 | if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0)) | |
bdb4c075 | 175 | winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */ |
ca3bf3bd DJ |
176 | } |
177 | else | |
178 | { | |
179 | if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03)) | |
bdb4c075 | 180 | winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */ |
ca3bf3bd DJ |
181 | } |
182 | return winsize; | |
183 | } | |
184 | ||
185 | ||
186 | /* REGISTER INFORMATION */ | |
187 | ||
188 | /* Returns the name of a register. */ | |
ca3bf3bd | 189 | static const char * |
d93859e2 | 190 | xtensa_register_name (struct gdbarch *gdbarch, int regnum) |
ca3bf3bd DJ |
191 | { |
192 | /* Return the name stored in the register map. */ | |
d93859e2 UW |
193 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch) |
194 | + gdbarch_num_pseudo_regs (gdbarch)) | |
195 | return gdbarch_tdep (gdbarch)->regmap[regnum].name; | |
ca3bf3bd | 196 | |
ca3bf3bd DJ |
197 | internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum); |
198 | return 0; | |
199 | } | |
200 | ||
bdb4c075 MG |
201 | static unsigned long |
202 | xtensa_read_register (int regnum) | |
203 | { | |
204 | ULONGEST value; | |
205 | ||
206 | regcache_raw_read_unsigned (get_current_regcache (), regnum, &value); | |
207 | return (unsigned long) value; | |
208 | } | |
ca3bf3bd DJ |
209 | |
210 | /* Return the type of a register. Create a new type, if necessary. */ | |
211 | ||
212 | static struct ctype_cache | |
213 | { | |
214 | struct ctype_cache *next; | |
215 | int size; | |
216 | struct type *virtual_type; | |
217 | } *type_entries = NULL; | |
218 | ||
219 | static struct type * | |
220 | xtensa_register_type (struct gdbarch *gdbarch, int regnum) | |
221 | { | |
222 | /* Return signed integer for ARx and Ax registers. */ | |
6b50c0b0 UW |
223 | if ((regnum >= gdbarch_tdep (gdbarch)->ar_base |
224 | && regnum < gdbarch_tdep (gdbarch)->ar_base | |
225 | + gdbarch_tdep (gdbarch)->num_aregs) | |
226 | || (regnum >= gdbarch_tdep (gdbarch)->a0_base | |
227 | && regnum < gdbarch_tdep (gdbarch)->a0_base + 16)) | |
ca3bf3bd DJ |
228 | return builtin_type_int; |
229 | ||
6b50c0b0 UW |
230 | if (regnum == gdbarch_pc_regnum (gdbarch) |
231 | || regnum == gdbarch_tdep (gdbarch)->a0_base + 1) | |
ca3bf3bd DJ |
232 | return lookup_pointer_type (builtin_type_void); |
233 | ||
234 | /* Return the stored type for all other registers. */ | |
6b50c0b0 UW |
235 | else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch) |
236 | + gdbarch_num_pseudo_regs (gdbarch)) | |
ca3bf3bd | 237 | { |
6b50c0b0 | 238 | xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; |
ca3bf3bd | 239 | |
bdb4c075 | 240 | /* Set ctype for this register (only the first time). */ |
ca3bf3bd DJ |
241 | |
242 | if (reg->ctype == 0) | |
243 | { | |
244 | struct ctype_cache *tp; | |
245 | int size = reg->byte_size; | |
246 | ||
bdb4c075 MG |
247 | /* We always use the memory representation, |
248 | even if the register width is smaller. */ | |
ca3bf3bd DJ |
249 | switch (size) |
250 | { | |
251 | case 1: | |
252 | reg->ctype = builtin_type_uint8; | |
253 | break; | |
254 | ||
255 | case 2: | |
256 | reg->ctype = builtin_type_uint16; | |
257 | break; | |
258 | ||
259 | case 4: | |
260 | reg->ctype = builtin_type_uint32; | |
261 | break; | |
262 | ||
263 | case 8: | |
264 | reg->ctype = builtin_type_uint64; | |
265 | break; | |
266 | ||
267 | case 16: | |
268 | reg->ctype = builtin_type_uint128; | |
269 | break; | |
270 | ||
271 | default: | |
272 | for (tp = type_entries; tp != NULL; tp = tp->next) | |
273 | if (tp->size == size) | |
274 | break; | |
275 | ||
276 | if (tp == NULL) | |
277 | { | |
278 | char *name = xmalloc (16); | |
279 | tp = xmalloc (sizeof (struct ctype_cache)); | |
280 | tp->next = type_entries; | |
281 | type_entries = tp; | |
282 | tp->size = size; | |
283 | ||
284 | sprintf (name, "int%d", size * 8); | |
285 | tp->virtual_type = init_type (TYPE_CODE_INT, size, | |
286 | TYPE_FLAG_UNSIGNED, name, | |
287 | NULL); | |
288 | } | |
289 | ||
290 | reg->ctype = tp->virtual_type; | |
291 | } | |
292 | } | |
293 | return reg->ctype; | |
294 | } | |
295 | ||
ca3bf3bd DJ |
296 | internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum); |
297 | return 0; | |
298 | } | |
299 | ||
300 | ||
bdb4c075 | 301 | /* Return the 'local' register number for stubs, dwarf2, etc. |
ca3bf3bd DJ |
302 | The debugging information enumerates registers starting from 0 for A0 |
303 | to n for An. So, we only have to add the base number for A0. */ | |
304 | ||
305 | static int | |
306 | xtensa_reg_to_regnum (int regnum) | |
307 | { | |
308 | int i; | |
309 | ||
310 | if (regnum >= 0 && regnum < 16) | |
304fe255 | 311 | return gdbarch_tdep (current_gdbarch)->a0_base + regnum; |
ca3bf3bd | 312 | |
f57d151a UW |
313 | for (i = 0; |
314 | i < gdbarch_num_regs (current_gdbarch) | |
315 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
316 | i++) | |
304fe255 | 317 | if (regnum == gdbarch_tdep (current_gdbarch)->regmap[i].target_number) |
ca3bf3bd DJ |
318 | return i; |
319 | ||
ca3bf3bd DJ |
320 | internal_error (__FILE__, __LINE__, |
321 | _("invalid dwarf/stabs register number %d"), regnum); | |
322 | return 0; | |
323 | } | |
324 | ||
325 | ||
bdb4c075 MG |
326 | /* Write the bits of a masked register to the various registers. |
327 | Only the masked areas of these registers are modified; the other | |
328 | fields are untouched. The size of masked registers is always less | |
329 | than or equal to 32 bits. */ | |
ca3bf3bd DJ |
330 | |
331 | static void | |
9c9acae0 UW |
332 | xtensa_register_write_masked (struct regcache *regcache, |
333 | xtensa_register_t *reg, const gdb_byte *buffer) | |
ca3bf3bd DJ |
334 | { |
335 | unsigned int value[(MAX_REGISTER_SIZE + 3) / 4]; | |
ca3bf3bd DJ |
336 | const xtensa_mask_t *mask = reg->mask; |
337 | ||
338 | int shift = 0; /* Shift for next mask (mod 32). */ | |
339 | int start, size; /* Start bit and size of current mask. */ | |
340 | ||
341 | unsigned int *ptr = value; | |
342 | unsigned int regval, m, mem = 0; | |
343 | ||
344 | int bytesize = reg->byte_size; | |
345 | int bitsize = bytesize * 8; | |
346 | int i, r; | |
347 | ||
348 | DEBUGTRACE ("xtensa_register_write_masked ()\n"); | |
349 | ||
350 | /* Copy the masked register to host byte-order. */ | |
6b50c0b0 | 351 | if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
352 | for (i = 0; i < bytesize; i++) |
353 | { | |
354 | mem >>= 8; | |
355 | mem |= (buffer[bytesize - i - 1] << 24); | |
356 | if ((i & 3) == 3) | |
357 | *ptr++ = mem; | |
358 | } | |
359 | else | |
360 | for (i = 0; i < bytesize; i++) | |
361 | { | |
362 | mem >>= 8; | |
363 | mem |= (buffer[i] << 24); | |
364 | if ((i & 3) == 3) | |
365 | *ptr++ = mem; | |
366 | } | |
367 | ||
368 | /* We might have to shift the final value: | |
369 | bytesize & 3 == 0 -> nothing to do, we use the full 32 bits, | |
370 | bytesize & 3 == x -> shift (4-x) * 8. */ | |
371 | ||
372 | *ptr = mem >> (((0 - bytesize) & 3) * 8); | |
373 | ptr = value; | |
374 | mem = *ptr; | |
375 | ||
376 | /* Write the bits to the masked areas of the other registers. */ | |
377 | for (i = 0; i < mask->count; i++) | |
378 | { | |
379 | start = mask->mask[i].bit_start; | |
380 | size = mask->mask[i].bit_size; | |
381 | regval = mem >> shift; | |
382 | ||
383 | if ((shift += size) > bitsize) | |
384 | error (_("size of all masks is larger than the register")); | |
385 | ||
386 | if (shift >= 32) | |
387 | { | |
388 | mem = *(++ptr); | |
389 | shift -= 32; | |
390 | bitsize -= 32; | |
391 | ||
392 | if (shift > 0) | |
393 | regval |= mem << (size - shift); | |
394 | } | |
395 | ||
396 | /* Make sure we have a valid register. */ | |
397 | r = mask->mask[i].reg_num; | |
398 | if (r >= 0 && size > 0) | |
399 | { | |
400 | /* Don't overwrite the unmasked areas. */ | |
9c9acae0 UW |
401 | ULONGEST old_val; |
402 | regcache_cooked_read_unsigned (regcache, r, &old_val); | |
ca3bf3bd DJ |
403 | m = 0xffffffff >> (32 - size) << start; |
404 | regval <<= start; | |
9c9acae0 UW |
405 | regval = (regval & m) | (old_val & ~m); |
406 | regcache_cooked_write_unsigned (regcache, r, regval); | |
ca3bf3bd DJ |
407 | } |
408 | } | |
409 | } | |
410 | ||
411 | ||
bdb4c075 MG |
412 | /* Read a tie state or mapped registers. Read the masked areas |
413 | of the registers and assemble them into a single value. */ | |
ca3bf3bd DJ |
414 | |
415 | static void | |
9c9acae0 UW |
416 | xtensa_register_read_masked (struct regcache *regcache, |
417 | xtensa_register_t *reg, gdb_byte *buffer) | |
ca3bf3bd DJ |
418 | { |
419 | unsigned int value[(MAX_REGISTER_SIZE + 3) / 4]; | |
ca3bf3bd DJ |
420 | const xtensa_mask_t *mask = reg->mask; |
421 | ||
422 | int shift = 0; | |
423 | int start, size; | |
424 | ||
425 | unsigned int *ptr = value; | |
426 | unsigned int regval, mem = 0; | |
427 | ||
428 | int bytesize = reg->byte_size; | |
429 | int bitsize = bytesize * 8; | |
430 | int i; | |
431 | ||
432 | DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n", | |
433 | reg->name == 0 ? "" : reg->name); | |
434 | ||
435 | /* Assemble the register from the masked areas of other registers. */ | |
436 | for (i = 0; i < mask->count; i++) | |
437 | { | |
438 | int r = mask->mask[i].reg_num; | |
9c9acae0 UW |
439 | if (r >= 0) |
440 | { | |
441 | ULONGEST val; | |
442 | regcache_cooked_read_unsigned (regcache, r, &val); | |
443 | regval = (unsigned int) val; | |
444 | } | |
445 | else | |
446 | regval = 0; | |
447 | ||
ca3bf3bd DJ |
448 | start = mask->mask[i].bit_start; |
449 | size = mask->mask[i].bit_size; | |
450 | ||
451 | regval >>= start; | |
452 | ||
453 | if (size < 32) | |
454 | regval &= (0xffffffff >> (32 - size)); | |
455 | ||
456 | mem |= regval << shift; | |
457 | ||
458 | if ((shift += size) > bitsize) | |
459 | error (_("size of all masks is larger than the register")); | |
460 | ||
461 | if (shift >= 32) | |
462 | { | |
463 | *ptr++ = mem; | |
464 | bitsize -= 32; | |
465 | shift -= 32; | |
466 | ||
467 | if (shift == 0) | |
468 | mem = 0; | |
469 | else | |
470 | mem = regval >> (size - shift); | |
471 | } | |
472 | } | |
473 | ||
474 | if (shift > 0) | |
475 | *ptr = mem; | |
476 | ||
477 | /* Copy value to target byte order. */ | |
478 | ptr = value; | |
479 | mem = *ptr; | |
480 | ||
6b50c0b0 | 481 | if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
482 | for (i = 0; i < bytesize; i++) |
483 | { | |
484 | if ((i & 3) == 0) | |
485 | mem = *ptr++; | |
486 | buffer[bytesize - i - 1] = mem & 0xff; | |
487 | mem >>= 8; | |
488 | } | |
489 | else | |
490 | for (i = 0; i < bytesize; i++) | |
491 | { | |
492 | if ((i & 3) == 0) | |
493 | mem = *ptr++; | |
494 | buffer[i] = mem & 0xff; | |
495 | mem >>= 8; | |
496 | } | |
497 | } | |
498 | ||
499 | ||
500 | /* Read pseudo registers. */ | |
501 | ||
502 | static void | |
503 | xtensa_pseudo_register_read (struct gdbarch *gdbarch, | |
504 | struct regcache *regcache, | |
505 | int regnum, | |
506 | gdb_byte *buffer) | |
507 | { | |
508 | DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n", | |
d93859e2 | 509 | regnum, xtensa_register_name (gdbarch, regnum)); |
ca3bf3bd | 510 | |
6b50c0b0 UW |
511 | if (regnum == gdbarch_num_regs (gdbarch) |
512 | + gdbarch_num_pseudo_regs (gdbarch)) | |
513 | regnum = gdbarch_tdep (gdbarch)->a0_base + 1; | |
ca3bf3bd | 514 | |
bdb4c075 | 515 | /* Read aliases a0..a15, if this is a Windowed ABI. */ |
6b50c0b0 UW |
516 | if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers |
517 | && (regnum >= gdbarch_tdep (gdbarch)->a0_base + 0) | |
518 | && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)) | |
ca3bf3bd | 519 | { |
ff7a4c00 | 520 | gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE); |
ca3bf3bd | 521 | |
6b50c0b0 | 522 | regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf); |
91d8eb23 | 523 | regnum = areg_number (gdbarch, regnum, extract_unsigned_integer (buf, 4)); |
ca3bf3bd DJ |
524 | } |
525 | ||
bdb4c075 | 526 | /* We can always read non-pseudo registers. */ |
6b50c0b0 | 527 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) |
ca3bf3bd DJ |
528 | regcache_raw_read (regcache, regnum, buffer); |
529 | ||
530 | /* Pseudo registers. */ | |
f57d151a | 531 | else if (regnum >= 0 |
6b50c0b0 UW |
532 | && regnum < gdbarch_num_regs (gdbarch) |
533 | + gdbarch_num_pseudo_regs (gdbarch)) | |
ca3bf3bd | 534 | { |
6b50c0b0 | 535 | xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; |
ca3bf3bd | 536 | xtensa_register_type_t type = reg->type; |
6b50c0b0 | 537 | int flags = gdbarch_tdep (gdbarch)->target_flags; |
ca3bf3bd | 538 | |
bdb4c075 | 539 | /* We cannot read Unknown or Unmapped registers. */ |
ca3bf3bd DJ |
540 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) |
541 | { | |
542 | if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
543 | { | |
544 | warning (_("cannot read register %s"), | |
d93859e2 | 545 | xtensa_register_name (gdbarch, regnum)); |
ca3bf3bd DJ |
546 | return; |
547 | } | |
548 | } | |
549 | ||
550 | /* Some targets cannot read TIE register files. */ | |
551 | else if (type == xtRegisterTypeTieRegfile) | |
552 | { | |
553 | /* Use 'fetch' to get register? */ | |
554 | if (flags & xtTargetFlagsUseFetchStore) | |
555 | { | |
556 | warning (_("cannot read register")); | |
557 | return; | |
558 | } | |
559 | ||
560 | /* On some targets (esp. simulators), we can always read the reg. */ | |
561 | else if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
562 | { | |
563 | warning (_("cannot read register")); | |
564 | return; | |
565 | } | |
566 | } | |
567 | ||
568 | /* We can always read mapped registers. */ | |
569 | else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState) | |
570 | { | |
9c9acae0 | 571 | xtensa_register_read_masked (regcache, reg, buffer); |
ca3bf3bd DJ |
572 | return; |
573 | } | |
574 | ||
575 | /* Assume that we can read the register. */ | |
576 | regcache_raw_read (regcache, regnum, buffer); | |
577 | } | |
ca3bf3bd DJ |
578 | else |
579 | internal_error (__FILE__, __LINE__, | |
580 | _("invalid register number %d"), regnum); | |
581 | } | |
582 | ||
583 | ||
584 | /* Write pseudo registers. */ | |
585 | ||
586 | static void | |
587 | xtensa_pseudo_register_write (struct gdbarch *gdbarch, | |
588 | struct regcache *regcache, | |
589 | int regnum, | |
590 | const gdb_byte *buffer) | |
591 | { | |
592 | DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n", | |
d93859e2 | 593 | regnum, xtensa_register_name (gdbarch, regnum)); |
ca3bf3bd | 594 | |
6b50c0b0 UW |
595 | if (regnum == gdbarch_num_regs (gdbarch) |
596 | + gdbarch_num_pseudo_regs (gdbarch)) | |
597 | regnum = gdbarch_tdep (gdbarch)->a0_base + 1; | |
ca3bf3bd | 598 | |
bdb4c075 | 599 | /* Renumber register, if aliase a0..a15 on Windowed ABI. */ |
6b50c0b0 UW |
600 | if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers |
601 | && (regnum >= gdbarch_tdep (gdbarch)->a0_base + 0) | |
602 | && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)) | |
ca3bf3bd | 603 | { |
ff7a4c00 | 604 | gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE); |
ca3bf3bd DJ |
605 | unsigned int wb; |
606 | ||
304fe255 | 607 | regcache_raw_read (regcache, |
6b50c0b0 | 608 | gdbarch_tdep (gdbarch)->wb_regnum, buf); |
91d8eb23 | 609 | regnum = areg_number (gdbarch, regnum, extract_unsigned_integer (buf, 4)); |
ca3bf3bd DJ |
610 | } |
611 | ||
612 | /* We can always write 'core' registers. | |
613 | Note: We might have converted Ax->ARy. */ | |
6b50c0b0 | 614 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) |
ca3bf3bd DJ |
615 | regcache_raw_write (regcache, regnum, buffer); |
616 | ||
617 | /* Pseudo registers. */ | |
f57d151a | 618 | else if (regnum >= 0 |
6b50c0b0 UW |
619 | && regnum < gdbarch_num_regs (gdbarch) |
620 | + gdbarch_num_pseudo_regs (gdbarch)) | |
ca3bf3bd | 621 | { |
6b50c0b0 | 622 | xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; |
ca3bf3bd | 623 | xtensa_register_type_t type = reg->type; |
6b50c0b0 | 624 | int flags = gdbarch_tdep (gdbarch)->target_flags; |
ca3bf3bd | 625 | |
bdb4c075 MG |
626 | /* On most targets, we cannot write registers |
627 | of type "Unknown" or "Unmapped". */ | |
ca3bf3bd DJ |
628 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) |
629 | { | |
630 | if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
631 | { | |
632 | warning (_("cannot write register %s"), | |
d93859e2 | 633 | xtensa_register_name (gdbarch, regnum)); |
ca3bf3bd DJ |
634 | return; |
635 | } | |
636 | } | |
637 | ||
638 | /* Some targets cannot read TIE register files. */ | |
639 | else if (type == xtRegisterTypeTieRegfile) | |
640 | { | |
641 | /* Use 'store' to get register? */ | |
642 | if (flags & xtTargetFlagsUseFetchStore) | |
643 | { | |
644 | warning (_("cannot write register")); | |
645 | return; | |
646 | } | |
647 | ||
648 | /* On some targets (esp. simulators), we can always write | |
649 | the register. */ | |
ca3bf3bd DJ |
650 | else if ((flags & xtTargetFlagsNonVisibleRegs) == 0) |
651 | { | |
652 | warning (_("cannot write register")); | |
653 | return; | |
654 | } | |
655 | } | |
656 | ||
657 | /* We can always write mapped registers. */ | |
658 | else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState) | |
659 | { | |
9c9acae0 | 660 | xtensa_register_write_masked (regcache, reg, buffer); |
ca3bf3bd DJ |
661 | return; |
662 | } | |
663 | ||
664 | /* Assume that we can write the register. */ | |
665 | regcache_raw_write (regcache, regnum, buffer); | |
666 | } | |
ca3bf3bd DJ |
667 | else |
668 | internal_error (__FILE__, __LINE__, | |
669 | _("invalid register number %d"), regnum); | |
670 | } | |
671 | ||
ca3bf3bd DJ |
672 | static struct reggroup *xtensa_ar_reggroup; |
673 | static struct reggroup *xtensa_user_reggroup; | |
674 | static struct reggroup *xtensa_vectra_reggroup; | |
7b871568 | 675 | static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR]; |
ca3bf3bd DJ |
676 | |
677 | static void | |
678 | xtensa_init_reggroups (void) | |
679 | { | |
680 | xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP); | |
681 | xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP); | |
682 | xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP); | |
ca3bf3bd | 683 | |
7b871568 MG |
684 | xtensa_cp[0] = reggroup_new ("cp0", USER_REGGROUP); |
685 | xtensa_cp[1] = reggroup_new ("cp1", USER_REGGROUP); | |
686 | xtensa_cp[2] = reggroup_new ("cp2", USER_REGGROUP); | |
687 | xtensa_cp[3] = reggroup_new ("cp3", USER_REGGROUP); | |
688 | xtensa_cp[4] = reggroup_new ("cp4", USER_REGGROUP); | |
689 | xtensa_cp[5] = reggroup_new ("cp5", USER_REGGROUP); | |
690 | xtensa_cp[6] = reggroup_new ("cp6", USER_REGGROUP); | |
691 | xtensa_cp[7] = reggroup_new ("cp7", USER_REGGROUP); | |
692 | } | |
ca3bf3bd DJ |
693 | |
694 | static void | |
695 | xtensa_add_reggroups (struct gdbarch *gdbarch) | |
696 | { | |
7b871568 MG |
697 | int i; |
698 | ||
699 | /* Predefined groups. */ | |
ca3bf3bd DJ |
700 | reggroup_add (gdbarch, all_reggroup); |
701 | reggroup_add (gdbarch, save_reggroup); | |
702 | reggroup_add (gdbarch, restore_reggroup); | |
703 | reggroup_add (gdbarch, system_reggroup); | |
7b871568 MG |
704 | reggroup_add (gdbarch, vector_reggroup); |
705 | reggroup_add (gdbarch, general_reggroup); | |
706 | reggroup_add (gdbarch, float_reggroup); | |
707 | ||
708 | /* Xtensa-specific groups. */ | |
709 | reggroup_add (gdbarch, xtensa_ar_reggroup); | |
710 | reggroup_add (gdbarch, xtensa_user_reggroup); | |
711 | reggroup_add (gdbarch, xtensa_vectra_reggroup); | |
ca3bf3bd | 712 | |
7b871568 MG |
713 | for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++) |
714 | reggroup_add (gdbarch, xtensa_cp[i]); | |
ca3bf3bd DJ |
715 | } |
716 | ||
7b871568 MG |
717 | static int |
718 | xtensa_coprocessor_register_group (struct reggroup *group) | |
719 | { | |
720 | int i; | |
721 | ||
722 | for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++) | |
723 | if (group == xtensa_cp[i]) | |
724 | return i; | |
725 | ||
726 | return -1; | |
727 | } | |
ca3bf3bd DJ |
728 | |
729 | #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \ | |
730 | | XTENSA_REGISTER_FLAGS_WRITABLE \ | |
731 | | XTENSA_REGISTER_FLAGS_VOLATILE) | |
732 | ||
733 | #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \ | |
734 | | XTENSA_REGISTER_FLAGS_WRITABLE) | |
735 | ||
736 | static int | |
737 | xtensa_register_reggroup_p (struct gdbarch *gdbarch, | |
738 | int regnum, | |
739 | struct reggroup *group) | |
740 | { | |
6b50c0b0 | 741 | xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; |
ca3bf3bd DJ |
742 | xtensa_register_type_t type = reg->type; |
743 | xtensa_register_group_t rg = reg->group; | |
7b871568 | 744 | int cp_number; |
ca3bf3bd DJ |
745 | |
746 | /* First, skip registers that are not visible to this target | |
747 | (unknown and unmapped registers when not using ISS). */ | |
748 | ||
749 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) | |
750 | return 0; | |
751 | if (group == all_reggroup) | |
752 | return 1; | |
753 | if (group == xtensa_ar_reggroup) | |
754 | return rg & xtRegisterGroupAddrReg; | |
755 | if (group == xtensa_user_reggroup) | |
756 | return rg & xtRegisterGroupUser; | |
757 | if (group == float_reggroup) | |
758 | return rg & xtRegisterGroupFloat; | |
759 | if (group == general_reggroup) | |
760 | return rg & xtRegisterGroupGeneral; | |
761 | if (group == float_reggroup) | |
762 | return rg & xtRegisterGroupFloat; | |
763 | if (group == system_reggroup) | |
764 | return rg & xtRegisterGroupState; | |
765 | if (group == vector_reggroup || group == xtensa_vectra_reggroup) | |
766 | return rg & xtRegisterGroupVectra; | |
767 | if (group == save_reggroup || group == restore_reggroup) | |
6b50c0b0 | 768 | return (regnum < gdbarch_num_regs (gdbarch) |
ca3bf3bd | 769 | && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID); |
7b871568 MG |
770 | if ((cp_number = xtensa_coprocessor_register_group (group)) >= 0) |
771 | return rg & (xtRegisterGroupCP0 << cp_number); | |
ca3bf3bd DJ |
772 | else |
773 | return 1; | |
774 | } | |
775 | ||
776 | ||
ca3bf3bd DJ |
777 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
778 | in the general-purpose register set REGSET to register cache | |
bdb4c075 | 779 | REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */ |
ca3bf3bd DJ |
780 | |
781 | static void | |
782 | xtensa_supply_gregset (const struct regset *regset, | |
783 | struct regcache *rc, | |
784 | int regnum, | |
785 | const void *gregs, | |
786 | size_t len) | |
787 | { | |
788 | const xtensa_elf_gregset_t *regs = gregs; | |
6b50c0b0 | 789 | struct gdbarch *gdbarch = get_regcache_arch (rc); |
ca3bf3bd DJ |
790 | int i; |
791 | ||
792 | DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...) \n", regnum); | |
793 | ||
6b50c0b0 UW |
794 | if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1) |
795 | regcache_raw_supply (rc, gdbarch_pc_regnum (gdbarch), (char *) ®s->pc); | |
796 | if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1) | |
797 | regcache_raw_supply (rc, gdbarch_ps_regnum (gdbarch), (char *) ®s->ps); | |
798 | if (regnum == gdbarch_tdep (gdbarch)->wb_regnum || regnum == -1) | |
799 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->wb_regnum, | |
304fe255 | 800 | (char *) ®s->windowbase); |
6b50c0b0 UW |
801 | if (regnum == gdbarch_tdep (gdbarch)->ws_regnum || regnum == -1) |
802 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ws_regnum, | |
304fe255 | 803 | (char *) ®s->windowstart); |
6b50c0b0 UW |
804 | if (regnum == gdbarch_tdep (gdbarch)->lbeg_regnum || regnum == -1) |
805 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lbeg_regnum, | |
304fe255 | 806 | (char *) ®s->lbeg); |
6b50c0b0 UW |
807 | if (regnum == gdbarch_tdep (gdbarch)->lend_regnum || regnum == -1) |
808 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lend_regnum, | |
304fe255 | 809 | (char *) ®s->lend); |
6b50c0b0 UW |
810 | if (regnum == gdbarch_tdep (gdbarch)->lcount_regnum || regnum == -1) |
811 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lcount_regnum, | |
304fe255 | 812 | (char *) ®s->lcount); |
6b50c0b0 UW |
813 | if (regnum == gdbarch_tdep (gdbarch)->sar_regnum || regnum == -1) |
814 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->sar_regnum, | |
304fe255 | 815 | (char *) ®s->sar); |
6b50c0b0 UW |
816 | if (regnum == gdbarch_tdep (gdbarch)->exccause_regnum || regnum == -1) |
817 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->exccause_regnum, | |
304fe255 | 818 | (char *) ®s->exccause); |
6b50c0b0 UW |
819 | if (regnum == gdbarch_tdep (gdbarch)->excvaddr_regnum || regnum == -1) |
820 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->excvaddr_regnum, | |
304fe255 | 821 | (char *) ®s->excvaddr); |
6b50c0b0 UW |
822 | if (regnum >=gdbarch_tdep (gdbarch)->ar_base |
823 | && regnum < gdbarch_tdep (gdbarch)->ar_base | |
824 | + gdbarch_tdep (gdbarch)->num_aregs) | |
304fe255 UW |
825 | regcache_raw_supply (rc, regnum, |
826 | (char *) ®s->ar[regnum - gdbarch_tdep | |
6b50c0b0 | 827 | (gdbarch)->ar_base]); |
ca3bf3bd DJ |
828 | else if (regnum == -1) |
829 | { | |
6b50c0b0 UW |
830 | for (i = 0; i < gdbarch_tdep (gdbarch)->num_aregs; ++i) |
831 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ar_base + i, | |
304fe255 | 832 | (char *) ®s->ar[i]); |
ca3bf3bd DJ |
833 | } |
834 | } | |
835 | ||
836 | ||
837 | /* Xtensa register set. */ | |
838 | ||
839 | static struct regset | |
840 | xtensa_gregset = | |
841 | { | |
842 | NULL, | |
843 | xtensa_supply_gregset | |
844 | }; | |
845 | ||
846 | ||
bdb4c075 MG |
847 | /* Return the appropriate register set for the core |
848 | section identified by SECT_NAME and SECT_SIZE. */ | |
ca3bf3bd DJ |
849 | |
850 | static const struct regset * | |
851 | xtensa_regset_from_core_section (struct gdbarch *core_arch, | |
852 | const char *sect_name, | |
853 | size_t sect_size) | |
854 | { | |
855 | DEBUGTRACE ("xtensa_regset_from_core_section " | |
856 | "(..., sect_name==\"%s\", sect_size==%x) \n", | |
ec20a626 | 857 | sect_name, (unsigned int) sect_size); |
ca3bf3bd DJ |
858 | |
859 | if (strcmp (sect_name, ".reg") == 0 | |
860 | && sect_size >= sizeof(xtensa_elf_gregset_t)) | |
861 | return &xtensa_gregset; | |
862 | ||
863 | return NULL; | |
864 | } | |
865 | ||
866 | ||
bdb4c075 | 867 | /* Handling frames. */ |
ca3bf3bd | 868 | |
bdb4c075 MG |
869 | /* Number of registers to save in case of Windowed ABI. */ |
870 | #define XTENSA_NUM_SAVED_AREGS 12 | |
ca3bf3bd | 871 | |
bdb4c075 MG |
872 | /* Frame cache part for Windowed ABI. */ |
873 | typedef struct xtensa_windowed_frame_cache | |
ca3bf3bd | 874 | { |
ca3bf3bd DJ |
875 | int wb; /* Base for this frame; -1 if not in regfile. */ |
876 | int callsize; /* Call size to next frame. */ | |
877 | int ws; | |
878 | CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS]; | |
bdb4c075 MG |
879 | } xtensa_windowed_frame_cache_t; |
880 | ||
881 | /* Call0 ABI Definitions. */ | |
882 | ||
883 | #define C0_MAXOPDS 3 /* Maximum number of operands for prologue analysis. */ | |
884 | #define C0_NREGS 16 /* Number of A-registers to track. */ | |
885 | #define C0_CLESV 12 /* Callee-saved registers are here and up. */ | |
886 | #define C0_SP 1 /* Register used as SP. */ | |
887 | #define C0_FP 15 /* Register used as FP. */ | |
888 | #define C0_RA 0 /* Register used as return address. */ | |
889 | #define C0_ARGS 2 /* Register used as first arg/retval. */ | |
890 | #define C0_NARGS 6 /* Number of A-regs for args/retvals. */ | |
891 | ||
892 | /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each | |
893 | A-register where the current content of the reg came from (in terms | |
894 | of an original reg and a constant). Negative values of c0_rt[n].fp_reg | |
895 | mean that the orignal content of the register was saved to the stack. | |
896 | c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't | |
897 | know where SP will end up until the entire prologue has been analyzed. */ | |
898 | ||
899 | #define C0_CONST -1 /* fr_reg value if register contains a constant. */ | |
900 | #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */ | |
901 | #define C0_NOSTK -1 /* to_stk value if register has not been stored. */ | |
902 | ||
903 | extern xtensa_isa xtensa_default_isa; | |
904 | ||
905 | typedef struct xtensa_c0reg | |
906 | { | |
907 | int fr_reg; /* original register from which register content | |
908 | is derived, or C0_CONST, or C0_INEXP. */ | |
909 | int fr_ofs; /* constant offset from reg, or immediate value. */ | |
910 | int to_stk; /* offset from original SP to register (4-byte aligned), | |
911 | or C0_NOSTK if register has not been saved. */ | |
912 | } xtensa_c0reg_t; | |
913 | ||
914 | ||
915 | /* Frame cache part for Call0 ABI. */ | |
916 | typedef struct xtensa_call0_frame_cache | |
917 | { | |
918 | int c0_frmsz; /* Stack frame size. */ | |
919 | int c0_hasfp; /* Current frame uses frame pointer. */ | |
920 | int fp_regnum; /* A-register used as FP. */ | |
921 | int c0_fp; /* Actual value of frame pointer. */ | |
922 | xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */ | |
923 | } xtensa_call0_frame_cache_t; | |
924 | ||
925 | typedef struct xtensa_frame_cache | |
926 | { | |
927 | CORE_ADDR base; /* Stack pointer of the next frame. */ | |
928 | CORE_ADDR pc; /* PC at the entry point to the function. */ | |
929 | CORE_ADDR ra; /* The raw return address. */ | |
930 | CORE_ADDR ps; /* The PS register of the frame. */ | |
931 | CORE_ADDR prev_sp; /* Stack Pointer of the frame. */ | |
932 | int call0; /* It's a call0 framework (else windowed). */ | |
933 | union | |
934 | { | |
935 | xtensa_windowed_frame_cache_t wd; /* call0 == false. */ | |
936 | xtensa_call0_frame_cache_t c0; /* call0 == true. */ | |
937 | }; | |
ca3bf3bd DJ |
938 | } xtensa_frame_cache_t; |
939 | ||
940 | ||
941 | static struct xtensa_frame_cache * | |
bdb4c075 | 942 | xtensa_alloc_frame_cache (int windowed) |
ca3bf3bd DJ |
943 | { |
944 | xtensa_frame_cache_t *cache; | |
945 | int i; | |
946 | ||
947 | DEBUGTRACE ("xtensa_alloc_frame_cache ()\n"); | |
948 | ||
949 | cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t); | |
950 | ||
951 | cache->base = 0; | |
952 | cache->pc = 0; | |
953 | cache->ra = 0; | |
ca3bf3bd | 954 | cache->ps = 0; |
ca3bf3bd | 955 | cache->prev_sp = 0; |
bdb4c075 MG |
956 | cache->call0 = !windowed; |
957 | if (cache->call0) | |
958 | { | |
959 | cache->c0.c0_frmsz = -1; | |
960 | cache->c0.c0_hasfp = 0; | |
961 | cache->c0.fp_regnum = -1; | |
962 | cache->c0.c0_fp = -1; | |
ca3bf3bd | 963 | |
bdb4c075 MG |
964 | for (i = 0; i < C0_NREGS; i++) |
965 | { | |
966 | cache->c0.c0_rt[i].fr_reg = i; | |
967 | cache->c0.c0_rt[i].fr_ofs = 0; | |
968 | cache->c0.c0_rt[i].to_stk = C0_NOSTK; | |
969 | } | |
970 | } | |
971 | else | |
972 | { | |
973 | cache->wd.wb = 0; | |
974 | cache->wd.callsize = -1; | |
ca3bf3bd | 975 | |
bdb4c075 MG |
976 | for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++) |
977 | cache->wd.aregs[i] = -1; | |
978 | } | |
ca3bf3bd DJ |
979 | return cache; |
980 | } | |
981 | ||
982 | ||
983 | static CORE_ADDR | |
984 | xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) | |
985 | { | |
986 | return address & ~15; | |
987 | } | |
988 | ||
989 | ||
990 | static CORE_ADDR | |
991 | xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
992 | { | |
ff7a4c00 | 993 | gdb_byte buf[8]; |
ca3bf3bd DJ |
994 | |
995 | DEBUGTRACE ("xtensa_unwind_pc (next_frame = %p)\n", next_frame); | |
996 | ||
6b50c0b0 | 997 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
ca3bf3bd DJ |
998 | |
999 | DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) | |
1000 | extract_typed_address (buf, builtin_type_void_func_ptr)); | |
1001 | ||
1002 | return extract_typed_address (buf, builtin_type_void_func_ptr); | |
1003 | } | |
1004 | ||
1005 | ||
1006 | static struct frame_id | |
1007 | xtensa_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1008 | { | |
1009 | CORE_ADDR pc, fp; | |
ca3bf3bd | 1010 | |
bdb4c075 | 1011 | /* next_frame->prev is a dummy frame. Return a frame ID of that frame. */ |
ca3bf3bd DJ |
1012 | |
1013 | DEBUGTRACE ("xtensa_unwind_dummy_id ()\n"); | |
1014 | ||
1015 | pc = frame_pc_unwind (next_frame); | |
304fe255 | 1016 | fp = frame_unwind_register_unsigned |
6b50c0b0 | 1017 | (next_frame, gdbarch_tdep (gdbarch)->a0_base + 1); |
ca3bf3bd DJ |
1018 | |
1019 | /* Make dummy frame ID unique by adding a constant. */ | |
bdb4c075 | 1020 | return frame_id_build (fp + SP_ALIGNMENT, pc); |
ca3bf3bd DJ |
1021 | } |
1022 | ||
bdb4c075 MG |
1023 | /* The key values to identify the frame using "cache" are |
1024 | ||
1025 | cache->base = SP of this frame; | |
1026 | cache->pc = entry-PC (entry point of the frame function); | |
1027 | cache->prev_sp = SP of the previous frame. | |
1028 | */ | |
1029 | ||
1030 | static void | |
1031 | call0_frame_cache (struct frame_info *next_frame, | |
1032 | xtensa_frame_cache_t *cache, | |
1033 | CORE_ADDR pc); | |
ca3bf3bd DJ |
1034 | |
1035 | static struct xtensa_frame_cache * | |
1036 | xtensa_frame_cache (struct frame_info *next_frame, void **this_cache) | |
1037 | { | |
1038 | xtensa_frame_cache_t *cache; | |
ca3bf3bd | 1039 | CORE_ADDR ra, wb, ws, pc, sp, ps; |
6b50c0b0 UW |
1040 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
1041 | unsigned int ps_regnum = gdbarch_ps_regnum (gdbarch); | |
ca3bf3bd | 1042 | char op1; |
bdb4c075 | 1043 | int windowed; |
ca3bf3bd DJ |
1044 | |
1045 | DEBUGTRACE ("xtensa_frame_cache (next_frame %p, *this_cache %p)\n", | |
1046 | next_frame, this_cache ? *this_cache : (void*)0xdeadbeef); | |
1047 | ||
ca3bf3bd DJ |
1048 | if (*this_cache) |
1049 | return *this_cache; | |
1050 | ||
bdb4c075 MG |
1051 | windowed = windowing_enabled (xtensa_read_register (ps_regnum)); |
1052 | ||
ca3bf3bd | 1053 | /* Get pristine xtensa-frame. */ |
bdb4c075 | 1054 | cache = xtensa_alloc_frame_cache (windowed); |
ca3bf3bd DJ |
1055 | *this_cache = cache; |
1056 | ||
3e8c568d | 1057 | pc = frame_unwind_register_unsigned (next_frame, |
6b50c0b0 | 1058 | gdbarch_pc_regnum (gdbarch)); |
ca3bf3bd | 1059 | |
bdb4c075 | 1060 | if (windowed) |
ca3bf3bd | 1061 | { |
bdb4c075 | 1062 | /* Get WINDOWBASE, WINDOWSTART, and PS registers. */ |
304fe255 | 1063 | wb = frame_unwind_register_unsigned |
6b50c0b0 | 1064 | (next_frame, gdbarch_tdep (gdbarch)->wb_regnum); |
304fe255 | 1065 | ws = frame_unwind_register_unsigned |
6b50c0b0 | 1066 | (next_frame, gdbarch_tdep (gdbarch)->ws_regnum); |
bdb4c075 | 1067 | ps = frame_unwind_register_unsigned (next_frame, ps_regnum); |
ca3bf3bd | 1068 | |
bdb4c075 | 1069 | op1 = read_memory_integer (pc, 1); |
91d8eb23 | 1070 | if (XTENSA_IS_ENTRY (gdbarch, op1)) |
ca3bf3bd | 1071 | { |
bdb4c075 | 1072 | int callinc = CALLINC (ps); |
304fe255 | 1073 | ra = frame_unwind_register_unsigned |
6b50c0b0 | 1074 | (next_frame, gdbarch_tdep (gdbarch)->a0_base + 0 + callinc * 4); |
bdb4c075 MG |
1075 | |
1076 | DEBUGINFO("[xtensa_frame_cache] 'entry' at 0x%08x\n (callinc = %d)", | |
1077 | (int)pc, callinc); | |
1078 | ||
1079 | /* ENTRY hasn't been executed yet, therefore callsize is still 0. */ | |
1080 | cache->wd.callsize = 0; | |
1081 | cache->wd.wb = wb; | |
1082 | cache->wd.ws = ws; | |
304fe255 | 1083 | cache->prev_sp = frame_unwind_register_unsigned |
6b50c0b0 | 1084 | (next_frame, gdbarch_tdep (gdbarch)->a0_base + 1); |
bdb4c075 MG |
1085 | } |
1086 | else | |
1087 | { | |
304fe255 | 1088 | ra = frame_unwind_register_unsigned |
6b50c0b0 | 1089 | (next_frame, gdbarch_tdep (gdbarch)->a0_base + 0); |
bdb4c075 | 1090 | cache->wd.callsize = WINSIZE (ra); |
304fe255 | 1091 | cache->wd.wb = (wb - cache->wd.callsize / 4) |
6b50c0b0 | 1092 | & (gdbarch_tdep (gdbarch)->num_aregs / 4 - 1); |
bdb4c075 | 1093 | cache->wd.ws = ws & ~(1 << wb); |
ca3bf3bd DJ |
1094 | } |
1095 | ||
bdb4c075 MG |
1096 | cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME); |
1097 | cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff); | |
1098 | cache->ps = (ps & ~PS_CALLINC_MASK) | |
1099 | | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT); | |
1100 | ||
1101 | if (cache->wd.ws == 0) | |
ca3bf3bd | 1102 | { |
bdb4c075 | 1103 | int i; |
ca3bf3bd | 1104 | |
bdb4c075 | 1105 | /* Set A0...A3. */ |
304fe255 | 1106 | sp = frame_unwind_register_unsigned |
6b50c0b0 | 1107 | (next_frame, gdbarch_tdep (gdbarch)->a0_base + 1) - 16; |
bdb4c075 MG |
1108 | |
1109 | for (i = 0; i < 4; i++, sp += 4) | |
1110 | { | |
1111 | cache->wd.aregs[i] = sp; | |
1112 | } | |
ca3bf3bd | 1113 | |
bdb4c075 | 1114 | if (cache->wd.callsize > 4) |
ca3bf3bd | 1115 | { |
bdb4c075 MG |
1116 | /* Set A4...A7/A11. */ |
1117 | /* Read an SP of the previous frame. */ | |
1118 | sp = (CORE_ADDR) read_memory_integer (sp - 12, 4); | |
1119 | sp -= cache->wd.callsize * 4; | |
1120 | ||
1121 | for ( /* i=4 */ ; i < cache->wd.callsize; i++, sp += 4) | |
1122 | { | |
1123 | cache->wd.aregs[i] = sp; | |
1124 | } | |
ca3bf3bd DJ |
1125 | } |
1126 | } | |
ca3bf3bd | 1127 | |
bdb4c075 MG |
1128 | if ((cache->prev_sp == 0) && ( ra != 0 )) |
1129 | /* If RA is equal to 0 this frame is an outermost frame. Leave | |
1130 | cache->prev_sp unchanged marking the boundary of the frame stack. */ | |
ca3bf3bd | 1131 | { |
bdb4c075 MG |
1132 | if (cache->wd.ws == 0) |
1133 | { | |
1134 | /* Register window overflow already happened. | |
1135 | We can read caller's SP from the proper spill loction. */ | |
1136 | cache->prev_sp = | |
1137 | read_memory_integer (cache->wd.aregs[1], | |
6b50c0b0 UW |
1138 | register_size (gdbarch, |
1139 | gdbarch_tdep (gdbarch)->a0_base + 1)); | |
bdb4c075 MG |
1140 | } |
1141 | else | |
1142 | { | |
1143 | /* Read caller's frame SP directly from the previous window. */ | |
91d8eb23 MD |
1144 | int regnum = areg_number |
1145 | (gdbarch, gdbarch_tdep (gdbarch)->a0_base + 1, | |
304fe255 | 1146 | cache->wd.wb); |
ca3bf3bd | 1147 | |
bdb4c075 MG |
1148 | cache->prev_sp = xtensa_read_register (regnum); |
1149 | } | |
ca3bf3bd DJ |
1150 | } |
1151 | } | |
bdb4c075 MG |
1152 | else /* Call0 framework. */ |
1153 | { | |
1154 | call0_frame_cache (next_frame, cache, pc); | |
1155 | } | |
ca3bf3bd | 1156 | |
304fe255 | 1157 | cache->base = frame_unwind_register_unsigned |
6b50c0b0 | 1158 | (next_frame, gdbarch_tdep (gdbarch)->a0_base + 1); |
ca3bf3bd | 1159 | |
ca3bf3bd DJ |
1160 | return cache; |
1161 | } | |
1162 | ||
ca3bf3bd DJ |
1163 | static void |
1164 | xtensa_frame_this_id (struct frame_info *next_frame, | |
1165 | void **this_cache, | |
1166 | struct frame_id *this_id) | |
1167 | { | |
1168 | struct xtensa_frame_cache *cache = | |
1169 | xtensa_frame_cache (next_frame, this_cache); | |
bdb4c075 | 1170 | struct frame_id id; |
ca3bf3bd | 1171 | |
ec20a626 UW |
1172 | DEBUGTRACE ("xtensa_frame_this_id (next 0x%lx, *this 0x%lx)\n", |
1173 | (unsigned long) next_frame, (unsigned long) *this_cache); | |
ca3bf3bd DJ |
1174 | |
1175 | if (cache->prev_sp == 0) | |
1176 | return; | |
1177 | ||
bdb4c075 MG |
1178 | id = frame_id_build (cache->prev_sp, cache->pc); |
1179 | if (frame_id_eq (id, get_frame_id(next_frame))) | |
1180 | { | |
1181 | warning(_("\ | |
1182 | Frame stack is corrupted. That could happen because of \ | |
1183 | setting register(s) from GDB or stopping execution \ | |
1184 | inside exception handler. Frame backtracing has stopped. \ | |
1185 | It can make some GDB commands work inappropriately.\n")); | |
1186 | cache->prev_sp = 0; | |
1187 | return; | |
1188 | } | |
1189 | (*this_id) = id; | |
ca3bf3bd DJ |
1190 | } |
1191 | ||
bdb4c075 MG |
1192 | static int |
1193 | call0_frame_get_reg_at_entry (struct frame_info *next_frame, | |
1194 | struct xtensa_frame_cache *cache, | |
1195 | int regnum, | |
1196 | CORE_ADDR *addrp, | |
1197 | enum lval_type *lval, | |
1198 | gdb_byte *valuep) | |
1199 | { | |
1200 | CORE_ADDR fp, spe; | |
1201 | int stkofs; | |
6b50c0b0 UW |
1202 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
1203 | int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base | |
1204 | && regnum <= (gdbarch_tdep (gdbarch)->ar_base + C0_NREGS)) | |
1205 | ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum; | |
bdb4c075 MG |
1206 | |
1207 | /* Determine stack pointer on entry to this function, based on FP. */ | |
1208 | spe = cache->c0.c0_fp - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs; | |
1209 | ||
1210 | /* If register was saved to the stack frame in the prologue, retrieve it. */ | |
1211 | stkofs = cache->c0.c0_rt[reg].to_stk; | |
1212 | if (stkofs != C0_NOSTK) | |
1213 | { | |
1214 | *lval = lval_memory; | |
1215 | *addrp = spe + stkofs; | |
1216 | ||
1217 | if (valuep) | |
6b50c0b0 | 1218 | read_memory (*addrp, valuep, register_size (gdbarch, regnum)); |
bdb4c075 MG |
1219 | |
1220 | return 1; | |
1221 | } | |
1222 | ||
1223 | /* If not callee-saved or if known to have been overwritten, give up. */ | |
1224 | if (reg < C0_CLESV | |
1225 | || cache->c0.c0_rt[reg].fr_reg != reg | |
1226 | || cache->c0.c0_rt[reg].fr_ofs != 0) | |
1227 | return 0; | |
1228 | ||
1229 | if (get_frame_type (next_frame) != NORMAL_FRAME) | |
1230 | /* TODO: Do we need a special case for DUMMY_FRAME here? */ | |
1231 | return 0; | |
1232 | ||
1233 | return call0_frame_get_reg_at_entry (get_next_frame(next_frame), | |
1234 | cache, regnum, addrp, lval, valuep); | |
1235 | } | |
ca3bf3bd DJ |
1236 | |
1237 | static void | |
1238 | xtensa_frame_prev_register (struct frame_info *next_frame, | |
1239 | void **this_cache, | |
1240 | int regnum, | |
1241 | int *optimizedp, | |
1242 | enum lval_type *lvalp, | |
1243 | CORE_ADDR *addrp, | |
1244 | int *realnump, | |
1245 | gdb_byte *valuep) | |
1246 | { | |
6b50c0b0 | 1247 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
ca3bf3bd DJ |
1248 | struct xtensa_frame_cache *cache = |
1249 | xtensa_frame_cache (next_frame, this_cache); | |
1250 | CORE_ADDR saved_reg = 0; | |
1251 | int done = 1; | |
1252 | ||
ec20a626 UW |
1253 | DEBUGTRACE ("xtensa_frame_prev_register (next 0x%lx, " |
1254 | "*this 0x%lx, regnum %d (%s), ...)\n", | |
1255 | (unsigned long) next_frame, | |
1256 | *this_cache ? (unsigned long) *this_cache : 0, regnum, | |
d93859e2 | 1257 | xtensa_register_name (gdbarch, regnum)); |
ca3bf3bd | 1258 | |
6b50c0b0 | 1259 | if (regnum ==gdbarch_pc_regnum (gdbarch)) |
bdb4c075 | 1260 | saved_reg = cache->ra; |
6b50c0b0 | 1261 | else if (regnum == gdbarch_tdep (gdbarch)->a0_base + 1) |
bdb4c075 MG |
1262 | saved_reg = cache->prev_sp; |
1263 | else if (!cache->call0) | |
ca3bf3bd | 1264 | { |
6b50c0b0 | 1265 | if (regnum == gdbarch_tdep (gdbarch)->ws_regnum) |
bdb4c075 MG |
1266 | { |
1267 | if (cache->wd.ws != 0) | |
1268 | saved_reg = cache->wd.ws; | |
1269 | else | |
1270 | saved_reg = 1 << cache->wd.wb; | |
1271 | } | |
6b50c0b0 | 1272 | else if (regnum == gdbarch_tdep (gdbarch)->wb_regnum) |
bdb4c075 | 1273 | saved_reg = cache->wd.wb; |
6b50c0b0 | 1274 | else if (regnum == gdbarch_ps_regnum (gdbarch)) |
bdb4c075 | 1275 | saved_reg = cache->ps; |
ca3bf3bd | 1276 | else |
bdb4c075 | 1277 | done = 0; |
ca3bf3bd | 1278 | } |
ca3bf3bd DJ |
1279 | else |
1280 | done = 0; | |
1281 | ||
1282 | if (done) | |
1283 | { | |
1284 | *optimizedp = 0; | |
1285 | *lvalp = not_lval; | |
1286 | *addrp = 0; | |
1287 | *realnump = -1; | |
1288 | if (valuep) | |
1289 | store_unsigned_integer (valuep, 4, saved_reg); | |
1290 | ||
1291 | return; | |
1292 | } | |
1293 | ||
bdb4c075 | 1294 | if (!cache->call0) /* Windowed ABI. */ |
ca3bf3bd | 1295 | { |
bdb4c075 | 1296 | /* Convert A-register numbers to AR-register numbers. */ |
6b50c0b0 UW |
1297 | if (regnum >= gdbarch_tdep (gdbarch)->a0_base + 0 |
1298 | && regnum <= gdbarch_tdep (gdbarch)->a0_base + 15) | |
91d8eb23 | 1299 | regnum = areg_number (gdbarch, regnum, cache->wd.wb); |
ca3bf3bd | 1300 | |
bdb4c075 | 1301 | /* Check if AR-register has been saved to stack. */ |
6b50c0b0 UW |
1302 | if (regnum >= gdbarch_tdep (gdbarch)->ar_base |
1303 | && regnum <= (gdbarch_tdep (gdbarch)->ar_base | |
1304 | + gdbarch_tdep (gdbarch)->num_aregs)) | |
bdb4c075 | 1305 | { |
6b50c0b0 | 1306 | int areg = regnum - gdbarch_tdep (gdbarch)->ar_base |
304fe255 | 1307 | - (cache->wd.wb * 4); |
ca3bf3bd | 1308 | |
bdb4c075 MG |
1309 | if (areg >= 0 |
1310 | && areg < XTENSA_NUM_SAVED_AREGS | |
1311 | && cache->wd.aregs[areg] != -1) | |
1312 | { | |
1313 | *optimizedp = 0; | |
1314 | *lvalp = lval_memory; | |
1315 | *addrp = cache->wd.aregs[areg]; | |
1316 | *realnump = -1; | |
ca3bf3bd | 1317 | |
bdb4c075 MG |
1318 | if (valuep) |
1319 | read_memory (*addrp, valuep, | |
6b50c0b0 | 1320 | register_size (gdbarch, regnum)); |
bdb4c075 MG |
1321 | |
1322 | DEBUGINFO ("[xtensa_frame_prev_register] register on stack\n"); | |
1323 | return; | |
1324 | } | |
ca3bf3bd DJ |
1325 | } |
1326 | } | |
bdb4c075 MG |
1327 | else /* Call0 ABI. */ |
1328 | { | |
6b50c0b0 UW |
1329 | int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base |
1330 | && regnum <= (gdbarch_tdep (gdbarch)->ar_base | |
304fe255 | 1331 | + C0_NREGS)) |
6b50c0b0 | 1332 | ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum; |
ca3bf3bd | 1333 | |
bdb4c075 MG |
1334 | if (reg < C0_NREGS) |
1335 | { | |
1336 | CORE_ADDR spe; | |
1337 | int stkofs; | |
1338 | ||
1339 | /* If register was saved in the prologue, retrieve it. */ | |
1340 | stkofs = cache->c0.c0_rt[reg].to_stk; | |
1341 | if (stkofs != C0_NOSTK) | |
1342 | { | |
1343 | /* Determine SP on entry based on FP. */ | |
1344 | spe = cache->c0.c0_fp | |
1345 | - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs; | |
1346 | *optimizedp = 0; | |
1347 | *lvalp = lval_memory; | |
1348 | *addrp = spe + stkofs; | |
1349 | *realnump = -1; | |
1350 | ||
1351 | if (valuep) | |
1352 | read_memory (*addrp, valuep, | |
6b50c0b0 | 1353 | register_size (gdbarch, regnum)); |
bdb4c075 MG |
1354 | |
1355 | DEBUGINFO ("[xtensa_frame_prev_register] register on stack\n"); | |
1356 | return; | |
1357 | } | |
1358 | } | |
1359 | } | |
1360 | ||
1361 | /* All other registers have been either saved to | |
1362 | the stack or are still alive in the processor. */ | |
ca3bf3bd DJ |
1363 | |
1364 | *optimizedp = 0; | |
1365 | *lvalp = lval_register; | |
1366 | *addrp = 0; | |
1367 | *realnump = regnum; | |
1368 | if (valuep) | |
1369 | frame_unwind_register (next_frame, (*realnump), valuep); | |
1370 | } | |
1371 | ||
1372 | ||
1373 | static const struct frame_unwind | |
1374 | xtensa_frame_unwind = | |
1375 | { | |
1376 | NORMAL_FRAME, | |
1377 | xtensa_frame_this_id, | |
1378 | xtensa_frame_prev_register | |
1379 | }; | |
1380 | ||
1381 | static const struct frame_unwind * | |
1382 | xtensa_frame_sniffer (struct frame_info *next_frame) | |
1383 | { | |
1384 | return &xtensa_frame_unwind; | |
1385 | } | |
1386 | ||
1387 | static CORE_ADDR | |
1388 | xtensa_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
1389 | { | |
1390 | struct xtensa_frame_cache *cache = | |
1391 | xtensa_frame_cache (next_frame, this_cache); | |
1392 | ||
1393 | return cache->base; | |
1394 | } | |
1395 | ||
1396 | static const struct frame_base | |
1397 | xtensa_frame_base = | |
1398 | { | |
1399 | &xtensa_frame_unwind, | |
1400 | xtensa_frame_base_address, | |
1401 | xtensa_frame_base_address, | |
1402 | xtensa_frame_base_address | |
1403 | }; | |
1404 | ||
1405 | ||
1406 | static void | |
1407 | xtensa_extract_return_value (struct type *type, | |
1408 | struct regcache *regcache, | |
1409 | void *dst) | |
1410 | { | |
6b50c0b0 | 1411 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
ca3bf3bd DJ |
1412 | bfd_byte *valbuf = dst; |
1413 | int len = TYPE_LENGTH (type); | |
1414 | ULONGEST pc, wb; | |
1415 | int callsize, areg; | |
1416 | int offset = 0; | |
1417 | ||
1418 | DEBUGTRACE ("xtensa_extract_return_value (...)\n"); | |
1419 | ||
1420 | gdb_assert(len > 0); | |
1421 | ||
6b50c0b0 | 1422 | if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
bdb4c075 MG |
1423 | { |
1424 | /* First, we have to find the caller window in the register file. */ | |
6b50c0b0 | 1425 | regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc); |
91d8eb23 | 1426 | callsize = extract_call_winsize (gdbarch, pc); |
ca3bf3bd | 1427 | |
bdb4c075 MG |
1428 | /* On Xtensa, we can return up to 4 words (or 2 for call12). */ |
1429 | if (len > (callsize > 8 ? 8 : 16)) | |
1430 | internal_error (__FILE__, __LINE__, | |
1431 | _("cannot extract return value of %d bytes long"), len); | |
ca3bf3bd | 1432 | |
bdb4c075 MG |
1433 | /* Get the register offset of the return |
1434 | register (A2) in the caller window. */ | |
304fe255 | 1435 | regcache_raw_read_unsigned |
6b50c0b0 | 1436 | (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb); |
91d8eb23 MD |
1437 | areg = areg_number (gdbarch, |
1438 | gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb); | |
bdb4c075 MG |
1439 | } |
1440 | else | |
1441 | { | |
1442 | /* No windowing hardware - Call0 ABI. */ | |
6b50c0b0 | 1443 | areg = gdbarch_tdep (gdbarch)->a0_base + 0 + C0_ARGS; |
bdb4c075 | 1444 | } |
ca3bf3bd DJ |
1445 | |
1446 | DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len); | |
1447 | ||
6b50c0b0 | 1448 | if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1449 | offset = 4 - len; |
1450 | ||
1451 | for (; len > 0; len -= 4, areg++, valbuf += 4) | |
1452 | { | |
1453 | if (len < 4) | |
1454 | regcache_raw_read_part (regcache, areg, offset, len, valbuf); | |
1455 | else | |
1456 | regcache_raw_read (regcache, areg, valbuf); | |
1457 | } | |
1458 | } | |
1459 | ||
1460 | ||
1461 | static void | |
1462 | xtensa_store_return_value (struct type *type, | |
1463 | struct regcache *regcache, | |
1464 | const void *dst) | |
1465 | { | |
6b50c0b0 | 1466 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
ca3bf3bd DJ |
1467 | const bfd_byte *valbuf = dst; |
1468 | unsigned int areg; | |
1469 | ULONGEST pc, wb; | |
1470 | int callsize; | |
1471 | int len = TYPE_LENGTH (type); | |
1472 | int offset = 0; | |
1473 | ||
1474 | DEBUGTRACE ("xtensa_store_return_value (...)\n"); | |
1475 | ||
6b50c0b0 | 1476 | if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
bdb4c075 | 1477 | { |
6b50c0b0 UW |
1478 | regcache_raw_read_unsigned |
1479 | (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb); | |
1480 | regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc); | |
91d8eb23 | 1481 | callsize = extract_call_winsize (gdbarch, pc); |
ca3bf3bd | 1482 | |
bdb4c075 MG |
1483 | if (len > (callsize > 8 ? 8 : 16)) |
1484 | internal_error (__FILE__, __LINE__, | |
1485 | _("unimplemented for this length: %d"), | |
1486 | TYPE_LENGTH (type)); | |
91d8eb23 MD |
1487 | areg = areg_number (gdbarch, |
1488 | gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb); | |
ca3bf3bd | 1489 | |
bdb4c075 | 1490 | DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n", |
ca3bf3bd | 1491 | callsize, (int) wb); |
bdb4c075 MG |
1492 | } |
1493 | else | |
1494 | { | |
6b50c0b0 | 1495 | areg = gdbarch_tdep (gdbarch)->a0_base + 0 + C0_ARGS; |
bdb4c075 | 1496 | } |
ca3bf3bd | 1497 | |
6b50c0b0 | 1498 | if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1499 | offset = 4 - len; |
1500 | ||
ca3bf3bd DJ |
1501 | for (; len > 0; len -= 4, areg++, valbuf += 4) |
1502 | { | |
1503 | if (len < 4) | |
1504 | regcache_raw_write_part (regcache, areg, offset, len, valbuf); | |
1505 | else | |
1506 | regcache_raw_write (regcache, areg, valbuf); | |
1507 | } | |
1508 | } | |
1509 | ||
1510 | ||
bdb4c075 | 1511 | static enum return_value_convention |
ca3bf3bd DJ |
1512 | xtensa_return_value (struct gdbarch *gdbarch, |
1513 | struct type *valtype, | |
1514 | struct regcache *regcache, | |
1515 | gdb_byte *readbuf, | |
1516 | const gdb_byte *writebuf) | |
1517 | { | |
bdb4c075 | 1518 | /* Structures up to 16 bytes are returned in registers. */ |
ca3bf3bd DJ |
1519 | |
1520 | int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT | |
1521 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
1522 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
1523 | && TYPE_LENGTH (valtype) > 16); | |
1524 | ||
1525 | if (struct_return) | |
1526 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1527 | ||
1528 | DEBUGTRACE ("xtensa_return_value(...)\n"); | |
1529 | ||
1530 | if (writebuf != NULL) | |
1531 | { | |
1532 | xtensa_store_return_value (valtype, regcache, writebuf); | |
1533 | } | |
1534 | ||
1535 | if (readbuf != NULL) | |
1536 | { | |
1537 | gdb_assert (!struct_return); | |
1538 | xtensa_extract_return_value (valtype, regcache, readbuf); | |
1539 | } | |
1540 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1541 | } | |
1542 | ||
1543 | ||
1544 | /* DUMMY FRAME */ | |
1545 | ||
1546 | static CORE_ADDR | |
1547 | xtensa_push_dummy_call (struct gdbarch *gdbarch, | |
1548 | struct value *function, | |
1549 | struct regcache *regcache, | |
1550 | CORE_ADDR bp_addr, | |
1551 | int nargs, | |
1552 | struct value **args, | |
1553 | CORE_ADDR sp, | |
1554 | int struct_return, | |
1555 | CORE_ADDR struct_addr) | |
1556 | { | |
1557 | int i; | |
1558 | int size, onstack_size; | |
ff7a4c00 | 1559 | gdb_byte *buf = (gdb_byte *) alloca (16); |
ca3bf3bd DJ |
1560 | CORE_ADDR ra, ps; |
1561 | struct argument_info | |
1562 | { | |
1563 | const bfd_byte *contents; | |
1564 | int length; | |
1565 | int onstack; /* onstack == 0 => in reg */ | |
1566 | int align; /* alignment */ | |
1567 | union | |
1568 | { | |
1569 | int offset; /* stack offset if on stack */ | |
1570 | int regno; /* regno if in register */ | |
1571 | } u; | |
1572 | }; | |
1573 | ||
1574 | struct argument_info *arg_info = | |
1575 | (struct argument_info *) alloca (nargs * sizeof (struct argument_info)); | |
1576 | ||
1577 | CORE_ADDR osp = sp; | |
1578 | ||
1579 | DEBUGTRACE ("xtensa_push_dummy_call (...)\n"); | |
1580 | ||
1581 | if (xtensa_debug_level > 3) | |
1582 | { | |
1583 | int i; | |
1584 | DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs); | |
1585 | DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, " | |
1586 | "struct_addr=0x%x\n", | |
1587 | (int) sp, (int) struct_return, (int) struct_addr); | |
1588 | ||
1589 | for (i = 0; i < nargs; i++) | |
1590 | { | |
1591 | struct value *arg = args[i]; | |
1592 | struct type *arg_type = check_typedef (value_type (arg)); | |
ec20a626 UW |
1593 | fprintf_unfiltered (gdb_stdlog, "%2d: 0x%lx %3d ", |
1594 | i, (unsigned long) arg, TYPE_LENGTH (arg_type)); | |
ca3bf3bd DJ |
1595 | switch (TYPE_CODE (arg_type)) |
1596 | { | |
1597 | case TYPE_CODE_INT: | |
1598 | fprintf_unfiltered (gdb_stdlog, "int"); | |
1599 | break; | |
1600 | case TYPE_CODE_STRUCT: | |
1601 | fprintf_unfiltered (gdb_stdlog, "struct"); | |
1602 | break; | |
1603 | default: | |
1604 | fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type)); | |
1605 | break; | |
1606 | } | |
ec20a626 UW |
1607 | fprintf_unfiltered (gdb_stdlog, " 0x%lx\n", |
1608 | (unsigned long) value_contents (arg)); | |
ca3bf3bd DJ |
1609 | } |
1610 | } | |
1611 | ||
1612 | /* First loop: collect information. | |
1613 | Cast into type_long. (This shouldn't happen often for C because | |
1614 | GDB already does this earlier.) It's possible that GDB could | |
1615 | do it all the time but it's harmless to leave this code here. */ | |
1616 | ||
1617 | size = 0; | |
1618 | onstack_size = 0; | |
1619 | i = 0; | |
1620 | ||
1621 | if (struct_return) | |
1622 | size = REGISTER_SIZE; | |
1623 | ||
1624 | for (i = 0; i < nargs; i++) | |
1625 | { | |
1626 | struct argument_info *info = &arg_info[i]; | |
1627 | struct value *arg = args[i]; | |
1628 | struct type *arg_type = check_typedef (value_type (arg)); | |
1629 | ||
1630 | switch (TYPE_CODE (arg_type)) | |
1631 | { | |
1632 | case TYPE_CODE_INT: | |
1633 | case TYPE_CODE_BOOL: | |
1634 | case TYPE_CODE_CHAR: | |
1635 | case TYPE_CODE_RANGE: | |
1636 | case TYPE_CODE_ENUM: | |
1637 | ||
1638 | /* Cast argument to long if necessary as the mask does it too. */ | |
1639 | if (TYPE_LENGTH (arg_type) < TYPE_LENGTH (builtin_type_long)) | |
1640 | { | |
1641 | arg_type = builtin_type_long; | |
1642 | arg = value_cast (arg_type, arg); | |
1643 | } | |
bdb4c075 MG |
1644 | /* Aligment is equal to the type length for the basic types. */ |
1645 | info->align = TYPE_LENGTH (arg_type); | |
ca3bf3bd DJ |
1646 | break; |
1647 | ||
1648 | case TYPE_CODE_FLT: | |
1649 | ||
1650 | /* Align doubles correctly. */ | |
1651 | if (TYPE_LENGTH (arg_type) == TYPE_LENGTH (builtin_type_double)) | |
1652 | info->align = TYPE_LENGTH (builtin_type_double); | |
1653 | else | |
1654 | info->align = TYPE_LENGTH (builtin_type_long); | |
1655 | break; | |
1656 | ||
1657 | case TYPE_CODE_STRUCT: | |
1658 | default: | |
1659 | info->align = TYPE_LENGTH (builtin_type_long); | |
1660 | break; | |
1661 | } | |
1662 | info->length = TYPE_LENGTH (arg_type); | |
1663 | info->contents = value_contents (arg); | |
1664 | ||
1665 | /* Align size and onstack_size. */ | |
1666 | size = (size + info->align - 1) & ~(info->align - 1); | |
1667 | onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1); | |
1668 | ||
91d8eb23 | 1669 | if (size + info->length > REGISTER_SIZE * ARG_NOF (gdbarch)) |
ca3bf3bd DJ |
1670 | { |
1671 | info->onstack = 1; | |
1672 | info->u.offset = onstack_size; | |
1673 | onstack_size += info->length; | |
1674 | } | |
1675 | else | |
1676 | { | |
1677 | info->onstack = 0; | |
91d8eb23 | 1678 | info->u.regno = ARG_1ST (gdbarch) + size / REGISTER_SIZE; |
ca3bf3bd DJ |
1679 | } |
1680 | size += info->length; | |
1681 | } | |
1682 | ||
1683 | /* Adjust the stack pointer and align it. */ | |
1684 | sp = align_down (sp - onstack_size, SP_ALIGNMENT); | |
1685 | ||
bdb4c075 | 1686 | /* Simulate MOVSP, if Windowed ABI. */ |
6b50c0b0 | 1687 | if ((gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
304fe255 | 1688 | && (sp != osp)) |
ca3bf3bd DJ |
1689 | { |
1690 | read_memory (osp - 16, buf, 16); | |
1691 | write_memory (sp - 16, buf, 16); | |
1692 | } | |
1693 | ||
1694 | /* Second Loop: Load arguments. */ | |
1695 | ||
1696 | if (struct_return) | |
1697 | { | |
1698 | store_unsigned_integer (buf, REGISTER_SIZE, struct_addr); | |
91d8eb23 | 1699 | regcache_cooked_write (regcache, ARG_1ST (gdbarch), buf); |
ca3bf3bd DJ |
1700 | } |
1701 | ||
1702 | for (i = 0; i < nargs; i++) | |
1703 | { | |
1704 | struct argument_info *info = &arg_info[i]; | |
1705 | ||
1706 | if (info->onstack) | |
1707 | { | |
1708 | int n = info->length; | |
1709 | CORE_ADDR offset = sp + info->u.offset; | |
1710 | ||
1711 | /* Odd-sized structs are aligned to the lower side of a memory | |
1712 | word in big-endian mode and require a shift. This only | |
1713 | applies for structures smaller than one word. */ | |
1714 | ||
4c6b5505 | 1715 | if (n < REGISTER_SIZE |
6b50c0b0 | 1716 | && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1717 | offset += (REGISTER_SIZE - n); |
1718 | ||
1719 | write_memory (offset, info->contents, info->length); | |
1720 | ||
1721 | } | |
1722 | else | |
1723 | { | |
1724 | int n = info->length; | |
1725 | const bfd_byte *cp = info->contents; | |
1726 | int r = info->u.regno; | |
1727 | ||
1728 | /* Odd-sized structs are aligned to the lower side of registers in | |
1729 | big-endian mode and require a shift. The odd-sized leftover will | |
1730 | be at the end. Note that this is only true for structures smaller | |
1731 | than REGISTER_SIZE; for larger odd-sized structures the excess | |
1732 | will be left-aligned in the register on both endiannesses. */ | |
1733 | ||
4c6b5505 | 1734 | if (n < REGISTER_SIZE |
6b50c0b0 | 1735 | && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1736 | { |
1737 | ULONGEST v = extract_unsigned_integer (cp, REGISTER_SIZE); | |
1738 | v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT); | |
1739 | ||
1740 | store_unsigned_integer (buf, REGISTER_SIZE, v); | |
1741 | regcache_cooked_write (regcache, r, buf); | |
1742 | ||
1743 | cp += REGISTER_SIZE; | |
1744 | n -= REGISTER_SIZE; | |
1745 | r++; | |
1746 | } | |
1747 | else | |
1748 | while (n > 0) | |
1749 | { | |
ca3bf3bd DJ |
1750 | regcache_cooked_write (regcache, r, cp); |
1751 | ||
ca3bf3bd DJ |
1752 | cp += REGISTER_SIZE; |
1753 | n -= REGISTER_SIZE; | |
1754 | r++; | |
1755 | } | |
1756 | } | |
1757 | } | |
1758 | ||
ca3bf3bd | 1759 | /* Set the return address of dummy frame to the dummy address. |
bdb4c075 | 1760 | The return address for the current function (in A0) is |
ca3bf3bd DJ |
1761 | saved in the dummy frame, so we can savely overwrite A0 here. */ |
1762 | ||
6b50c0b0 | 1763 | if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
bdb4c075 MG |
1764 | { |
1765 | ra = (bp_addr & 0x3fffffff) | 0x40000000; | |
6b50c0b0 | 1766 | regcache_raw_read (regcache, gdbarch_ps_regnum (gdbarch), buf); |
bdb4c075 | 1767 | ps = extract_unsigned_integer (buf, 4) & ~0x00030000; |
304fe255 | 1768 | regcache_cooked_write_unsigned |
6b50c0b0 | 1769 | (regcache, gdbarch_tdep (gdbarch)->a0_base + 4, ra); |
bdb4c075 | 1770 | regcache_cooked_write_unsigned (regcache, |
6b50c0b0 | 1771 | gdbarch_ps_regnum (gdbarch), |
bdb4c075 MG |
1772 | ps | 0x00010000); |
1773 | } | |
1774 | else | |
1775 | { | |
1776 | /* Simulate CALL0: write RA into A0 register. */ | |
304fe255 | 1777 | regcache_cooked_write_unsigned |
6b50c0b0 | 1778 | (regcache, gdbarch_tdep (gdbarch)->a0_base + 0, bp_addr); |
bdb4c075 | 1779 | } |
ca3bf3bd DJ |
1780 | |
1781 | /* Set new stack pointer and return it. */ | |
304fe255 | 1782 | regcache_cooked_write_unsigned (regcache, |
6b50c0b0 | 1783 | gdbarch_tdep (gdbarch)->a0_base + 1, sp); |
ca3bf3bd DJ |
1784 | /* Make dummy frame ID unique by adding a constant. */ |
1785 | return sp + SP_ALIGNMENT; | |
1786 | } | |
1787 | ||
1788 | ||
1789 | /* Return a breakpoint for the current location of PC. We always use | |
1790 | the density version if we have density instructions (regardless of the | |
1791 | current instruction at PC), and use regular instructions otherwise. */ | |
1792 | ||
1793 | #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 } | |
1794 | #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 } | |
1795 | #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f } | |
1796 | #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 } | |
1797 | ||
bdb4c075 | 1798 | static const unsigned char * |
67d57894 MD |
1799 | xtensa_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, |
1800 | int *lenptr) | |
ca3bf3bd | 1801 | { |
ff7a4c00 MG |
1802 | static unsigned char big_breakpoint[] = BIG_BREAKPOINT; |
1803 | static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT; | |
1804 | static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT; | |
1805 | static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT; | |
ca3bf3bd DJ |
1806 | |
1807 | DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr); | |
1808 | ||
67d57894 | 1809 | if (gdbarch_tdep (gdbarch)->isa_use_density_instructions) |
ca3bf3bd | 1810 | { |
67d57894 | 1811 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1812 | { |
1813 | *lenptr = sizeof (density_big_breakpoint); | |
1814 | return density_big_breakpoint; | |
1815 | } | |
1816 | else | |
1817 | { | |
1818 | *lenptr = sizeof (density_little_breakpoint); | |
1819 | return density_little_breakpoint; | |
1820 | } | |
1821 | } | |
1822 | else | |
1823 | { | |
67d57894 | 1824 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1825 | { |
1826 | *lenptr = sizeof (big_breakpoint); | |
1827 | return big_breakpoint; | |
1828 | } | |
1829 | else | |
1830 | { | |
1831 | *lenptr = sizeof (little_breakpoint); | |
1832 | return little_breakpoint; | |
1833 | } | |
1834 | } | |
1835 | } | |
1836 | ||
bdb4c075 MG |
1837 | /* Call0 ABI support routines. */ |
1838 | ||
1839 | /* Call0 opcode class. Opcodes are preclassified according to what they | |
1840 | mean for Call0 prologue analysis, and their number of significant operands. | |
1841 | The purpose of this is to simplify prologue analysis by separating | |
1842 | instruction decoding (libisa) from the semantics of prologue analysis. */ | |
1843 | ||
1844 | typedef enum { | |
1845 | c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */ | |
1846 | c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */ | |
1847 | c0opc_flow, /* Flow control insn. */ | |
1848 | c0opc_entry, /* ENTRY indicates non-Call0 prologue. */ | |
1849 | c0opc_break, /* Debugger software breakpoints. */ | |
1850 | c0opc_add, /* Adding two registers. */ | |
1851 | c0opc_addi, /* Adding a register and an immediate. */ | |
1852 | c0opc_sub, /* Subtracting a register from a register. */ | |
1853 | c0opc_mov, /* Moving a register to a register. */ | |
1854 | c0opc_movi, /* Moving an immediate to a register. */ | |
1855 | c0opc_l32r, /* Loading a literal. */ | |
1856 | c0opc_s32i, /* Storing word at fixed offset from a base register. */ | |
1857 | c0opc_NrOf /* Number of opcode classifications. */ | |
1858 | } xtensa_insn_kind; | |
1859 | ||
1860 | ||
1861 | /* Classify an opcode based on what it means for Call0 prologue analysis. */ | |
1862 | ||
1863 | static xtensa_insn_kind | |
1864 | call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc) | |
1865 | { | |
1866 | const char *opcname; | |
1867 | xtensa_insn_kind opclass = c0opc_uninteresting; | |
1868 | ||
1869 | DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc); | |
1870 | ||
1871 | /* Get opcode name and handle special classifications. */ | |
1872 | ||
1873 | opcname = xtensa_opcode_name (isa, opc); | |
1874 | ||
1875 | if (opcname == NULL | |
1876 | || strcasecmp (opcname, "ill") == 0 | |
1877 | || strcasecmp (opcname, "ill.n") == 0) | |
1878 | opclass = c0opc_illegal; | |
1879 | else if (strcasecmp (opcname, "break") == 0 | |
1880 | || strcasecmp (opcname, "break.n") == 0) | |
1881 | opclass = c0opc_break; | |
1882 | else if (strcasecmp (opcname, "entry") == 0) | |
1883 | opclass = c0opc_entry; | |
1884 | else if (xtensa_opcode_is_branch (isa, opc) > 0 | |
1885 | || xtensa_opcode_is_jump (isa, opc) > 0 | |
1886 | || xtensa_opcode_is_loop (isa, opc) > 0 | |
1887 | || xtensa_opcode_is_call (isa, opc) > 0 | |
1888 | || strcasecmp (opcname, "simcall") == 0 | |
1889 | || strcasecmp (opcname, "syscall") == 0) | |
1890 | opclass = c0opc_flow; | |
1891 | ||
1892 | /* Also, classify specific opcodes that need to be tracked. */ | |
1893 | else if (strcasecmp (opcname, "add") == 0 | |
1894 | || strcasecmp (opcname, "add.n") == 0) | |
1895 | opclass = c0opc_add; | |
1896 | else if (strcasecmp (opcname, "addi") == 0 | |
1897 | || strcasecmp (opcname, "addi.n") == 0 | |
1898 | || strcasecmp (opcname, "addmi") == 0) | |
1899 | opclass = c0opc_addi; | |
1900 | else if (strcasecmp (opcname, "sub") == 0) | |
1901 | opclass = c0opc_sub; | |
1902 | else if (strcasecmp (opcname, "mov.n") == 0 | |
1903 | || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */ | |
1904 | opclass = c0opc_mov; | |
1905 | else if (strcasecmp (opcname, "movi") == 0 | |
1906 | || strcasecmp (opcname, "movi.n") == 0) | |
1907 | opclass = c0opc_movi; | |
1908 | else if (strcasecmp (opcname, "l32r") == 0) | |
1909 | opclass = c0opc_l32r; | |
1910 | else if (strcasecmp (opcname, "s32i") == 0 | |
1911 | || strcasecmp (opcname, "s32i.n") == 0) | |
1912 | opclass = c0opc_s32i; | |
1913 | ||
1914 | return opclass; | |
1915 | } | |
1916 | ||
1917 | /* Tracks register movement/mutation for a given operation, which may | |
1918 | be within a bundle. Updates the destination register tracking info | |
1919 | accordingly. The pc is needed only for pc-relative load instructions | |
1920 | (eg. l32r). The SP register number is needed to identify stores to | |
1921 | the stack frame. */ | |
1922 | ||
1923 | static void | |
1924 | call0_track_op (xtensa_c0reg_t dst[], xtensa_c0reg_t src[], | |
1925 | xtensa_insn_kind opclass, int nods, unsigned odv[], | |
1926 | CORE_ADDR pc, int spreg) | |
1927 | { | |
1928 | unsigned litbase, litaddr, litval; | |
1929 | ||
1930 | switch (opclass) | |
1931 | { | |
1932 | case c0opc_addi: | |
1933 | /* 3 operands: dst, src, imm. */ | |
1934 | gdb_assert (nods == 3); | |
1935 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
1936 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2]; | |
1937 | break; | |
1938 | case c0opc_add: | |
1939 | /* 3 operands: dst, src1, src2. */ | |
1940 | gdb_assert (nods == 3); | |
1941 | if (src[odv[1]].fr_reg == C0_CONST) | |
1942 | { | |
1943 | dst[odv[0]].fr_reg = src[odv[2]].fr_reg; | |
1944 | dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs; | |
1945 | } | |
1946 | else if (src[odv[2]].fr_reg == C0_CONST) | |
1947 | { | |
1948 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
1949 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs; | |
1950 | } | |
1951 | else dst[odv[0]].fr_reg = C0_INEXP; | |
1952 | break; | |
1953 | case c0opc_sub: | |
1954 | /* 3 operands: dst, src1, src2. */ | |
1955 | gdb_assert (nods == 3); | |
1956 | if (src[odv[2]].fr_reg == C0_CONST) | |
1957 | { | |
1958 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
1959 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs; | |
1960 | } | |
1961 | else dst[odv[0]].fr_reg = C0_INEXP; | |
1962 | break; | |
1963 | case c0opc_mov: | |
1964 | /* 2 operands: dst, src [, src]. */ | |
1965 | gdb_assert (nods == 2); | |
1966 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
1967 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs; | |
1968 | break; | |
1969 | case c0opc_movi: | |
1970 | /* 2 operands: dst, imm. */ | |
1971 | gdb_assert (nods == 2); | |
1972 | dst[odv[0]].fr_reg = C0_CONST; | |
1973 | dst[odv[0]].fr_ofs = odv[1]; | |
1974 | break; | |
1975 | case c0opc_l32r: | |
1976 | /* 2 operands: dst, literal offset. */ | |
1977 | gdb_assert (nods == 2); | |
1978 | /* litbase = xtensa_get_litbase (pc); can be also used. */ | |
304fe255 UW |
1979 | litbase = (gdbarch_tdep (current_gdbarch)->litbase_regnum == -1) |
1980 | ? 0 : xtensa_read_register | |
1981 | (gdbarch_tdep (current_gdbarch)->litbase_regnum); | |
bdb4c075 MG |
1982 | litaddr = litbase & 1 |
1983 | ? (litbase & ~1) + (signed)odv[1] | |
1984 | : (pc + 3 + (signed)odv[1]) & ~3; | |
1985 | litval = read_memory_integer(litaddr, 4); | |
1986 | dst[odv[0]].fr_reg = C0_CONST; | |
1987 | dst[odv[0]].fr_ofs = litval; | |
1988 | break; | |
1989 | case c0opc_s32i: | |
1990 | /* 3 operands: value, base, offset. */ | |
1991 | gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS); | |
1992 | if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */ | |
1993 | && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */ | |
1994 | && src[odv[0]].fr_reg >= 0 /* Value is from a register. */ | |
1995 | && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */ | |
1996 | && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */ | |
1997 | { | |
1998 | /* ISA encoding guarantees alignment. But, check it anyway. */ | |
1999 | gdb_assert ((odv[2] & 3) == 0); | |
2000 | dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2]; | |
2001 | } | |
2002 | break; | |
2003 | default: | |
2004 | gdb_assert (0); | |
2005 | } | |
2006 | } | |
2007 | ||
2008 | /* Analyze prologue of the function at start address to determine if it uses | |
2009 | the Call0 ABI, and if so track register moves and linear modifications | |
2010 | in the prologue up to the PC or just beyond the prologue, whichever is first. | |
2011 | An 'entry' instruction indicates non-Call0 ABI and the end of the prologue. | |
2012 | The prologue may overlap non-prologue instructions but is guaranteed to end | |
2013 | by the first flow-control instruction (jump, branch, call or return). | |
2014 | Since an optimized function may move information around and change the | |
2015 | stack frame arbitrarily during the prologue, the information is guaranteed | |
2016 | valid only at the point in the function indicated by the PC. | |
2017 | May be used to skip the prologue or identify the ABI, w/o tracking. | |
2018 | ||
2019 | Returns: Address of first instruction after prologue, or PC (whichever | |
2020 | is first), or 0, if decoding failed (in libisa). | |
2021 | Input args: | |
2022 | start Start address of function/prologue. | |
2023 | pc Program counter to stop at. Use 0 to continue to end of prologue. | |
2024 | If 0, avoids infinite run-on in corrupt code memory by bounding | |
2025 | the scan to the end of the function if that can be determined. | |
2026 | nregs Number of general registers to track (size of rt[] array). | |
2027 | InOut args: | |
2028 | rt[] Array[nregs] of xtensa_c0reg structures for register tracking info. | |
2029 | If NULL, registers are not tracked. | |
2030 | Output args: | |
2031 | call0 If != NULL, *call0 is set non-zero if Call0 ABI used, else 0 | |
2032 | (more accurately, non-zero until 'entry' insn is encountered). | |
2033 | ||
2034 | Note that these may produce useful results even if decoding fails | |
2035 | because they begin with default assumptions that analysis may change. */ | |
2036 | ||
2037 | static CORE_ADDR | |
2038 | call0_analyze_prologue (CORE_ADDR start, CORE_ADDR pc, | |
2039 | int nregs, xtensa_c0reg_t rt[], int *call0) | |
2040 | { | |
2041 | CORE_ADDR ia; /* Current insn address in prologue. */ | |
2042 | CORE_ADDR ba = 0; /* Current address at base of insn buffer. */ | |
2043 | CORE_ADDR bt; /* Current address at top+1 of insn buffer. */ | |
2044 | #define BSZ 32 /* Instruction buffer size. */ | |
2045 | char ibuf[BSZ]; /* Instruction buffer for decoding prologue. */ | |
2046 | xtensa_isa isa; /* libisa ISA handle. */ | |
2047 | xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */ | |
2048 | xtensa_format ifmt; /* libisa instruction format. */ | |
2049 | int ilen, islots, is; /* Instruction length, nbr slots, current slot. */ | |
2050 | xtensa_opcode opc; /* Opcode in current slot. */ | |
2051 | xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */ | |
2052 | int nods; /* Opcode number of operands. */ | |
2053 | unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */ | |
2054 | xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */ | |
2055 | int j; /* General loop counter. */ | |
2056 | int fail = 0; /* Set non-zero and exit, if decoding fails. */ | |
2057 | CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */ | |
2058 | CORE_ADDR end_pc; /* The PC for the lust function insn. */ | |
2059 | ||
2060 | struct symtab_and_line prologue_sal; | |
2061 | ||
2062 | DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n", | |
2063 | (int)start, (int)pc); | |
2064 | ||
2065 | /* Try to limit the scan to the end of the function if a non-zero pc | |
2066 | arg was not supplied to avoid probing beyond the end of valid memory. | |
2067 | If memory is full of garbage that classifies as c0opc_uninteresting. | |
2068 | If this fails (eg. if no symbols) pc ends up 0 as it was. | |
2069 | Intialize the Call0 frame and register tracking info. | |
2070 | Assume it's Call0 until an 'entry' instruction is encountered. | |
2071 | Assume we may be in the prologue until we hit a flow control instr. */ | |
2072 | ||
2073 | rtmp = NULL; | |
2074 | body_pc = INT_MAX; | |
2075 | end_pc = 0; | |
2076 | ||
2077 | /* Find out, if we have an information about the prologue from DWARF. */ | |
2078 | prologue_sal = find_pc_line (start, 0); | |
2079 | if (prologue_sal.line != 0) /* Found debug info. */ | |
2080 | body_pc = prologue_sal.end; | |
2081 | ||
2082 | /* If we are going to analyze the prologue in general without knowing about | |
2083 | the current PC, make the best assumtion for the end of the prologue. */ | |
2084 | if (pc == 0) | |
2085 | { | |
2086 | find_pc_partial_function (start, 0, NULL, &end_pc); | |
2087 | body_pc = min (end_pc, body_pc); | |
2088 | } | |
2089 | else | |
2090 | body_pc = min (pc, body_pc); | |
2091 | ||
2092 | if (call0 != NULL) | |
2093 | *call0 = 1; | |
2094 | ||
2095 | if (rt != NULL) | |
2096 | { | |
2097 | rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t)); | |
2098 | /* rt is already initialized in xtensa_alloc_frame_cache(). */ | |
2099 | } | |
2100 | else nregs = 0; | |
2101 | ||
2102 | isa = xtensa_default_isa; | |
2103 | gdb_assert (BSZ >= xtensa_isa_maxlength (isa)); | |
2104 | ins = xtensa_insnbuf_alloc (isa); | |
2105 | slot = xtensa_insnbuf_alloc (isa); | |
2106 | ||
2107 | for (ia = start, bt = ia; ia < body_pc ; ia += ilen) | |
2108 | { | |
2109 | /* (Re)fill instruction buffer from memory if necessary, but do not | |
2110 | read memory beyond PC to be sure we stay within text section | |
2111 | (this protection only works if a non-zero pc is supplied). */ | |
2112 | ||
2113 | if (ia + xtensa_isa_maxlength (isa) > bt) | |
2114 | { | |
2115 | ba = ia; | |
2116 | bt = (ba + BSZ) < body_pc ? ba + BSZ : body_pc; | |
2117 | read_memory (ba, ibuf, bt - ba); | |
2118 | } | |
2119 | ||
2120 | /* Decode format information. */ | |
2121 | ||
2122 | xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); | |
2123 | ifmt = xtensa_format_decode (isa, ins); | |
2124 | if (ifmt == XTENSA_UNDEFINED) | |
2125 | { | |
2126 | fail = 1; | |
2127 | goto done; | |
2128 | } | |
2129 | ilen = xtensa_format_length (isa, ifmt); | |
2130 | if (ilen == XTENSA_UNDEFINED) | |
2131 | { | |
2132 | fail = 1; | |
2133 | goto done; | |
2134 | } | |
2135 | islots = xtensa_format_num_slots (isa, ifmt); | |
2136 | if (islots == XTENSA_UNDEFINED) | |
2137 | { | |
2138 | fail = 1; | |
2139 | goto done; | |
2140 | } | |
2141 | ||
2142 | /* Analyze a bundle or a single instruction, using a snapshot of | |
2143 | the register tracking info as input for the entire bundle so that | |
2144 | register changes do not take effect within this bundle. */ | |
ca3bf3bd | 2145 | |
bdb4c075 MG |
2146 | for (j = 0; j < nregs; ++j) |
2147 | rtmp[j] = rt[j]; | |
2148 | ||
2149 | for (is = 0; is < islots; ++is) | |
2150 | { | |
2151 | /* Decode a slot and classify the opcode. */ | |
2152 | ||
2153 | fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot); | |
2154 | if (fail) | |
2155 | goto done; | |
2156 | ||
2157 | opc = xtensa_opcode_decode (isa, ifmt, is, slot); | |
2158 | DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n", | |
2159 | (unsigned)ia, opc); | |
2160 | if (opc == XTENSA_UNDEFINED) | |
2161 | opclass = c0opc_illegal; | |
2162 | else | |
2163 | opclass = call0_classify_opcode (isa, opc); | |
2164 | ||
2165 | /* Decide whether to track this opcode, ignore it, or bail out. */ | |
2166 | ||
2167 | switch (opclass) | |
2168 | { | |
2169 | case c0opc_illegal: | |
2170 | case c0opc_break: | |
2171 | fail = 1; | |
2172 | goto done; | |
2173 | ||
2174 | case c0opc_uninteresting: | |
2175 | continue; | |
2176 | ||
2177 | case c0opc_flow: | |
2178 | goto done; | |
2179 | ||
2180 | case c0opc_entry: | |
2181 | if (call0 != NULL) | |
2182 | *call0 = 0; | |
2183 | ia += ilen; /* Skip over 'entry' insn. */ | |
2184 | goto done; | |
2185 | ||
2186 | default: | |
2187 | if (call0 != NULL) | |
2188 | *call0 = 1; | |
2189 | } | |
2190 | ||
2191 | /* Only expected opcodes should get this far. */ | |
2192 | if (rt == NULL) | |
2193 | continue; | |
2194 | ||
2195 | /* Extract and decode the operands. */ | |
2196 | nods = xtensa_opcode_num_operands (isa, opc); | |
2197 | if (nods == XTENSA_UNDEFINED) | |
2198 | { | |
2199 | fail = 1; | |
2200 | goto done; | |
2201 | } | |
2202 | ||
2203 | for (j = 0; j < nods && j < C0_MAXOPDS; ++j) | |
2204 | { | |
2205 | fail = xtensa_operand_get_field (isa, opc, j, ifmt, | |
2206 | is, slot, &odv[j]); | |
2207 | if (fail) | |
2208 | goto done; | |
2209 | ||
2210 | fail = xtensa_operand_decode (isa, opc, j, &odv[j]); | |
2211 | if (fail) | |
2212 | goto done; | |
2213 | } | |
2214 | ||
2215 | /* Check operands to verify use of 'mov' assembler macro. */ | |
2216 | if (opclass == c0opc_mov && nods == 3) | |
2217 | { | |
2218 | if (odv[2] == odv[1]) | |
2219 | nods = 2; | |
2220 | else | |
2221 | { | |
2222 | opclass = c0opc_uninteresting; | |
2223 | continue; | |
2224 | } | |
2225 | } | |
2226 | ||
2227 | /* Track register movement and modification for this operation. */ | |
2228 | call0_track_op (rt, rtmp, opclass, nods, odv, ia, 1); | |
2229 | } | |
2230 | } | |
2231 | done: | |
2232 | DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n", | |
2233 | (unsigned)ia, fail ? "failed" : "succeeded"); | |
2234 | xtensa_insnbuf_free(isa, slot); | |
2235 | xtensa_insnbuf_free(isa, ins); | |
2236 | return fail ? 0 : ia; | |
2237 | } | |
2238 | ||
2239 | /* Initialize frame cache for the current frame. The "next_frame" is the next | |
2240 | one relative to current frame. "cache" is the pointer to the data structure | |
2241 | we have to initialize. "pc" is curretnt PC. */ | |
2242 | ||
2243 | static void | |
2244 | call0_frame_cache (struct frame_info *next_frame, | |
2245 | xtensa_frame_cache_t *cache, CORE_ADDR pc) | |
2246 | { | |
6b50c0b0 | 2247 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
bdb4c075 MG |
2248 | CORE_ADDR start_pc; /* The beginning of the function. */ |
2249 | CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */ | |
2250 | CORE_ADDR sp, fp, ra; | |
2251 | int fp_regnum, c0_hasfp, c0_frmsz, prev_sp, to_stk; | |
2252 | ||
2253 | /* Find the beginning of the prologue of the function containing the PC | |
2254 | and analyze it up to the PC or the end of the prologue. */ | |
2255 | ||
2256 | if (find_pc_partial_function (pc, NULL, &start_pc, NULL)) | |
2257 | { | |
2258 | body_pc = call0_analyze_prologue (start_pc, pc, C0_NREGS, | |
2259 | &cache->c0.c0_rt[0], | |
2260 | &cache->call0); | |
2261 | } | |
2262 | ||
304fe255 | 2263 | sp = frame_unwind_register_unsigned |
6b50c0b0 | 2264 | (next_frame, gdbarch_tdep (gdbarch)->a0_base + 1); |
bdb4c075 MG |
2265 | fp = sp; /* Assume FP == SP until proven otherwise. */ |
2266 | ||
2267 | /* Get the frame information and FP (if used) at the current PC. | |
2268 | If PC is in the prologue, the prologue analysis is more reliable | |
2269 | than DWARF info. We don't not know for sure if PC is in the prologue, | |
2270 | but we know no calls have yet taken place, so we can almost | |
2271 | certainly rely on the prologue analysis. */ | |
2272 | ||
2273 | if (body_pc <= pc) | |
2274 | { | |
2275 | /* Prologue analysis was successful up to the PC. | |
2276 | It includes the cases when PC == START_PC. */ | |
2277 | c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP; | |
2278 | /* c0_hasfp == true means there is a frame pointer because | |
2279 | we analyzed the prologue and found that cache->c0.c0_rt[C0_FP] | |
2280 | was derived from SP. Otherwise, it would be C0_FP. */ | |
2281 | fp_regnum = c0_hasfp ? C0_FP : C0_SP; | |
2282 | c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs; | |
6b50c0b0 | 2283 | fp_regnum += gdbarch_tdep (gdbarch)->a0_base; |
bdb4c075 MG |
2284 | } |
2285 | else /* No data from the prologue analysis. */ | |
2286 | { | |
2287 | c0_hasfp = 0; | |
6b50c0b0 | 2288 | fp_regnum = gdbarch_tdep (gdbarch)->a0_base + C0_SP; |
bdb4c075 MG |
2289 | c0_frmsz = 0; |
2290 | start_pc = pc; | |
2291 | } | |
2292 | ||
2293 | prev_sp = fp + c0_frmsz; | |
2294 | ||
2295 | /* Frame size from debug info or prologue tracking does not account for | |
2296 | alloca() and other dynamic allocations. Adjust frame size by FP - SP. */ | |
2297 | if (c0_hasfp) | |
2298 | { | |
2299 | fp = frame_unwind_register_unsigned (next_frame, fp_regnum); | |
2300 | ||
2301 | /* Recalculate previous SP. */ | |
2302 | prev_sp = fp + c0_frmsz; | |
2303 | /* Update the stack frame size. */ | |
2304 | c0_frmsz += fp - sp; | |
2305 | } | |
2306 | ||
2307 | /* Get the return address (RA) from the stack if saved, | |
2308 | or try to get it from a register. */ | |
2309 | ||
2310 | to_stk = cache->c0.c0_rt[C0_RA].to_stk; | |
2311 | if (to_stk != C0_NOSTK) | |
2312 | ra = (CORE_ADDR) | |
2313 | read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk, 4); | |
2314 | ||
2315 | else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST | |
2316 | && cache->c0.c0_rt[C0_RA].fr_ofs == 0) | |
2317 | { | |
2318 | /* Special case for terminating backtrace at a function that wants to | |
2319 | be seen as the outermost. Such a function will clear it's RA (A0) | |
2320 | register to 0 in the prologue instead of saving its original value. */ | |
2321 | ra = 0; | |
2322 | } | |
2323 | else | |
2324 | { | |
2325 | /* RA was copied to another register or (before any function call) may | |
2326 | still be in the original RA register. This is not always reliable: | |
2327 | even in a leaf function, register tracking stops after prologue, and | |
2328 | even in prologue, non-prologue instructions (not tracked) may overwrite | |
2329 | RA or any register it was copied to. If likely in prologue or before | |
2330 | any call, use retracking info and hope for the best (compiler should | |
2331 | have saved RA in stack if not in a leaf function). If not in prologue, | |
2332 | too bad. */ | |
2333 | ||
2334 | int i; | |
2335 | for (i = 0; | |
2336 | (i < C0_NREGS) && | |
2337 | (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA); | |
2338 | ++i); | |
2339 | if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA) | |
2340 | i = C0_RA; | |
2341 | if (i < C0_NREGS) /* Read from the next_frame. */ | |
2342 | { | |
304fe255 UW |
2343 | ra = frame_unwind_register_unsigned |
2344 | (next_frame, | |
6b50c0b0 | 2345 | gdbarch_tdep (gdbarch)->a0_base + 0 |
304fe255 | 2346 | + cache->c0.c0_rt[i].fr_reg); |
bdb4c075 MG |
2347 | } |
2348 | else ra = 0; | |
2349 | } | |
2350 | ||
2351 | cache->pc = start_pc; | |
2352 | cache->ra = ra; | |
2353 | /* RA == 0 marks the outermost frame. Do not go past it. */ | |
2354 | cache->prev_sp = (ra != 0) ? prev_sp : 0; | |
2355 | cache->c0.fp_regnum = fp_regnum; | |
2356 | cache->c0.c0_frmsz = c0_frmsz; | |
2357 | cache->c0.c0_hasfp = c0_hasfp; | |
2358 | cache->c0.c0_fp = fp; | |
2359 | } | |
2360 | ||
2361 | ||
2362 | /* Skip function prologue. | |
2363 | ||
2364 | Return the pc of the first instruction after prologue. GDB calls this to | |
2365 | find the address of the first line of the function or (if there is no line | |
2366 | number information) to skip the prologue for planting breakpoints on | |
2367 | function entries. Use debug info (if present) or prologue analysis to skip | |
2368 | the prologue to achieve reliable debugging behavior. For windowed ABI, | |
2369 | only the 'entry' instruction is skipped. It is not strictly necessary to | |
2370 | skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to | |
2371 | backtrace at any point in the prologue, however certain potential hazards | |
2372 | are avoided and a more "normal" debugging experience is ensured by | |
2373 | skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG). | |
2374 | For example, if we don't skip the prologue: | |
2375 | - Some args may not yet have been saved to the stack where the debug | |
2376 | info expects to find them (true anyway when only 'entry' is skipped); | |
2377 | - Software breakpoints ('break' instrs) may not have been unplanted | |
2378 | when the prologue analysis is done on initializing the frame cache, | |
2379 | and breaks in the prologue will throw off the analysis. | |
ca3bf3bd DJ |
2380 | |
2381 | If we have debug info ( line-number info, in particular ) we simply skip | |
2382 | the code associated with the first function line effectively skipping | |
bdb4c075 | 2383 | the prologue code. It works even in cases like |
ca3bf3bd DJ |
2384 | |
2385 | int main() | |
2386 | { int local_var = 1; | |
2387 | .... | |
2388 | } | |
2389 | ||
2390 | because, for this source code, both Xtensa compilers will generate two | |
2391 | separate entries ( with the same line number ) in dwarf line-number | |
2392 | section to make sure there is a boundary between the prologue code and | |
2393 | the rest of the function. | |
2394 | ||
bdb4c075 MG |
2395 | If there is no debug info, we need to analyze the code. */ |
2396 | ||
2397 | /* #define DONT_SKIP_PROLOGUE */ | |
ca3bf3bd DJ |
2398 | |
2399 | CORE_ADDR | |
2400 | xtensa_skip_prologue (CORE_ADDR start_pc) | |
2401 | { | |
bdb4c075 MG |
2402 | struct symtab_and_line prologue_sal; |
2403 | CORE_ADDR body_pc; | |
2404 | ||
ca3bf3bd DJ |
2405 | DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc); |
2406 | ||
bdb4c075 MG |
2407 | #if DONT_SKIP_PROLOGUE |
2408 | return start_pc; | |
2409 | #endif | |
2410 | ||
2411 | /* Try to find first body line from debug info. */ | |
2412 | ||
2413 | prologue_sal = find_pc_line (start_pc, 0); | |
2414 | if (prologue_sal.line != 0) /* Found debug info. */ | |
ca3bf3bd | 2415 | { |
bdb4c075 MG |
2416 | /* In Call0, it is possible to have a function with only one instruction |
2417 | ('ret') resulting from a 1-line optimized function that does nothing. | |
2418 | In that case, prologue_sal.end may actually point to the start of the | |
2419 | next function in the text section, causing a breakpoint to be set at | |
2420 | the wrong place. Check if the end address is in a different function, | |
2421 | and if so return the start PC. We know we have symbol info. */ | |
ca3bf3bd | 2422 | |
bdb4c075 MG |
2423 | CORE_ADDR end_func; |
2424 | ||
2425 | find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL); | |
2426 | if (end_func != start_pc) | |
ca3bf3bd DJ |
2427 | return start_pc; |
2428 | ||
bdb4c075 | 2429 | return prologue_sal.end; |
ca3bf3bd | 2430 | } |
ca3bf3bd | 2431 | |
bdb4c075 MG |
2432 | /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */ |
2433 | body_pc = call0_analyze_prologue(start_pc, 0, 0, NULL, NULL); | |
2434 | return body_pc != 0 ? body_pc : start_pc; | |
2435 | } | |
ca3bf3bd DJ |
2436 | |
2437 | /* Verify the current configuration. */ | |
ca3bf3bd DJ |
2438 | static void |
2439 | xtensa_verify_config (struct gdbarch *gdbarch) | |
2440 | { | |
2441 | struct ui_file *log; | |
2442 | struct cleanup *cleanups; | |
2443 | struct gdbarch_tdep *tdep; | |
2444 | long dummy; | |
2445 | char *buf; | |
2446 | ||
2447 | tdep = gdbarch_tdep (gdbarch); | |
2448 | log = mem_fileopen (); | |
2449 | cleanups = make_cleanup_ui_file_delete (log); | |
2450 | ||
2451 | /* Verify that we got a reasonable number of AREGS. */ | |
2452 | if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs) | |
bdb4c075 MG |
2453 | fprintf_unfiltered (log, _("\ |
2454 | \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"), | |
2455 | tdep->num_aregs); | |
ca3bf3bd DJ |
2456 | |
2457 | /* Verify that certain registers exist. */ | |
bdb4c075 | 2458 | |
ca3bf3bd | 2459 | if (tdep->pc_regnum == -1) |
bdb4c075 MG |
2460 | fprintf_unfiltered (log, _("\n\tpc_regnum: No PC register")); |
2461 | if (tdep->isa_use_exceptions && tdep->ps_regnum == -1) | |
2462 | fprintf_unfiltered (log, _("\n\tps_regnum: No PS register")); | |
2463 | ||
2464 | if (tdep->isa_use_windowed_registers) | |
2465 | { | |
2466 | if (tdep->wb_regnum == -1) | |
2467 | fprintf_unfiltered (log, _("\n\twb_regnum: No WB register")); | |
2468 | if (tdep->ws_regnum == -1) | |
2469 | fprintf_unfiltered (log, _("\n\tws_regnum: No WS register")); | |
2470 | if (tdep->ar_base == -1) | |
2471 | fprintf_unfiltered (log, _("\n\tar_base: No AR registers")); | |
2472 | } | |
2473 | ||
ca3bf3bd | 2474 | if (tdep->a0_base == -1) |
bdb4c075 | 2475 | fprintf_unfiltered (log, _("\n\ta0_base: No Ax registers")); |
ca3bf3bd DJ |
2476 | |
2477 | buf = ui_file_xstrdup (log, &dummy); | |
2478 | make_cleanup (xfree, buf); | |
2479 | if (strlen (buf) > 0) | |
2480 | internal_error (__FILE__, __LINE__, | |
2481 | _("the following are invalid: %s"), buf); | |
2482 | do_cleanups (cleanups); | |
2483 | } | |
2484 | ||
ca3bf3bd DJ |
2485 | /* Module "constructor" function. */ |
2486 | ||
2487 | static struct gdbarch * | |
2488 | xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2489 | { | |
2490 | struct gdbarch_tdep *tdep; | |
2491 | struct gdbarch *gdbarch; | |
2492 | struct xtensa_abi_handler *abi_handler; | |
2493 | ||
2494 | DEBUGTRACE ("gdbarch_init()\n"); | |
2495 | ||
2496 | /* We have to set the byte order before we call gdbarch_alloc. */ | |
2497 | info.byte_order = xtensa_config_byte_order (&info); | |
2498 | ||
2499 | tdep = xtensa_config_tdep (&info); | |
2500 | gdbarch = gdbarch_alloc (&info, tdep); | |
2501 | ||
2502 | /* Verify our configuration. */ | |
2503 | xtensa_verify_config (gdbarch); | |
2504 | ||
bdb4c075 | 2505 | /* Pseudo-Register read/write. */ |
ca3bf3bd DJ |
2506 | set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read); |
2507 | set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write); | |
2508 | ||
2509 | /* Set target information. */ | |
2510 | set_gdbarch_num_regs (gdbarch, tdep->num_regs); | |
2511 | set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs); | |
2512 | set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1); | |
2513 | set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum); | |
2514 | set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum); | |
2515 | ||
2516 | /* Renumber registers for known formats (stab, dwarf, and dwarf2). */ | |
2517 | set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); | |
2518 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); | |
2519 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); | |
2520 | ||
2521 | /* We provide our own function to get register information. */ | |
2522 | set_gdbarch_register_name (gdbarch, xtensa_register_name); | |
2523 | set_gdbarch_register_type (gdbarch, xtensa_register_type); | |
2524 | ||
2525 | /* To call functions from GDB using dummy frame */ | |
2526 | set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call); | |
2527 | ||
2528 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); | |
2529 | ||
2530 | set_gdbarch_return_value (gdbarch, xtensa_return_value); | |
2531 | ||
2532 | /* Advance PC across any prologue instructions to reach "real" code. */ | |
2533 | set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue); | |
2534 | ||
2535 | /* Stack grows downward. */ | |
2536 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2537 | ||
2538 | /* Set breakpoints. */ | |
2539 | set_gdbarch_breakpoint_from_pc (gdbarch, xtensa_breakpoint_from_pc); | |
2540 | ||
2541 | /* After breakpoint instruction or illegal instruction, pc still | |
2542 | points at break instruction, so don't decrement. */ | |
2543 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
2544 | ||
2545 | /* We don't skip args. */ | |
2546 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
2547 | ||
2548 | set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc); | |
2549 | ||
2550 | set_gdbarch_frame_align (gdbarch, xtensa_frame_align); | |
2551 | ||
2552 | set_gdbarch_unwind_dummy_id (gdbarch, xtensa_unwind_dummy_id); | |
2553 | ||
2554 | /* Frame handling. */ | |
2555 | frame_base_set_default (gdbarch, &xtensa_frame_base); | |
2556 | frame_unwind_append_sniffer (gdbarch, xtensa_frame_sniffer); | |
2557 | ||
2558 | set_gdbarch_print_insn (gdbarch, print_insn_xtensa); | |
2559 | ||
2560 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
2561 | ||
2562 | xtensa_add_reggroups (gdbarch); | |
2563 | set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p); | |
2564 | ||
2565 | set_gdbarch_regset_from_core_section (gdbarch, | |
2566 | xtensa_regset_from_core_section); | |
2567 | ||
2568 | return gdbarch; | |
2569 | } | |
2570 | ||
ca3bf3bd | 2571 | static void |
6b50c0b0 | 2572 | xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
ca3bf3bd DJ |
2573 | { |
2574 | error (_("xtensa_dump_tdep(): not implemented")); | |
2575 | } | |
2576 | ||
ca3bf3bd DJ |
2577 | void |
2578 | _initialize_xtensa_tdep (void) | |
2579 | { | |
2580 | struct cmd_list_element *c; | |
2581 | ||
2582 | gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep); | |
2583 | xtensa_init_reggroups (); | |
2584 | ||
2585 | add_setshow_zinteger_cmd ("xtensa", | |
2586 | class_maintenance, | |
2587 | &xtensa_debug_level, _("\ | |
2588 | Set Xtensa debugging."), _("\ | |
2589 | Show Xtensa debugging."), _("\ | |
2590 | When non-zero, Xtensa-specific debugging is enabled. \ | |
2591 | Can be 1, 2, 3, or 4 indicating the level of debugging."), | |
2592 | NULL, | |
2593 | NULL, | |
2594 | &setdebuglist, &showdebuglist); | |
2595 | } |