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* minsyms.c: Include "target.h".
[deliverable/binutils-gdb.git] / gdb / xtensa-tdep.c
CommitLineData
ca3bf3bd
DJ		 1/* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
2
9b254dd1 3 Copyright (C) 2003, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
ca3bf3bd
DJ		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
ca3bf3bd
DJ		 10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
ca3bf3bd
DJ		 19
20#include "defs.h"
21#include "frame.h"
ee967b5f 22#include "solib-svr4.h"
ca3bf3bd
DJ		 23#include "symtab.h"
24#include "symfile.h"
25#include "objfiles.h"
26#include "gdbtypes.h"
27#include "gdbcore.h"
28#include "value.h"
29#include "dis-asm.h"
30#include "inferior.h"
31#include "floatformat.h"
32#include "regcache.h"
33#include "reggroups.h"
34#include "regset.h"
35
36#include "dummy-frame.h"
37#include "elf/dwarf2.h"
38#include "dwarf2-frame.h"
39#include "dwarf2loc.h"
40#include "frame.h"
41#include "frame-base.h"
42#include "frame-unwind.h"
43
44#include "arch-utils.h"
45#include "gdbarch.h"
46#include "remote.h"
47#include "serial.h"
48
49#include "command.h"
50#include "gdbcmd.h"
51#include "gdb_assert.h"
52
bdb4c075 53#include "xtensa-isa.h"
ca3bf3bd 54#include "xtensa-tdep.h"
94a0e877 55#include "xtensa-config.h"
ca3bf3bd
DJ		 56
57
58static int xtensa_debug_level = 0;
59
60#define DEBUGWARN(args...) \
61 if (xtensa_debug_level > 0) \
62 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
63
64#define DEBUGINFO(args...) \
65 if (xtensa_debug_level > 1) \
66 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
67
68#define DEBUGTRACE(args...) \
69 if (xtensa_debug_level > 2) \
70 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
71
72#define DEBUGVERB(args...) \
73 if (xtensa_debug_level > 3) \
74 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
75
76
77/* According to the ABI, the SP must be aligned to 16-byte boundaries. */
ca3bf3bd
DJ		 78#define SP_ALIGNMENT 16
79
80
bdb4c075
MG		 81/* On Windowed ABI, we use a6 through a11 for passing arguments
82 to a function called by GDB because CALL4 is used. */
bdb4c075
MG		 83#define ARGS_NUM_REGS 6
84#define REGISTER_SIZE 4
ca3bf3bd 85
ca3bf3bd 86
bdb4c075
MG		 87/* Extract the call size from the return address or PS register. */
88#define PS_CALLINC_SHIFT 16
89#define PS_CALLINC_MASK 0x00030000
90#define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
91#define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
ca3bf3bd 92
bdb4c075 93/* ABI-independent macros. */
91d8eb23
MD		 94#define ARG_NOF(gdbarch) \
95 (gdbarch_tdep (gdbarch)->call_abi \
96 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
97#define ARG_1ST(gdbarch) \
98 (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \
94a0e877 99 ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \
91d8eb23 100 : (gdbarch_tdep (gdbarch)->a0_base + 6))
ca3bf3bd 101
ca3bf3bd
DJ		 102/* XTENSA_IS_ENTRY tests whether the first byte of an instruction
103 indicates that the instruction is an ENTRY instruction. */
104
91d8eb23
MD		 105#define XTENSA_IS_ENTRY(gdbarch, op1) \
106 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
4c6b5505 107 ? ((op1) == 0x6c) : ((op1) == 0x36))
ca3bf3bd 108
bdb4c075 109#define XTENSA_ENTRY_LENGTH 3
ca3bf3bd
DJ		 110
111/* windowing_enabled() returns true, if windowing is enabled.
112 WOE must be set to 1; EXCM to 0.
113 Note: We assume that EXCM is always 0 for XEA1. */
114
bdb4c075
MG		 115#define PS_WOE (1<<18)
116#define PS_EXC (1<<4)
117
ee967b5f 118/* Convert a live A-register number to the corresponding AR-register number. */
91d8eb23 119static int
ee967b5f 120arreg_number (struct gdbarch *gdbarch, int a_regnum, ULONGEST wb)
91d8eb23
MD		 121{
122 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
ee967b5f 123 int arreg;
91d8eb23 124
ee967b5f
MG		 125 arreg = a_regnum - tdep->a0_base;
126 arreg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT;
127 arreg &= tdep->num_aregs - 1;
91d8eb23 128
ee967b5f
MG		 129 return arreg + tdep->ar_base;
130}
131
132/* Convert a live AR-register number to the corresponding A-register order
133 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
134static int
135areg_number (struct gdbarch *gdbarch, int ar_regnum, unsigned int wb)
136{
137 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
138 int areg;
139
140 areg = ar_regnum - tdep->ar_base;
141 if (areg < 0 || areg >= tdep->num_aregs)
142 return -1;
143 areg = (areg - wb * 4) & (tdep->num_aregs - 1);
144 return (areg > 15) ? -1 : areg;
91d8eb23
MD		 145}
146
ca3bf3bd
DJ		 147static inline int
148windowing_enabled (CORE_ADDR ps)
149{
bdb4c075 150 return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0);
ca3bf3bd
DJ		 151}
152
153/* Return the window size of the previous call to the function from which we
154 have just returned.
155
156 This function is used to extract the return value after a called function
bdb4c075 157 has returned to the caller. On Xtensa, the register that holds the return
ca3bf3bd
DJ		 158 value (from the perspective of the caller) depends on what call
159 instruction was used. For now, we are assuming that the call instruction
160 precedes the current address, so we simply analyze the call instruction.
161 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
162 method to call the inferior function. */
163
164static int
91d8eb23 165extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc)
ca3bf3bd 166{
bdb4c075 167 int winsize = 4;
ca3bf3bd 168 int insn;
ff7a4c00 169 gdb_byte buf[4];
ca3bf3bd
DJ		 170
171 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc);
172
173 /* Read the previous instruction (should be a call[x]{4|8|12}. */
174 read_memory (pc-3, buf, 3);
175 insn = extract_unsigned_integer (buf, 3);
176
177 /* Decode call instruction:
178 Little Endian
179 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
180 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
181 Big Endian
182 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
183 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
184
91d8eb23 185 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
ca3bf3bd
DJ		 186 {
187 if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0))
bdb4c075 188 winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */
ca3bf3bd
DJ		 189 }
190 else
191 {
192 if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03))
bdb4c075 193 winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */
ca3bf3bd
DJ		 194 }
195 return winsize;
196}
197
198
199/* REGISTER INFORMATION */
200
201/* Returns the name of a register. */
ca3bf3bd 202static const char *
d93859e2 203xtensa_register_name (struct gdbarch *gdbarch, int regnum)
ca3bf3bd
DJ		 204{
205 /* Return the name stored in the register map. */
d93859e2
UW		 206 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
207 + gdbarch_num_pseudo_regs (gdbarch))
208 return gdbarch_tdep (gdbarch)->regmap[regnum].name;
ca3bf3bd 209
ca3bf3bd
DJ		 210 internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum);
211 return 0;
212}
213
bdb4c075
MG		 214static unsigned long
215xtensa_read_register (int regnum)
216{
217 ULONGEST value;
218
219 regcache_raw_read_unsigned (get_current_regcache (), regnum, &value);
220 return (unsigned long) value;
221}
ca3bf3bd
DJ		 222
223/* Return the type of a register. Create a new type, if necessary. */
224
225static struct ctype_cache
226{
227 struct ctype_cache *next;
228 int size;
229 struct type *virtual_type;
230} *type_entries = NULL;
231
232static struct type *
233xtensa_register_type (struct gdbarch *gdbarch, int regnum)
234{
235 /* Return signed integer for ARx and Ax registers. */
6b50c0b0
UW		 236 if ((regnum >= gdbarch_tdep (gdbarch)->ar_base
237 && regnum < gdbarch_tdep (gdbarch)->ar_base
238 + gdbarch_tdep (gdbarch)->num_aregs)
239 || (regnum >= gdbarch_tdep (gdbarch)->a0_base
240 && regnum < gdbarch_tdep (gdbarch)->a0_base + 16))
ca3bf3bd
DJ		 241 return builtin_type_int;
242
6b50c0b0
UW		 243 if (regnum == gdbarch_pc_regnum (gdbarch)
244 || regnum == gdbarch_tdep (gdbarch)->a0_base + 1)
ca3bf3bd
DJ		 245 return lookup_pointer_type (builtin_type_void);
246
247 /* Return the stored type for all other registers. */
6b50c0b0
UW		 248 else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
249 + gdbarch_num_pseudo_regs (gdbarch))
ca3bf3bd 250 {
6b50c0b0 251 xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
ca3bf3bd 252
bdb4c075 253 /* Set ctype for this register (only the first time). */
ca3bf3bd
DJ		 254
255 if (reg->ctype == 0)
256 {
257 struct ctype_cache *tp;
258 int size = reg->byte_size;
259
bdb4c075
MG		 260 /* We always use the memory representation,
261 even if the register width is smaller. */
ca3bf3bd
DJ		 262 switch (size)
263 {
264 case 1:
265 reg->ctype = builtin_type_uint8;
266 break;
267
268 case 2:
269 reg->ctype = builtin_type_uint16;
270 break;
271
272 case 4:
273 reg->ctype = builtin_type_uint32;
274 break;
275
276 case 8:
277 reg->ctype = builtin_type_uint64;
278 break;
279
280 case 16:
281 reg->ctype = builtin_type_uint128;
282 break;
283
284 default:
285 for (tp = type_entries; tp != NULL; tp = tp->next)
286 if (tp->size == size)
287 break;
288
289 if (tp == NULL)
290 {
291 char *name = xmalloc (16);
292 tp = xmalloc (sizeof (struct ctype_cache));
293 tp->next = type_entries;
294 type_entries = tp;
295 tp->size = size;
296
297 sprintf (name, "int%d", size * 8);
298 tp->virtual_type = init_type (TYPE_CODE_INT, size,
299 TYPE_FLAG_UNSIGNED, name,
300 NULL);
301 }
302
303 reg->ctype = tp->virtual_type;
304 }
305 }
306 return reg->ctype;
307 }
308
ca3bf3bd
DJ		 309 internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum);
310 return 0;
311}
312
313
bdb4c075 314/* Return the 'local' register number for stubs, dwarf2, etc.
ca3bf3bd
DJ		 315 The debugging information enumerates registers starting from 0 for A0
316 to n for An. So, we only have to add the base number for A0. */
317
318static int
d3f73121 319xtensa_reg_to_regnum (struct gdbarch *gdbarch, int regnum)
ca3bf3bd
DJ		 320{
321 int i;
322
323 if (regnum >= 0 && regnum < 16)
d3f73121 324 return gdbarch_tdep (gdbarch)->a0_base + regnum;
ca3bf3bd 325
f57d151a 326 for (i = 0;
d3f73121 327 i < gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
f57d151a 328 i++)
d3f73121 329 if (regnum == gdbarch_tdep (gdbarch)->regmap[i].target_number)
ca3bf3bd
DJ		 330 return i;
331
ca3bf3bd
DJ		 332 internal_error (__FILE__, __LINE__,
333 _("invalid dwarf/stabs register number %d"), regnum);
334 return 0;
335}
336
337
bdb4c075
MG		 338/* Write the bits of a masked register to the various registers.
339 Only the masked areas of these registers are modified; the other
340 fields are untouched. The size of masked registers is always less
341 than or equal to 32 bits. */
ca3bf3bd
DJ		 342
343static void
9c9acae0
UW		 344xtensa_register_write_masked (struct regcache *regcache,
345 xtensa_register_t *reg, const gdb_byte *buffer)
ca3bf3bd
DJ		 346{
347 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
ca3bf3bd
DJ		 348 const xtensa_mask_t *mask = reg->mask;
349
350 int shift = 0; /* Shift for next mask (mod 32). */
351 int start, size; /* Start bit and size of current mask. */
352
353 unsigned int *ptr = value;
354 unsigned int regval, m, mem = 0;
355
356 int bytesize = reg->byte_size;
357 int bitsize = bytesize * 8;
358 int i, r;
359
360 DEBUGTRACE ("xtensa_register_write_masked ()\n");
361
362 /* Copy the masked register to host byte-order. */
6b50c0b0 363 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
ca3bf3bd
DJ		 364 for (i = 0; i < bytesize; i++)
365 {
366 mem >>= 8;
367 mem |= (buffer[bytesize - i - 1] << 24);
368 if ((i & 3) == 3)
369 *ptr++ = mem;
370 }
371 else
372 for (i = 0; i < bytesize; i++)
373 {
374 mem >>= 8;
375 mem |= (buffer[i] << 24);
376 if ((i & 3) == 3)
377 *ptr++ = mem;
378 }
379
380 /* We might have to shift the final value:
381 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
382 bytesize & 3 == x -> shift (4-x) * 8. */
383
384 *ptr = mem >> (((0 - bytesize) & 3) * 8);
385 ptr = value;
386 mem = *ptr;
387
388 /* Write the bits to the masked areas of the other registers. */
389 for (i = 0; i < mask->count; i++)
390 {
391 start = mask->mask[i].bit_start;
392 size = mask->mask[i].bit_size;
393 regval = mem >> shift;
394
395 if ((shift += size) > bitsize)
396 error (_("size of all masks is larger than the register"));
397
398 if (shift >= 32)
399 {
400 mem = *(++ptr);
401 shift -= 32;
402 bitsize -= 32;
403
404 if (shift > 0)
405 regval |= mem << (size - shift);
406 }
407
408 /* Make sure we have a valid register. */
409 r = mask->mask[i].reg_num;
410 if (r >= 0 && size > 0)
411 {
412 /* Don't overwrite the unmasked areas. */
9c9acae0
UW		 413 ULONGEST old_val;
414 regcache_cooked_read_unsigned (regcache, r, &old_val);
ca3bf3bd
DJ		 415 m = 0xffffffff >> (32 - size) << start;
416 regval <<= start;
9c9acae0
UW		 417 regval = (regval & m) | (old_val & ~m);
418 regcache_cooked_write_unsigned (regcache, r, regval);
ca3bf3bd
DJ		 419 }
420 }
421}
422
423
bdb4c075
MG		 424/* Read a tie state or mapped registers. Read the masked areas
425 of the registers and assemble them into a single value. */
ca3bf3bd
DJ		 426
427static void
9c9acae0
UW		 428xtensa_register_read_masked (struct regcache *regcache,
429 xtensa_register_t *reg, gdb_byte *buffer)
ca3bf3bd
DJ		 430{
431 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
ca3bf3bd
DJ		 432 const xtensa_mask_t *mask = reg->mask;
433
434 int shift = 0;
435 int start, size;
436
437 unsigned int *ptr = value;
438 unsigned int regval, mem = 0;
439
440 int bytesize = reg->byte_size;
441 int bitsize = bytesize * 8;
442 int i;
443
444 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
445 reg->name == 0 ? "" : reg->name);
446
447 /* Assemble the register from the masked areas of other registers. */
448 for (i = 0; i < mask->count; i++)
449 {
450 int r = mask->mask[i].reg_num;
9c9acae0
UW		 451 if (r >= 0)
452 {
453 ULONGEST val;
454 regcache_cooked_read_unsigned (regcache, r, &val);
455 regval = (unsigned int) val;
456 }
457 else
458 regval = 0;
459
ca3bf3bd
DJ		 460 start = mask->mask[i].bit_start;
461 size = mask->mask[i].bit_size;
462
463 regval >>= start;
464
465 if (size < 32)
466 regval &= (0xffffffff >> (32 - size));
467
468 mem |= regval << shift;
469
470 if ((shift += size) > bitsize)
471 error (_("size of all masks is larger than the register"));
472
473 if (shift >= 32)
474 {
475 *ptr++ = mem;
476 bitsize -= 32;
477 shift -= 32;
478
479 if (shift == 0)
480 mem = 0;
481 else
482 mem = regval >> (size - shift);
483 }
484 }
485
486 if (shift > 0)
487 *ptr = mem;
488
489 /* Copy value to target byte order. */
490 ptr = value;
491 mem = *ptr;
492
6b50c0b0 493 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
ca3bf3bd
DJ		 494 for (i = 0; i < bytesize; i++)
495 {
496 if ((i & 3) == 0)
497 mem = *ptr++;
498 buffer[bytesize - i - 1] = mem & 0xff;
499 mem >>= 8;
500 }
501 else
502 for (i = 0; i < bytesize; i++)
503 {
504 if ((i & 3) == 0)
505 mem = *ptr++;
506 buffer[i] = mem & 0xff;
507 mem >>= 8;
508 }
509}
510
511
512/* Read pseudo registers. */
513
514static void
515xtensa_pseudo_register_read (struct gdbarch *gdbarch,
516 struct regcache *regcache,
517 int regnum,
518 gdb_byte *buffer)
519{
520 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
d93859e2 521 regnum, xtensa_register_name (gdbarch, regnum));
ca3bf3bd 522
6b50c0b0 523 if (regnum == gdbarch_num_regs (gdbarch)
94a0e877 524 + gdbarch_num_pseudo_regs (gdbarch) - 1)
6b50c0b0 525 regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
ca3bf3bd 526
bdb4c075 527 /* Read aliases a0..a15, if this is a Windowed ABI. */
6b50c0b0 528 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
94a0e877 529 && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
6b50c0b0 530 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
ca3bf3bd 531 {
ff7a4c00 532 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
ca3bf3bd 533
6b50c0b0 534 regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
ee967b5f
MG		 535 regnum = arreg_number (gdbarch, regnum,
536 extract_unsigned_integer (buf, 4));
ca3bf3bd
DJ		 537 }
538
bdb4c075 539 /* We can always read non-pseudo registers. */
6b50c0b0 540 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
ca3bf3bd
DJ		 541 regcache_raw_read (regcache, regnum, buffer);
542
94a0e877
MG		 543
544 /* We have to find out how to deal with priveleged registers.
545 Let's treat them as pseudo-registers, but we cannot read/write them. */
546
547 else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
548 {
549 buffer[0] = (gdb_byte)0;
550 buffer[1] = (gdb_byte)0;
551 buffer[2] = (gdb_byte)0;
552 buffer[3] = (gdb_byte)0;
553 }
ca3bf3bd 554 /* Pseudo registers. */
f57d151a 555 else if (regnum >= 0
6b50c0b0
UW		 556 && regnum < gdbarch_num_regs (gdbarch)
557 + gdbarch_num_pseudo_regs (gdbarch))
ca3bf3bd 558 {
6b50c0b0 559 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
ca3bf3bd 560 xtensa_register_type_t type = reg->type;
6b50c0b0 561 int flags = gdbarch_tdep (gdbarch)->target_flags;
ca3bf3bd 562
bdb4c075 563 /* We cannot read Unknown or Unmapped registers. */
ca3bf3bd
DJ		 564 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
565 {
566 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
567 {
568 warning (_("cannot read register %s"),
d93859e2 569 xtensa_register_name (gdbarch, regnum));
ca3bf3bd
DJ		 570 return;
571 }
572 }
573
574 /* Some targets cannot read TIE register files. */
575 else if (type == xtRegisterTypeTieRegfile)
576 {
577 /* Use 'fetch' to get register? */
578 if (flags & xtTargetFlagsUseFetchStore)
579 {
580 warning (_("cannot read register"));
581 return;
582 }
583
584 /* On some targets (esp. simulators), we can always read the reg. */
585 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
586 {
587 warning (_("cannot read register"));
588 return;
589 }
590 }
591
592 /* We can always read mapped registers. */
593 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
594 {
9c9acae0 595 xtensa_register_read_masked (regcache, reg, buffer);
ca3bf3bd
DJ		 596 return;
597 }
598
599 /* Assume that we can read the register. */
600 regcache_raw_read (regcache, regnum, buffer);
601 }
ca3bf3bd
DJ		 602 else
603 internal_error (__FILE__, __LINE__,
604 _("invalid register number %d"), regnum);
605}
606
607
608/* Write pseudo registers. */
609
610static void
611xtensa_pseudo_register_write (struct gdbarch *gdbarch,
612 struct regcache *regcache,
613 int regnum,
614 const gdb_byte *buffer)
615{
616 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
d93859e2 617 regnum, xtensa_register_name (gdbarch, regnum));
ca3bf3bd 618
6b50c0b0 619 if (regnum == gdbarch_num_regs (gdbarch)
94a0e877 620 + gdbarch_num_pseudo_regs (gdbarch) -1)
6b50c0b0 621 regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
ca3bf3bd 622
bdb4c075 623 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
6b50c0b0 624 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
94a0e877 625 && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
6b50c0b0 626 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
ca3bf3bd 627 {
ff7a4c00 628 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
ca3bf3bd
DJ		 629 unsigned int wb;
630
304fe255 631 regcache_raw_read (regcache,
6b50c0b0 632 gdbarch_tdep (gdbarch)->wb_regnum, buf);
ee967b5f
MG		 633 regnum = arreg_number (gdbarch, regnum,
634 extract_unsigned_integer (buf, 4));
ca3bf3bd
DJ		 635 }
636
637 /* We can always write 'core' registers.
638 Note: We might have converted Ax->ARy. */
6b50c0b0 639 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
ca3bf3bd
DJ		 640 regcache_raw_write (regcache, regnum, buffer);
641
94a0e877
MG		 642 /* We have to find out how to deal with priveleged registers.
643 Let's treat them as pseudo-registers, but we cannot read/write them. */
644
645 else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
646 {
647 return;
648 }
ca3bf3bd 649 /* Pseudo registers. */
f57d151a 650 else if (regnum >= 0
6b50c0b0
UW		 651 && regnum < gdbarch_num_regs (gdbarch)
652 + gdbarch_num_pseudo_regs (gdbarch))
ca3bf3bd 653 {
6b50c0b0 654 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
ca3bf3bd 655 xtensa_register_type_t type = reg->type;
6b50c0b0 656 int flags = gdbarch_tdep (gdbarch)->target_flags;
ca3bf3bd 657
bdb4c075
MG		 658 /* On most targets, we cannot write registers
659 of type "Unknown" or "Unmapped". */
ca3bf3bd
DJ		 660 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
661 {
662 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
663 {
664 warning (_("cannot write register %s"),
d93859e2 665 xtensa_register_name (gdbarch, regnum));
ca3bf3bd
DJ		 666 return;
667 }
668 }
669
670 /* Some targets cannot read TIE register files. */
671 else if (type == xtRegisterTypeTieRegfile)
672 {
673 /* Use 'store' to get register? */
674 if (flags & xtTargetFlagsUseFetchStore)
675 {
676 warning (_("cannot write register"));
677 return;
678 }
679
680 /* On some targets (esp. simulators), we can always write
681 the register. */
ca3bf3bd
DJ		 682 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
683 {
684 warning (_("cannot write register"));
685 return;
686 }
687 }
688
689 /* We can always write mapped registers. */
690 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
691 {
9c9acae0 692 xtensa_register_write_masked (regcache, reg, buffer);
ca3bf3bd
DJ		 693 return;
694 }
695
696 /* Assume that we can write the register. */
697 regcache_raw_write (regcache, regnum, buffer);
698 }
ca3bf3bd
DJ		 699 else
700 internal_error (__FILE__, __LINE__,
701 _("invalid register number %d"), regnum);
702}
703
ca3bf3bd
DJ		 704static struct reggroup *xtensa_ar_reggroup;
705static struct reggroup *xtensa_user_reggroup;
706static struct reggroup *xtensa_vectra_reggroup;
7b871568 707static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR];
ca3bf3bd
DJ		 708
709static void
710xtensa_init_reggroups (void)
711{
712 xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP);
713 xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP);
714 xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP);
ca3bf3bd 715
7b871568
MG		 716 xtensa_cp[0] = reggroup_new ("cp0", USER_REGGROUP);
717 xtensa_cp[1] = reggroup_new ("cp1", USER_REGGROUP);
718 xtensa_cp[2] = reggroup_new ("cp2", USER_REGGROUP);
719 xtensa_cp[3] = reggroup_new ("cp3", USER_REGGROUP);
720 xtensa_cp[4] = reggroup_new ("cp4", USER_REGGROUP);
721 xtensa_cp[5] = reggroup_new ("cp5", USER_REGGROUP);
722 xtensa_cp[6] = reggroup_new ("cp6", USER_REGGROUP);
723 xtensa_cp[7] = reggroup_new ("cp7", USER_REGGROUP);
724}
ca3bf3bd
DJ		 725
726static void
727xtensa_add_reggroups (struct gdbarch *gdbarch)
728{
7b871568
MG		 729 int i;
730
731 /* Predefined groups. */
ca3bf3bd
DJ		 732 reggroup_add (gdbarch, all_reggroup);
733 reggroup_add (gdbarch, save_reggroup);
734 reggroup_add (gdbarch, restore_reggroup);
735 reggroup_add (gdbarch, system_reggroup);
7b871568
MG		 736 reggroup_add (gdbarch, vector_reggroup);
737 reggroup_add (gdbarch, general_reggroup);
738 reggroup_add (gdbarch, float_reggroup);
739
740 /* Xtensa-specific groups. */
741 reggroup_add (gdbarch, xtensa_ar_reggroup);
742 reggroup_add (gdbarch, xtensa_user_reggroup);
743 reggroup_add (gdbarch, xtensa_vectra_reggroup);
ca3bf3bd 744
7b871568
MG		 745 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
746 reggroup_add (gdbarch, xtensa_cp[i]);
ca3bf3bd
DJ		 747}
748
7b871568
MG		 749static int
750xtensa_coprocessor_register_group (struct reggroup *group)
751{
752 int i;
753
754 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
755 if (group == xtensa_cp[i])
756 return i;
757
758 return -1;
759}
ca3bf3bd
DJ		 760
761#define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
762 | XTENSA_REGISTER_FLAGS_WRITABLE \
763 | XTENSA_REGISTER_FLAGS_VOLATILE)
764
765#define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
766 | XTENSA_REGISTER_FLAGS_WRITABLE)
767
768static int
769xtensa_register_reggroup_p (struct gdbarch *gdbarch,
770 int regnum,
771 struct reggroup *group)
772{
6b50c0b0 773 xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
ca3bf3bd
DJ		 774 xtensa_register_type_t type = reg->type;
775 xtensa_register_group_t rg = reg->group;
7b871568 776 int cp_number;
ca3bf3bd
DJ		 777
778 /* First, skip registers that are not visible to this target
779 (unknown and unmapped registers when not using ISS). */
780
781 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
782 return 0;
783 if (group == all_reggroup)
784 return 1;
785 if (group == xtensa_ar_reggroup)
786 return rg & xtRegisterGroupAddrReg;
787 if (group == xtensa_user_reggroup)
788 return rg & xtRegisterGroupUser;
789 if (group == float_reggroup)
790 return rg & xtRegisterGroupFloat;
791 if (group == general_reggroup)
792 return rg & xtRegisterGroupGeneral;
793 if (group == float_reggroup)
794 return rg & xtRegisterGroupFloat;
795 if (group == system_reggroup)
796 return rg & xtRegisterGroupState;
797 if (group == vector_reggroup || group == xtensa_vectra_reggroup)
798 return rg & xtRegisterGroupVectra;
799 if (group == save_reggroup || group == restore_reggroup)
6b50c0b0 800 return (regnum < gdbarch_num_regs (gdbarch)
ca3bf3bd 801 && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID);
7b871568
MG		 802 if ((cp_number = xtensa_coprocessor_register_group (group)) >= 0)
803 return rg & (xtRegisterGroupCP0 << cp_number);
ca3bf3bd
DJ		 804 else
805 return 1;
806}
807
808
ca3bf3bd
DJ		 809/* Supply register REGNUM from the buffer specified by GREGS and LEN
810 in the general-purpose register set REGSET to register cache
bdb4c075 811 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
ca3bf3bd
DJ		 812
813static void
814xtensa_supply_gregset (const struct regset *regset,
815 struct regcache *rc,
816 int regnum,
817 const void *gregs,
818 size_t len)
819{
820 const xtensa_elf_gregset_t *regs = gregs;
6b50c0b0 821 struct gdbarch *gdbarch = get_regcache_arch (rc);
ca3bf3bd
DJ		 822 int i;
823
824 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...) \n", regnum);
825
6b50c0b0
UW		 826 if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1)
827 regcache_raw_supply (rc, gdbarch_pc_regnum (gdbarch), (char *) &regs->pc);
828 if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1)
829 regcache_raw_supply (rc, gdbarch_ps_regnum (gdbarch), (char *) &regs->ps);
830 if (regnum == gdbarch_tdep (gdbarch)->wb_regnum || regnum == -1)
831 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->wb_regnum,
304fe255 832 (char *) &regs->windowbase);
6b50c0b0
UW		 833 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum || regnum == -1)
834 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ws_regnum,
304fe255 835 (char *) &regs->windowstart);
6b50c0b0
UW		 836 if (regnum == gdbarch_tdep (gdbarch)->lbeg_regnum || regnum == -1)
837 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lbeg_regnum,
304fe255 838 (char *) &regs->lbeg);
6b50c0b0
UW		 839 if (regnum == gdbarch_tdep (gdbarch)->lend_regnum || regnum == -1)
840 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lend_regnum,
304fe255 841 (char *) &regs->lend);
6b50c0b0
UW		 842 if (regnum == gdbarch_tdep (gdbarch)->lcount_regnum || regnum == -1)
843 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lcount_regnum,
304fe255 844 (char *) &regs->lcount);
6b50c0b0
UW		 845 if (regnum == gdbarch_tdep (gdbarch)->sar_regnum || regnum == -1)
846 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->sar_regnum,
304fe255 847 (char *) &regs->sar);
6b50c0b0
UW		 848 if (regnum >=gdbarch_tdep (gdbarch)->ar_base
849 && regnum < gdbarch_tdep (gdbarch)->ar_base
850 + gdbarch_tdep (gdbarch)->num_aregs)
304fe255
UW		 851 regcache_raw_supply (rc, regnum,
852 (char *) &regs->ar[regnum - gdbarch_tdep
6b50c0b0 853 (gdbarch)->ar_base]);
ca3bf3bd
DJ		 854 else if (regnum == -1)
855 {
6b50c0b0
UW		 856 for (i = 0; i < gdbarch_tdep (gdbarch)->num_aregs; ++i)
857 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ar_base + i,
304fe255 858 (char *) &regs->ar[i]);
ca3bf3bd
DJ		 859 }
860}
861
862
863/* Xtensa register set. */
864
865static struct regset
866xtensa_gregset =
867{
868 NULL,
869 xtensa_supply_gregset
870};
871
872
bdb4c075
MG		 873/* Return the appropriate register set for the core
874 section identified by SECT_NAME and SECT_SIZE. */
ca3bf3bd
DJ		 875
876static const struct regset *
877xtensa_regset_from_core_section (struct gdbarch *core_arch,
878 const char *sect_name,
879 size_t sect_size)
880{
881 DEBUGTRACE ("xtensa_regset_from_core_section "
882 "(..., sect_name==\"%s\", sect_size==%x) \n",
ec20a626 883 sect_name, (unsigned int) sect_size);
ca3bf3bd
DJ		 884
885 if (strcmp (sect_name, ".reg") == 0
886 && sect_size >= sizeof(xtensa_elf_gregset_t))
887 return &xtensa_gregset;
888
889 return NULL;
890}
891
892
bdb4c075 893/* Handling frames. */
ca3bf3bd 894
bdb4c075
MG		 895/* Number of registers to save in case of Windowed ABI. */
896#define XTENSA_NUM_SAVED_AREGS 12
ca3bf3bd 897
bdb4c075
MG		 898/* Frame cache part for Windowed ABI. */
899typedef struct xtensa_windowed_frame_cache
ca3bf3bd 900{
ee967b5f
MG		 901 int wb; /* WINDOWBASE of the previous frame. */
902 int callsize; /* Call size of this frame. */
903 int ws; /* WINDOWSTART of the previous frame. It keeps track of
904 life windows only. If there is no bit set for the
905 window, that means it had been already spilled
906 because of window overflow. */
907
908 /* Spilled A-registers from the previous frame.
909 AREGS[i] == -1, if corresponding AR is alive. */
ca3bf3bd 910 CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS];
bdb4c075
MG		 911} xtensa_windowed_frame_cache_t;
912
913/* Call0 ABI Definitions. */
914
915#define C0_MAXOPDS 3 /* Maximum number of operands for prologue analysis. */
916#define C0_NREGS 16 /* Number of A-registers to track. */
917#define C0_CLESV 12 /* Callee-saved registers are here and up. */
918#define C0_SP 1 /* Register used as SP. */
919#define C0_FP 15 /* Register used as FP. */
920#define C0_RA 0 /* Register used as return address. */
921#define C0_ARGS 2 /* Register used as first arg/retval. */
922#define C0_NARGS 6 /* Number of A-regs for args/retvals. */
923
924/* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
925 A-register where the current content of the reg came from (in terms
926 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
927 mean that the orignal content of the register was saved to the stack.
928 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
929 know where SP will end up until the entire prologue has been analyzed. */
930
931#define C0_CONST -1 /* fr_reg value if register contains a constant. */
932#define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
933#define C0_NOSTK -1 /* to_stk value if register has not been stored. */
934
935extern xtensa_isa xtensa_default_isa;
936
937typedef struct xtensa_c0reg
938{
939 int fr_reg; /* original register from which register content
940 is derived, or C0_CONST, or C0_INEXP. */
941 int fr_ofs; /* constant offset from reg, or immediate value. */
942 int to_stk; /* offset from original SP to register (4-byte aligned),
943 or C0_NOSTK if register has not been saved. */
944} xtensa_c0reg_t;
945
946
947/* Frame cache part for Call0 ABI. */
948typedef struct xtensa_call0_frame_cache
949{
950 int c0_frmsz; /* Stack frame size. */
951 int c0_hasfp; /* Current frame uses frame pointer. */
952 int fp_regnum; /* A-register used as FP. */
953 int c0_fp; /* Actual value of frame pointer. */
954 xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */
955} xtensa_call0_frame_cache_t;
956
957typedef struct xtensa_frame_cache
958{
ee967b5f 959 CORE_ADDR base; /* Stack pointer of this frame. */
bdb4c075 960 CORE_ADDR pc; /* PC at the entry point to the function. */
ee967b5f
MG		 961 CORE_ADDR ra; /* The raw return address (without CALLINC). */
962 CORE_ADDR ps; /* The PS register of the previous frame. */
963 CORE_ADDR prev_sp; /* Stack Pointer of the previous frame. */
bdb4c075
MG		 964 int call0; /* It's a call0 framework (else windowed). */
965 union
966 {
967 xtensa_windowed_frame_cache_t wd; /* call0 == false. */
968 xtensa_call0_frame_cache_t c0; /* call0 == true. */
969 };
ca3bf3bd
DJ		 970} xtensa_frame_cache_t;
971
972
973static struct xtensa_frame_cache *
bdb4c075 974xtensa_alloc_frame_cache (int windowed)
ca3bf3bd
DJ		 975{
976 xtensa_frame_cache_t *cache;
977 int i;
978
979 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
980
981 cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t);
982
983 cache->base = 0;
984 cache->pc = 0;
985 cache->ra = 0;
ca3bf3bd 986 cache->ps = 0;
ca3bf3bd 987 cache->prev_sp = 0;
bdb4c075
MG		 988 cache->call0 = !windowed;
989 if (cache->call0)
990 {
991 cache->c0.c0_frmsz = -1;
992 cache->c0.c0_hasfp = 0;
993 cache->c0.fp_regnum = -1;
994 cache->c0.c0_fp = -1;
ca3bf3bd 995
bdb4c075
MG		 996 for (i = 0; i < C0_NREGS; i++)
997 {
998 cache->c0.c0_rt[i].fr_reg = i;
999 cache->c0.c0_rt[i].fr_ofs = 0;
1000 cache->c0.c0_rt[i].to_stk = C0_NOSTK;
1001 }
1002 }
1003 else
1004 {
1005 cache->wd.wb = 0;
ee967b5f 1006 cache->wd.ws = 0;
bdb4c075 1007 cache->wd.callsize = -1;
ca3bf3bd 1008
bdb4c075
MG		 1009 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
1010 cache->wd.aregs[i] = -1;
1011 }
ca3bf3bd
DJ		 1012 return cache;
1013}
1014
1015
1016static CORE_ADDR
1017xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
1018{
1019 return address & ~15;
1020}
1021
1022
1023static CORE_ADDR
1024xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1025{
ff7a4c00 1026 gdb_byte buf[8];
ca3bf3bd
DJ		 1027
1028 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %p)\n", next_frame);
1029
6b50c0b0 1030 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
ca3bf3bd
DJ		 1031
1032 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int)
1033 extract_typed_address (buf, builtin_type_void_func_ptr));
1034
1035 return extract_typed_address (buf, builtin_type_void_func_ptr);
1036}
1037
1038
1039static struct frame_id
5142f611 1040xtensa_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
ca3bf3bd
DJ		 1041{
1042 CORE_ADDR pc, fp;
ca3bf3bd 1043
5142f611 1044 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
ca3bf3bd 1045
5142f611
MG		 1046 pc = get_frame_pc (this_frame);
1047 fp = get_frame_register_unsigned
1048 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
ca3bf3bd
DJ		 1049
1050 /* Make dummy frame ID unique by adding a constant. */
bdb4c075 1051 return frame_id_build (fp + SP_ALIGNMENT, pc);
ca3bf3bd
DJ		 1052}
1053
ee967b5f
MG		 1054/* Returns the best guess about which register is a frame pointer
1055 for the function containing CURRENT_PC. */
1056
1057#define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1058
1059static unsigned int
1060xtensa_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR current_pc)
1061{
1062#define RETURN_FP goto done
1063
1064 unsigned int fp_regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
1065 CORE_ADDR start_addr;
1066 xtensa_isa isa;
1067 xtensa_insnbuf ins, slot;
1068 char ibuf[XTENSA_ISA_BSZ];
1069 CORE_ADDR ia, bt, ba;
1070 xtensa_format ifmt;
1071 int ilen, islots, is;
1072 xtensa_opcode opc;
1073 const char *opcname;
1074
1075 find_pc_partial_function (current_pc, NULL, &start_addr, NULL);
1076 if (start_addr == 0)
1077 return fp_regnum;
1078
1079 if (!xtensa_default_isa)
1080 xtensa_default_isa = xtensa_isa_init (0, 0);
1081 isa = xtensa_default_isa;
1082 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
1083 ins = xtensa_insnbuf_alloc (isa);
1084 slot = xtensa_insnbuf_alloc (isa);
1085 ba = 0;
1086
1087 for (ia = start_addr, bt = ia; ia < current_pc ; ia += ilen)
1088 {
1089 if (ia + xtensa_isa_maxlength (isa) > bt)
1090 {
1091 ba = ia;
1092 bt = (ba + XTENSA_ISA_BSZ) < current_pc
1093 ? ba + XTENSA_ISA_BSZ : current_pc;
1094 read_memory (ba, ibuf, bt - ba);
1095 }
1096
1097 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
1098 ifmt = xtensa_format_decode (isa, ins);
1099 if (ifmt == XTENSA_UNDEFINED)
1100 RETURN_FP;
1101 ilen = xtensa_format_length (isa, ifmt);
1102 if (ilen == XTENSA_UNDEFINED)
1103 RETURN_FP;
1104 islots = xtensa_format_num_slots (isa, ifmt);
1105 if (islots == XTENSA_UNDEFINED)
1106 RETURN_FP;
1107
1108 for (is = 0; is < islots; ++is)
1109 {
1110 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
1111 RETURN_FP;
1112
1113 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
1114 if (opc == XTENSA_UNDEFINED)
1115 RETURN_FP;
1116
1117 opcname = xtensa_opcode_name (isa, opc);
1118
1119 if (strcasecmp (opcname, "mov.n") == 0
1120 || strcasecmp (opcname, "or") == 0)
1121 {
1122 unsigned int register_operand;
1123
1124 /* Possible candidate for setting frame pointer
1125 from A1. This is what we are looking for. */
1126
1127 if (xtensa_operand_get_field (isa, opc, 1, ifmt,
1128 is, slot, &register_operand) != 0)
1129 RETURN_FP;
1130 if (xtensa_operand_decode (isa, opc, 1, &register_operand) != 0)
1131 RETURN_FP;
1132 if (register_operand == 1) /* Mov{.n} FP A1. */
1133 {
1134 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot,
1135 &register_operand) != 0)
1136 RETURN_FP;
1137 if (xtensa_operand_decode (isa, opc, 0,
1138 &register_operand) != 0)
1139 RETURN_FP;
1140
1141 fp_regnum = gdbarch_tdep (gdbarch)->a0_base + register_operand;
1142 RETURN_FP;
1143 }
1144 }
1145
1146 if (
1147 /* We have problems decoding the memory. */
1148 opcname == NULL
1149 || strcasecmp (opcname, "ill") == 0
1150 || strcasecmp (opcname, "ill.n") == 0
1151 /* Hit planted breakpoint. */
1152 || strcasecmp (opcname, "break") == 0
1153 || strcasecmp (opcname, "break.n") == 0
1154 /* Flow control instructions finish prologue. */
1155 || xtensa_opcode_is_branch (isa, opc) > 0
1156 || xtensa_opcode_is_jump (isa, opc) > 0
1157 || xtensa_opcode_is_loop (isa, opc) > 0
1158 || xtensa_opcode_is_call (isa, opc) > 0
1159 || strcasecmp (opcname, "simcall") == 0
1160 || strcasecmp (opcname, "syscall") == 0)
1161 /* Can not continue analysis. */
1162 RETURN_FP;
1163 }
1164 }
1165done:
1166 xtensa_insnbuf_free(isa, slot);
1167 xtensa_insnbuf_free(isa, ins);
1168 return fp_regnum;
1169}
1170
bdb4c075
MG		 1171/* The key values to identify the frame using "cache" are
1172
ee967b5f 1173 cache->base = SP (or best guess about FP) of this frame;
bdb4c075
MG		 1174 cache->pc = entry-PC (entry point of the frame function);
1175 cache->prev_sp = SP of the previous frame.
1176*/
1177
1178static void
5142f611 1179call0_frame_cache (struct frame_info *this_frame,
bdb4c075
MG		 1180 xtensa_frame_cache_t *cache,
1181 CORE_ADDR pc);
ca3bf3bd
DJ		 1182
1183static struct xtensa_frame_cache *
5142f611 1184xtensa_frame_cache (struct frame_info *this_frame, void **this_cache)
ca3bf3bd
DJ		 1185{
1186 xtensa_frame_cache_t *cache;
ca3bf3bd 1187 CORE_ADDR ra, wb, ws, pc, sp, ps;
5142f611 1188 struct gdbarch *gdbarch = get_frame_arch (this_frame);
6b50c0b0 1189 unsigned int ps_regnum = gdbarch_ps_regnum (gdbarch);
ee967b5f 1190 unsigned int fp_regnum;
ca3bf3bd 1191 char op1;
bdb4c075 1192 int windowed;
ca3bf3bd 1193
ca3bf3bd
DJ		 1194 if (*this_cache)
1195 return *this_cache;
1196
bdb4c075
MG		 1197 windowed = windowing_enabled (xtensa_read_register (ps_regnum));
1198
ca3bf3bd 1199 /* Get pristine xtensa-frame. */
bdb4c075 1200 cache = xtensa_alloc_frame_cache (windowed);
ca3bf3bd
DJ		 1201 *this_cache = cache;
1202
5142f611
MG		 1203 pc = get_frame_register_unsigned (this_frame,
1204 gdbarch_pc_regnum (gdbarch));
ca3bf3bd 1205
bdb4c075 1206 if (windowed)
ca3bf3bd 1207 {
bdb4c075 1208 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
5142f611
MG		 1209 wb = get_frame_register_unsigned (this_frame,
1210 gdbarch_tdep (gdbarch)->wb_regnum);
1211 ws = get_frame_register_unsigned (this_frame,
1212 gdbarch_tdep (gdbarch)->ws_regnum);
1213 ps = get_frame_register_unsigned (this_frame, ps_regnum);
ca3bf3bd 1214
bdb4c075 1215 op1 = read_memory_integer (pc, 1);
91d8eb23 1216 if (XTENSA_IS_ENTRY (gdbarch, op1))
ca3bf3bd 1217 {
bdb4c075 1218 int callinc = CALLINC (ps);
5142f611
MG		 1219 ra = get_frame_register_unsigned
1220 (this_frame, gdbarch_tdep (gdbarch)->a0_base + callinc * 4);
bdb4c075
MG		 1221
1222 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1223 cache->wd.callsize = 0;
1224 cache->wd.wb = wb;
1225 cache->wd.ws = ws;
5142f611
MG		 1226 cache->prev_sp = get_frame_register_unsigned
1227 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
ee967b5f
MG		 1228
1229 /* This only can be the outermost frame since we are
1230 just about to execute ENTRY. SP hasn't been set yet.
1231 We can assume any frame size, because it does not
1232 matter, and, let's fake frame base in cache. */
1233 cache->base = cache->prev_sp + 16;
1234
1235 cache->pc = pc;
1236 cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
1237 cache->ps = (ps & ~PS_CALLINC_MASK)
1238 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1239
1240 return cache;
bdb4c075
MG		 1241 }
1242 else
1243 {
ee967b5f 1244 fp_regnum = xtensa_scan_prologue (gdbarch, pc);
5142f611
MG		 1245 ra = get_frame_register_unsigned (this_frame,
1246 gdbarch_tdep (gdbarch)->a0_base);
bdb4c075 1247 cache->wd.callsize = WINSIZE (ra);
304fe255 1248 cache->wd.wb = (wb - cache->wd.callsize / 4)
6b50c0b0 1249 & (gdbarch_tdep (gdbarch)->num_aregs / 4 - 1);
bdb4c075 1250 cache->wd.ws = ws & ~(1 << wb);
ca3bf3bd 1251
5142f611 1252 cache->pc = get_frame_func (this_frame);
ee967b5f
MG		 1253 cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
1254 cache->ps = (ps & ~PS_CALLINC_MASK)
1255 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1256 }
bdb4c075
MG		 1257
1258 if (cache->wd.ws == 0)
ca3bf3bd 1259 {
bdb4c075 1260 int i;
ca3bf3bd 1261
bdb4c075 1262 /* Set A0...A3. */
5142f611
MG		 1263 sp = get_frame_register_unsigned
1264 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1) - 16;
bdb4c075
MG		 1265
1266 for (i = 0; i < 4; i++, sp += 4)
1267 {
1268 cache->wd.aregs[i] = sp;
1269 }
ca3bf3bd 1270
bdb4c075 1271 if (cache->wd.callsize > 4)
ca3bf3bd 1272 {
bdb4c075 1273 /* Set A4...A7/A11. */
ee967b5f
MG		 1274 /* Get the SP of the frame previous to the previous one.
1275 To achieve this, we have to dereference SP twice. */
bdb4c075 1276 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4);
94a0e877 1277 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4);
bdb4c075
MG		 1278 sp -= cache->wd.callsize * 4;
1279
ee967b5f 1280 for ( i = 4; i < cache->wd.callsize; i++, sp += 4)
bdb4c075
MG		 1281 {
1282 cache->wd.aregs[i] = sp;
1283 }
ca3bf3bd
DJ		 1284 }
1285 }
ca3bf3bd 1286
bdb4c075
MG		 1287 if ((cache->prev_sp == 0) && ( ra != 0 ))
1288 /* If RA is equal to 0 this frame is an outermost frame. Leave
1289 cache->prev_sp unchanged marking the boundary of the frame stack. */
ca3bf3bd 1290 {
ee967b5f 1291 if ((cache->wd.ws & (1 << cache->wd.wb)) == 0)
bdb4c075
MG		 1292 {
1293 /* Register window overflow already happened.
1294 We can read caller's SP from the proper spill loction. */
5142f611
MG		 1295 sp = get_frame_register_unsigned
1296 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
ee967b5f 1297 cache->prev_sp = read_memory_integer (sp - 12, 4);
bdb4c075
MG		 1298 }
1299 else
1300 {
1301 /* Read caller's frame SP directly from the previous window. */
ee967b5f 1302 int regnum = arreg_number
91d8eb23 1303 (gdbarch, gdbarch_tdep (gdbarch)->a0_base + 1,
304fe255 1304 cache->wd.wb);
ca3bf3bd 1305
bdb4c075
MG		 1306 cache->prev_sp = xtensa_read_register (regnum);
1307 }
ca3bf3bd
DJ		 1308 }
1309 }
bdb4c075
MG		 1310 else /* Call0 framework. */
1311 {
5142f611 1312 call0_frame_cache (this_frame, cache, pc);
ee967b5f 1313 fp_regnum = cache->c0.fp_regnum;
bdb4c075 1314 }
ca3bf3bd 1315
5142f611 1316 cache->base = get_frame_register_unsigned (this_frame, fp_regnum);
ca3bf3bd 1317
ca3bf3bd
DJ		 1318 return cache;
1319}
1320
ca3bf3bd 1321static void
5142f611 1322xtensa_frame_this_id (struct frame_info *this_frame,
ca3bf3bd
DJ		 1323 void **this_cache,
1324 struct frame_id *this_id)
1325{
1326 struct xtensa_frame_cache *cache =
5142f611 1327 xtensa_frame_cache (this_frame, this_cache);
ca3bf3bd
DJ		 1328
1329 if (cache->prev_sp == 0)
1330 return;
1331
5142f611 1332 (*this_id) = frame_id_build (cache->prev_sp, cache->pc);
bdb4c075 1333}
ca3bf3bd 1334
5142f611
MG		 1335static struct value *
1336xtensa_frame_prev_register (struct frame_info *this_frame,
ca3bf3bd 1337 void **this_cache,
5142f611 1338 int regnum)
ca3bf3bd 1339{
5142f611
MG		 1340 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1341 struct xtensa_frame_cache *cache;
1342 ULONGEST saved_reg = 0;
ca3bf3bd
DJ		 1343 int done = 1;
1344
5142f611
MG		 1345 if (*this_cache == NULL)
1346 *this_cache = xtensa_frame_cache (this_frame, this_cache);
1347 cache = *this_cache;
ca3bf3bd 1348
6b50c0b0 1349 if (regnum ==gdbarch_pc_regnum (gdbarch))
bdb4c075 1350 saved_reg = cache->ra;
6b50c0b0 1351 else if (regnum == gdbarch_tdep (gdbarch)->a0_base + 1)
bdb4c075
MG		 1352 saved_reg = cache->prev_sp;
1353 else if (!cache->call0)
ca3bf3bd 1354 {
6b50c0b0 1355 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum)
ee967b5f 1356 saved_reg = cache->wd.ws;
6b50c0b0 1357 else if (regnum == gdbarch_tdep (gdbarch)->wb_regnum)
bdb4c075 1358 saved_reg = cache->wd.wb;
6b50c0b0 1359 else if (regnum == gdbarch_ps_regnum (gdbarch))
bdb4c075 1360 saved_reg = cache->ps;
ca3bf3bd 1361 else
bdb4c075 1362 done = 0;
ca3bf3bd 1363 }
ca3bf3bd
DJ		 1364 else
1365 done = 0;
1366
1367 if (done)
5142f611 1368 return frame_unwind_got_constant (this_frame, regnum, saved_reg);
ca3bf3bd 1369
bdb4c075 1370 if (!cache->call0) /* Windowed ABI. */
ca3bf3bd 1371 {
ee967b5f
MG		 1372 /* Convert A-register numbers to AR-register numbers,
1373 if we deal with A-register. */
94a0e877 1374 if (regnum >= gdbarch_tdep (gdbarch)->a0_base
6b50c0b0 1375 && regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)
ee967b5f 1376 regnum = arreg_number (gdbarch, regnum, cache->wd.wb);
ca3bf3bd 1377
ee967b5f 1378 /* Check, if we deal with AR-register saved on stack. */
6b50c0b0
UW		 1379 if (regnum >= gdbarch_tdep (gdbarch)->ar_base
1380 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1381 + gdbarch_tdep (gdbarch)->num_aregs))
bdb4c075 1382 {
ee967b5f 1383 int areg = areg_number (gdbarch, regnum, cache->wd.wb);
ca3bf3bd 1384
bdb4c075
MG		 1385 if (areg >= 0
1386 && areg < XTENSA_NUM_SAVED_AREGS
1387 && cache->wd.aregs[areg] != -1)
5142f611
MG		 1388 return frame_unwind_got_memory (this_frame, regnum,
1389 cache->wd.aregs[areg]);
ca3bf3bd
DJ		 1390 }
1391 }
bdb4c075
MG		 1392 else /* Call0 ABI. */
1393 {
6b50c0b0
UW		 1394 int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base
1395 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
304fe255 1396 + C0_NREGS))
6b50c0b0 1397 ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum;
ca3bf3bd 1398
bdb4c075
MG		 1399 if (reg < C0_NREGS)
1400 {
1401 CORE_ADDR spe;
1402 int stkofs;
1403
1404 /* If register was saved in the prologue, retrieve it. */
1405 stkofs = cache->c0.c0_rt[reg].to_stk;
1406 if (stkofs != C0_NOSTK)
1407 {
1408 /* Determine SP on entry based on FP. */
1409 spe = cache->c0.c0_fp
1410 - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
5142f611
MG		 1411
1412 return frame_unwind_got_memory (this_frame, regnum, spe + stkofs);
bdb4c075
MG		 1413 }
1414 }
1415 }
1416
1417 /* All other registers have been either saved to
1418 the stack or are still alive in the processor. */
ca3bf3bd 1419
5142f611 1420 return frame_unwind_got_register (this_frame, regnum, regnum);
ca3bf3bd
DJ		 1421}
1422
1423
1424static const struct frame_unwind
5142f611 1425xtensa_unwind =
ca3bf3bd
DJ		 1426{
1427 NORMAL_FRAME,
1428 xtensa_frame_this_id,
5142f611
MG		 1429 xtensa_frame_prev_register,
1430 NULL,
1431 default_frame_sniffer
ca3bf3bd
DJ		 1432};
1433
ca3bf3bd 1434static CORE_ADDR
5142f611 1435xtensa_frame_base_address (struct frame_info *this_frame, void **this_cache)
ca3bf3bd
DJ		 1436{
1437 struct xtensa_frame_cache *cache =
5142f611 1438 xtensa_frame_cache (this_frame, this_cache);
ca3bf3bd
DJ		 1439
1440 return cache->base;
1441}
1442
1443static const struct frame_base
1444xtensa_frame_base =
1445{
5142f611 1446 &xtensa_unwind,
ca3bf3bd
DJ		 1447 xtensa_frame_base_address,
1448 xtensa_frame_base_address,
1449 xtensa_frame_base_address
1450};
1451
1452
1453static void
1454xtensa_extract_return_value (struct type *type,
1455 struct regcache *regcache,
1456 void *dst)
1457{
6b50c0b0 1458 struct gdbarch *gdbarch = get_regcache_arch (regcache);
ca3bf3bd
DJ		 1459 bfd_byte *valbuf = dst;
1460 int len = TYPE_LENGTH (type);
1461 ULONGEST pc, wb;
1462 int callsize, areg;
1463 int offset = 0;
1464
1465 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1466
1467 gdb_assert(len > 0);
1468
6b50c0b0 1469 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
bdb4c075
MG		 1470 {
1471 /* First, we have to find the caller window in the register file. */
6b50c0b0 1472 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
91d8eb23 1473 callsize = extract_call_winsize (gdbarch, pc);
ca3bf3bd 1474
bdb4c075
MG		 1475 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1476 if (len > (callsize > 8 ? 8 : 16))
1477 internal_error (__FILE__, __LINE__,
1478 _("cannot extract return value of %d bytes long"), len);
ca3bf3bd 1479
bdb4c075
MG		 1480 /* Get the register offset of the return
1481 register (A2) in the caller window. */
304fe255 1482 regcache_raw_read_unsigned
6b50c0b0 1483 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
ee967b5f 1484 areg = arreg_number (gdbarch,
91d8eb23 1485 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
bdb4c075
MG		 1486 }
1487 else
1488 {
1489 /* No windowing hardware - Call0 ABI. */
94a0e877 1490 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
bdb4c075 1491 }
ca3bf3bd
DJ		 1492
1493 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len);
1494
6b50c0b0 1495 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
ca3bf3bd
DJ		 1496 offset = 4 - len;
1497
1498 for (; len > 0; len -= 4, areg++, valbuf += 4)
1499 {
1500 if (len < 4)
1501 regcache_raw_read_part (regcache, areg, offset, len, valbuf);
1502 else
1503 regcache_raw_read (regcache, areg, valbuf);
1504 }
1505}
1506
1507
1508static void
1509xtensa_store_return_value (struct type *type,
1510 struct regcache *regcache,
1511 const void *dst)
1512{
6b50c0b0 1513 struct gdbarch *gdbarch = get_regcache_arch (regcache);
ca3bf3bd
DJ		 1514 const bfd_byte *valbuf = dst;
1515 unsigned int areg;
1516 ULONGEST pc, wb;
1517 int callsize;
1518 int len = TYPE_LENGTH (type);
1519 int offset = 0;
1520
1521 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1522
6b50c0b0 1523 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
bdb4c075 1524 {
6b50c0b0
UW		 1525 regcache_raw_read_unsigned
1526 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1527 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
91d8eb23 1528 callsize = extract_call_winsize (gdbarch, pc);
ca3bf3bd 1529
bdb4c075
MG		 1530 if (len > (callsize > 8 ? 8 : 16))
1531 internal_error (__FILE__, __LINE__,
1532 _("unimplemented for this length: %d"),
1533 TYPE_LENGTH (type));
ee967b5f
MG		 1534 areg = arreg_number (gdbarch,
1535 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
ca3bf3bd 1536
bdb4c075 1537 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
ca3bf3bd 1538 callsize, (int) wb);
bdb4c075
MG		 1539 }
1540 else
1541 {
94a0e877 1542 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
bdb4c075 1543 }
ca3bf3bd 1544
6b50c0b0 1545 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
ca3bf3bd
DJ		 1546 offset = 4 - len;
1547
ca3bf3bd
DJ		 1548 for (; len > 0; len -= 4, areg++, valbuf += 4)
1549 {
1550 if (len < 4)
1551 regcache_raw_write_part (regcache, areg, offset, len, valbuf);
1552 else
1553 regcache_raw_write (regcache, areg, valbuf);
1554 }
1555}
1556
1557
bdb4c075 1558static enum return_value_convention
ca3bf3bd 1559xtensa_return_value (struct gdbarch *gdbarch,
c055b101 1560 struct type *func_type,
ca3bf3bd
DJ		 1561 struct type *valtype,
1562 struct regcache *regcache,
1563 gdb_byte *readbuf,
1564 const gdb_byte *writebuf)
1565{
bdb4c075 1566 /* Structures up to 16 bytes are returned in registers. */
ca3bf3bd
DJ		 1567
1568 int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1569 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1570 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1571 && TYPE_LENGTH (valtype) > 16);
1572
1573 if (struct_return)
1574 return RETURN_VALUE_STRUCT_CONVENTION;
1575
1576 DEBUGTRACE ("xtensa_return_value(...)\n");
1577
1578 if (writebuf != NULL)
1579 {
1580 xtensa_store_return_value (valtype, regcache, writebuf);
1581 }
1582
1583 if (readbuf != NULL)
1584 {
1585 gdb_assert (!struct_return);
1586 xtensa_extract_return_value (valtype, regcache, readbuf);
1587 }
1588 return RETURN_VALUE_REGISTER_CONVENTION;
1589}
1590
1591
1592/* DUMMY FRAME */
1593
1594static CORE_ADDR
1595xtensa_push_dummy_call (struct gdbarch *gdbarch,
1596 struct value *function,
1597 struct regcache *regcache,
1598 CORE_ADDR bp_addr,
1599 int nargs,
1600 struct value **args,
1601 CORE_ADDR sp,
1602 int struct_return,
1603 CORE_ADDR struct_addr)
1604{
1605 int i;
1606 int size, onstack_size;
ff7a4c00 1607 gdb_byte *buf = (gdb_byte *) alloca (16);
ca3bf3bd
DJ		 1608 CORE_ADDR ra, ps;
1609 struct argument_info
1610 {
1611 const bfd_byte *contents;
1612 int length;
1613 int onstack; /* onstack == 0 => in reg */
1614 int align; /* alignment */
1615 union
1616 {
1617 int offset; /* stack offset if on stack */
1618 int regno; /* regno if in register */
1619 } u;
1620 };
1621
1622 struct argument_info *arg_info =
1623 (struct argument_info *) alloca (nargs * sizeof (struct argument_info));
1624
1625 CORE_ADDR osp = sp;
1626
1627 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1628
1629 if (xtensa_debug_level > 3)
1630 {
1631 int i;
1632 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs);
1633 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1634 "struct_addr=0x%x\n",
1635 (int) sp, (int) struct_return, (int) struct_addr);
1636
1637 for (i = 0; i < nargs; i++)
1638 {
1639 struct value *arg = args[i];
1640 struct type *arg_type = check_typedef (value_type (arg));
ec20a626
UW		 1641 fprintf_unfiltered (gdb_stdlog, "%2d: 0x%lx %3d ",
1642 i, (unsigned long) arg, TYPE_LENGTH (arg_type));
ca3bf3bd
DJ		 1643 switch (TYPE_CODE (arg_type))
1644 {
1645 case TYPE_CODE_INT:
1646 fprintf_unfiltered (gdb_stdlog, "int");
1647 break;
1648 case TYPE_CODE_STRUCT:
1649 fprintf_unfiltered (gdb_stdlog, "struct");
1650 break;
1651 default:
1652 fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type));
1653 break;
1654 }
ec20a626
UW		 1655 fprintf_unfiltered (gdb_stdlog, " 0x%lx\n",
1656 (unsigned long) value_contents (arg));
ca3bf3bd
DJ		 1657 }
1658 }
1659
1660 /* First loop: collect information.
1661 Cast into type_long. (This shouldn't happen often for C because
1662 GDB already does this earlier.) It's possible that GDB could
1663 do it all the time but it's harmless to leave this code here. */
1664
1665 size = 0;
1666 onstack_size = 0;
1667 i = 0;
1668
1669 if (struct_return)
1670 size = REGISTER_SIZE;
1671
1672 for (i = 0; i < nargs; i++)
1673 {
1674 struct argument_info *info = &arg_info[i];
1675 struct value *arg = args[i];
1676 struct type *arg_type = check_typedef (value_type (arg));
1677
1678 switch (TYPE_CODE (arg_type))
1679 {
1680 case TYPE_CODE_INT:
1681 case TYPE_CODE_BOOL:
1682 case TYPE_CODE_CHAR:
1683 case TYPE_CODE_RANGE:
1684 case TYPE_CODE_ENUM:
1685
1686 /* Cast argument to long if necessary as the mask does it too. */
1687 if (TYPE_LENGTH (arg_type) < TYPE_LENGTH (builtin_type_long))
1688 {
1689 arg_type = builtin_type_long;
1690 arg = value_cast (arg_type, arg);
1691 }
bdb4c075
MG		 1692 /* Aligment is equal to the type length for the basic types. */
1693 info->align = TYPE_LENGTH (arg_type);
ca3bf3bd
DJ		 1694 break;
1695
1696 case TYPE_CODE_FLT:
1697
1698 /* Align doubles correctly. */
1699 if (TYPE_LENGTH (arg_type) == TYPE_LENGTH (builtin_type_double))
1700 info->align = TYPE_LENGTH (builtin_type_double);
1701 else
1702 info->align = TYPE_LENGTH (builtin_type_long);
1703 break;
1704
1705 case TYPE_CODE_STRUCT:
1706 default:
1707 info->align = TYPE_LENGTH (builtin_type_long);
1708 break;
1709 }
1710 info->length = TYPE_LENGTH (arg_type);
1711 info->contents = value_contents (arg);
1712
1713 /* Align size and onstack_size. */
1714 size = (size + info->align - 1) & ~(info->align - 1);
1715 onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1);
1716
91d8eb23 1717 if (size + info->length > REGISTER_SIZE * ARG_NOF (gdbarch))
ca3bf3bd
DJ		 1718 {
1719 info->onstack = 1;
1720 info->u.offset = onstack_size;
1721 onstack_size += info->length;
1722 }
1723 else
1724 {
1725 info->onstack = 0;
91d8eb23 1726 info->u.regno = ARG_1ST (gdbarch) + size / REGISTER_SIZE;
ca3bf3bd
DJ		 1727 }
1728 size += info->length;
1729 }
1730
1731 /* Adjust the stack pointer and align it. */
1732 sp = align_down (sp - onstack_size, SP_ALIGNMENT);
1733
bdb4c075 1734 /* Simulate MOVSP, if Windowed ABI. */
6b50c0b0 1735 if ((gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
304fe255 1736 && (sp != osp))
ca3bf3bd
DJ		 1737 {
1738 read_memory (osp - 16, buf, 16);
1739 write_memory (sp - 16, buf, 16);
1740 }
1741
1742 /* Second Loop: Load arguments. */
1743
1744 if (struct_return)
1745 {
1746 store_unsigned_integer (buf, REGISTER_SIZE, struct_addr);
91d8eb23 1747 regcache_cooked_write (regcache, ARG_1ST (gdbarch), buf);
ca3bf3bd
DJ		 1748 }
1749
1750 for (i = 0; i < nargs; i++)
1751 {
1752 struct argument_info *info = &arg_info[i];
1753
1754 if (info->onstack)
1755 {
1756 int n = info->length;
1757 CORE_ADDR offset = sp + info->u.offset;
1758
1759 /* Odd-sized structs are aligned to the lower side of a memory
1760 word in big-endian mode and require a shift. This only
1761 applies for structures smaller than one word. */
1762
4c6b5505 1763 if (n < REGISTER_SIZE
6b50c0b0 1764 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
ca3bf3bd
DJ		 1765 offset += (REGISTER_SIZE - n);
1766
1767 write_memory (offset, info->contents, info->length);
1768
1769 }
1770 else
1771 {
1772 int n = info->length;
1773 const bfd_byte *cp = info->contents;
1774 int r = info->u.regno;
1775
1776 /* Odd-sized structs are aligned to the lower side of registers in
1777 big-endian mode and require a shift. The odd-sized leftover will
1778 be at the end. Note that this is only true for structures smaller
1779 than REGISTER_SIZE; for larger odd-sized structures the excess
1780 will be left-aligned in the register on both endiannesses. */
1781
4c6b5505 1782 if (n < REGISTER_SIZE
6b50c0b0 1783 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
ca3bf3bd
DJ		 1784 {
1785 ULONGEST v = extract_unsigned_integer (cp, REGISTER_SIZE);
1786 v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT);
1787
1788 store_unsigned_integer (buf, REGISTER_SIZE, v);
1789 regcache_cooked_write (regcache, r, buf);
1790
1791 cp += REGISTER_SIZE;
1792 n -= REGISTER_SIZE;
1793 r++;
1794 }
1795 else
1796 while (n > 0)
1797 {
ca3bf3bd
DJ		 1798 regcache_cooked_write (regcache, r, cp);
1799
ca3bf3bd
DJ		 1800 cp += REGISTER_SIZE;
1801 n -= REGISTER_SIZE;
1802 r++;
1803 }
1804 }
1805 }
1806
ca3bf3bd 1807 /* Set the return address of dummy frame to the dummy address.
bdb4c075 1808 The return address for the current function (in A0) is
ca3bf3bd
DJ		 1809 saved in the dummy frame, so we can savely overwrite A0 here. */
1810
6b50c0b0 1811 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
bdb4c075
MG		 1812 {
1813 ra = (bp_addr & 0x3fffffff) | 0x40000000;
6b50c0b0 1814 regcache_raw_read (regcache, gdbarch_ps_regnum (gdbarch), buf);
bdb4c075 1815 ps = extract_unsigned_integer (buf, 4) & ~0x00030000;
304fe255 1816 regcache_cooked_write_unsigned
6b50c0b0 1817 (regcache, gdbarch_tdep (gdbarch)->a0_base + 4, ra);
bdb4c075 1818 regcache_cooked_write_unsigned (regcache,
6b50c0b0 1819 gdbarch_ps_regnum (gdbarch),
bdb4c075 1820 ps | 0x00010000);
94a0e877
MG		 1821
1822 /* All the registers have been saved. After executing
1823 dummy call, they all will be restored. So it's safe
1824 to modify WINDOWSTART register to make it look like there
1825 is only one register window corresponding to WINDOWEBASE. */
1826
1827 regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
1828 regcache_cooked_write_unsigned (regcache,
1829 gdbarch_tdep (gdbarch)->ws_regnum,
1830 1 << extract_unsigned_integer (buf, 4));
bdb4c075
MG		 1831 }
1832 else
1833 {
1834 /* Simulate CALL0: write RA into A0 register. */
304fe255 1835 regcache_cooked_write_unsigned
94a0e877 1836 (regcache, gdbarch_tdep (gdbarch)->a0_base, bp_addr);
bdb4c075 1837 }
ca3bf3bd
DJ		 1838
1839 /* Set new stack pointer and return it. */
304fe255 1840 regcache_cooked_write_unsigned (regcache,
6b50c0b0 1841 gdbarch_tdep (gdbarch)->a0_base + 1, sp);
ca3bf3bd
DJ		 1842 /* Make dummy frame ID unique by adding a constant. */
1843 return sp + SP_ALIGNMENT;
1844}
1845
1846
1847/* Return a breakpoint for the current location of PC. We always use
1848 the density version if we have density instructions (regardless of the
1849 current instruction at PC), and use regular instructions otherwise. */
1850
1851#define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1852#define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1853#define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1854#define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1855
bdb4c075 1856static const unsigned char *
67d57894
MD		 1857xtensa_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
1858 int *lenptr)
ca3bf3bd 1859{
ff7a4c00
MG		 1860 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
1861 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
1862 static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT;
1863 static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT;
ca3bf3bd
DJ		 1864
1865 DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr);
1866
67d57894 1867 if (gdbarch_tdep (gdbarch)->isa_use_density_instructions)
ca3bf3bd 1868 {
67d57894 1869 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
ca3bf3bd
DJ		 1870 {
1871 *lenptr = sizeof (density_big_breakpoint);
1872 return density_big_breakpoint;
1873 }
1874 else
1875 {
1876 *lenptr = sizeof (density_little_breakpoint);
1877 return density_little_breakpoint;
1878 }
1879 }
1880 else
1881 {
67d57894 1882 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
ca3bf3bd
DJ		 1883 {
1884 *lenptr = sizeof (big_breakpoint);
1885 return big_breakpoint;
1886 }
1887 else
1888 {
1889 *lenptr = sizeof (little_breakpoint);
1890 return little_breakpoint;
1891 }
1892 }
1893}
1894
bdb4c075
MG		 1895/* Call0 ABI support routines. */
1896
1897/* Call0 opcode class. Opcodes are preclassified according to what they
1898 mean for Call0 prologue analysis, and their number of significant operands.
1899 The purpose of this is to simplify prologue analysis by separating
1900 instruction decoding (libisa) from the semantics of prologue analysis. */
1901
1902typedef enum {
1903 c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */
1904 c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */
1905 c0opc_flow, /* Flow control insn. */
1906 c0opc_entry, /* ENTRY indicates non-Call0 prologue. */
1907 c0opc_break, /* Debugger software breakpoints. */
1908 c0opc_add, /* Adding two registers. */
1909 c0opc_addi, /* Adding a register and an immediate. */
1910 c0opc_sub, /* Subtracting a register from a register. */
1911 c0opc_mov, /* Moving a register to a register. */
1912 c0opc_movi, /* Moving an immediate to a register. */
1913 c0opc_l32r, /* Loading a literal. */
1914 c0opc_s32i, /* Storing word at fixed offset from a base register. */
1915 c0opc_NrOf /* Number of opcode classifications. */
1916} xtensa_insn_kind;
1917
1918
1919/* Classify an opcode based on what it means for Call0 prologue analysis. */
1920
1921static xtensa_insn_kind
1922call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc)
1923{
1924 const char *opcname;
1925 xtensa_insn_kind opclass = c0opc_uninteresting;
1926
1927 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc);
1928
1929 /* Get opcode name and handle special classifications. */
1930
1931 opcname = xtensa_opcode_name (isa, opc);
1932
1933 if (opcname == NULL
1934 || strcasecmp (opcname, "ill") == 0
1935 || strcasecmp (opcname, "ill.n") == 0)
1936 opclass = c0opc_illegal;
1937 else if (strcasecmp (opcname, "break") == 0
1938 || strcasecmp (opcname, "break.n") == 0)
1939 opclass = c0opc_break;
1940 else if (strcasecmp (opcname, "entry") == 0)
1941 opclass = c0opc_entry;
1942 else if (xtensa_opcode_is_branch (isa, opc) > 0
1943 || xtensa_opcode_is_jump (isa, opc) > 0
1944 || xtensa_opcode_is_loop (isa, opc) > 0
1945 || xtensa_opcode_is_call (isa, opc) > 0
1946 || strcasecmp (opcname, "simcall") == 0
1947 || strcasecmp (opcname, "syscall") == 0)
1948 opclass = c0opc_flow;
1949
1950 /* Also, classify specific opcodes that need to be tracked. */
1951 else if (strcasecmp (opcname, "add") == 0
1952 || strcasecmp (opcname, "add.n") == 0)
1953 opclass = c0opc_add;
1954 else if (strcasecmp (opcname, "addi") == 0
1955 || strcasecmp (opcname, "addi.n") == 0
1956 || strcasecmp (opcname, "addmi") == 0)
1957 opclass = c0opc_addi;
1958 else if (strcasecmp (opcname, "sub") == 0)
1959 opclass = c0opc_sub;
1960 else if (strcasecmp (opcname, "mov.n") == 0
1961 || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */
1962 opclass = c0opc_mov;
1963 else if (strcasecmp (opcname, "movi") == 0
1964 || strcasecmp (opcname, "movi.n") == 0)
1965 opclass = c0opc_movi;
1966 else if (strcasecmp (opcname, "l32r") == 0)
1967 opclass = c0opc_l32r;
1968 else if (strcasecmp (opcname, "s32i") == 0
1969 || strcasecmp (opcname, "s32i.n") == 0)
1970 opclass = c0opc_s32i;
1971
1972 return opclass;
1973}
1974
1975/* Tracks register movement/mutation for a given operation, which may
1976 be within a bundle. Updates the destination register tracking info
1977 accordingly. The pc is needed only for pc-relative load instructions
1978 (eg. l32r). The SP register number is needed to identify stores to
1979 the stack frame. */
1980
1981static void
1982call0_track_op (xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
1983 xtensa_insn_kind opclass, int nods, unsigned odv[],
1984 CORE_ADDR pc, int spreg)
1985{
1986 unsigned litbase, litaddr, litval;
1987
1988 switch (opclass)
1989 {
1990 case c0opc_addi:
1991 /* 3 operands: dst, src, imm. */
1992 gdb_assert (nods == 3);
1993 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
1994 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2];
1995 break;
1996 case c0opc_add:
1997 /* 3 operands: dst, src1, src2. */
1998 gdb_assert (nods == 3);
1999 if (src[odv[1]].fr_reg == C0_CONST)
2000 {
2001 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
2002 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs;
2003 }
2004 else if (src[odv[2]].fr_reg == C0_CONST)
2005 {
2006 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2007 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs;
2008 }
2009 else dst[odv[0]].fr_reg = C0_INEXP;
2010 break;
2011 case c0opc_sub:
2012 /* 3 operands: dst, src1, src2. */
2013 gdb_assert (nods == 3);
2014 if (src[odv[2]].fr_reg == C0_CONST)
2015 {
2016 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2017 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs;
2018 }
2019 else dst[odv[0]].fr_reg = C0_INEXP;
2020 break;
2021 case c0opc_mov:
2022 /* 2 operands: dst, src [, src]. */
2023 gdb_assert (nods == 2);
2024 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2025 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs;
2026 break;
2027 case c0opc_movi:
2028 /* 2 operands: dst, imm. */
2029 gdb_assert (nods == 2);
2030 dst[odv[0]].fr_reg = C0_CONST;
2031 dst[odv[0]].fr_ofs = odv[1];
2032 break;
2033 case c0opc_l32r:
2034 /* 2 operands: dst, literal offset. */
2035 gdb_assert (nods == 2);
2036 /* litbase = xtensa_get_litbase (pc); can be also used. */
304fe255
UW		 2037 litbase = (gdbarch_tdep (current_gdbarch)->litbase_regnum == -1)
2038 ? 0 : xtensa_read_register
2039 (gdbarch_tdep (current_gdbarch)->litbase_regnum);
bdb4c075
MG		 2040 litaddr = litbase & 1
2041 ? (litbase & ~1) + (signed)odv[1]
2042 : (pc + 3 + (signed)odv[1]) & ~3;
2043 litval = read_memory_integer(litaddr, 4);
2044 dst[odv[0]].fr_reg = C0_CONST;
2045 dst[odv[0]].fr_ofs = litval;
2046 break;
2047 case c0opc_s32i:
2048 /* 3 operands: value, base, offset. */
2049 gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS);
2050 if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */
2051 && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */
2052 && src[odv[0]].fr_reg >= 0 /* Value is from a register. */
2053 && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */
2054 && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */
2055 {
2056 /* ISA encoding guarantees alignment. But, check it anyway. */
2057 gdb_assert ((odv[2] & 3) == 0);
2058 dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2];
2059 }
2060 break;
2061 default:
2062 gdb_assert (0);
2063 }
2064}
2065
2066/* Analyze prologue of the function at start address to determine if it uses
2067 the Call0 ABI, and if so track register moves and linear modifications
2068 in the prologue up to the PC or just beyond the prologue, whichever is first.
2069 An 'entry' instruction indicates non-Call0 ABI and the end of the prologue.
2070 The prologue may overlap non-prologue instructions but is guaranteed to end
2071 by the first flow-control instruction (jump, branch, call or return).
2072 Since an optimized function may move information around and change the
2073 stack frame arbitrarily during the prologue, the information is guaranteed
2074 valid only at the point in the function indicated by the PC.
2075 May be used to skip the prologue or identify the ABI, w/o tracking.
2076
2077 Returns: Address of first instruction after prologue, or PC (whichever
2078 is first), or 0, if decoding failed (in libisa).
2079 Input args:
2080 start Start address of function/prologue.
2081 pc Program counter to stop at. Use 0 to continue to end of prologue.
2082 If 0, avoids infinite run-on in corrupt code memory by bounding
2083 the scan to the end of the function if that can be determined.
2084 nregs Number of general registers to track (size of rt[] array).
2085 InOut args:
2086 rt[] Array[nregs] of xtensa_c0reg structures for register tracking info.
2087 If NULL, registers are not tracked.
2088 Output args:
2089 call0 If != NULL, *call0 is set non-zero if Call0 ABI used, else 0
2090 (more accurately, non-zero until 'entry' insn is encountered).
2091
2092 Note that these may produce useful results even if decoding fails
2093 because they begin with default assumptions that analysis may change. */
2094
2095static CORE_ADDR
2096call0_analyze_prologue (CORE_ADDR start, CORE_ADDR pc,
2097 int nregs, xtensa_c0reg_t rt[], int *call0)
2098{
2099 CORE_ADDR ia; /* Current insn address in prologue. */
2100 CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
2101 CORE_ADDR bt; /* Current address at top+1 of insn buffer. */
2102 #define BSZ 32 /* Instruction buffer size. */
2103 char ibuf[BSZ]; /* Instruction buffer for decoding prologue. */
2104 xtensa_isa isa; /* libisa ISA handle. */
2105 xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */
2106 xtensa_format ifmt; /* libisa instruction format. */
2107 int ilen, islots, is; /* Instruction length, nbr slots, current slot. */
2108 xtensa_opcode opc; /* Opcode in current slot. */
2109 xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */
2110 int nods; /* Opcode number of operands. */
2111 unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */
2112 xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */
2113 int j; /* General loop counter. */
2114 int fail = 0; /* Set non-zero and exit, if decoding fails. */
2115 CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */
2116 CORE_ADDR end_pc; /* The PC for the lust function insn. */
2117
2118 struct symtab_and_line prologue_sal;
2119
2120 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2121 (int)start, (int)pc);
2122
2123 /* Try to limit the scan to the end of the function if a non-zero pc
2124 arg was not supplied to avoid probing beyond the end of valid memory.
2125 If memory is full of garbage that classifies as c0opc_uninteresting.
2126 If this fails (eg. if no symbols) pc ends up 0 as it was.
2127 Intialize the Call0 frame and register tracking info.
2128 Assume it's Call0 until an 'entry' instruction is encountered.
2129 Assume we may be in the prologue until we hit a flow control instr. */
2130
2131 rtmp = NULL;
2132 body_pc = INT_MAX;
2133 end_pc = 0;
2134
2135 /* Find out, if we have an information about the prologue from DWARF. */
2136 prologue_sal = find_pc_line (start, 0);
2137 if (prologue_sal.line != 0) /* Found debug info. */
2138 body_pc = prologue_sal.end;
2139
2140 /* If we are going to analyze the prologue in general without knowing about
2141 the current PC, make the best assumtion for the end of the prologue. */
2142 if (pc == 0)
2143 {
2144 find_pc_partial_function (start, 0, NULL, &end_pc);
2145 body_pc = min (end_pc, body_pc);
2146 }
2147 else
2148 body_pc = min (pc, body_pc);
2149
2150 if (call0 != NULL)
2151 *call0 = 1;
2152
2153 if (rt != NULL)
2154 {
2155 rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t));
2156 /* rt is already initialized in xtensa_alloc_frame_cache(). */
2157 }
2158 else nregs = 0;
2159
94a0e877
MG		 2160 if (!xtensa_default_isa)
2161 xtensa_default_isa = xtensa_isa_init (0, 0);
bdb4c075
MG		 2162 isa = xtensa_default_isa;
2163 gdb_assert (BSZ >= xtensa_isa_maxlength (isa));
2164 ins = xtensa_insnbuf_alloc (isa);
2165 slot = xtensa_insnbuf_alloc (isa);
2166
2167 for (ia = start, bt = ia; ia < body_pc ; ia += ilen)
2168 {
2169 /* (Re)fill instruction buffer from memory if necessary, but do not
2170 read memory beyond PC to be sure we stay within text section
2171 (this protection only works if a non-zero pc is supplied). */
2172
2173 if (ia + xtensa_isa_maxlength (isa) > bt)
2174 {
2175 ba = ia;
2176 bt = (ba + BSZ) < body_pc ? ba + BSZ : body_pc;
2177 read_memory (ba, ibuf, bt - ba);
2178 }
2179
2180 /* Decode format information. */
2181
2182 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2183 ifmt = xtensa_format_decode (isa, ins);
2184 if (ifmt == XTENSA_UNDEFINED)
2185 {
2186 fail = 1;
2187 goto done;
2188 }
2189 ilen = xtensa_format_length (isa, ifmt);
2190 if (ilen == XTENSA_UNDEFINED)
2191 {
2192 fail = 1;
2193 goto done;
2194 }
2195 islots = xtensa_format_num_slots (isa, ifmt);
2196 if (islots == XTENSA_UNDEFINED)
2197 {
2198 fail = 1;
2199 goto done;
2200 }
2201
2202 /* Analyze a bundle or a single instruction, using a snapshot of
2203 the register tracking info as input for the entire bundle so that
2204 register changes do not take effect within this bundle. */
ca3bf3bd 2205
bdb4c075
MG		 2206 for (j = 0; j < nregs; ++j)
2207 rtmp[j] = rt[j];
2208
2209 for (is = 0; is < islots; ++is)
2210 {
2211 /* Decode a slot and classify the opcode. */
2212
2213 fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot);
2214 if (fail)
2215 goto done;
2216
2217 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2218 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2219 (unsigned)ia, opc);
2220 if (opc == XTENSA_UNDEFINED)
2221 opclass = c0opc_illegal;
2222 else
2223 opclass = call0_classify_opcode (isa, opc);
2224
2225 /* Decide whether to track this opcode, ignore it, or bail out. */
2226
2227 switch (opclass)
2228 {
2229 case c0opc_illegal:
2230 case c0opc_break:
2231 fail = 1;
2232 goto done;
2233
2234 case c0opc_uninteresting:
2235 continue;
2236
2237 case c0opc_flow:
2238 goto done;
2239
2240 case c0opc_entry:
2241 if (call0 != NULL)
2242 *call0 = 0;
2243 ia += ilen; /* Skip over 'entry' insn. */
2244 goto done;
2245
2246 default:
2247 if (call0 != NULL)
2248 *call0 = 1;
2249 }
2250
2251 /* Only expected opcodes should get this far. */
2252 if (rt == NULL)
2253 continue;
2254
2255 /* Extract and decode the operands. */
2256 nods = xtensa_opcode_num_operands (isa, opc);
2257 if (nods == XTENSA_UNDEFINED)
2258 {
2259 fail = 1;
2260 goto done;
2261 }
2262
2263 for (j = 0; j < nods && j < C0_MAXOPDS; ++j)
2264 {
2265 fail = xtensa_operand_get_field (isa, opc, j, ifmt,
2266 is, slot, &odv[j]);
2267 if (fail)
2268 goto done;
2269
2270 fail = xtensa_operand_decode (isa, opc, j, &odv[j]);
2271 if (fail)
2272 goto done;
2273 }
2274
2275 /* Check operands to verify use of 'mov' assembler macro. */
2276 if (opclass == c0opc_mov && nods == 3)
2277 {
2278 if (odv[2] == odv[1])
2279 nods = 2;
2280 else
2281 {
2282 opclass = c0opc_uninteresting;
2283 continue;
2284 }
2285 }
2286
2287 /* Track register movement and modification for this operation. */
2288 call0_track_op (rt, rtmp, opclass, nods, odv, ia, 1);
2289 }
2290 }
2291done:
2292 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2293 (unsigned)ia, fail ? "failed" : "succeeded");
2294 xtensa_insnbuf_free(isa, slot);
2295 xtensa_insnbuf_free(isa, ins);
2296 return fail ? 0 : ia;
2297}
2298
5142f611 2299/* Initialize frame cache for the current frame in CALL0 ABI. */
bdb4c075
MG		 2300
2301static void
5142f611 2302call0_frame_cache (struct frame_info *this_frame,
bdb4c075
MG		 2303 xtensa_frame_cache_t *cache, CORE_ADDR pc)
2304{
5142f611 2305 struct gdbarch *gdbarch = get_frame_arch (this_frame);
bdb4c075
MG		 2306 CORE_ADDR start_pc; /* The beginning of the function. */
2307 CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */
2308 CORE_ADDR sp, fp, ra;
2309 int fp_regnum, c0_hasfp, c0_frmsz, prev_sp, to_stk;
2310
2311 /* Find the beginning of the prologue of the function containing the PC
2312 and analyze it up to the PC or the end of the prologue. */
2313
2314 if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
2315 {
2316 body_pc = call0_analyze_prologue (start_pc, pc, C0_NREGS,
2317 &cache->c0.c0_rt[0],
2318 &cache->call0);
2319 }
2320
5142f611
MG		 2321 sp = get_frame_register_unsigned
2322 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
bdb4c075
MG		 2323 fp = sp; /* Assume FP == SP until proven otherwise. */
2324
2325 /* Get the frame information and FP (if used) at the current PC.
2326 If PC is in the prologue, the prologue analysis is more reliable
2327 than DWARF info. We don't not know for sure if PC is in the prologue,
2328 but we know no calls have yet taken place, so we can almost
2329 certainly rely on the prologue analysis. */
2330
2331 if (body_pc <= pc)
2332 {
2333 /* Prologue analysis was successful up to the PC.
2334 It includes the cases when PC == START_PC. */
2335 c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP;
2336 /* c0_hasfp == true means there is a frame pointer because
2337 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2338 was derived from SP. Otherwise, it would be C0_FP. */
2339 fp_regnum = c0_hasfp ? C0_FP : C0_SP;
2340 c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs;
6b50c0b0 2341 fp_regnum += gdbarch_tdep (gdbarch)->a0_base;
bdb4c075
MG		 2342 }
2343 else /* No data from the prologue analysis. */
2344 {
2345 c0_hasfp = 0;
6b50c0b0 2346 fp_regnum = gdbarch_tdep (gdbarch)->a0_base + C0_SP;
bdb4c075
MG		 2347 c0_frmsz = 0;
2348 start_pc = pc;
2349 }
2350
2351 prev_sp = fp + c0_frmsz;
2352
2353 /* Frame size from debug info or prologue tracking does not account for
2354 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2355 if (c0_hasfp)
2356 {
5142f611 2357 fp = get_frame_register_unsigned (this_frame, fp_regnum);
bdb4c075
MG		 2358
2359 /* Recalculate previous SP. */
2360 prev_sp = fp + c0_frmsz;
2361 /* Update the stack frame size. */
2362 c0_frmsz += fp - sp;
2363 }
2364
2365 /* Get the return address (RA) from the stack if saved,
2366 or try to get it from a register. */
2367
2368 to_stk = cache->c0.c0_rt[C0_RA].to_stk;
2369 if (to_stk != C0_NOSTK)
2370 ra = (CORE_ADDR)
2371 read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk, 4);
2372
2373 else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST
2374 && cache->c0.c0_rt[C0_RA].fr_ofs == 0)
2375 {
2376 /* Special case for terminating backtrace at a function that wants to
2377 be seen as the outermost. Such a function will clear it's RA (A0)
2378 register to 0 in the prologue instead of saving its original value. */
2379 ra = 0;
2380 }
2381 else
2382 {
2383 /* RA was copied to another register or (before any function call) may
2384 still be in the original RA register. This is not always reliable:
2385 even in a leaf function, register tracking stops after prologue, and
2386 even in prologue, non-prologue instructions (not tracked) may overwrite
2387 RA or any register it was copied to. If likely in prologue or before
2388 any call, use retracking info and hope for the best (compiler should
2389 have saved RA in stack if not in a leaf function). If not in prologue,
2390 too bad. */
2391
2392 int i;
2393 for (i = 0;
2394 (i < C0_NREGS) &&
2395 (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA);
2396 ++i);
2397 if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA)
2398 i = C0_RA;
5142f611 2399 if (i < C0_NREGS)
bdb4c075 2400 {
5142f611
MG		 2401 ra = get_frame_register_unsigned
2402 (this_frame,
2403 gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_rt[i].fr_reg);
bdb4c075
MG		 2404 }
2405 else ra = 0;
2406 }
2407
2408 cache->pc = start_pc;
2409 cache->ra = ra;
2410 /* RA == 0 marks the outermost frame. Do not go past it. */
2411 cache->prev_sp = (ra != 0) ? prev_sp : 0;
2412 cache->c0.fp_regnum = fp_regnum;
2413 cache->c0.c0_frmsz = c0_frmsz;
2414 cache->c0.c0_hasfp = c0_hasfp;
2415 cache->c0.c0_fp = fp;
2416}
2417
2418
2419/* Skip function prologue.
2420
2421 Return the pc of the first instruction after prologue. GDB calls this to
2422 find the address of the first line of the function or (if there is no line
2423 number information) to skip the prologue for planting breakpoints on
2424 function entries. Use debug info (if present) or prologue analysis to skip
2425 the prologue to achieve reliable debugging behavior. For windowed ABI,
2426 only the 'entry' instruction is skipped. It is not strictly necessary to
2427 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2428 backtrace at any point in the prologue, however certain potential hazards
2429 are avoided and a more "normal" debugging experience is ensured by
2430 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2431 For example, if we don't skip the prologue:
2432 - Some args may not yet have been saved to the stack where the debug
2433 info expects to find them (true anyway when only 'entry' is skipped);
2434 - Software breakpoints ('break' instrs) may not have been unplanted
2435 when the prologue analysis is done on initializing the frame cache,
2436 and breaks in the prologue will throw off the analysis.
ca3bf3bd
DJ		 2437
2438 If we have debug info ( line-number info, in particular ) we simply skip
2439 the code associated with the first function line effectively skipping
bdb4c075 2440 the prologue code. It works even in cases like
ca3bf3bd
DJ		 2441
2442 int main()
2443 { int local_var = 1;
2444 ....
2445 }
2446
2447 because, for this source code, both Xtensa compilers will generate two
2448 separate entries ( with the same line number ) in dwarf line-number
2449 section to make sure there is a boundary between the prologue code and
2450 the rest of the function.
2451
bdb4c075
MG		 2452 If there is no debug info, we need to analyze the code. */
2453
2454/* #define DONT_SKIP_PROLOGUE */
ca3bf3bd
DJ		 2455
2456CORE_ADDR
6093d2eb 2457xtensa_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
ca3bf3bd 2458{
bdb4c075
MG		 2459 struct symtab_and_line prologue_sal;
2460 CORE_ADDR body_pc;
2461
ca3bf3bd
DJ		 2462 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc);
2463
bdb4c075
MG		 2464#if DONT_SKIP_PROLOGUE
2465 return start_pc;
2466#endif
2467
2468 /* Try to find first body line from debug info. */
2469
2470 prologue_sal = find_pc_line (start_pc, 0);
2471 if (prologue_sal.line != 0) /* Found debug info. */
ca3bf3bd 2472 {
bdb4c075
MG		 2473 /* In Call0, it is possible to have a function with only one instruction
2474 ('ret') resulting from a 1-line optimized function that does nothing.
2475 In that case, prologue_sal.end may actually point to the start of the
2476 next function in the text section, causing a breakpoint to be set at
2477 the wrong place. Check if the end address is in a different function,
2478 and if so return the start PC. We know we have symbol info. */
ca3bf3bd 2479
bdb4c075
MG		 2480 CORE_ADDR end_func;
2481
2482 find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL);
2483 if (end_func != start_pc)
ca3bf3bd
DJ		 2484 return start_pc;
2485
bdb4c075 2486 return prologue_sal.end;
ca3bf3bd 2487 }
ca3bf3bd 2488
bdb4c075
MG		 2489 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
2490 body_pc = call0_analyze_prologue(start_pc, 0, 0, NULL, NULL);
2491 return body_pc != 0 ? body_pc : start_pc;
2492}
ca3bf3bd
DJ		 2493
2494/* Verify the current configuration. */
ca3bf3bd
DJ		 2495static void
2496xtensa_verify_config (struct gdbarch *gdbarch)
2497{
2498 struct ui_file *log;
2499 struct cleanup *cleanups;
2500 struct gdbarch_tdep *tdep;
2501 long dummy;
2502 char *buf;
2503
2504 tdep = gdbarch_tdep (gdbarch);
2505 log = mem_fileopen ();
2506 cleanups = make_cleanup_ui_file_delete (log);
2507
2508 /* Verify that we got a reasonable number of AREGS. */
2509 if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs)
bdb4c075
MG		 2510 fprintf_unfiltered (log, _("\
2511\n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
2512 tdep->num_aregs);
ca3bf3bd
DJ		 2513
2514 /* Verify that certain registers exist. */
bdb4c075 2515
ca3bf3bd 2516 if (tdep->pc_regnum == -1)
bdb4c075
MG		 2517 fprintf_unfiltered (log, _("\n\tpc_regnum: No PC register"));
2518 if (tdep->isa_use_exceptions && tdep->ps_regnum == -1)
2519 fprintf_unfiltered (log, _("\n\tps_regnum: No PS register"));
2520
2521 if (tdep->isa_use_windowed_registers)
2522 {
2523 if (tdep->wb_regnum == -1)
2524 fprintf_unfiltered (log, _("\n\twb_regnum: No WB register"));
2525 if (tdep->ws_regnum == -1)
2526 fprintf_unfiltered (log, _("\n\tws_regnum: No WS register"));
2527 if (tdep->ar_base == -1)
2528 fprintf_unfiltered (log, _("\n\tar_base: No AR registers"));
2529 }
2530
ca3bf3bd 2531 if (tdep->a0_base == -1)
bdb4c075 2532 fprintf_unfiltered (log, _("\n\ta0_base: No Ax registers"));
ca3bf3bd
DJ		 2533
2534 buf = ui_file_xstrdup (log, &dummy);
2535 make_cleanup (xfree, buf);
2536 if (strlen (buf) > 0)
2537 internal_error (__FILE__, __LINE__,
2538 _("the following are invalid: %s"), buf);
2539 do_cleanups (cleanups);
2540}
2541
94a0e877
MG		 2542
2543/* Derive specific register numbers from the array of registers. */
2544
2545void
2546xtensa_derive_tdep (struct gdbarch_tdep *tdep)
2547{
2548 xtensa_register_t* rmap;
2549 int n, max_size = 4;
2550
2551 tdep->num_regs = 0;
2552 tdep->num_nopriv_regs = 0;
2553
2554/* Special registers 0..255 (core). */
2555#define XTENSA_DBREGN_SREG(n) (0x0200+(n))
2556
2557 for (rmap = tdep->regmap, n = 0; rmap->target_number != -1; n++, rmap++)
2558 {
2559 if (rmap->target_number == 0x0020)
2560 tdep->pc_regnum = n;
2561 else if (rmap->target_number == 0x0100)
2562 tdep->ar_base = n;
2563 else if (rmap->target_number == 0x0000)
2564 tdep->a0_base = n;
2565 else if (rmap->target_number == XTENSA_DBREGN_SREG(72))
2566 tdep->wb_regnum = n;
2567 else if (rmap->target_number == XTENSA_DBREGN_SREG(73))
2568 tdep->ws_regnum = n;
2569 else if (rmap->target_number == XTENSA_DBREGN_SREG(233))
2570 tdep->debugcause_regnum = n;
2571 else if (rmap->target_number == XTENSA_DBREGN_SREG(232))
2572 tdep->exccause_regnum = n;
2573 else if (rmap->target_number == XTENSA_DBREGN_SREG(238))
2574 tdep->excvaddr_regnum = n;
2575 else if (rmap->target_number == XTENSA_DBREGN_SREG(0))
2576 tdep->lbeg_regnum = n;
2577 else if (rmap->target_number == XTENSA_DBREGN_SREG(1))
2578 tdep->lend_regnum = n;
2579 else if (rmap->target_number == XTENSA_DBREGN_SREG(2))
2580 tdep->lcount_regnum = n;
2581 else if (rmap->target_number == XTENSA_DBREGN_SREG(3))
2582 tdep->sar_regnum = n;
2583 else if (rmap->target_number == XTENSA_DBREGN_SREG(5))
2584 tdep->litbase_regnum = n;
2585 else if (rmap->target_number == XTENSA_DBREGN_SREG(230))
2586 tdep->ps_regnum = n;
2587#if 0
2588 else if (rmap->target_number == XTENSA_DBREGN_SREG(226))
2589 tdep->interrupt_regnum = n;
2590 else if (rmap->target_number == XTENSA_DBREGN_SREG(227))
2591 tdep->interrupt2_regnum = n;
2592 else if (rmap->target_number == XTENSA_DBREGN_SREG(224))
2593 tdep->cpenable_regnum = n;
2594#endif
2595
2596 if (rmap->byte_size > max_size)
2597 max_size = rmap->byte_size;
2598 if (rmap->mask != 0 && tdep->num_regs == 0)
2599 tdep->num_regs = n;
2600 /* Find out out how to deal with priveleged registers.
2601
2602 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
2603 && tdep->num_nopriv_regs == 0)
2604 tdep->num_nopriv_regs = n;
2605 */
2606 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
2607 && tdep->num_regs == 0)
2608 tdep->num_regs = n;
2609 }
2610
2611 /* Number of pseudo registers. */
2612 tdep->num_pseudo_regs = n - tdep->num_regs;
2613
2614 /* Empirically determined maximum sizes. */
2615 tdep->max_register_raw_size = max_size;
2616 tdep->max_register_virtual_size = max_size;
2617}
2618
ca3bf3bd
DJ		 2619/* Module "constructor" function. */
2620
94a0e877
MG		 2621extern struct gdbarch_tdep xtensa_tdep;
2622
ca3bf3bd
DJ		 2623static struct gdbarch *
2624xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2625{
2626 struct gdbarch_tdep *tdep;
2627 struct gdbarch *gdbarch;
2628 struct xtensa_abi_handler *abi_handler;
2629
2630 DEBUGTRACE ("gdbarch_init()\n");
2631
2632 /* We have to set the byte order before we call gdbarch_alloc. */
94a0e877 2633 info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
ca3bf3bd 2634
94a0e877 2635 tdep = &xtensa_tdep;
ca3bf3bd 2636 gdbarch = gdbarch_alloc (&info, tdep);
94a0e877 2637 xtensa_derive_tdep (tdep);
ca3bf3bd
DJ		 2638
2639 /* Verify our configuration. */
2640 xtensa_verify_config (gdbarch);
2641
bdb4c075 2642 /* Pseudo-Register read/write. */
ca3bf3bd
DJ		 2643 set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read);
2644 set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write);
2645
2646 /* Set target information. */
2647 set_gdbarch_num_regs (gdbarch, tdep->num_regs);
2648 set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs);
2649 set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1);
2650 set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum);
2651 set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum);
2652
ba2b1c56 2653 /* Renumber registers for known formats (stabs and dwarf2). */
ca3bf3bd 2654 set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
ca3bf3bd
DJ		 2655 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
2656
2657 /* We provide our own function to get register information. */
2658 set_gdbarch_register_name (gdbarch, xtensa_register_name);
2659 set_gdbarch_register_type (gdbarch, xtensa_register_type);
2660
2661 /* To call functions from GDB using dummy frame */
2662 set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call);
2663
2664 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2665
2666 set_gdbarch_return_value (gdbarch, xtensa_return_value);
2667
2668 /* Advance PC across any prologue instructions to reach "real" code. */
2669 set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue);
2670
2671 /* Stack grows downward. */
2672 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2673
2674 /* Set breakpoints. */
2675 set_gdbarch_breakpoint_from_pc (gdbarch, xtensa_breakpoint_from_pc);
2676
2677 /* After breakpoint instruction or illegal instruction, pc still
2678 points at break instruction, so don't decrement. */
2679 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2680
2681 /* We don't skip args. */
2682 set_gdbarch_frame_args_skip (gdbarch, 0);
2683
2684 set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc);
2685
2686 set_gdbarch_frame_align (gdbarch, xtensa_frame_align);
2687
5142f611 2688 set_gdbarch_dummy_id (gdbarch, xtensa_dummy_id);
ca3bf3bd
DJ		 2689
2690 /* Frame handling. */
2691 frame_base_set_default (gdbarch, &xtensa_frame_base);
5142f611
MG		 2692 frame_unwind_append_unwinder (gdbarch, &xtensa_unwind);
2693 dwarf2_append_unwinders (gdbarch);
ca3bf3bd
DJ		 2694
2695 set_gdbarch_print_insn (gdbarch, print_insn_xtensa);
2696
2697 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
2698
2699 xtensa_add_reggroups (gdbarch);
2700 set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p);
2701
2702 set_gdbarch_regset_from_core_section (gdbarch,
2703 xtensa_regset_from_core_section);
2704
ee967b5f
MG		 2705 set_solib_svr4_fetch_link_map_offsets
2706 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
2707
ca3bf3bd
DJ		 2708 return gdbarch;
2709}
2710
ca3bf3bd 2711static void
6b50c0b0 2712xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
ca3bf3bd
DJ		 2713{
2714 error (_("xtensa_dump_tdep(): not implemented"));
2715}
2716
ca3bf3bd
DJ		 2717void
2718_initialize_xtensa_tdep (void)
2719{
2720 struct cmd_list_element *c;
2721
2722 gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep);
2723 xtensa_init_reggroups ();
2724
2725 add_setshow_zinteger_cmd ("xtensa",
2726 class_maintenance,
2727 &xtensa_debug_level, _("\
2728Set Xtensa debugging."), _("\
2729Show Xtensa debugging."), _("\
2730When non-zero, Xtensa-specific debugging is enabled. \
2731Can be 1, 2, 3, or 4 indicating the level of debugging."),
2732 NULL,
2733 NULL,
2734 &setdebuglist, &showdebuglist);
2735}
GDB Binutils - Deliverables
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