Commit | Line | Data |
---|---|---|
ca3bf3bd DJ |
1 | /* Target-dependent code for the Xtensa port of GDB, the GNU debugger. |
2 | ||
61baf725 | 3 | Copyright (C) 2003-2017 Free Software Foundation, Inc. |
ca3bf3bd DJ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
ca3bf3bd DJ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
ca3bf3bd DJ |
19 | |
20 | #include "defs.h" | |
21 | #include "frame.h" | |
ee967b5f | 22 | #include "solib-svr4.h" |
ca3bf3bd DJ |
23 | #include "symtab.h" |
24 | #include "symfile.h" | |
25 | #include "objfiles.h" | |
26 | #include "gdbtypes.h" | |
27 | #include "gdbcore.h" | |
28 | #include "value.h" | |
29 | #include "dis-asm.h" | |
30 | #include "inferior.h" | |
40045d91 | 31 | #include "osabi.h" |
ca3bf3bd DJ |
32 | #include "floatformat.h" |
33 | #include "regcache.h" | |
34 | #include "reggroups.h" | |
35 | #include "regset.h" | |
36 | ||
37 | #include "dummy-frame.h" | |
fa8f86ff | 38 | #include "dwarf2.h" |
ca3bf3bd DJ |
39 | #include "dwarf2-frame.h" |
40 | #include "dwarf2loc.h" | |
ca3bf3bd DJ |
41 | #include "frame-base.h" |
42 | #include "frame-unwind.h" | |
43 | ||
44 | #include "arch-utils.h" | |
45 | #include "gdbarch.h" | |
46 | #include "remote.h" | |
47 | #include "serial.h" | |
48 | ||
49 | #include "command.h" | |
50 | #include "gdbcmd.h" | |
ca3bf3bd | 51 | |
bdb4c075 | 52 | #include "xtensa-isa.h" |
ca3bf3bd | 53 | #include "xtensa-tdep.h" |
94a0e877 | 54 | #include "xtensa-config.h" |
325fac50 | 55 | #include <algorithm> |
ca3bf3bd DJ |
56 | |
57 | ||
ccce17b0 | 58 | static unsigned int xtensa_debug_level = 0; |
ca3bf3bd DJ |
59 | |
60 | #define DEBUGWARN(args...) \ | |
61 | if (xtensa_debug_level > 0) \ | |
62 | fprintf_unfiltered (gdb_stdlog, "(warn ) " args) | |
63 | ||
64 | #define DEBUGINFO(args...) \ | |
65 | if (xtensa_debug_level > 1) \ | |
66 | fprintf_unfiltered (gdb_stdlog, "(info ) " args) | |
67 | ||
68 | #define DEBUGTRACE(args...) \ | |
69 | if (xtensa_debug_level > 2) \ | |
70 | fprintf_unfiltered (gdb_stdlog, "(trace) " args) | |
71 | ||
72 | #define DEBUGVERB(args...) \ | |
73 | if (xtensa_debug_level > 3) \ | |
74 | fprintf_unfiltered (gdb_stdlog, "(verb ) " args) | |
75 | ||
76 | ||
77 | /* According to the ABI, the SP must be aligned to 16-byte boundaries. */ | |
ca3bf3bd DJ |
78 | #define SP_ALIGNMENT 16 |
79 | ||
80 | ||
bdb4c075 MG |
81 | /* On Windowed ABI, we use a6 through a11 for passing arguments |
82 | to a function called by GDB because CALL4 is used. */ | |
bdb4c075 MG |
83 | #define ARGS_NUM_REGS 6 |
84 | #define REGISTER_SIZE 4 | |
ca3bf3bd | 85 | |
ca3bf3bd | 86 | |
bdb4c075 MG |
87 | /* Extract the call size from the return address or PS register. */ |
88 | #define PS_CALLINC_SHIFT 16 | |
89 | #define PS_CALLINC_MASK 0x00030000 | |
90 | #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT) | |
91 | #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3)) | |
ca3bf3bd | 92 | |
98689b25 MG |
93 | /* On TX, hardware can be configured without Exception Option. |
94 | There is no PS register in this case. Inside XT-GDB, let us treat | |
95 | it as a virtual read-only register always holding the same value. */ | |
96 | #define TX_PS 0x20 | |
97 | ||
bdb4c075 | 98 | /* ABI-independent macros. */ |
91d8eb23 MD |
99 | #define ARG_NOF(gdbarch) \ |
100 | (gdbarch_tdep (gdbarch)->call_abi \ | |
101 | == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS)) | |
102 | #define ARG_1ST(gdbarch) \ | |
103 | (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \ | |
94a0e877 | 104 | ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \ |
91d8eb23 | 105 | : (gdbarch_tdep (gdbarch)->a0_base + 6)) |
ca3bf3bd | 106 | |
ca3bf3bd DJ |
107 | /* XTENSA_IS_ENTRY tests whether the first byte of an instruction |
108 | indicates that the instruction is an ENTRY instruction. */ | |
109 | ||
91d8eb23 MD |
110 | #define XTENSA_IS_ENTRY(gdbarch, op1) \ |
111 | ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \ | |
4c6b5505 | 112 | ? ((op1) == 0x6c) : ((op1) == 0x36)) |
ca3bf3bd | 113 | |
bdb4c075 | 114 | #define XTENSA_ENTRY_LENGTH 3 |
ca3bf3bd DJ |
115 | |
116 | /* windowing_enabled() returns true, if windowing is enabled. | |
117 | WOE must be set to 1; EXCM to 0. | |
118 | Note: We assume that EXCM is always 0 for XEA1. */ | |
119 | ||
bdb4c075 MG |
120 | #define PS_WOE (1<<18) |
121 | #define PS_EXC (1<<4) | |
122 | ||
0dd5cbc5 AH |
123 | /* Big enough to hold the size of the largest register in bytes. */ |
124 | #define XTENSA_MAX_REGISTER_SIZE 64 | |
125 | ||
b801de47 | 126 | static int |
98689b25 MG |
127 | windowing_enabled (struct gdbarch *gdbarch, unsigned int ps) |
128 | { | |
129 | /* If we know CALL0 ABI is set explicitly, say it is Call0. */ | |
130 | if (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only) | |
131 | return 0; | |
132 | ||
133 | return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0); | |
134 | } | |
135 | ||
581e13c1 MS |
136 | /* Convert a live A-register number to the corresponding AR-register |
137 | number. */ | |
91d8eb23 | 138 | static int |
ee967b5f | 139 | arreg_number (struct gdbarch *gdbarch, int a_regnum, ULONGEST wb) |
91d8eb23 MD |
140 | { |
141 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
ee967b5f | 142 | int arreg; |
91d8eb23 | 143 | |
ee967b5f MG |
144 | arreg = a_regnum - tdep->a0_base; |
145 | arreg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT; | |
146 | arreg &= tdep->num_aregs - 1; | |
91d8eb23 | 147 | |
ee967b5f MG |
148 | return arreg + tdep->ar_base; |
149 | } | |
150 | ||
151 | /* Convert a live AR-register number to the corresponding A-register order | |
152 | number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */ | |
153 | static int | |
154 | areg_number (struct gdbarch *gdbarch, int ar_regnum, unsigned int wb) | |
155 | { | |
156 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
157 | int areg; | |
158 | ||
159 | areg = ar_regnum - tdep->ar_base; | |
160 | if (areg < 0 || areg >= tdep->num_aregs) | |
161 | return -1; | |
162 | areg = (areg - wb * 4) & (tdep->num_aregs - 1); | |
163 | return (areg > 15) ? -1 : areg; | |
91d8eb23 MD |
164 | } |
165 | ||
68d6df83 | 166 | /* Read Xtensa register directly from the hardware. */ |
b801de47 | 167 | static unsigned long |
08b9c608 MG |
168 | xtensa_read_register (int regnum) |
169 | { | |
170 | ULONGEST value; | |
171 | ||
172 | regcache_raw_read_unsigned (get_current_regcache (), regnum, &value); | |
173 | return (unsigned long) value; | |
174 | } | |
175 | ||
68d6df83 | 176 | /* Write Xtensa register directly to the hardware. */ |
b801de47 | 177 | static void |
08b9c608 MG |
178 | xtensa_write_register (int regnum, ULONGEST value) |
179 | { | |
180 | regcache_raw_write_unsigned (get_current_regcache (), regnum, value); | |
181 | } | |
182 | ||
ca3bf3bd DJ |
183 | /* Return the window size of the previous call to the function from which we |
184 | have just returned. | |
185 | ||
186 | This function is used to extract the return value after a called function | |
bdb4c075 | 187 | has returned to the caller. On Xtensa, the register that holds the return |
ca3bf3bd DJ |
188 | value (from the perspective of the caller) depends on what call |
189 | instruction was used. For now, we are assuming that the call instruction | |
190 | precedes the current address, so we simply analyze the call instruction. | |
191 | If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4' | |
192 | method to call the inferior function. */ | |
193 | ||
194 | static int | |
91d8eb23 | 195 | extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc) |
ca3bf3bd | 196 | { |
e17a4113 | 197 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
bdb4c075 | 198 | int winsize = 4; |
ca3bf3bd | 199 | int insn; |
ff7a4c00 | 200 | gdb_byte buf[4]; |
ca3bf3bd DJ |
201 | |
202 | DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc); | |
203 | ||
204 | /* Read the previous instruction (should be a call[x]{4|8|12}. */ | |
205 | read_memory (pc-3, buf, 3); | |
e17a4113 | 206 | insn = extract_unsigned_integer (buf, 3, byte_order); |
ca3bf3bd DJ |
207 | |
208 | /* Decode call instruction: | |
209 | Little Endian | |
210 | call{0,4,8,12} OFFSET || {00,01,10,11} || 0101 | |
211 | callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000 | |
212 | Big Endian | |
213 | call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET | |
214 | callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */ | |
215 | ||
e17a4113 | 216 | if (byte_order == BFD_ENDIAN_LITTLE) |
ca3bf3bd DJ |
217 | { |
218 | if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0)) | |
bdb4c075 | 219 | winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */ |
ca3bf3bd DJ |
220 | } |
221 | else | |
222 | { | |
223 | if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03)) | |
bdb4c075 | 224 | winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */ |
ca3bf3bd DJ |
225 | } |
226 | return winsize; | |
227 | } | |
228 | ||
229 | ||
230 | /* REGISTER INFORMATION */ | |
231 | ||
08b9c608 MG |
232 | /* Find register by name. */ |
233 | static int | |
a121b7c1 | 234 | xtensa_find_register_by_name (struct gdbarch *gdbarch, const char *name) |
08b9c608 MG |
235 | { |
236 | int i; | |
237 | ||
238 | for (i = 0; i < gdbarch_num_regs (gdbarch) | |
239 | + gdbarch_num_pseudo_regs (gdbarch); | |
240 | i++) | |
241 | ||
242 | if (strcasecmp (gdbarch_tdep (gdbarch)->regmap[i].name, name) == 0) | |
243 | return i; | |
244 | ||
245 | return -1; | |
246 | } | |
247 | ||
ca3bf3bd | 248 | /* Returns the name of a register. */ |
ca3bf3bd | 249 | static const char * |
d93859e2 | 250 | xtensa_register_name (struct gdbarch *gdbarch, int regnum) |
ca3bf3bd DJ |
251 | { |
252 | /* Return the name stored in the register map. */ | |
d93859e2 UW |
253 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch) |
254 | + gdbarch_num_pseudo_regs (gdbarch)) | |
255 | return gdbarch_tdep (gdbarch)->regmap[regnum].name; | |
ca3bf3bd | 256 | |
ca3bf3bd DJ |
257 | internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum); |
258 | return 0; | |
259 | } | |
260 | ||
ca3bf3bd DJ |
261 | /* Return the type of a register. Create a new type, if necessary. */ |
262 | ||
ca3bf3bd DJ |
263 | static struct type * |
264 | xtensa_register_type (struct gdbarch *gdbarch, int regnum) | |
265 | { | |
df4df182 UW |
266 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
267 | ||
ca3bf3bd | 268 | /* Return signed integer for ARx and Ax registers. */ |
df4df182 UW |
269 | if ((regnum >= tdep->ar_base |
270 | && regnum < tdep->ar_base + tdep->num_aregs) | |
271 | || (regnum >= tdep->a0_base | |
272 | && regnum < tdep->a0_base + 16)) | |
0dfff4cb | 273 | return builtin_type (gdbarch)->builtin_int; |
ca3bf3bd | 274 | |
6b50c0b0 | 275 | if (regnum == gdbarch_pc_regnum (gdbarch) |
df4df182 | 276 | || regnum == tdep->a0_base + 1) |
fde6c819 | 277 | return builtin_type (gdbarch)->builtin_data_ptr; |
ca3bf3bd DJ |
278 | |
279 | /* Return the stored type for all other registers. */ | |
6b50c0b0 UW |
280 | else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch) |
281 | + gdbarch_num_pseudo_regs (gdbarch)) | |
ca3bf3bd | 282 | { |
df4df182 | 283 | xtensa_register_t* reg = &tdep->regmap[regnum]; |
ca3bf3bd | 284 | |
bdb4c075 | 285 | /* Set ctype for this register (only the first time). */ |
ca3bf3bd DJ |
286 | |
287 | if (reg->ctype == 0) | |
288 | { | |
289 | struct ctype_cache *tp; | |
290 | int size = reg->byte_size; | |
291 | ||
bdb4c075 MG |
292 | /* We always use the memory representation, |
293 | even if the register width is smaller. */ | |
ca3bf3bd DJ |
294 | switch (size) |
295 | { | |
296 | case 1: | |
df4df182 | 297 | reg->ctype = builtin_type (gdbarch)->builtin_uint8; |
ca3bf3bd DJ |
298 | break; |
299 | ||
300 | case 2: | |
df4df182 | 301 | reg->ctype = builtin_type (gdbarch)->builtin_uint16; |
ca3bf3bd DJ |
302 | break; |
303 | ||
304 | case 4: | |
df4df182 | 305 | reg->ctype = builtin_type (gdbarch)->builtin_uint32; |
ca3bf3bd DJ |
306 | break; |
307 | ||
308 | case 8: | |
df4df182 | 309 | reg->ctype = builtin_type (gdbarch)->builtin_uint64; |
ca3bf3bd DJ |
310 | break; |
311 | ||
312 | case 16: | |
df4df182 | 313 | reg->ctype = builtin_type (gdbarch)->builtin_uint128; |
ca3bf3bd DJ |
314 | break; |
315 | ||
316 | default: | |
df4df182 | 317 | for (tp = tdep->type_entries; tp != NULL; tp = tp->next) |
ca3bf3bd DJ |
318 | if (tp->size == size) |
319 | break; | |
320 | ||
321 | if (tp == NULL) | |
322 | { | |
1448a0a2 | 323 | char *name = xstrprintf ("int%d", size * 8); |
8d749320 SM |
324 | |
325 | tp = XNEW (struct ctype_cache); | |
df4df182 UW |
326 | tp->next = tdep->type_entries; |
327 | tdep->type_entries = tp; | |
ca3bf3bd | 328 | tp->size = size; |
e9bb382b | 329 | tp->virtual_type |
1448a0a2 PM |
330 | = arch_integer_type (gdbarch, size * 8, 1, name); |
331 | xfree (name); | |
ca3bf3bd DJ |
332 | } |
333 | ||
334 | reg->ctype = tp->virtual_type; | |
335 | } | |
336 | } | |
337 | return reg->ctype; | |
338 | } | |
339 | ||
ca3bf3bd DJ |
340 | internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum); |
341 | return 0; | |
342 | } | |
343 | ||
344 | ||
bdb4c075 | 345 | /* Return the 'local' register number for stubs, dwarf2, etc. |
ca3bf3bd DJ |
346 | The debugging information enumerates registers starting from 0 for A0 |
347 | to n for An. So, we only have to add the base number for A0. */ | |
348 | ||
349 | static int | |
d3f73121 | 350 | xtensa_reg_to_regnum (struct gdbarch *gdbarch, int regnum) |
ca3bf3bd DJ |
351 | { |
352 | int i; | |
353 | ||
354 | if (regnum >= 0 && regnum < 16) | |
d3f73121 | 355 | return gdbarch_tdep (gdbarch)->a0_base + regnum; |
ca3bf3bd | 356 | |
f57d151a | 357 | for (i = 0; |
d3f73121 | 358 | i < gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
f57d151a | 359 | i++) |
d3f73121 | 360 | if (regnum == gdbarch_tdep (gdbarch)->regmap[i].target_number) |
ca3bf3bd DJ |
361 | return i; |
362 | ||
0fde2c53 | 363 | return -1; |
ca3bf3bd DJ |
364 | } |
365 | ||
366 | ||
bdb4c075 MG |
367 | /* Write the bits of a masked register to the various registers. |
368 | Only the masked areas of these registers are modified; the other | |
369 | fields are untouched. The size of masked registers is always less | |
370 | than or equal to 32 bits. */ | |
ca3bf3bd DJ |
371 | |
372 | static void | |
9c9acae0 UW |
373 | xtensa_register_write_masked (struct regcache *regcache, |
374 | xtensa_register_t *reg, const gdb_byte *buffer) | |
ca3bf3bd | 375 | { |
0dd5cbc5 | 376 | unsigned int value[(XTENSA_MAX_REGISTER_SIZE + 3) / 4]; |
ca3bf3bd DJ |
377 | const xtensa_mask_t *mask = reg->mask; |
378 | ||
379 | int shift = 0; /* Shift for next mask (mod 32). */ | |
380 | int start, size; /* Start bit and size of current mask. */ | |
381 | ||
382 | unsigned int *ptr = value; | |
383 | unsigned int regval, m, mem = 0; | |
384 | ||
385 | int bytesize = reg->byte_size; | |
386 | int bitsize = bytesize * 8; | |
387 | int i, r; | |
388 | ||
389 | DEBUGTRACE ("xtensa_register_write_masked ()\n"); | |
390 | ||
391 | /* Copy the masked register to host byte-order. */ | |
6b50c0b0 | 392 | if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
393 | for (i = 0; i < bytesize; i++) |
394 | { | |
395 | mem >>= 8; | |
396 | mem |= (buffer[bytesize - i - 1] << 24); | |
397 | if ((i & 3) == 3) | |
398 | *ptr++ = mem; | |
399 | } | |
400 | else | |
401 | for (i = 0; i < bytesize; i++) | |
402 | { | |
403 | mem >>= 8; | |
404 | mem |= (buffer[i] << 24); | |
405 | if ((i & 3) == 3) | |
406 | *ptr++ = mem; | |
407 | } | |
408 | ||
409 | /* We might have to shift the final value: | |
410 | bytesize & 3 == 0 -> nothing to do, we use the full 32 bits, | |
411 | bytesize & 3 == x -> shift (4-x) * 8. */ | |
412 | ||
413 | *ptr = mem >> (((0 - bytesize) & 3) * 8); | |
414 | ptr = value; | |
415 | mem = *ptr; | |
416 | ||
417 | /* Write the bits to the masked areas of the other registers. */ | |
418 | for (i = 0; i < mask->count; i++) | |
419 | { | |
420 | start = mask->mask[i].bit_start; | |
421 | size = mask->mask[i].bit_size; | |
422 | regval = mem >> shift; | |
423 | ||
424 | if ((shift += size) > bitsize) | |
425 | error (_("size of all masks is larger than the register")); | |
426 | ||
427 | if (shift >= 32) | |
428 | { | |
429 | mem = *(++ptr); | |
430 | shift -= 32; | |
431 | bitsize -= 32; | |
432 | ||
433 | if (shift > 0) | |
434 | regval |= mem << (size - shift); | |
435 | } | |
436 | ||
437 | /* Make sure we have a valid register. */ | |
438 | r = mask->mask[i].reg_num; | |
439 | if (r >= 0 && size > 0) | |
440 | { | |
441 | /* Don't overwrite the unmasked areas. */ | |
9c9acae0 UW |
442 | ULONGEST old_val; |
443 | regcache_cooked_read_unsigned (regcache, r, &old_val); | |
ca3bf3bd DJ |
444 | m = 0xffffffff >> (32 - size) << start; |
445 | regval <<= start; | |
9c9acae0 UW |
446 | regval = (regval & m) | (old_val & ~m); |
447 | regcache_cooked_write_unsigned (regcache, r, regval); | |
ca3bf3bd DJ |
448 | } |
449 | } | |
450 | } | |
451 | ||
452 | ||
bdb4c075 MG |
453 | /* Read a tie state or mapped registers. Read the masked areas |
454 | of the registers and assemble them into a single value. */ | |
ca3bf3bd | 455 | |
05d1431c | 456 | static enum register_status |
9c9acae0 UW |
457 | xtensa_register_read_masked (struct regcache *regcache, |
458 | xtensa_register_t *reg, gdb_byte *buffer) | |
ca3bf3bd | 459 | { |
0dd5cbc5 | 460 | unsigned int value[(XTENSA_MAX_REGISTER_SIZE + 3) / 4]; |
ca3bf3bd DJ |
461 | const xtensa_mask_t *mask = reg->mask; |
462 | ||
463 | int shift = 0; | |
464 | int start, size; | |
465 | ||
466 | unsigned int *ptr = value; | |
467 | unsigned int regval, mem = 0; | |
468 | ||
469 | int bytesize = reg->byte_size; | |
470 | int bitsize = bytesize * 8; | |
471 | int i; | |
472 | ||
473 | DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n", | |
474 | reg->name == 0 ? "" : reg->name); | |
475 | ||
476 | /* Assemble the register from the masked areas of other registers. */ | |
477 | for (i = 0; i < mask->count; i++) | |
478 | { | |
479 | int r = mask->mask[i].reg_num; | |
9c9acae0 UW |
480 | if (r >= 0) |
481 | { | |
05d1431c | 482 | enum register_status status; |
9c9acae0 | 483 | ULONGEST val; |
05d1431c PA |
484 | |
485 | status = regcache_cooked_read_unsigned (regcache, r, &val); | |
486 | if (status != REG_VALID) | |
487 | return status; | |
9c9acae0 UW |
488 | regval = (unsigned int) val; |
489 | } | |
490 | else | |
491 | regval = 0; | |
492 | ||
ca3bf3bd DJ |
493 | start = mask->mask[i].bit_start; |
494 | size = mask->mask[i].bit_size; | |
495 | ||
496 | regval >>= start; | |
497 | ||
498 | if (size < 32) | |
499 | regval &= (0xffffffff >> (32 - size)); | |
500 | ||
501 | mem |= regval << shift; | |
502 | ||
503 | if ((shift += size) > bitsize) | |
504 | error (_("size of all masks is larger than the register")); | |
505 | ||
506 | if (shift >= 32) | |
507 | { | |
508 | *ptr++ = mem; | |
509 | bitsize -= 32; | |
510 | shift -= 32; | |
511 | ||
512 | if (shift == 0) | |
513 | mem = 0; | |
514 | else | |
515 | mem = regval >> (size - shift); | |
516 | } | |
517 | } | |
518 | ||
519 | if (shift > 0) | |
520 | *ptr = mem; | |
521 | ||
522 | /* Copy value to target byte order. */ | |
523 | ptr = value; | |
524 | mem = *ptr; | |
525 | ||
6b50c0b0 | 526 | if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
527 | for (i = 0; i < bytesize; i++) |
528 | { | |
529 | if ((i & 3) == 0) | |
530 | mem = *ptr++; | |
531 | buffer[bytesize - i - 1] = mem & 0xff; | |
532 | mem >>= 8; | |
533 | } | |
534 | else | |
535 | for (i = 0; i < bytesize; i++) | |
536 | { | |
537 | if ((i & 3) == 0) | |
538 | mem = *ptr++; | |
539 | buffer[i] = mem & 0xff; | |
540 | mem >>= 8; | |
541 | } | |
05d1431c PA |
542 | |
543 | return REG_VALID; | |
ca3bf3bd DJ |
544 | } |
545 | ||
546 | ||
547 | /* Read pseudo registers. */ | |
548 | ||
05d1431c | 549 | static enum register_status |
ca3bf3bd DJ |
550 | xtensa_pseudo_register_read (struct gdbarch *gdbarch, |
551 | struct regcache *regcache, | |
552 | int regnum, | |
553 | gdb_byte *buffer) | |
554 | { | |
e17a4113 UW |
555 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
556 | ||
ca3bf3bd | 557 | DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n", |
d93859e2 | 558 | regnum, xtensa_register_name (gdbarch, regnum)); |
ca3bf3bd | 559 | |
bdb4c075 | 560 | /* Read aliases a0..a15, if this is a Windowed ABI. */ |
6b50c0b0 | 561 | if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers |
94a0e877 | 562 | && (regnum >= gdbarch_tdep (gdbarch)->a0_base) |
6b50c0b0 | 563 | && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)) |
ca3bf3bd | 564 | { |
c185f580 | 565 | ULONGEST value; |
05d1431c | 566 | enum register_status status; |
ca3bf3bd | 567 | |
c185f580 AH |
568 | status = regcache_raw_read_unsigned (regcache, |
569 | gdbarch_tdep (gdbarch)->wb_regnum, | |
570 | &value); | |
05d1431c PA |
571 | if (status != REG_VALID) |
572 | return status; | |
c185f580 | 573 | regnum = arreg_number (gdbarch, regnum, value); |
ca3bf3bd DJ |
574 | } |
575 | ||
bdb4c075 | 576 | /* We can always read non-pseudo registers. */ |
6b50c0b0 | 577 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) |
05d1431c | 578 | return regcache_raw_read (regcache, regnum, buffer); |
94a0e877 MG |
579 | |
580 | /* We have to find out how to deal with priveleged registers. | |
581 | Let's treat them as pseudo-registers, but we cannot read/write them. */ | |
582 | ||
0d0bf81a MF |
583 | else if (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only |
584 | || regnum < gdbarch_tdep (gdbarch)->a0_base) | |
94a0e877 MG |
585 | { |
586 | buffer[0] = (gdb_byte)0; | |
587 | buffer[1] = (gdb_byte)0; | |
588 | buffer[2] = (gdb_byte)0; | |
589 | buffer[3] = (gdb_byte)0; | |
05d1431c | 590 | return REG_VALID; |
94a0e877 | 591 | } |
ca3bf3bd | 592 | /* Pseudo registers. */ |
f57d151a | 593 | else if (regnum >= 0 |
6b50c0b0 UW |
594 | && regnum < gdbarch_num_regs (gdbarch) |
595 | + gdbarch_num_pseudo_regs (gdbarch)) | |
ca3bf3bd | 596 | { |
6b50c0b0 | 597 | xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; |
ca3bf3bd | 598 | xtensa_register_type_t type = reg->type; |
6b50c0b0 | 599 | int flags = gdbarch_tdep (gdbarch)->target_flags; |
ca3bf3bd | 600 | |
bdb4c075 | 601 | /* We cannot read Unknown or Unmapped registers. */ |
ca3bf3bd DJ |
602 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) |
603 | { | |
604 | if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
605 | { | |
606 | warning (_("cannot read register %s"), | |
d93859e2 | 607 | xtensa_register_name (gdbarch, regnum)); |
05d1431c | 608 | return REG_VALID; |
ca3bf3bd DJ |
609 | } |
610 | } | |
611 | ||
612 | /* Some targets cannot read TIE register files. */ | |
613 | else if (type == xtRegisterTypeTieRegfile) | |
614 | { | |
615 | /* Use 'fetch' to get register? */ | |
616 | if (flags & xtTargetFlagsUseFetchStore) | |
617 | { | |
618 | warning (_("cannot read register")); | |
05d1431c | 619 | return REG_VALID; |
ca3bf3bd DJ |
620 | } |
621 | ||
622 | /* On some targets (esp. simulators), we can always read the reg. */ | |
623 | else if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
624 | { | |
625 | warning (_("cannot read register")); | |
05d1431c | 626 | return REG_VALID; |
ca3bf3bd DJ |
627 | } |
628 | } | |
629 | ||
630 | /* We can always read mapped registers. */ | |
631 | else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState) | |
05d1431c | 632 | return xtensa_register_read_masked (regcache, reg, buffer); |
ca3bf3bd DJ |
633 | |
634 | /* Assume that we can read the register. */ | |
05d1431c | 635 | return regcache_raw_read (regcache, regnum, buffer); |
ca3bf3bd | 636 | } |
ca3bf3bd DJ |
637 | else |
638 | internal_error (__FILE__, __LINE__, | |
639 | _("invalid register number %d"), regnum); | |
640 | } | |
641 | ||
642 | ||
643 | /* Write pseudo registers. */ | |
644 | ||
645 | static void | |
646 | xtensa_pseudo_register_write (struct gdbarch *gdbarch, | |
647 | struct regcache *regcache, | |
648 | int regnum, | |
649 | const gdb_byte *buffer) | |
650 | { | |
e17a4113 UW |
651 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
652 | ||
ca3bf3bd | 653 | DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n", |
d93859e2 | 654 | regnum, xtensa_register_name (gdbarch, regnum)); |
ca3bf3bd | 655 | |
bdb4c075 | 656 | /* Renumber register, if aliase a0..a15 on Windowed ABI. */ |
6b50c0b0 | 657 | if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers |
94a0e877 | 658 | && (regnum >= gdbarch_tdep (gdbarch)->a0_base) |
6b50c0b0 | 659 | && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)) |
ca3bf3bd | 660 | { |
c185f580 AH |
661 | ULONGEST value; |
662 | regcache_raw_read_unsigned (regcache, | |
663 | gdbarch_tdep (gdbarch)->wb_regnum, &value); | |
664 | regnum = arreg_number (gdbarch, regnum, value); | |
ca3bf3bd DJ |
665 | } |
666 | ||
667 | /* We can always write 'core' registers. | |
668 | Note: We might have converted Ax->ARy. */ | |
6b50c0b0 | 669 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) |
ca3bf3bd DJ |
670 | regcache_raw_write (regcache, regnum, buffer); |
671 | ||
94a0e877 MG |
672 | /* We have to find out how to deal with priveleged registers. |
673 | Let's treat them as pseudo-registers, but we cannot read/write them. */ | |
674 | ||
675 | else if (regnum < gdbarch_tdep (gdbarch)->a0_base) | |
676 | { | |
677 | return; | |
678 | } | |
ca3bf3bd | 679 | /* Pseudo registers. */ |
f57d151a | 680 | else if (regnum >= 0 |
6b50c0b0 UW |
681 | && regnum < gdbarch_num_regs (gdbarch) |
682 | + gdbarch_num_pseudo_regs (gdbarch)) | |
ca3bf3bd | 683 | { |
6b50c0b0 | 684 | xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; |
ca3bf3bd | 685 | xtensa_register_type_t type = reg->type; |
6b50c0b0 | 686 | int flags = gdbarch_tdep (gdbarch)->target_flags; |
ca3bf3bd | 687 | |
bdb4c075 MG |
688 | /* On most targets, we cannot write registers |
689 | of type "Unknown" or "Unmapped". */ | |
ca3bf3bd DJ |
690 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) |
691 | { | |
692 | if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
693 | { | |
694 | warning (_("cannot write register %s"), | |
d93859e2 | 695 | xtensa_register_name (gdbarch, regnum)); |
ca3bf3bd DJ |
696 | return; |
697 | } | |
698 | } | |
699 | ||
700 | /* Some targets cannot read TIE register files. */ | |
701 | else if (type == xtRegisterTypeTieRegfile) | |
702 | { | |
703 | /* Use 'store' to get register? */ | |
704 | if (flags & xtTargetFlagsUseFetchStore) | |
705 | { | |
706 | warning (_("cannot write register")); | |
707 | return; | |
708 | } | |
709 | ||
710 | /* On some targets (esp. simulators), we can always write | |
711 | the register. */ | |
ca3bf3bd DJ |
712 | else if ((flags & xtTargetFlagsNonVisibleRegs) == 0) |
713 | { | |
714 | warning (_("cannot write register")); | |
715 | return; | |
716 | } | |
717 | } | |
718 | ||
719 | /* We can always write mapped registers. */ | |
720 | else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState) | |
721 | { | |
9c9acae0 | 722 | xtensa_register_write_masked (regcache, reg, buffer); |
ca3bf3bd DJ |
723 | return; |
724 | } | |
725 | ||
726 | /* Assume that we can write the register. */ | |
727 | regcache_raw_write (regcache, regnum, buffer); | |
728 | } | |
ca3bf3bd DJ |
729 | else |
730 | internal_error (__FILE__, __LINE__, | |
731 | _("invalid register number %d"), regnum); | |
732 | } | |
733 | ||
ca3bf3bd DJ |
734 | static struct reggroup *xtensa_ar_reggroup; |
735 | static struct reggroup *xtensa_user_reggroup; | |
736 | static struct reggroup *xtensa_vectra_reggroup; | |
7b871568 | 737 | static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR]; |
ca3bf3bd DJ |
738 | |
739 | static void | |
740 | xtensa_init_reggroups (void) | |
741 | { | |
98689b25 | 742 | int i; |
98689b25 | 743 | |
ca3bf3bd DJ |
744 | xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP); |
745 | xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP); | |
746 | xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP); | |
ca3bf3bd | 747 | |
98689b25 | 748 | for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++) |
9c3cc999 | 749 | xtensa_cp[i] = reggroup_new (xstrprintf ("cp%d", i), USER_REGGROUP); |
7b871568 | 750 | } |
ca3bf3bd DJ |
751 | |
752 | static void | |
753 | xtensa_add_reggroups (struct gdbarch *gdbarch) | |
754 | { | |
7b871568 MG |
755 | int i; |
756 | ||
757 | /* Predefined groups. */ | |
ca3bf3bd DJ |
758 | reggroup_add (gdbarch, all_reggroup); |
759 | reggroup_add (gdbarch, save_reggroup); | |
760 | reggroup_add (gdbarch, restore_reggroup); | |
761 | reggroup_add (gdbarch, system_reggroup); | |
7b871568 MG |
762 | reggroup_add (gdbarch, vector_reggroup); |
763 | reggroup_add (gdbarch, general_reggroup); | |
764 | reggroup_add (gdbarch, float_reggroup); | |
765 | ||
766 | /* Xtensa-specific groups. */ | |
767 | reggroup_add (gdbarch, xtensa_ar_reggroup); | |
768 | reggroup_add (gdbarch, xtensa_user_reggroup); | |
769 | reggroup_add (gdbarch, xtensa_vectra_reggroup); | |
ca3bf3bd | 770 | |
7b871568 MG |
771 | for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++) |
772 | reggroup_add (gdbarch, xtensa_cp[i]); | |
ca3bf3bd DJ |
773 | } |
774 | ||
7b871568 MG |
775 | static int |
776 | xtensa_coprocessor_register_group (struct reggroup *group) | |
777 | { | |
778 | int i; | |
779 | ||
780 | for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++) | |
781 | if (group == xtensa_cp[i]) | |
782 | return i; | |
783 | ||
784 | return -1; | |
785 | } | |
ca3bf3bd DJ |
786 | |
787 | #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \ | |
788 | | XTENSA_REGISTER_FLAGS_WRITABLE \ | |
789 | | XTENSA_REGISTER_FLAGS_VOLATILE) | |
790 | ||
791 | #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \ | |
792 | | XTENSA_REGISTER_FLAGS_WRITABLE) | |
793 | ||
794 | static int | |
795 | xtensa_register_reggroup_p (struct gdbarch *gdbarch, | |
796 | int regnum, | |
797 | struct reggroup *group) | |
798 | { | |
6b50c0b0 | 799 | xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; |
ca3bf3bd DJ |
800 | xtensa_register_type_t type = reg->type; |
801 | xtensa_register_group_t rg = reg->group; | |
7b871568 | 802 | int cp_number; |
ca3bf3bd | 803 | |
57041825 MG |
804 | if (group == save_reggroup) |
805 | /* Every single register should be included into the list of registers | |
806 | to be watched for changes while using -data-list-changed-registers. */ | |
807 | return 1; | |
808 | ||
ca3bf3bd DJ |
809 | /* First, skip registers that are not visible to this target |
810 | (unknown and unmapped registers when not using ISS). */ | |
811 | ||
812 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) | |
813 | return 0; | |
814 | if (group == all_reggroup) | |
815 | return 1; | |
816 | if (group == xtensa_ar_reggroup) | |
817 | return rg & xtRegisterGroupAddrReg; | |
818 | if (group == xtensa_user_reggroup) | |
819 | return rg & xtRegisterGroupUser; | |
820 | if (group == float_reggroup) | |
821 | return rg & xtRegisterGroupFloat; | |
822 | if (group == general_reggroup) | |
823 | return rg & xtRegisterGroupGeneral; | |
ca3bf3bd DJ |
824 | if (group == system_reggroup) |
825 | return rg & xtRegisterGroupState; | |
826 | if (group == vector_reggroup || group == xtensa_vectra_reggroup) | |
827 | return rg & xtRegisterGroupVectra; | |
57041825 | 828 | if (group == restore_reggroup) |
6b50c0b0 | 829 | return (regnum < gdbarch_num_regs (gdbarch) |
ca3bf3bd | 830 | && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID); |
1448a0a2 PM |
831 | cp_number = xtensa_coprocessor_register_group (group); |
832 | if (cp_number >= 0) | |
7b871568 | 833 | return rg & (xtRegisterGroupCP0 << cp_number); |
ca3bf3bd DJ |
834 | else |
835 | return 1; | |
836 | } | |
837 | ||
838 | ||
ca3bf3bd DJ |
839 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
840 | in the general-purpose register set REGSET to register cache | |
bdb4c075 | 841 | REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */ |
ca3bf3bd DJ |
842 | |
843 | static void | |
844 | xtensa_supply_gregset (const struct regset *regset, | |
845 | struct regcache *rc, | |
846 | int regnum, | |
847 | const void *gregs, | |
848 | size_t len) | |
849 | { | |
19ba03f4 | 850 | const xtensa_elf_gregset_t *regs = (const xtensa_elf_gregset_t *) gregs; |
6b50c0b0 | 851 | struct gdbarch *gdbarch = get_regcache_arch (rc); |
ca3bf3bd DJ |
852 | int i; |
853 | ||
cce7e648 | 854 | DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum); |
ca3bf3bd | 855 | |
6b50c0b0 UW |
856 | if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1) |
857 | regcache_raw_supply (rc, gdbarch_pc_regnum (gdbarch), (char *) ®s->pc); | |
858 | if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1) | |
859 | regcache_raw_supply (rc, gdbarch_ps_regnum (gdbarch), (char *) ®s->ps); | |
860 | if (regnum == gdbarch_tdep (gdbarch)->wb_regnum || regnum == -1) | |
861 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->wb_regnum, | |
304fe255 | 862 | (char *) ®s->windowbase); |
6b50c0b0 UW |
863 | if (regnum == gdbarch_tdep (gdbarch)->ws_regnum || regnum == -1) |
864 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ws_regnum, | |
304fe255 | 865 | (char *) ®s->windowstart); |
6b50c0b0 UW |
866 | if (regnum == gdbarch_tdep (gdbarch)->lbeg_regnum || regnum == -1) |
867 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lbeg_regnum, | |
304fe255 | 868 | (char *) ®s->lbeg); |
6b50c0b0 UW |
869 | if (regnum == gdbarch_tdep (gdbarch)->lend_regnum || regnum == -1) |
870 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lend_regnum, | |
304fe255 | 871 | (char *) ®s->lend); |
6b50c0b0 UW |
872 | if (regnum == gdbarch_tdep (gdbarch)->lcount_regnum || regnum == -1) |
873 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lcount_regnum, | |
304fe255 | 874 | (char *) ®s->lcount); |
6b50c0b0 UW |
875 | if (regnum == gdbarch_tdep (gdbarch)->sar_regnum || regnum == -1) |
876 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->sar_regnum, | |
304fe255 | 877 | (char *) ®s->sar); |
6b50c0b0 UW |
878 | if (regnum >=gdbarch_tdep (gdbarch)->ar_base |
879 | && regnum < gdbarch_tdep (gdbarch)->ar_base | |
880 | + gdbarch_tdep (gdbarch)->num_aregs) | |
304fe255 UW |
881 | regcache_raw_supply (rc, regnum, |
882 | (char *) ®s->ar[regnum - gdbarch_tdep | |
6b50c0b0 | 883 | (gdbarch)->ar_base]); |
ca3bf3bd DJ |
884 | else if (regnum == -1) |
885 | { | |
6b50c0b0 UW |
886 | for (i = 0; i < gdbarch_tdep (gdbarch)->num_aregs; ++i) |
887 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ar_base + i, | |
304fe255 | 888 | (char *) ®s->ar[i]); |
ca3bf3bd DJ |
889 | } |
890 | } | |
891 | ||
892 | ||
893 | /* Xtensa register set. */ | |
894 | ||
895 | static struct regset | |
896 | xtensa_gregset = | |
897 | { | |
898 | NULL, | |
899 | xtensa_supply_gregset | |
900 | }; | |
901 | ||
902 | ||
97094034 | 903 | /* Iterate over supported core file register note sections. */ |
ca3bf3bd | 904 | |
97094034 AA |
905 | static void |
906 | xtensa_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
907 | iterate_over_regset_sections_cb *cb, | |
908 | void *cb_data, | |
909 | const struct regcache *regcache) | |
ca3bf3bd | 910 | { |
97094034 | 911 | DEBUGTRACE ("xtensa_iterate_over_regset_sections\n"); |
ca3bf3bd | 912 | |
97094034 AA |
913 | cb (".reg", sizeof (xtensa_elf_gregset_t), &xtensa_gregset, |
914 | NULL, cb_data); | |
ca3bf3bd DJ |
915 | } |
916 | ||
917 | ||
bdb4c075 | 918 | /* Handling frames. */ |
ca3bf3bd | 919 | |
bdb4c075 MG |
920 | /* Number of registers to save in case of Windowed ABI. */ |
921 | #define XTENSA_NUM_SAVED_AREGS 12 | |
ca3bf3bd | 922 | |
bdb4c075 MG |
923 | /* Frame cache part for Windowed ABI. */ |
924 | typedef struct xtensa_windowed_frame_cache | |
ca3bf3bd | 925 | { |
ee967b5f MG |
926 | int wb; /* WINDOWBASE of the previous frame. */ |
927 | int callsize; /* Call size of this frame. */ | |
08b9c608 MG |
928 | int ws; /* WINDOWSTART of the previous frame. It keeps track of |
929 | life windows only. If there is no bit set for the | |
930 | window, that means it had been already spilled | |
931 | because of window overflow. */ | |
932 | ||
933 | /* Addresses of spilled A-registers. | |
934 | AREGS[i] == -1, if corresponding AR is alive. */ | |
ca3bf3bd | 935 | CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS]; |
bdb4c075 MG |
936 | } xtensa_windowed_frame_cache_t; |
937 | ||
938 | /* Call0 ABI Definitions. */ | |
939 | ||
581e13c1 MS |
940 | #define C0_MAXOPDS 3 /* Maximum number of operands for prologue |
941 | analysis. */ | |
bdb4c075 MG |
942 | #define C0_CLESV 12 /* Callee-saved registers are here and up. */ |
943 | #define C0_SP 1 /* Register used as SP. */ | |
944 | #define C0_FP 15 /* Register used as FP. */ | |
945 | #define C0_RA 0 /* Register used as return address. */ | |
946 | #define C0_ARGS 2 /* Register used as first arg/retval. */ | |
947 | #define C0_NARGS 6 /* Number of A-regs for args/retvals. */ | |
948 | ||
949 | /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each | |
950 | A-register where the current content of the reg came from (in terms | |
951 | of an original reg and a constant). Negative values of c0_rt[n].fp_reg | |
952 | mean that the orignal content of the register was saved to the stack. | |
953 | c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't | |
954 | know where SP will end up until the entire prologue has been analyzed. */ | |
955 | ||
956 | #define C0_CONST -1 /* fr_reg value if register contains a constant. */ | |
957 | #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */ | |
958 | #define C0_NOSTK -1 /* to_stk value if register has not been stored. */ | |
959 | ||
960 | extern xtensa_isa xtensa_default_isa; | |
961 | ||
962 | typedef struct xtensa_c0reg | |
963 | { | |
dbab50de MG |
964 | int fr_reg; /* original register from which register content |
965 | is derived, or C0_CONST, or C0_INEXP. */ | |
966 | int fr_ofs; /* constant offset from reg, or immediate value. */ | |
967 | int to_stk; /* offset from original SP to register (4-byte aligned), | |
968 | or C0_NOSTK if register has not been saved. */ | |
bdb4c075 MG |
969 | } xtensa_c0reg_t; |
970 | ||
bdb4c075 MG |
971 | /* Frame cache part for Call0 ABI. */ |
972 | typedef struct xtensa_call0_frame_cache | |
973 | { | |
dbab50de MG |
974 | int c0_frmsz; /* Stack frame size. */ |
975 | int c0_hasfp; /* Current frame uses frame pointer. */ | |
976 | int fp_regnum; /* A-register used as FP. */ | |
977 | int c0_fp; /* Actual value of frame pointer. */ | |
978 | int c0_fpalign; /* Dinamic adjustment for the stack | |
979 | pointer. It's an AND mask. Zero, | |
980 | if alignment was not adjusted. */ | |
981 | int c0_old_sp; /* In case of dynamic adjustment, it is | |
982 | a register holding unaligned sp. | |
983 | C0_INEXP, when undefined. */ | |
984 | int c0_sp_ofs; /* If "c0_old_sp" was spilled it's a | |
985 | stack offset. C0_NOSTK otherwise. */ | |
986 | ||
987 | xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */ | |
bdb4c075 MG |
988 | } xtensa_call0_frame_cache_t; |
989 | ||
990 | typedef struct xtensa_frame_cache | |
991 | { | |
ee967b5f | 992 | CORE_ADDR base; /* Stack pointer of this frame. */ |
08b9c608 MG |
993 | CORE_ADDR pc; /* PC of this frame at the function entry point. */ |
994 | CORE_ADDR ra; /* The raw return address of this frame. */ | |
995 | CORE_ADDR ps; /* The PS register of the previous (older) frame. */ | |
996 | CORE_ADDR prev_sp; /* Stack Pointer of the previous (older) frame. */ | |
bdb4c075 MG |
997 | int call0; /* It's a call0 framework (else windowed). */ |
998 | union | |
999 | { | |
1000 | xtensa_windowed_frame_cache_t wd; /* call0 == false. */ | |
1001 | xtensa_call0_frame_cache_t c0; /* call0 == true. */ | |
1002 | }; | |
ca3bf3bd DJ |
1003 | } xtensa_frame_cache_t; |
1004 | ||
1005 | ||
1006 | static struct xtensa_frame_cache * | |
bdb4c075 | 1007 | xtensa_alloc_frame_cache (int windowed) |
ca3bf3bd DJ |
1008 | { |
1009 | xtensa_frame_cache_t *cache; | |
1010 | int i; | |
1011 | ||
1012 | DEBUGTRACE ("xtensa_alloc_frame_cache ()\n"); | |
1013 | ||
1014 | cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t); | |
1015 | ||
1016 | cache->base = 0; | |
1017 | cache->pc = 0; | |
1018 | cache->ra = 0; | |
ca3bf3bd | 1019 | cache->ps = 0; |
ca3bf3bd | 1020 | cache->prev_sp = 0; |
bdb4c075 MG |
1021 | cache->call0 = !windowed; |
1022 | if (cache->call0) | |
1023 | { | |
1024 | cache->c0.c0_frmsz = -1; | |
1025 | cache->c0.c0_hasfp = 0; | |
1026 | cache->c0.fp_regnum = -1; | |
1027 | cache->c0.c0_fp = -1; | |
dbab50de MG |
1028 | cache->c0.c0_fpalign = 0; |
1029 | cache->c0.c0_old_sp = C0_INEXP; | |
1030 | cache->c0.c0_sp_ofs = C0_NOSTK; | |
ca3bf3bd | 1031 | |
bdb4c075 MG |
1032 | for (i = 0; i < C0_NREGS; i++) |
1033 | { | |
1034 | cache->c0.c0_rt[i].fr_reg = i; | |
1035 | cache->c0.c0_rt[i].fr_ofs = 0; | |
1036 | cache->c0.c0_rt[i].to_stk = C0_NOSTK; | |
1037 | } | |
1038 | } | |
1039 | else | |
1040 | { | |
1041 | cache->wd.wb = 0; | |
ee967b5f | 1042 | cache->wd.ws = 0; |
bdb4c075 | 1043 | cache->wd.callsize = -1; |
ca3bf3bd | 1044 | |
bdb4c075 MG |
1045 | for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++) |
1046 | cache->wd.aregs[i] = -1; | |
1047 | } | |
ca3bf3bd DJ |
1048 | return cache; |
1049 | } | |
1050 | ||
1051 | ||
1052 | static CORE_ADDR | |
1053 | xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) | |
1054 | { | |
1055 | return address & ~15; | |
1056 | } | |
1057 | ||
1058 | ||
1059 | static CORE_ADDR | |
1060 | xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1061 | { | |
ff7a4c00 | 1062 | gdb_byte buf[8]; |
0dfff4cb | 1063 | CORE_ADDR pc; |
ca3bf3bd | 1064 | |
a74ce742 PM |
1065 | DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n", |
1066 | host_address_to_string (next_frame)); | |
ca3bf3bd | 1067 | |
6b50c0b0 | 1068 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1069 | pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
ca3bf3bd | 1070 | |
0dfff4cb | 1071 | DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc); |
ca3bf3bd | 1072 | |
0dfff4cb | 1073 | return pc; |
ca3bf3bd DJ |
1074 | } |
1075 | ||
1076 | ||
1077 | static struct frame_id | |
5142f611 | 1078 | xtensa_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
ca3bf3bd DJ |
1079 | { |
1080 | CORE_ADDR pc, fp; | |
ca3bf3bd | 1081 | |
5142f611 | 1082 | /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */ |
ca3bf3bd | 1083 | |
5142f611 MG |
1084 | pc = get_frame_pc (this_frame); |
1085 | fp = get_frame_register_unsigned | |
1086 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1); | |
ca3bf3bd DJ |
1087 | |
1088 | /* Make dummy frame ID unique by adding a constant. */ | |
bdb4c075 | 1089 | return frame_id_build (fp + SP_ALIGNMENT, pc); |
ca3bf3bd DJ |
1090 | } |
1091 | ||
08b9c608 MG |
1092 | /* Returns true, if instruction to execute next is unique to Xtensa Window |
1093 | Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */ | |
1094 | ||
1095 | static int | |
1096 | xtensa_window_interrupt_insn (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1097 | { | |
1098 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1099 | unsigned int insn = read_memory_integer (pc, 4, byte_order); | |
1100 | unsigned int code; | |
1101 | ||
1102 | if (byte_order == BFD_ENDIAN_BIG) | |
1103 | { | |
1104 | /* Check, if this is L32E or S32E. */ | |
1105 | code = insn & 0xf000ff00; | |
1106 | if ((code == 0x00009000) || (code == 0x00009400)) | |
1107 | return 1; | |
1108 | /* Check, if this is RFWU or RFWO. */ | |
1109 | code = insn & 0xffffff00; | |
1110 | return ((code == 0x00430000) || (code == 0x00530000)); | |
1111 | } | |
1112 | else | |
1113 | { | |
1114 | /* Check, if this is L32E or S32E. */ | |
1115 | code = insn & 0x00ff000f; | |
1116 | if ((code == 0x090000) || (code == 0x490000)) | |
1117 | return 1; | |
1118 | /* Check, if this is RFWU or RFWO. */ | |
1119 | code = insn & 0x00ffffff; | |
1120 | return ((code == 0x00003400) || (code == 0x00003500)); | |
1121 | } | |
1122 | } | |
1123 | ||
ee967b5f MG |
1124 | /* Returns the best guess about which register is a frame pointer |
1125 | for the function containing CURRENT_PC. */ | |
1126 | ||
d4709618 MG |
1127 | #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */ |
1128 | #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */ | |
ee967b5f MG |
1129 | |
1130 | static unsigned int | |
1131 | xtensa_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR current_pc) | |
1132 | { | |
1133 | #define RETURN_FP goto done | |
1134 | ||
1135 | unsigned int fp_regnum = gdbarch_tdep (gdbarch)->a0_base + 1; | |
1136 | CORE_ADDR start_addr; | |
1137 | xtensa_isa isa; | |
1138 | xtensa_insnbuf ins, slot; | |
948f8e3d | 1139 | gdb_byte ibuf[XTENSA_ISA_BSZ]; |
ee967b5f MG |
1140 | CORE_ADDR ia, bt, ba; |
1141 | xtensa_format ifmt; | |
1142 | int ilen, islots, is; | |
1143 | xtensa_opcode opc; | |
1144 | const char *opcname; | |
1145 | ||
1146 | find_pc_partial_function (current_pc, NULL, &start_addr, NULL); | |
1147 | if (start_addr == 0) | |
1148 | return fp_regnum; | |
1149 | ||
ee967b5f MG |
1150 | isa = xtensa_default_isa; |
1151 | gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); | |
1152 | ins = xtensa_insnbuf_alloc (isa); | |
1153 | slot = xtensa_insnbuf_alloc (isa); | |
1154 | ba = 0; | |
1155 | ||
1156 | for (ia = start_addr, bt = ia; ia < current_pc ; ia += ilen) | |
1157 | { | |
1158 | if (ia + xtensa_isa_maxlength (isa) > bt) | |
1159 | { | |
1160 | ba = ia; | |
1161 | bt = (ba + XTENSA_ISA_BSZ) < current_pc | |
1162 | ? ba + XTENSA_ISA_BSZ : current_pc; | |
d4709618 MG |
1163 | if (target_read_memory (ba, ibuf, bt - ba) != 0) |
1164 | RETURN_FP; | |
ee967b5f MG |
1165 | } |
1166 | ||
1167 | xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); | |
1168 | ifmt = xtensa_format_decode (isa, ins); | |
1169 | if (ifmt == XTENSA_UNDEFINED) | |
1170 | RETURN_FP; | |
1171 | ilen = xtensa_format_length (isa, ifmt); | |
1172 | if (ilen == XTENSA_UNDEFINED) | |
1173 | RETURN_FP; | |
1174 | islots = xtensa_format_num_slots (isa, ifmt); | |
1175 | if (islots == XTENSA_UNDEFINED) | |
1176 | RETURN_FP; | |
1177 | ||
1178 | for (is = 0; is < islots; ++is) | |
1179 | { | |
1180 | if (xtensa_format_get_slot (isa, ifmt, is, ins, slot)) | |
1181 | RETURN_FP; | |
1182 | ||
1183 | opc = xtensa_opcode_decode (isa, ifmt, is, slot); | |
1184 | if (opc == XTENSA_UNDEFINED) | |
1185 | RETURN_FP; | |
1186 | ||
1187 | opcname = xtensa_opcode_name (isa, opc); | |
1188 | ||
1189 | if (strcasecmp (opcname, "mov.n") == 0 | |
1190 | || strcasecmp (opcname, "or") == 0) | |
1191 | { | |
1192 | unsigned int register_operand; | |
1193 | ||
1194 | /* Possible candidate for setting frame pointer | |
581e13c1 | 1195 | from A1. This is what we are looking for. */ |
ee967b5f MG |
1196 | |
1197 | if (xtensa_operand_get_field (isa, opc, 1, ifmt, | |
1198 | is, slot, ®ister_operand) != 0) | |
1199 | RETURN_FP; | |
1200 | if (xtensa_operand_decode (isa, opc, 1, ®ister_operand) != 0) | |
1201 | RETURN_FP; | |
1202 | if (register_operand == 1) /* Mov{.n} FP A1. */ | |
1203 | { | |
1204 | if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, | |
1205 | ®ister_operand) != 0) | |
1206 | RETURN_FP; | |
1207 | if (xtensa_operand_decode (isa, opc, 0, | |
1208 | ®ister_operand) != 0) | |
1209 | RETURN_FP; | |
1210 | ||
581e13c1 MS |
1211 | fp_regnum |
1212 | = gdbarch_tdep (gdbarch)->a0_base + register_operand; | |
ee967b5f MG |
1213 | RETURN_FP; |
1214 | } | |
1215 | } | |
1216 | ||
1217 | if ( | |
1218 | /* We have problems decoding the memory. */ | |
1219 | opcname == NULL | |
1220 | || strcasecmp (opcname, "ill") == 0 | |
1221 | || strcasecmp (opcname, "ill.n") == 0 | |
1222 | /* Hit planted breakpoint. */ | |
1223 | || strcasecmp (opcname, "break") == 0 | |
1224 | || strcasecmp (opcname, "break.n") == 0 | |
1225 | /* Flow control instructions finish prologue. */ | |
1226 | || xtensa_opcode_is_branch (isa, opc) > 0 | |
1227 | || xtensa_opcode_is_jump (isa, opc) > 0 | |
1228 | || xtensa_opcode_is_loop (isa, opc) > 0 | |
1229 | || xtensa_opcode_is_call (isa, opc) > 0 | |
1230 | || strcasecmp (opcname, "simcall") == 0 | |
1231 | || strcasecmp (opcname, "syscall") == 0) | |
1232 | /* Can not continue analysis. */ | |
1233 | RETURN_FP; | |
1234 | } | |
1235 | } | |
1236 | done: | |
1237 | xtensa_insnbuf_free(isa, slot); | |
1238 | xtensa_insnbuf_free(isa, ins); | |
1239 | return fp_regnum; | |
1240 | } | |
1241 | ||
bdb4c075 MG |
1242 | /* The key values to identify the frame using "cache" are |
1243 | ||
ee967b5f | 1244 | cache->base = SP (or best guess about FP) of this frame; |
bdb4c075 | 1245 | cache->pc = entry-PC (entry point of the frame function); |
581e13c1 | 1246 | cache->prev_sp = SP of the previous frame. */ |
bdb4c075 MG |
1247 | |
1248 | static void | |
5142f611 | 1249 | call0_frame_cache (struct frame_info *this_frame, |
dbab50de | 1250 | xtensa_frame_cache_t *cache, CORE_ADDR pc); |
ca3bf3bd | 1251 | |
08b9c608 MG |
1252 | static void |
1253 | xtensa_window_interrupt_frame_cache (struct frame_info *this_frame, | |
1254 | xtensa_frame_cache_t *cache, | |
1255 | CORE_ADDR pc); | |
1256 | ||
ca3bf3bd | 1257 | static struct xtensa_frame_cache * |
5142f611 | 1258 | xtensa_frame_cache (struct frame_info *this_frame, void **this_cache) |
ca3bf3bd DJ |
1259 | { |
1260 | xtensa_frame_cache_t *cache; | |
ca3bf3bd | 1261 | CORE_ADDR ra, wb, ws, pc, sp, ps; |
5142f611 | 1262 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
e17a4113 | 1263 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
ee967b5f | 1264 | unsigned int fp_regnum; |
98689b25 | 1265 | int windowed, ps_regnum; |
ca3bf3bd | 1266 | |
ca3bf3bd | 1267 | if (*this_cache) |
19ba03f4 | 1268 | return (struct xtensa_frame_cache *) *this_cache; |
ca3bf3bd | 1269 | |
98689b25 MG |
1270 | pc = get_frame_register_unsigned (this_frame, gdbarch_pc_regnum (gdbarch)); |
1271 | ps_regnum = gdbarch_ps_regnum (gdbarch); | |
68d6df83 MG |
1272 | ps = (ps_regnum >= 0 |
1273 | ? get_frame_register_unsigned (this_frame, ps_regnum) : TX_PS); | |
98689b25 MG |
1274 | |
1275 | windowed = windowing_enabled (gdbarch, ps); | |
bdb4c075 | 1276 | |
ca3bf3bd | 1277 | /* Get pristine xtensa-frame. */ |
bdb4c075 | 1278 | cache = xtensa_alloc_frame_cache (windowed); |
ca3bf3bd DJ |
1279 | *this_cache = cache; |
1280 | ||
bdb4c075 | 1281 | if (windowed) |
ca3bf3bd | 1282 | { |
a08b52b5 | 1283 | LONGEST op1; |
98689b25 | 1284 | |
bdb4c075 | 1285 | /* Get WINDOWBASE, WINDOWSTART, and PS registers. */ |
5142f611 MG |
1286 | wb = get_frame_register_unsigned (this_frame, |
1287 | gdbarch_tdep (gdbarch)->wb_regnum); | |
1288 | ws = get_frame_register_unsigned (this_frame, | |
1289 | gdbarch_tdep (gdbarch)->ws_regnum); | |
ca3bf3bd | 1290 | |
a08b52b5 MF |
1291 | if (safe_read_memory_integer (pc, 1, byte_order, &op1) |
1292 | && XTENSA_IS_ENTRY (gdbarch, op1)) | |
ca3bf3bd | 1293 | { |
bdb4c075 | 1294 | int callinc = CALLINC (ps); |
5142f611 MG |
1295 | ra = get_frame_register_unsigned |
1296 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + callinc * 4); | |
bdb4c075 MG |
1297 | |
1298 | /* ENTRY hasn't been executed yet, therefore callsize is still 0. */ | |
1299 | cache->wd.callsize = 0; | |
1300 | cache->wd.wb = wb; | |
1301 | cache->wd.ws = ws; | |
5142f611 MG |
1302 | cache->prev_sp = get_frame_register_unsigned |
1303 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1); | |
ee967b5f MG |
1304 | |
1305 | /* This only can be the outermost frame since we are | |
1306 | just about to execute ENTRY. SP hasn't been set yet. | |
1307 | We can assume any frame size, because it does not | |
1308 | matter, and, let's fake frame base in cache. */ | |
98689b25 | 1309 | cache->base = cache->prev_sp - 16; |
ee967b5f MG |
1310 | |
1311 | cache->pc = pc; | |
1312 | cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff); | |
1313 | cache->ps = (ps & ~PS_CALLINC_MASK) | |
1314 | | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT); | |
1315 | ||
1316 | return cache; | |
bdb4c075 MG |
1317 | } |
1318 | else | |
1319 | { | |
ee967b5f | 1320 | fp_regnum = xtensa_scan_prologue (gdbarch, pc); |
5142f611 MG |
1321 | ra = get_frame_register_unsigned (this_frame, |
1322 | gdbarch_tdep (gdbarch)->a0_base); | |
bdb4c075 | 1323 | cache->wd.callsize = WINSIZE (ra); |
304fe255 | 1324 | cache->wd.wb = (wb - cache->wd.callsize / 4) |
6b50c0b0 | 1325 | & (gdbarch_tdep (gdbarch)->num_aregs / 4 - 1); |
bdb4c075 | 1326 | cache->wd.ws = ws & ~(1 << wb); |
ca3bf3bd | 1327 | |
5142f611 | 1328 | cache->pc = get_frame_func (this_frame); |
f6402f18 | 1329 | cache->ra = (pc & 0xc0000000) | (ra & 0x3fffffff); |
ee967b5f MG |
1330 | cache->ps = (ps & ~PS_CALLINC_MASK) |
1331 | | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT); | |
1332 | } | |
bdb4c075 MG |
1333 | |
1334 | if (cache->wd.ws == 0) | |
ca3bf3bd | 1335 | { |
bdb4c075 | 1336 | int i; |
ca3bf3bd | 1337 | |
bdb4c075 | 1338 | /* Set A0...A3. */ |
5142f611 MG |
1339 | sp = get_frame_register_unsigned |
1340 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1) - 16; | |
bdb4c075 MG |
1341 | |
1342 | for (i = 0; i < 4; i++, sp += 4) | |
1343 | { | |
1344 | cache->wd.aregs[i] = sp; | |
1345 | } | |
ca3bf3bd | 1346 | |
bdb4c075 | 1347 | if (cache->wd.callsize > 4) |
ca3bf3bd | 1348 | { |
bdb4c075 | 1349 | /* Set A4...A7/A11. */ |
ee967b5f MG |
1350 | /* Get the SP of the frame previous to the previous one. |
1351 | To achieve this, we have to dereference SP twice. */ | |
e17a4113 UW |
1352 | sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order); |
1353 | sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order); | |
bdb4c075 MG |
1354 | sp -= cache->wd.callsize * 4; |
1355 | ||
ee967b5f | 1356 | for ( i = 4; i < cache->wd.callsize; i++, sp += 4) |
bdb4c075 MG |
1357 | { |
1358 | cache->wd.aregs[i] = sp; | |
1359 | } | |
ca3bf3bd DJ |
1360 | } |
1361 | } | |
ca3bf3bd | 1362 | |
bdb4c075 | 1363 | if ((cache->prev_sp == 0) && ( ra != 0 )) |
08b9c608 MG |
1364 | /* If RA is equal to 0 this frame is an outermost frame. Leave |
1365 | cache->prev_sp unchanged marking the boundary of the frame stack. */ | |
ca3bf3bd | 1366 | { |
ee967b5f | 1367 | if ((cache->wd.ws & (1 << cache->wd.wb)) == 0) |
bdb4c075 MG |
1368 | { |
1369 | /* Register window overflow already happened. | |
1370 | We can read caller's SP from the proper spill loction. */ | |
5142f611 MG |
1371 | sp = get_frame_register_unsigned |
1372 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1); | |
e17a4113 | 1373 | cache->prev_sp = read_memory_integer (sp - 12, 4, byte_order); |
bdb4c075 MG |
1374 | } |
1375 | else | |
1376 | { | |
1377 | /* Read caller's frame SP directly from the previous window. */ | |
ee967b5f | 1378 | int regnum = arreg_number |
91d8eb23 | 1379 | (gdbarch, gdbarch_tdep (gdbarch)->a0_base + 1, |
304fe255 | 1380 | cache->wd.wb); |
ca3bf3bd | 1381 | |
08b9c608 | 1382 | cache->prev_sp = xtensa_read_register (regnum); |
bdb4c075 | 1383 | } |
ca3bf3bd DJ |
1384 | } |
1385 | } | |
08b9c608 MG |
1386 | else if (xtensa_window_interrupt_insn (gdbarch, pc)) |
1387 | { | |
1388 | /* Execution stopped inside Xtensa Window Interrupt Handler. */ | |
1389 | ||
1390 | xtensa_window_interrupt_frame_cache (this_frame, cache, pc); | |
1391 | /* Everything was set already, including cache->base. */ | |
1392 | return cache; | |
1393 | } | |
bdb4c075 MG |
1394 | else /* Call0 framework. */ |
1395 | { | |
dbab50de | 1396 | call0_frame_cache (this_frame, cache, pc); |
ee967b5f | 1397 | fp_regnum = cache->c0.fp_regnum; |
bdb4c075 | 1398 | } |
ca3bf3bd | 1399 | |
5142f611 | 1400 | cache->base = get_frame_register_unsigned (this_frame, fp_regnum); |
ca3bf3bd | 1401 | |
ca3bf3bd DJ |
1402 | return cache; |
1403 | } | |
1404 | ||
dbab50de MG |
1405 | static int xtensa_session_once_reported = 1; |
1406 | ||
1407 | /* Report a problem with prologue analysis while doing backtracing. | |
1408 | But, do it only once to avoid annoyng repeated messages. */ | |
1409 | ||
4e6ca6d5 MG |
1410 | static void |
1411 | warning_once (void) | |
dbab50de MG |
1412 | { |
1413 | if (xtensa_session_once_reported == 0) | |
1414 | warning (_("\ | |
1415 | \nUnrecognised function prologue. Stack trace cannot be resolved. \ | |
1416 | This message will not be repeated in this session.\n")); | |
1417 | ||
1418 | xtensa_session_once_reported = 1; | |
1419 | } | |
1420 | ||
1421 | ||
ca3bf3bd | 1422 | static void |
5142f611 | 1423 | xtensa_frame_this_id (struct frame_info *this_frame, |
ca3bf3bd DJ |
1424 | void **this_cache, |
1425 | struct frame_id *this_id) | |
1426 | { | |
1427 | struct xtensa_frame_cache *cache = | |
5142f611 | 1428 | xtensa_frame_cache (this_frame, this_cache); |
ca3bf3bd DJ |
1429 | |
1430 | if (cache->prev_sp == 0) | |
1431 | return; | |
1432 | ||
5142f611 | 1433 | (*this_id) = frame_id_build (cache->prev_sp, cache->pc); |
bdb4c075 | 1434 | } |
ca3bf3bd | 1435 | |
5142f611 MG |
1436 | static struct value * |
1437 | xtensa_frame_prev_register (struct frame_info *this_frame, | |
ca3bf3bd | 1438 | void **this_cache, |
5142f611 | 1439 | int regnum) |
ca3bf3bd | 1440 | { |
5142f611 MG |
1441 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1442 | struct xtensa_frame_cache *cache; | |
1443 | ULONGEST saved_reg = 0; | |
ca3bf3bd DJ |
1444 | int done = 1; |
1445 | ||
5142f611 MG |
1446 | if (*this_cache == NULL) |
1447 | *this_cache = xtensa_frame_cache (this_frame, this_cache); | |
19ba03f4 | 1448 | cache = (struct xtensa_frame_cache *) *this_cache; |
ca3bf3bd | 1449 | |
6b50c0b0 | 1450 | if (regnum ==gdbarch_pc_regnum (gdbarch)) |
bdb4c075 | 1451 | saved_reg = cache->ra; |
6b50c0b0 | 1452 | else if (regnum == gdbarch_tdep (gdbarch)->a0_base + 1) |
bdb4c075 MG |
1453 | saved_reg = cache->prev_sp; |
1454 | else if (!cache->call0) | |
ca3bf3bd | 1455 | { |
6b50c0b0 | 1456 | if (regnum == gdbarch_tdep (gdbarch)->ws_regnum) |
ee967b5f | 1457 | saved_reg = cache->wd.ws; |
6b50c0b0 | 1458 | else if (regnum == gdbarch_tdep (gdbarch)->wb_regnum) |
bdb4c075 | 1459 | saved_reg = cache->wd.wb; |
6b50c0b0 | 1460 | else if (regnum == gdbarch_ps_regnum (gdbarch)) |
bdb4c075 | 1461 | saved_reg = cache->ps; |
ca3bf3bd | 1462 | else |
bdb4c075 | 1463 | done = 0; |
ca3bf3bd | 1464 | } |
ca3bf3bd DJ |
1465 | else |
1466 | done = 0; | |
1467 | ||
1468 | if (done) | |
5142f611 | 1469 | return frame_unwind_got_constant (this_frame, regnum, saved_reg); |
ca3bf3bd | 1470 | |
bdb4c075 | 1471 | if (!cache->call0) /* Windowed ABI. */ |
ca3bf3bd | 1472 | { |
ee967b5f MG |
1473 | /* Convert A-register numbers to AR-register numbers, |
1474 | if we deal with A-register. */ | |
94a0e877 | 1475 | if (regnum >= gdbarch_tdep (gdbarch)->a0_base |
6b50c0b0 | 1476 | && regnum <= gdbarch_tdep (gdbarch)->a0_base + 15) |
ee967b5f | 1477 | regnum = arreg_number (gdbarch, regnum, cache->wd.wb); |
ca3bf3bd | 1478 | |
ee967b5f | 1479 | /* Check, if we deal with AR-register saved on stack. */ |
6b50c0b0 UW |
1480 | if (regnum >= gdbarch_tdep (gdbarch)->ar_base |
1481 | && regnum <= (gdbarch_tdep (gdbarch)->ar_base | |
1482 | + gdbarch_tdep (gdbarch)->num_aregs)) | |
bdb4c075 | 1483 | { |
ee967b5f | 1484 | int areg = areg_number (gdbarch, regnum, cache->wd.wb); |
ca3bf3bd | 1485 | |
bdb4c075 MG |
1486 | if (areg >= 0 |
1487 | && areg < XTENSA_NUM_SAVED_AREGS | |
1488 | && cache->wd.aregs[areg] != -1) | |
5142f611 MG |
1489 | return frame_unwind_got_memory (this_frame, regnum, |
1490 | cache->wd.aregs[areg]); | |
ca3bf3bd DJ |
1491 | } |
1492 | } | |
bdb4c075 MG |
1493 | else /* Call0 ABI. */ |
1494 | { | |
6b50c0b0 UW |
1495 | int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base |
1496 | && regnum <= (gdbarch_tdep (gdbarch)->ar_base | |
304fe255 | 1497 | + C0_NREGS)) |
6b50c0b0 | 1498 | ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum; |
ca3bf3bd | 1499 | |
bdb4c075 MG |
1500 | if (reg < C0_NREGS) |
1501 | { | |
1502 | CORE_ADDR spe; | |
1503 | int stkofs; | |
1504 | ||
1505 | /* If register was saved in the prologue, retrieve it. */ | |
1506 | stkofs = cache->c0.c0_rt[reg].to_stk; | |
1507 | if (stkofs != C0_NOSTK) | |
1508 | { | |
1509 | /* Determine SP on entry based on FP. */ | |
1510 | spe = cache->c0.c0_fp | |
1511 | - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs; | |
5142f611 | 1512 | |
581e13c1 MS |
1513 | return frame_unwind_got_memory (this_frame, regnum, |
1514 | spe + stkofs); | |
bdb4c075 MG |
1515 | } |
1516 | } | |
1517 | } | |
1518 | ||
1519 | /* All other registers have been either saved to | |
1520 | the stack or are still alive in the processor. */ | |
ca3bf3bd | 1521 | |
5142f611 | 1522 | return frame_unwind_got_register (this_frame, regnum, regnum); |
ca3bf3bd DJ |
1523 | } |
1524 | ||
1525 | ||
1526 | static const struct frame_unwind | |
5142f611 | 1527 | xtensa_unwind = |
ca3bf3bd DJ |
1528 | { |
1529 | NORMAL_FRAME, | |
8fbca658 | 1530 | default_frame_unwind_stop_reason, |
ca3bf3bd | 1531 | xtensa_frame_this_id, |
5142f611 MG |
1532 | xtensa_frame_prev_register, |
1533 | NULL, | |
1534 | default_frame_sniffer | |
ca3bf3bd DJ |
1535 | }; |
1536 | ||
ca3bf3bd | 1537 | static CORE_ADDR |
5142f611 | 1538 | xtensa_frame_base_address (struct frame_info *this_frame, void **this_cache) |
ca3bf3bd DJ |
1539 | { |
1540 | struct xtensa_frame_cache *cache = | |
5142f611 | 1541 | xtensa_frame_cache (this_frame, this_cache); |
ca3bf3bd DJ |
1542 | |
1543 | return cache->base; | |
1544 | } | |
1545 | ||
1546 | static const struct frame_base | |
1547 | xtensa_frame_base = | |
1548 | { | |
5142f611 | 1549 | &xtensa_unwind, |
ca3bf3bd DJ |
1550 | xtensa_frame_base_address, |
1551 | xtensa_frame_base_address, | |
1552 | xtensa_frame_base_address | |
1553 | }; | |
1554 | ||
1555 | ||
1556 | static void | |
1557 | xtensa_extract_return_value (struct type *type, | |
1558 | struct regcache *regcache, | |
1559 | void *dst) | |
1560 | { | |
6b50c0b0 | 1561 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
19ba03f4 | 1562 | bfd_byte *valbuf = (bfd_byte *) dst; |
ca3bf3bd DJ |
1563 | int len = TYPE_LENGTH (type); |
1564 | ULONGEST pc, wb; | |
1565 | int callsize, areg; | |
1566 | int offset = 0; | |
1567 | ||
1568 | DEBUGTRACE ("xtensa_extract_return_value (...)\n"); | |
1569 | ||
1570 | gdb_assert(len > 0); | |
1571 | ||
6b50c0b0 | 1572 | if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
bdb4c075 MG |
1573 | { |
1574 | /* First, we have to find the caller window in the register file. */ | |
6b50c0b0 | 1575 | regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc); |
91d8eb23 | 1576 | callsize = extract_call_winsize (gdbarch, pc); |
ca3bf3bd | 1577 | |
bdb4c075 MG |
1578 | /* On Xtensa, we can return up to 4 words (or 2 for call12). */ |
1579 | if (len > (callsize > 8 ? 8 : 16)) | |
1580 | internal_error (__FILE__, __LINE__, | |
581e13c1 MS |
1581 | _("cannot extract return value of %d bytes long"), |
1582 | len); | |
ca3bf3bd | 1583 | |
bdb4c075 MG |
1584 | /* Get the register offset of the return |
1585 | register (A2) in the caller window. */ | |
304fe255 | 1586 | regcache_raw_read_unsigned |
6b50c0b0 | 1587 | (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb); |
ee967b5f | 1588 | areg = arreg_number (gdbarch, |
91d8eb23 | 1589 | gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb); |
bdb4c075 MG |
1590 | } |
1591 | else | |
1592 | { | |
1593 | /* No windowing hardware - Call0 ABI. */ | |
94a0e877 | 1594 | areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS; |
bdb4c075 | 1595 | } |
ca3bf3bd DJ |
1596 | |
1597 | DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len); | |
1598 | ||
6b50c0b0 | 1599 | if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1600 | offset = 4 - len; |
1601 | ||
1602 | for (; len > 0; len -= 4, areg++, valbuf += 4) | |
1603 | { | |
1604 | if (len < 4) | |
1605 | regcache_raw_read_part (regcache, areg, offset, len, valbuf); | |
1606 | else | |
1607 | regcache_raw_read (regcache, areg, valbuf); | |
1608 | } | |
1609 | } | |
1610 | ||
1611 | ||
1612 | static void | |
1613 | xtensa_store_return_value (struct type *type, | |
1614 | struct regcache *regcache, | |
1615 | const void *dst) | |
1616 | { | |
6b50c0b0 | 1617 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
19ba03f4 | 1618 | const bfd_byte *valbuf = (const bfd_byte *) dst; |
ca3bf3bd DJ |
1619 | unsigned int areg; |
1620 | ULONGEST pc, wb; | |
1621 | int callsize; | |
1622 | int len = TYPE_LENGTH (type); | |
1623 | int offset = 0; | |
1624 | ||
1625 | DEBUGTRACE ("xtensa_store_return_value (...)\n"); | |
1626 | ||
6b50c0b0 | 1627 | if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
bdb4c075 | 1628 | { |
6b50c0b0 UW |
1629 | regcache_raw_read_unsigned |
1630 | (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb); | |
1631 | regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc); | |
91d8eb23 | 1632 | callsize = extract_call_winsize (gdbarch, pc); |
ca3bf3bd | 1633 | |
bdb4c075 MG |
1634 | if (len > (callsize > 8 ? 8 : 16)) |
1635 | internal_error (__FILE__, __LINE__, | |
1636 | _("unimplemented for this length: %d"), | |
1637 | TYPE_LENGTH (type)); | |
ee967b5f MG |
1638 | areg = arreg_number (gdbarch, |
1639 | gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb); | |
ca3bf3bd | 1640 | |
bdb4c075 | 1641 | DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n", |
ca3bf3bd | 1642 | callsize, (int) wb); |
bdb4c075 MG |
1643 | } |
1644 | else | |
1645 | { | |
94a0e877 | 1646 | areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS; |
bdb4c075 | 1647 | } |
ca3bf3bd | 1648 | |
6b50c0b0 | 1649 | if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1650 | offset = 4 - len; |
1651 | ||
ca3bf3bd DJ |
1652 | for (; len > 0; len -= 4, areg++, valbuf += 4) |
1653 | { | |
1654 | if (len < 4) | |
1655 | regcache_raw_write_part (regcache, areg, offset, len, valbuf); | |
1656 | else | |
1657 | regcache_raw_write (regcache, areg, valbuf); | |
1658 | } | |
1659 | } | |
1660 | ||
1661 | ||
bdb4c075 | 1662 | static enum return_value_convention |
ca3bf3bd | 1663 | xtensa_return_value (struct gdbarch *gdbarch, |
6a3a010b | 1664 | struct value *function, |
ca3bf3bd DJ |
1665 | struct type *valtype, |
1666 | struct regcache *regcache, | |
1667 | gdb_byte *readbuf, | |
1668 | const gdb_byte *writebuf) | |
1669 | { | |
bdb4c075 | 1670 | /* Structures up to 16 bytes are returned in registers. */ |
ca3bf3bd DJ |
1671 | |
1672 | int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT | |
1673 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
1674 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
1675 | && TYPE_LENGTH (valtype) > 16); | |
1676 | ||
1677 | if (struct_return) | |
1678 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1679 | ||
1680 | DEBUGTRACE ("xtensa_return_value(...)\n"); | |
1681 | ||
1682 | if (writebuf != NULL) | |
1683 | { | |
1684 | xtensa_store_return_value (valtype, regcache, writebuf); | |
1685 | } | |
1686 | ||
1687 | if (readbuf != NULL) | |
1688 | { | |
1689 | gdb_assert (!struct_return); | |
1690 | xtensa_extract_return_value (valtype, regcache, readbuf); | |
1691 | } | |
1692 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1693 | } | |
1694 | ||
1695 | ||
1696 | /* DUMMY FRAME */ | |
1697 | ||
1698 | static CORE_ADDR | |
1699 | xtensa_push_dummy_call (struct gdbarch *gdbarch, | |
1700 | struct value *function, | |
1701 | struct regcache *regcache, | |
1702 | CORE_ADDR bp_addr, | |
1703 | int nargs, | |
1704 | struct value **args, | |
1705 | CORE_ADDR sp, | |
1706 | int struct_return, | |
1707 | CORE_ADDR struct_addr) | |
1708 | { | |
e17a4113 | 1709 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
ca3bf3bd DJ |
1710 | int i; |
1711 | int size, onstack_size; | |
ff7a4c00 | 1712 | gdb_byte *buf = (gdb_byte *) alloca (16); |
ca3bf3bd DJ |
1713 | CORE_ADDR ra, ps; |
1714 | struct argument_info | |
1715 | { | |
1716 | const bfd_byte *contents; | |
1717 | int length; | |
1718 | int onstack; /* onstack == 0 => in reg */ | |
1719 | int align; /* alignment */ | |
1720 | union | |
1721 | { | |
581e13c1 MS |
1722 | int offset; /* stack offset if on stack. */ |
1723 | int regno; /* regno if in register. */ | |
ca3bf3bd DJ |
1724 | } u; |
1725 | }; | |
1726 | ||
1727 | struct argument_info *arg_info = | |
1728 | (struct argument_info *) alloca (nargs * sizeof (struct argument_info)); | |
1729 | ||
1730 | CORE_ADDR osp = sp; | |
1731 | ||
1732 | DEBUGTRACE ("xtensa_push_dummy_call (...)\n"); | |
1733 | ||
1734 | if (xtensa_debug_level > 3) | |
1735 | { | |
1736 | int i; | |
1737 | DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs); | |
1738 | DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, " | |
1739 | "struct_addr=0x%x\n", | |
1740 | (int) sp, (int) struct_return, (int) struct_addr); | |
1741 | ||
1742 | for (i = 0; i < nargs; i++) | |
1743 | { | |
1744 | struct value *arg = args[i]; | |
1745 | struct type *arg_type = check_typedef (value_type (arg)); | |
3329c4b5 PM |
1746 | fprintf_unfiltered (gdb_stdlog, "%2d: %s %3d ", i, |
1747 | host_address_to_string (arg), | |
1748 | TYPE_LENGTH (arg_type)); | |
ca3bf3bd DJ |
1749 | switch (TYPE_CODE (arg_type)) |
1750 | { | |
1751 | case TYPE_CODE_INT: | |
1752 | fprintf_unfiltered (gdb_stdlog, "int"); | |
1753 | break; | |
1754 | case TYPE_CODE_STRUCT: | |
1755 | fprintf_unfiltered (gdb_stdlog, "struct"); | |
1756 | break; | |
1757 | default: | |
1758 | fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type)); | |
1759 | break; | |
1760 | } | |
3329c4b5 PM |
1761 | fprintf_unfiltered (gdb_stdlog, " %s\n", |
1762 | host_address_to_string (value_contents (arg))); | |
ca3bf3bd DJ |
1763 | } |
1764 | } | |
1765 | ||
1766 | /* First loop: collect information. | |
1767 | Cast into type_long. (This shouldn't happen often for C because | |
1768 | GDB already does this earlier.) It's possible that GDB could | |
1769 | do it all the time but it's harmless to leave this code here. */ | |
1770 | ||
1771 | size = 0; | |
1772 | onstack_size = 0; | |
1773 | i = 0; | |
1774 | ||
1775 | if (struct_return) | |
1776 | size = REGISTER_SIZE; | |
1777 | ||
1778 | for (i = 0; i < nargs; i++) | |
1779 | { | |
1780 | struct argument_info *info = &arg_info[i]; | |
1781 | struct value *arg = args[i]; | |
1782 | struct type *arg_type = check_typedef (value_type (arg)); | |
1783 | ||
1784 | switch (TYPE_CODE (arg_type)) | |
1785 | { | |
1786 | case TYPE_CODE_INT: | |
1787 | case TYPE_CODE_BOOL: | |
1788 | case TYPE_CODE_CHAR: | |
1789 | case TYPE_CODE_RANGE: | |
1790 | case TYPE_CODE_ENUM: | |
1791 | ||
1792 | /* Cast argument to long if necessary as the mask does it too. */ | |
0dfff4cb UW |
1793 | if (TYPE_LENGTH (arg_type) |
1794 | < TYPE_LENGTH (builtin_type (gdbarch)->builtin_long)) | |
ca3bf3bd | 1795 | { |
0dfff4cb | 1796 | arg_type = builtin_type (gdbarch)->builtin_long; |
ca3bf3bd DJ |
1797 | arg = value_cast (arg_type, arg); |
1798 | } | |
bdb4c075 MG |
1799 | /* Aligment is equal to the type length for the basic types. */ |
1800 | info->align = TYPE_LENGTH (arg_type); | |
ca3bf3bd DJ |
1801 | break; |
1802 | ||
1803 | case TYPE_CODE_FLT: | |
1804 | ||
1805 | /* Align doubles correctly. */ | |
0dfff4cb UW |
1806 | if (TYPE_LENGTH (arg_type) |
1807 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_double)) | |
1808 | info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_double); | |
ca3bf3bd | 1809 | else |
0dfff4cb | 1810 | info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long); |
ca3bf3bd DJ |
1811 | break; |
1812 | ||
1813 | case TYPE_CODE_STRUCT: | |
1814 | default: | |
0dfff4cb | 1815 | info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long); |
ca3bf3bd DJ |
1816 | break; |
1817 | } | |
1818 | info->length = TYPE_LENGTH (arg_type); | |
1819 | info->contents = value_contents (arg); | |
1820 | ||
1821 | /* Align size and onstack_size. */ | |
1822 | size = (size + info->align - 1) & ~(info->align - 1); | |
1823 | onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1); | |
1824 | ||
91d8eb23 | 1825 | if (size + info->length > REGISTER_SIZE * ARG_NOF (gdbarch)) |
ca3bf3bd DJ |
1826 | { |
1827 | info->onstack = 1; | |
1828 | info->u.offset = onstack_size; | |
1829 | onstack_size += info->length; | |
1830 | } | |
1831 | else | |
1832 | { | |
1833 | info->onstack = 0; | |
91d8eb23 | 1834 | info->u.regno = ARG_1ST (gdbarch) + size / REGISTER_SIZE; |
ca3bf3bd DJ |
1835 | } |
1836 | size += info->length; | |
1837 | } | |
1838 | ||
1839 | /* Adjust the stack pointer and align it. */ | |
1840 | sp = align_down (sp - onstack_size, SP_ALIGNMENT); | |
1841 | ||
bdb4c075 | 1842 | /* Simulate MOVSP, if Windowed ABI. */ |
6b50c0b0 | 1843 | if ((gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
304fe255 | 1844 | && (sp != osp)) |
ca3bf3bd DJ |
1845 | { |
1846 | read_memory (osp - 16, buf, 16); | |
1847 | write_memory (sp - 16, buf, 16); | |
1848 | } | |
1849 | ||
1850 | /* Second Loop: Load arguments. */ | |
1851 | ||
1852 | if (struct_return) | |
1853 | { | |
e17a4113 | 1854 | store_unsigned_integer (buf, REGISTER_SIZE, byte_order, struct_addr); |
91d8eb23 | 1855 | regcache_cooked_write (regcache, ARG_1ST (gdbarch), buf); |
ca3bf3bd DJ |
1856 | } |
1857 | ||
1858 | for (i = 0; i < nargs; i++) | |
1859 | { | |
1860 | struct argument_info *info = &arg_info[i]; | |
1861 | ||
1862 | if (info->onstack) | |
1863 | { | |
1864 | int n = info->length; | |
1865 | CORE_ADDR offset = sp + info->u.offset; | |
1866 | ||
1867 | /* Odd-sized structs are aligned to the lower side of a memory | |
1868 | word in big-endian mode and require a shift. This only | |
1869 | applies for structures smaller than one word. */ | |
1870 | ||
4c6b5505 | 1871 | if (n < REGISTER_SIZE |
6b50c0b0 | 1872 | && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1873 | offset += (REGISTER_SIZE - n); |
1874 | ||
1875 | write_memory (offset, info->contents, info->length); | |
1876 | ||
1877 | } | |
1878 | else | |
1879 | { | |
1880 | int n = info->length; | |
1881 | const bfd_byte *cp = info->contents; | |
1882 | int r = info->u.regno; | |
1883 | ||
1884 | /* Odd-sized structs are aligned to the lower side of registers in | |
1885 | big-endian mode and require a shift. The odd-sized leftover will | |
1886 | be at the end. Note that this is only true for structures smaller | |
1887 | than REGISTER_SIZE; for larger odd-sized structures the excess | |
1888 | will be left-aligned in the register on both endiannesses. */ | |
1889 | ||
e17a4113 | 1890 | if (n < REGISTER_SIZE && byte_order == BFD_ENDIAN_BIG) |
ca3bf3bd | 1891 | { |
e17a4113 UW |
1892 | ULONGEST v; |
1893 | v = extract_unsigned_integer (cp, REGISTER_SIZE, byte_order); | |
ca3bf3bd DJ |
1894 | v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT); |
1895 | ||
e17a4113 | 1896 | store_unsigned_integer (buf, REGISTER_SIZE, byte_order, v); |
ca3bf3bd DJ |
1897 | regcache_cooked_write (regcache, r, buf); |
1898 | ||
1899 | cp += REGISTER_SIZE; | |
1900 | n -= REGISTER_SIZE; | |
1901 | r++; | |
1902 | } | |
1903 | else | |
1904 | while (n > 0) | |
1905 | { | |
ca3bf3bd DJ |
1906 | regcache_cooked_write (regcache, r, cp); |
1907 | ||
ca3bf3bd DJ |
1908 | cp += REGISTER_SIZE; |
1909 | n -= REGISTER_SIZE; | |
1910 | r++; | |
1911 | } | |
1912 | } | |
1913 | } | |
1914 | ||
ca3bf3bd | 1915 | /* Set the return address of dummy frame to the dummy address. |
bdb4c075 | 1916 | The return address for the current function (in A0) is |
ca3bf3bd DJ |
1917 | saved in the dummy frame, so we can savely overwrite A0 here. */ |
1918 | ||
6b50c0b0 | 1919 | if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
bdb4c075 | 1920 | { |
98689b25 | 1921 | ULONGEST val; |
68d6df83 | 1922 | |
bdb4c075 | 1923 | ra = (bp_addr & 0x3fffffff) | 0x40000000; |
98689b25 MG |
1924 | regcache_raw_read_unsigned (regcache, gdbarch_ps_regnum (gdbarch), &val); |
1925 | ps = (unsigned long) val & ~0x00030000; | |
304fe255 | 1926 | regcache_cooked_write_unsigned |
6b50c0b0 | 1927 | (regcache, gdbarch_tdep (gdbarch)->a0_base + 4, ra); |
bdb4c075 | 1928 | regcache_cooked_write_unsigned (regcache, |
6b50c0b0 | 1929 | gdbarch_ps_regnum (gdbarch), |
bdb4c075 | 1930 | ps | 0x00010000); |
94a0e877 MG |
1931 | |
1932 | /* All the registers have been saved. After executing | |
1933 | dummy call, they all will be restored. So it's safe | |
1934 | to modify WINDOWSTART register to make it look like there | |
1935 | is only one register window corresponding to WINDOWEBASE. */ | |
1936 | ||
1937 | regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf); | |
e17a4113 UW |
1938 | regcache_cooked_write_unsigned |
1939 | (regcache, gdbarch_tdep (gdbarch)->ws_regnum, | |
1940 | 1 << extract_unsigned_integer (buf, 4, byte_order)); | |
bdb4c075 MG |
1941 | } |
1942 | else | |
1943 | { | |
1944 | /* Simulate CALL0: write RA into A0 register. */ | |
304fe255 | 1945 | regcache_cooked_write_unsigned |
94a0e877 | 1946 | (regcache, gdbarch_tdep (gdbarch)->a0_base, bp_addr); |
bdb4c075 | 1947 | } |
ca3bf3bd DJ |
1948 | |
1949 | /* Set new stack pointer and return it. */ | |
304fe255 | 1950 | regcache_cooked_write_unsigned (regcache, |
6b50c0b0 | 1951 | gdbarch_tdep (gdbarch)->a0_base + 1, sp); |
ca3bf3bd DJ |
1952 | /* Make dummy frame ID unique by adding a constant. */ |
1953 | return sp + SP_ALIGNMENT; | |
1954 | } | |
1955 | ||
cd6c3b4f YQ |
1956 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
1957 | ||
d19280ad YQ |
1958 | static int |
1959 | xtensa_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
1960 | { | |
1961 | if (gdbarch_tdep (gdbarch)->isa_use_density_instructions) | |
1962 | return 2; | |
1963 | else | |
1964 | return 4; | |
1965 | } | |
ca3bf3bd DJ |
1966 | |
1967 | /* Return a breakpoint for the current location of PC. We always use | |
1968 | the density version if we have density instructions (regardless of the | |
1969 | current instruction at PC), and use regular instructions otherwise. */ | |
1970 | ||
1971 | #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 } | |
1972 | #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 } | |
1973 | #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f } | |
1974 | #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 } | |
1975 | ||
cd6c3b4f YQ |
1976 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
1977 | ||
d19280ad YQ |
1978 | static const gdb_byte * |
1979 | xtensa_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
ca3bf3bd | 1980 | { |
d19280ad | 1981 | *size = kind; |
ca3bf3bd | 1982 | |
d19280ad | 1983 | if (kind == 4) |
ca3bf3bd | 1984 | { |
d19280ad YQ |
1985 | static unsigned char big_breakpoint[] = BIG_BREAKPOINT; |
1986 | static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT; | |
1987 | ||
67d57894 | 1988 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d19280ad | 1989 | return big_breakpoint; |
ca3bf3bd | 1990 | else |
d19280ad | 1991 | return little_breakpoint; |
ca3bf3bd DJ |
1992 | } |
1993 | else | |
1994 | { | |
d19280ad YQ |
1995 | static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT; |
1996 | static unsigned char density_little_breakpoint[] | |
1997 | = DENSITY_LITTLE_BREAKPOINT; | |
1998 | ||
67d57894 | 1999 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d19280ad | 2000 | return density_big_breakpoint; |
ca3bf3bd | 2001 | else |
d19280ad | 2002 | return density_little_breakpoint; |
ca3bf3bd DJ |
2003 | } |
2004 | } | |
2005 | ||
bdb4c075 MG |
2006 | /* Call0 ABI support routines. */ |
2007 | ||
f976a05d MG |
2008 | /* Return true, if PC points to "ret" or "ret.n". */ |
2009 | ||
2010 | static int | |
2011 | call0_ret (CORE_ADDR start_pc, CORE_ADDR finish_pc) | |
2012 | { | |
2013 | #define RETURN_RET goto done | |
2014 | xtensa_isa isa; | |
2015 | xtensa_insnbuf ins, slot; | |
948f8e3d | 2016 | gdb_byte ibuf[XTENSA_ISA_BSZ]; |
f976a05d MG |
2017 | CORE_ADDR ia, bt, ba; |
2018 | xtensa_format ifmt; | |
2019 | int ilen, islots, is; | |
2020 | xtensa_opcode opc; | |
2021 | const char *opcname; | |
2022 | int found_ret = 0; | |
2023 | ||
2024 | isa = xtensa_default_isa; | |
2025 | gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); | |
2026 | ins = xtensa_insnbuf_alloc (isa); | |
2027 | slot = xtensa_insnbuf_alloc (isa); | |
2028 | ba = 0; | |
2029 | ||
2030 | for (ia = start_pc, bt = ia; ia < finish_pc ; ia += ilen) | |
2031 | { | |
2032 | if (ia + xtensa_isa_maxlength (isa) > bt) | |
2033 | { | |
2034 | ba = ia; | |
2035 | bt = (ba + XTENSA_ISA_BSZ) < finish_pc | |
2036 | ? ba + XTENSA_ISA_BSZ : finish_pc; | |
2037 | if (target_read_memory (ba, ibuf, bt - ba) != 0 ) | |
2038 | RETURN_RET; | |
2039 | } | |
2040 | ||
2041 | xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); | |
2042 | ifmt = xtensa_format_decode (isa, ins); | |
2043 | if (ifmt == XTENSA_UNDEFINED) | |
2044 | RETURN_RET; | |
2045 | ilen = xtensa_format_length (isa, ifmt); | |
2046 | if (ilen == XTENSA_UNDEFINED) | |
2047 | RETURN_RET; | |
2048 | islots = xtensa_format_num_slots (isa, ifmt); | |
2049 | if (islots == XTENSA_UNDEFINED) | |
2050 | RETURN_RET; | |
2051 | ||
2052 | for (is = 0; is < islots; ++is) | |
2053 | { | |
2054 | if (xtensa_format_get_slot (isa, ifmt, is, ins, slot)) | |
2055 | RETURN_RET; | |
2056 | ||
2057 | opc = xtensa_opcode_decode (isa, ifmt, is, slot); | |
2058 | if (opc == XTENSA_UNDEFINED) | |
2059 | RETURN_RET; | |
2060 | ||
2061 | opcname = xtensa_opcode_name (isa, opc); | |
2062 | ||
2063 | if ((strcasecmp (opcname, "ret.n") == 0) | |
2064 | || (strcasecmp (opcname, "ret") == 0)) | |
2065 | { | |
2066 | found_ret = 1; | |
2067 | RETURN_RET; | |
2068 | } | |
2069 | } | |
2070 | } | |
2071 | done: | |
2072 | xtensa_insnbuf_free(isa, slot); | |
2073 | xtensa_insnbuf_free(isa, ins); | |
2074 | return found_ret; | |
2075 | } | |
2076 | ||
bdb4c075 MG |
2077 | /* Call0 opcode class. Opcodes are preclassified according to what they |
2078 | mean for Call0 prologue analysis, and their number of significant operands. | |
2079 | The purpose of this is to simplify prologue analysis by separating | |
2080 | instruction decoding (libisa) from the semantics of prologue analysis. */ | |
2081 | ||
68d6df83 MG |
2082 | typedef enum |
2083 | { | |
bdb4c075 MG |
2084 | c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */ |
2085 | c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */ | |
2086 | c0opc_flow, /* Flow control insn. */ | |
2087 | c0opc_entry, /* ENTRY indicates non-Call0 prologue. */ | |
2088 | c0opc_break, /* Debugger software breakpoints. */ | |
2089 | c0opc_add, /* Adding two registers. */ | |
2090 | c0opc_addi, /* Adding a register and an immediate. */ | |
dbab50de | 2091 | c0opc_and, /* Bitwise "and"-ing two registers. */ |
bdb4c075 MG |
2092 | c0opc_sub, /* Subtracting a register from a register. */ |
2093 | c0opc_mov, /* Moving a register to a register. */ | |
2094 | c0opc_movi, /* Moving an immediate to a register. */ | |
2095 | c0opc_l32r, /* Loading a literal. */ | |
08b9c608 MG |
2096 | c0opc_s32i, /* Storing word at fixed offset from a base register. */ |
2097 | c0opc_rwxsr, /* RSR, WRS, or XSR instructions. */ | |
2098 | c0opc_l32e, /* L32E instruction. */ | |
2099 | c0opc_s32e, /* S32E instruction. */ | |
2100 | c0opc_rfwo, /* RFWO instruction. */ | |
2101 | c0opc_rfwu, /* RFWU instruction. */ | |
bdb4c075 MG |
2102 | c0opc_NrOf /* Number of opcode classifications. */ |
2103 | } xtensa_insn_kind; | |
2104 | ||
08b9c608 MG |
2105 | /* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */ |
2106 | ||
2107 | static int | |
2108 | rwx_special_register (const char *opcname) | |
2109 | { | |
2110 | char ch = *opcname++; | |
2111 | ||
2112 | if ((ch != 'r') && (ch != 'w') && (ch != 'x')) | |
2113 | return 0; | |
2114 | if (*opcname++ != 's') | |
2115 | return 0; | |
2116 | if (*opcname++ != 'r') | |
2117 | return 0; | |
2118 | if (*opcname++ != '.') | |
2119 | return 0; | |
2120 | ||
2121 | return 1; | |
2122 | } | |
bdb4c075 MG |
2123 | |
2124 | /* Classify an opcode based on what it means for Call0 prologue analysis. */ | |
2125 | ||
2126 | static xtensa_insn_kind | |
2127 | call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc) | |
2128 | { | |
2129 | const char *opcname; | |
2130 | xtensa_insn_kind opclass = c0opc_uninteresting; | |
2131 | ||
2132 | DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc); | |
2133 | ||
2134 | /* Get opcode name and handle special classifications. */ | |
2135 | ||
2136 | opcname = xtensa_opcode_name (isa, opc); | |
2137 | ||
2138 | if (opcname == NULL | |
2139 | || strcasecmp (opcname, "ill") == 0 | |
2140 | || strcasecmp (opcname, "ill.n") == 0) | |
2141 | opclass = c0opc_illegal; | |
2142 | else if (strcasecmp (opcname, "break") == 0 | |
2143 | || strcasecmp (opcname, "break.n") == 0) | |
2144 | opclass = c0opc_break; | |
2145 | else if (strcasecmp (opcname, "entry") == 0) | |
2146 | opclass = c0opc_entry; | |
08b9c608 MG |
2147 | else if (strcasecmp (opcname, "rfwo") == 0) |
2148 | opclass = c0opc_rfwo; | |
2149 | else if (strcasecmp (opcname, "rfwu") == 0) | |
2150 | opclass = c0opc_rfwu; | |
bdb4c075 MG |
2151 | else if (xtensa_opcode_is_branch (isa, opc) > 0 |
2152 | || xtensa_opcode_is_jump (isa, opc) > 0 | |
2153 | || xtensa_opcode_is_loop (isa, opc) > 0 | |
2154 | || xtensa_opcode_is_call (isa, opc) > 0 | |
2155 | || strcasecmp (opcname, "simcall") == 0 | |
2156 | || strcasecmp (opcname, "syscall") == 0) | |
2157 | opclass = c0opc_flow; | |
2158 | ||
2159 | /* Also, classify specific opcodes that need to be tracked. */ | |
2160 | else if (strcasecmp (opcname, "add") == 0 | |
2161 | || strcasecmp (opcname, "add.n") == 0) | |
2162 | opclass = c0opc_add; | |
dbab50de MG |
2163 | else if (strcasecmp (opcname, "and") == 0) |
2164 | opclass = c0opc_and; | |
bdb4c075 MG |
2165 | else if (strcasecmp (opcname, "addi") == 0 |
2166 | || strcasecmp (opcname, "addi.n") == 0 | |
2167 | || strcasecmp (opcname, "addmi") == 0) | |
2168 | opclass = c0opc_addi; | |
2169 | else if (strcasecmp (opcname, "sub") == 0) | |
2170 | opclass = c0opc_sub; | |
2171 | else if (strcasecmp (opcname, "mov.n") == 0 | |
2172 | || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */ | |
2173 | opclass = c0opc_mov; | |
2174 | else if (strcasecmp (opcname, "movi") == 0 | |
2175 | || strcasecmp (opcname, "movi.n") == 0) | |
2176 | opclass = c0opc_movi; | |
2177 | else if (strcasecmp (opcname, "l32r") == 0) | |
2178 | opclass = c0opc_l32r; | |
2179 | else if (strcasecmp (opcname, "s32i") == 0 | |
2180 | || strcasecmp (opcname, "s32i.n") == 0) | |
2181 | opclass = c0opc_s32i; | |
08b9c608 MG |
2182 | else if (strcasecmp (opcname, "l32e") == 0) |
2183 | opclass = c0opc_l32e; | |
2184 | else if (strcasecmp (opcname, "s32e") == 0) | |
2185 | opclass = c0opc_s32e; | |
2186 | else if (rwx_special_register (opcname)) | |
2187 | opclass = c0opc_rwxsr; | |
bdb4c075 MG |
2188 | |
2189 | return opclass; | |
2190 | } | |
2191 | ||
2192 | /* Tracks register movement/mutation for a given operation, which may | |
2193 | be within a bundle. Updates the destination register tracking info | |
2194 | accordingly. The pc is needed only for pc-relative load instructions | |
2195 | (eg. l32r). The SP register number is needed to identify stores to | |
dbab50de MG |
2196 | the stack frame. Returns 0, if analysis was succesfull, non-zero |
2197 | otherwise. */ | |
bdb4c075 | 2198 | |
dbab50de MG |
2199 | static int |
2200 | call0_track_op (struct gdbarch *gdbarch, xtensa_c0reg_t dst[], xtensa_c0reg_t src[], | |
bdb4c075 | 2201 | xtensa_insn_kind opclass, int nods, unsigned odv[], |
dbab50de | 2202 | CORE_ADDR pc, int spreg, xtensa_frame_cache_t *cache) |
bdb4c075 | 2203 | { |
e17a4113 | 2204 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
dbab50de | 2205 | unsigned litbase, litaddr, litval; |
bdb4c075 MG |
2206 | |
2207 | switch (opclass) | |
2208 | { | |
2209 | case c0opc_addi: | |
2210 | /* 3 operands: dst, src, imm. */ | |
2211 | gdb_assert (nods == 3); | |
2212 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
2213 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2]; | |
2214 | break; | |
2215 | case c0opc_add: | |
2216 | /* 3 operands: dst, src1, src2. */ | |
08b9c608 | 2217 | gdb_assert (nods == 3); |
bdb4c075 MG |
2218 | if (src[odv[1]].fr_reg == C0_CONST) |
2219 | { | |
2220 | dst[odv[0]].fr_reg = src[odv[2]].fr_reg; | |
2221 | dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs; | |
2222 | } | |
2223 | else if (src[odv[2]].fr_reg == C0_CONST) | |
2224 | { | |
2225 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
2226 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs; | |
2227 | } | |
2228 | else dst[odv[0]].fr_reg = C0_INEXP; | |
2229 | break; | |
dbab50de MG |
2230 | case c0opc_and: |
2231 | /* 3 operands: dst, src1, src2. */ | |
2232 | gdb_assert (nods == 3); | |
2233 | if (cache->c0.c0_fpalign == 0) | |
2234 | { | |
2235 | /* Handle dynamic stack alignment. */ | |
2236 | if ((src[odv[0]].fr_reg == spreg) && (src[odv[1]].fr_reg == spreg)) | |
2237 | { | |
2238 | if (src[odv[2]].fr_reg == C0_CONST) | |
2239 | cache->c0.c0_fpalign = src[odv[2]].fr_ofs; | |
2240 | break; | |
2241 | } | |
2242 | else if ((src[odv[0]].fr_reg == spreg) | |
2243 | && (src[odv[2]].fr_reg == spreg)) | |
2244 | { | |
2245 | if (src[odv[1]].fr_reg == C0_CONST) | |
2246 | cache->c0.c0_fpalign = src[odv[1]].fr_ofs; | |
2247 | break; | |
2248 | } | |
2249 | /* else fall through. */ | |
2250 | } | |
2251 | if (src[odv[1]].fr_reg == C0_CONST) | |
2252 | { | |
2253 | dst[odv[0]].fr_reg = src[odv[2]].fr_reg; | |
2254 | dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs & src[odv[1]].fr_ofs; | |
2255 | } | |
2256 | else if (src[odv[2]].fr_reg == C0_CONST) | |
2257 | { | |
2258 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
2259 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs & src[odv[2]].fr_ofs; | |
2260 | } | |
2261 | else dst[odv[0]].fr_reg = C0_INEXP; | |
2262 | break; | |
bdb4c075 MG |
2263 | case c0opc_sub: |
2264 | /* 3 operands: dst, src1, src2. */ | |
2265 | gdb_assert (nods == 3); | |
2266 | if (src[odv[2]].fr_reg == C0_CONST) | |
2267 | { | |
2268 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
2269 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs; | |
2270 | } | |
2271 | else dst[odv[0]].fr_reg = C0_INEXP; | |
2272 | break; | |
2273 | case c0opc_mov: | |
2274 | /* 2 operands: dst, src [, src]. */ | |
2275 | gdb_assert (nods == 2); | |
dbab50de MG |
2276 | /* First, check if it's a special case of saving unaligned SP |
2277 | to a spare register in case of dynamic stack adjustment. | |
2278 | But, only do it one time. The second time could be initializing | |
2279 | frame pointer. We don't want to overwrite the first one. */ | |
2280 | if ((odv[1] == spreg) && (cache->c0.c0_old_sp == C0_INEXP)) | |
2281 | cache->c0.c0_old_sp = odv[0]; | |
2282 | ||
bdb4c075 MG |
2283 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; |
2284 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs; | |
2285 | break; | |
2286 | case c0opc_movi: | |
2287 | /* 2 operands: dst, imm. */ | |
2288 | gdb_assert (nods == 2); | |
2289 | dst[odv[0]].fr_reg = C0_CONST; | |
2290 | dst[odv[0]].fr_ofs = odv[1]; | |
2291 | break; | |
2292 | case c0opc_l32r: | |
2293 | /* 2 operands: dst, literal offset. */ | |
2294 | gdb_assert (nods == 2); | |
dbab50de MG |
2295 | /* litbase = xtensa_get_litbase (pc); can be also used. */ |
2296 | litbase = (gdbarch_tdep (gdbarch)->litbase_regnum == -1) | |
2297 | ? 0 : xtensa_read_register | |
2298 | (gdbarch_tdep (gdbarch)->litbase_regnum); | |
bdb4c075 MG |
2299 | litaddr = litbase & 1 |
2300 | ? (litbase & ~1) + (signed)odv[1] | |
2301 | : (pc + 3 + (signed)odv[1]) & ~3; | |
e17a4113 | 2302 | litval = read_memory_integer (litaddr, 4, byte_order); |
bdb4c075 MG |
2303 | dst[odv[0]].fr_reg = C0_CONST; |
2304 | dst[odv[0]].fr_ofs = litval; | |
2305 | break; | |
2306 | case c0opc_s32i: | |
2307 | /* 3 operands: value, base, offset. */ | |
2308 | gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS); | |
dbab50de MG |
2309 | /* First, check if it's a spill for saved unaligned SP, |
2310 | when dynamic stack adjustment was applied to this frame. */ | |
2311 | if ((cache->c0.c0_fpalign != 0) /* Dynamic stack adjustment. */ | |
2312 | && (odv[1] == spreg) /* SP usage indicates spill. */ | |
2313 | && (odv[0] == cache->c0.c0_old_sp)) /* Old SP register spilled. */ | |
2314 | cache->c0.c0_sp_ofs = odv[2]; | |
2315 | ||
bdb4c075 MG |
2316 | if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */ |
2317 | && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */ | |
2318 | && src[odv[0]].fr_reg >= 0 /* Value is from a register. */ | |
2319 | && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */ | |
2320 | && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */ | |
2321 | { | |
2322 | /* ISA encoding guarantees alignment. But, check it anyway. */ | |
2323 | gdb_assert ((odv[2] & 3) == 0); | |
2324 | dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2]; | |
2325 | } | |
2326 | break; | |
dbab50de MG |
2327 | /* If we end up inside Window Overflow / Underflow interrupt handler |
2328 | report an error because these handlers should have been handled | |
2329 | already in a different way. */ | |
2330 | case c0opc_l32e: | |
2331 | case c0opc_s32e: | |
2332 | case c0opc_rfwo: | |
2333 | case c0opc_rfwu: | |
2334 | return 1; | |
bdb4c075 | 2335 | default: |
dbab50de | 2336 | return 1; |
bdb4c075 | 2337 | } |
dbab50de | 2338 | return 0; |
bdb4c075 MG |
2339 | } |
2340 | ||
dbab50de | 2341 | /* Analyze prologue of the function at start address to determine if it uses |
bdb4c075 | 2342 | the Call0 ABI, and if so track register moves and linear modifications |
dbab50de MG |
2343 | in the prologue up to the PC or just beyond the prologue, whichever is |
2344 | first. An 'entry' instruction indicates non-Call0 ABI and the end of the | |
2345 | prologue. The prologue may overlap non-prologue instructions but is | |
2346 | guaranteed to end by the first flow-control instruction (jump, branch, | |
2347 | call or return). Since an optimized function may move information around | |
2348 | and change the stack frame arbitrarily during the prologue, the information | |
2349 | is guaranteed valid only at the point in the function indicated by the PC. | |
bdb4c075 MG |
2350 | May be used to skip the prologue or identify the ABI, w/o tracking. |
2351 | ||
2352 | Returns: Address of first instruction after prologue, or PC (whichever | |
2353 | is first), or 0, if decoding failed (in libisa). | |
2354 | Input args: | |
2355 | start Start address of function/prologue. | |
2356 | pc Program counter to stop at. Use 0 to continue to end of prologue. | |
2357 | If 0, avoids infinite run-on in corrupt code memory by bounding | |
2358 | the scan to the end of the function if that can be determined. | |
dbab50de | 2359 | nregs Number of general registers to track. |
bdb4c075 | 2360 | InOut args: |
dbab50de | 2361 | cache Xtensa frame cache. |
bdb4c075 MG |
2362 | |
2363 | Note that these may produce useful results even if decoding fails | |
2364 | because they begin with default assumptions that analysis may change. */ | |
2365 | ||
2366 | static CORE_ADDR | |
e17a4113 | 2367 | call0_analyze_prologue (struct gdbarch *gdbarch, |
dbab50de MG |
2368 | CORE_ADDR start, CORE_ADDR pc, |
2369 | int nregs, xtensa_frame_cache_t *cache) | |
bdb4c075 MG |
2370 | { |
2371 | CORE_ADDR ia; /* Current insn address in prologue. */ | |
2372 | CORE_ADDR ba = 0; /* Current address at base of insn buffer. */ | |
2373 | CORE_ADDR bt; /* Current address at top+1 of insn buffer. */ | |
948f8e3d | 2374 | gdb_byte ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue. */ |
bdb4c075 MG |
2375 | xtensa_isa isa; /* libisa ISA handle. */ |
2376 | xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */ | |
2377 | xtensa_format ifmt; /* libisa instruction format. */ | |
2378 | int ilen, islots, is; /* Instruction length, nbr slots, current slot. */ | |
2379 | xtensa_opcode opc; /* Opcode in current slot. */ | |
2380 | xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */ | |
2381 | int nods; /* Opcode number of operands. */ | |
2382 | unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */ | |
2383 | xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */ | |
2384 | int j; /* General loop counter. */ | |
2385 | int fail = 0; /* Set non-zero and exit, if decoding fails. */ | |
2386 | CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */ | |
2387 | CORE_ADDR end_pc; /* The PC for the lust function insn. */ | |
2388 | ||
2389 | struct symtab_and_line prologue_sal; | |
2390 | ||
2391 | DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n", | |
2392 | (int)start, (int)pc); | |
2393 | ||
2394 | /* Try to limit the scan to the end of the function if a non-zero pc | |
2395 | arg was not supplied to avoid probing beyond the end of valid memory. | |
2396 | If memory is full of garbage that classifies as c0opc_uninteresting. | |
2397 | If this fails (eg. if no symbols) pc ends up 0 as it was. | |
26c4b26f | 2398 | Initialize the Call0 frame and register tracking info. |
bdb4c075 MG |
2399 | Assume it's Call0 until an 'entry' instruction is encountered. |
2400 | Assume we may be in the prologue until we hit a flow control instr. */ | |
2401 | ||
2402 | rtmp = NULL; | |
8179e739 | 2403 | body_pc = UINT_MAX; |
bdb4c075 MG |
2404 | end_pc = 0; |
2405 | ||
2406 | /* Find out, if we have an information about the prologue from DWARF. */ | |
2407 | prologue_sal = find_pc_line (start, 0); | |
2408 | if (prologue_sal.line != 0) /* Found debug info. */ | |
2409 | body_pc = prologue_sal.end; | |
2410 | ||
2411 | /* If we are going to analyze the prologue in general without knowing about | |
2412 | the current PC, make the best assumtion for the end of the prologue. */ | |
2413 | if (pc == 0) | |
2414 | { | |
2415 | find_pc_partial_function (start, 0, NULL, &end_pc); | |
325fac50 | 2416 | body_pc = std::min (end_pc, body_pc); |
bdb4c075 MG |
2417 | } |
2418 | else | |
325fac50 | 2419 | body_pc = std::min (pc, body_pc); |
bdb4c075 | 2420 | |
dbab50de MG |
2421 | cache->call0 = 1; |
2422 | rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t)); | |
bdb4c075 MG |
2423 | |
2424 | isa = xtensa_default_isa; | |
2ff5e605 | 2425 | gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); |
bdb4c075 MG |
2426 | ins = xtensa_insnbuf_alloc (isa); |
2427 | slot = xtensa_insnbuf_alloc (isa); | |
2428 | ||
2429 | for (ia = start, bt = ia; ia < body_pc ; ia += ilen) | |
2430 | { | |
2431 | /* (Re)fill instruction buffer from memory if necessary, but do not | |
2432 | read memory beyond PC to be sure we stay within text section | |
2433 | (this protection only works if a non-zero pc is supplied). */ | |
2434 | ||
2435 | if (ia + xtensa_isa_maxlength (isa) > bt) | |
2436 | { | |
2437 | ba = ia; | |
2ff5e605 | 2438 | bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ : body_pc; |
dbab50de MG |
2439 | if (target_read_memory (ba, ibuf, bt - ba) != 0 ) |
2440 | error (_("Unable to read target memory ...")); | |
bdb4c075 MG |
2441 | } |
2442 | ||
2443 | /* Decode format information. */ | |
2444 | ||
2445 | xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); | |
2446 | ifmt = xtensa_format_decode (isa, ins); | |
2447 | if (ifmt == XTENSA_UNDEFINED) | |
2448 | { | |
2449 | fail = 1; | |
2450 | goto done; | |
2451 | } | |
2452 | ilen = xtensa_format_length (isa, ifmt); | |
2453 | if (ilen == XTENSA_UNDEFINED) | |
2454 | { | |
2455 | fail = 1; | |
2456 | goto done; | |
2457 | } | |
2458 | islots = xtensa_format_num_slots (isa, ifmt); | |
2459 | if (islots == XTENSA_UNDEFINED) | |
2460 | { | |
2461 | fail = 1; | |
2462 | goto done; | |
2463 | } | |
2464 | ||
2465 | /* Analyze a bundle or a single instruction, using a snapshot of | |
2466 | the register tracking info as input for the entire bundle so that | |
2467 | register changes do not take effect within this bundle. */ | |
ca3bf3bd | 2468 | |
bdb4c075 | 2469 | for (j = 0; j < nregs; ++j) |
dbab50de | 2470 | rtmp[j] = cache->c0.c0_rt[j]; |
bdb4c075 MG |
2471 | |
2472 | for (is = 0; is < islots; ++is) | |
2473 | { | |
2474 | /* Decode a slot and classify the opcode. */ | |
2475 | ||
2476 | fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot); | |
2477 | if (fail) | |
2478 | goto done; | |
2479 | ||
2480 | opc = xtensa_opcode_decode (isa, ifmt, is, slot); | |
dbab50de | 2481 | DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n", |
bdb4c075 MG |
2482 | (unsigned)ia, opc); |
2483 | if (opc == XTENSA_UNDEFINED) | |
2484 | opclass = c0opc_illegal; | |
2485 | else | |
2486 | opclass = call0_classify_opcode (isa, opc); | |
2487 | ||
2488 | /* Decide whether to track this opcode, ignore it, or bail out. */ | |
2489 | ||
2490 | switch (opclass) | |
2491 | { | |
2492 | case c0opc_illegal: | |
2493 | case c0opc_break: | |
2494 | fail = 1; | |
2495 | goto done; | |
2496 | ||
2497 | case c0opc_uninteresting: | |
2498 | continue; | |
2499 | ||
dbab50de MG |
2500 | case c0opc_flow: /* Flow control instructions stop analysis. */ |
2501 | case c0opc_rwxsr: /* RSR, WSR, XSR instructions stop analysis. */ | |
bdb4c075 MG |
2502 | goto done; |
2503 | ||
2504 | case c0opc_entry: | |
dbab50de | 2505 | cache->call0 = 0; |
bdb4c075 MG |
2506 | ia += ilen; /* Skip over 'entry' insn. */ |
2507 | goto done; | |
2508 | ||
2509 | default: | |
dbab50de | 2510 | cache->call0 = 1; |
bdb4c075 MG |
2511 | } |
2512 | ||
2513 | /* Only expected opcodes should get this far. */ | |
bdb4c075 MG |
2514 | |
2515 | /* Extract and decode the operands. */ | |
2516 | nods = xtensa_opcode_num_operands (isa, opc); | |
2517 | if (nods == XTENSA_UNDEFINED) | |
2518 | { | |
2519 | fail = 1; | |
2520 | goto done; | |
2521 | } | |
2522 | ||
2523 | for (j = 0; j < nods && j < C0_MAXOPDS; ++j) | |
2524 | { | |
2525 | fail = xtensa_operand_get_field (isa, opc, j, ifmt, | |
2526 | is, slot, &odv[j]); | |
2527 | if (fail) | |
2528 | goto done; | |
2529 | ||
2530 | fail = xtensa_operand_decode (isa, opc, j, &odv[j]); | |
2531 | if (fail) | |
2532 | goto done; | |
2533 | } | |
2534 | ||
2535 | /* Check operands to verify use of 'mov' assembler macro. */ | |
2536 | if (opclass == c0opc_mov && nods == 3) | |
2537 | { | |
2538 | if (odv[2] == odv[1]) | |
dbab50de MG |
2539 | { |
2540 | nods = 2; | |
2541 | if ((odv[0] == 1) && (odv[1] != 1)) | |
2542 | /* OR A1, An, An , where n != 1. | |
2543 | This means we are inside epilogue already. */ | |
2544 | goto done; | |
2545 | } | |
bdb4c075 MG |
2546 | else |
2547 | { | |
2548 | opclass = c0opc_uninteresting; | |
2549 | continue; | |
2550 | } | |
2551 | } | |
2552 | ||
2553 | /* Track register movement and modification for this operation. */ | |
dbab50de MG |
2554 | fail = call0_track_op (gdbarch, cache->c0.c0_rt, rtmp, |
2555 | opclass, nods, odv, ia, 1, cache); | |
2556 | if (fail) | |
2557 | goto done; | |
bdb4c075 MG |
2558 | } |
2559 | } | |
2560 | done: | |
2561 | DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n", | |
2562 | (unsigned)ia, fail ? "failed" : "succeeded"); | |
2563 | xtensa_insnbuf_free(isa, slot); | |
2564 | xtensa_insnbuf_free(isa, ins); | |
d4709618 | 2565 | return fail ? XTENSA_ISA_BADPC : ia; |
bdb4c075 MG |
2566 | } |
2567 | ||
5142f611 | 2568 | /* Initialize frame cache for the current frame in CALL0 ABI. */ |
bdb4c075 MG |
2569 | |
2570 | static void | |
5142f611 | 2571 | call0_frame_cache (struct frame_info *this_frame, |
dbab50de | 2572 | xtensa_frame_cache_t *cache, CORE_ADDR pc) |
bdb4c075 | 2573 | { |
5142f611 | 2574 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
e17a4113 | 2575 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
bdb4c075 MG |
2576 | CORE_ADDR start_pc; /* The beginning of the function. */ |
2577 | CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */ | |
2578 | CORE_ADDR sp, fp, ra; | |
dbab50de | 2579 | int fp_regnum = C0_SP, c0_hasfp = 0, c0_frmsz = 0, prev_sp = 0, to_stk; |
bdb4c075 | 2580 | |
dbab50de MG |
2581 | sp = get_frame_register_unsigned |
2582 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1); | |
2583 | fp = sp; /* Assume FP == SP until proven otherwise. */ | |
2584 | ||
bdb4c075 MG |
2585 | /* Find the beginning of the prologue of the function containing the PC |
2586 | and analyze it up to the PC or the end of the prologue. */ | |
2587 | ||
2588 | if (find_pc_partial_function (pc, NULL, &start_pc, NULL)) | |
2589 | { | |
dbab50de | 2590 | body_pc = call0_analyze_prologue (gdbarch, start_pc, pc, C0_NREGS, cache); |
d4709618 MG |
2591 | |
2592 | if (body_pc == XTENSA_ISA_BADPC) | |
dbab50de MG |
2593 | { |
2594 | warning_once (); | |
2595 | ra = 0; | |
2596 | goto finish_frame_analysis; | |
2597 | } | |
bdb4c075 MG |
2598 | } |
2599 | ||
bdb4c075 MG |
2600 | /* Get the frame information and FP (if used) at the current PC. |
2601 | If PC is in the prologue, the prologue analysis is more reliable | |
dbab50de MG |
2602 | than DWARF info. We don't not know for sure, if PC is in the prologue, |
2603 | but we do know no calls have yet taken place, so we can almost | |
bdb4c075 MG |
2604 | certainly rely on the prologue analysis. */ |
2605 | ||
2606 | if (body_pc <= pc) | |
2607 | { | |
2608 | /* Prologue analysis was successful up to the PC. | |
2609 | It includes the cases when PC == START_PC. */ | |
2610 | c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP; | |
2611 | /* c0_hasfp == true means there is a frame pointer because | |
2612 | we analyzed the prologue and found that cache->c0.c0_rt[C0_FP] | |
2613 | was derived from SP. Otherwise, it would be C0_FP. */ | |
2614 | fp_regnum = c0_hasfp ? C0_FP : C0_SP; | |
2615 | c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs; | |
6b50c0b0 | 2616 | fp_regnum += gdbarch_tdep (gdbarch)->a0_base; |
bdb4c075 MG |
2617 | } |
2618 | else /* No data from the prologue analysis. */ | |
2619 | { | |
2620 | c0_hasfp = 0; | |
6b50c0b0 | 2621 | fp_regnum = gdbarch_tdep (gdbarch)->a0_base + C0_SP; |
bdb4c075 MG |
2622 | c0_frmsz = 0; |
2623 | start_pc = pc; | |
2624 | } | |
2625 | ||
dbab50de MG |
2626 | if (cache->c0.c0_fpalign) |
2627 | { | |
2628 | /* This frame has a special prologue with a dynamic stack adjustment | |
2629 | to force an alignment, which is bigger than standard 16 bytes. */ | |
2630 | ||
2631 | CORE_ADDR unaligned_sp; | |
2632 | ||
2633 | if (cache->c0.c0_old_sp == C0_INEXP) | |
2634 | /* This can't be. Prologue code should be consistent. | |
2635 | Unaligned stack pointer should be saved in a spare register. */ | |
2636 | { | |
2637 | warning_once (); | |
2638 | ra = 0; | |
2639 | goto finish_frame_analysis; | |
2640 | } | |
2641 | ||
2642 | if (cache->c0.c0_sp_ofs == C0_NOSTK) | |
2643 | /* Saved unaligned value of SP is kept in a register. */ | |
2644 | unaligned_sp = get_frame_register_unsigned | |
2645 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_old_sp); | |
2646 | else | |
2647 | /* Get the value from stack. */ | |
2648 | unaligned_sp = (CORE_ADDR) | |
2649 | read_memory_integer (fp + cache->c0.c0_sp_ofs, 4, byte_order); | |
2650 | ||
2651 | prev_sp = unaligned_sp + c0_frmsz; | |
2652 | } | |
2653 | else | |
2654 | prev_sp = fp + c0_frmsz; | |
bdb4c075 MG |
2655 | |
2656 | /* Frame size from debug info or prologue tracking does not account for | |
2657 | alloca() and other dynamic allocations. Adjust frame size by FP - SP. */ | |
2658 | if (c0_hasfp) | |
2659 | { | |
5142f611 | 2660 | fp = get_frame_register_unsigned (this_frame, fp_regnum); |
bdb4c075 | 2661 | |
bdb4c075 MG |
2662 | /* Update the stack frame size. */ |
2663 | c0_frmsz += fp - sp; | |
2664 | } | |
2665 | ||
2666 | /* Get the return address (RA) from the stack if saved, | |
2667 | or try to get it from a register. */ | |
2668 | ||
2669 | to_stk = cache->c0.c0_rt[C0_RA].to_stk; | |
2670 | if (to_stk != C0_NOSTK) | |
2671 | ra = (CORE_ADDR) | |
e17a4113 UW |
2672 | read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk, |
2673 | 4, byte_order); | |
bdb4c075 MG |
2674 | |
2675 | else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST | |
2676 | && cache->c0.c0_rt[C0_RA].fr_ofs == 0) | |
2677 | { | |
dbab50de MG |
2678 | /* Special case for terminating backtrace at a function that wants to |
2679 | be seen as the outermost one. Such a function will clear it's RA (A0) | |
2680 | register to 0 in the prologue instead of saving its original value. */ | |
bdb4c075 MG |
2681 | ra = 0; |
2682 | } | |
2683 | else | |
2684 | { | |
dbab50de MG |
2685 | /* RA was copied to another register or (before any function call) may |
2686 | still be in the original RA register. This is not always reliable: | |
2687 | even in a leaf function, register tracking stops after prologue, and | |
2688 | even in prologue, non-prologue instructions (not tracked) may overwrite | |
2689 | RA or any register it was copied to. If likely in prologue or before | |
2690 | any call, use retracking info and hope for the best (compiler should | |
2691 | have saved RA in stack if not in a leaf function). If not in prologue, | |
2692 | too bad. */ | |
bdb4c075 MG |
2693 | |
2694 | int i; | |
1448a0a2 PM |
2695 | for (i = 0; |
2696 | (i < C0_NREGS) | |
2697 | && (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA); | |
bdb4c075 MG |
2698 | ++i); |
2699 | if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA) | |
2700 | i = C0_RA; | |
5142f611 | 2701 | if (i < C0_NREGS) |
bdb4c075 | 2702 | { |
5142f611 MG |
2703 | ra = get_frame_register_unsigned |
2704 | (this_frame, | |
2705 | gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_rt[i].fr_reg); | |
bdb4c075 MG |
2706 | } |
2707 | else ra = 0; | |
2708 | } | |
2709 | ||
dbab50de | 2710 | finish_frame_analysis: |
bdb4c075 MG |
2711 | cache->pc = start_pc; |
2712 | cache->ra = ra; | |
2713 | /* RA == 0 marks the outermost frame. Do not go past it. */ | |
2714 | cache->prev_sp = (ra != 0) ? prev_sp : 0; | |
2715 | cache->c0.fp_regnum = fp_regnum; | |
2716 | cache->c0.c0_frmsz = c0_frmsz; | |
2717 | cache->c0.c0_hasfp = c0_hasfp; | |
2718 | cache->c0.c0_fp = fp; | |
2719 | } | |
2720 | ||
08b9c608 MG |
2721 | static CORE_ADDR a0_saved; |
2722 | static CORE_ADDR a7_saved; | |
2723 | static CORE_ADDR a11_saved; | |
2724 | static int a0_was_saved; | |
2725 | static int a7_was_saved; | |
2726 | static int a11_was_saved; | |
2727 | ||
68d6df83 | 2728 | /* Simulate L32E instruction: AT <-- ref (AS + offset). */ |
08b9c608 MG |
2729 | static void |
2730 | execute_l32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb) | |
2731 | { | |
2732 | int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb); | |
2733 | int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb); | |
2734 | CORE_ADDR addr = xtensa_read_register (asreg) + offset; | |
2735 | unsigned int spilled_value | |
2736 | = read_memory_unsigned_integer (addr, 4, gdbarch_byte_order (gdbarch)); | |
2737 | ||
2738 | if ((at == 0) && !a0_was_saved) | |
2739 | { | |
2740 | a0_saved = xtensa_read_register (atreg); | |
2741 | a0_was_saved = 1; | |
2742 | } | |
2743 | else if ((at == 7) && !a7_was_saved) | |
2744 | { | |
2745 | a7_saved = xtensa_read_register (atreg); | |
2746 | a7_was_saved = 1; | |
2747 | } | |
2748 | else if ((at == 11) && !a11_was_saved) | |
2749 | { | |
2750 | a11_saved = xtensa_read_register (atreg); | |
2751 | a11_was_saved = 1; | |
2752 | } | |
2753 | ||
2754 | xtensa_write_register (atreg, spilled_value); | |
2755 | } | |
2756 | ||
68d6df83 | 2757 | /* Simulate S32E instruction: AT --> ref (AS + offset). */ |
08b9c608 MG |
2758 | static void |
2759 | execute_s32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb) | |
2760 | { | |
2761 | int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb); | |
2762 | int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb); | |
2763 | CORE_ADDR addr = xtensa_read_register (asreg) + offset; | |
2764 | ULONGEST spilled_value = xtensa_read_register (atreg); | |
2765 | ||
2766 | write_memory_unsigned_integer (addr, 4, | |
2767 | gdbarch_byte_order (gdbarch), | |
2768 | spilled_value); | |
2769 | } | |
2770 | ||
2771 | #define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200 | |
2772 | ||
68d6df83 MG |
2773 | typedef enum |
2774 | { | |
08b9c608 MG |
2775 | xtWindowOverflow, |
2776 | xtWindowUnderflow, | |
2777 | xtNoExceptionHandler | |
2778 | } xtensa_exception_handler_t; | |
2779 | ||
68d6df83 | 2780 | /* Execute instruction stream from current PC until hitting RFWU or RFWO. |
08b9c608 MG |
2781 | Return type of Xtensa Window Interrupt Handler on success. */ |
2782 | static xtensa_exception_handler_t | |
2783 | execute_code (struct gdbarch *gdbarch, CORE_ADDR current_pc, CORE_ADDR wb) | |
2784 | { | |
2785 | xtensa_isa isa; | |
2786 | xtensa_insnbuf ins, slot; | |
948f8e3d | 2787 | gdb_byte ibuf[XTENSA_ISA_BSZ]; |
08b9c608 MG |
2788 | CORE_ADDR ia, bt, ba; |
2789 | xtensa_format ifmt; | |
2790 | int ilen, islots, is; | |
2791 | xtensa_opcode opc; | |
2792 | int insn_num = 0; | |
08b9c608 MG |
2793 | void (*func) (struct gdbarch *, int, int, int, CORE_ADDR); |
2794 | ||
19afdd07 | 2795 | uint32_t at, as, offset; |
08b9c608 MG |
2796 | |
2797 | /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */ | |
2798 | int WindowUnderflow12 = (current_pc & 0x1ff) >= 0x140; | |
2799 | ||
2800 | isa = xtensa_default_isa; | |
2801 | gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); | |
2802 | ins = xtensa_insnbuf_alloc (isa); | |
2803 | slot = xtensa_insnbuf_alloc (isa); | |
2804 | ba = 0; | |
2805 | ia = current_pc; | |
2806 | bt = ia; | |
2807 | ||
2808 | a0_was_saved = 0; | |
2809 | a7_was_saved = 0; | |
2810 | a11_was_saved = 0; | |
2811 | ||
2812 | while (insn_num++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN) | |
2813 | { | |
2814 | if (ia + xtensa_isa_maxlength (isa) > bt) | |
2815 | { | |
2816 | ba = ia; | |
2817 | bt = (ba + XTENSA_ISA_BSZ); | |
2818 | if (target_read_memory (ba, ibuf, bt - ba) != 0) | |
2819 | return xtNoExceptionHandler; | |
2820 | } | |
2821 | xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); | |
2822 | ifmt = xtensa_format_decode (isa, ins); | |
2823 | if (ifmt == XTENSA_UNDEFINED) | |
2824 | return xtNoExceptionHandler; | |
2825 | ilen = xtensa_format_length (isa, ifmt); | |
2826 | if (ilen == XTENSA_UNDEFINED) | |
2827 | return xtNoExceptionHandler; | |
2828 | islots = xtensa_format_num_slots (isa, ifmt); | |
2829 | if (islots == XTENSA_UNDEFINED) | |
2830 | return xtNoExceptionHandler; | |
2831 | for (is = 0; is < islots; ++is) | |
2832 | { | |
2833 | if (xtensa_format_get_slot (isa, ifmt, is, ins, slot)) | |
2834 | return xtNoExceptionHandler; | |
2835 | opc = xtensa_opcode_decode (isa, ifmt, is, slot); | |
2836 | if (opc == XTENSA_UNDEFINED) | |
2837 | return xtNoExceptionHandler; | |
2838 | switch (call0_classify_opcode (isa, opc)) | |
2839 | { | |
2840 | case c0opc_illegal: | |
2841 | case c0opc_flow: | |
2842 | case c0opc_entry: | |
2843 | case c0opc_break: | |
2844 | /* We expect none of them here. */ | |
2845 | return xtNoExceptionHandler; | |
2846 | case c0opc_l32e: | |
2847 | func = execute_l32e; | |
2848 | break; | |
2849 | case c0opc_s32e: | |
2850 | func = execute_s32e; | |
2851 | break; | |
2852 | case c0opc_rfwo: /* RFWO. */ | |
2853 | /* Here, we return from WindowOverflow handler and, | |
2854 | if we stopped at the very beginning, which means | |
2855 | A0 was saved, we have to restore it now. */ | |
2856 | if (a0_was_saved) | |
2857 | { | |
2858 | int arreg = arreg_number (gdbarch, | |
2859 | gdbarch_tdep (gdbarch)->a0_base, | |
2860 | wb); | |
2861 | xtensa_write_register (arreg, a0_saved); | |
2862 | } | |
2863 | return xtWindowOverflow; | |
2864 | case c0opc_rfwu: /* RFWU. */ | |
2865 | /* Here, we return from WindowUnderflow handler. | |
2866 | Let's see if either A7 or A11 has to be restored. */ | |
2867 | if (WindowUnderflow12) | |
2868 | { | |
2869 | if (a11_was_saved) | |
2870 | { | |
2871 | int arreg = arreg_number (gdbarch, | |
2872 | gdbarch_tdep (gdbarch)->a0_base + 11, | |
2873 | wb); | |
2874 | xtensa_write_register (arreg, a11_saved); | |
2875 | } | |
2876 | } | |
2877 | else if (a7_was_saved) | |
2878 | { | |
2879 | int arreg = arreg_number (gdbarch, | |
2880 | gdbarch_tdep (gdbarch)->a0_base + 7, | |
2881 | wb); | |
2882 | xtensa_write_register (arreg, a7_saved); | |
2883 | } | |
2884 | return xtWindowUnderflow; | |
2885 | default: /* Simply skip this insns. */ | |
2886 | continue; | |
2887 | } | |
2888 | ||
2889 | /* Decode arguments for L32E / S32E and simulate their execution. */ | |
2890 | if ( xtensa_opcode_num_operands (isa, opc) != 3 ) | |
2891 | return xtNoExceptionHandler; | |
2892 | if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, &at)) | |
2893 | return xtNoExceptionHandler; | |
2894 | if (xtensa_operand_decode (isa, opc, 0, &at)) | |
2895 | return xtNoExceptionHandler; | |
2896 | if (xtensa_operand_get_field (isa, opc, 1, ifmt, is, slot, &as)) | |
2897 | return xtNoExceptionHandler; | |
2898 | if (xtensa_operand_decode (isa, opc, 1, &as)) | |
2899 | return xtNoExceptionHandler; | |
2900 | if (xtensa_operand_get_field (isa, opc, 2, ifmt, is, slot, &offset)) | |
2901 | return xtNoExceptionHandler; | |
2902 | if (xtensa_operand_decode (isa, opc, 2, &offset)) | |
2903 | return xtNoExceptionHandler; | |
2904 | ||
2905 | (*func) (gdbarch, at, as, offset, wb); | |
2906 | } | |
2907 | ||
2908 | ia += ilen; | |
2909 | } | |
2910 | return xtNoExceptionHandler; | |
2911 | } | |
2912 | ||
2913 | /* Handle Window Overflow / Underflow exception frames. */ | |
2914 | ||
2915 | static void | |
2916 | xtensa_window_interrupt_frame_cache (struct frame_info *this_frame, | |
2917 | xtensa_frame_cache_t *cache, | |
2918 | CORE_ADDR pc) | |
2919 | { | |
2920 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2921 | CORE_ADDR ps, wb, ws, ra; | |
2922 | int epc1_regnum, i, regnum; | |
2923 | xtensa_exception_handler_t eh_type; | |
2924 | ||
2925 | /* Read PS, WB, and WS from the hardware. Note that PS register | |
2926 | must be present, if Windowed ABI is supported. */ | |
2927 | ps = xtensa_read_register (gdbarch_ps_regnum (gdbarch)); | |
2928 | wb = xtensa_read_register (gdbarch_tdep (gdbarch)->wb_regnum); | |
2929 | ws = xtensa_read_register (gdbarch_tdep (gdbarch)->ws_regnum); | |
2930 | ||
2931 | /* Execute all the remaining instructions from Window Interrupt Handler | |
2932 | by simulating them on the remote protocol level. On return, set the | |
2933 | type of Xtensa Window Interrupt Handler, or report an error. */ | |
2934 | eh_type = execute_code (gdbarch, pc, wb); | |
2935 | if (eh_type == xtNoExceptionHandler) | |
2936 | error (_("\ | |
2937 | Unable to decode Xtensa Window Interrupt Handler's code.")); | |
2938 | ||
2939 | cache->ps = ps ^ PS_EXC; /* Clear the exception bit in PS. */ | |
2940 | cache->call0 = 0; /* It's Windowed ABI. */ | |
2941 | ||
2942 | /* All registers for the cached frame will be alive. */ | |
2943 | for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++) | |
2944 | cache->wd.aregs[i] = -1; | |
2945 | ||
2946 | if (eh_type == xtWindowOverflow) | |
2947 | cache->wd.ws = ws ^ (1 << wb); | |
2948 | else /* eh_type == xtWindowUnderflow. */ | |
2949 | cache->wd.ws = ws | (1 << wb); | |
2950 | ||
2951 | cache->wd.wb = (ps & 0xf00) >> 8; /* Set WB to OWB. */ | |
2952 | regnum = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base, | |
2953 | cache->wd.wb); | |
2954 | ra = xtensa_read_register (regnum); | |
2955 | cache->wd.callsize = WINSIZE (ra); | |
2956 | cache->prev_sp = xtensa_read_register (regnum + 1); | |
2957 | /* Set regnum to a frame pointer of the frame being cached. */ | |
2958 | regnum = xtensa_scan_prologue (gdbarch, pc); | |
2959 | regnum = arreg_number (gdbarch, | |
2960 | gdbarch_tdep (gdbarch)->a0_base + regnum, | |
2961 | cache->wd.wb); | |
2962 | cache->base = get_frame_register_unsigned (this_frame, regnum); | |
2963 | ||
2964 | /* Read PC of interrupted function from EPC1 register. */ | |
2965 | epc1_regnum = xtensa_find_register_by_name (gdbarch,"epc1"); | |
2966 | if (epc1_regnum < 0) | |
2967 | error(_("Unable to read Xtensa register EPC1")); | |
2968 | cache->ra = xtensa_read_register (epc1_regnum); | |
2969 | cache->pc = get_frame_func (this_frame); | |
2970 | } | |
2971 | ||
bdb4c075 MG |
2972 | |
2973 | /* Skip function prologue. | |
2974 | ||
2975 | Return the pc of the first instruction after prologue. GDB calls this to | |
2976 | find the address of the first line of the function or (if there is no line | |
2977 | number information) to skip the prologue for planting breakpoints on | |
2978 | function entries. Use debug info (if present) or prologue analysis to skip | |
2979 | the prologue to achieve reliable debugging behavior. For windowed ABI, | |
2980 | only the 'entry' instruction is skipped. It is not strictly necessary to | |
2981 | skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to | |
2982 | backtrace at any point in the prologue, however certain potential hazards | |
2983 | are avoided and a more "normal" debugging experience is ensured by | |
2984 | skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG). | |
2985 | For example, if we don't skip the prologue: | |
2986 | - Some args may not yet have been saved to the stack where the debug | |
2987 | info expects to find them (true anyway when only 'entry' is skipped); | |
2988 | - Software breakpoints ('break' instrs) may not have been unplanted | |
2989 | when the prologue analysis is done on initializing the frame cache, | |
2990 | and breaks in the prologue will throw off the analysis. | |
ca3bf3bd DJ |
2991 | |
2992 | If we have debug info ( line-number info, in particular ) we simply skip | |
2993 | the code associated with the first function line effectively skipping | |
bdb4c075 | 2994 | the prologue code. It works even in cases like |
ca3bf3bd DJ |
2995 | |
2996 | int main() | |
2997 | { int local_var = 1; | |
2998 | .... | |
2999 | } | |
3000 | ||
3001 | because, for this source code, both Xtensa compilers will generate two | |
3002 | separate entries ( with the same line number ) in dwarf line-number | |
3003 | section to make sure there is a boundary between the prologue code and | |
3004 | the rest of the function. | |
3005 | ||
bdb4c075 MG |
3006 | If there is no debug info, we need to analyze the code. */ |
3007 | ||
3008 | /* #define DONT_SKIP_PROLOGUE */ | |
ca3bf3bd | 3009 | |
63807e1d | 3010 | static CORE_ADDR |
6093d2eb | 3011 | xtensa_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
ca3bf3bd | 3012 | { |
bdb4c075 MG |
3013 | struct symtab_and_line prologue_sal; |
3014 | CORE_ADDR body_pc; | |
3015 | ||
ca3bf3bd DJ |
3016 | DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc); |
3017 | ||
bdb4c075 MG |
3018 | #if DONT_SKIP_PROLOGUE |
3019 | return start_pc; | |
3020 | #endif | |
3021 | ||
3022 | /* Try to find first body line from debug info. */ | |
3023 | ||
3024 | prologue_sal = find_pc_line (start_pc, 0); | |
3025 | if (prologue_sal.line != 0) /* Found debug info. */ | |
ca3bf3bd | 3026 | { |
f976a05d MG |
3027 | /* In Call0, it is possible to have a function with only one instruction |
3028 | ('ret') resulting from a one-line optimized function that does nothing. | |
3029 | In that case, prologue_sal.end may actually point to the start of the | |
3030 | next function in the text section, causing a breakpoint to be set at | |
3031 | the wrong place. Check, if the end address is within a different | |
3032 | function, and if so return the start PC. We know we have symbol | |
3033 | information. */ | |
ca3bf3bd | 3034 | |
bdb4c075 MG |
3035 | CORE_ADDR end_func; |
3036 | ||
f976a05d MG |
3037 | if ((gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only) |
3038 | && call0_ret (start_pc, prologue_sal.end)) | |
3039 | return start_pc; | |
3040 | ||
bdb4c075 MG |
3041 | find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL); |
3042 | if (end_func != start_pc) | |
ca3bf3bd DJ |
3043 | return start_pc; |
3044 | ||
bdb4c075 | 3045 | return prologue_sal.end; |
ca3bf3bd | 3046 | } |
ca3bf3bd | 3047 | |
bdb4c075 | 3048 | /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */ |
dbab50de MG |
3049 | body_pc = call0_analyze_prologue (gdbarch, start_pc, 0, 0, |
3050 | xtensa_alloc_frame_cache (0)); | |
bdb4c075 MG |
3051 | return body_pc != 0 ? body_pc : start_pc; |
3052 | } | |
ca3bf3bd DJ |
3053 | |
3054 | /* Verify the current configuration. */ | |
ca3bf3bd DJ |
3055 | static void |
3056 | xtensa_verify_config (struct gdbarch *gdbarch) | |
3057 | { | |
d7e74731 PA |
3058 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3059 | string_file log; | |
ca3bf3bd DJ |
3060 | |
3061 | /* Verify that we got a reasonable number of AREGS. */ | |
3062 | if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs) | |
d7e74731 | 3063 | log.printf (_("\ |
bdb4c075 | 3064 | \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"), |
d7e74731 | 3065 | tdep->num_aregs); |
ca3bf3bd DJ |
3066 | |
3067 | /* Verify that certain registers exist. */ | |
bdb4c075 | 3068 | |
ca3bf3bd | 3069 | if (tdep->pc_regnum == -1) |
d7e74731 | 3070 | log.printf (_("\n\tpc_regnum: No PC register")); |
bdb4c075 | 3071 | if (tdep->isa_use_exceptions && tdep->ps_regnum == -1) |
d7e74731 | 3072 | log.printf (_("\n\tps_regnum: No PS register")); |
bdb4c075 MG |
3073 | |
3074 | if (tdep->isa_use_windowed_registers) | |
3075 | { | |
3076 | if (tdep->wb_regnum == -1) | |
d7e74731 | 3077 | log.printf (_("\n\twb_regnum: No WB register")); |
bdb4c075 | 3078 | if (tdep->ws_regnum == -1) |
d7e74731 | 3079 | log.printf (_("\n\tws_regnum: No WS register")); |
bdb4c075 | 3080 | if (tdep->ar_base == -1) |
d7e74731 | 3081 | log.printf (_("\n\tar_base: No AR registers")); |
bdb4c075 MG |
3082 | } |
3083 | ||
ca3bf3bd | 3084 | if (tdep->a0_base == -1) |
d7e74731 | 3085 | log.printf (_("\n\ta0_base: No Ax registers")); |
ca3bf3bd | 3086 | |
d7e74731 | 3087 | if (!log.empty ()) |
ca3bf3bd | 3088 | internal_error (__FILE__, __LINE__, |
d7e74731 | 3089 | _("the following are invalid: %s"), log.c_str ()); |
ca3bf3bd DJ |
3090 | } |
3091 | ||
94a0e877 MG |
3092 | |
3093 | /* Derive specific register numbers from the array of registers. */ | |
3094 | ||
63807e1d | 3095 | static void |
94a0e877 MG |
3096 | xtensa_derive_tdep (struct gdbarch_tdep *tdep) |
3097 | { | |
3098 | xtensa_register_t* rmap; | |
3099 | int n, max_size = 4; | |
3100 | ||
3101 | tdep->num_regs = 0; | |
3102 | tdep->num_nopriv_regs = 0; | |
3103 | ||
3104 | /* Special registers 0..255 (core). */ | |
3105 | #define XTENSA_DBREGN_SREG(n) (0x0200+(n)) | |
f74f865e MF |
3106 | /* User registers 0..255. */ |
3107 | #define XTENSA_DBREGN_UREG(n) (0x0300+(n)) | |
94a0e877 MG |
3108 | |
3109 | for (rmap = tdep->regmap, n = 0; rmap->target_number != -1; n++, rmap++) | |
3110 | { | |
3111 | if (rmap->target_number == 0x0020) | |
3112 | tdep->pc_regnum = n; | |
3113 | else if (rmap->target_number == 0x0100) | |
3114 | tdep->ar_base = n; | |
3115 | else if (rmap->target_number == 0x0000) | |
3116 | tdep->a0_base = n; | |
3117 | else if (rmap->target_number == XTENSA_DBREGN_SREG(72)) | |
3118 | tdep->wb_regnum = n; | |
3119 | else if (rmap->target_number == XTENSA_DBREGN_SREG(73)) | |
3120 | tdep->ws_regnum = n; | |
3121 | else if (rmap->target_number == XTENSA_DBREGN_SREG(233)) | |
3122 | tdep->debugcause_regnum = n; | |
3123 | else if (rmap->target_number == XTENSA_DBREGN_SREG(232)) | |
3124 | tdep->exccause_regnum = n; | |
3125 | else if (rmap->target_number == XTENSA_DBREGN_SREG(238)) | |
3126 | tdep->excvaddr_regnum = n; | |
3127 | else if (rmap->target_number == XTENSA_DBREGN_SREG(0)) | |
3128 | tdep->lbeg_regnum = n; | |
3129 | else if (rmap->target_number == XTENSA_DBREGN_SREG(1)) | |
3130 | tdep->lend_regnum = n; | |
3131 | else if (rmap->target_number == XTENSA_DBREGN_SREG(2)) | |
3132 | tdep->lcount_regnum = n; | |
3133 | else if (rmap->target_number == XTENSA_DBREGN_SREG(3)) | |
3134 | tdep->sar_regnum = n; | |
3135 | else if (rmap->target_number == XTENSA_DBREGN_SREG(5)) | |
3136 | tdep->litbase_regnum = n; | |
3137 | else if (rmap->target_number == XTENSA_DBREGN_SREG(230)) | |
3138 | tdep->ps_regnum = n; | |
f74f865e MF |
3139 | else if (rmap->target_number == XTENSA_DBREGN_UREG(231)) |
3140 | tdep->threadptr_regnum = n; | |
94a0e877 MG |
3141 | #if 0 |
3142 | else if (rmap->target_number == XTENSA_DBREGN_SREG(226)) | |
3143 | tdep->interrupt_regnum = n; | |
3144 | else if (rmap->target_number == XTENSA_DBREGN_SREG(227)) | |
3145 | tdep->interrupt2_regnum = n; | |
3146 | else if (rmap->target_number == XTENSA_DBREGN_SREG(224)) | |
3147 | tdep->cpenable_regnum = n; | |
3148 | #endif | |
3149 | ||
3150 | if (rmap->byte_size > max_size) | |
3151 | max_size = rmap->byte_size; | |
3152 | if (rmap->mask != 0 && tdep->num_regs == 0) | |
3153 | tdep->num_regs = n; | |
3154 | /* Find out out how to deal with priveleged registers. | |
3155 | ||
3156 | if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0 | |
3157 | && tdep->num_nopriv_regs == 0) | |
3158 | tdep->num_nopriv_regs = n; | |
3159 | */ | |
3160 | if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0 | |
3161 | && tdep->num_regs == 0) | |
3162 | tdep->num_regs = n; | |
3163 | } | |
3164 | ||
3165 | /* Number of pseudo registers. */ | |
3166 | tdep->num_pseudo_regs = n - tdep->num_regs; | |
3167 | ||
3168 | /* Empirically determined maximum sizes. */ | |
3169 | tdep->max_register_raw_size = max_size; | |
3170 | tdep->max_register_virtual_size = max_size; | |
3171 | } | |
3172 | ||
ca3bf3bd DJ |
3173 | /* Module "constructor" function. */ |
3174 | ||
94a0e877 MG |
3175 | extern struct gdbarch_tdep xtensa_tdep; |
3176 | ||
ca3bf3bd DJ |
3177 | static struct gdbarch * |
3178 | xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
3179 | { | |
3180 | struct gdbarch_tdep *tdep; | |
3181 | struct gdbarch *gdbarch; | |
ca3bf3bd DJ |
3182 | |
3183 | DEBUGTRACE ("gdbarch_init()\n"); | |
3184 | ||
a4398628 MF |
3185 | if (!xtensa_default_isa) |
3186 | xtensa_default_isa = xtensa_isa_init (0, 0); | |
3187 | ||
ca3bf3bd | 3188 | /* We have to set the byte order before we call gdbarch_alloc. */ |
94a0e877 | 3189 | info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE; |
ca3bf3bd | 3190 | |
94a0e877 | 3191 | tdep = &xtensa_tdep; |
ca3bf3bd | 3192 | gdbarch = gdbarch_alloc (&info, tdep); |
94a0e877 | 3193 | xtensa_derive_tdep (tdep); |
ca3bf3bd DJ |
3194 | |
3195 | /* Verify our configuration. */ | |
3196 | xtensa_verify_config (gdbarch); | |
dbab50de | 3197 | xtensa_session_once_reported = 0; |
ca3bf3bd | 3198 | |
53375380 PA |
3199 | set_gdbarch_wchar_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
3200 | set_gdbarch_wchar_signed (gdbarch, 0); | |
3201 | ||
bdb4c075 | 3202 | /* Pseudo-Register read/write. */ |
ca3bf3bd DJ |
3203 | set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read); |
3204 | set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write); | |
3205 | ||
3206 | /* Set target information. */ | |
3207 | set_gdbarch_num_regs (gdbarch, tdep->num_regs); | |
3208 | set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs); | |
3209 | set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1); | |
3210 | set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum); | |
3211 | set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum); | |
3212 | ||
ba2b1c56 | 3213 | /* Renumber registers for known formats (stabs and dwarf2). */ |
ca3bf3bd | 3214 | set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); |
ca3bf3bd DJ |
3215 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); |
3216 | ||
3217 | /* We provide our own function to get register information. */ | |
3218 | set_gdbarch_register_name (gdbarch, xtensa_register_name); | |
3219 | set_gdbarch_register_type (gdbarch, xtensa_register_type); | |
3220 | ||
581e13c1 | 3221 | /* To call functions from GDB using dummy frame. */ |
ca3bf3bd DJ |
3222 | set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call); |
3223 | ||
3224 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); | |
3225 | ||
3226 | set_gdbarch_return_value (gdbarch, xtensa_return_value); | |
3227 | ||
3228 | /* Advance PC across any prologue instructions to reach "real" code. */ | |
3229 | set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue); | |
3230 | ||
3231 | /* Stack grows downward. */ | |
3232 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
3233 | ||
3234 | /* Set breakpoints. */ | |
04180708 YQ |
3235 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
3236 | xtensa_breakpoint_kind_from_pc); | |
3237 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
3238 | xtensa_sw_breakpoint_from_kind); | |
ca3bf3bd DJ |
3239 | |
3240 | /* After breakpoint instruction or illegal instruction, pc still | |
3241 | points at break instruction, so don't decrement. */ | |
3242 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
3243 | ||
3244 | /* We don't skip args. */ | |
3245 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
3246 | ||
3247 | set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc); | |
3248 | ||
3249 | set_gdbarch_frame_align (gdbarch, xtensa_frame_align); | |
3250 | ||
5142f611 | 3251 | set_gdbarch_dummy_id (gdbarch, xtensa_dummy_id); |
ca3bf3bd DJ |
3252 | |
3253 | /* Frame handling. */ | |
3254 | frame_base_set_default (gdbarch, &xtensa_frame_base); | |
5142f611 MG |
3255 | frame_unwind_append_unwinder (gdbarch, &xtensa_unwind); |
3256 | dwarf2_append_unwinders (gdbarch); | |
ca3bf3bd | 3257 | |
ca3bf3bd DJ |
3258 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
3259 | ||
3260 | xtensa_add_reggroups (gdbarch); | |
3261 | set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p); | |
3262 | ||
97094034 AA |
3263 | set_gdbarch_iterate_over_regset_sections |
3264 | (gdbarch, xtensa_iterate_over_regset_sections); | |
ca3bf3bd | 3265 | |
ee967b5f MG |
3266 | set_solib_svr4_fetch_link_map_offsets |
3267 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); | |
3268 | ||
40045d91 MF |
3269 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
3270 | gdbarch_init_osabi (info, gdbarch); | |
3271 | ||
ca3bf3bd DJ |
3272 | return gdbarch; |
3273 | } | |
3274 | ||
ca3bf3bd | 3275 | static void |
6b50c0b0 | 3276 | xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
ca3bf3bd DJ |
3277 | { |
3278 | error (_("xtensa_dump_tdep(): not implemented")); | |
3279 | } | |
3280 | ||
63807e1d PA |
3281 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
3282 | extern initialize_file_ftype _initialize_xtensa_tdep; | |
3283 | ||
ca3bf3bd DJ |
3284 | void |
3285 | _initialize_xtensa_tdep (void) | |
3286 | { | |
ca3bf3bd DJ |
3287 | gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep); |
3288 | xtensa_init_reggroups (); | |
3289 | ||
ccce17b0 YQ |
3290 | add_setshow_zuinteger_cmd ("xtensa", |
3291 | class_maintenance, | |
3292 | &xtensa_debug_level, | |
581e13c1 MS |
3293 | _("Set Xtensa debugging."), |
3294 | _("Show Xtensa debugging."), _("\ | |
ca3bf3bd DJ |
3295 | When non-zero, Xtensa-specific debugging is enabled. \ |
3296 | Can be 1, 2, 3, or 4 indicating the level of debugging."), | |
ccce17b0 YQ |
3297 | NULL, |
3298 | NULL, | |
3299 | &setdebuglist, &showdebuglist); | |
ca3bf3bd | 3300 | } |