Commit | Line | Data |
---|---|---|
ca3bf3bd DJ |
1 | /* Target-dependent code for the Xtensa port of GDB, the GNU debugger. |
2 | ||
7b6bb8da | 3 | Copyright (C) 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2011 |
0fb0cc75 | 4 | Free Software Foundation, Inc. |
ca3bf3bd DJ |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
ca3bf3bd DJ |
11 | (at your option) any later version. |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
ca3bf3bd DJ |
20 | |
21 | #include "defs.h" | |
22 | #include "frame.h" | |
ee967b5f | 23 | #include "solib-svr4.h" |
ca3bf3bd DJ |
24 | #include "symtab.h" |
25 | #include "symfile.h" | |
26 | #include "objfiles.h" | |
27 | #include "gdbtypes.h" | |
28 | #include "gdbcore.h" | |
29 | #include "value.h" | |
30 | #include "dis-asm.h" | |
31 | #include "inferior.h" | |
32 | #include "floatformat.h" | |
33 | #include "regcache.h" | |
34 | #include "reggroups.h" | |
35 | #include "regset.h" | |
36 | ||
37 | #include "dummy-frame.h" | |
fa8f86ff | 38 | #include "dwarf2.h" |
ca3bf3bd DJ |
39 | #include "dwarf2-frame.h" |
40 | #include "dwarf2loc.h" | |
41 | #include "frame.h" | |
42 | #include "frame-base.h" | |
43 | #include "frame-unwind.h" | |
44 | ||
45 | #include "arch-utils.h" | |
46 | #include "gdbarch.h" | |
47 | #include "remote.h" | |
48 | #include "serial.h" | |
49 | ||
50 | #include "command.h" | |
51 | #include "gdbcmd.h" | |
52 | #include "gdb_assert.h" | |
53 | ||
bdb4c075 | 54 | #include "xtensa-isa.h" |
ca3bf3bd | 55 | #include "xtensa-tdep.h" |
94a0e877 | 56 | #include "xtensa-config.h" |
ca3bf3bd DJ |
57 | |
58 | ||
59 | static int xtensa_debug_level = 0; | |
60 | ||
61 | #define DEBUGWARN(args...) \ | |
62 | if (xtensa_debug_level > 0) \ | |
63 | fprintf_unfiltered (gdb_stdlog, "(warn ) " args) | |
64 | ||
65 | #define DEBUGINFO(args...) \ | |
66 | if (xtensa_debug_level > 1) \ | |
67 | fprintf_unfiltered (gdb_stdlog, "(info ) " args) | |
68 | ||
69 | #define DEBUGTRACE(args...) \ | |
70 | if (xtensa_debug_level > 2) \ | |
71 | fprintf_unfiltered (gdb_stdlog, "(trace) " args) | |
72 | ||
73 | #define DEBUGVERB(args...) \ | |
74 | if (xtensa_debug_level > 3) \ | |
75 | fprintf_unfiltered (gdb_stdlog, "(verb ) " args) | |
76 | ||
77 | ||
78 | /* According to the ABI, the SP must be aligned to 16-byte boundaries. */ | |
ca3bf3bd DJ |
79 | #define SP_ALIGNMENT 16 |
80 | ||
81 | ||
bdb4c075 MG |
82 | /* On Windowed ABI, we use a6 through a11 for passing arguments |
83 | to a function called by GDB because CALL4 is used. */ | |
bdb4c075 MG |
84 | #define ARGS_NUM_REGS 6 |
85 | #define REGISTER_SIZE 4 | |
ca3bf3bd | 86 | |
ca3bf3bd | 87 | |
bdb4c075 MG |
88 | /* Extract the call size from the return address or PS register. */ |
89 | #define PS_CALLINC_SHIFT 16 | |
90 | #define PS_CALLINC_MASK 0x00030000 | |
91 | #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT) | |
92 | #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3)) | |
ca3bf3bd | 93 | |
bdb4c075 | 94 | /* ABI-independent macros. */ |
91d8eb23 MD |
95 | #define ARG_NOF(gdbarch) \ |
96 | (gdbarch_tdep (gdbarch)->call_abi \ | |
97 | == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS)) | |
98 | #define ARG_1ST(gdbarch) \ | |
99 | (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \ | |
94a0e877 | 100 | ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \ |
91d8eb23 | 101 | : (gdbarch_tdep (gdbarch)->a0_base + 6)) |
ca3bf3bd | 102 | |
ca3bf3bd DJ |
103 | /* XTENSA_IS_ENTRY tests whether the first byte of an instruction |
104 | indicates that the instruction is an ENTRY instruction. */ | |
105 | ||
91d8eb23 MD |
106 | #define XTENSA_IS_ENTRY(gdbarch, op1) \ |
107 | ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \ | |
4c6b5505 | 108 | ? ((op1) == 0x6c) : ((op1) == 0x36)) |
ca3bf3bd | 109 | |
bdb4c075 | 110 | #define XTENSA_ENTRY_LENGTH 3 |
ca3bf3bd DJ |
111 | |
112 | /* windowing_enabled() returns true, if windowing is enabled. | |
113 | WOE must be set to 1; EXCM to 0. | |
114 | Note: We assume that EXCM is always 0 for XEA1. */ | |
115 | ||
bdb4c075 MG |
116 | #define PS_WOE (1<<18) |
117 | #define PS_EXC (1<<4) | |
118 | ||
581e13c1 MS |
119 | /* Convert a live A-register number to the corresponding AR-register |
120 | number. */ | |
91d8eb23 | 121 | static int |
ee967b5f | 122 | arreg_number (struct gdbarch *gdbarch, int a_regnum, ULONGEST wb) |
91d8eb23 MD |
123 | { |
124 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
ee967b5f | 125 | int arreg; |
91d8eb23 | 126 | |
ee967b5f MG |
127 | arreg = a_regnum - tdep->a0_base; |
128 | arreg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT; | |
129 | arreg &= tdep->num_aregs - 1; | |
91d8eb23 | 130 | |
ee967b5f MG |
131 | return arreg + tdep->ar_base; |
132 | } | |
133 | ||
134 | /* Convert a live AR-register number to the corresponding A-register order | |
135 | number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */ | |
136 | static int | |
137 | areg_number (struct gdbarch *gdbarch, int ar_regnum, unsigned int wb) | |
138 | { | |
139 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
140 | int areg; | |
141 | ||
142 | areg = ar_regnum - tdep->ar_base; | |
143 | if (areg < 0 || areg >= tdep->num_aregs) | |
144 | return -1; | |
145 | areg = (areg - wb * 4) & (tdep->num_aregs - 1); | |
146 | return (areg > 15) ? -1 : areg; | |
91d8eb23 MD |
147 | } |
148 | ||
ca3bf3bd DJ |
149 | static inline int |
150 | windowing_enabled (CORE_ADDR ps) | |
151 | { | |
bdb4c075 | 152 | return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0); |
ca3bf3bd DJ |
153 | } |
154 | ||
155 | /* Return the window size of the previous call to the function from which we | |
156 | have just returned. | |
157 | ||
158 | This function is used to extract the return value after a called function | |
bdb4c075 | 159 | has returned to the caller. On Xtensa, the register that holds the return |
ca3bf3bd DJ |
160 | value (from the perspective of the caller) depends on what call |
161 | instruction was used. For now, we are assuming that the call instruction | |
162 | precedes the current address, so we simply analyze the call instruction. | |
163 | If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4' | |
164 | method to call the inferior function. */ | |
165 | ||
166 | static int | |
91d8eb23 | 167 | extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc) |
ca3bf3bd | 168 | { |
e17a4113 | 169 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
bdb4c075 | 170 | int winsize = 4; |
ca3bf3bd | 171 | int insn; |
ff7a4c00 | 172 | gdb_byte buf[4]; |
ca3bf3bd DJ |
173 | |
174 | DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc); | |
175 | ||
176 | /* Read the previous instruction (should be a call[x]{4|8|12}. */ | |
177 | read_memory (pc-3, buf, 3); | |
e17a4113 | 178 | insn = extract_unsigned_integer (buf, 3, byte_order); |
ca3bf3bd DJ |
179 | |
180 | /* Decode call instruction: | |
181 | Little Endian | |
182 | call{0,4,8,12} OFFSET || {00,01,10,11} || 0101 | |
183 | callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000 | |
184 | Big Endian | |
185 | call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET | |
186 | callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */ | |
187 | ||
e17a4113 | 188 | if (byte_order == BFD_ENDIAN_LITTLE) |
ca3bf3bd DJ |
189 | { |
190 | if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0)) | |
bdb4c075 | 191 | winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */ |
ca3bf3bd DJ |
192 | } |
193 | else | |
194 | { | |
195 | if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03)) | |
bdb4c075 | 196 | winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */ |
ca3bf3bd DJ |
197 | } |
198 | return winsize; | |
199 | } | |
200 | ||
201 | ||
202 | /* REGISTER INFORMATION */ | |
203 | ||
204 | /* Returns the name of a register. */ | |
ca3bf3bd | 205 | static const char * |
d93859e2 | 206 | xtensa_register_name (struct gdbarch *gdbarch, int regnum) |
ca3bf3bd DJ |
207 | { |
208 | /* Return the name stored in the register map. */ | |
d93859e2 UW |
209 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch) |
210 | + gdbarch_num_pseudo_regs (gdbarch)) | |
211 | return gdbarch_tdep (gdbarch)->regmap[regnum].name; | |
ca3bf3bd | 212 | |
ca3bf3bd DJ |
213 | internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum); |
214 | return 0; | |
215 | } | |
216 | ||
ca3bf3bd DJ |
217 | /* Return the type of a register. Create a new type, if necessary. */ |
218 | ||
ca3bf3bd DJ |
219 | static struct type * |
220 | xtensa_register_type (struct gdbarch *gdbarch, int regnum) | |
221 | { | |
df4df182 UW |
222 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
223 | ||
ca3bf3bd | 224 | /* Return signed integer for ARx and Ax registers. */ |
df4df182 UW |
225 | if ((regnum >= tdep->ar_base |
226 | && regnum < tdep->ar_base + tdep->num_aregs) | |
227 | || (regnum >= tdep->a0_base | |
228 | && regnum < tdep->a0_base + 16)) | |
0dfff4cb | 229 | return builtin_type (gdbarch)->builtin_int; |
ca3bf3bd | 230 | |
6b50c0b0 | 231 | if (regnum == gdbarch_pc_regnum (gdbarch) |
df4df182 | 232 | || regnum == tdep->a0_base + 1) |
fde6c819 | 233 | return builtin_type (gdbarch)->builtin_data_ptr; |
ca3bf3bd DJ |
234 | |
235 | /* Return the stored type for all other registers. */ | |
6b50c0b0 UW |
236 | else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch) |
237 | + gdbarch_num_pseudo_regs (gdbarch)) | |
ca3bf3bd | 238 | { |
df4df182 | 239 | xtensa_register_t* reg = &tdep->regmap[regnum]; |
ca3bf3bd | 240 | |
bdb4c075 | 241 | /* Set ctype for this register (only the first time). */ |
ca3bf3bd DJ |
242 | |
243 | if (reg->ctype == 0) | |
244 | { | |
245 | struct ctype_cache *tp; | |
246 | int size = reg->byte_size; | |
247 | ||
bdb4c075 MG |
248 | /* We always use the memory representation, |
249 | even if the register width is smaller. */ | |
ca3bf3bd DJ |
250 | switch (size) |
251 | { | |
252 | case 1: | |
df4df182 | 253 | reg->ctype = builtin_type (gdbarch)->builtin_uint8; |
ca3bf3bd DJ |
254 | break; |
255 | ||
256 | case 2: | |
df4df182 | 257 | reg->ctype = builtin_type (gdbarch)->builtin_uint16; |
ca3bf3bd DJ |
258 | break; |
259 | ||
260 | case 4: | |
df4df182 | 261 | reg->ctype = builtin_type (gdbarch)->builtin_uint32; |
ca3bf3bd DJ |
262 | break; |
263 | ||
264 | case 8: | |
df4df182 | 265 | reg->ctype = builtin_type (gdbarch)->builtin_uint64; |
ca3bf3bd DJ |
266 | break; |
267 | ||
268 | case 16: | |
df4df182 | 269 | reg->ctype = builtin_type (gdbarch)->builtin_uint128; |
ca3bf3bd DJ |
270 | break; |
271 | ||
272 | default: | |
df4df182 | 273 | for (tp = tdep->type_entries; tp != NULL; tp = tp->next) |
ca3bf3bd DJ |
274 | if (tp->size == size) |
275 | break; | |
276 | ||
277 | if (tp == NULL) | |
278 | { | |
279 | char *name = xmalloc (16); | |
280 | tp = xmalloc (sizeof (struct ctype_cache)); | |
df4df182 UW |
281 | tp->next = tdep->type_entries; |
282 | tdep->type_entries = tp; | |
ca3bf3bd DJ |
283 | tp->size = size; |
284 | ||
285 | sprintf (name, "int%d", size * 8); | |
e9bb382b UW |
286 | tp->virtual_type |
287 | = arch_integer_type (gdbarch, size * 8, 1, xstrdup (name)); | |
ca3bf3bd DJ |
288 | } |
289 | ||
290 | reg->ctype = tp->virtual_type; | |
291 | } | |
292 | } | |
293 | return reg->ctype; | |
294 | } | |
295 | ||
ca3bf3bd DJ |
296 | internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum); |
297 | return 0; | |
298 | } | |
299 | ||
300 | ||
bdb4c075 | 301 | /* Return the 'local' register number for stubs, dwarf2, etc. |
ca3bf3bd DJ |
302 | The debugging information enumerates registers starting from 0 for A0 |
303 | to n for An. So, we only have to add the base number for A0. */ | |
304 | ||
305 | static int | |
d3f73121 | 306 | xtensa_reg_to_regnum (struct gdbarch *gdbarch, int regnum) |
ca3bf3bd DJ |
307 | { |
308 | int i; | |
309 | ||
310 | if (regnum >= 0 && regnum < 16) | |
d3f73121 | 311 | return gdbarch_tdep (gdbarch)->a0_base + regnum; |
ca3bf3bd | 312 | |
f57d151a | 313 | for (i = 0; |
d3f73121 | 314 | i < gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
f57d151a | 315 | i++) |
d3f73121 | 316 | if (regnum == gdbarch_tdep (gdbarch)->regmap[i].target_number) |
ca3bf3bd DJ |
317 | return i; |
318 | ||
ca3bf3bd DJ |
319 | internal_error (__FILE__, __LINE__, |
320 | _("invalid dwarf/stabs register number %d"), regnum); | |
321 | return 0; | |
322 | } | |
323 | ||
324 | ||
bdb4c075 MG |
325 | /* Write the bits of a masked register to the various registers. |
326 | Only the masked areas of these registers are modified; the other | |
327 | fields are untouched. The size of masked registers is always less | |
328 | than or equal to 32 bits. */ | |
ca3bf3bd DJ |
329 | |
330 | static void | |
9c9acae0 UW |
331 | xtensa_register_write_masked (struct regcache *regcache, |
332 | xtensa_register_t *reg, const gdb_byte *buffer) | |
ca3bf3bd DJ |
333 | { |
334 | unsigned int value[(MAX_REGISTER_SIZE + 3) / 4]; | |
ca3bf3bd DJ |
335 | const xtensa_mask_t *mask = reg->mask; |
336 | ||
337 | int shift = 0; /* Shift for next mask (mod 32). */ | |
338 | int start, size; /* Start bit and size of current mask. */ | |
339 | ||
340 | unsigned int *ptr = value; | |
341 | unsigned int regval, m, mem = 0; | |
342 | ||
343 | int bytesize = reg->byte_size; | |
344 | int bitsize = bytesize * 8; | |
345 | int i, r; | |
346 | ||
347 | DEBUGTRACE ("xtensa_register_write_masked ()\n"); | |
348 | ||
349 | /* Copy the masked register to host byte-order. */ | |
6b50c0b0 | 350 | if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
351 | for (i = 0; i < bytesize; i++) |
352 | { | |
353 | mem >>= 8; | |
354 | mem |= (buffer[bytesize - i - 1] << 24); | |
355 | if ((i & 3) == 3) | |
356 | *ptr++ = mem; | |
357 | } | |
358 | else | |
359 | for (i = 0; i < bytesize; i++) | |
360 | { | |
361 | mem >>= 8; | |
362 | mem |= (buffer[i] << 24); | |
363 | if ((i & 3) == 3) | |
364 | *ptr++ = mem; | |
365 | } | |
366 | ||
367 | /* We might have to shift the final value: | |
368 | bytesize & 3 == 0 -> nothing to do, we use the full 32 bits, | |
369 | bytesize & 3 == x -> shift (4-x) * 8. */ | |
370 | ||
371 | *ptr = mem >> (((0 - bytesize) & 3) * 8); | |
372 | ptr = value; | |
373 | mem = *ptr; | |
374 | ||
375 | /* Write the bits to the masked areas of the other registers. */ | |
376 | for (i = 0; i < mask->count; i++) | |
377 | { | |
378 | start = mask->mask[i].bit_start; | |
379 | size = mask->mask[i].bit_size; | |
380 | regval = mem >> shift; | |
381 | ||
382 | if ((shift += size) > bitsize) | |
383 | error (_("size of all masks is larger than the register")); | |
384 | ||
385 | if (shift >= 32) | |
386 | { | |
387 | mem = *(++ptr); | |
388 | shift -= 32; | |
389 | bitsize -= 32; | |
390 | ||
391 | if (shift > 0) | |
392 | regval |= mem << (size - shift); | |
393 | } | |
394 | ||
395 | /* Make sure we have a valid register. */ | |
396 | r = mask->mask[i].reg_num; | |
397 | if (r >= 0 && size > 0) | |
398 | { | |
399 | /* Don't overwrite the unmasked areas. */ | |
9c9acae0 UW |
400 | ULONGEST old_val; |
401 | regcache_cooked_read_unsigned (regcache, r, &old_val); | |
ca3bf3bd DJ |
402 | m = 0xffffffff >> (32 - size) << start; |
403 | regval <<= start; | |
9c9acae0 UW |
404 | regval = (regval & m) | (old_val & ~m); |
405 | regcache_cooked_write_unsigned (regcache, r, regval); | |
ca3bf3bd DJ |
406 | } |
407 | } | |
408 | } | |
409 | ||
410 | ||
bdb4c075 MG |
411 | /* Read a tie state or mapped registers. Read the masked areas |
412 | of the registers and assemble them into a single value. */ | |
ca3bf3bd DJ |
413 | |
414 | static void | |
9c9acae0 UW |
415 | xtensa_register_read_masked (struct regcache *regcache, |
416 | xtensa_register_t *reg, gdb_byte *buffer) | |
ca3bf3bd DJ |
417 | { |
418 | unsigned int value[(MAX_REGISTER_SIZE + 3) / 4]; | |
ca3bf3bd DJ |
419 | const xtensa_mask_t *mask = reg->mask; |
420 | ||
421 | int shift = 0; | |
422 | int start, size; | |
423 | ||
424 | unsigned int *ptr = value; | |
425 | unsigned int regval, mem = 0; | |
426 | ||
427 | int bytesize = reg->byte_size; | |
428 | int bitsize = bytesize * 8; | |
429 | int i; | |
430 | ||
431 | DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n", | |
432 | reg->name == 0 ? "" : reg->name); | |
433 | ||
434 | /* Assemble the register from the masked areas of other registers. */ | |
435 | for (i = 0; i < mask->count; i++) | |
436 | { | |
437 | int r = mask->mask[i].reg_num; | |
9c9acae0 UW |
438 | if (r >= 0) |
439 | { | |
440 | ULONGEST val; | |
441 | regcache_cooked_read_unsigned (regcache, r, &val); | |
442 | regval = (unsigned int) val; | |
443 | } | |
444 | else | |
445 | regval = 0; | |
446 | ||
ca3bf3bd DJ |
447 | start = mask->mask[i].bit_start; |
448 | size = mask->mask[i].bit_size; | |
449 | ||
450 | regval >>= start; | |
451 | ||
452 | if (size < 32) | |
453 | regval &= (0xffffffff >> (32 - size)); | |
454 | ||
455 | mem |= regval << shift; | |
456 | ||
457 | if ((shift += size) > bitsize) | |
458 | error (_("size of all masks is larger than the register")); | |
459 | ||
460 | if (shift >= 32) | |
461 | { | |
462 | *ptr++ = mem; | |
463 | bitsize -= 32; | |
464 | shift -= 32; | |
465 | ||
466 | if (shift == 0) | |
467 | mem = 0; | |
468 | else | |
469 | mem = regval >> (size - shift); | |
470 | } | |
471 | } | |
472 | ||
473 | if (shift > 0) | |
474 | *ptr = mem; | |
475 | ||
476 | /* Copy value to target byte order. */ | |
477 | ptr = value; | |
478 | mem = *ptr; | |
479 | ||
6b50c0b0 | 480 | if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
481 | for (i = 0; i < bytesize; i++) |
482 | { | |
483 | if ((i & 3) == 0) | |
484 | mem = *ptr++; | |
485 | buffer[bytesize - i - 1] = mem & 0xff; | |
486 | mem >>= 8; | |
487 | } | |
488 | else | |
489 | for (i = 0; i < bytesize; i++) | |
490 | { | |
491 | if ((i & 3) == 0) | |
492 | mem = *ptr++; | |
493 | buffer[i] = mem & 0xff; | |
494 | mem >>= 8; | |
495 | } | |
496 | } | |
497 | ||
498 | ||
499 | /* Read pseudo registers. */ | |
500 | ||
501 | static void | |
502 | xtensa_pseudo_register_read (struct gdbarch *gdbarch, | |
503 | struct regcache *regcache, | |
504 | int regnum, | |
505 | gdb_byte *buffer) | |
506 | { | |
e17a4113 UW |
507 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
508 | ||
ca3bf3bd | 509 | DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n", |
d93859e2 | 510 | regnum, xtensa_register_name (gdbarch, regnum)); |
ca3bf3bd | 511 | |
6b50c0b0 | 512 | if (regnum == gdbarch_num_regs (gdbarch) |
94a0e877 | 513 | + gdbarch_num_pseudo_regs (gdbarch) - 1) |
6b50c0b0 | 514 | regnum = gdbarch_tdep (gdbarch)->a0_base + 1; |
ca3bf3bd | 515 | |
bdb4c075 | 516 | /* Read aliases a0..a15, if this is a Windowed ABI. */ |
6b50c0b0 | 517 | if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers |
94a0e877 | 518 | && (regnum >= gdbarch_tdep (gdbarch)->a0_base) |
6b50c0b0 | 519 | && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)) |
ca3bf3bd | 520 | { |
ff7a4c00 | 521 | gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE); |
ca3bf3bd | 522 | |
6b50c0b0 | 523 | regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf); |
ee967b5f | 524 | regnum = arreg_number (gdbarch, regnum, |
e17a4113 | 525 | extract_unsigned_integer (buf, 4, byte_order)); |
ca3bf3bd DJ |
526 | } |
527 | ||
bdb4c075 | 528 | /* We can always read non-pseudo registers. */ |
6b50c0b0 | 529 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) |
ca3bf3bd DJ |
530 | regcache_raw_read (regcache, regnum, buffer); |
531 | ||
94a0e877 MG |
532 | |
533 | /* We have to find out how to deal with priveleged registers. | |
534 | Let's treat them as pseudo-registers, but we cannot read/write them. */ | |
535 | ||
536 | else if (regnum < gdbarch_tdep (gdbarch)->a0_base) | |
537 | { | |
538 | buffer[0] = (gdb_byte)0; | |
539 | buffer[1] = (gdb_byte)0; | |
540 | buffer[2] = (gdb_byte)0; | |
541 | buffer[3] = (gdb_byte)0; | |
542 | } | |
ca3bf3bd | 543 | /* Pseudo registers. */ |
f57d151a | 544 | else if (regnum >= 0 |
6b50c0b0 UW |
545 | && regnum < gdbarch_num_regs (gdbarch) |
546 | + gdbarch_num_pseudo_regs (gdbarch)) | |
ca3bf3bd | 547 | { |
6b50c0b0 | 548 | xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; |
ca3bf3bd | 549 | xtensa_register_type_t type = reg->type; |
6b50c0b0 | 550 | int flags = gdbarch_tdep (gdbarch)->target_flags; |
ca3bf3bd | 551 | |
bdb4c075 | 552 | /* We cannot read Unknown or Unmapped registers. */ |
ca3bf3bd DJ |
553 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) |
554 | { | |
555 | if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
556 | { | |
557 | warning (_("cannot read register %s"), | |
d93859e2 | 558 | xtensa_register_name (gdbarch, regnum)); |
ca3bf3bd DJ |
559 | return; |
560 | } | |
561 | } | |
562 | ||
563 | /* Some targets cannot read TIE register files. */ | |
564 | else if (type == xtRegisterTypeTieRegfile) | |
565 | { | |
566 | /* Use 'fetch' to get register? */ | |
567 | if (flags & xtTargetFlagsUseFetchStore) | |
568 | { | |
569 | warning (_("cannot read register")); | |
570 | return; | |
571 | } | |
572 | ||
573 | /* On some targets (esp. simulators), we can always read the reg. */ | |
574 | else if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
575 | { | |
576 | warning (_("cannot read register")); | |
577 | return; | |
578 | } | |
579 | } | |
580 | ||
581 | /* We can always read mapped registers. */ | |
582 | else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState) | |
583 | { | |
9c9acae0 | 584 | xtensa_register_read_masked (regcache, reg, buffer); |
ca3bf3bd DJ |
585 | return; |
586 | } | |
587 | ||
588 | /* Assume that we can read the register. */ | |
589 | regcache_raw_read (regcache, regnum, buffer); | |
590 | } | |
ca3bf3bd DJ |
591 | else |
592 | internal_error (__FILE__, __LINE__, | |
593 | _("invalid register number %d"), regnum); | |
594 | } | |
595 | ||
596 | ||
597 | /* Write pseudo registers. */ | |
598 | ||
599 | static void | |
600 | xtensa_pseudo_register_write (struct gdbarch *gdbarch, | |
601 | struct regcache *regcache, | |
602 | int regnum, | |
603 | const gdb_byte *buffer) | |
604 | { | |
e17a4113 UW |
605 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
606 | ||
ca3bf3bd | 607 | DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n", |
d93859e2 | 608 | regnum, xtensa_register_name (gdbarch, regnum)); |
ca3bf3bd | 609 | |
6b50c0b0 | 610 | if (regnum == gdbarch_num_regs (gdbarch) |
94a0e877 | 611 | + gdbarch_num_pseudo_regs (gdbarch) -1) |
6b50c0b0 | 612 | regnum = gdbarch_tdep (gdbarch)->a0_base + 1; |
ca3bf3bd | 613 | |
bdb4c075 | 614 | /* Renumber register, if aliase a0..a15 on Windowed ABI. */ |
6b50c0b0 | 615 | if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers |
94a0e877 | 616 | && (regnum >= gdbarch_tdep (gdbarch)->a0_base) |
6b50c0b0 | 617 | && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)) |
ca3bf3bd | 618 | { |
ff7a4c00 | 619 | gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE); |
ca3bf3bd DJ |
620 | unsigned int wb; |
621 | ||
304fe255 | 622 | regcache_raw_read (regcache, |
6b50c0b0 | 623 | gdbarch_tdep (gdbarch)->wb_regnum, buf); |
ee967b5f | 624 | regnum = arreg_number (gdbarch, regnum, |
e17a4113 | 625 | extract_unsigned_integer (buf, 4, byte_order)); |
ca3bf3bd DJ |
626 | } |
627 | ||
628 | /* We can always write 'core' registers. | |
629 | Note: We might have converted Ax->ARy. */ | |
6b50c0b0 | 630 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) |
ca3bf3bd DJ |
631 | regcache_raw_write (regcache, regnum, buffer); |
632 | ||
94a0e877 MG |
633 | /* We have to find out how to deal with priveleged registers. |
634 | Let's treat them as pseudo-registers, but we cannot read/write them. */ | |
635 | ||
636 | else if (regnum < gdbarch_tdep (gdbarch)->a0_base) | |
637 | { | |
638 | return; | |
639 | } | |
ca3bf3bd | 640 | /* Pseudo registers. */ |
f57d151a | 641 | else if (regnum >= 0 |
6b50c0b0 UW |
642 | && regnum < gdbarch_num_regs (gdbarch) |
643 | + gdbarch_num_pseudo_regs (gdbarch)) | |
ca3bf3bd | 644 | { |
6b50c0b0 | 645 | xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; |
ca3bf3bd | 646 | xtensa_register_type_t type = reg->type; |
6b50c0b0 | 647 | int flags = gdbarch_tdep (gdbarch)->target_flags; |
ca3bf3bd | 648 | |
bdb4c075 MG |
649 | /* On most targets, we cannot write registers |
650 | of type "Unknown" or "Unmapped". */ | |
ca3bf3bd DJ |
651 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) |
652 | { | |
653 | if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
654 | { | |
655 | warning (_("cannot write register %s"), | |
d93859e2 | 656 | xtensa_register_name (gdbarch, regnum)); |
ca3bf3bd DJ |
657 | return; |
658 | } | |
659 | } | |
660 | ||
661 | /* Some targets cannot read TIE register files. */ | |
662 | else if (type == xtRegisterTypeTieRegfile) | |
663 | { | |
664 | /* Use 'store' to get register? */ | |
665 | if (flags & xtTargetFlagsUseFetchStore) | |
666 | { | |
667 | warning (_("cannot write register")); | |
668 | return; | |
669 | } | |
670 | ||
671 | /* On some targets (esp. simulators), we can always write | |
672 | the register. */ | |
ca3bf3bd DJ |
673 | else if ((flags & xtTargetFlagsNonVisibleRegs) == 0) |
674 | { | |
675 | warning (_("cannot write register")); | |
676 | return; | |
677 | } | |
678 | } | |
679 | ||
680 | /* We can always write mapped registers. */ | |
681 | else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState) | |
682 | { | |
9c9acae0 | 683 | xtensa_register_write_masked (regcache, reg, buffer); |
ca3bf3bd DJ |
684 | return; |
685 | } | |
686 | ||
687 | /* Assume that we can write the register. */ | |
688 | regcache_raw_write (regcache, regnum, buffer); | |
689 | } | |
ca3bf3bd DJ |
690 | else |
691 | internal_error (__FILE__, __LINE__, | |
692 | _("invalid register number %d"), regnum); | |
693 | } | |
694 | ||
ca3bf3bd DJ |
695 | static struct reggroup *xtensa_ar_reggroup; |
696 | static struct reggroup *xtensa_user_reggroup; | |
697 | static struct reggroup *xtensa_vectra_reggroup; | |
7b871568 | 698 | static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR]; |
ca3bf3bd DJ |
699 | |
700 | static void | |
701 | xtensa_init_reggroups (void) | |
702 | { | |
703 | xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP); | |
704 | xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP); | |
705 | xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP); | |
ca3bf3bd | 706 | |
7b871568 MG |
707 | xtensa_cp[0] = reggroup_new ("cp0", USER_REGGROUP); |
708 | xtensa_cp[1] = reggroup_new ("cp1", USER_REGGROUP); | |
709 | xtensa_cp[2] = reggroup_new ("cp2", USER_REGGROUP); | |
710 | xtensa_cp[3] = reggroup_new ("cp3", USER_REGGROUP); | |
711 | xtensa_cp[4] = reggroup_new ("cp4", USER_REGGROUP); | |
712 | xtensa_cp[5] = reggroup_new ("cp5", USER_REGGROUP); | |
713 | xtensa_cp[6] = reggroup_new ("cp6", USER_REGGROUP); | |
714 | xtensa_cp[7] = reggroup_new ("cp7", USER_REGGROUP); | |
715 | } | |
ca3bf3bd DJ |
716 | |
717 | static void | |
718 | xtensa_add_reggroups (struct gdbarch *gdbarch) | |
719 | { | |
7b871568 MG |
720 | int i; |
721 | ||
722 | /* Predefined groups. */ | |
ca3bf3bd DJ |
723 | reggroup_add (gdbarch, all_reggroup); |
724 | reggroup_add (gdbarch, save_reggroup); | |
725 | reggroup_add (gdbarch, restore_reggroup); | |
726 | reggroup_add (gdbarch, system_reggroup); | |
7b871568 MG |
727 | reggroup_add (gdbarch, vector_reggroup); |
728 | reggroup_add (gdbarch, general_reggroup); | |
729 | reggroup_add (gdbarch, float_reggroup); | |
730 | ||
731 | /* Xtensa-specific groups. */ | |
732 | reggroup_add (gdbarch, xtensa_ar_reggroup); | |
733 | reggroup_add (gdbarch, xtensa_user_reggroup); | |
734 | reggroup_add (gdbarch, xtensa_vectra_reggroup); | |
ca3bf3bd | 735 | |
7b871568 MG |
736 | for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++) |
737 | reggroup_add (gdbarch, xtensa_cp[i]); | |
ca3bf3bd DJ |
738 | } |
739 | ||
7b871568 MG |
740 | static int |
741 | xtensa_coprocessor_register_group (struct reggroup *group) | |
742 | { | |
743 | int i; | |
744 | ||
745 | for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++) | |
746 | if (group == xtensa_cp[i]) | |
747 | return i; | |
748 | ||
749 | return -1; | |
750 | } | |
ca3bf3bd DJ |
751 | |
752 | #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \ | |
753 | | XTENSA_REGISTER_FLAGS_WRITABLE \ | |
754 | | XTENSA_REGISTER_FLAGS_VOLATILE) | |
755 | ||
756 | #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \ | |
757 | | XTENSA_REGISTER_FLAGS_WRITABLE) | |
758 | ||
759 | static int | |
760 | xtensa_register_reggroup_p (struct gdbarch *gdbarch, | |
761 | int regnum, | |
762 | struct reggroup *group) | |
763 | { | |
6b50c0b0 | 764 | xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; |
ca3bf3bd DJ |
765 | xtensa_register_type_t type = reg->type; |
766 | xtensa_register_group_t rg = reg->group; | |
7b871568 | 767 | int cp_number; |
ca3bf3bd DJ |
768 | |
769 | /* First, skip registers that are not visible to this target | |
770 | (unknown and unmapped registers when not using ISS). */ | |
771 | ||
772 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) | |
773 | return 0; | |
774 | if (group == all_reggroup) | |
775 | return 1; | |
776 | if (group == xtensa_ar_reggroup) | |
777 | return rg & xtRegisterGroupAddrReg; | |
778 | if (group == xtensa_user_reggroup) | |
779 | return rg & xtRegisterGroupUser; | |
780 | if (group == float_reggroup) | |
781 | return rg & xtRegisterGroupFloat; | |
782 | if (group == general_reggroup) | |
783 | return rg & xtRegisterGroupGeneral; | |
784 | if (group == float_reggroup) | |
785 | return rg & xtRegisterGroupFloat; | |
786 | if (group == system_reggroup) | |
787 | return rg & xtRegisterGroupState; | |
788 | if (group == vector_reggroup || group == xtensa_vectra_reggroup) | |
789 | return rg & xtRegisterGroupVectra; | |
790 | if (group == save_reggroup || group == restore_reggroup) | |
6b50c0b0 | 791 | return (regnum < gdbarch_num_regs (gdbarch) |
ca3bf3bd | 792 | && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID); |
7b871568 MG |
793 | if ((cp_number = xtensa_coprocessor_register_group (group)) >= 0) |
794 | return rg & (xtRegisterGroupCP0 << cp_number); | |
ca3bf3bd DJ |
795 | else |
796 | return 1; | |
797 | } | |
798 | ||
799 | ||
ca3bf3bd DJ |
800 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
801 | in the general-purpose register set REGSET to register cache | |
bdb4c075 | 802 | REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */ |
ca3bf3bd DJ |
803 | |
804 | static void | |
805 | xtensa_supply_gregset (const struct regset *regset, | |
806 | struct regcache *rc, | |
807 | int regnum, | |
808 | const void *gregs, | |
809 | size_t len) | |
810 | { | |
811 | const xtensa_elf_gregset_t *regs = gregs; | |
6b50c0b0 | 812 | struct gdbarch *gdbarch = get_regcache_arch (rc); |
ca3bf3bd DJ |
813 | int i; |
814 | ||
cce7e648 | 815 | DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum); |
ca3bf3bd | 816 | |
6b50c0b0 UW |
817 | if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1) |
818 | regcache_raw_supply (rc, gdbarch_pc_regnum (gdbarch), (char *) ®s->pc); | |
819 | if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1) | |
820 | regcache_raw_supply (rc, gdbarch_ps_regnum (gdbarch), (char *) ®s->ps); | |
821 | if (regnum == gdbarch_tdep (gdbarch)->wb_regnum || regnum == -1) | |
822 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->wb_regnum, | |
304fe255 | 823 | (char *) ®s->windowbase); |
6b50c0b0 UW |
824 | if (regnum == gdbarch_tdep (gdbarch)->ws_regnum || regnum == -1) |
825 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ws_regnum, | |
304fe255 | 826 | (char *) ®s->windowstart); |
6b50c0b0 UW |
827 | if (regnum == gdbarch_tdep (gdbarch)->lbeg_regnum || regnum == -1) |
828 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lbeg_regnum, | |
304fe255 | 829 | (char *) ®s->lbeg); |
6b50c0b0 UW |
830 | if (regnum == gdbarch_tdep (gdbarch)->lend_regnum || regnum == -1) |
831 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lend_regnum, | |
304fe255 | 832 | (char *) ®s->lend); |
6b50c0b0 UW |
833 | if (regnum == gdbarch_tdep (gdbarch)->lcount_regnum || regnum == -1) |
834 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lcount_regnum, | |
304fe255 | 835 | (char *) ®s->lcount); |
6b50c0b0 UW |
836 | if (regnum == gdbarch_tdep (gdbarch)->sar_regnum || regnum == -1) |
837 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->sar_regnum, | |
304fe255 | 838 | (char *) ®s->sar); |
6b50c0b0 UW |
839 | if (regnum >=gdbarch_tdep (gdbarch)->ar_base |
840 | && regnum < gdbarch_tdep (gdbarch)->ar_base | |
841 | + gdbarch_tdep (gdbarch)->num_aregs) | |
304fe255 UW |
842 | regcache_raw_supply (rc, regnum, |
843 | (char *) ®s->ar[regnum - gdbarch_tdep | |
6b50c0b0 | 844 | (gdbarch)->ar_base]); |
ca3bf3bd DJ |
845 | else if (regnum == -1) |
846 | { | |
6b50c0b0 UW |
847 | for (i = 0; i < gdbarch_tdep (gdbarch)->num_aregs; ++i) |
848 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ar_base + i, | |
304fe255 | 849 | (char *) ®s->ar[i]); |
ca3bf3bd DJ |
850 | } |
851 | } | |
852 | ||
853 | ||
854 | /* Xtensa register set. */ | |
855 | ||
856 | static struct regset | |
857 | xtensa_gregset = | |
858 | { | |
859 | NULL, | |
860 | xtensa_supply_gregset | |
861 | }; | |
862 | ||
863 | ||
bdb4c075 MG |
864 | /* Return the appropriate register set for the core |
865 | section identified by SECT_NAME and SECT_SIZE. */ | |
ca3bf3bd DJ |
866 | |
867 | static const struct regset * | |
868 | xtensa_regset_from_core_section (struct gdbarch *core_arch, | |
869 | const char *sect_name, | |
870 | size_t sect_size) | |
871 | { | |
872 | DEBUGTRACE ("xtensa_regset_from_core_section " | |
cce7e648 | 873 | "(..., sect_name==\"%s\", sect_size==%x)\n", |
ec20a626 | 874 | sect_name, (unsigned int) sect_size); |
ca3bf3bd DJ |
875 | |
876 | if (strcmp (sect_name, ".reg") == 0 | |
877 | && sect_size >= sizeof(xtensa_elf_gregset_t)) | |
878 | return &xtensa_gregset; | |
879 | ||
880 | return NULL; | |
881 | } | |
882 | ||
883 | ||
bdb4c075 | 884 | /* Handling frames. */ |
ca3bf3bd | 885 | |
bdb4c075 MG |
886 | /* Number of registers to save in case of Windowed ABI. */ |
887 | #define XTENSA_NUM_SAVED_AREGS 12 | |
ca3bf3bd | 888 | |
bdb4c075 MG |
889 | /* Frame cache part for Windowed ABI. */ |
890 | typedef struct xtensa_windowed_frame_cache | |
ca3bf3bd | 891 | { |
ee967b5f MG |
892 | int wb; /* WINDOWBASE of the previous frame. */ |
893 | int callsize; /* Call size of this frame. */ | |
581e13c1 MS |
894 | int ws; /* WINDOWSTART of the previous frame. It |
895 | keeps track of life windows only. If there | |
896 | is no bit set for the window, that means it | |
897 | had been already spilled because of window | |
898 | overflow. */ | |
ee967b5f MG |
899 | |
900 | /* Spilled A-registers from the previous frame. | |
901 | AREGS[i] == -1, if corresponding AR is alive. */ | |
ca3bf3bd | 902 | CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS]; |
bdb4c075 MG |
903 | } xtensa_windowed_frame_cache_t; |
904 | ||
905 | /* Call0 ABI Definitions. */ | |
906 | ||
581e13c1 MS |
907 | #define C0_MAXOPDS 3 /* Maximum number of operands for prologue |
908 | analysis. */ | |
bdb4c075 MG |
909 | #define C0_NREGS 16 /* Number of A-registers to track. */ |
910 | #define C0_CLESV 12 /* Callee-saved registers are here and up. */ | |
911 | #define C0_SP 1 /* Register used as SP. */ | |
912 | #define C0_FP 15 /* Register used as FP. */ | |
913 | #define C0_RA 0 /* Register used as return address. */ | |
914 | #define C0_ARGS 2 /* Register used as first arg/retval. */ | |
915 | #define C0_NARGS 6 /* Number of A-regs for args/retvals. */ | |
916 | ||
917 | /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each | |
918 | A-register where the current content of the reg came from (in terms | |
919 | of an original reg and a constant). Negative values of c0_rt[n].fp_reg | |
920 | mean that the orignal content of the register was saved to the stack. | |
921 | c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't | |
922 | know where SP will end up until the entire prologue has been analyzed. */ | |
923 | ||
924 | #define C0_CONST -1 /* fr_reg value if register contains a constant. */ | |
925 | #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */ | |
926 | #define C0_NOSTK -1 /* to_stk value if register has not been stored. */ | |
927 | ||
928 | extern xtensa_isa xtensa_default_isa; | |
929 | ||
930 | typedef struct xtensa_c0reg | |
931 | { | |
932 | int fr_reg; /* original register from which register content | |
933 | is derived, or C0_CONST, or C0_INEXP. */ | |
934 | int fr_ofs; /* constant offset from reg, or immediate value. */ | |
581e13c1 MS |
935 | int to_stk; /* offset from original SP to register (4-byte |
936 | aligned), or C0_NOSTK if register has not | |
937 | been saved. */ | |
bdb4c075 MG |
938 | } xtensa_c0reg_t; |
939 | ||
940 | ||
941 | /* Frame cache part for Call0 ABI. */ | |
942 | typedef struct xtensa_call0_frame_cache | |
943 | { | |
944 | int c0_frmsz; /* Stack frame size. */ | |
581e13c1 MS |
945 | int c0_hasfp; /* Current frame uses frame |
946 | pointer. */ | |
bdb4c075 MG |
947 | int fp_regnum; /* A-register used as FP. */ |
948 | int c0_fp; /* Actual value of frame pointer. */ | |
949 | xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */ | |
950 | } xtensa_call0_frame_cache_t; | |
951 | ||
952 | typedef struct xtensa_frame_cache | |
953 | { | |
ee967b5f | 954 | CORE_ADDR base; /* Stack pointer of this frame. */ |
bdb4c075 | 955 | CORE_ADDR pc; /* PC at the entry point to the function. */ |
ee967b5f | 956 | CORE_ADDR ra; /* The raw return address (without CALLINC). */ |
9f61f19b | 957 | CORE_ADDR ps; /* The PS register of this frame. */ |
ee967b5f | 958 | CORE_ADDR prev_sp; /* Stack Pointer of the previous frame. */ |
bdb4c075 MG |
959 | int call0; /* It's a call0 framework (else windowed). */ |
960 | union | |
961 | { | |
962 | xtensa_windowed_frame_cache_t wd; /* call0 == false. */ | |
963 | xtensa_call0_frame_cache_t c0; /* call0 == true. */ | |
964 | }; | |
ca3bf3bd DJ |
965 | } xtensa_frame_cache_t; |
966 | ||
967 | ||
968 | static struct xtensa_frame_cache * | |
bdb4c075 | 969 | xtensa_alloc_frame_cache (int windowed) |
ca3bf3bd DJ |
970 | { |
971 | xtensa_frame_cache_t *cache; | |
972 | int i; | |
973 | ||
974 | DEBUGTRACE ("xtensa_alloc_frame_cache ()\n"); | |
975 | ||
976 | cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t); | |
977 | ||
978 | cache->base = 0; | |
979 | cache->pc = 0; | |
980 | cache->ra = 0; | |
ca3bf3bd | 981 | cache->ps = 0; |
ca3bf3bd | 982 | cache->prev_sp = 0; |
bdb4c075 MG |
983 | cache->call0 = !windowed; |
984 | if (cache->call0) | |
985 | { | |
986 | cache->c0.c0_frmsz = -1; | |
987 | cache->c0.c0_hasfp = 0; | |
988 | cache->c0.fp_regnum = -1; | |
989 | cache->c0.c0_fp = -1; | |
ca3bf3bd | 990 | |
bdb4c075 MG |
991 | for (i = 0; i < C0_NREGS; i++) |
992 | { | |
993 | cache->c0.c0_rt[i].fr_reg = i; | |
994 | cache->c0.c0_rt[i].fr_ofs = 0; | |
995 | cache->c0.c0_rt[i].to_stk = C0_NOSTK; | |
996 | } | |
997 | } | |
998 | else | |
999 | { | |
1000 | cache->wd.wb = 0; | |
ee967b5f | 1001 | cache->wd.ws = 0; |
bdb4c075 | 1002 | cache->wd.callsize = -1; |
ca3bf3bd | 1003 | |
bdb4c075 MG |
1004 | for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++) |
1005 | cache->wd.aregs[i] = -1; | |
1006 | } | |
ca3bf3bd DJ |
1007 | return cache; |
1008 | } | |
1009 | ||
1010 | ||
1011 | static CORE_ADDR | |
1012 | xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) | |
1013 | { | |
1014 | return address & ~15; | |
1015 | } | |
1016 | ||
1017 | ||
1018 | static CORE_ADDR | |
1019 | xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1020 | { | |
ff7a4c00 | 1021 | gdb_byte buf[8]; |
0dfff4cb | 1022 | CORE_ADDR pc; |
ca3bf3bd | 1023 | |
a74ce742 PM |
1024 | DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n", |
1025 | host_address_to_string (next_frame)); | |
ca3bf3bd | 1026 | |
6b50c0b0 | 1027 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1028 | pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
ca3bf3bd | 1029 | |
0dfff4cb | 1030 | DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc); |
ca3bf3bd | 1031 | |
0dfff4cb | 1032 | return pc; |
ca3bf3bd DJ |
1033 | } |
1034 | ||
1035 | ||
1036 | static struct frame_id | |
5142f611 | 1037 | xtensa_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
ca3bf3bd DJ |
1038 | { |
1039 | CORE_ADDR pc, fp; | |
ca3bf3bd | 1040 | |
5142f611 | 1041 | /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */ |
ca3bf3bd | 1042 | |
5142f611 MG |
1043 | pc = get_frame_pc (this_frame); |
1044 | fp = get_frame_register_unsigned | |
1045 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1); | |
ca3bf3bd DJ |
1046 | |
1047 | /* Make dummy frame ID unique by adding a constant. */ | |
bdb4c075 | 1048 | return frame_id_build (fp + SP_ALIGNMENT, pc); |
ca3bf3bd DJ |
1049 | } |
1050 | ||
ee967b5f MG |
1051 | /* Returns the best guess about which register is a frame pointer |
1052 | for the function containing CURRENT_PC. */ | |
1053 | ||
d4709618 MG |
1054 | #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */ |
1055 | #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */ | |
ee967b5f MG |
1056 | |
1057 | static unsigned int | |
1058 | xtensa_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR current_pc) | |
1059 | { | |
1060 | #define RETURN_FP goto done | |
1061 | ||
1062 | unsigned int fp_regnum = gdbarch_tdep (gdbarch)->a0_base + 1; | |
1063 | CORE_ADDR start_addr; | |
1064 | xtensa_isa isa; | |
1065 | xtensa_insnbuf ins, slot; | |
1066 | char ibuf[XTENSA_ISA_BSZ]; | |
1067 | CORE_ADDR ia, bt, ba; | |
1068 | xtensa_format ifmt; | |
1069 | int ilen, islots, is; | |
1070 | xtensa_opcode opc; | |
1071 | const char *opcname; | |
1072 | ||
1073 | find_pc_partial_function (current_pc, NULL, &start_addr, NULL); | |
1074 | if (start_addr == 0) | |
1075 | return fp_regnum; | |
1076 | ||
1077 | if (!xtensa_default_isa) | |
1078 | xtensa_default_isa = xtensa_isa_init (0, 0); | |
1079 | isa = xtensa_default_isa; | |
1080 | gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); | |
1081 | ins = xtensa_insnbuf_alloc (isa); | |
1082 | slot = xtensa_insnbuf_alloc (isa); | |
1083 | ba = 0; | |
1084 | ||
1085 | for (ia = start_addr, bt = ia; ia < current_pc ; ia += ilen) | |
1086 | { | |
1087 | if (ia + xtensa_isa_maxlength (isa) > bt) | |
1088 | { | |
1089 | ba = ia; | |
1090 | bt = (ba + XTENSA_ISA_BSZ) < current_pc | |
1091 | ? ba + XTENSA_ISA_BSZ : current_pc; | |
d4709618 MG |
1092 | if (target_read_memory (ba, ibuf, bt - ba) != 0) |
1093 | RETURN_FP; | |
ee967b5f MG |
1094 | } |
1095 | ||
1096 | xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); | |
1097 | ifmt = xtensa_format_decode (isa, ins); | |
1098 | if (ifmt == XTENSA_UNDEFINED) | |
1099 | RETURN_FP; | |
1100 | ilen = xtensa_format_length (isa, ifmt); | |
1101 | if (ilen == XTENSA_UNDEFINED) | |
1102 | RETURN_FP; | |
1103 | islots = xtensa_format_num_slots (isa, ifmt); | |
1104 | if (islots == XTENSA_UNDEFINED) | |
1105 | RETURN_FP; | |
1106 | ||
1107 | for (is = 0; is < islots; ++is) | |
1108 | { | |
1109 | if (xtensa_format_get_slot (isa, ifmt, is, ins, slot)) | |
1110 | RETURN_FP; | |
1111 | ||
1112 | opc = xtensa_opcode_decode (isa, ifmt, is, slot); | |
1113 | if (opc == XTENSA_UNDEFINED) | |
1114 | RETURN_FP; | |
1115 | ||
1116 | opcname = xtensa_opcode_name (isa, opc); | |
1117 | ||
1118 | if (strcasecmp (opcname, "mov.n") == 0 | |
1119 | || strcasecmp (opcname, "or") == 0) | |
1120 | { | |
1121 | unsigned int register_operand; | |
1122 | ||
1123 | /* Possible candidate for setting frame pointer | |
581e13c1 | 1124 | from A1. This is what we are looking for. */ |
ee967b5f MG |
1125 | |
1126 | if (xtensa_operand_get_field (isa, opc, 1, ifmt, | |
1127 | is, slot, ®ister_operand) != 0) | |
1128 | RETURN_FP; | |
1129 | if (xtensa_operand_decode (isa, opc, 1, ®ister_operand) != 0) | |
1130 | RETURN_FP; | |
1131 | if (register_operand == 1) /* Mov{.n} FP A1. */ | |
1132 | { | |
1133 | if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, | |
1134 | ®ister_operand) != 0) | |
1135 | RETURN_FP; | |
1136 | if (xtensa_operand_decode (isa, opc, 0, | |
1137 | ®ister_operand) != 0) | |
1138 | RETURN_FP; | |
1139 | ||
581e13c1 MS |
1140 | fp_regnum |
1141 | = gdbarch_tdep (gdbarch)->a0_base + register_operand; | |
ee967b5f MG |
1142 | RETURN_FP; |
1143 | } | |
1144 | } | |
1145 | ||
1146 | if ( | |
1147 | /* We have problems decoding the memory. */ | |
1148 | opcname == NULL | |
1149 | || strcasecmp (opcname, "ill") == 0 | |
1150 | || strcasecmp (opcname, "ill.n") == 0 | |
1151 | /* Hit planted breakpoint. */ | |
1152 | || strcasecmp (opcname, "break") == 0 | |
1153 | || strcasecmp (opcname, "break.n") == 0 | |
1154 | /* Flow control instructions finish prologue. */ | |
1155 | || xtensa_opcode_is_branch (isa, opc) > 0 | |
1156 | || xtensa_opcode_is_jump (isa, opc) > 0 | |
1157 | || xtensa_opcode_is_loop (isa, opc) > 0 | |
1158 | || xtensa_opcode_is_call (isa, opc) > 0 | |
1159 | || strcasecmp (opcname, "simcall") == 0 | |
1160 | || strcasecmp (opcname, "syscall") == 0) | |
1161 | /* Can not continue analysis. */ | |
1162 | RETURN_FP; | |
1163 | } | |
1164 | } | |
1165 | done: | |
1166 | xtensa_insnbuf_free(isa, slot); | |
1167 | xtensa_insnbuf_free(isa, ins); | |
1168 | return fp_regnum; | |
1169 | } | |
1170 | ||
bdb4c075 MG |
1171 | /* The key values to identify the frame using "cache" are |
1172 | ||
ee967b5f | 1173 | cache->base = SP (or best guess about FP) of this frame; |
bdb4c075 | 1174 | cache->pc = entry-PC (entry point of the frame function); |
581e13c1 | 1175 | cache->prev_sp = SP of the previous frame. */ |
bdb4c075 MG |
1176 | |
1177 | static void | |
5142f611 | 1178 | call0_frame_cache (struct frame_info *this_frame, |
bdb4c075 | 1179 | xtensa_frame_cache_t *cache, |
9f61f19b | 1180 | CORE_ADDR pc, CORE_ADDR litbase); |
ca3bf3bd DJ |
1181 | |
1182 | static struct xtensa_frame_cache * | |
5142f611 | 1183 | xtensa_frame_cache (struct frame_info *this_frame, void **this_cache) |
ca3bf3bd DJ |
1184 | { |
1185 | xtensa_frame_cache_t *cache; | |
ca3bf3bd | 1186 | CORE_ADDR ra, wb, ws, pc, sp, ps; |
5142f611 | 1187 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
e17a4113 | 1188 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
ee967b5f | 1189 | unsigned int fp_regnum; |
ca3bf3bd | 1190 | char op1; |
bdb4c075 | 1191 | int windowed; |
ca3bf3bd | 1192 | |
ca3bf3bd DJ |
1193 | if (*this_cache) |
1194 | return *this_cache; | |
1195 | ||
9f61f19b MG |
1196 | ps = get_frame_register_unsigned (this_frame, gdbarch_ps_regnum (gdbarch)); |
1197 | windowed = windowing_enabled (ps); | |
bdb4c075 | 1198 | |
ca3bf3bd | 1199 | /* Get pristine xtensa-frame. */ |
bdb4c075 | 1200 | cache = xtensa_alloc_frame_cache (windowed); |
ca3bf3bd DJ |
1201 | *this_cache = cache; |
1202 | ||
9f61f19b | 1203 | pc = get_frame_register_unsigned (this_frame, gdbarch_pc_regnum (gdbarch)); |
ca3bf3bd | 1204 | |
bdb4c075 | 1205 | if (windowed) |
ca3bf3bd | 1206 | { |
bdb4c075 | 1207 | /* Get WINDOWBASE, WINDOWSTART, and PS registers. */ |
5142f611 MG |
1208 | wb = get_frame_register_unsigned (this_frame, |
1209 | gdbarch_tdep (gdbarch)->wb_regnum); | |
1210 | ws = get_frame_register_unsigned (this_frame, | |
1211 | gdbarch_tdep (gdbarch)->ws_regnum); | |
ca3bf3bd | 1212 | |
e17a4113 | 1213 | op1 = read_memory_integer (pc, 1, byte_order); |
91d8eb23 | 1214 | if (XTENSA_IS_ENTRY (gdbarch, op1)) |
ca3bf3bd | 1215 | { |
bdb4c075 | 1216 | int callinc = CALLINC (ps); |
5142f611 MG |
1217 | ra = get_frame_register_unsigned |
1218 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + callinc * 4); | |
bdb4c075 MG |
1219 | |
1220 | /* ENTRY hasn't been executed yet, therefore callsize is still 0. */ | |
1221 | cache->wd.callsize = 0; | |
1222 | cache->wd.wb = wb; | |
1223 | cache->wd.ws = ws; | |
5142f611 MG |
1224 | cache->prev_sp = get_frame_register_unsigned |
1225 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1); | |
ee967b5f MG |
1226 | |
1227 | /* This only can be the outermost frame since we are | |
1228 | just about to execute ENTRY. SP hasn't been set yet. | |
1229 | We can assume any frame size, because it does not | |
1230 | matter, and, let's fake frame base in cache. */ | |
1231 | cache->base = cache->prev_sp + 16; | |
1232 | ||
1233 | cache->pc = pc; | |
1234 | cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff); | |
1235 | cache->ps = (ps & ~PS_CALLINC_MASK) | |
1236 | | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT); | |
1237 | ||
1238 | return cache; | |
bdb4c075 MG |
1239 | } |
1240 | else | |
1241 | { | |
ee967b5f | 1242 | fp_regnum = xtensa_scan_prologue (gdbarch, pc); |
5142f611 MG |
1243 | ra = get_frame_register_unsigned (this_frame, |
1244 | gdbarch_tdep (gdbarch)->a0_base); | |
bdb4c075 | 1245 | cache->wd.callsize = WINSIZE (ra); |
304fe255 | 1246 | cache->wd.wb = (wb - cache->wd.callsize / 4) |
6b50c0b0 | 1247 | & (gdbarch_tdep (gdbarch)->num_aregs / 4 - 1); |
bdb4c075 | 1248 | cache->wd.ws = ws & ~(1 << wb); |
ca3bf3bd | 1249 | |
5142f611 | 1250 | cache->pc = get_frame_func (this_frame); |
f6402f18 | 1251 | cache->ra = (pc & 0xc0000000) | (ra & 0x3fffffff); |
ee967b5f MG |
1252 | cache->ps = (ps & ~PS_CALLINC_MASK) |
1253 | | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT); | |
1254 | } | |
bdb4c075 MG |
1255 | |
1256 | if (cache->wd.ws == 0) | |
ca3bf3bd | 1257 | { |
bdb4c075 | 1258 | int i; |
ca3bf3bd | 1259 | |
bdb4c075 | 1260 | /* Set A0...A3. */ |
5142f611 MG |
1261 | sp = get_frame_register_unsigned |
1262 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1) - 16; | |
bdb4c075 MG |
1263 | |
1264 | for (i = 0; i < 4; i++, sp += 4) | |
1265 | { | |
1266 | cache->wd.aregs[i] = sp; | |
1267 | } | |
ca3bf3bd | 1268 | |
bdb4c075 | 1269 | if (cache->wd.callsize > 4) |
ca3bf3bd | 1270 | { |
bdb4c075 | 1271 | /* Set A4...A7/A11. */ |
ee967b5f MG |
1272 | /* Get the SP of the frame previous to the previous one. |
1273 | To achieve this, we have to dereference SP twice. */ | |
e17a4113 UW |
1274 | sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order); |
1275 | sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order); | |
bdb4c075 MG |
1276 | sp -= cache->wd.callsize * 4; |
1277 | ||
ee967b5f | 1278 | for ( i = 4; i < cache->wd.callsize; i++, sp += 4) |
bdb4c075 MG |
1279 | { |
1280 | cache->wd.aregs[i] = sp; | |
1281 | } | |
ca3bf3bd DJ |
1282 | } |
1283 | } | |
ca3bf3bd | 1284 | |
bdb4c075 | 1285 | if ((cache->prev_sp == 0) && ( ra != 0 )) |
581e13c1 MS |
1286 | /* If RA is equal to 0 this frame is an outermost frame. |
1287 | Leave cache->prev_sp unchanged marking the boundary of the | |
1288 | frame stack. */ | |
ca3bf3bd | 1289 | { |
ee967b5f | 1290 | if ((cache->wd.ws & (1 << cache->wd.wb)) == 0) |
bdb4c075 MG |
1291 | { |
1292 | /* Register window overflow already happened. | |
1293 | We can read caller's SP from the proper spill loction. */ | |
5142f611 MG |
1294 | sp = get_frame_register_unsigned |
1295 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1); | |
e17a4113 | 1296 | cache->prev_sp = read_memory_integer (sp - 12, 4, byte_order); |
bdb4c075 MG |
1297 | } |
1298 | else | |
1299 | { | |
1300 | /* Read caller's frame SP directly from the previous window. */ | |
ee967b5f | 1301 | int regnum = arreg_number |
91d8eb23 | 1302 | (gdbarch, gdbarch_tdep (gdbarch)->a0_base + 1, |
304fe255 | 1303 | cache->wd.wb); |
ca3bf3bd | 1304 | |
581e13c1 MS |
1305 | cache->prev_sp = get_frame_register_unsigned (this_frame, |
1306 | regnum); | |
bdb4c075 | 1307 | } |
ca3bf3bd DJ |
1308 | } |
1309 | } | |
bdb4c075 MG |
1310 | else /* Call0 framework. */ |
1311 | { | |
9f61f19b MG |
1312 | unsigned int litbase_regnum = gdbarch_tdep (gdbarch)->litbase_regnum; |
1313 | CORE_ADDR litbase = (litbase_regnum == -1) | |
1314 | ? 0 : get_frame_register_unsigned (this_frame, litbase_regnum); | |
1315 | ||
1316 | call0_frame_cache (this_frame, cache, pc, litbase); | |
ee967b5f | 1317 | fp_regnum = cache->c0.fp_regnum; |
bdb4c075 | 1318 | } |
ca3bf3bd | 1319 | |
5142f611 | 1320 | cache->base = get_frame_register_unsigned (this_frame, fp_regnum); |
ca3bf3bd | 1321 | |
ca3bf3bd DJ |
1322 | return cache; |
1323 | } | |
1324 | ||
ca3bf3bd | 1325 | static void |
5142f611 | 1326 | xtensa_frame_this_id (struct frame_info *this_frame, |
ca3bf3bd DJ |
1327 | void **this_cache, |
1328 | struct frame_id *this_id) | |
1329 | { | |
1330 | struct xtensa_frame_cache *cache = | |
5142f611 | 1331 | xtensa_frame_cache (this_frame, this_cache); |
ca3bf3bd DJ |
1332 | |
1333 | if (cache->prev_sp == 0) | |
1334 | return; | |
1335 | ||
5142f611 | 1336 | (*this_id) = frame_id_build (cache->prev_sp, cache->pc); |
bdb4c075 | 1337 | } |
ca3bf3bd | 1338 | |
5142f611 MG |
1339 | static struct value * |
1340 | xtensa_frame_prev_register (struct frame_info *this_frame, | |
ca3bf3bd | 1341 | void **this_cache, |
5142f611 | 1342 | int regnum) |
ca3bf3bd | 1343 | { |
5142f611 MG |
1344 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1345 | struct xtensa_frame_cache *cache; | |
1346 | ULONGEST saved_reg = 0; | |
ca3bf3bd DJ |
1347 | int done = 1; |
1348 | ||
5142f611 MG |
1349 | if (*this_cache == NULL) |
1350 | *this_cache = xtensa_frame_cache (this_frame, this_cache); | |
1351 | cache = *this_cache; | |
ca3bf3bd | 1352 | |
6b50c0b0 | 1353 | if (regnum ==gdbarch_pc_regnum (gdbarch)) |
bdb4c075 | 1354 | saved_reg = cache->ra; |
6b50c0b0 | 1355 | else if (regnum == gdbarch_tdep (gdbarch)->a0_base + 1) |
bdb4c075 MG |
1356 | saved_reg = cache->prev_sp; |
1357 | else if (!cache->call0) | |
ca3bf3bd | 1358 | { |
6b50c0b0 | 1359 | if (regnum == gdbarch_tdep (gdbarch)->ws_regnum) |
ee967b5f | 1360 | saved_reg = cache->wd.ws; |
6b50c0b0 | 1361 | else if (regnum == gdbarch_tdep (gdbarch)->wb_regnum) |
bdb4c075 | 1362 | saved_reg = cache->wd.wb; |
6b50c0b0 | 1363 | else if (regnum == gdbarch_ps_regnum (gdbarch)) |
bdb4c075 | 1364 | saved_reg = cache->ps; |
ca3bf3bd | 1365 | else |
bdb4c075 | 1366 | done = 0; |
ca3bf3bd | 1367 | } |
ca3bf3bd DJ |
1368 | else |
1369 | done = 0; | |
1370 | ||
1371 | if (done) | |
5142f611 | 1372 | return frame_unwind_got_constant (this_frame, regnum, saved_reg); |
ca3bf3bd | 1373 | |
bdb4c075 | 1374 | if (!cache->call0) /* Windowed ABI. */ |
ca3bf3bd | 1375 | { |
ee967b5f MG |
1376 | /* Convert A-register numbers to AR-register numbers, |
1377 | if we deal with A-register. */ | |
94a0e877 | 1378 | if (regnum >= gdbarch_tdep (gdbarch)->a0_base |
6b50c0b0 | 1379 | && regnum <= gdbarch_tdep (gdbarch)->a0_base + 15) |
ee967b5f | 1380 | regnum = arreg_number (gdbarch, regnum, cache->wd.wb); |
ca3bf3bd | 1381 | |
ee967b5f | 1382 | /* Check, if we deal with AR-register saved on stack. */ |
6b50c0b0 UW |
1383 | if (regnum >= gdbarch_tdep (gdbarch)->ar_base |
1384 | && regnum <= (gdbarch_tdep (gdbarch)->ar_base | |
1385 | + gdbarch_tdep (gdbarch)->num_aregs)) | |
bdb4c075 | 1386 | { |
ee967b5f | 1387 | int areg = areg_number (gdbarch, regnum, cache->wd.wb); |
ca3bf3bd | 1388 | |
bdb4c075 MG |
1389 | if (areg >= 0 |
1390 | && areg < XTENSA_NUM_SAVED_AREGS | |
1391 | && cache->wd.aregs[areg] != -1) | |
5142f611 MG |
1392 | return frame_unwind_got_memory (this_frame, regnum, |
1393 | cache->wd.aregs[areg]); | |
ca3bf3bd DJ |
1394 | } |
1395 | } | |
bdb4c075 MG |
1396 | else /* Call0 ABI. */ |
1397 | { | |
6b50c0b0 UW |
1398 | int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base |
1399 | && regnum <= (gdbarch_tdep (gdbarch)->ar_base | |
304fe255 | 1400 | + C0_NREGS)) |
6b50c0b0 | 1401 | ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum; |
ca3bf3bd | 1402 | |
bdb4c075 MG |
1403 | if (reg < C0_NREGS) |
1404 | { | |
1405 | CORE_ADDR spe; | |
1406 | int stkofs; | |
1407 | ||
1408 | /* If register was saved in the prologue, retrieve it. */ | |
1409 | stkofs = cache->c0.c0_rt[reg].to_stk; | |
1410 | if (stkofs != C0_NOSTK) | |
1411 | { | |
1412 | /* Determine SP on entry based on FP. */ | |
1413 | spe = cache->c0.c0_fp | |
1414 | - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs; | |
5142f611 | 1415 | |
581e13c1 MS |
1416 | return frame_unwind_got_memory (this_frame, regnum, |
1417 | spe + stkofs); | |
bdb4c075 MG |
1418 | } |
1419 | } | |
1420 | } | |
1421 | ||
1422 | /* All other registers have been either saved to | |
1423 | the stack or are still alive in the processor. */ | |
ca3bf3bd | 1424 | |
5142f611 | 1425 | return frame_unwind_got_register (this_frame, regnum, regnum); |
ca3bf3bd DJ |
1426 | } |
1427 | ||
1428 | ||
1429 | static const struct frame_unwind | |
5142f611 | 1430 | xtensa_unwind = |
ca3bf3bd DJ |
1431 | { |
1432 | NORMAL_FRAME, | |
1433 | xtensa_frame_this_id, | |
5142f611 MG |
1434 | xtensa_frame_prev_register, |
1435 | NULL, | |
1436 | default_frame_sniffer | |
ca3bf3bd DJ |
1437 | }; |
1438 | ||
ca3bf3bd | 1439 | static CORE_ADDR |
5142f611 | 1440 | xtensa_frame_base_address (struct frame_info *this_frame, void **this_cache) |
ca3bf3bd DJ |
1441 | { |
1442 | struct xtensa_frame_cache *cache = | |
5142f611 | 1443 | xtensa_frame_cache (this_frame, this_cache); |
ca3bf3bd DJ |
1444 | |
1445 | return cache->base; | |
1446 | } | |
1447 | ||
1448 | static const struct frame_base | |
1449 | xtensa_frame_base = | |
1450 | { | |
5142f611 | 1451 | &xtensa_unwind, |
ca3bf3bd DJ |
1452 | xtensa_frame_base_address, |
1453 | xtensa_frame_base_address, | |
1454 | xtensa_frame_base_address | |
1455 | }; | |
1456 | ||
1457 | ||
1458 | static void | |
1459 | xtensa_extract_return_value (struct type *type, | |
1460 | struct regcache *regcache, | |
1461 | void *dst) | |
1462 | { | |
6b50c0b0 | 1463 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
ca3bf3bd DJ |
1464 | bfd_byte *valbuf = dst; |
1465 | int len = TYPE_LENGTH (type); | |
1466 | ULONGEST pc, wb; | |
1467 | int callsize, areg; | |
1468 | int offset = 0; | |
1469 | ||
1470 | DEBUGTRACE ("xtensa_extract_return_value (...)\n"); | |
1471 | ||
1472 | gdb_assert(len > 0); | |
1473 | ||
6b50c0b0 | 1474 | if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
bdb4c075 MG |
1475 | { |
1476 | /* First, we have to find the caller window in the register file. */ | |
6b50c0b0 | 1477 | regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc); |
91d8eb23 | 1478 | callsize = extract_call_winsize (gdbarch, pc); |
ca3bf3bd | 1479 | |
bdb4c075 MG |
1480 | /* On Xtensa, we can return up to 4 words (or 2 for call12). */ |
1481 | if (len > (callsize > 8 ? 8 : 16)) | |
1482 | internal_error (__FILE__, __LINE__, | |
581e13c1 MS |
1483 | _("cannot extract return value of %d bytes long"), |
1484 | len); | |
ca3bf3bd | 1485 | |
bdb4c075 MG |
1486 | /* Get the register offset of the return |
1487 | register (A2) in the caller window. */ | |
304fe255 | 1488 | regcache_raw_read_unsigned |
6b50c0b0 | 1489 | (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb); |
ee967b5f | 1490 | areg = arreg_number (gdbarch, |
91d8eb23 | 1491 | gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb); |
bdb4c075 MG |
1492 | } |
1493 | else | |
1494 | { | |
1495 | /* No windowing hardware - Call0 ABI. */ | |
94a0e877 | 1496 | areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS; |
bdb4c075 | 1497 | } |
ca3bf3bd DJ |
1498 | |
1499 | DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len); | |
1500 | ||
6b50c0b0 | 1501 | if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1502 | offset = 4 - len; |
1503 | ||
1504 | for (; len > 0; len -= 4, areg++, valbuf += 4) | |
1505 | { | |
1506 | if (len < 4) | |
1507 | regcache_raw_read_part (regcache, areg, offset, len, valbuf); | |
1508 | else | |
1509 | regcache_raw_read (regcache, areg, valbuf); | |
1510 | } | |
1511 | } | |
1512 | ||
1513 | ||
1514 | static void | |
1515 | xtensa_store_return_value (struct type *type, | |
1516 | struct regcache *regcache, | |
1517 | const void *dst) | |
1518 | { | |
6b50c0b0 | 1519 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
ca3bf3bd DJ |
1520 | const bfd_byte *valbuf = dst; |
1521 | unsigned int areg; | |
1522 | ULONGEST pc, wb; | |
1523 | int callsize; | |
1524 | int len = TYPE_LENGTH (type); | |
1525 | int offset = 0; | |
1526 | ||
1527 | DEBUGTRACE ("xtensa_store_return_value (...)\n"); | |
1528 | ||
6b50c0b0 | 1529 | if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
bdb4c075 | 1530 | { |
6b50c0b0 UW |
1531 | regcache_raw_read_unsigned |
1532 | (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb); | |
1533 | regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc); | |
91d8eb23 | 1534 | callsize = extract_call_winsize (gdbarch, pc); |
ca3bf3bd | 1535 | |
bdb4c075 MG |
1536 | if (len > (callsize > 8 ? 8 : 16)) |
1537 | internal_error (__FILE__, __LINE__, | |
1538 | _("unimplemented for this length: %d"), | |
1539 | TYPE_LENGTH (type)); | |
ee967b5f MG |
1540 | areg = arreg_number (gdbarch, |
1541 | gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb); | |
ca3bf3bd | 1542 | |
bdb4c075 | 1543 | DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n", |
ca3bf3bd | 1544 | callsize, (int) wb); |
bdb4c075 MG |
1545 | } |
1546 | else | |
1547 | { | |
94a0e877 | 1548 | areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS; |
bdb4c075 | 1549 | } |
ca3bf3bd | 1550 | |
6b50c0b0 | 1551 | if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1552 | offset = 4 - len; |
1553 | ||
ca3bf3bd DJ |
1554 | for (; len > 0; len -= 4, areg++, valbuf += 4) |
1555 | { | |
1556 | if (len < 4) | |
1557 | regcache_raw_write_part (regcache, areg, offset, len, valbuf); | |
1558 | else | |
1559 | regcache_raw_write (regcache, areg, valbuf); | |
1560 | } | |
1561 | } | |
1562 | ||
1563 | ||
bdb4c075 | 1564 | static enum return_value_convention |
ca3bf3bd | 1565 | xtensa_return_value (struct gdbarch *gdbarch, |
c055b101 | 1566 | struct type *func_type, |
ca3bf3bd DJ |
1567 | struct type *valtype, |
1568 | struct regcache *regcache, | |
1569 | gdb_byte *readbuf, | |
1570 | const gdb_byte *writebuf) | |
1571 | { | |
bdb4c075 | 1572 | /* Structures up to 16 bytes are returned in registers. */ |
ca3bf3bd DJ |
1573 | |
1574 | int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT | |
1575 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
1576 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
1577 | && TYPE_LENGTH (valtype) > 16); | |
1578 | ||
1579 | if (struct_return) | |
1580 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1581 | ||
1582 | DEBUGTRACE ("xtensa_return_value(...)\n"); | |
1583 | ||
1584 | if (writebuf != NULL) | |
1585 | { | |
1586 | xtensa_store_return_value (valtype, regcache, writebuf); | |
1587 | } | |
1588 | ||
1589 | if (readbuf != NULL) | |
1590 | { | |
1591 | gdb_assert (!struct_return); | |
1592 | xtensa_extract_return_value (valtype, regcache, readbuf); | |
1593 | } | |
1594 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1595 | } | |
1596 | ||
1597 | ||
1598 | /* DUMMY FRAME */ | |
1599 | ||
1600 | static CORE_ADDR | |
1601 | xtensa_push_dummy_call (struct gdbarch *gdbarch, | |
1602 | struct value *function, | |
1603 | struct regcache *regcache, | |
1604 | CORE_ADDR bp_addr, | |
1605 | int nargs, | |
1606 | struct value **args, | |
1607 | CORE_ADDR sp, | |
1608 | int struct_return, | |
1609 | CORE_ADDR struct_addr) | |
1610 | { | |
e17a4113 | 1611 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
ca3bf3bd DJ |
1612 | int i; |
1613 | int size, onstack_size; | |
ff7a4c00 | 1614 | gdb_byte *buf = (gdb_byte *) alloca (16); |
ca3bf3bd DJ |
1615 | CORE_ADDR ra, ps; |
1616 | struct argument_info | |
1617 | { | |
1618 | const bfd_byte *contents; | |
1619 | int length; | |
1620 | int onstack; /* onstack == 0 => in reg */ | |
1621 | int align; /* alignment */ | |
1622 | union | |
1623 | { | |
581e13c1 MS |
1624 | int offset; /* stack offset if on stack. */ |
1625 | int regno; /* regno if in register. */ | |
ca3bf3bd DJ |
1626 | } u; |
1627 | }; | |
1628 | ||
1629 | struct argument_info *arg_info = | |
1630 | (struct argument_info *) alloca (nargs * sizeof (struct argument_info)); | |
1631 | ||
1632 | CORE_ADDR osp = sp; | |
1633 | ||
1634 | DEBUGTRACE ("xtensa_push_dummy_call (...)\n"); | |
1635 | ||
1636 | if (xtensa_debug_level > 3) | |
1637 | { | |
1638 | int i; | |
1639 | DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs); | |
1640 | DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, " | |
1641 | "struct_addr=0x%x\n", | |
1642 | (int) sp, (int) struct_return, (int) struct_addr); | |
1643 | ||
1644 | for (i = 0; i < nargs; i++) | |
1645 | { | |
1646 | struct value *arg = args[i]; | |
1647 | struct type *arg_type = check_typedef (value_type (arg)); | |
3329c4b5 PM |
1648 | fprintf_unfiltered (gdb_stdlog, "%2d: %s %3d ", i, |
1649 | host_address_to_string (arg), | |
1650 | TYPE_LENGTH (arg_type)); | |
ca3bf3bd DJ |
1651 | switch (TYPE_CODE (arg_type)) |
1652 | { | |
1653 | case TYPE_CODE_INT: | |
1654 | fprintf_unfiltered (gdb_stdlog, "int"); | |
1655 | break; | |
1656 | case TYPE_CODE_STRUCT: | |
1657 | fprintf_unfiltered (gdb_stdlog, "struct"); | |
1658 | break; | |
1659 | default: | |
1660 | fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type)); | |
1661 | break; | |
1662 | } | |
3329c4b5 PM |
1663 | fprintf_unfiltered (gdb_stdlog, " %s\n", |
1664 | host_address_to_string (value_contents (arg))); | |
ca3bf3bd DJ |
1665 | } |
1666 | } | |
1667 | ||
1668 | /* First loop: collect information. | |
1669 | Cast into type_long. (This shouldn't happen often for C because | |
1670 | GDB already does this earlier.) It's possible that GDB could | |
1671 | do it all the time but it's harmless to leave this code here. */ | |
1672 | ||
1673 | size = 0; | |
1674 | onstack_size = 0; | |
1675 | i = 0; | |
1676 | ||
1677 | if (struct_return) | |
1678 | size = REGISTER_SIZE; | |
1679 | ||
1680 | for (i = 0; i < nargs; i++) | |
1681 | { | |
1682 | struct argument_info *info = &arg_info[i]; | |
1683 | struct value *arg = args[i]; | |
1684 | struct type *arg_type = check_typedef (value_type (arg)); | |
1685 | ||
1686 | switch (TYPE_CODE (arg_type)) | |
1687 | { | |
1688 | case TYPE_CODE_INT: | |
1689 | case TYPE_CODE_BOOL: | |
1690 | case TYPE_CODE_CHAR: | |
1691 | case TYPE_CODE_RANGE: | |
1692 | case TYPE_CODE_ENUM: | |
1693 | ||
1694 | /* Cast argument to long if necessary as the mask does it too. */ | |
0dfff4cb UW |
1695 | if (TYPE_LENGTH (arg_type) |
1696 | < TYPE_LENGTH (builtin_type (gdbarch)->builtin_long)) | |
ca3bf3bd | 1697 | { |
0dfff4cb | 1698 | arg_type = builtin_type (gdbarch)->builtin_long; |
ca3bf3bd DJ |
1699 | arg = value_cast (arg_type, arg); |
1700 | } | |
bdb4c075 MG |
1701 | /* Aligment is equal to the type length for the basic types. */ |
1702 | info->align = TYPE_LENGTH (arg_type); | |
ca3bf3bd DJ |
1703 | break; |
1704 | ||
1705 | case TYPE_CODE_FLT: | |
1706 | ||
1707 | /* Align doubles correctly. */ | |
0dfff4cb UW |
1708 | if (TYPE_LENGTH (arg_type) |
1709 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_double)) | |
1710 | info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_double); | |
ca3bf3bd | 1711 | else |
0dfff4cb | 1712 | info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long); |
ca3bf3bd DJ |
1713 | break; |
1714 | ||
1715 | case TYPE_CODE_STRUCT: | |
1716 | default: | |
0dfff4cb | 1717 | info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long); |
ca3bf3bd DJ |
1718 | break; |
1719 | } | |
1720 | info->length = TYPE_LENGTH (arg_type); | |
1721 | info->contents = value_contents (arg); | |
1722 | ||
1723 | /* Align size and onstack_size. */ | |
1724 | size = (size + info->align - 1) & ~(info->align - 1); | |
1725 | onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1); | |
1726 | ||
91d8eb23 | 1727 | if (size + info->length > REGISTER_SIZE * ARG_NOF (gdbarch)) |
ca3bf3bd DJ |
1728 | { |
1729 | info->onstack = 1; | |
1730 | info->u.offset = onstack_size; | |
1731 | onstack_size += info->length; | |
1732 | } | |
1733 | else | |
1734 | { | |
1735 | info->onstack = 0; | |
91d8eb23 | 1736 | info->u.regno = ARG_1ST (gdbarch) + size / REGISTER_SIZE; |
ca3bf3bd DJ |
1737 | } |
1738 | size += info->length; | |
1739 | } | |
1740 | ||
1741 | /* Adjust the stack pointer and align it. */ | |
1742 | sp = align_down (sp - onstack_size, SP_ALIGNMENT); | |
1743 | ||
bdb4c075 | 1744 | /* Simulate MOVSP, if Windowed ABI. */ |
6b50c0b0 | 1745 | if ((gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
304fe255 | 1746 | && (sp != osp)) |
ca3bf3bd DJ |
1747 | { |
1748 | read_memory (osp - 16, buf, 16); | |
1749 | write_memory (sp - 16, buf, 16); | |
1750 | } | |
1751 | ||
1752 | /* Second Loop: Load arguments. */ | |
1753 | ||
1754 | if (struct_return) | |
1755 | { | |
e17a4113 | 1756 | store_unsigned_integer (buf, REGISTER_SIZE, byte_order, struct_addr); |
91d8eb23 | 1757 | regcache_cooked_write (regcache, ARG_1ST (gdbarch), buf); |
ca3bf3bd DJ |
1758 | } |
1759 | ||
1760 | for (i = 0; i < nargs; i++) | |
1761 | { | |
1762 | struct argument_info *info = &arg_info[i]; | |
1763 | ||
1764 | if (info->onstack) | |
1765 | { | |
1766 | int n = info->length; | |
1767 | CORE_ADDR offset = sp + info->u.offset; | |
1768 | ||
1769 | /* Odd-sized structs are aligned to the lower side of a memory | |
1770 | word in big-endian mode and require a shift. This only | |
1771 | applies for structures smaller than one word. */ | |
1772 | ||
4c6b5505 | 1773 | if (n < REGISTER_SIZE |
6b50c0b0 | 1774 | && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1775 | offset += (REGISTER_SIZE - n); |
1776 | ||
1777 | write_memory (offset, info->contents, info->length); | |
1778 | ||
1779 | } | |
1780 | else | |
1781 | { | |
1782 | int n = info->length; | |
1783 | const bfd_byte *cp = info->contents; | |
1784 | int r = info->u.regno; | |
1785 | ||
1786 | /* Odd-sized structs are aligned to the lower side of registers in | |
1787 | big-endian mode and require a shift. The odd-sized leftover will | |
1788 | be at the end. Note that this is only true for structures smaller | |
1789 | than REGISTER_SIZE; for larger odd-sized structures the excess | |
1790 | will be left-aligned in the register on both endiannesses. */ | |
1791 | ||
e17a4113 | 1792 | if (n < REGISTER_SIZE && byte_order == BFD_ENDIAN_BIG) |
ca3bf3bd | 1793 | { |
e17a4113 UW |
1794 | ULONGEST v; |
1795 | v = extract_unsigned_integer (cp, REGISTER_SIZE, byte_order); | |
ca3bf3bd DJ |
1796 | v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT); |
1797 | ||
e17a4113 | 1798 | store_unsigned_integer (buf, REGISTER_SIZE, byte_order, v); |
ca3bf3bd DJ |
1799 | regcache_cooked_write (regcache, r, buf); |
1800 | ||
1801 | cp += REGISTER_SIZE; | |
1802 | n -= REGISTER_SIZE; | |
1803 | r++; | |
1804 | } | |
1805 | else | |
1806 | while (n > 0) | |
1807 | { | |
ca3bf3bd DJ |
1808 | regcache_cooked_write (regcache, r, cp); |
1809 | ||
ca3bf3bd DJ |
1810 | cp += REGISTER_SIZE; |
1811 | n -= REGISTER_SIZE; | |
1812 | r++; | |
1813 | } | |
1814 | } | |
1815 | } | |
1816 | ||
ca3bf3bd | 1817 | /* Set the return address of dummy frame to the dummy address. |
bdb4c075 | 1818 | The return address for the current function (in A0) is |
ca3bf3bd DJ |
1819 | saved in the dummy frame, so we can savely overwrite A0 here. */ |
1820 | ||
6b50c0b0 | 1821 | if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
bdb4c075 MG |
1822 | { |
1823 | ra = (bp_addr & 0x3fffffff) | 0x40000000; | |
6b50c0b0 | 1824 | regcache_raw_read (regcache, gdbarch_ps_regnum (gdbarch), buf); |
e17a4113 | 1825 | ps = extract_unsigned_integer (buf, 4, byte_order) & ~0x00030000; |
304fe255 | 1826 | regcache_cooked_write_unsigned |
6b50c0b0 | 1827 | (regcache, gdbarch_tdep (gdbarch)->a0_base + 4, ra); |
bdb4c075 | 1828 | regcache_cooked_write_unsigned (regcache, |
6b50c0b0 | 1829 | gdbarch_ps_regnum (gdbarch), |
bdb4c075 | 1830 | ps | 0x00010000); |
94a0e877 MG |
1831 | |
1832 | /* All the registers have been saved. After executing | |
1833 | dummy call, they all will be restored. So it's safe | |
1834 | to modify WINDOWSTART register to make it look like there | |
1835 | is only one register window corresponding to WINDOWEBASE. */ | |
1836 | ||
1837 | regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf); | |
e17a4113 UW |
1838 | regcache_cooked_write_unsigned |
1839 | (regcache, gdbarch_tdep (gdbarch)->ws_regnum, | |
1840 | 1 << extract_unsigned_integer (buf, 4, byte_order)); | |
bdb4c075 MG |
1841 | } |
1842 | else | |
1843 | { | |
1844 | /* Simulate CALL0: write RA into A0 register. */ | |
304fe255 | 1845 | regcache_cooked_write_unsigned |
94a0e877 | 1846 | (regcache, gdbarch_tdep (gdbarch)->a0_base, bp_addr); |
bdb4c075 | 1847 | } |
ca3bf3bd DJ |
1848 | |
1849 | /* Set new stack pointer and return it. */ | |
304fe255 | 1850 | regcache_cooked_write_unsigned (regcache, |
6b50c0b0 | 1851 | gdbarch_tdep (gdbarch)->a0_base + 1, sp); |
ca3bf3bd DJ |
1852 | /* Make dummy frame ID unique by adding a constant. */ |
1853 | return sp + SP_ALIGNMENT; | |
1854 | } | |
1855 | ||
1856 | ||
1857 | /* Return a breakpoint for the current location of PC. We always use | |
1858 | the density version if we have density instructions (regardless of the | |
1859 | current instruction at PC), and use regular instructions otherwise. */ | |
1860 | ||
1861 | #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 } | |
1862 | #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 } | |
1863 | #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f } | |
1864 | #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 } | |
1865 | ||
bdb4c075 | 1866 | static const unsigned char * |
67d57894 MD |
1867 | xtensa_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, |
1868 | int *lenptr) | |
ca3bf3bd | 1869 | { |
ff7a4c00 MG |
1870 | static unsigned char big_breakpoint[] = BIG_BREAKPOINT; |
1871 | static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT; | |
1872 | static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT; | |
1873 | static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT; | |
ca3bf3bd DJ |
1874 | |
1875 | DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr); | |
1876 | ||
67d57894 | 1877 | if (gdbarch_tdep (gdbarch)->isa_use_density_instructions) |
ca3bf3bd | 1878 | { |
67d57894 | 1879 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1880 | { |
1881 | *lenptr = sizeof (density_big_breakpoint); | |
1882 | return density_big_breakpoint; | |
1883 | } | |
1884 | else | |
1885 | { | |
1886 | *lenptr = sizeof (density_little_breakpoint); | |
1887 | return density_little_breakpoint; | |
1888 | } | |
1889 | } | |
1890 | else | |
1891 | { | |
67d57894 | 1892 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1893 | { |
1894 | *lenptr = sizeof (big_breakpoint); | |
1895 | return big_breakpoint; | |
1896 | } | |
1897 | else | |
1898 | { | |
1899 | *lenptr = sizeof (little_breakpoint); | |
1900 | return little_breakpoint; | |
1901 | } | |
1902 | } | |
1903 | } | |
1904 | ||
bdb4c075 MG |
1905 | /* Call0 ABI support routines. */ |
1906 | ||
1907 | /* Call0 opcode class. Opcodes are preclassified according to what they | |
1908 | mean for Call0 prologue analysis, and their number of significant operands. | |
1909 | The purpose of this is to simplify prologue analysis by separating | |
1910 | instruction decoding (libisa) from the semantics of prologue analysis. */ | |
1911 | ||
1912 | typedef enum { | |
1913 | c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */ | |
1914 | c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */ | |
1915 | c0opc_flow, /* Flow control insn. */ | |
1916 | c0opc_entry, /* ENTRY indicates non-Call0 prologue. */ | |
1917 | c0opc_break, /* Debugger software breakpoints. */ | |
1918 | c0opc_add, /* Adding two registers. */ | |
1919 | c0opc_addi, /* Adding a register and an immediate. */ | |
1920 | c0opc_sub, /* Subtracting a register from a register. */ | |
1921 | c0opc_mov, /* Moving a register to a register. */ | |
1922 | c0opc_movi, /* Moving an immediate to a register. */ | |
1923 | c0opc_l32r, /* Loading a literal. */ | |
581e13c1 MS |
1924 | c0opc_s32i, /* Storing word at fixed offset from a base |
1925 | register. */ | |
bdb4c075 MG |
1926 | c0opc_NrOf /* Number of opcode classifications. */ |
1927 | } xtensa_insn_kind; | |
1928 | ||
1929 | ||
1930 | /* Classify an opcode based on what it means for Call0 prologue analysis. */ | |
1931 | ||
1932 | static xtensa_insn_kind | |
1933 | call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc) | |
1934 | { | |
1935 | const char *opcname; | |
1936 | xtensa_insn_kind opclass = c0opc_uninteresting; | |
1937 | ||
1938 | DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc); | |
1939 | ||
1940 | /* Get opcode name and handle special classifications. */ | |
1941 | ||
1942 | opcname = xtensa_opcode_name (isa, opc); | |
1943 | ||
1944 | if (opcname == NULL | |
1945 | || strcasecmp (opcname, "ill") == 0 | |
1946 | || strcasecmp (opcname, "ill.n") == 0) | |
1947 | opclass = c0opc_illegal; | |
1948 | else if (strcasecmp (opcname, "break") == 0 | |
1949 | || strcasecmp (opcname, "break.n") == 0) | |
1950 | opclass = c0opc_break; | |
1951 | else if (strcasecmp (opcname, "entry") == 0) | |
1952 | opclass = c0opc_entry; | |
1953 | else if (xtensa_opcode_is_branch (isa, opc) > 0 | |
1954 | || xtensa_opcode_is_jump (isa, opc) > 0 | |
1955 | || xtensa_opcode_is_loop (isa, opc) > 0 | |
1956 | || xtensa_opcode_is_call (isa, opc) > 0 | |
1957 | || strcasecmp (opcname, "simcall") == 0 | |
1958 | || strcasecmp (opcname, "syscall") == 0) | |
1959 | opclass = c0opc_flow; | |
1960 | ||
1961 | /* Also, classify specific opcodes that need to be tracked. */ | |
1962 | else if (strcasecmp (opcname, "add") == 0 | |
1963 | || strcasecmp (opcname, "add.n") == 0) | |
1964 | opclass = c0opc_add; | |
1965 | else if (strcasecmp (opcname, "addi") == 0 | |
1966 | || strcasecmp (opcname, "addi.n") == 0 | |
1967 | || strcasecmp (opcname, "addmi") == 0) | |
1968 | opclass = c0opc_addi; | |
1969 | else if (strcasecmp (opcname, "sub") == 0) | |
1970 | opclass = c0opc_sub; | |
1971 | else if (strcasecmp (opcname, "mov.n") == 0 | |
1972 | || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */ | |
1973 | opclass = c0opc_mov; | |
1974 | else if (strcasecmp (opcname, "movi") == 0 | |
1975 | || strcasecmp (opcname, "movi.n") == 0) | |
1976 | opclass = c0opc_movi; | |
1977 | else if (strcasecmp (opcname, "l32r") == 0) | |
1978 | opclass = c0opc_l32r; | |
1979 | else if (strcasecmp (opcname, "s32i") == 0 | |
1980 | || strcasecmp (opcname, "s32i.n") == 0) | |
1981 | opclass = c0opc_s32i; | |
1982 | ||
1983 | return opclass; | |
1984 | } | |
1985 | ||
1986 | /* Tracks register movement/mutation for a given operation, which may | |
1987 | be within a bundle. Updates the destination register tracking info | |
1988 | accordingly. The pc is needed only for pc-relative load instructions | |
1989 | (eg. l32r). The SP register number is needed to identify stores to | |
1990 | the stack frame. */ | |
1991 | ||
1992 | static void | |
e17a4113 UW |
1993 | call0_track_op (struct gdbarch *gdbarch, |
1994 | xtensa_c0reg_t dst[], xtensa_c0reg_t src[], | |
bdb4c075 | 1995 | xtensa_insn_kind opclass, int nods, unsigned odv[], |
9f61f19b | 1996 | CORE_ADDR pc, CORE_ADDR litbase, int spreg) |
bdb4c075 | 1997 | { |
e17a4113 | 1998 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
9f61f19b | 1999 | unsigned litaddr, litval; |
bdb4c075 MG |
2000 | |
2001 | switch (opclass) | |
2002 | { | |
2003 | case c0opc_addi: | |
2004 | /* 3 operands: dst, src, imm. */ | |
2005 | gdb_assert (nods == 3); | |
2006 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
2007 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2]; | |
2008 | break; | |
2009 | case c0opc_add: | |
2010 | /* 3 operands: dst, src1, src2. */ | |
2011 | gdb_assert (nods == 3); | |
2012 | if (src[odv[1]].fr_reg == C0_CONST) | |
2013 | { | |
2014 | dst[odv[0]].fr_reg = src[odv[2]].fr_reg; | |
2015 | dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs; | |
2016 | } | |
2017 | else if (src[odv[2]].fr_reg == C0_CONST) | |
2018 | { | |
2019 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
2020 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs; | |
2021 | } | |
2022 | else dst[odv[0]].fr_reg = C0_INEXP; | |
2023 | break; | |
2024 | case c0opc_sub: | |
2025 | /* 3 operands: dst, src1, src2. */ | |
2026 | gdb_assert (nods == 3); | |
2027 | if (src[odv[2]].fr_reg == C0_CONST) | |
2028 | { | |
2029 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
2030 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs; | |
2031 | } | |
2032 | else dst[odv[0]].fr_reg = C0_INEXP; | |
2033 | break; | |
2034 | case c0opc_mov: | |
2035 | /* 2 operands: dst, src [, src]. */ | |
2036 | gdb_assert (nods == 2); | |
2037 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
2038 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs; | |
2039 | break; | |
2040 | case c0opc_movi: | |
2041 | /* 2 operands: dst, imm. */ | |
2042 | gdb_assert (nods == 2); | |
2043 | dst[odv[0]].fr_reg = C0_CONST; | |
2044 | dst[odv[0]].fr_ofs = odv[1]; | |
2045 | break; | |
2046 | case c0opc_l32r: | |
2047 | /* 2 operands: dst, literal offset. */ | |
2048 | gdb_assert (nods == 2); | |
bdb4c075 MG |
2049 | litaddr = litbase & 1 |
2050 | ? (litbase & ~1) + (signed)odv[1] | |
2051 | : (pc + 3 + (signed)odv[1]) & ~3; | |
e17a4113 | 2052 | litval = read_memory_integer (litaddr, 4, byte_order); |
bdb4c075 MG |
2053 | dst[odv[0]].fr_reg = C0_CONST; |
2054 | dst[odv[0]].fr_ofs = litval; | |
2055 | break; | |
2056 | case c0opc_s32i: | |
2057 | /* 3 operands: value, base, offset. */ | |
2058 | gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS); | |
2059 | if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */ | |
2060 | && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */ | |
2061 | && src[odv[0]].fr_reg >= 0 /* Value is from a register. */ | |
2062 | && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */ | |
2063 | && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */ | |
2064 | { | |
2065 | /* ISA encoding guarantees alignment. But, check it anyway. */ | |
2066 | gdb_assert ((odv[2] & 3) == 0); | |
2067 | dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2]; | |
2068 | } | |
2069 | break; | |
2070 | default: | |
f3574227 | 2071 | gdb_assert_not_reached ("unexpected instruction kind"); |
bdb4c075 MG |
2072 | } |
2073 | } | |
2074 | ||
2075 | /* Analyze prologue of the function at start address to determine if it uses | |
2076 | the Call0 ABI, and if so track register moves and linear modifications | |
2077 | in the prologue up to the PC or just beyond the prologue, whichever is first. | |
2078 | An 'entry' instruction indicates non-Call0 ABI and the end of the prologue. | |
2079 | The prologue may overlap non-prologue instructions but is guaranteed to end | |
2080 | by the first flow-control instruction (jump, branch, call or return). | |
2081 | Since an optimized function may move information around and change the | |
2082 | stack frame arbitrarily during the prologue, the information is guaranteed | |
2083 | valid only at the point in the function indicated by the PC. | |
2084 | May be used to skip the prologue or identify the ABI, w/o tracking. | |
2085 | ||
2086 | Returns: Address of first instruction after prologue, or PC (whichever | |
2087 | is first), or 0, if decoding failed (in libisa). | |
2088 | Input args: | |
2089 | start Start address of function/prologue. | |
2090 | pc Program counter to stop at. Use 0 to continue to end of prologue. | |
2091 | If 0, avoids infinite run-on in corrupt code memory by bounding | |
2092 | the scan to the end of the function if that can be determined. | |
2093 | nregs Number of general registers to track (size of rt[] array). | |
2094 | InOut args: | |
2095 | rt[] Array[nregs] of xtensa_c0reg structures for register tracking info. | |
2096 | If NULL, registers are not tracked. | |
2097 | Output args: | |
2098 | call0 If != NULL, *call0 is set non-zero if Call0 ABI used, else 0 | |
2099 | (more accurately, non-zero until 'entry' insn is encountered). | |
2100 | ||
2101 | Note that these may produce useful results even if decoding fails | |
2102 | because they begin with default assumptions that analysis may change. */ | |
2103 | ||
2104 | static CORE_ADDR | |
e17a4113 UW |
2105 | call0_analyze_prologue (struct gdbarch *gdbarch, |
2106 | CORE_ADDR start, CORE_ADDR pc, CORE_ADDR litbase, | |
bdb4c075 MG |
2107 | int nregs, xtensa_c0reg_t rt[], int *call0) |
2108 | { | |
2109 | CORE_ADDR ia; /* Current insn address in prologue. */ | |
2110 | CORE_ADDR ba = 0; /* Current address at base of insn buffer. */ | |
2111 | CORE_ADDR bt; /* Current address at top+1 of insn buffer. */ | |
2ff5e605 | 2112 | char ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue. */ |
bdb4c075 MG |
2113 | xtensa_isa isa; /* libisa ISA handle. */ |
2114 | xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */ | |
2115 | xtensa_format ifmt; /* libisa instruction format. */ | |
2116 | int ilen, islots, is; /* Instruction length, nbr slots, current slot. */ | |
2117 | xtensa_opcode opc; /* Opcode in current slot. */ | |
2118 | xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */ | |
2119 | int nods; /* Opcode number of operands. */ | |
2120 | unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */ | |
2121 | xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */ | |
2122 | int j; /* General loop counter. */ | |
2123 | int fail = 0; /* Set non-zero and exit, if decoding fails. */ | |
2124 | CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */ | |
2125 | CORE_ADDR end_pc; /* The PC for the lust function insn. */ | |
2126 | ||
2127 | struct symtab_and_line prologue_sal; | |
2128 | ||
2129 | DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n", | |
2130 | (int)start, (int)pc); | |
2131 | ||
2132 | /* Try to limit the scan to the end of the function if a non-zero pc | |
2133 | arg was not supplied to avoid probing beyond the end of valid memory. | |
2134 | If memory is full of garbage that classifies as c0opc_uninteresting. | |
2135 | If this fails (eg. if no symbols) pc ends up 0 as it was. | |
2136 | Intialize the Call0 frame and register tracking info. | |
2137 | Assume it's Call0 until an 'entry' instruction is encountered. | |
2138 | Assume we may be in the prologue until we hit a flow control instr. */ | |
2139 | ||
2140 | rtmp = NULL; | |
8179e739 | 2141 | body_pc = UINT_MAX; |
bdb4c075 MG |
2142 | end_pc = 0; |
2143 | ||
2144 | /* Find out, if we have an information about the prologue from DWARF. */ | |
2145 | prologue_sal = find_pc_line (start, 0); | |
2146 | if (prologue_sal.line != 0) /* Found debug info. */ | |
2147 | body_pc = prologue_sal.end; | |
2148 | ||
2149 | /* If we are going to analyze the prologue in general without knowing about | |
2150 | the current PC, make the best assumtion for the end of the prologue. */ | |
2151 | if (pc == 0) | |
2152 | { | |
2153 | find_pc_partial_function (start, 0, NULL, &end_pc); | |
2154 | body_pc = min (end_pc, body_pc); | |
2155 | } | |
2156 | else | |
2157 | body_pc = min (pc, body_pc); | |
2158 | ||
2159 | if (call0 != NULL) | |
2160 | *call0 = 1; | |
2161 | ||
2162 | if (rt != NULL) | |
2163 | { | |
2164 | rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t)); | |
2165 | /* rt is already initialized in xtensa_alloc_frame_cache(). */ | |
2166 | } | |
2167 | else nregs = 0; | |
2168 | ||
94a0e877 MG |
2169 | if (!xtensa_default_isa) |
2170 | xtensa_default_isa = xtensa_isa_init (0, 0); | |
bdb4c075 | 2171 | isa = xtensa_default_isa; |
2ff5e605 | 2172 | gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); |
bdb4c075 MG |
2173 | ins = xtensa_insnbuf_alloc (isa); |
2174 | slot = xtensa_insnbuf_alloc (isa); | |
2175 | ||
2176 | for (ia = start, bt = ia; ia < body_pc ; ia += ilen) | |
2177 | { | |
2178 | /* (Re)fill instruction buffer from memory if necessary, but do not | |
2179 | read memory beyond PC to be sure we stay within text section | |
2180 | (this protection only works if a non-zero pc is supplied). */ | |
2181 | ||
2182 | if (ia + xtensa_isa_maxlength (isa) > bt) | |
2183 | { | |
2184 | ba = ia; | |
2ff5e605 | 2185 | bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ : body_pc; |
bdb4c075 | 2186 | read_memory (ba, ibuf, bt - ba); |
d4709618 MG |
2187 | /* If there is a memory reading error read_memory () will report it |
2188 | and then throw an exception, stopping command execution. */ | |
bdb4c075 MG |
2189 | } |
2190 | ||
2191 | /* Decode format information. */ | |
2192 | ||
2193 | xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); | |
2194 | ifmt = xtensa_format_decode (isa, ins); | |
2195 | if (ifmt == XTENSA_UNDEFINED) | |
2196 | { | |
2197 | fail = 1; | |
2198 | goto done; | |
2199 | } | |
2200 | ilen = xtensa_format_length (isa, ifmt); | |
2201 | if (ilen == XTENSA_UNDEFINED) | |
2202 | { | |
2203 | fail = 1; | |
2204 | goto done; | |
2205 | } | |
2206 | islots = xtensa_format_num_slots (isa, ifmt); | |
2207 | if (islots == XTENSA_UNDEFINED) | |
2208 | { | |
2209 | fail = 1; | |
2210 | goto done; | |
2211 | } | |
2212 | ||
2213 | /* Analyze a bundle or a single instruction, using a snapshot of | |
2214 | the register tracking info as input for the entire bundle so that | |
2215 | register changes do not take effect within this bundle. */ | |
ca3bf3bd | 2216 | |
bdb4c075 MG |
2217 | for (j = 0; j < nregs; ++j) |
2218 | rtmp[j] = rt[j]; | |
2219 | ||
2220 | for (is = 0; is < islots; ++is) | |
2221 | { | |
2222 | /* Decode a slot and classify the opcode. */ | |
2223 | ||
2224 | fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot); | |
2225 | if (fail) | |
2226 | goto done; | |
2227 | ||
2228 | opc = xtensa_opcode_decode (isa, ifmt, is, slot); | |
581e13c1 MS |
2229 | DEBUGVERB ("[call0_analyze_prologue] instr " |
2230 | "addr = 0x%08x, opc = %d\n", | |
bdb4c075 MG |
2231 | (unsigned)ia, opc); |
2232 | if (opc == XTENSA_UNDEFINED) | |
2233 | opclass = c0opc_illegal; | |
2234 | else | |
2235 | opclass = call0_classify_opcode (isa, opc); | |
2236 | ||
2237 | /* Decide whether to track this opcode, ignore it, or bail out. */ | |
2238 | ||
2239 | switch (opclass) | |
2240 | { | |
2241 | case c0opc_illegal: | |
2242 | case c0opc_break: | |
2243 | fail = 1; | |
2244 | goto done; | |
2245 | ||
2246 | case c0opc_uninteresting: | |
2247 | continue; | |
2248 | ||
2249 | case c0opc_flow: | |
2250 | goto done; | |
2251 | ||
2252 | case c0opc_entry: | |
2253 | if (call0 != NULL) | |
2254 | *call0 = 0; | |
2255 | ia += ilen; /* Skip over 'entry' insn. */ | |
2256 | goto done; | |
2257 | ||
2258 | default: | |
2259 | if (call0 != NULL) | |
2260 | *call0 = 1; | |
2261 | } | |
2262 | ||
2263 | /* Only expected opcodes should get this far. */ | |
2264 | if (rt == NULL) | |
2265 | continue; | |
2266 | ||
2267 | /* Extract and decode the operands. */ | |
2268 | nods = xtensa_opcode_num_operands (isa, opc); | |
2269 | if (nods == XTENSA_UNDEFINED) | |
2270 | { | |
2271 | fail = 1; | |
2272 | goto done; | |
2273 | } | |
2274 | ||
2275 | for (j = 0; j < nods && j < C0_MAXOPDS; ++j) | |
2276 | { | |
2277 | fail = xtensa_operand_get_field (isa, opc, j, ifmt, | |
2278 | is, slot, &odv[j]); | |
2279 | if (fail) | |
2280 | goto done; | |
2281 | ||
2282 | fail = xtensa_operand_decode (isa, opc, j, &odv[j]); | |
2283 | if (fail) | |
2284 | goto done; | |
2285 | } | |
2286 | ||
2287 | /* Check operands to verify use of 'mov' assembler macro. */ | |
2288 | if (opclass == c0opc_mov && nods == 3) | |
2289 | { | |
2290 | if (odv[2] == odv[1]) | |
2291 | nods = 2; | |
2292 | else | |
2293 | { | |
2294 | opclass = c0opc_uninteresting; | |
2295 | continue; | |
2296 | } | |
2297 | } | |
2298 | ||
2299 | /* Track register movement and modification for this operation. */ | |
e17a4113 UW |
2300 | call0_track_op (gdbarch, rt, rtmp, opclass, |
2301 | nods, odv, ia, litbase, 1); | |
bdb4c075 MG |
2302 | } |
2303 | } | |
2304 | done: | |
2305 | DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n", | |
2306 | (unsigned)ia, fail ? "failed" : "succeeded"); | |
2307 | xtensa_insnbuf_free(isa, slot); | |
2308 | xtensa_insnbuf_free(isa, ins); | |
d4709618 | 2309 | return fail ? XTENSA_ISA_BADPC : ia; |
bdb4c075 MG |
2310 | } |
2311 | ||
5142f611 | 2312 | /* Initialize frame cache for the current frame in CALL0 ABI. */ |
bdb4c075 MG |
2313 | |
2314 | static void | |
5142f611 | 2315 | call0_frame_cache (struct frame_info *this_frame, |
581e13c1 MS |
2316 | xtensa_frame_cache_t *cache, |
2317 | CORE_ADDR pc, CORE_ADDR litbase) | |
bdb4c075 | 2318 | { |
5142f611 | 2319 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
e17a4113 | 2320 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
bdb4c075 MG |
2321 | CORE_ADDR start_pc; /* The beginning of the function. */ |
2322 | CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */ | |
2323 | CORE_ADDR sp, fp, ra; | |
2324 | int fp_regnum, c0_hasfp, c0_frmsz, prev_sp, to_stk; | |
2325 | ||
2326 | /* Find the beginning of the prologue of the function containing the PC | |
2327 | and analyze it up to the PC or the end of the prologue. */ | |
2328 | ||
2329 | if (find_pc_partial_function (pc, NULL, &start_pc, NULL)) | |
2330 | { | |
e17a4113 UW |
2331 | body_pc = call0_analyze_prologue (gdbarch, start_pc, pc, litbase, |
2332 | C0_NREGS, | |
bdb4c075 MG |
2333 | &cache->c0.c0_rt[0], |
2334 | &cache->call0); | |
d4709618 MG |
2335 | |
2336 | if (body_pc == XTENSA_ISA_BADPC) | |
2337 | error (_("Xtensa-specific internal error: CALL0 prologue \ | |
2338 | analysis failed in this frame. GDB command execution stopped.")); | |
bdb4c075 MG |
2339 | } |
2340 | ||
5142f611 MG |
2341 | sp = get_frame_register_unsigned |
2342 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1); | |
bdb4c075 MG |
2343 | fp = sp; /* Assume FP == SP until proven otherwise. */ |
2344 | ||
2345 | /* Get the frame information and FP (if used) at the current PC. | |
2346 | If PC is in the prologue, the prologue analysis is more reliable | |
2347 | than DWARF info. We don't not know for sure if PC is in the prologue, | |
2348 | but we know no calls have yet taken place, so we can almost | |
2349 | certainly rely on the prologue analysis. */ | |
2350 | ||
2351 | if (body_pc <= pc) | |
2352 | { | |
2353 | /* Prologue analysis was successful up to the PC. | |
2354 | It includes the cases when PC == START_PC. */ | |
2355 | c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP; | |
2356 | /* c0_hasfp == true means there is a frame pointer because | |
2357 | we analyzed the prologue and found that cache->c0.c0_rt[C0_FP] | |
2358 | was derived from SP. Otherwise, it would be C0_FP. */ | |
2359 | fp_regnum = c0_hasfp ? C0_FP : C0_SP; | |
2360 | c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs; | |
6b50c0b0 | 2361 | fp_regnum += gdbarch_tdep (gdbarch)->a0_base; |
bdb4c075 MG |
2362 | } |
2363 | else /* No data from the prologue analysis. */ | |
2364 | { | |
2365 | c0_hasfp = 0; | |
6b50c0b0 | 2366 | fp_regnum = gdbarch_tdep (gdbarch)->a0_base + C0_SP; |
bdb4c075 MG |
2367 | c0_frmsz = 0; |
2368 | start_pc = pc; | |
2369 | } | |
2370 | ||
2371 | prev_sp = fp + c0_frmsz; | |
2372 | ||
2373 | /* Frame size from debug info or prologue tracking does not account for | |
2374 | alloca() and other dynamic allocations. Adjust frame size by FP - SP. */ | |
2375 | if (c0_hasfp) | |
2376 | { | |
5142f611 | 2377 | fp = get_frame_register_unsigned (this_frame, fp_regnum); |
bdb4c075 MG |
2378 | |
2379 | /* Recalculate previous SP. */ | |
2380 | prev_sp = fp + c0_frmsz; | |
2381 | /* Update the stack frame size. */ | |
2382 | c0_frmsz += fp - sp; | |
2383 | } | |
2384 | ||
2385 | /* Get the return address (RA) from the stack if saved, | |
2386 | or try to get it from a register. */ | |
2387 | ||
2388 | to_stk = cache->c0.c0_rt[C0_RA].to_stk; | |
2389 | if (to_stk != C0_NOSTK) | |
2390 | ra = (CORE_ADDR) | |
e17a4113 UW |
2391 | read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk, |
2392 | 4, byte_order); | |
bdb4c075 MG |
2393 | |
2394 | else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST | |
2395 | && cache->c0.c0_rt[C0_RA].fr_ofs == 0) | |
2396 | { | |
581e13c1 MS |
2397 | /* Special case for terminating backtrace at a function that |
2398 | wants to be seen as the outermost. Such a function will | |
2399 | clear it's RA (A0) register to 0 in the prologue instead of | |
2400 | saving its original value. */ | |
bdb4c075 MG |
2401 | ra = 0; |
2402 | } | |
2403 | else | |
2404 | { | |
581e13c1 MS |
2405 | /* RA was copied to another register or (before any function |
2406 | call) may still be in the original RA register. This is not | |
2407 | always reliable: even in a leaf function, register tracking | |
2408 | stops after prologue, and even in prologue, non-prologue | |
2409 | instructions (not tracked) may overwrite RA or any register | |
2410 | it was copied to. If likely in prologue or before any call, | |
2411 | use retracking info and hope for the best (compiler should | |
2412 | have saved RA in stack if not in a leaf function). If not in | |
2413 | prologue, too bad. */ | |
bdb4c075 MG |
2414 | |
2415 | int i; | |
2416 | for (i = 0; | |
2417 | (i < C0_NREGS) && | |
2418 | (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA); | |
2419 | ++i); | |
2420 | if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA) | |
2421 | i = C0_RA; | |
5142f611 | 2422 | if (i < C0_NREGS) |
bdb4c075 | 2423 | { |
5142f611 MG |
2424 | ra = get_frame_register_unsigned |
2425 | (this_frame, | |
2426 | gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_rt[i].fr_reg); | |
bdb4c075 MG |
2427 | } |
2428 | else ra = 0; | |
2429 | } | |
2430 | ||
2431 | cache->pc = start_pc; | |
2432 | cache->ra = ra; | |
2433 | /* RA == 0 marks the outermost frame. Do not go past it. */ | |
2434 | cache->prev_sp = (ra != 0) ? prev_sp : 0; | |
2435 | cache->c0.fp_regnum = fp_regnum; | |
2436 | cache->c0.c0_frmsz = c0_frmsz; | |
2437 | cache->c0.c0_hasfp = c0_hasfp; | |
2438 | cache->c0.c0_fp = fp; | |
2439 | } | |
2440 | ||
2441 | ||
2442 | /* Skip function prologue. | |
2443 | ||
2444 | Return the pc of the first instruction after prologue. GDB calls this to | |
2445 | find the address of the first line of the function or (if there is no line | |
2446 | number information) to skip the prologue for planting breakpoints on | |
2447 | function entries. Use debug info (if present) or prologue analysis to skip | |
2448 | the prologue to achieve reliable debugging behavior. For windowed ABI, | |
2449 | only the 'entry' instruction is skipped. It is not strictly necessary to | |
2450 | skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to | |
2451 | backtrace at any point in the prologue, however certain potential hazards | |
2452 | are avoided and a more "normal" debugging experience is ensured by | |
2453 | skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG). | |
2454 | For example, if we don't skip the prologue: | |
2455 | - Some args may not yet have been saved to the stack where the debug | |
2456 | info expects to find them (true anyway when only 'entry' is skipped); | |
2457 | - Software breakpoints ('break' instrs) may not have been unplanted | |
2458 | when the prologue analysis is done on initializing the frame cache, | |
2459 | and breaks in the prologue will throw off the analysis. | |
ca3bf3bd DJ |
2460 | |
2461 | If we have debug info ( line-number info, in particular ) we simply skip | |
2462 | the code associated with the first function line effectively skipping | |
bdb4c075 | 2463 | the prologue code. It works even in cases like |
ca3bf3bd DJ |
2464 | |
2465 | int main() | |
2466 | { int local_var = 1; | |
2467 | .... | |
2468 | } | |
2469 | ||
2470 | because, for this source code, both Xtensa compilers will generate two | |
2471 | separate entries ( with the same line number ) in dwarf line-number | |
2472 | section to make sure there is a boundary between the prologue code and | |
2473 | the rest of the function. | |
2474 | ||
bdb4c075 MG |
2475 | If there is no debug info, we need to analyze the code. */ |
2476 | ||
2477 | /* #define DONT_SKIP_PROLOGUE */ | |
ca3bf3bd | 2478 | |
63807e1d | 2479 | static CORE_ADDR |
6093d2eb | 2480 | xtensa_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
ca3bf3bd | 2481 | { |
bdb4c075 MG |
2482 | struct symtab_and_line prologue_sal; |
2483 | CORE_ADDR body_pc; | |
2484 | ||
ca3bf3bd DJ |
2485 | DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc); |
2486 | ||
bdb4c075 MG |
2487 | #if DONT_SKIP_PROLOGUE |
2488 | return start_pc; | |
2489 | #endif | |
2490 | ||
2491 | /* Try to find first body line from debug info. */ | |
2492 | ||
2493 | prologue_sal = find_pc_line (start_pc, 0); | |
2494 | if (prologue_sal.line != 0) /* Found debug info. */ | |
ca3bf3bd | 2495 | { |
bdb4c075 MG |
2496 | /* In Call0, it is possible to have a function with only one instruction |
2497 | ('ret') resulting from a 1-line optimized function that does nothing. | |
2498 | In that case, prologue_sal.end may actually point to the start of the | |
2499 | next function in the text section, causing a breakpoint to be set at | |
2500 | the wrong place. Check if the end address is in a different function, | |
2501 | and if so return the start PC. We know we have symbol info. */ | |
ca3bf3bd | 2502 | |
bdb4c075 MG |
2503 | CORE_ADDR end_func; |
2504 | ||
2505 | find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL); | |
2506 | if (end_func != start_pc) | |
ca3bf3bd DJ |
2507 | return start_pc; |
2508 | ||
bdb4c075 | 2509 | return prologue_sal.end; |
ca3bf3bd | 2510 | } |
ca3bf3bd | 2511 | |
bdb4c075 | 2512 | /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */ |
e17a4113 | 2513 | body_pc = call0_analyze_prologue (gdbarch, start_pc, 0, 0, 0, NULL, NULL); |
bdb4c075 MG |
2514 | return body_pc != 0 ? body_pc : start_pc; |
2515 | } | |
ca3bf3bd DJ |
2516 | |
2517 | /* Verify the current configuration. */ | |
ca3bf3bd DJ |
2518 | static void |
2519 | xtensa_verify_config (struct gdbarch *gdbarch) | |
2520 | { | |
2521 | struct ui_file *log; | |
2522 | struct cleanup *cleanups; | |
2523 | struct gdbarch_tdep *tdep; | |
759ef836 | 2524 | long length; |
ca3bf3bd DJ |
2525 | char *buf; |
2526 | ||
2527 | tdep = gdbarch_tdep (gdbarch); | |
2528 | log = mem_fileopen (); | |
2529 | cleanups = make_cleanup_ui_file_delete (log); | |
2530 | ||
2531 | /* Verify that we got a reasonable number of AREGS. */ | |
2532 | if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs) | |
bdb4c075 MG |
2533 | fprintf_unfiltered (log, _("\ |
2534 | \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"), | |
2535 | tdep->num_aregs); | |
ca3bf3bd DJ |
2536 | |
2537 | /* Verify that certain registers exist. */ | |
bdb4c075 | 2538 | |
ca3bf3bd | 2539 | if (tdep->pc_regnum == -1) |
bdb4c075 MG |
2540 | fprintf_unfiltered (log, _("\n\tpc_regnum: No PC register")); |
2541 | if (tdep->isa_use_exceptions && tdep->ps_regnum == -1) | |
2542 | fprintf_unfiltered (log, _("\n\tps_regnum: No PS register")); | |
2543 | ||
2544 | if (tdep->isa_use_windowed_registers) | |
2545 | { | |
2546 | if (tdep->wb_regnum == -1) | |
2547 | fprintf_unfiltered (log, _("\n\twb_regnum: No WB register")); | |
2548 | if (tdep->ws_regnum == -1) | |
2549 | fprintf_unfiltered (log, _("\n\tws_regnum: No WS register")); | |
2550 | if (tdep->ar_base == -1) | |
2551 | fprintf_unfiltered (log, _("\n\tar_base: No AR registers")); | |
2552 | } | |
2553 | ||
ca3bf3bd | 2554 | if (tdep->a0_base == -1) |
bdb4c075 | 2555 | fprintf_unfiltered (log, _("\n\ta0_base: No Ax registers")); |
ca3bf3bd | 2556 | |
759ef836 | 2557 | buf = ui_file_xstrdup (log, &length); |
ca3bf3bd | 2558 | make_cleanup (xfree, buf); |
759ef836 | 2559 | if (length > 0) |
ca3bf3bd DJ |
2560 | internal_error (__FILE__, __LINE__, |
2561 | _("the following are invalid: %s"), buf); | |
2562 | do_cleanups (cleanups); | |
2563 | } | |
2564 | ||
94a0e877 MG |
2565 | |
2566 | /* Derive specific register numbers from the array of registers. */ | |
2567 | ||
63807e1d | 2568 | static void |
94a0e877 MG |
2569 | xtensa_derive_tdep (struct gdbarch_tdep *tdep) |
2570 | { | |
2571 | xtensa_register_t* rmap; | |
2572 | int n, max_size = 4; | |
2573 | ||
2574 | tdep->num_regs = 0; | |
2575 | tdep->num_nopriv_regs = 0; | |
2576 | ||
2577 | /* Special registers 0..255 (core). */ | |
2578 | #define XTENSA_DBREGN_SREG(n) (0x0200+(n)) | |
2579 | ||
2580 | for (rmap = tdep->regmap, n = 0; rmap->target_number != -1; n++, rmap++) | |
2581 | { | |
2582 | if (rmap->target_number == 0x0020) | |
2583 | tdep->pc_regnum = n; | |
2584 | else if (rmap->target_number == 0x0100) | |
2585 | tdep->ar_base = n; | |
2586 | else if (rmap->target_number == 0x0000) | |
2587 | tdep->a0_base = n; | |
2588 | else if (rmap->target_number == XTENSA_DBREGN_SREG(72)) | |
2589 | tdep->wb_regnum = n; | |
2590 | else if (rmap->target_number == XTENSA_DBREGN_SREG(73)) | |
2591 | tdep->ws_regnum = n; | |
2592 | else if (rmap->target_number == XTENSA_DBREGN_SREG(233)) | |
2593 | tdep->debugcause_regnum = n; | |
2594 | else if (rmap->target_number == XTENSA_DBREGN_SREG(232)) | |
2595 | tdep->exccause_regnum = n; | |
2596 | else if (rmap->target_number == XTENSA_DBREGN_SREG(238)) | |
2597 | tdep->excvaddr_regnum = n; | |
2598 | else if (rmap->target_number == XTENSA_DBREGN_SREG(0)) | |
2599 | tdep->lbeg_regnum = n; | |
2600 | else if (rmap->target_number == XTENSA_DBREGN_SREG(1)) | |
2601 | tdep->lend_regnum = n; | |
2602 | else if (rmap->target_number == XTENSA_DBREGN_SREG(2)) | |
2603 | tdep->lcount_regnum = n; | |
2604 | else if (rmap->target_number == XTENSA_DBREGN_SREG(3)) | |
2605 | tdep->sar_regnum = n; | |
2606 | else if (rmap->target_number == XTENSA_DBREGN_SREG(5)) | |
2607 | tdep->litbase_regnum = n; | |
2608 | else if (rmap->target_number == XTENSA_DBREGN_SREG(230)) | |
2609 | tdep->ps_regnum = n; | |
2610 | #if 0 | |
2611 | else if (rmap->target_number == XTENSA_DBREGN_SREG(226)) | |
2612 | tdep->interrupt_regnum = n; | |
2613 | else if (rmap->target_number == XTENSA_DBREGN_SREG(227)) | |
2614 | tdep->interrupt2_regnum = n; | |
2615 | else if (rmap->target_number == XTENSA_DBREGN_SREG(224)) | |
2616 | tdep->cpenable_regnum = n; | |
2617 | #endif | |
2618 | ||
2619 | if (rmap->byte_size > max_size) | |
2620 | max_size = rmap->byte_size; | |
2621 | if (rmap->mask != 0 && tdep->num_regs == 0) | |
2622 | tdep->num_regs = n; | |
2623 | /* Find out out how to deal with priveleged registers. | |
2624 | ||
2625 | if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0 | |
2626 | && tdep->num_nopriv_regs == 0) | |
2627 | tdep->num_nopriv_regs = n; | |
2628 | */ | |
2629 | if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0 | |
2630 | && tdep->num_regs == 0) | |
2631 | tdep->num_regs = n; | |
2632 | } | |
2633 | ||
2634 | /* Number of pseudo registers. */ | |
2635 | tdep->num_pseudo_regs = n - tdep->num_regs; | |
2636 | ||
2637 | /* Empirically determined maximum sizes. */ | |
2638 | tdep->max_register_raw_size = max_size; | |
2639 | tdep->max_register_virtual_size = max_size; | |
2640 | } | |
2641 | ||
ca3bf3bd DJ |
2642 | /* Module "constructor" function. */ |
2643 | ||
94a0e877 MG |
2644 | extern struct gdbarch_tdep xtensa_tdep; |
2645 | ||
ca3bf3bd DJ |
2646 | static struct gdbarch * |
2647 | xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2648 | { | |
2649 | struct gdbarch_tdep *tdep; | |
2650 | struct gdbarch *gdbarch; | |
2651 | struct xtensa_abi_handler *abi_handler; | |
2652 | ||
2653 | DEBUGTRACE ("gdbarch_init()\n"); | |
2654 | ||
2655 | /* We have to set the byte order before we call gdbarch_alloc. */ | |
94a0e877 | 2656 | info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE; |
ca3bf3bd | 2657 | |
94a0e877 | 2658 | tdep = &xtensa_tdep; |
ca3bf3bd | 2659 | gdbarch = gdbarch_alloc (&info, tdep); |
94a0e877 | 2660 | xtensa_derive_tdep (tdep); |
ca3bf3bd DJ |
2661 | |
2662 | /* Verify our configuration. */ | |
2663 | xtensa_verify_config (gdbarch); | |
2664 | ||
bdb4c075 | 2665 | /* Pseudo-Register read/write. */ |
ca3bf3bd DJ |
2666 | set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read); |
2667 | set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write); | |
2668 | ||
2669 | /* Set target information. */ | |
2670 | set_gdbarch_num_regs (gdbarch, tdep->num_regs); | |
2671 | set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs); | |
2672 | set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1); | |
2673 | set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum); | |
2674 | set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum); | |
2675 | ||
ba2b1c56 | 2676 | /* Renumber registers for known formats (stabs and dwarf2). */ |
ca3bf3bd | 2677 | set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); |
ca3bf3bd DJ |
2678 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); |
2679 | ||
2680 | /* We provide our own function to get register information. */ | |
2681 | set_gdbarch_register_name (gdbarch, xtensa_register_name); | |
2682 | set_gdbarch_register_type (gdbarch, xtensa_register_type); | |
2683 | ||
581e13c1 | 2684 | /* To call functions from GDB using dummy frame. */ |
ca3bf3bd DJ |
2685 | set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call); |
2686 | ||
2687 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); | |
2688 | ||
2689 | set_gdbarch_return_value (gdbarch, xtensa_return_value); | |
2690 | ||
2691 | /* Advance PC across any prologue instructions to reach "real" code. */ | |
2692 | set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue); | |
2693 | ||
2694 | /* Stack grows downward. */ | |
2695 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2696 | ||
2697 | /* Set breakpoints. */ | |
2698 | set_gdbarch_breakpoint_from_pc (gdbarch, xtensa_breakpoint_from_pc); | |
2699 | ||
2700 | /* After breakpoint instruction or illegal instruction, pc still | |
2701 | points at break instruction, so don't decrement. */ | |
2702 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
2703 | ||
2704 | /* We don't skip args. */ | |
2705 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
2706 | ||
2707 | set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc); | |
2708 | ||
2709 | set_gdbarch_frame_align (gdbarch, xtensa_frame_align); | |
2710 | ||
5142f611 | 2711 | set_gdbarch_dummy_id (gdbarch, xtensa_dummy_id); |
ca3bf3bd DJ |
2712 | |
2713 | /* Frame handling. */ | |
2714 | frame_base_set_default (gdbarch, &xtensa_frame_base); | |
5142f611 MG |
2715 | frame_unwind_append_unwinder (gdbarch, &xtensa_unwind); |
2716 | dwarf2_append_unwinders (gdbarch); | |
ca3bf3bd DJ |
2717 | |
2718 | set_gdbarch_print_insn (gdbarch, print_insn_xtensa); | |
2719 | ||
2720 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
2721 | ||
2722 | xtensa_add_reggroups (gdbarch); | |
2723 | set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p); | |
2724 | ||
2725 | set_gdbarch_regset_from_core_section (gdbarch, | |
2726 | xtensa_regset_from_core_section); | |
2727 | ||
ee967b5f MG |
2728 | set_solib_svr4_fetch_link_map_offsets |
2729 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); | |
2730 | ||
ca3bf3bd DJ |
2731 | return gdbarch; |
2732 | } | |
2733 | ||
ca3bf3bd | 2734 | static void |
6b50c0b0 | 2735 | xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
ca3bf3bd DJ |
2736 | { |
2737 | error (_("xtensa_dump_tdep(): not implemented")); | |
2738 | } | |
2739 | ||
63807e1d PA |
2740 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
2741 | extern initialize_file_ftype _initialize_xtensa_tdep; | |
2742 | ||
ca3bf3bd DJ |
2743 | void |
2744 | _initialize_xtensa_tdep (void) | |
2745 | { | |
2746 | struct cmd_list_element *c; | |
2747 | ||
2748 | gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep); | |
2749 | xtensa_init_reggroups (); | |
2750 | ||
2751 | add_setshow_zinteger_cmd ("xtensa", | |
2752 | class_maintenance, | |
581e13c1 MS |
2753 | &xtensa_debug_level, |
2754 | _("Set Xtensa debugging."), | |
2755 | _("Show Xtensa debugging."), _("\ | |
ca3bf3bd DJ |
2756 | When non-zero, Xtensa-specific debugging is enabled. \ |
2757 | Can be 1, 2, 3, or 4 indicating the level of debugging."), | |
2758 | NULL, | |
2759 | NULL, | |
2760 | &setdebuglist, &showdebuglist); | |
2761 | } |