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ca3bf3bd DJ |
1 | /* Target-dependent code for the Xtensa port of GDB, the GNU debugger. |
2 | ||
6aba47ca | 3 | Copyright (C) 2003, 2005, 2006, 2007 Free Software Foundation, Inc. |
ca3bf3bd DJ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
ca3bf3bd DJ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
ca3bf3bd DJ |
19 | |
20 | #include "defs.h" | |
21 | #include "frame.h" | |
22 | #include "symtab.h" | |
23 | #include "symfile.h" | |
24 | #include "objfiles.h" | |
25 | #include "gdbtypes.h" | |
26 | #include "gdbcore.h" | |
27 | #include "value.h" | |
28 | #include "dis-asm.h" | |
29 | #include "inferior.h" | |
30 | #include "floatformat.h" | |
31 | #include "regcache.h" | |
32 | #include "reggroups.h" | |
33 | #include "regset.h" | |
34 | ||
35 | #include "dummy-frame.h" | |
36 | #include "elf/dwarf2.h" | |
37 | #include "dwarf2-frame.h" | |
38 | #include "dwarf2loc.h" | |
39 | #include "frame.h" | |
40 | #include "frame-base.h" | |
41 | #include "frame-unwind.h" | |
42 | ||
43 | #include "arch-utils.h" | |
44 | #include "gdbarch.h" | |
45 | #include "remote.h" | |
46 | #include "serial.h" | |
47 | ||
48 | #include "command.h" | |
49 | #include "gdbcmd.h" | |
50 | #include "gdb_assert.h" | |
51 | ||
bdb4c075 | 52 | #include "xtensa-isa.h" |
ca3bf3bd DJ |
53 | #include "xtensa-tdep.h" |
54 | ||
55 | ||
56 | static int xtensa_debug_level = 0; | |
57 | ||
58 | #define DEBUGWARN(args...) \ | |
59 | if (xtensa_debug_level > 0) \ | |
60 | fprintf_unfiltered (gdb_stdlog, "(warn ) " args) | |
61 | ||
62 | #define DEBUGINFO(args...) \ | |
63 | if (xtensa_debug_level > 1) \ | |
64 | fprintf_unfiltered (gdb_stdlog, "(info ) " args) | |
65 | ||
66 | #define DEBUGTRACE(args...) \ | |
67 | if (xtensa_debug_level > 2) \ | |
68 | fprintf_unfiltered (gdb_stdlog, "(trace) " args) | |
69 | ||
70 | #define DEBUGVERB(args...) \ | |
71 | if (xtensa_debug_level > 3) \ | |
72 | fprintf_unfiltered (gdb_stdlog, "(verb ) " args) | |
73 | ||
74 | ||
75 | /* According to the ABI, the SP must be aligned to 16-byte boundaries. */ | |
ca3bf3bd DJ |
76 | #define SP_ALIGNMENT 16 |
77 | ||
78 | ||
bdb4c075 MG |
79 | /* On Windowed ABI, we use a6 through a11 for passing arguments |
80 | to a function called by GDB because CALL4 is used. */ | |
304fe255 | 81 | #define ARGS_FIRST_REG gdbarch_tdep (current_gdbarch)->a0_base + 6 |
bdb4c075 MG |
82 | #define ARGS_NUM_REGS 6 |
83 | #define REGISTER_SIZE 4 | |
ca3bf3bd | 84 | |
ca3bf3bd | 85 | |
bdb4c075 MG |
86 | /* Extract the call size from the return address or PS register. */ |
87 | #define PS_CALLINC_SHIFT 16 | |
88 | #define PS_CALLINC_MASK 0x00030000 | |
89 | #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT) | |
90 | #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3)) | |
ca3bf3bd DJ |
91 | |
92 | ||
93 | /* Convert a live Ax register number to the corresponding Areg number. */ | |
ca3bf3bd | 94 | #define AREG_NUMBER(r, wb) \ |
304fe255 UW |
95 | ((((r) - (gdbarch_tdep (current_gdbarch)->a0_base + 0) + (((wb) \ |
96 | & ((gdbarch_tdep (current_gdbarch)->num_aregs - 1) >> 2)) << WB_SHIFT)) & \ | |
97 | (gdbarch_tdep (current_gdbarch)->num_aregs - 1)) \ | |
98 | + gdbarch_tdep (current_gdbarch)->ar_base) | |
ca3bf3bd | 99 | |
bdb4c075 | 100 | /* ABI-independent macros. */ |
304fe255 UW |
101 | #define ARG_NOF (gdbarch_tdep (current_gdbarch)->call_abi \ |
102 | == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS)) | |
103 | #define ARG_1ST (gdbarch_tdep (current_gdbarch)->call_abi \ | |
104 | == CallAbiCall0Only \ | |
105 | ? (gdbarch_tdep (current_gdbarch)->a0_base + 0) + C0_ARGS \ | |
106 | : (ARGS_FIRST_REG)) | |
ca3bf3bd DJ |
107 | |
108 | extern struct gdbarch_tdep *xtensa_config_tdep (struct gdbarch_info *); | |
109 | extern int xtensa_config_byte_order (struct gdbarch_info *); | |
110 | ||
111 | ||
112 | /* XTENSA_IS_ENTRY tests whether the first byte of an instruction | |
113 | indicates that the instruction is an ENTRY instruction. */ | |
114 | ||
115 | #define XTENSA_IS_ENTRY(op1) \ | |
4c6b5505 UW |
116 | ((gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) \ |
117 | ? ((op1) == 0x6c) : ((op1) == 0x36)) | |
ca3bf3bd | 118 | |
bdb4c075 | 119 | #define XTENSA_ENTRY_LENGTH 3 |
ca3bf3bd DJ |
120 | |
121 | /* windowing_enabled() returns true, if windowing is enabled. | |
122 | WOE must be set to 1; EXCM to 0. | |
123 | Note: We assume that EXCM is always 0 for XEA1. */ | |
124 | ||
bdb4c075 MG |
125 | #define PS_WOE (1<<18) |
126 | #define PS_EXC (1<<4) | |
127 | ||
ca3bf3bd DJ |
128 | static inline int |
129 | windowing_enabled (CORE_ADDR ps) | |
130 | { | |
bdb4c075 | 131 | return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0); |
ca3bf3bd DJ |
132 | } |
133 | ||
134 | /* Return the window size of the previous call to the function from which we | |
135 | have just returned. | |
136 | ||
137 | This function is used to extract the return value after a called function | |
bdb4c075 | 138 | has returned to the caller. On Xtensa, the register that holds the return |
ca3bf3bd DJ |
139 | value (from the perspective of the caller) depends on what call |
140 | instruction was used. For now, we are assuming that the call instruction | |
141 | precedes the current address, so we simply analyze the call instruction. | |
142 | If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4' | |
143 | method to call the inferior function. */ | |
144 | ||
145 | static int | |
146 | extract_call_winsize (CORE_ADDR pc) | |
147 | { | |
bdb4c075 | 148 | int winsize = 4; |
ca3bf3bd | 149 | int insn; |
ff7a4c00 | 150 | gdb_byte buf[4]; |
ca3bf3bd DJ |
151 | |
152 | DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc); | |
153 | ||
154 | /* Read the previous instruction (should be a call[x]{4|8|12}. */ | |
155 | read_memory (pc-3, buf, 3); | |
156 | insn = extract_unsigned_integer (buf, 3); | |
157 | ||
158 | /* Decode call instruction: | |
159 | Little Endian | |
160 | call{0,4,8,12} OFFSET || {00,01,10,11} || 0101 | |
161 | callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000 | |
162 | Big Endian | |
163 | call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET | |
164 | callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */ | |
165 | ||
4c6b5505 | 166 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) |
ca3bf3bd DJ |
167 | { |
168 | if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0)) | |
bdb4c075 | 169 | winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */ |
ca3bf3bd DJ |
170 | } |
171 | else | |
172 | { | |
173 | if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03)) | |
bdb4c075 | 174 | winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */ |
ca3bf3bd DJ |
175 | } |
176 | return winsize; | |
177 | } | |
178 | ||
179 | ||
180 | /* REGISTER INFORMATION */ | |
181 | ||
182 | /* Returns the name of a register. */ | |
ca3bf3bd DJ |
183 | static const char * |
184 | xtensa_register_name (int regnum) | |
185 | { | |
186 | /* Return the name stored in the register map. */ | |
f57d151a UW |
187 | if (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch) |
188 | + gdbarch_num_pseudo_regs (current_gdbarch)) | |
304fe255 | 189 | return gdbarch_tdep (current_gdbarch)->regmap[regnum].name; |
ca3bf3bd | 190 | |
ca3bf3bd DJ |
191 | internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum); |
192 | return 0; | |
193 | } | |
194 | ||
bdb4c075 MG |
195 | static unsigned long |
196 | xtensa_read_register (int regnum) | |
197 | { | |
198 | ULONGEST value; | |
199 | ||
200 | regcache_raw_read_unsigned (get_current_regcache (), regnum, &value); | |
201 | return (unsigned long) value; | |
202 | } | |
ca3bf3bd DJ |
203 | |
204 | /* Return the type of a register. Create a new type, if necessary. */ | |
205 | ||
206 | static struct ctype_cache | |
207 | { | |
208 | struct ctype_cache *next; | |
209 | int size; | |
210 | struct type *virtual_type; | |
211 | } *type_entries = NULL; | |
212 | ||
213 | static struct type * | |
214 | xtensa_register_type (struct gdbarch *gdbarch, int regnum) | |
215 | { | |
216 | /* Return signed integer for ARx and Ax registers. */ | |
6b50c0b0 UW |
217 | if ((regnum >= gdbarch_tdep (gdbarch)->ar_base |
218 | && regnum < gdbarch_tdep (gdbarch)->ar_base | |
219 | + gdbarch_tdep (gdbarch)->num_aregs) | |
220 | || (regnum >= gdbarch_tdep (gdbarch)->a0_base | |
221 | && regnum < gdbarch_tdep (gdbarch)->a0_base + 16)) | |
ca3bf3bd DJ |
222 | return builtin_type_int; |
223 | ||
6b50c0b0 UW |
224 | if (regnum == gdbarch_pc_regnum (gdbarch) |
225 | || regnum == gdbarch_tdep (gdbarch)->a0_base + 1) | |
ca3bf3bd DJ |
226 | return lookup_pointer_type (builtin_type_void); |
227 | ||
228 | /* Return the stored type for all other registers. */ | |
6b50c0b0 UW |
229 | else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch) |
230 | + gdbarch_num_pseudo_regs (gdbarch)) | |
ca3bf3bd | 231 | { |
6b50c0b0 | 232 | xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; |
ca3bf3bd | 233 | |
bdb4c075 | 234 | /* Set ctype for this register (only the first time). */ |
ca3bf3bd DJ |
235 | |
236 | if (reg->ctype == 0) | |
237 | { | |
238 | struct ctype_cache *tp; | |
239 | int size = reg->byte_size; | |
240 | ||
bdb4c075 MG |
241 | /* We always use the memory representation, |
242 | even if the register width is smaller. */ | |
ca3bf3bd DJ |
243 | switch (size) |
244 | { | |
245 | case 1: | |
246 | reg->ctype = builtin_type_uint8; | |
247 | break; | |
248 | ||
249 | case 2: | |
250 | reg->ctype = builtin_type_uint16; | |
251 | break; | |
252 | ||
253 | case 4: | |
254 | reg->ctype = builtin_type_uint32; | |
255 | break; | |
256 | ||
257 | case 8: | |
258 | reg->ctype = builtin_type_uint64; | |
259 | break; | |
260 | ||
261 | case 16: | |
262 | reg->ctype = builtin_type_uint128; | |
263 | break; | |
264 | ||
265 | default: | |
266 | for (tp = type_entries; tp != NULL; tp = tp->next) | |
267 | if (tp->size == size) | |
268 | break; | |
269 | ||
270 | if (tp == NULL) | |
271 | { | |
272 | char *name = xmalloc (16); | |
273 | tp = xmalloc (sizeof (struct ctype_cache)); | |
274 | tp->next = type_entries; | |
275 | type_entries = tp; | |
276 | tp->size = size; | |
277 | ||
278 | sprintf (name, "int%d", size * 8); | |
279 | tp->virtual_type = init_type (TYPE_CODE_INT, size, | |
280 | TYPE_FLAG_UNSIGNED, name, | |
281 | NULL); | |
282 | } | |
283 | ||
284 | reg->ctype = tp->virtual_type; | |
285 | } | |
286 | } | |
287 | return reg->ctype; | |
288 | } | |
289 | ||
ca3bf3bd DJ |
290 | internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum); |
291 | return 0; | |
292 | } | |
293 | ||
294 | ||
bdb4c075 | 295 | /* Return the 'local' register number for stubs, dwarf2, etc. |
ca3bf3bd DJ |
296 | The debugging information enumerates registers starting from 0 for A0 |
297 | to n for An. So, we only have to add the base number for A0. */ | |
298 | ||
299 | static int | |
300 | xtensa_reg_to_regnum (int regnum) | |
301 | { | |
302 | int i; | |
303 | ||
304 | if (regnum >= 0 && regnum < 16) | |
304fe255 | 305 | return gdbarch_tdep (current_gdbarch)->a0_base + regnum; |
ca3bf3bd | 306 | |
f57d151a UW |
307 | for (i = 0; |
308 | i < gdbarch_num_regs (current_gdbarch) | |
309 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
310 | i++) | |
304fe255 | 311 | if (regnum == gdbarch_tdep (current_gdbarch)->regmap[i].target_number) |
ca3bf3bd DJ |
312 | return i; |
313 | ||
ca3bf3bd DJ |
314 | internal_error (__FILE__, __LINE__, |
315 | _("invalid dwarf/stabs register number %d"), regnum); | |
316 | return 0; | |
317 | } | |
318 | ||
319 | ||
bdb4c075 MG |
320 | /* Write the bits of a masked register to the various registers. |
321 | Only the masked areas of these registers are modified; the other | |
322 | fields are untouched. The size of masked registers is always less | |
323 | than or equal to 32 bits. */ | |
ca3bf3bd DJ |
324 | |
325 | static void | |
9c9acae0 UW |
326 | xtensa_register_write_masked (struct regcache *regcache, |
327 | xtensa_register_t *reg, const gdb_byte *buffer) | |
ca3bf3bd DJ |
328 | { |
329 | unsigned int value[(MAX_REGISTER_SIZE + 3) / 4]; | |
ca3bf3bd DJ |
330 | const xtensa_mask_t *mask = reg->mask; |
331 | ||
332 | int shift = 0; /* Shift for next mask (mod 32). */ | |
333 | int start, size; /* Start bit and size of current mask. */ | |
334 | ||
335 | unsigned int *ptr = value; | |
336 | unsigned int regval, m, mem = 0; | |
337 | ||
338 | int bytesize = reg->byte_size; | |
339 | int bitsize = bytesize * 8; | |
340 | int i, r; | |
341 | ||
342 | DEBUGTRACE ("xtensa_register_write_masked ()\n"); | |
343 | ||
344 | /* Copy the masked register to host byte-order. */ | |
6b50c0b0 | 345 | if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
346 | for (i = 0; i < bytesize; i++) |
347 | { | |
348 | mem >>= 8; | |
349 | mem |= (buffer[bytesize - i - 1] << 24); | |
350 | if ((i & 3) == 3) | |
351 | *ptr++ = mem; | |
352 | } | |
353 | else | |
354 | for (i = 0; i < bytesize; i++) | |
355 | { | |
356 | mem >>= 8; | |
357 | mem |= (buffer[i] << 24); | |
358 | if ((i & 3) == 3) | |
359 | *ptr++ = mem; | |
360 | } | |
361 | ||
362 | /* We might have to shift the final value: | |
363 | bytesize & 3 == 0 -> nothing to do, we use the full 32 bits, | |
364 | bytesize & 3 == x -> shift (4-x) * 8. */ | |
365 | ||
366 | *ptr = mem >> (((0 - bytesize) & 3) * 8); | |
367 | ptr = value; | |
368 | mem = *ptr; | |
369 | ||
370 | /* Write the bits to the masked areas of the other registers. */ | |
371 | for (i = 0; i < mask->count; i++) | |
372 | { | |
373 | start = mask->mask[i].bit_start; | |
374 | size = mask->mask[i].bit_size; | |
375 | regval = mem >> shift; | |
376 | ||
377 | if ((shift += size) > bitsize) | |
378 | error (_("size of all masks is larger than the register")); | |
379 | ||
380 | if (shift >= 32) | |
381 | { | |
382 | mem = *(++ptr); | |
383 | shift -= 32; | |
384 | bitsize -= 32; | |
385 | ||
386 | if (shift > 0) | |
387 | regval |= mem << (size - shift); | |
388 | } | |
389 | ||
390 | /* Make sure we have a valid register. */ | |
391 | r = mask->mask[i].reg_num; | |
392 | if (r >= 0 && size > 0) | |
393 | { | |
394 | /* Don't overwrite the unmasked areas. */ | |
9c9acae0 UW |
395 | ULONGEST old_val; |
396 | regcache_cooked_read_unsigned (regcache, r, &old_val); | |
ca3bf3bd DJ |
397 | m = 0xffffffff >> (32 - size) << start; |
398 | regval <<= start; | |
9c9acae0 UW |
399 | regval = (regval & m) | (old_val & ~m); |
400 | regcache_cooked_write_unsigned (regcache, r, regval); | |
ca3bf3bd DJ |
401 | } |
402 | } | |
403 | } | |
404 | ||
405 | ||
bdb4c075 MG |
406 | /* Read a tie state or mapped registers. Read the masked areas |
407 | of the registers and assemble them into a single value. */ | |
ca3bf3bd DJ |
408 | |
409 | static void | |
9c9acae0 UW |
410 | xtensa_register_read_masked (struct regcache *regcache, |
411 | xtensa_register_t *reg, gdb_byte *buffer) | |
ca3bf3bd DJ |
412 | { |
413 | unsigned int value[(MAX_REGISTER_SIZE + 3) / 4]; | |
ca3bf3bd DJ |
414 | const xtensa_mask_t *mask = reg->mask; |
415 | ||
416 | int shift = 0; | |
417 | int start, size; | |
418 | ||
419 | unsigned int *ptr = value; | |
420 | unsigned int regval, mem = 0; | |
421 | ||
422 | int bytesize = reg->byte_size; | |
423 | int bitsize = bytesize * 8; | |
424 | int i; | |
425 | ||
426 | DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n", | |
427 | reg->name == 0 ? "" : reg->name); | |
428 | ||
429 | /* Assemble the register from the masked areas of other registers. */ | |
430 | for (i = 0; i < mask->count; i++) | |
431 | { | |
432 | int r = mask->mask[i].reg_num; | |
9c9acae0 UW |
433 | if (r >= 0) |
434 | { | |
435 | ULONGEST val; | |
436 | regcache_cooked_read_unsigned (regcache, r, &val); | |
437 | regval = (unsigned int) val; | |
438 | } | |
439 | else | |
440 | regval = 0; | |
441 | ||
ca3bf3bd DJ |
442 | start = mask->mask[i].bit_start; |
443 | size = mask->mask[i].bit_size; | |
444 | ||
445 | regval >>= start; | |
446 | ||
447 | if (size < 32) | |
448 | regval &= (0xffffffff >> (32 - size)); | |
449 | ||
450 | mem |= regval << shift; | |
451 | ||
452 | if ((shift += size) > bitsize) | |
453 | error (_("size of all masks is larger than the register")); | |
454 | ||
455 | if (shift >= 32) | |
456 | { | |
457 | *ptr++ = mem; | |
458 | bitsize -= 32; | |
459 | shift -= 32; | |
460 | ||
461 | if (shift == 0) | |
462 | mem = 0; | |
463 | else | |
464 | mem = regval >> (size - shift); | |
465 | } | |
466 | } | |
467 | ||
468 | if (shift > 0) | |
469 | *ptr = mem; | |
470 | ||
471 | /* Copy value to target byte order. */ | |
472 | ptr = value; | |
473 | mem = *ptr; | |
474 | ||
6b50c0b0 | 475 | if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
476 | for (i = 0; i < bytesize; i++) |
477 | { | |
478 | if ((i & 3) == 0) | |
479 | mem = *ptr++; | |
480 | buffer[bytesize - i - 1] = mem & 0xff; | |
481 | mem >>= 8; | |
482 | } | |
483 | else | |
484 | for (i = 0; i < bytesize; i++) | |
485 | { | |
486 | if ((i & 3) == 0) | |
487 | mem = *ptr++; | |
488 | buffer[i] = mem & 0xff; | |
489 | mem >>= 8; | |
490 | } | |
491 | } | |
492 | ||
493 | ||
494 | /* Read pseudo registers. */ | |
495 | ||
496 | static void | |
497 | xtensa_pseudo_register_read (struct gdbarch *gdbarch, | |
498 | struct regcache *regcache, | |
499 | int regnum, | |
500 | gdb_byte *buffer) | |
501 | { | |
502 | DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n", | |
503 | regnum, xtensa_register_name (regnum)); | |
504 | ||
6b50c0b0 UW |
505 | if (regnum == gdbarch_num_regs (gdbarch) |
506 | + gdbarch_num_pseudo_regs (gdbarch)) | |
507 | regnum = gdbarch_tdep (gdbarch)->a0_base + 1; | |
ca3bf3bd | 508 | |
bdb4c075 | 509 | /* Read aliases a0..a15, if this is a Windowed ABI. */ |
6b50c0b0 UW |
510 | if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers |
511 | && (regnum >= gdbarch_tdep (gdbarch)->a0_base + 0) | |
512 | && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)) | |
ca3bf3bd | 513 | { |
ff7a4c00 | 514 | gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE); |
ca3bf3bd | 515 | |
6b50c0b0 | 516 | regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf); |
ca3bf3bd DJ |
517 | regnum = AREG_NUMBER (regnum, extract_unsigned_integer (buf, 4)); |
518 | } | |
519 | ||
bdb4c075 | 520 | /* We can always read non-pseudo registers. */ |
6b50c0b0 | 521 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) |
ca3bf3bd DJ |
522 | regcache_raw_read (regcache, regnum, buffer); |
523 | ||
524 | /* Pseudo registers. */ | |
f57d151a | 525 | else if (regnum >= 0 |
6b50c0b0 UW |
526 | && regnum < gdbarch_num_regs (gdbarch) |
527 | + gdbarch_num_pseudo_regs (gdbarch)) | |
ca3bf3bd | 528 | { |
6b50c0b0 | 529 | xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; |
ca3bf3bd | 530 | xtensa_register_type_t type = reg->type; |
6b50c0b0 | 531 | int flags = gdbarch_tdep (gdbarch)->target_flags; |
ca3bf3bd | 532 | |
bdb4c075 | 533 | /* We cannot read Unknown or Unmapped registers. */ |
ca3bf3bd DJ |
534 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) |
535 | { | |
536 | if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
537 | { | |
538 | warning (_("cannot read register %s"), | |
539 | xtensa_register_name (regnum)); | |
540 | return; | |
541 | } | |
542 | } | |
543 | ||
544 | /* Some targets cannot read TIE register files. */ | |
545 | else if (type == xtRegisterTypeTieRegfile) | |
546 | { | |
547 | /* Use 'fetch' to get register? */ | |
548 | if (flags & xtTargetFlagsUseFetchStore) | |
549 | { | |
550 | warning (_("cannot read register")); | |
551 | return; | |
552 | } | |
553 | ||
554 | /* On some targets (esp. simulators), we can always read the reg. */ | |
555 | else if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
556 | { | |
557 | warning (_("cannot read register")); | |
558 | return; | |
559 | } | |
560 | } | |
561 | ||
562 | /* We can always read mapped registers. */ | |
563 | else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState) | |
564 | { | |
9c9acae0 | 565 | xtensa_register_read_masked (regcache, reg, buffer); |
ca3bf3bd DJ |
566 | return; |
567 | } | |
568 | ||
569 | /* Assume that we can read the register. */ | |
570 | regcache_raw_read (regcache, regnum, buffer); | |
571 | } | |
ca3bf3bd DJ |
572 | else |
573 | internal_error (__FILE__, __LINE__, | |
574 | _("invalid register number %d"), regnum); | |
575 | } | |
576 | ||
577 | ||
578 | /* Write pseudo registers. */ | |
579 | ||
580 | static void | |
581 | xtensa_pseudo_register_write (struct gdbarch *gdbarch, | |
582 | struct regcache *regcache, | |
583 | int regnum, | |
584 | const gdb_byte *buffer) | |
585 | { | |
586 | DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n", | |
587 | regnum, xtensa_register_name (regnum)); | |
588 | ||
6b50c0b0 UW |
589 | if (regnum == gdbarch_num_regs (gdbarch) |
590 | + gdbarch_num_pseudo_regs (gdbarch)) | |
591 | regnum = gdbarch_tdep (gdbarch)->a0_base + 1; | |
ca3bf3bd | 592 | |
bdb4c075 | 593 | /* Renumber register, if aliase a0..a15 on Windowed ABI. */ |
6b50c0b0 UW |
594 | if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers |
595 | && (regnum >= gdbarch_tdep (gdbarch)->a0_base + 0) | |
596 | && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)) | |
ca3bf3bd | 597 | { |
ff7a4c00 | 598 | gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE); |
ca3bf3bd DJ |
599 | unsigned int wb; |
600 | ||
304fe255 | 601 | regcache_raw_read (regcache, |
6b50c0b0 | 602 | gdbarch_tdep (gdbarch)->wb_regnum, buf); |
ca3bf3bd DJ |
603 | regnum = AREG_NUMBER (regnum, extract_unsigned_integer (buf, 4)); |
604 | } | |
605 | ||
606 | /* We can always write 'core' registers. | |
607 | Note: We might have converted Ax->ARy. */ | |
6b50c0b0 | 608 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) |
ca3bf3bd DJ |
609 | regcache_raw_write (regcache, regnum, buffer); |
610 | ||
611 | /* Pseudo registers. */ | |
f57d151a | 612 | else if (regnum >= 0 |
6b50c0b0 UW |
613 | && regnum < gdbarch_num_regs (gdbarch) |
614 | + gdbarch_num_pseudo_regs (gdbarch)) | |
ca3bf3bd | 615 | { |
6b50c0b0 | 616 | xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; |
ca3bf3bd | 617 | xtensa_register_type_t type = reg->type; |
6b50c0b0 | 618 | int flags = gdbarch_tdep (gdbarch)->target_flags; |
ca3bf3bd | 619 | |
bdb4c075 MG |
620 | /* On most targets, we cannot write registers |
621 | of type "Unknown" or "Unmapped". */ | |
ca3bf3bd DJ |
622 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) |
623 | { | |
624 | if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
625 | { | |
626 | warning (_("cannot write register %s"), | |
627 | xtensa_register_name (regnum)); | |
628 | return; | |
629 | } | |
630 | } | |
631 | ||
632 | /* Some targets cannot read TIE register files. */ | |
633 | else if (type == xtRegisterTypeTieRegfile) | |
634 | { | |
635 | /* Use 'store' to get register? */ | |
636 | if (flags & xtTargetFlagsUseFetchStore) | |
637 | { | |
638 | warning (_("cannot write register")); | |
639 | return; | |
640 | } | |
641 | ||
642 | /* On some targets (esp. simulators), we can always write | |
643 | the register. */ | |
ca3bf3bd DJ |
644 | else if ((flags & xtTargetFlagsNonVisibleRegs) == 0) |
645 | { | |
646 | warning (_("cannot write register")); | |
647 | return; | |
648 | } | |
649 | } | |
650 | ||
651 | /* We can always write mapped registers. */ | |
652 | else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState) | |
653 | { | |
9c9acae0 | 654 | xtensa_register_write_masked (regcache, reg, buffer); |
ca3bf3bd DJ |
655 | return; |
656 | } | |
657 | ||
658 | /* Assume that we can write the register. */ | |
659 | regcache_raw_write (regcache, regnum, buffer); | |
660 | } | |
ca3bf3bd DJ |
661 | else |
662 | internal_error (__FILE__, __LINE__, | |
663 | _("invalid register number %d"), regnum); | |
664 | } | |
665 | ||
ca3bf3bd DJ |
666 | static struct reggroup *xtensa_ar_reggroup; |
667 | static struct reggroup *xtensa_user_reggroup; | |
668 | static struct reggroup *xtensa_vectra_reggroup; | |
7b871568 | 669 | static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR]; |
ca3bf3bd DJ |
670 | |
671 | static void | |
672 | xtensa_init_reggroups (void) | |
673 | { | |
674 | xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP); | |
675 | xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP); | |
676 | xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP); | |
ca3bf3bd | 677 | |
7b871568 MG |
678 | xtensa_cp[0] = reggroup_new ("cp0", USER_REGGROUP); |
679 | xtensa_cp[1] = reggroup_new ("cp1", USER_REGGROUP); | |
680 | xtensa_cp[2] = reggroup_new ("cp2", USER_REGGROUP); | |
681 | xtensa_cp[3] = reggroup_new ("cp3", USER_REGGROUP); | |
682 | xtensa_cp[4] = reggroup_new ("cp4", USER_REGGROUP); | |
683 | xtensa_cp[5] = reggroup_new ("cp5", USER_REGGROUP); | |
684 | xtensa_cp[6] = reggroup_new ("cp6", USER_REGGROUP); | |
685 | xtensa_cp[7] = reggroup_new ("cp7", USER_REGGROUP); | |
686 | } | |
ca3bf3bd DJ |
687 | |
688 | static void | |
689 | xtensa_add_reggroups (struct gdbarch *gdbarch) | |
690 | { | |
7b871568 MG |
691 | int i; |
692 | ||
693 | /* Predefined groups. */ | |
ca3bf3bd DJ |
694 | reggroup_add (gdbarch, all_reggroup); |
695 | reggroup_add (gdbarch, save_reggroup); | |
696 | reggroup_add (gdbarch, restore_reggroup); | |
697 | reggroup_add (gdbarch, system_reggroup); | |
7b871568 MG |
698 | reggroup_add (gdbarch, vector_reggroup); |
699 | reggroup_add (gdbarch, general_reggroup); | |
700 | reggroup_add (gdbarch, float_reggroup); | |
701 | ||
702 | /* Xtensa-specific groups. */ | |
703 | reggroup_add (gdbarch, xtensa_ar_reggroup); | |
704 | reggroup_add (gdbarch, xtensa_user_reggroup); | |
705 | reggroup_add (gdbarch, xtensa_vectra_reggroup); | |
ca3bf3bd | 706 | |
7b871568 MG |
707 | for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++) |
708 | reggroup_add (gdbarch, xtensa_cp[i]); | |
ca3bf3bd DJ |
709 | } |
710 | ||
7b871568 MG |
711 | static int |
712 | xtensa_coprocessor_register_group (struct reggroup *group) | |
713 | { | |
714 | int i; | |
715 | ||
716 | for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++) | |
717 | if (group == xtensa_cp[i]) | |
718 | return i; | |
719 | ||
720 | return -1; | |
721 | } | |
ca3bf3bd DJ |
722 | |
723 | #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \ | |
724 | | XTENSA_REGISTER_FLAGS_WRITABLE \ | |
725 | | XTENSA_REGISTER_FLAGS_VOLATILE) | |
726 | ||
727 | #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \ | |
728 | | XTENSA_REGISTER_FLAGS_WRITABLE) | |
729 | ||
730 | static int | |
731 | xtensa_register_reggroup_p (struct gdbarch *gdbarch, | |
732 | int regnum, | |
733 | struct reggroup *group) | |
734 | { | |
6b50c0b0 | 735 | xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; |
ca3bf3bd DJ |
736 | xtensa_register_type_t type = reg->type; |
737 | xtensa_register_group_t rg = reg->group; | |
7b871568 | 738 | int cp_number; |
ca3bf3bd DJ |
739 | |
740 | /* First, skip registers that are not visible to this target | |
741 | (unknown and unmapped registers when not using ISS). */ | |
742 | ||
743 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) | |
744 | return 0; | |
745 | if (group == all_reggroup) | |
746 | return 1; | |
747 | if (group == xtensa_ar_reggroup) | |
748 | return rg & xtRegisterGroupAddrReg; | |
749 | if (group == xtensa_user_reggroup) | |
750 | return rg & xtRegisterGroupUser; | |
751 | if (group == float_reggroup) | |
752 | return rg & xtRegisterGroupFloat; | |
753 | if (group == general_reggroup) | |
754 | return rg & xtRegisterGroupGeneral; | |
755 | if (group == float_reggroup) | |
756 | return rg & xtRegisterGroupFloat; | |
757 | if (group == system_reggroup) | |
758 | return rg & xtRegisterGroupState; | |
759 | if (group == vector_reggroup || group == xtensa_vectra_reggroup) | |
760 | return rg & xtRegisterGroupVectra; | |
761 | if (group == save_reggroup || group == restore_reggroup) | |
6b50c0b0 | 762 | return (regnum < gdbarch_num_regs (gdbarch) |
ca3bf3bd | 763 | && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID); |
7b871568 MG |
764 | if ((cp_number = xtensa_coprocessor_register_group (group)) >= 0) |
765 | return rg & (xtRegisterGroupCP0 << cp_number); | |
ca3bf3bd DJ |
766 | else |
767 | return 1; | |
768 | } | |
769 | ||
770 | ||
ca3bf3bd DJ |
771 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
772 | in the general-purpose register set REGSET to register cache | |
bdb4c075 | 773 | REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */ |
ca3bf3bd DJ |
774 | |
775 | static void | |
776 | xtensa_supply_gregset (const struct regset *regset, | |
777 | struct regcache *rc, | |
778 | int regnum, | |
779 | const void *gregs, | |
780 | size_t len) | |
781 | { | |
782 | const xtensa_elf_gregset_t *regs = gregs; | |
6b50c0b0 | 783 | struct gdbarch *gdbarch = get_regcache_arch (rc); |
ca3bf3bd DJ |
784 | int i; |
785 | ||
786 | DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...) \n", regnum); | |
787 | ||
6b50c0b0 UW |
788 | if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1) |
789 | regcache_raw_supply (rc, gdbarch_pc_regnum (gdbarch), (char *) ®s->pc); | |
790 | if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1) | |
791 | regcache_raw_supply (rc, gdbarch_ps_regnum (gdbarch), (char *) ®s->ps); | |
792 | if (regnum == gdbarch_tdep (gdbarch)->wb_regnum || regnum == -1) | |
793 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->wb_regnum, | |
304fe255 | 794 | (char *) ®s->windowbase); |
6b50c0b0 UW |
795 | if (regnum == gdbarch_tdep (gdbarch)->ws_regnum || regnum == -1) |
796 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ws_regnum, | |
304fe255 | 797 | (char *) ®s->windowstart); |
6b50c0b0 UW |
798 | if (regnum == gdbarch_tdep (gdbarch)->lbeg_regnum || regnum == -1) |
799 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lbeg_regnum, | |
304fe255 | 800 | (char *) ®s->lbeg); |
6b50c0b0 UW |
801 | if (regnum == gdbarch_tdep (gdbarch)->lend_regnum || regnum == -1) |
802 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lend_regnum, | |
304fe255 | 803 | (char *) ®s->lend); |
6b50c0b0 UW |
804 | if (regnum == gdbarch_tdep (gdbarch)->lcount_regnum || regnum == -1) |
805 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lcount_regnum, | |
304fe255 | 806 | (char *) ®s->lcount); |
6b50c0b0 UW |
807 | if (regnum == gdbarch_tdep (gdbarch)->sar_regnum || regnum == -1) |
808 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->sar_regnum, | |
304fe255 | 809 | (char *) ®s->sar); |
6b50c0b0 UW |
810 | if (regnum == gdbarch_tdep (gdbarch)->exccause_regnum || regnum == -1) |
811 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->exccause_regnum, | |
304fe255 | 812 | (char *) ®s->exccause); |
6b50c0b0 UW |
813 | if (regnum == gdbarch_tdep (gdbarch)->excvaddr_regnum || regnum == -1) |
814 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->excvaddr_regnum, | |
304fe255 | 815 | (char *) ®s->excvaddr); |
6b50c0b0 UW |
816 | if (regnum >=gdbarch_tdep (gdbarch)->ar_base |
817 | && regnum < gdbarch_tdep (gdbarch)->ar_base | |
818 | + gdbarch_tdep (gdbarch)->num_aregs) | |
304fe255 UW |
819 | regcache_raw_supply (rc, regnum, |
820 | (char *) ®s->ar[regnum - gdbarch_tdep | |
6b50c0b0 | 821 | (gdbarch)->ar_base]); |
ca3bf3bd DJ |
822 | else if (regnum == -1) |
823 | { | |
6b50c0b0 UW |
824 | for (i = 0; i < gdbarch_tdep (gdbarch)->num_aregs; ++i) |
825 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ar_base + i, | |
304fe255 | 826 | (char *) ®s->ar[i]); |
ca3bf3bd DJ |
827 | } |
828 | } | |
829 | ||
830 | ||
831 | /* Xtensa register set. */ | |
832 | ||
833 | static struct regset | |
834 | xtensa_gregset = | |
835 | { | |
836 | NULL, | |
837 | xtensa_supply_gregset | |
838 | }; | |
839 | ||
840 | ||
bdb4c075 MG |
841 | /* Return the appropriate register set for the core |
842 | section identified by SECT_NAME and SECT_SIZE. */ | |
ca3bf3bd DJ |
843 | |
844 | static const struct regset * | |
845 | xtensa_regset_from_core_section (struct gdbarch *core_arch, | |
846 | const char *sect_name, | |
847 | size_t sect_size) | |
848 | { | |
849 | DEBUGTRACE ("xtensa_regset_from_core_section " | |
850 | "(..., sect_name==\"%s\", sect_size==%x) \n", | |
bdb4c075 | 851 | sect_name, sect_size); |
ca3bf3bd DJ |
852 | |
853 | if (strcmp (sect_name, ".reg") == 0 | |
854 | && sect_size >= sizeof(xtensa_elf_gregset_t)) | |
855 | return &xtensa_gregset; | |
856 | ||
857 | return NULL; | |
858 | } | |
859 | ||
860 | ||
bdb4c075 | 861 | /* Handling frames. */ |
ca3bf3bd | 862 | |
bdb4c075 MG |
863 | /* Number of registers to save in case of Windowed ABI. */ |
864 | #define XTENSA_NUM_SAVED_AREGS 12 | |
ca3bf3bd | 865 | |
bdb4c075 MG |
866 | /* Frame cache part for Windowed ABI. */ |
867 | typedef struct xtensa_windowed_frame_cache | |
ca3bf3bd | 868 | { |
ca3bf3bd DJ |
869 | int wb; /* Base for this frame; -1 if not in regfile. */ |
870 | int callsize; /* Call size to next frame. */ | |
871 | int ws; | |
872 | CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS]; | |
bdb4c075 MG |
873 | } xtensa_windowed_frame_cache_t; |
874 | ||
875 | /* Call0 ABI Definitions. */ | |
876 | ||
877 | #define C0_MAXOPDS 3 /* Maximum number of operands for prologue analysis. */ | |
878 | #define C0_NREGS 16 /* Number of A-registers to track. */ | |
879 | #define C0_CLESV 12 /* Callee-saved registers are here and up. */ | |
880 | #define C0_SP 1 /* Register used as SP. */ | |
881 | #define C0_FP 15 /* Register used as FP. */ | |
882 | #define C0_RA 0 /* Register used as return address. */ | |
883 | #define C0_ARGS 2 /* Register used as first arg/retval. */ | |
884 | #define C0_NARGS 6 /* Number of A-regs for args/retvals. */ | |
885 | ||
886 | /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each | |
887 | A-register where the current content of the reg came from (in terms | |
888 | of an original reg and a constant). Negative values of c0_rt[n].fp_reg | |
889 | mean that the orignal content of the register was saved to the stack. | |
890 | c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't | |
891 | know where SP will end up until the entire prologue has been analyzed. */ | |
892 | ||
893 | #define C0_CONST -1 /* fr_reg value if register contains a constant. */ | |
894 | #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */ | |
895 | #define C0_NOSTK -1 /* to_stk value if register has not been stored. */ | |
896 | ||
897 | extern xtensa_isa xtensa_default_isa; | |
898 | ||
899 | typedef struct xtensa_c0reg | |
900 | { | |
901 | int fr_reg; /* original register from which register content | |
902 | is derived, or C0_CONST, or C0_INEXP. */ | |
903 | int fr_ofs; /* constant offset from reg, or immediate value. */ | |
904 | int to_stk; /* offset from original SP to register (4-byte aligned), | |
905 | or C0_NOSTK if register has not been saved. */ | |
906 | } xtensa_c0reg_t; | |
907 | ||
908 | ||
909 | /* Frame cache part for Call0 ABI. */ | |
910 | typedef struct xtensa_call0_frame_cache | |
911 | { | |
912 | int c0_frmsz; /* Stack frame size. */ | |
913 | int c0_hasfp; /* Current frame uses frame pointer. */ | |
914 | int fp_regnum; /* A-register used as FP. */ | |
915 | int c0_fp; /* Actual value of frame pointer. */ | |
916 | xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */ | |
917 | } xtensa_call0_frame_cache_t; | |
918 | ||
919 | typedef struct xtensa_frame_cache | |
920 | { | |
921 | CORE_ADDR base; /* Stack pointer of the next frame. */ | |
922 | CORE_ADDR pc; /* PC at the entry point to the function. */ | |
923 | CORE_ADDR ra; /* The raw return address. */ | |
924 | CORE_ADDR ps; /* The PS register of the frame. */ | |
925 | CORE_ADDR prev_sp; /* Stack Pointer of the frame. */ | |
926 | int call0; /* It's a call0 framework (else windowed). */ | |
927 | union | |
928 | { | |
929 | xtensa_windowed_frame_cache_t wd; /* call0 == false. */ | |
930 | xtensa_call0_frame_cache_t c0; /* call0 == true. */ | |
931 | }; | |
ca3bf3bd DJ |
932 | } xtensa_frame_cache_t; |
933 | ||
934 | ||
935 | static struct xtensa_frame_cache * | |
bdb4c075 | 936 | xtensa_alloc_frame_cache (int windowed) |
ca3bf3bd DJ |
937 | { |
938 | xtensa_frame_cache_t *cache; | |
939 | int i; | |
940 | ||
941 | DEBUGTRACE ("xtensa_alloc_frame_cache ()\n"); | |
942 | ||
943 | cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t); | |
944 | ||
945 | cache->base = 0; | |
946 | cache->pc = 0; | |
947 | cache->ra = 0; | |
ca3bf3bd | 948 | cache->ps = 0; |
ca3bf3bd | 949 | cache->prev_sp = 0; |
bdb4c075 MG |
950 | cache->call0 = !windowed; |
951 | if (cache->call0) | |
952 | { | |
953 | cache->c0.c0_frmsz = -1; | |
954 | cache->c0.c0_hasfp = 0; | |
955 | cache->c0.fp_regnum = -1; | |
956 | cache->c0.c0_fp = -1; | |
ca3bf3bd | 957 | |
bdb4c075 MG |
958 | for (i = 0; i < C0_NREGS; i++) |
959 | { | |
960 | cache->c0.c0_rt[i].fr_reg = i; | |
961 | cache->c0.c0_rt[i].fr_ofs = 0; | |
962 | cache->c0.c0_rt[i].to_stk = C0_NOSTK; | |
963 | } | |
964 | } | |
965 | else | |
966 | { | |
967 | cache->wd.wb = 0; | |
968 | cache->wd.callsize = -1; | |
ca3bf3bd | 969 | |
bdb4c075 MG |
970 | for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++) |
971 | cache->wd.aregs[i] = -1; | |
972 | } | |
ca3bf3bd DJ |
973 | return cache; |
974 | } | |
975 | ||
976 | ||
977 | static CORE_ADDR | |
978 | xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) | |
979 | { | |
980 | return address & ~15; | |
981 | } | |
982 | ||
983 | ||
984 | static CORE_ADDR | |
985 | xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
986 | { | |
ff7a4c00 | 987 | gdb_byte buf[8]; |
ca3bf3bd DJ |
988 | |
989 | DEBUGTRACE ("xtensa_unwind_pc (next_frame = %p)\n", next_frame); | |
990 | ||
6b50c0b0 | 991 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
ca3bf3bd DJ |
992 | |
993 | DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) | |
994 | extract_typed_address (buf, builtin_type_void_func_ptr)); | |
995 | ||
996 | return extract_typed_address (buf, builtin_type_void_func_ptr); | |
997 | } | |
998 | ||
999 | ||
1000 | static struct frame_id | |
1001 | xtensa_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1002 | { | |
1003 | CORE_ADDR pc, fp; | |
ca3bf3bd | 1004 | |
bdb4c075 | 1005 | /* next_frame->prev is a dummy frame. Return a frame ID of that frame. */ |
ca3bf3bd DJ |
1006 | |
1007 | DEBUGTRACE ("xtensa_unwind_dummy_id ()\n"); | |
1008 | ||
1009 | pc = frame_pc_unwind (next_frame); | |
304fe255 | 1010 | fp = frame_unwind_register_unsigned |
6b50c0b0 | 1011 | (next_frame, gdbarch_tdep (gdbarch)->a0_base + 1); |
ca3bf3bd DJ |
1012 | |
1013 | /* Make dummy frame ID unique by adding a constant. */ | |
bdb4c075 | 1014 | return frame_id_build (fp + SP_ALIGNMENT, pc); |
ca3bf3bd DJ |
1015 | } |
1016 | ||
bdb4c075 MG |
1017 | /* The key values to identify the frame using "cache" are |
1018 | ||
1019 | cache->base = SP of this frame; | |
1020 | cache->pc = entry-PC (entry point of the frame function); | |
1021 | cache->prev_sp = SP of the previous frame. | |
1022 | */ | |
1023 | ||
1024 | static void | |
1025 | call0_frame_cache (struct frame_info *next_frame, | |
1026 | xtensa_frame_cache_t *cache, | |
1027 | CORE_ADDR pc); | |
ca3bf3bd DJ |
1028 | |
1029 | static struct xtensa_frame_cache * | |
1030 | xtensa_frame_cache (struct frame_info *next_frame, void **this_cache) | |
1031 | { | |
1032 | xtensa_frame_cache_t *cache; | |
ca3bf3bd | 1033 | CORE_ADDR ra, wb, ws, pc, sp, ps; |
6b50c0b0 UW |
1034 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
1035 | unsigned int ps_regnum = gdbarch_ps_regnum (gdbarch); | |
ca3bf3bd | 1036 | char op1; |
bdb4c075 | 1037 | int windowed; |
ca3bf3bd DJ |
1038 | |
1039 | DEBUGTRACE ("xtensa_frame_cache (next_frame %p, *this_cache %p)\n", | |
1040 | next_frame, this_cache ? *this_cache : (void*)0xdeadbeef); | |
1041 | ||
ca3bf3bd DJ |
1042 | if (*this_cache) |
1043 | return *this_cache; | |
1044 | ||
bdb4c075 MG |
1045 | windowed = windowing_enabled (xtensa_read_register (ps_regnum)); |
1046 | ||
ca3bf3bd | 1047 | /* Get pristine xtensa-frame. */ |
bdb4c075 | 1048 | cache = xtensa_alloc_frame_cache (windowed); |
ca3bf3bd DJ |
1049 | *this_cache = cache; |
1050 | ||
3e8c568d | 1051 | pc = frame_unwind_register_unsigned (next_frame, |
6b50c0b0 | 1052 | gdbarch_pc_regnum (gdbarch)); |
ca3bf3bd | 1053 | |
bdb4c075 | 1054 | if (windowed) |
ca3bf3bd | 1055 | { |
bdb4c075 | 1056 | /* Get WINDOWBASE, WINDOWSTART, and PS registers. */ |
304fe255 | 1057 | wb = frame_unwind_register_unsigned |
6b50c0b0 | 1058 | (next_frame, gdbarch_tdep (gdbarch)->wb_regnum); |
304fe255 | 1059 | ws = frame_unwind_register_unsigned |
6b50c0b0 | 1060 | (next_frame, gdbarch_tdep (gdbarch)->ws_regnum); |
bdb4c075 | 1061 | ps = frame_unwind_register_unsigned (next_frame, ps_regnum); |
ca3bf3bd | 1062 | |
bdb4c075 MG |
1063 | op1 = read_memory_integer (pc, 1); |
1064 | if (XTENSA_IS_ENTRY (op1)) | |
ca3bf3bd | 1065 | { |
bdb4c075 | 1066 | int callinc = CALLINC (ps); |
304fe255 | 1067 | ra = frame_unwind_register_unsigned |
6b50c0b0 | 1068 | (next_frame, gdbarch_tdep (gdbarch)->a0_base + 0 + callinc * 4); |
bdb4c075 MG |
1069 | |
1070 | DEBUGINFO("[xtensa_frame_cache] 'entry' at 0x%08x\n (callinc = %d)", | |
1071 | (int)pc, callinc); | |
1072 | ||
1073 | /* ENTRY hasn't been executed yet, therefore callsize is still 0. */ | |
1074 | cache->wd.callsize = 0; | |
1075 | cache->wd.wb = wb; | |
1076 | cache->wd.ws = ws; | |
304fe255 | 1077 | cache->prev_sp = frame_unwind_register_unsigned |
6b50c0b0 | 1078 | (next_frame, gdbarch_tdep (gdbarch)->a0_base + 1); |
bdb4c075 MG |
1079 | } |
1080 | else | |
1081 | { | |
304fe255 | 1082 | ra = frame_unwind_register_unsigned |
6b50c0b0 | 1083 | (next_frame, gdbarch_tdep (gdbarch)->a0_base + 0); |
bdb4c075 | 1084 | cache->wd.callsize = WINSIZE (ra); |
304fe255 | 1085 | cache->wd.wb = (wb - cache->wd.callsize / 4) |
6b50c0b0 | 1086 | & (gdbarch_tdep (gdbarch)->num_aregs / 4 - 1); |
bdb4c075 | 1087 | cache->wd.ws = ws & ~(1 << wb); |
ca3bf3bd DJ |
1088 | } |
1089 | ||
bdb4c075 MG |
1090 | cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME); |
1091 | cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff); | |
1092 | cache->ps = (ps & ~PS_CALLINC_MASK) | |
1093 | | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT); | |
1094 | ||
1095 | if (cache->wd.ws == 0) | |
ca3bf3bd | 1096 | { |
bdb4c075 | 1097 | int i; |
ca3bf3bd | 1098 | |
bdb4c075 | 1099 | /* Set A0...A3. */ |
304fe255 | 1100 | sp = frame_unwind_register_unsigned |
6b50c0b0 | 1101 | (next_frame, gdbarch_tdep (gdbarch)->a0_base + 1) - 16; |
bdb4c075 MG |
1102 | |
1103 | for (i = 0; i < 4; i++, sp += 4) | |
1104 | { | |
1105 | cache->wd.aregs[i] = sp; | |
1106 | } | |
ca3bf3bd | 1107 | |
bdb4c075 | 1108 | if (cache->wd.callsize > 4) |
ca3bf3bd | 1109 | { |
bdb4c075 MG |
1110 | /* Set A4...A7/A11. */ |
1111 | /* Read an SP of the previous frame. */ | |
1112 | sp = (CORE_ADDR) read_memory_integer (sp - 12, 4); | |
1113 | sp -= cache->wd.callsize * 4; | |
1114 | ||
1115 | for ( /* i=4 */ ; i < cache->wd.callsize; i++, sp += 4) | |
1116 | { | |
1117 | cache->wd.aregs[i] = sp; | |
1118 | } | |
ca3bf3bd DJ |
1119 | } |
1120 | } | |
ca3bf3bd | 1121 | |
bdb4c075 MG |
1122 | if ((cache->prev_sp == 0) && ( ra != 0 )) |
1123 | /* If RA is equal to 0 this frame is an outermost frame. Leave | |
1124 | cache->prev_sp unchanged marking the boundary of the frame stack. */ | |
ca3bf3bd | 1125 | { |
bdb4c075 MG |
1126 | if (cache->wd.ws == 0) |
1127 | { | |
1128 | /* Register window overflow already happened. | |
1129 | We can read caller's SP from the proper spill loction. */ | |
1130 | cache->prev_sp = | |
1131 | read_memory_integer (cache->wd.aregs[1], | |
6b50c0b0 UW |
1132 | register_size (gdbarch, |
1133 | gdbarch_tdep (gdbarch)->a0_base + 1)); | |
bdb4c075 MG |
1134 | } |
1135 | else | |
1136 | { | |
1137 | /* Read caller's frame SP directly from the previous window. */ | |
304fe255 | 1138 | int regnum = AREG_NUMBER |
6b50c0b0 | 1139 | (gdbarch_tdep (gdbarch)->a0_base + 1, |
304fe255 | 1140 | cache->wd.wb); |
ca3bf3bd | 1141 | |
bdb4c075 MG |
1142 | cache->prev_sp = xtensa_read_register (regnum); |
1143 | } | |
ca3bf3bd DJ |
1144 | } |
1145 | } | |
bdb4c075 MG |
1146 | else /* Call0 framework. */ |
1147 | { | |
1148 | call0_frame_cache (next_frame, cache, pc); | |
1149 | } | |
ca3bf3bd | 1150 | |
304fe255 | 1151 | cache->base = frame_unwind_register_unsigned |
6b50c0b0 | 1152 | (next_frame, gdbarch_tdep (gdbarch)->a0_base + 1); |
ca3bf3bd | 1153 | |
ca3bf3bd DJ |
1154 | return cache; |
1155 | } | |
1156 | ||
ca3bf3bd DJ |
1157 | static void |
1158 | xtensa_frame_this_id (struct frame_info *next_frame, | |
1159 | void **this_cache, | |
1160 | struct frame_id *this_id) | |
1161 | { | |
1162 | struct xtensa_frame_cache *cache = | |
1163 | xtensa_frame_cache (next_frame, this_cache); | |
bdb4c075 | 1164 | struct frame_id id; |
ca3bf3bd | 1165 | |
bdb4c075 MG |
1166 | DEBUGTRACE ("xtensa_frame_this_id (next 0x%08x, *this 0x%08x)\n", |
1167 | (unsigned int) next_frame, (unsigned int) *this_cache); | |
ca3bf3bd DJ |
1168 | |
1169 | if (cache->prev_sp == 0) | |
1170 | return; | |
1171 | ||
bdb4c075 MG |
1172 | id = frame_id_build (cache->prev_sp, cache->pc); |
1173 | if (frame_id_eq (id, get_frame_id(next_frame))) | |
1174 | { | |
1175 | warning(_("\ | |
1176 | Frame stack is corrupted. That could happen because of \ | |
1177 | setting register(s) from GDB or stopping execution \ | |
1178 | inside exception handler. Frame backtracing has stopped. \ | |
1179 | It can make some GDB commands work inappropriately.\n")); | |
1180 | cache->prev_sp = 0; | |
1181 | return; | |
1182 | } | |
1183 | (*this_id) = id; | |
ca3bf3bd DJ |
1184 | } |
1185 | ||
bdb4c075 MG |
1186 | static int |
1187 | call0_frame_get_reg_at_entry (struct frame_info *next_frame, | |
1188 | struct xtensa_frame_cache *cache, | |
1189 | int regnum, | |
1190 | CORE_ADDR *addrp, | |
1191 | enum lval_type *lval, | |
1192 | gdb_byte *valuep) | |
1193 | { | |
1194 | CORE_ADDR fp, spe; | |
1195 | int stkofs; | |
6b50c0b0 UW |
1196 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
1197 | int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base | |
1198 | && regnum <= (gdbarch_tdep (gdbarch)->ar_base + C0_NREGS)) | |
1199 | ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum; | |
bdb4c075 MG |
1200 | |
1201 | /* Determine stack pointer on entry to this function, based on FP. */ | |
1202 | spe = cache->c0.c0_fp - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs; | |
1203 | ||
1204 | /* If register was saved to the stack frame in the prologue, retrieve it. */ | |
1205 | stkofs = cache->c0.c0_rt[reg].to_stk; | |
1206 | if (stkofs != C0_NOSTK) | |
1207 | { | |
1208 | *lval = lval_memory; | |
1209 | *addrp = spe + stkofs; | |
1210 | ||
1211 | if (valuep) | |
6b50c0b0 | 1212 | read_memory (*addrp, valuep, register_size (gdbarch, regnum)); |
bdb4c075 MG |
1213 | |
1214 | return 1; | |
1215 | } | |
1216 | ||
1217 | /* If not callee-saved or if known to have been overwritten, give up. */ | |
1218 | if (reg < C0_CLESV | |
1219 | || cache->c0.c0_rt[reg].fr_reg != reg | |
1220 | || cache->c0.c0_rt[reg].fr_ofs != 0) | |
1221 | return 0; | |
1222 | ||
1223 | if (get_frame_type (next_frame) != NORMAL_FRAME) | |
1224 | /* TODO: Do we need a special case for DUMMY_FRAME here? */ | |
1225 | return 0; | |
1226 | ||
1227 | return call0_frame_get_reg_at_entry (get_next_frame(next_frame), | |
1228 | cache, regnum, addrp, lval, valuep); | |
1229 | } | |
ca3bf3bd DJ |
1230 | |
1231 | static void | |
1232 | xtensa_frame_prev_register (struct frame_info *next_frame, | |
1233 | void **this_cache, | |
1234 | int regnum, | |
1235 | int *optimizedp, | |
1236 | enum lval_type *lvalp, | |
1237 | CORE_ADDR *addrp, | |
1238 | int *realnump, | |
1239 | gdb_byte *valuep) | |
1240 | { | |
6b50c0b0 | 1241 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
ca3bf3bd DJ |
1242 | struct xtensa_frame_cache *cache = |
1243 | xtensa_frame_cache (next_frame, this_cache); | |
1244 | CORE_ADDR saved_reg = 0; | |
1245 | int done = 1; | |
1246 | ||
bdb4c075 MG |
1247 | DEBUGTRACE ("xtensa_frame_prev_register (next 0x%08x, " |
1248 | "*this 0x%08x, regnum %d (%s), ...)\n", | |
1249 | (unsigned int) next_frame, | |
1250 | *this_cache ? (unsigned int) *this_cache : 0, regnum, | |
ca3bf3bd DJ |
1251 | xtensa_register_name (regnum)); |
1252 | ||
6b50c0b0 | 1253 | if (regnum ==gdbarch_pc_regnum (gdbarch)) |
bdb4c075 | 1254 | saved_reg = cache->ra; |
6b50c0b0 | 1255 | else if (regnum == gdbarch_tdep (gdbarch)->a0_base + 1) |
bdb4c075 MG |
1256 | saved_reg = cache->prev_sp; |
1257 | else if (!cache->call0) | |
ca3bf3bd | 1258 | { |
6b50c0b0 | 1259 | if (regnum == gdbarch_tdep (gdbarch)->ws_regnum) |
bdb4c075 MG |
1260 | { |
1261 | if (cache->wd.ws != 0) | |
1262 | saved_reg = cache->wd.ws; | |
1263 | else | |
1264 | saved_reg = 1 << cache->wd.wb; | |
1265 | } | |
6b50c0b0 | 1266 | else if (regnum == gdbarch_tdep (gdbarch)->wb_regnum) |
bdb4c075 | 1267 | saved_reg = cache->wd.wb; |
6b50c0b0 | 1268 | else if (regnum == gdbarch_ps_regnum (gdbarch)) |
bdb4c075 | 1269 | saved_reg = cache->ps; |
ca3bf3bd | 1270 | else |
bdb4c075 | 1271 | done = 0; |
ca3bf3bd | 1272 | } |
ca3bf3bd DJ |
1273 | else |
1274 | done = 0; | |
1275 | ||
1276 | if (done) | |
1277 | { | |
1278 | *optimizedp = 0; | |
1279 | *lvalp = not_lval; | |
1280 | *addrp = 0; | |
1281 | *realnump = -1; | |
1282 | if (valuep) | |
1283 | store_unsigned_integer (valuep, 4, saved_reg); | |
1284 | ||
1285 | return; | |
1286 | } | |
1287 | ||
bdb4c075 | 1288 | if (!cache->call0) /* Windowed ABI. */ |
ca3bf3bd | 1289 | { |
bdb4c075 | 1290 | /* Convert A-register numbers to AR-register numbers. */ |
6b50c0b0 UW |
1291 | if (regnum >= gdbarch_tdep (gdbarch)->a0_base + 0 |
1292 | && regnum <= gdbarch_tdep (gdbarch)->a0_base + 15) | |
bdb4c075 | 1293 | regnum = AREG_NUMBER (regnum, cache->wd.wb); |
ca3bf3bd | 1294 | |
bdb4c075 | 1295 | /* Check if AR-register has been saved to stack. */ |
6b50c0b0 UW |
1296 | if (regnum >= gdbarch_tdep (gdbarch)->ar_base |
1297 | && regnum <= (gdbarch_tdep (gdbarch)->ar_base | |
1298 | + gdbarch_tdep (gdbarch)->num_aregs)) | |
bdb4c075 | 1299 | { |
6b50c0b0 | 1300 | int areg = regnum - gdbarch_tdep (gdbarch)->ar_base |
304fe255 | 1301 | - (cache->wd.wb * 4); |
ca3bf3bd | 1302 | |
bdb4c075 MG |
1303 | if (areg >= 0 |
1304 | && areg < XTENSA_NUM_SAVED_AREGS | |
1305 | && cache->wd.aregs[areg] != -1) | |
1306 | { | |
1307 | *optimizedp = 0; | |
1308 | *lvalp = lval_memory; | |
1309 | *addrp = cache->wd.aregs[areg]; | |
1310 | *realnump = -1; | |
ca3bf3bd | 1311 | |
bdb4c075 MG |
1312 | if (valuep) |
1313 | read_memory (*addrp, valuep, | |
6b50c0b0 | 1314 | register_size (gdbarch, regnum)); |
bdb4c075 MG |
1315 | |
1316 | DEBUGINFO ("[xtensa_frame_prev_register] register on stack\n"); | |
1317 | return; | |
1318 | } | |
ca3bf3bd DJ |
1319 | } |
1320 | } | |
bdb4c075 MG |
1321 | else /* Call0 ABI. */ |
1322 | { | |
6b50c0b0 UW |
1323 | int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base |
1324 | && regnum <= (gdbarch_tdep (gdbarch)->ar_base | |
304fe255 | 1325 | + C0_NREGS)) |
6b50c0b0 | 1326 | ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum; |
ca3bf3bd | 1327 | |
bdb4c075 MG |
1328 | if (reg < C0_NREGS) |
1329 | { | |
1330 | CORE_ADDR spe; | |
1331 | int stkofs; | |
1332 | ||
1333 | /* If register was saved in the prologue, retrieve it. */ | |
1334 | stkofs = cache->c0.c0_rt[reg].to_stk; | |
1335 | if (stkofs != C0_NOSTK) | |
1336 | { | |
1337 | /* Determine SP on entry based on FP. */ | |
1338 | spe = cache->c0.c0_fp | |
1339 | - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs; | |
1340 | *optimizedp = 0; | |
1341 | *lvalp = lval_memory; | |
1342 | *addrp = spe + stkofs; | |
1343 | *realnump = -1; | |
1344 | ||
1345 | if (valuep) | |
1346 | read_memory (*addrp, valuep, | |
6b50c0b0 | 1347 | register_size (gdbarch, regnum)); |
bdb4c075 MG |
1348 | |
1349 | DEBUGINFO ("[xtensa_frame_prev_register] register on stack\n"); | |
1350 | return; | |
1351 | } | |
1352 | } | |
1353 | } | |
1354 | ||
1355 | /* All other registers have been either saved to | |
1356 | the stack or are still alive in the processor. */ | |
ca3bf3bd DJ |
1357 | |
1358 | *optimizedp = 0; | |
1359 | *lvalp = lval_register; | |
1360 | *addrp = 0; | |
1361 | *realnump = regnum; | |
1362 | if (valuep) | |
1363 | frame_unwind_register (next_frame, (*realnump), valuep); | |
1364 | } | |
1365 | ||
1366 | ||
1367 | static const struct frame_unwind | |
1368 | xtensa_frame_unwind = | |
1369 | { | |
1370 | NORMAL_FRAME, | |
1371 | xtensa_frame_this_id, | |
1372 | xtensa_frame_prev_register | |
1373 | }; | |
1374 | ||
1375 | static const struct frame_unwind * | |
1376 | xtensa_frame_sniffer (struct frame_info *next_frame) | |
1377 | { | |
1378 | return &xtensa_frame_unwind; | |
1379 | } | |
1380 | ||
1381 | static CORE_ADDR | |
1382 | xtensa_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
1383 | { | |
1384 | struct xtensa_frame_cache *cache = | |
1385 | xtensa_frame_cache (next_frame, this_cache); | |
1386 | ||
1387 | return cache->base; | |
1388 | } | |
1389 | ||
1390 | static const struct frame_base | |
1391 | xtensa_frame_base = | |
1392 | { | |
1393 | &xtensa_frame_unwind, | |
1394 | xtensa_frame_base_address, | |
1395 | xtensa_frame_base_address, | |
1396 | xtensa_frame_base_address | |
1397 | }; | |
1398 | ||
1399 | ||
1400 | static void | |
1401 | xtensa_extract_return_value (struct type *type, | |
1402 | struct regcache *regcache, | |
1403 | void *dst) | |
1404 | { | |
6b50c0b0 | 1405 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
ca3bf3bd DJ |
1406 | bfd_byte *valbuf = dst; |
1407 | int len = TYPE_LENGTH (type); | |
1408 | ULONGEST pc, wb; | |
1409 | int callsize, areg; | |
1410 | int offset = 0; | |
1411 | ||
1412 | DEBUGTRACE ("xtensa_extract_return_value (...)\n"); | |
1413 | ||
1414 | gdb_assert(len > 0); | |
1415 | ||
6b50c0b0 | 1416 | if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
bdb4c075 MG |
1417 | { |
1418 | /* First, we have to find the caller window in the register file. */ | |
6b50c0b0 | 1419 | regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc); |
bdb4c075 | 1420 | callsize = extract_call_winsize (pc); |
ca3bf3bd | 1421 | |
bdb4c075 MG |
1422 | /* On Xtensa, we can return up to 4 words (or 2 for call12). */ |
1423 | if (len > (callsize > 8 ? 8 : 16)) | |
1424 | internal_error (__FILE__, __LINE__, | |
1425 | _("cannot extract return value of %d bytes long"), len); | |
ca3bf3bd | 1426 | |
bdb4c075 MG |
1427 | /* Get the register offset of the return |
1428 | register (A2) in the caller window. */ | |
304fe255 | 1429 | regcache_raw_read_unsigned |
6b50c0b0 UW |
1430 | (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb); |
1431 | areg = AREG_NUMBER(gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb); | |
bdb4c075 MG |
1432 | } |
1433 | else | |
1434 | { | |
1435 | /* No windowing hardware - Call0 ABI. */ | |
6b50c0b0 | 1436 | areg = gdbarch_tdep (gdbarch)->a0_base + 0 + C0_ARGS; |
bdb4c075 | 1437 | } |
ca3bf3bd DJ |
1438 | |
1439 | DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len); | |
1440 | ||
6b50c0b0 | 1441 | if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1442 | offset = 4 - len; |
1443 | ||
1444 | for (; len > 0; len -= 4, areg++, valbuf += 4) | |
1445 | { | |
1446 | if (len < 4) | |
1447 | regcache_raw_read_part (regcache, areg, offset, len, valbuf); | |
1448 | else | |
1449 | regcache_raw_read (regcache, areg, valbuf); | |
1450 | } | |
1451 | } | |
1452 | ||
1453 | ||
1454 | static void | |
1455 | xtensa_store_return_value (struct type *type, | |
1456 | struct regcache *regcache, | |
1457 | const void *dst) | |
1458 | { | |
6b50c0b0 | 1459 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
ca3bf3bd DJ |
1460 | const bfd_byte *valbuf = dst; |
1461 | unsigned int areg; | |
1462 | ULONGEST pc, wb; | |
1463 | int callsize; | |
1464 | int len = TYPE_LENGTH (type); | |
1465 | int offset = 0; | |
1466 | ||
1467 | DEBUGTRACE ("xtensa_store_return_value (...)\n"); | |
1468 | ||
6b50c0b0 | 1469 | if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
bdb4c075 | 1470 | { |
6b50c0b0 UW |
1471 | regcache_raw_read_unsigned |
1472 | (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb); | |
1473 | regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc); | |
bdb4c075 | 1474 | callsize = extract_call_winsize (pc); |
ca3bf3bd | 1475 | |
bdb4c075 MG |
1476 | if (len > (callsize > 8 ? 8 : 16)) |
1477 | internal_error (__FILE__, __LINE__, | |
1478 | _("unimplemented for this length: %d"), | |
1479 | TYPE_LENGTH (type)); | |
6b50c0b0 | 1480 | areg = AREG_NUMBER (gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb); |
ca3bf3bd | 1481 | |
bdb4c075 | 1482 | DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n", |
ca3bf3bd | 1483 | callsize, (int) wb); |
bdb4c075 MG |
1484 | } |
1485 | else | |
1486 | { | |
6b50c0b0 | 1487 | areg = gdbarch_tdep (gdbarch)->a0_base + 0 + C0_ARGS; |
bdb4c075 | 1488 | } |
ca3bf3bd | 1489 | |
6b50c0b0 | 1490 | if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1491 | offset = 4 - len; |
1492 | ||
ca3bf3bd DJ |
1493 | for (; len > 0; len -= 4, areg++, valbuf += 4) |
1494 | { | |
1495 | if (len < 4) | |
1496 | regcache_raw_write_part (regcache, areg, offset, len, valbuf); | |
1497 | else | |
1498 | regcache_raw_write (regcache, areg, valbuf); | |
1499 | } | |
1500 | } | |
1501 | ||
1502 | ||
bdb4c075 | 1503 | static enum return_value_convention |
ca3bf3bd DJ |
1504 | xtensa_return_value (struct gdbarch *gdbarch, |
1505 | struct type *valtype, | |
1506 | struct regcache *regcache, | |
1507 | gdb_byte *readbuf, | |
1508 | const gdb_byte *writebuf) | |
1509 | { | |
bdb4c075 | 1510 | /* Structures up to 16 bytes are returned in registers. */ |
ca3bf3bd DJ |
1511 | |
1512 | int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT | |
1513 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
1514 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
1515 | && TYPE_LENGTH (valtype) > 16); | |
1516 | ||
1517 | if (struct_return) | |
1518 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1519 | ||
1520 | DEBUGTRACE ("xtensa_return_value(...)\n"); | |
1521 | ||
1522 | if (writebuf != NULL) | |
1523 | { | |
1524 | xtensa_store_return_value (valtype, regcache, writebuf); | |
1525 | } | |
1526 | ||
1527 | if (readbuf != NULL) | |
1528 | { | |
1529 | gdb_assert (!struct_return); | |
1530 | xtensa_extract_return_value (valtype, regcache, readbuf); | |
1531 | } | |
1532 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1533 | } | |
1534 | ||
1535 | ||
1536 | /* DUMMY FRAME */ | |
1537 | ||
1538 | static CORE_ADDR | |
1539 | xtensa_push_dummy_call (struct gdbarch *gdbarch, | |
1540 | struct value *function, | |
1541 | struct regcache *regcache, | |
1542 | CORE_ADDR bp_addr, | |
1543 | int nargs, | |
1544 | struct value **args, | |
1545 | CORE_ADDR sp, | |
1546 | int struct_return, | |
1547 | CORE_ADDR struct_addr) | |
1548 | { | |
1549 | int i; | |
1550 | int size, onstack_size; | |
ff7a4c00 | 1551 | gdb_byte *buf = (gdb_byte *) alloca (16); |
ca3bf3bd DJ |
1552 | CORE_ADDR ra, ps; |
1553 | struct argument_info | |
1554 | { | |
1555 | const bfd_byte *contents; | |
1556 | int length; | |
1557 | int onstack; /* onstack == 0 => in reg */ | |
1558 | int align; /* alignment */ | |
1559 | union | |
1560 | { | |
1561 | int offset; /* stack offset if on stack */ | |
1562 | int regno; /* regno if in register */ | |
1563 | } u; | |
1564 | }; | |
1565 | ||
1566 | struct argument_info *arg_info = | |
1567 | (struct argument_info *) alloca (nargs * sizeof (struct argument_info)); | |
1568 | ||
1569 | CORE_ADDR osp = sp; | |
1570 | ||
1571 | DEBUGTRACE ("xtensa_push_dummy_call (...)\n"); | |
1572 | ||
1573 | if (xtensa_debug_level > 3) | |
1574 | { | |
1575 | int i; | |
1576 | DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs); | |
1577 | DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, " | |
1578 | "struct_addr=0x%x\n", | |
1579 | (int) sp, (int) struct_return, (int) struct_addr); | |
1580 | ||
1581 | for (i = 0; i < nargs; i++) | |
1582 | { | |
1583 | struct value *arg = args[i]; | |
1584 | struct type *arg_type = check_typedef (value_type (arg)); | |
bdb4c075 MG |
1585 | fprintf_unfiltered (gdb_stdlog, "%2d: 0x%08x %3d ", |
1586 | i, (int) arg, TYPE_LENGTH (arg_type)); | |
ca3bf3bd DJ |
1587 | switch (TYPE_CODE (arg_type)) |
1588 | { | |
1589 | case TYPE_CODE_INT: | |
1590 | fprintf_unfiltered (gdb_stdlog, "int"); | |
1591 | break; | |
1592 | case TYPE_CODE_STRUCT: | |
1593 | fprintf_unfiltered (gdb_stdlog, "struct"); | |
1594 | break; | |
1595 | default: | |
1596 | fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type)); | |
1597 | break; | |
1598 | } | |
bdb4c075 MG |
1599 | fprintf_unfiltered (gdb_stdlog, " 0x%08x\n", |
1600 | (unsigned int) value_contents (arg)); | |
ca3bf3bd DJ |
1601 | } |
1602 | } | |
1603 | ||
1604 | /* First loop: collect information. | |
1605 | Cast into type_long. (This shouldn't happen often for C because | |
1606 | GDB already does this earlier.) It's possible that GDB could | |
1607 | do it all the time but it's harmless to leave this code here. */ | |
1608 | ||
1609 | size = 0; | |
1610 | onstack_size = 0; | |
1611 | i = 0; | |
1612 | ||
1613 | if (struct_return) | |
1614 | size = REGISTER_SIZE; | |
1615 | ||
1616 | for (i = 0; i < nargs; i++) | |
1617 | { | |
1618 | struct argument_info *info = &arg_info[i]; | |
1619 | struct value *arg = args[i]; | |
1620 | struct type *arg_type = check_typedef (value_type (arg)); | |
1621 | ||
1622 | switch (TYPE_CODE (arg_type)) | |
1623 | { | |
1624 | case TYPE_CODE_INT: | |
1625 | case TYPE_CODE_BOOL: | |
1626 | case TYPE_CODE_CHAR: | |
1627 | case TYPE_CODE_RANGE: | |
1628 | case TYPE_CODE_ENUM: | |
1629 | ||
1630 | /* Cast argument to long if necessary as the mask does it too. */ | |
1631 | if (TYPE_LENGTH (arg_type) < TYPE_LENGTH (builtin_type_long)) | |
1632 | { | |
1633 | arg_type = builtin_type_long; | |
1634 | arg = value_cast (arg_type, arg); | |
1635 | } | |
bdb4c075 MG |
1636 | /* Aligment is equal to the type length for the basic types. */ |
1637 | info->align = TYPE_LENGTH (arg_type); | |
ca3bf3bd DJ |
1638 | break; |
1639 | ||
1640 | case TYPE_CODE_FLT: | |
1641 | ||
1642 | /* Align doubles correctly. */ | |
1643 | if (TYPE_LENGTH (arg_type) == TYPE_LENGTH (builtin_type_double)) | |
1644 | info->align = TYPE_LENGTH (builtin_type_double); | |
1645 | else | |
1646 | info->align = TYPE_LENGTH (builtin_type_long); | |
1647 | break; | |
1648 | ||
1649 | case TYPE_CODE_STRUCT: | |
1650 | default: | |
1651 | info->align = TYPE_LENGTH (builtin_type_long); | |
1652 | break; | |
1653 | } | |
1654 | info->length = TYPE_LENGTH (arg_type); | |
1655 | info->contents = value_contents (arg); | |
1656 | ||
1657 | /* Align size and onstack_size. */ | |
1658 | size = (size + info->align - 1) & ~(info->align - 1); | |
1659 | onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1); | |
1660 | ||
bdb4c075 | 1661 | if (size + info->length > REGISTER_SIZE * ARG_NOF) |
ca3bf3bd DJ |
1662 | { |
1663 | info->onstack = 1; | |
1664 | info->u.offset = onstack_size; | |
1665 | onstack_size += info->length; | |
1666 | } | |
1667 | else | |
1668 | { | |
1669 | info->onstack = 0; | |
bdb4c075 | 1670 | info->u.regno = ARG_1ST + size / REGISTER_SIZE; |
ca3bf3bd DJ |
1671 | } |
1672 | size += info->length; | |
1673 | } | |
1674 | ||
1675 | /* Adjust the stack pointer and align it. */ | |
1676 | sp = align_down (sp - onstack_size, SP_ALIGNMENT); | |
1677 | ||
bdb4c075 | 1678 | /* Simulate MOVSP, if Windowed ABI. */ |
6b50c0b0 | 1679 | if ((gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
304fe255 | 1680 | && (sp != osp)) |
ca3bf3bd DJ |
1681 | { |
1682 | read_memory (osp - 16, buf, 16); | |
1683 | write_memory (sp - 16, buf, 16); | |
1684 | } | |
1685 | ||
1686 | /* Second Loop: Load arguments. */ | |
1687 | ||
1688 | if (struct_return) | |
1689 | { | |
1690 | store_unsigned_integer (buf, REGISTER_SIZE, struct_addr); | |
bdb4c075 | 1691 | regcache_cooked_write (regcache, ARG_1ST, buf); |
ca3bf3bd DJ |
1692 | } |
1693 | ||
1694 | for (i = 0; i < nargs; i++) | |
1695 | { | |
1696 | struct argument_info *info = &arg_info[i]; | |
1697 | ||
1698 | if (info->onstack) | |
1699 | { | |
1700 | int n = info->length; | |
1701 | CORE_ADDR offset = sp + info->u.offset; | |
1702 | ||
1703 | /* Odd-sized structs are aligned to the lower side of a memory | |
1704 | word in big-endian mode and require a shift. This only | |
1705 | applies for structures smaller than one word. */ | |
1706 | ||
4c6b5505 | 1707 | if (n < REGISTER_SIZE |
6b50c0b0 | 1708 | && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1709 | offset += (REGISTER_SIZE - n); |
1710 | ||
1711 | write_memory (offset, info->contents, info->length); | |
1712 | ||
1713 | } | |
1714 | else | |
1715 | { | |
1716 | int n = info->length; | |
1717 | const bfd_byte *cp = info->contents; | |
1718 | int r = info->u.regno; | |
1719 | ||
1720 | /* Odd-sized structs are aligned to the lower side of registers in | |
1721 | big-endian mode and require a shift. The odd-sized leftover will | |
1722 | be at the end. Note that this is only true for structures smaller | |
1723 | than REGISTER_SIZE; for larger odd-sized structures the excess | |
1724 | will be left-aligned in the register on both endiannesses. */ | |
1725 | ||
4c6b5505 | 1726 | if (n < REGISTER_SIZE |
6b50c0b0 | 1727 | && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1728 | { |
1729 | ULONGEST v = extract_unsigned_integer (cp, REGISTER_SIZE); | |
1730 | v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT); | |
1731 | ||
1732 | store_unsigned_integer (buf, REGISTER_SIZE, v); | |
1733 | regcache_cooked_write (regcache, r, buf); | |
1734 | ||
1735 | cp += REGISTER_SIZE; | |
1736 | n -= REGISTER_SIZE; | |
1737 | r++; | |
1738 | } | |
1739 | else | |
1740 | while (n > 0) | |
1741 | { | |
ca3bf3bd DJ |
1742 | regcache_cooked_write (regcache, r, cp); |
1743 | ||
ca3bf3bd DJ |
1744 | cp += REGISTER_SIZE; |
1745 | n -= REGISTER_SIZE; | |
1746 | r++; | |
1747 | } | |
1748 | } | |
1749 | } | |
1750 | ||
ca3bf3bd | 1751 | /* Set the return address of dummy frame to the dummy address. |
bdb4c075 | 1752 | The return address for the current function (in A0) is |
ca3bf3bd DJ |
1753 | saved in the dummy frame, so we can savely overwrite A0 here. */ |
1754 | ||
6b50c0b0 | 1755 | if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
bdb4c075 MG |
1756 | { |
1757 | ra = (bp_addr & 0x3fffffff) | 0x40000000; | |
6b50c0b0 | 1758 | regcache_raw_read (regcache, gdbarch_ps_regnum (gdbarch), buf); |
bdb4c075 | 1759 | ps = extract_unsigned_integer (buf, 4) & ~0x00030000; |
304fe255 | 1760 | regcache_cooked_write_unsigned |
6b50c0b0 | 1761 | (regcache, gdbarch_tdep (gdbarch)->a0_base + 4, ra); |
bdb4c075 | 1762 | regcache_cooked_write_unsigned (regcache, |
6b50c0b0 | 1763 | gdbarch_ps_regnum (gdbarch), |
bdb4c075 MG |
1764 | ps | 0x00010000); |
1765 | } | |
1766 | else | |
1767 | { | |
1768 | /* Simulate CALL0: write RA into A0 register. */ | |
304fe255 | 1769 | regcache_cooked_write_unsigned |
6b50c0b0 | 1770 | (regcache, gdbarch_tdep (gdbarch)->a0_base + 0, bp_addr); |
bdb4c075 | 1771 | } |
ca3bf3bd DJ |
1772 | |
1773 | /* Set new stack pointer and return it. */ | |
304fe255 | 1774 | regcache_cooked_write_unsigned (regcache, |
6b50c0b0 | 1775 | gdbarch_tdep (gdbarch)->a0_base + 1, sp); |
ca3bf3bd DJ |
1776 | /* Make dummy frame ID unique by adding a constant. */ |
1777 | return sp + SP_ALIGNMENT; | |
1778 | } | |
1779 | ||
1780 | ||
1781 | /* Return a breakpoint for the current location of PC. We always use | |
1782 | the density version if we have density instructions (regardless of the | |
1783 | current instruction at PC), and use regular instructions otherwise. */ | |
1784 | ||
1785 | #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 } | |
1786 | #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 } | |
1787 | #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f } | |
1788 | #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 } | |
1789 | ||
bdb4c075 | 1790 | static const unsigned char * |
ca3bf3bd DJ |
1791 | xtensa_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
1792 | { | |
ff7a4c00 MG |
1793 | static unsigned char big_breakpoint[] = BIG_BREAKPOINT; |
1794 | static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT; | |
1795 | static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT; | |
1796 | static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT; | |
ca3bf3bd DJ |
1797 | |
1798 | DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr); | |
1799 | ||
304fe255 | 1800 | if (gdbarch_tdep (current_gdbarch)->isa_use_density_instructions) |
ca3bf3bd | 1801 | { |
4c6b5505 | 1802 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1803 | { |
1804 | *lenptr = sizeof (density_big_breakpoint); | |
1805 | return density_big_breakpoint; | |
1806 | } | |
1807 | else | |
1808 | { | |
1809 | *lenptr = sizeof (density_little_breakpoint); | |
1810 | return density_little_breakpoint; | |
1811 | } | |
1812 | } | |
1813 | else | |
1814 | { | |
4c6b5505 | 1815 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1816 | { |
1817 | *lenptr = sizeof (big_breakpoint); | |
1818 | return big_breakpoint; | |
1819 | } | |
1820 | else | |
1821 | { | |
1822 | *lenptr = sizeof (little_breakpoint); | |
1823 | return little_breakpoint; | |
1824 | } | |
1825 | } | |
1826 | } | |
1827 | ||
bdb4c075 MG |
1828 | /* Call0 ABI support routines. */ |
1829 | ||
1830 | /* Call0 opcode class. Opcodes are preclassified according to what they | |
1831 | mean for Call0 prologue analysis, and their number of significant operands. | |
1832 | The purpose of this is to simplify prologue analysis by separating | |
1833 | instruction decoding (libisa) from the semantics of prologue analysis. */ | |
1834 | ||
1835 | typedef enum { | |
1836 | c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */ | |
1837 | c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */ | |
1838 | c0opc_flow, /* Flow control insn. */ | |
1839 | c0opc_entry, /* ENTRY indicates non-Call0 prologue. */ | |
1840 | c0opc_break, /* Debugger software breakpoints. */ | |
1841 | c0opc_add, /* Adding two registers. */ | |
1842 | c0opc_addi, /* Adding a register and an immediate. */ | |
1843 | c0opc_sub, /* Subtracting a register from a register. */ | |
1844 | c0opc_mov, /* Moving a register to a register. */ | |
1845 | c0opc_movi, /* Moving an immediate to a register. */ | |
1846 | c0opc_l32r, /* Loading a literal. */ | |
1847 | c0opc_s32i, /* Storing word at fixed offset from a base register. */ | |
1848 | c0opc_NrOf /* Number of opcode classifications. */ | |
1849 | } xtensa_insn_kind; | |
1850 | ||
1851 | ||
1852 | /* Classify an opcode based on what it means for Call0 prologue analysis. */ | |
1853 | ||
1854 | static xtensa_insn_kind | |
1855 | call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc) | |
1856 | { | |
1857 | const char *opcname; | |
1858 | xtensa_insn_kind opclass = c0opc_uninteresting; | |
1859 | ||
1860 | DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc); | |
1861 | ||
1862 | /* Get opcode name and handle special classifications. */ | |
1863 | ||
1864 | opcname = xtensa_opcode_name (isa, opc); | |
1865 | ||
1866 | if (opcname == NULL | |
1867 | || strcasecmp (opcname, "ill") == 0 | |
1868 | || strcasecmp (opcname, "ill.n") == 0) | |
1869 | opclass = c0opc_illegal; | |
1870 | else if (strcasecmp (opcname, "break") == 0 | |
1871 | || strcasecmp (opcname, "break.n") == 0) | |
1872 | opclass = c0opc_break; | |
1873 | else if (strcasecmp (opcname, "entry") == 0) | |
1874 | opclass = c0opc_entry; | |
1875 | else if (xtensa_opcode_is_branch (isa, opc) > 0 | |
1876 | || xtensa_opcode_is_jump (isa, opc) > 0 | |
1877 | || xtensa_opcode_is_loop (isa, opc) > 0 | |
1878 | || xtensa_opcode_is_call (isa, opc) > 0 | |
1879 | || strcasecmp (opcname, "simcall") == 0 | |
1880 | || strcasecmp (opcname, "syscall") == 0) | |
1881 | opclass = c0opc_flow; | |
1882 | ||
1883 | /* Also, classify specific opcodes that need to be tracked. */ | |
1884 | else if (strcasecmp (opcname, "add") == 0 | |
1885 | || strcasecmp (opcname, "add.n") == 0) | |
1886 | opclass = c0opc_add; | |
1887 | else if (strcasecmp (opcname, "addi") == 0 | |
1888 | || strcasecmp (opcname, "addi.n") == 0 | |
1889 | || strcasecmp (opcname, "addmi") == 0) | |
1890 | opclass = c0opc_addi; | |
1891 | else if (strcasecmp (opcname, "sub") == 0) | |
1892 | opclass = c0opc_sub; | |
1893 | else if (strcasecmp (opcname, "mov.n") == 0 | |
1894 | || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */ | |
1895 | opclass = c0opc_mov; | |
1896 | else if (strcasecmp (opcname, "movi") == 0 | |
1897 | || strcasecmp (opcname, "movi.n") == 0) | |
1898 | opclass = c0opc_movi; | |
1899 | else if (strcasecmp (opcname, "l32r") == 0) | |
1900 | opclass = c0opc_l32r; | |
1901 | else if (strcasecmp (opcname, "s32i") == 0 | |
1902 | || strcasecmp (opcname, "s32i.n") == 0) | |
1903 | opclass = c0opc_s32i; | |
1904 | ||
1905 | return opclass; | |
1906 | } | |
1907 | ||
1908 | /* Tracks register movement/mutation for a given operation, which may | |
1909 | be within a bundle. Updates the destination register tracking info | |
1910 | accordingly. The pc is needed only for pc-relative load instructions | |
1911 | (eg. l32r). The SP register number is needed to identify stores to | |
1912 | the stack frame. */ | |
1913 | ||
1914 | static void | |
1915 | call0_track_op (xtensa_c0reg_t dst[], xtensa_c0reg_t src[], | |
1916 | xtensa_insn_kind opclass, int nods, unsigned odv[], | |
1917 | CORE_ADDR pc, int spreg) | |
1918 | { | |
1919 | unsigned litbase, litaddr, litval; | |
1920 | ||
1921 | switch (opclass) | |
1922 | { | |
1923 | case c0opc_addi: | |
1924 | /* 3 operands: dst, src, imm. */ | |
1925 | gdb_assert (nods == 3); | |
1926 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
1927 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2]; | |
1928 | break; | |
1929 | case c0opc_add: | |
1930 | /* 3 operands: dst, src1, src2. */ | |
1931 | gdb_assert (nods == 3); | |
1932 | if (src[odv[1]].fr_reg == C0_CONST) | |
1933 | { | |
1934 | dst[odv[0]].fr_reg = src[odv[2]].fr_reg; | |
1935 | dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs; | |
1936 | } | |
1937 | else if (src[odv[2]].fr_reg == C0_CONST) | |
1938 | { | |
1939 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
1940 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs; | |
1941 | } | |
1942 | else dst[odv[0]].fr_reg = C0_INEXP; | |
1943 | break; | |
1944 | case c0opc_sub: | |
1945 | /* 3 operands: dst, src1, src2. */ | |
1946 | gdb_assert (nods == 3); | |
1947 | if (src[odv[2]].fr_reg == C0_CONST) | |
1948 | { | |
1949 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
1950 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs; | |
1951 | } | |
1952 | else dst[odv[0]].fr_reg = C0_INEXP; | |
1953 | break; | |
1954 | case c0opc_mov: | |
1955 | /* 2 operands: dst, src [, src]. */ | |
1956 | gdb_assert (nods == 2); | |
1957 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
1958 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs; | |
1959 | break; | |
1960 | case c0opc_movi: | |
1961 | /* 2 operands: dst, imm. */ | |
1962 | gdb_assert (nods == 2); | |
1963 | dst[odv[0]].fr_reg = C0_CONST; | |
1964 | dst[odv[0]].fr_ofs = odv[1]; | |
1965 | break; | |
1966 | case c0opc_l32r: | |
1967 | /* 2 operands: dst, literal offset. */ | |
1968 | gdb_assert (nods == 2); | |
1969 | /* litbase = xtensa_get_litbase (pc); can be also used. */ | |
304fe255 UW |
1970 | litbase = (gdbarch_tdep (current_gdbarch)->litbase_regnum == -1) |
1971 | ? 0 : xtensa_read_register | |
1972 | (gdbarch_tdep (current_gdbarch)->litbase_regnum); | |
bdb4c075 MG |
1973 | litaddr = litbase & 1 |
1974 | ? (litbase & ~1) + (signed)odv[1] | |
1975 | : (pc + 3 + (signed)odv[1]) & ~3; | |
1976 | litval = read_memory_integer(litaddr, 4); | |
1977 | dst[odv[0]].fr_reg = C0_CONST; | |
1978 | dst[odv[0]].fr_ofs = litval; | |
1979 | break; | |
1980 | case c0opc_s32i: | |
1981 | /* 3 operands: value, base, offset. */ | |
1982 | gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS); | |
1983 | if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */ | |
1984 | && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */ | |
1985 | && src[odv[0]].fr_reg >= 0 /* Value is from a register. */ | |
1986 | && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */ | |
1987 | && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */ | |
1988 | { | |
1989 | /* ISA encoding guarantees alignment. But, check it anyway. */ | |
1990 | gdb_assert ((odv[2] & 3) == 0); | |
1991 | dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2]; | |
1992 | } | |
1993 | break; | |
1994 | default: | |
1995 | gdb_assert (0); | |
1996 | } | |
1997 | } | |
1998 | ||
1999 | /* Analyze prologue of the function at start address to determine if it uses | |
2000 | the Call0 ABI, and if so track register moves and linear modifications | |
2001 | in the prologue up to the PC or just beyond the prologue, whichever is first. | |
2002 | An 'entry' instruction indicates non-Call0 ABI and the end of the prologue. | |
2003 | The prologue may overlap non-prologue instructions but is guaranteed to end | |
2004 | by the first flow-control instruction (jump, branch, call or return). | |
2005 | Since an optimized function may move information around and change the | |
2006 | stack frame arbitrarily during the prologue, the information is guaranteed | |
2007 | valid only at the point in the function indicated by the PC. | |
2008 | May be used to skip the prologue or identify the ABI, w/o tracking. | |
2009 | ||
2010 | Returns: Address of first instruction after prologue, or PC (whichever | |
2011 | is first), or 0, if decoding failed (in libisa). | |
2012 | Input args: | |
2013 | start Start address of function/prologue. | |
2014 | pc Program counter to stop at. Use 0 to continue to end of prologue. | |
2015 | If 0, avoids infinite run-on in corrupt code memory by bounding | |
2016 | the scan to the end of the function if that can be determined. | |
2017 | nregs Number of general registers to track (size of rt[] array). | |
2018 | InOut args: | |
2019 | rt[] Array[nregs] of xtensa_c0reg structures for register tracking info. | |
2020 | If NULL, registers are not tracked. | |
2021 | Output args: | |
2022 | call0 If != NULL, *call0 is set non-zero if Call0 ABI used, else 0 | |
2023 | (more accurately, non-zero until 'entry' insn is encountered). | |
2024 | ||
2025 | Note that these may produce useful results even if decoding fails | |
2026 | because they begin with default assumptions that analysis may change. */ | |
2027 | ||
2028 | static CORE_ADDR | |
2029 | call0_analyze_prologue (CORE_ADDR start, CORE_ADDR pc, | |
2030 | int nregs, xtensa_c0reg_t rt[], int *call0) | |
2031 | { | |
2032 | CORE_ADDR ia; /* Current insn address in prologue. */ | |
2033 | CORE_ADDR ba = 0; /* Current address at base of insn buffer. */ | |
2034 | CORE_ADDR bt; /* Current address at top+1 of insn buffer. */ | |
2035 | #define BSZ 32 /* Instruction buffer size. */ | |
2036 | char ibuf[BSZ]; /* Instruction buffer for decoding prologue. */ | |
2037 | xtensa_isa isa; /* libisa ISA handle. */ | |
2038 | xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */ | |
2039 | xtensa_format ifmt; /* libisa instruction format. */ | |
2040 | int ilen, islots, is; /* Instruction length, nbr slots, current slot. */ | |
2041 | xtensa_opcode opc; /* Opcode in current slot. */ | |
2042 | xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */ | |
2043 | int nods; /* Opcode number of operands. */ | |
2044 | unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */ | |
2045 | xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */ | |
2046 | int j; /* General loop counter. */ | |
2047 | int fail = 0; /* Set non-zero and exit, if decoding fails. */ | |
2048 | CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */ | |
2049 | CORE_ADDR end_pc; /* The PC for the lust function insn. */ | |
2050 | ||
2051 | struct symtab_and_line prologue_sal; | |
2052 | ||
2053 | DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n", | |
2054 | (int)start, (int)pc); | |
2055 | ||
2056 | /* Try to limit the scan to the end of the function if a non-zero pc | |
2057 | arg was not supplied to avoid probing beyond the end of valid memory. | |
2058 | If memory is full of garbage that classifies as c0opc_uninteresting. | |
2059 | If this fails (eg. if no symbols) pc ends up 0 as it was. | |
2060 | Intialize the Call0 frame and register tracking info. | |
2061 | Assume it's Call0 until an 'entry' instruction is encountered. | |
2062 | Assume we may be in the prologue until we hit a flow control instr. */ | |
2063 | ||
2064 | rtmp = NULL; | |
2065 | body_pc = INT_MAX; | |
2066 | end_pc = 0; | |
2067 | ||
2068 | /* Find out, if we have an information about the prologue from DWARF. */ | |
2069 | prologue_sal = find_pc_line (start, 0); | |
2070 | if (prologue_sal.line != 0) /* Found debug info. */ | |
2071 | body_pc = prologue_sal.end; | |
2072 | ||
2073 | /* If we are going to analyze the prologue in general without knowing about | |
2074 | the current PC, make the best assumtion for the end of the prologue. */ | |
2075 | if (pc == 0) | |
2076 | { | |
2077 | find_pc_partial_function (start, 0, NULL, &end_pc); | |
2078 | body_pc = min (end_pc, body_pc); | |
2079 | } | |
2080 | else | |
2081 | body_pc = min (pc, body_pc); | |
2082 | ||
2083 | if (call0 != NULL) | |
2084 | *call0 = 1; | |
2085 | ||
2086 | if (rt != NULL) | |
2087 | { | |
2088 | rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t)); | |
2089 | /* rt is already initialized in xtensa_alloc_frame_cache(). */ | |
2090 | } | |
2091 | else nregs = 0; | |
2092 | ||
2093 | isa = xtensa_default_isa; | |
2094 | gdb_assert (BSZ >= xtensa_isa_maxlength (isa)); | |
2095 | ins = xtensa_insnbuf_alloc (isa); | |
2096 | slot = xtensa_insnbuf_alloc (isa); | |
2097 | ||
2098 | for (ia = start, bt = ia; ia < body_pc ; ia += ilen) | |
2099 | { | |
2100 | /* (Re)fill instruction buffer from memory if necessary, but do not | |
2101 | read memory beyond PC to be sure we stay within text section | |
2102 | (this protection only works if a non-zero pc is supplied). */ | |
2103 | ||
2104 | if (ia + xtensa_isa_maxlength (isa) > bt) | |
2105 | { | |
2106 | ba = ia; | |
2107 | bt = (ba + BSZ) < body_pc ? ba + BSZ : body_pc; | |
2108 | read_memory (ba, ibuf, bt - ba); | |
2109 | } | |
2110 | ||
2111 | /* Decode format information. */ | |
2112 | ||
2113 | xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); | |
2114 | ifmt = xtensa_format_decode (isa, ins); | |
2115 | if (ifmt == XTENSA_UNDEFINED) | |
2116 | { | |
2117 | fail = 1; | |
2118 | goto done; | |
2119 | } | |
2120 | ilen = xtensa_format_length (isa, ifmt); | |
2121 | if (ilen == XTENSA_UNDEFINED) | |
2122 | { | |
2123 | fail = 1; | |
2124 | goto done; | |
2125 | } | |
2126 | islots = xtensa_format_num_slots (isa, ifmt); | |
2127 | if (islots == XTENSA_UNDEFINED) | |
2128 | { | |
2129 | fail = 1; | |
2130 | goto done; | |
2131 | } | |
2132 | ||
2133 | /* Analyze a bundle or a single instruction, using a snapshot of | |
2134 | the register tracking info as input for the entire bundle so that | |
2135 | register changes do not take effect within this bundle. */ | |
ca3bf3bd | 2136 | |
bdb4c075 MG |
2137 | for (j = 0; j < nregs; ++j) |
2138 | rtmp[j] = rt[j]; | |
2139 | ||
2140 | for (is = 0; is < islots; ++is) | |
2141 | { | |
2142 | /* Decode a slot and classify the opcode. */ | |
2143 | ||
2144 | fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot); | |
2145 | if (fail) | |
2146 | goto done; | |
2147 | ||
2148 | opc = xtensa_opcode_decode (isa, ifmt, is, slot); | |
2149 | DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n", | |
2150 | (unsigned)ia, opc); | |
2151 | if (opc == XTENSA_UNDEFINED) | |
2152 | opclass = c0opc_illegal; | |
2153 | else | |
2154 | opclass = call0_classify_opcode (isa, opc); | |
2155 | ||
2156 | /* Decide whether to track this opcode, ignore it, or bail out. */ | |
2157 | ||
2158 | switch (opclass) | |
2159 | { | |
2160 | case c0opc_illegal: | |
2161 | case c0opc_break: | |
2162 | fail = 1; | |
2163 | goto done; | |
2164 | ||
2165 | case c0opc_uninteresting: | |
2166 | continue; | |
2167 | ||
2168 | case c0opc_flow: | |
2169 | goto done; | |
2170 | ||
2171 | case c0opc_entry: | |
2172 | if (call0 != NULL) | |
2173 | *call0 = 0; | |
2174 | ia += ilen; /* Skip over 'entry' insn. */ | |
2175 | goto done; | |
2176 | ||
2177 | default: | |
2178 | if (call0 != NULL) | |
2179 | *call0 = 1; | |
2180 | } | |
2181 | ||
2182 | /* Only expected opcodes should get this far. */ | |
2183 | if (rt == NULL) | |
2184 | continue; | |
2185 | ||
2186 | /* Extract and decode the operands. */ | |
2187 | nods = xtensa_opcode_num_operands (isa, opc); | |
2188 | if (nods == XTENSA_UNDEFINED) | |
2189 | { | |
2190 | fail = 1; | |
2191 | goto done; | |
2192 | } | |
2193 | ||
2194 | for (j = 0; j < nods && j < C0_MAXOPDS; ++j) | |
2195 | { | |
2196 | fail = xtensa_operand_get_field (isa, opc, j, ifmt, | |
2197 | is, slot, &odv[j]); | |
2198 | if (fail) | |
2199 | goto done; | |
2200 | ||
2201 | fail = xtensa_operand_decode (isa, opc, j, &odv[j]); | |
2202 | if (fail) | |
2203 | goto done; | |
2204 | } | |
2205 | ||
2206 | /* Check operands to verify use of 'mov' assembler macro. */ | |
2207 | if (opclass == c0opc_mov && nods == 3) | |
2208 | { | |
2209 | if (odv[2] == odv[1]) | |
2210 | nods = 2; | |
2211 | else | |
2212 | { | |
2213 | opclass = c0opc_uninteresting; | |
2214 | continue; | |
2215 | } | |
2216 | } | |
2217 | ||
2218 | /* Track register movement and modification for this operation. */ | |
2219 | call0_track_op (rt, rtmp, opclass, nods, odv, ia, 1); | |
2220 | } | |
2221 | } | |
2222 | done: | |
2223 | DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n", | |
2224 | (unsigned)ia, fail ? "failed" : "succeeded"); | |
2225 | xtensa_insnbuf_free(isa, slot); | |
2226 | xtensa_insnbuf_free(isa, ins); | |
2227 | return fail ? 0 : ia; | |
2228 | } | |
2229 | ||
2230 | /* Initialize frame cache for the current frame. The "next_frame" is the next | |
2231 | one relative to current frame. "cache" is the pointer to the data structure | |
2232 | we have to initialize. "pc" is curretnt PC. */ | |
2233 | ||
2234 | static void | |
2235 | call0_frame_cache (struct frame_info *next_frame, | |
2236 | xtensa_frame_cache_t *cache, CORE_ADDR pc) | |
2237 | { | |
6b50c0b0 | 2238 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
bdb4c075 MG |
2239 | CORE_ADDR start_pc; /* The beginning of the function. */ |
2240 | CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */ | |
2241 | CORE_ADDR sp, fp, ra; | |
2242 | int fp_regnum, c0_hasfp, c0_frmsz, prev_sp, to_stk; | |
2243 | ||
2244 | /* Find the beginning of the prologue of the function containing the PC | |
2245 | and analyze it up to the PC or the end of the prologue. */ | |
2246 | ||
2247 | if (find_pc_partial_function (pc, NULL, &start_pc, NULL)) | |
2248 | { | |
2249 | body_pc = call0_analyze_prologue (start_pc, pc, C0_NREGS, | |
2250 | &cache->c0.c0_rt[0], | |
2251 | &cache->call0); | |
2252 | } | |
2253 | ||
304fe255 | 2254 | sp = frame_unwind_register_unsigned |
6b50c0b0 | 2255 | (next_frame, gdbarch_tdep (gdbarch)->a0_base + 1); |
bdb4c075 MG |
2256 | fp = sp; /* Assume FP == SP until proven otherwise. */ |
2257 | ||
2258 | /* Get the frame information and FP (if used) at the current PC. | |
2259 | If PC is in the prologue, the prologue analysis is more reliable | |
2260 | than DWARF info. We don't not know for sure if PC is in the prologue, | |
2261 | but we know no calls have yet taken place, so we can almost | |
2262 | certainly rely on the prologue analysis. */ | |
2263 | ||
2264 | if (body_pc <= pc) | |
2265 | { | |
2266 | /* Prologue analysis was successful up to the PC. | |
2267 | It includes the cases when PC == START_PC. */ | |
2268 | c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP; | |
2269 | /* c0_hasfp == true means there is a frame pointer because | |
2270 | we analyzed the prologue and found that cache->c0.c0_rt[C0_FP] | |
2271 | was derived from SP. Otherwise, it would be C0_FP. */ | |
2272 | fp_regnum = c0_hasfp ? C0_FP : C0_SP; | |
2273 | c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs; | |
6b50c0b0 | 2274 | fp_regnum += gdbarch_tdep (gdbarch)->a0_base; |
bdb4c075 MG |
2275 | } |
2276 | else /* No data from the prologue analysis. */ | |
2277 | { | |
2278 | c0_hasfp = 0; | |
6b50c0b0 | 2279 | fp_regnum = gdbarch_tdep (gdbarch)->a0_base + C0_SP; |
bdb4c075 MG |
2280 | c0_frmsz = 0; |
2281 | start_pc = pc; | |
2282 | } | |
2283 | ||
2284 | prev_sp = fp + c0_frmsz; | |
2285 | ||
2286 | /* Frame size from debug info or prologue tracking does not account for | |
2287 | alloca() and other dynamic allocations. Adjust frame size by FP - SP. */ | |
2288 | if (c0_hasfp) | |
2289 | { | |
2290 | fp = frame_unwind_register_unsigned (next_frame, fp_regnum); | |
2291 | ||
2292 | /* Recalculate previous SP. */ | |
2293 | prev_sp = fp + c0_frmsz; | |
2294 | /* Update the stack frame size. */ | |
2295 | c0_frmsz += fp - sp; | |
2296 | } | |
2297 | ||
2298 | /* Get the return address (RA) from the stack if saved, | |
2299 | or try to get it from a register. */ | |
2300 | ||
2301 | to_stk = cache->c0.c0_rt[C0_RA].to_stk; | |
2302 | if (to_stk != C0_NOSTK) | |
2303 | ra = (CORE_ADDR) | |
2304 | read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk, 4); | |
2305 | ||
2306 | else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST | |
2307 | && cache->c0.c0_rt[C0_RA].fr_ofs == 0) | |
2308 | { | |
2309 | /* Special case for terminating backtrace at a function that wants to | |
2310 | be seen as the outermost. Such a function will clear it's RA (A0) | |
2311 | register to 0 in the prologue instead of saving its original value. */ | |
2312 | ra = 0; | |
2313 | } | |
2314 | else | |
2315 | { | |
2316 | /* RA was copied to another register or (before any function call) may | |
2317 | still be in the original RA register. This is not always reliable: | |
2318 | even in a leaf function, register tracking stops after prologue, and | |
2319 | even in prologue, non-prologue instructions (not tracked) may overwrite | |
2320 | RA or any register it was copied to. If likely in prologue or before | |
2321 | any call, use retracking info and hope for the best (compiler should | |
2322 | have saved RA in stack if not in a leaf function). If not in prologue, | |
2323 | too bad. */ | |
2324 | ||
2325 | int i; | |
2326 | for (i = 0; | |
2327 | (i < C0_NREGS) && | |
2328 | (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA); | |
2329 | ++i); | |
2330 | if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA) | |
2331 | i = C0_RA; | |
2332 | if (i < C0_NREGS) /* Read from the next_frame. */ | |
2333 | { | |
304fe255 UW |
2334 | ra = frame_unwind_register_unsigned |
2335 | (next_frame, | |
6b50c0b0 | 2336 | gdbarch_tdep (gdbarch)->a0_base + 0 |
304fe255 | 2337 | + cache->c0.c0_rt[i].fr_reg); |
bdb4c075 MG |
2338 | } |
2339 | else ra = 0; | |
2340 | } | |
2341 | ||
2342 | cache->pc = start_pc; | |
2343 | cache->ra = ra; | |
2344 | /* RA == 0 marks the outermost frame. Do not go past it. */ | |
2345 | cache->prev_sp = (ra != 0) ? prev_sp : 0; | |
2346 | cache->c0.fp_regnum = fp_regnum; | |
2347 | cache->c0.c0_frmsz = c0_frmsz; | |
2348 | cache->c0.c0_hasfp = c0_hasfp; | |
2349 | cache->c0.c0_fp = fp; | |
2350 | } | |
2351 | ||
2352 | ||
2353 | /* Skip function prologue. | |
2354 | ||
2355 | Return the pc of the first instruction after prologue. GDB calls this to | |
2356 | find the address of the first line of the function or (if there is no line | |
2357 | number information) to skip the prologue for planting breakpoints on | |
2358 | function entries. Use debug info (if present) or prologue analysis to skip | |
2359 | the prologue to achieve reliable debugging behavior. For windowed ABI, | |
2360 | only the 'entry' instruction is skipped. It is not strictly necessary to | |
2361 | skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to | |
2362 | backtrace at any point in the prologue, however certain potential hazards | |
2363 | are avoided and a more "normal" debugging experience is ensured by | |
2364 | skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG). | |
2365 | For example, if we don't skip the prologue: | |
2366 | - Some args may not yet have been saved to the stack where the debug | |
2367 | info expects to find them (true anyway when only 'entry' is skipped); | |
2368 | - Software breakpoints ('break' instrs) may not have been unplanted | |
2369 | when the prologue analysis is done on initializing the frame cache, | |
2370 | and breaks in the prologue will throw off the analysis. | |
ca3bf3bd DJ |
2371 | |
2372 | If we have debug info ( line-number info, in particular ) we simply skip | |
2373 | the code associated with the first function line effectively skipping | |
bdb4c075 | 2374 | the prologue code. It works even in cases like |
ca3bf3bd DJ |
2375 | |
2376 | int main() | |
2377 | { int local_var = 1; | |
2378 | .... | |
2379 | } | |
2380 | ||
2381 | because, for this source code, both Xtensa compilers will generate two | |
2382 | separate entries ( with the same line number ) in dwarf line-number | |
2383 | section to make sure there is a boundary between the prologue code and | |
2384 | the rest of the function. | |
2385 | ||
bdb4c075 MG |
2386 | If there is no debug info, we need to analyze the code. */ |
2387 | ||
2388 | /* #define DONT_SKIP_PROLOGUE */ | |
ca3bf3bd DJ |
2389 | |
2390 | CORE_ADDR | |
2391 | xtensa_skip_prologue (CORE_ADDR start_pc) | |
2392 | { | |
bdb4c075 MG |
2393 | struct symtab_and_line prologue_sal; |
2394 | CORE_ADDR body_pc; | |
2395 | ||
ca3bf3bd DJ |
2396 | DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc); |
2397 | ||
bdb4c075 MG |
2398 | #if DONT_SKIP_PROLOGUE |
2399 | return start_pc; | |
2400 | #endif | |
2401 | ||
2402 | /* Try to find first body line from debug info. */ | |
2403 | ||
2404 | prologue_sal = find_pc_line (start_pc, 0); | |
2405 | if (prologue_sal.line != 0) /* Found debug info. */ | |
ca3bf3bd | 2406 | { |
bdb4c075 MG |
2407 | /* In Call0, it is possible to have a function with only one instruction |
2408 | ('ret') resulting from a 1-line optimized function that does nothing. | |
2409 | In that case, prologue_sal.end may actually point to the start of the | |
2410 | next function in the text section, causing a breakpoint to be set at | |
2411 | the wrong place. Check if the end address is in a different function, | |
2412 | and if so return the start PC. We know we have symbol info. */ | |
ca3bf3bd | 2413 | |
bdb4c075 MG |
2414 | CORE_ADDR end_func; |
2415 | ||
2416 | find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL); | |
2417 | if (end_func != start_pc) | |
ca3bf3bd DJ |
2418 | return start_pc; |
2419 | ||
bdb4c075 | 2420 | return prologue_sal.end; |
ca3bf3bd | 2421 | } |
ca3bf3bd | 2422 | |
bdb4c075 MG |
2423 | /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */ |
2424 | body_pc = call0_analyze_prologue(start_pc, 0, 0, NULL, NULL); | |
2425 | return body_pc != 0 ? body_pc : start_pc; | |
2426 | } | |
ca3bf3bd DJ |
2427 | |
2428 | /* Verify the current configuration. */ | |
ca3bf3bd DJ |
2429 | static void |
2430 | xtensa_verify_config (struct gdbarch *gdbarch) | |
2431 | { | |
2432 | struct ui_file *log; | |
2433 | struct cleanup *cleanups; | |
2434 | struct gdbarch_tdep *tdep; | |
2435 | long dummy; | |
2436 | char *buf; | |
2437 | ||
2438 | tdep = gdbarch_tdep (gdbarch); | |
2439 | log = mem_fileopen (); | |
2440 | cleanups = make_cleanup_ui_file_delete (log); | |
2441 | ||
2442 | /* Verify that we got a reasonable number of AREGS. */ | |
2443 | if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs) | |
bdb4c075 MG |
2444 | fprintf_unfiltered (log, _("\ |
2445 | \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"), | |
2446 | tdep->num_aregs); | |
ca3bf3bd DJ |
2447 | |
2448 | /* Verify that certain registers exist. */ | |
bdb4c075 | 2449 | |
ca3bf3bd | 2450 | if (tdep->pc_regnum == -1) |
bdb4c075 MG |
2451 | fprintf_unfiltered (log, _("\n\tpc_regnum: No PC register")); |
2452 | if (tdep->isa_use_exceptions && tdep->ps_regnum == -1) | |
2453 | fprintf_unfiltered (log, _("\n\tps_regnum: No PS register")); | |
2454 | ||
2455 | if (tdep->isa_use_windowed_registers) | |
2456 | { | |
2457 | if (tdep->wb_regnum == -1) | |
2458 | fprintf_unfiltered (log, _("\n\twb_regnum: No WB register")); | |
2459 | if (tdep->ws_regnum == -1) | |
2460 | fprintf_unfiltered (log, _("\n\tws_regnum: No WS register")); | |
2461 | if (tdep->ar_base == -1) | |
2462 | fprintf_unfiltered (log, _("\n\tar_base: No AR registers")); | |
2463 | } | |
2464 | ||
ca3bf3bd | 2465 | if (tdep->a0_base == -1) |
bdb4c075 | 2466 | fprintf_unfiltered (log, _("\n\ta0_base: No Ax registers")); |
ca3bf3bd DJ |
2467 | |
2468 | buf = ui_file_xstrdup (log, &dummy); | |
2469 | make_cleanup (xfree, buf); | |
2470 | if (strlen (buf) > 0) | |
2471 | internal_error (__FILE__, __LINE__, | |
2472 | _("the following are invalid: %s"), buf); | |
2473 | do_cleanups (cleanups); | |
2474 | } | |
2475 | ||
ca3bf3bd DJ |
2476 | /* Module "constructor" function. */ |
2477 | ||
2478 | static struct gdbarch * | |
2479 | xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2480 | { | |
2481 | struct gdbarch_tdep *tdep; | |
2482 | struct gdbarch *gdbarch; | |
2483 | struct xtensa_abi_handler *abi_handler; | |
2484 | ||
2485 | DEBUGTRACE ("gdbarch_init()\n"); | |
2486 | ||
2487 | /* We have to set the byte order before we call gdbarch_alloc. */ | |
2488 | info.byte_order = xtensa_config_byte_order (&info); | |
2489 | ||
2490 | tdep = xtensa_config_tdep (&info); | |
2491 | gdbarch = gdbarch_alloc (&info, tdep); | |
2492 | ||
2493 | /* Verify our configuration. */ | |
2494 | xtensa_verify_config (gdbarch); | |
2495 | ||
bdb4c075 | 2496 | /* Pseudo-Register read/write. */ |
ca3bf3bd DJ |
2497 | set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read); |
2498 | set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write); | |
2499 | ||
2500 | /* Set target information. */ | |
2501 | set_gdbarch_num_regs (gdbarch, tdep->num_regs); | |
2502 | set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs); | |
2503 | set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1); | |
2504 | set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum); | |
2505 | set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum); | |
2506 | ||
2507 | /* Renumber registers for known formats (stab, dwarf, and dwarf2). */ | |
2508 | set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); | |
2509 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); | |
2510 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); | |
2511 | ||
2512 | /* We provide our own function to get register information. */ | |
2513 | set_gdbarch_register_name (gdbarch, xtensa_register_name); | |
2514 | set_gdbarch_register_type (gdbarch, xtensa_register_type); | |
2515 | ||
2516 | /* To call functions from GDB using dummy frame */ | |
2517 | set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call); | |
2518 | ||
2519 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); | |
2520 | ||
2521 | set_gdbarch_return_value (gdbarch, xtensa_return_value); | |
2522 | ||
2523 | /* Advance PC across any prologue instructions to reach "real" code. */ | |
2524 | set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue); | |
2525 | ||
2526 | /* Stack grows downward. */ | |
2527 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2528 | ||
2529 | /* Set breakpoints. */ | |
2530 | set_gdbarch_breakpoint_from_pc (gdbarch, xtensa_breakpoint_from_pc); | |
2531 | ||
2532 | /* After breakpoint instruction or illegal instruction, pc still | |
2533 | points at break instruction, so don't decrement. */ | |
2534 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
2535 | ||
2536 | /* We don't skip args. */ | |
2537 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
2538 | ||
2539 | set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc); | |
2540 | ||
2541 | set_gdbarch_frame_align (gdbarch, xtensa_frame_align); | |
2542 | ||
2543 | set_gdbarch_unwind_dummy_id (gdbarch, xtensa_unwind_dummy_id); | |
2544 | ||
2545 | /* Frame handling. */ | |
2546 | frame_base_set_default (gdbarch, &xtensa_frame_base); | |
2547 | frame_unwind_append_sniffer (gdbarch, xtensa_frame_sniffer); | |
2548 | ||
2549 | set_gdbarch_print_insn (gdbarch, print_insn_xtensa); | |
2550 | ||
2551 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
2552 | ||
2553 | xtensa_add_reggroups (gdbarch); | |
2554 | set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p); | |
2555 | ||
2556 | set_gdbarch_regset_from_core_section (gdbarch, | |
2557 | xtensa_regset_from_core_section); | |
2558 | ||
2559 | return gdbarch; | |
2560 | } | |
2561 | ||
ca3bf3bd | 2562 | static void |
6b50c0b0 | 2563 | xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
ca3bf3bd DJ |
2564 | { |
2565 | error (_("xtensa_dump_tdep(): not implemented")); | |
2566 | } | |
2567 | ||
ca3bf3bd DJ |
2568 | void |
2569 | _initialize_xtensa_tdep (void) | |
2570 | { | |
2571 | struct cmd_list_element *c; | |
2572 | ||
2573 | gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep); | |
2574 | xtensa_init_reggroups (); | |
2575 | ||
2576 | add_setshow_zinteger_cmd ("xtensa", | |
2577 | class_maintenance, | |
2578 | &xtensa_debug_level, _("\ | |
2579 | Set Xtensa debugging."), _("\ | |
2580 | Show Xtensa debugging."), _("\ | |
2581 | When non-zero, Xtensa-specific debugging is enabled. \ | |
2582 | Can be 1, 2, 3, or 4 indicating the level of debugging."), | |
2583 | NULL, | |
2584 | NULL, | |
2585 | &setdebuglist, &showdebuglist); | |
2586 | } |