Commit | Line | Data |
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ca3bf3bd DJ |
1 | /* Target-dependent code for the Xtensa port of GDB, the GNU debugger. |
2 | ||
6aba47ca | 3 | Copyright (C) 2003, 2005, 2006, 2007 Free Software Foundation, Inc. |
ca3bf3bd DJ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
ca3bf3bd DJ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
ca3bf3bd DJ |
19 | |
20 | #include "defs.h" | |
21 | #include "frame.h" | |
22 | #include "symtab.h" | |
23 | #include "symfile.h" | |
24 | #include "objfiles.h" | |
25 | #include "gdbtypes.h" | |
26 | #include "gdbcore.h" | |
27 | #include "value.h" | |
28 | #include "dis-asm.h" | |
29 | #include "inferior.h" | |
30 | #include "floatformat.h" | |
31 | #include "regcache.h" | |
32 | #include "reggroups.h" | |
33 | #include "regset.h" | |
34 | ||
35 | #include "dummy-frame.h" | |
36 | #include "elf/dwarf2.h" | |
37 | #include "dwarf2-frame.h" | |
38 | #include "dwarf2loc.h" | |
39 | #include "frame.h" | |
40 | #include "frame-base.h" | |
41 | #include "frame-unwind.h" | |
42 | ||
43 | #include "arch-utils.h" | |
44 | #include "gdbarch.h" | |
45 | #include "remote.h" | |
46 | #include "serial.h" | |
47 | ||
48 | #include "command.h" | |
49 | #include "gdbcmd.h" | |
50 | #include "gdb_assert.h" | |
51 | ||
bdb4c075 | 52 | #include "xtensa-isa.h" |
ca3bf3bd DJ |
53 | #include "xtensa-tdep.h" |
54 | ||
55 | ||
56 | static int xtensa_debug_level = 0; | |
57 | ||
58 | #define DEBUGWARN(args...) \ | |
59 | if (xtensa_debug_level > 0) \ | |
60 | fprintf_unfiltered (gdb_stdlog, "(warn ) " args) | |
61 | ||
62 | #define DEBUGINFO(args...) \ | |
63 | if (xtensa_debug_level > 1) \ | |
64 | fprintf_unfiltered (gdb_stdlog, "(info ) " args) | |
65 | ||
66 | #define DEBUGTRACE(args...) \ | |
67 | if (xtensa_debug_level > 2) \ | |
68 | fprintf_unfiltered (gdb_stdlog, "(trace) " args) | |
69 | ||
70 | #define DEBUGVERB(args...) \ | |
71 | if (xtensa_debug_level > 3) \ | |
72 | fprintf_unfiltered (gdb_stdlog, "(verb ) " args) | |
73 | ||
74 | ||
75 | /* According to the ABI, the SP must be aligned to 16-byte boundaries. */ | |
ca3bf3bd DJ |
76 | #define SP_ALIGNMENT 16 |
77 | ||
78 | ||
bdb4c075 MG |
79 | /* On Windowed ABI, we use a6 through a11 for passing arguments |
80 | to a function called by GDB because CALL4 is used. */ | |
81 | #define ARGS_FIRST_REG A6_REGNUM | |
82 | #define ARGS_NUM_REGS 6 | |
83 | #define REGISTER_SIZE 4 | |
ca3bf3bd | 84 | |
ca3bf3bd | 85 | |
bdb4c075 MG |
86 | /* Extract the call size from the return address or PS register. */ |
87 | #define PS_CALLINC_SHIFT 16 | |
88 | #define PS_CALLINC_MASK 0x00030000 | |
89 | #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT) | |
90 | #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3)) | |
ca3bf3bd DJ |
91 | |
92 | ||
93 | /* Convert a live Ax register number to the corresponding Areg number. */ | |
ca3bf3bd | 94 | #define AREG_NUMBER(r, wb) \ |
bdb4c075 | 95 | ((((r) - A0_REGNUM + (((wb) & WB_MASK) << WB_SHIFT)) & AREGS_MASK) + AR_BASE) |
ca3bf3bd | 96 | |
bdb4c075 MG |
97 | /* ABI-independent macros. */ |
98 | #define ARG_NOF (CALL_ABI == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS)) | |
99 | #define ARG_1ST (CALL_ABI == CallAbiCall0Only \ | |
100 | ? (A0_REGNUM) + C0_ARGS : (ARGS_FIRST_REG)) | |
ca3bf3bd DJ |
101 | |
102 | extern struct gdbarch_tdep *xtensa_config_tdep (struct gdbarch_info *); | |
103 | extern int xtensa_config_byte_order (struct gdbarch_info *); | |
104 | ||
105 | ||
106 | /* XTENSA_IS_ENTRY tests whether the first byte of an instruction | |
107 | indicates that the instruction is an ENTRY instruction. */ | |
108 | ||
109 | #define XTENSA_IS_ENTRY(op1) \ | |
4c6b5505 UW |
110 | ((gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) \ |
111 | ? ((op1) == 0x6c) : ((op1) == 0x36)) | |
ca3bf3bd | 112 | |
bdb4c075 | 113 | #define XTENSA_ENTRY_LENGTH 3 |
ca3bf3bd DJ |
114 | |
115 | /* windowing_enabled() returns true, if windowing is enabled. | |
116 | WOE must be set to 1; EXCM to 0. | |
117 | Note: We assume that EXCM is always 0 for XEA1. */ | |
118 | ||
bdb4c075 MG |
119 | #define PS_WOE (1<<18) |
120 | #define PS_EXC (1<<4) | |
121 | ||
ca3bf3bd DJ |
122 | static inline int |
123 | windowing_enabled (CORE_ADDR ps) | |
124 | { | |
bdb4c075 | 125 | return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0); |
ca3bf3bd DJ |
126 | } |
127 | ||
128 | /* Return the window size of the previous call to the function from which we | |
129 | have just returned. | |
130 | ||
131 | This function is used to extract the return value after a called function | |
bdb4c075 | 132 | has returned to the caller. On Xtensa, the register that holds the return |
ca3bf3bd DJ |
133 | value (from the perspective of the caller) depends on what call |
134 | instruction was used. For now, we are assuming that the call instruction | |
135 | precedes the current address, so we simply analyze the call instruction. | |
136 | If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4' | |
137 | method to call the inferior function. */ | |
138 | ||
139 | static int | |
140 | extract_call_winsize (CORE_ADDR pc) | |
141 | { | |
bdb4c075 | 142 | int winsize = 4; |
ca3bf3bd | 143 | int insn; |
ff7a4c00 | 144 | gdb_byte buf[4]; |
ca3bf3bd DJ |
145 | |
146 | DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc); | |
147 | ||
148 | /* Read the previous instruction (should be a call[x]{4|8|12}. */ | |
149 | read_memory (pc-3, buf, 3); | |
150 | insn = extract_unsigned_integer (buf, 3); | |
151 | ||
152 | /* Decode call instruction: | |
153 | Little Endian | |
154 | call{0,4,8,12} OFFSET || {00,01,10,11} || 0101 | |
155 | callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000 | |
156 | Big Endian | |
157 | call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET | |
158 | callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */ | |
159 | ||
4c6b5505 | 160 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) |
ca3bf3bd DJ |
161 | { |
162 | if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0)) | |
bdb4c075 | 163 | winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */ |
ca3bf3bd DJ |
164 | } |
165 | else | |
166 | { | |
167 | if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03)) | |
bdb4c075 | 168 | winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */ |
ca3bf3bd DJ |
169 | } |
170 | return winsize; | |
171 | } | |
172 | ||
173 | ||
174 | /* REGISTER INFORMATION */ | |
175 | ||
176 | /* Returns the name of a register. */ | |
ca3bf3bd DJ |
177 | static const char * |
178 | xtensa_register_name (int regnum) | |
179 | { | |
180 | /* Return the name stored in the register map. */ | |
f57d151a UW |
181 | if (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch) |
182 | + gdbarch_num_pseudo_regs (current_gdbarch)) | |
ca3bf3bd DJ |
183 | return REGMAP[regnum].name; |
184 | ||
ca3bf3bd DJ |
185 | internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum); |
186 | return 0; | |
187 | } | |
188 | ||
bdb4c075 MG |
189 | static unsigned long |
190 | xtensa_read_register (int regnum) | |
191 | { | |
192 | ULONGEST value; | |
193 | ||
194 | regcache_raw_read_unsigned (get_current_regcache (), regnum, &value); | |
195 | return (unsigned long) value; | |
196 | } | |
ca3bf3bd DJ |
197 | |
198 | /* Return the type of a register. Create a new type, if necessary. */ | |
199 | ||
200 | static struct ctype_cache | |
201 | { | |
202 | struct ctype_cache *next; | |
203 | int size; | |
204 | struct type *virtual_type; | |
205 | } *type_entries = NULL; | |
206 | ||
207 | static struct type * | |
208 | xtensa_register_type (struct gdbarch *gdbarch, int regnum) | |
209 | { | |
210 | /* Return signed integer for ARx and Ax registers. */ | |
211 | if ((regnum >= AR_BASE && regnum < AR_BASE + NUM_AREGS) | |
212 | || (regnum >= A0_BASE && regnum < A0_BASE + 16)) | |
213 | return builtin_type_int; | |
214 | ||
3e8c568d | 215 | if (regnum == gdbarch_pc_regnum (current_gdbarch) || regnum == A1_REGNUM) |
ca3bf3bd DJ |
216 | return lookup_pointer_type (builtin_type_void); |
217 | ||
218 | /* Return the stored type for all other registers. */ | |
f57d151a UW |
219 | else if (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch) |
220 | + gdbarch_num_pseudo_regs (current_gdbarch)) | |
ca3bf3bd DJ |
221 | { |
222 | xtensa_register_t* reg = ®MAP[regnum]; | |
223 | ||
bdb4c075 | 224 | /* Set ctype for this register (only the first time). */ |
ca3bf3bd DJ |
225 | |
226 | if (reg->ctype == 0) | |
227 | { | |
228 | struct ctype_cache *tp; | |
229 | int size = reg->byte_size; | |
230 | ||
bdb4c075 MG |
231 | /* We always use the memory representation, |
232 | even if the register width is smaller. */ | |
ca3bf3bd DJ |
233 | switch (size) |
234 | { | |
235 | case 1: | |
236 | reg->ctype = builtin_type_uint8; | |
237 | break; | |
238 | ||
239 | case 2: | |
240 | reg->ctype = builtin_type_uint16; | |
241 | break; | |
242 | ||
243 | case 4: | |
244 | reg->ctype = builtin_type_uint32; | |
245 | break; | |
246 | ||
247 | case 8: | |
248 | reg->ctype = builtin_type_uint64; | |
249 | break; | |
250 | ||
251 | case 16: | |
252 | reg->ctype = builtin_type_uint128; | |
253 | break; | |
254 | ||
255 | default: | |
256 | for (tp = type_entries; tp != NULL; tp = tp->next) | |
257 | if (tp->size == size) | |
258 | break; | |
259 | ||
260 | if (tp == NULL) | |
261 | { | |
262 | char *name = xmalloc (16); | |
263 | tp = xmalloc (sizeof (struct ctype_cache)); | |
264 | tp->next = type_entries; | |
265 | type_entries = tp; | |
266 | tp->size = size; | |
267 | ||
268 | sprintf (name, "int%d", size * 8); | |
269 | tp->virtual_type = init_type (TYPE_CODE_INT, size, | |
270 | TYPE_FLAG_UNSIGNED, name, | |
271 | NULL); | |
272 | } | |
273 | ||
274 | reg->ctype = tp->virtual_type; | |
275 | } | |
276 | } | |
277 | return reg->ctype; | |
278 | } | |
279 | ||
ca3bf3bd DJ |
280 | internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum); |
281 | return 0; | |
282 | } | |
283 | ||
284 | ||
bdb4c075 | 285 | /* Return the 'local' register number for stubs, dwarf2, etc. |
ca3bf3bd DJ |
286 | The debugging information enumerates registers starting from 0 for A0 |
287 | to n for An. So, we only have to add the base number for A0. */ | |
288 | ||
289 | static int | |
290 | xtensa_reg_to_regnum (int regnum) | |
291 | { | |
292 | int i; | |
293 | ||
294 | if (regnum >= 0 && regnum < 16) | |
295 | return A0_BASE + regnum; | |
296 | ||
f57d151a UW |
297 | for (i = 0; |
298 | i < gdbarch_num_regs (current_gdbarch) | |
299 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
300 | i++) | |
ca3bf3bd DJ |
301 | if (regnum == REGMAP[i].target_number) |
302 | return i; | |
303 | ||
ca3bf3bd DJ |
304 | internal_error (__FILE__, __LINE__, |
305 | _("invalid dwarf/stabs register number %d"), regnum); | |
306 | return 0; | |
307 | } | |
308 | ||
309 | ||
bdb4c075 MG |
310 | /* Write the bits of a masked register to the various registers. |
311 | Only the masked areas of these registers are modified; the other | |
312 | fields are untouched. The size of masked registers is always less | |
313 | than or equal to 32 bits. */ | |
ca3bf3bd DJ |
314 | |
315 | static void | |
9c9acae0 UW |
316 | xtensa_register_write_masked (struct regcache *regcache, |
317 | xtensa_register_t *reg, const gdb_byte *buffer) | |
ca3bf3bd DJ |
318 | { |
319 | unsigned int value[(MAX_REGISTER_SIZE + 3) / 4]; | |
ca3bf3bd DJ |
320 | const xtensa_mask_t *mask = reg->mask; |
321 | ||
322 | int shift = 0; /* Shift for next mask (mod 32). */ | |
323 | int start, size; /* Start bit and size of current mask. */ | |
324 | ||
325 | unsigned int *ptr = value; | |
326 | unsigned int regval, m, mem = 0; | |
327 | ||
328 | int bytesize = reg->byte_size; | |
329 | int bitsize = bytesize * 8; | |
330 | int i, r; | |
331 | ||
332 | DEBUGTRACE ("xtensa_register_write_masked ()\n"); | |
333 | ||
334 | /* Copy the masked register to host byte-order. */ | |
4c6b5505 | 335 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
336 | for (i = 0; i < bytesize; i++) |
337 | { | |
338 | mem >>= 8; | |
339 | mem |= (buffer[bytesize - i - 1] << 24); | |
340 | if ((i & 3) == 3) | |
341 | *ptr++ = mem; | |
342 | } | |
343 | else | |
344 | for (i = 0; i < bytesize; i++) | |
345 | { | |
346 | mem >>= 8; | |
347 | mem |= (buffer[i] << 24); | |
348 | if ((i & 3) == 3) | |
349 | *ptr++ = mem; | |
350 | } | |
351 | ||
352 | /* We might have to shift the final value: | |
353 | bytesize & 3 == 0 -> nothing to do, we use the full 32 bits, | |
354 | bytesize & 3 == x -> shift (4-x) * 8. */ | |
355 | ||
356 | *ptr = mem >> (((0 - bytesize) & 3) * 8); | |
357 | ptr = value; | |
358 | mem = *ptr; | |
359 | ||
360 | /* Write the bits to the masked areas of the other registers. */ | |
361 | for (i = 0; i < mask->count; i++) | |
362 | { | |
363 | start = mask->mask[i].bit_start; | |
364 | size = mask->mask[i].bit_size; | |
365 | regval = mem >> shift; | |
366 | ||
367 | if ((shift += size) > bitsize) | |
368 | error (_("size of all masks is larger than the register")); | |
369 | ||
370 | if (shift >= 32) | |
371 | { | |
372 | mem = *(++ptr); | |
373 | shift -= 32; | |
374 | bitsize -= 32; | |
375 | ||
376 | if (shift > 0) | |
377 | regval |= mem << (size - shift); | |
378 | } | |
379 | ||
380 | /* Make sure we have a valid register. */ | |
381 | r = mask->mask[i].reg_num; | |
382 | if (r >= 0 && size > 0) | |
383 | { | |
384 | /* Don't overwrite the unmasked areas. */ | |
9c9acae0 UW |
385 | ULONGEST old_val; |
386 | regcache_cooked_read_unsigned (regcache, r, &old_val); | |
ca3bf3bd DJ |
387 | m = 0xffffffff >> (32 - size) << start; |
388 | regval <<= start; | |
9c9acae0 UW |
389 | regval = (regval & m) | (old_val & ~m); |
390 | regcache_cooked_write_unsigned (regcache, r, regval); | |
ca3bf3bd DJ |
391 | } |
392 | } | |
393 | } | |
394 | ||
395 | ||
bdb4c075 MG |
396 | /* Read a tie state or mapped registers. Read the masked areas |
397 | of the registers and assemble them into a single value. */ | |
ca3bf3bd DJ |
398 | |
399 | static void | |
9c9acae0 UW |
400 | xtensa_register_read_masked (struct regcache *regcache, |
401 | xtensa_register_t *reg, gdb_byte *buffer) | |
ca3bf3bd DJ |
402 | { |
403 | unsigned int value[(MAX_REGISTER_SIZE + 3) / 4]; | |
ca3bf3bd DJ |
404 | const xtensa_mask_t *mask = reg->mask; |
405 | ||
406 | int shift = 0; | |
407 | int start, size; | |
408 | ||
409 | unsigned int *ptr = value; | |
410 | unsigned int regval, mem = 0; | |
411 | ||
412 | int bytesize = reg->byte_size; | |
413 | int bitsize = bytesize * 8; | |
414 | int i; | |
415 | ||
416 | DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n", | |
417 | reg->name == 0 ? "" : reg->name); | |
418 | ||
419 | /* Assemble the register from the masked areas of other registers. */ | |
420 | for (i = 0; i < mask->count; i++) | |
421 | { | |
422 | int r = mask->mask[i].reg_num; | |
9c9acae0 UW |
423 | if (r >= 0) |
424 | { | |
425 | ULONGEST val; | |
426 | regcache_cooked_read_unsigned (regcache, r, &val); | |
427 | regval = (unsigned int) val; | |
428 | } | |
429 | else | |
430 | regval = 0; | |
431 | ||
ca3bf3bd DJ |
432 | start = mask->mask[i].bit_start; |
433 | size = mask->mask[i].bit_size; | |
434 | ||
435 | regval >>= start; | |
436 | ||
437 | if (size < 32) | |
438 | regval &= (0xffffffff >> (32 - size)); | |
439 | ||
440 | mem |= regval << shift; | |
441 | ||
442 | if ((shift += size) > bitsize) | |
443 | error (_("size of all masks is larger than the register")); | |
444 | ||
445 | if (shift >= 32) | |
446 | { | |
447 | *ptr++ = mem; | |
448 | bitsize -= 32; | |
449 | shift -= 32; | |
450 | ||
451 | if (shift == 0) | |
452 | mem = 0; | |
453 | else | |
454 | mem = regval >> (size - shift); | |
455 | } | |
456 | } | |
457 | ||
458 | if (shift > 0) | |
459 | *ptr = mem; | |
460 | ||
461 | /* Copy value to target byte order. */ | |
462 | ptr = value; | |
463 | mem = *ptr; | |
464 | ||
4c6b5505 | 465 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
466 | for (i = 0; i < bytesize; i++) |
467 | { | |
468 | if ((i & 3) == 0) | |
469 | mem = *ptr++; | |
470 | buffer[bytesize - i - 1] = mem & 0xff; | |
471 | mem >>= 8; | |
472 | } | |
473 | else | |
474 | for (i = 0; i < bytesize; i++) | |
475 | { | |
476 | if ((i & 3) == 0) | |
477 | mem = *ptr++; | |
478 | buffer[i] = mem & 0xff; | |
479 | mem >>= 8; | |
480 | } | |
481 | } | |
482 | ||
483 | ||
484 | /* Read pseudo registers. */ | |
485 | ||
486 | static void | |
487 | xtensa_pseudo_register_read (struct gdbarch *gdbarch, | |
488 | struct regcache *regcache, | |
489 | int regnum, | |
490 | gdb_byte *buffer) | |
491 | { | |
492 | DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n", | |
493 | regnum, xtensa_register_name (regnum)); | |
494 | ||
ca3bf3bd | 495 | if (regnum == FP_ALIAS) |
bdb4c075 | 496 | regnum = A1_REGNUM; |
ca3bf3bd | 497 | |
bdb4c075 MG |
498 | /* Read aliases a0..a15, if this is a Windowed ABI. */ |
499 | if (ISA_USE_WINDOWED_REGISTERS | |
500 | && (regnum >= A0_REGNUM) && (regnum <= A15_REGNUM)) | |
ca3bf3bd | 501 | { |
ff7a4c00 | 502 | gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE); |
ca3bf3bd DJ |
503 | |
504 | regcache_raw_read (regcache, WB_REGNUM, buf); | |
505 | regnum = AREG_NUMBER (regnum, extract_unsigned_integer (buf, 4)); | |
506 | } | |
507 | ||
bdb4c075 | 508 | /* We can always read non-pseudo registers. */ |
f57d151a | 509 | if (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch)) |
ca3bf3bd DJ |
510 | regcache_raw_read (regcache, regnum, buffer); |
511 | ||
512 | /* Pseudo registers. */ | |
f57d151a UW |
513 | else if (regnum >= 0 |
514 | && regnum < gdbarch_num_regs (current_gdbarch) | |
515 | + gdbarch_num_pseudo_regs (current_gdbarch)) | |
ca3bf3bd DJ |
516 | { |
517 | xtensa_register_t *reg = ®MAP[regnum]; | |
518 | xtensa_register_type_t type = reg->type; | |
519 | int flags = XTENSA_TARGET_FLAGS; | |
520 | ||
bdb4c075 | 521 | /* We cannot read Unknown or Unmapped registers. */ |
ca3bf3bd DJ |
522 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) |
523 | { | |
524 | if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
525 | { | |
526 | warning (_("cannot read register %s"), | |
527 | xtensa_register_name (regnum)); | |
528 | return; | |
529 | } | |
530 | } | |
531 | ||
532 | /* Some targets cannot read TIE register files. */ | |
533 | else if (type == xtRegisterTypeTieRegfile) | |
534 | { | |
535 | /* Use 'fetch' to get register? */ | |
536 | if (flags & xtTargetFlagsUseFetchStore) | |
537 | { | |
538 | warning (_("cannot read register")); | |
539 | return; | |
540 | } | |
541 | ||
542 | /* On some targets (esp. simulators), we can always read the reg. */ | |
543 | else if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
544 | { | |
545 | warning (_("cannot read register")); | |
546 | return; | |
547 | } | |
548 | } | |
549 | ||
550 | /* We can always read mapped registers. */ | |
551 | else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState) | |
552 | { | |
9c9acae0 | 553 | xtensa_register_read_masked (regcache, reg, buffer); |
ca3bf3bd DJ |
554 | return; |
555 | } | |
556 | ||
557 | /* Assume that we can read the register. */ | |
558 | regcache_raw_read (regcache, regnum, buffer); | |
559 | } | |
ca3bf3bd DJ |
560 | else |
561 | internal_error (__FILE__, __LINE__, | |
562 | _("invalid register number %d"), regnum); | |
563 | } | |
564 | ||
565 | ||
566 | /* Write pseudo registers. */ | |
567 | ||
568 | static void | |
569 | xtensa_pseudo_register_write (struct gdbarch *gdbarch, | |
570 | struct regcache *regcache, | |
571 | int regnum, | |
572 | const gdb_byte *buffer) | |
573 | { | |
574 | DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n", | |
575 | regnum, xtensa_register_name (regnum)); | |
576 | ||
ca3bf3bd | 577 | if (regnum == FP_ALIAS) |
bdb4c075 | 578 | regnum = A1_REGNUM; |
ca3bf3bd | 579 | |
bdb4c075 MG |
580 | /* Renumber register, if aliase a0..a15 on Windowed ABI. */ |
581 | if (ISA_USE_WINDOWED_REGISTERS | |
582 | && (regnum >= A0_REGNUM) && (regnum <= A15_REGNUM)) | |
ca3bf3bd | 583 | { |
ff7a4c00 | 584 | gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE); |
ca3bf3bd DJ |
585 | unsigned int wb; |
586 | ||
587 | regcache_raw_read (regcache, WB_REGNUM, buf); | |
588 | regnum = AREG_NUMBER (regnum, extract_unsigned_integer (buf, 4)); | |
589 | } | |
590 | ||
591 | /* We can always write 'core' registers. | |
592 | Note: We might have converted Ax->ARy. */ | |
f57d151a | 593 | if (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch)) |
ca3bf3bd DJ |
594 | regcache_raw_write (regcache, regnum, buffer); |
595 | ||
596 | /* Pseudo registers. */ | |
f57d151a UW |
597 | else if (regnum >= 0 |
598 | && regnum < gdbarch_num_regs (current_gdbarch) | |
599 | + gdbarch_num_pseudo_regs (current_gdbarch)) | |
ca3bf3bd DJ |
600 | { |
601 | xtensa_register_t *reg = ®MAP[regnum]; | |
602 | xtensa_register_type_t type = reg->type; | |
603 | int flags = XTENSA_TARGET_FLAGS; | |
604 | ||
bdb4c075 MG |
605 | /* On most targets, we cannot write registers |
606 | of type "Unknown" or "Unmapped". */ | |
ca3bf3bd DJ |
607 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) |
608 | { | |
609 | if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
610 | { | |
611 | warning (_("cannot write register %s"), | |
612 | xtensa_register_name (regnum)); | |
613 | return; | |
614 | } | |
615 | } | |
616 | ||
617 | /* Some targets cannot read TIE register files. */ | |
618 | else if (type == xtRegisterTypeTieRegfile) | |
619 | { | |
620 | /* Use 'store' to get register? */ | |
621 | if (flags & xtTargetFlagsUseFetchStore) | |
622 | { | |
623 | warning (_("cannot write register")); | |
624 | return; | |
625 | } | |
626 | ||
627 | /* On some targets (esp. simulators), we can always write | |
628 | the register. */ | |
ca3bf3bd DJ |
629 | else if ((flags & xtTargetFlagsNonVisibleRegs) == 0) |
630 | { | |
631 | warning (_("cannot write register")); | |
632 | return; | |
633 | } | |
634 | } | |
635 | ||
636 | /* We can always write mapped registers. */ | |
637 | else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState) | |
638 | { | |
9c9acae0 | 639 | xtensa_register_write_masked (regcache, reg, buffer); |
ca3bf3bd DJ |
640 | return; |
641 | } | |
642 | ||
643 | /* Assume that we can write the register. */ | |
644 | regcache_raw_write (regcache, regnum, buffer); | |
645 | } | |
ca3bf3bd DJ |
646 | else |
647 | internal_error (__FILE__, __LINE__, | |
648 | _("invalid register number %d"), regnum); | |
649 | } | |
650 | ||
ca3bf3bd DJ |
651 | static struct reggroup *xtensa_ar_reggroup; |
652 | static struct reggroup *xtensa_user_reggroup; | |
653 | static struct reggroup *xtensa_vectra_reggroup; | |
7b871568 | 654 | static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR]; |
ca3bf3bd DJ |
655 | |
656 | static void | |
657 | xtensa_init_reggroups (void) | |
658 | { | |
659 | xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP); | |
660 | xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP); | |
661 | xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP); | |
ca3bf3bd | 662 | |
7b871568 MG |
663 | xtensa_cp[0] = reggroup_new ("cp0", USER_REGGROUP); |
664 | xtensa_cp[1] = reggroup_new ("cp1", USER_REGGROUP); | |
665 | xtensa_cp[2] = reggroup_new ("cp2", USER_REGGROUP); | |
666 | xtensa_cp[3] = reggroup_new ("cp3", USER_REGGROUP); | |
667 | xtensa_cp[4] = reggroup_new ("cp4", USER_REGGROUP); | |
668 | xtensa_cp[5] = reggroup_new ("cp5", USER_REGGROUP); | |
669 | xtensa_cp[6] = reggroup_new ("cp6", USER_REGGROUP); | |
670 | xtensa_cp[7] = reggroup_new ("cp7", USER_REGGROUP); | |
671 | } | |
ca3bf3bd DJ |
672 | |
673 | static void | |
674 | xtensa_add_reggroups (struct gdbarch *gdbarch) | |
675 | { | |
7b871568 MG |
676 | int i; |
677 | ||
678 | /* Predefined groups. */ | |
ca3bf3bd DJ |
679 | reggroup_add (gdbarch, all_reggroup); |
680 | reggroup_add (gdbarch, save_reggroup); | |
681 | reggroup_add (gdbarch, restore_reggroup); | |
682 | reggroup_add (gdbarch, system_reggroup); | |
7b871568 MG |
683 | reggroup_add (gdbarch, vector_reggroup); |
684 | reggroup_add (gdbarch, general_reggroup); | |
685 | reggroup_add (gdbarch, float_reggroup); | |
686 | ||
687 | /* Xtensa-specific groups. */ | |
688 | reggroup_add (gdbarch, xtensa_ar_reggroup); | |
689 | reggroup_add (gdbarch, xtensa_user_reggroup); | |
690 | reggroup_add (gdbarch, xtensa_vectra_reggroup); | |
ca3bf3bd | 691 | |
7b871568 MG |
692 | for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++) |
693 | reggroup_add (gdbarch, xtensa_cp[i]); | |
ca3bf3bd DJ |
694 | } |
695 | ||
7b871568 MG |
696 | static int |
697 | xtensa_coprocessor_register_group (struct reggroup *group) | |
698 | { | |
699 | int i; | |
700 | ||
701 | for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++) | |
702 | if (group == xtensa_cp[i]) | |
703 | return i; | |
704 | ||
705 | return -1; | |
706 | } | |
ca3bf3bd DJ |
707 | |
708 | #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \ | |
709 | | XTENSA_REGISTER_FLAGS_WRITABLE \ | |
710 | | XTENSA_REGISTER_FLAGS_VOLATILE) | |
711 | ||
712 | #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \ | |
713 | | XTENSA_REGISTER_FLAGS_WRITABLE) | |
714 | ||
715 | static int | |
716 | xtensa_register_reggroup_p (struct gdbarch *gdbarch, | |
717 | int regnum, | |
718 | struct reggroup *group) | |
719 | { | |
720 | xtensa_register_t* reg = ®MAP[regnum]; | |
721 | xtensa_register_type_t type = reg->type; | |
722 | xtensa_register_group_t rg = reg->group; | |
7b871568 | 723 | int cp_number; |
ca3bf3bd DJ |
724 | |
725 | /* First, skip registers that are not visible to this target | |
726 | (unknown and unmapped registers when not using ISS). */ | |
727 | ||
728 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) | |
729 | return 0; | |
730 | if (group == all_reggroup) | |
731 | return 1; | |
732 | if (group == xtensa_ar_reggroup) | |
733 | return rg & xtRegisterGroupAddrReg; | |
734 | if (group == xtensa_user_reggroup) | |
735 | return rg & xtRegisterGroupUser; | |
736 | if (group == float_reggroup) | |
737 | return rg & xtRegisterGroupFloat; | |
738 | if (group == general_reggroup) | |
739 | return rg & xtRegisterGroupGeneral; | |
740 | if (group == float_reggroup) | |
741 | return rg & xtRegisterGroupFloat; | |
742 | if (group == system_reggroup) | |
743 | return rg & xtRegisterGroupState; | |
744 | if (group == vector_reggroup || group == xtensa_vectra_reggroup) | |
745 | return rg & xtRegisterGroupVectra; | |
746 | if (group == save_reggroup || group == restore_reggroup) | |
f57d151a | 747 | return (regnum < gdbarch_num_regs (current_gdbarch) |
ca3bf3bd | 748 | && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID); |
7b871568 MG |
749 | if ((cp_number = xtensa_coprocessor_register_group (group)) >= 0) |
750 | return rg & (xtRegisterGroupCP0 << cp_number); | |
ca3bf3bd DJ |
751 | else |
752 | return 1; | |
753 | } | |
754 | ||
755 | ||
ca3bf3bd DJ |
756 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
757 | in the general-purpose register set REGSET to register cache | |
bdb4c075 | 758 | REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */ |
ca3bf3bd DJ |
759 | |
760 | static void | |
761 | xtensa_supply_gregset (const struct regset *regset, | |
762 | struct regcache *rc, | |
763 | int regnum, | |
764 | const void *gregs, | |
765 | size_t len) | |
766 | { | |
767 | const xtensa_elf_gregset_t *regs = gregs; | |
768 | int i; | |
769 | ||
770 | DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...) \n", regnum); | |
771 | ||
3e8c568d UW |
772 | if (regnum == gdbarch_pc_regnum (current_gdbarch) || regnum == -1) |
773 | regcache_raw_supply (rc, | |
774 | gdbarch_pc_regnum (current_gdbarch), | |
775 | (char *) ®s->pc); | |
776 | if (regnum == gdbarch_ps_regnum (current_gdbarch) || regnum == -1) | |
777 | regcache_raw_supply (rc, gdbarch_ps_regnum (current_gdbarch), | |
778 | (char *) ®s->ps); | |
ca3bf3bd DJ |
779 | if (regnum == WB_REGNUM || regnum == -1) |
780 | regcache_raw_supply (rc, WB_REGNUM, (char *) ®s->windowbase); | |
781 | if (regnum == WS_REGNUM || regnum == -1) | |
782 | regcache_raw_supply (rc, WS_REGNUM, (char *) ®s->windowstart); | |
783 | if (regnum == LBEG_REGNUM || regnum == -1) | |
784 | regcache_raw_supply (rc, LBEG_REGNUM, (char *) ®s->lbeg); | |
785 | if (regnum == LEND_REGNUM || regnum == -1) | |
786 | regcache_raw_supply (rc, LEND_REGNUM, (char *) ®s->lend); | |
787 | if (regnum == LCOUNT_REGNUM || regnum == -1) | |
788 | regcache_raw_supply (rc, LCOUNT_REGNUM, (char *) ®s->lcount); | |
789 | if (regnum == SAR_REGNUM || regnum == -1) | |
790 | regcache_raw_supply (rc, SAR_REGNUM, (char *) ®s->sar); | |
791 | if (regnum == EXCCAUSE_REGNUM || regnum == -1) | |
792 | regcache_raw_supply (rc, EXCCAUSE_REGNUM, (char *) ®s->exccause); | |
793 | if (regnum == EXCVADDR_REGNUM || regnum == -1) | |
794 | regcache_raw_supply (rc, EXCVADDR_REGNUM, (char *) ®s->excvaddr); | |
795 | if (regnum >= AR_BASE && regnum < AR_BASE + NUM_AREGS) | |
796 | regcache_raw_supply (rc, regnum, (char *) ®s->ar[regnum - AR_BASE]); | |
797 | else if (regnum == -1) | |
798 | { | |
799 | for (i = 0; i < NUM_AREGS; ++i) | |
800 | regcache_raw_supply (rc, AR_BASE + i, (char *) ®s->ar[i]); | |
801 | } | |
802 | } | |
803 | ||
804 | ||
805 | /* Xtensa register set. */ | |
806 | ||
807 | static struct regset | |
808 | xtensa_gregset = | |
809 | { | |
810 | NULL, | |
811 | xtensa_supply_gregset | |
812 | }; | |
813 | ||
814 | ||
bdb4c075 MG |
815 | /* Return the appropriate register set for the core |
816 | section identified by SECT_NAME and SECT_SIZE. */ | |
ca3bf3bd DJ |
817 | |
818 | static const struct regset * | |
819 | xtensa_regset_from_core_section (struct gdbarch *core_arch, | |
820 | const char *sect_name, | |
821 | size_t sect_size) | |
822 | { | |
823 | DEBUGTRACE ("xtensa_regset_from_core_section " | |
824 | "(..., sect_name==\"%s\", sect_size==%x) \n", | |
bdb4c075 | 825 | sect_name, sect_size); |
ca3bf3bd DJ |
826 | |
827 | if (strcmp (sect_name, ".reg") == 0 | |
828 | && sect_size >= sizeof(xtensa_elf_gregset_t)) | |
829 | return &xtensa_gregset; | |
830 | ||
831 | return NULL; | |
832 | } | |
833 | ||
834 | ||
bdb4c075 | 835 | /* Handling frames. */ |
ca3bf3bd | 836 | |
bdb4c075 MG |
837 | /* Number of registers to save in case of Windowed ABI. */ |
838 | #define XTENSA_NUM_SAVED_AREGS 12 | |
ca3bf3bd | 839 | |
bdb4c075 MG |
840 | /* Frame cache part for Windowed ABI. */ |
841 | typedef struct xtensa_windowed_frame_cache | |
ca3bf3bd | 842 | { |
ca3bf3bd DJ |
843 | int wb; /* Base for this frame; -1 if not in regfile. */ |
844 | int callsize; /* Call size to next frame. */ | |
845 | int ws; | |
846 | CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS]; | |
bdb4c075 MG |
847 | } xtensa_windowed_frame_cache_t; |
848 | ||
849 | /* Call0 ABI Definitions. */ | |
850 | ||
851 | #define C0_MAXOPDS 3 /* Maximum number of operands for prologue analysis. */ | |
852 | #define C0_NREGS 16 /* Number of A-registers to track. */ | |
853 | #define C0_CLESV 12 /* Callee-saved registers are here and up. */ | |
854 | #define C0_SP 1 /* Register used as SP. */ | |
855 | #define C0_FP 15 /* Register used as FP. */ | |
856 | #define C0_RA 0 /* Register used as return address. */ | |
857 | #define C0_ARGS 2 /* Register used as first arg/retval. */ | |
858 | #define C0_NARGS 6 /* Number of A-regs for args/retvals. */ | |
859 | ||
860 | /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each | |
861 | A-register where the current content of the reg came from (in terms | |
862 | of an original reg and a constant). Negative values of c0_rt[n].fp_reg | |
863 | mean that the orignal content of the register was saved to the stack. | |
864 | c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't | |
865 | know where SP will end up until the entire prologue has been analyzed. */ | |
866 | ||
867 | #define C0_CONST -1 /* fr_reg value if register contains a constant. */ | |
868 | #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */ | |
869 | #define C0_NOSTK -1 /* to_stk value if register has not been stored. */ | |
870 | ||
871 | extern xtensa_isa xtensa_default_isa; | |
872 | ||
873 | typedef struct xtensa_c0reg | |
874 | { | |
875 | int fr_reg; /* original register from which register content | |
876 | is derived, or C0_CONST, or C0_INEXP. */ | |
877 | int fr_ofs; /* constant offset from reg, or immediate value. */ | |
878 | int to_stk; /* offset from original SP to register (4-byte aligned), | |
879 | or C0_NOSTK if register has not been saved. */ | |
880 | } xtensa_c0reg_t; | |
881 | ||
882 | ||
883 | /* Frame cache part for Call0 ABI. */ | |
884 | typedef struct xtensa_call0_frame_cache | |
885 | { | |
886 | int c0_frmsz; /* Stack frame size. */ | |
887 | int c0_hasfp; /* Current frame uses frame pointer. */ | |
888 | int fp_regnum; /* A-register used as FP. */ | |
889 | int c0_fp; /* Actual value of frame pointer. */ | |
890 | xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */ | |
891 | } xtensa_call0_frame_cache_t; | |
892 | ||
893 | typedef struct xtensa_frame_cache | |
894 | { | |
895 | CORE_ADDR base; /* Stack pointer of the next frame. */ | |
896 | CORE_ADDR pc; /* PC at the entry point to the function. */ | |
897 | CORE_ADDR ra; /* The raw return address. */ | |
898 | CORE_ADDR ps; /* The PS register of the frame. */ | |
899 | CORE_ADDR prev_sp; /* Stack Pointer of the frame. */ | |
900 | int call0; /* It's a call0 framework (else windowed). */ | |
901 | union | |
902 | { | |
903 | xtensa_windowed_frame_cache_t wd; /* call0 == false. */ | |
904 | xtensa_call0_frame_cache_t c0; /* call0 == true. */ | |
905 | }; | |
ca3bf3bd DJ |
906 | } xtensa_frame_cache_t; |
907 | ||
908 | ||
909 | static struct xtensa_frame_cache * | |
bdb4c075 | 910 | xtensa_alloc_frame_cache (int windowed) |
ca3bf3bd DJ |
911 | { |
912 | xtensa_frame_cache_t *cache; | |
913 | int i; | |
914 | ||
915 | DEBUGTRACE ("xtensa_alloc_frame_cache ()\n"); | |
916 | ||
917 | cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t); | |
918 | ||
919 | cache->base = 0; | |
920 | cache->pc = 0; | |
921 | cache->ra = 0; | |
ca3bf3bd | 922 | cache->ps = 0; |
ca3bf3bd | 923 | cache->prev_sp = 0; |
bdb4c075 MG |
924 | cache->call0 = !windowed; |
925 | if (cache->call0) | |
926 | { | |
927 | cache->c0.c0_frmsz = -1; | |
928 | cache->c0.c0_hasfp = 0; | |
929 | cache->c0.fp_regnum = -1; | |
930 | cache->c0.c0_fp = -1; | |
ca3bf3bd | 931 | |
bdb4c075 MG |
932 | for (i = 0; i < C0_NREGS; i++) |
933 | { | |
934 | cache->c0.c0_rt[i].fr_reg = i; | |
935 | cache->c0.c0_rt[i].fr_ofs = 0; | |
936 | cache->c0.c0_rt[i].to_stk = C0_NOSTK; | |
937 | } | |
938 | } | |
939 | else | |
940 | { | |
941 | cache->wd.wb = 0; | |
942 | cache->wd.callsize = -1; | |
ca3bf3bd | 943 | |
bdb4c075 MG |
944 | for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++) |
945 | cache->wd.aregs[i] = -1; | |
946 | } | |
ca3bf3bd DJ |
947 | return cache; |
948 | } | |
949 | ||
950 | ||
951 | static CORE_ADDR | |
952 | xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) | |
953 | { | |
954 | return address & ~15; | |
955 | } | |
956 | ||
957 | ||
958 | static CORE_ADDR | |
959 | xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
960 | { | |
ff7a4c00 | 961 | gdb_byte buf[8]; |
ca3bf3bd DJ |
962 | |
963 | DEBUGTRACE ("xtensa_unwind_pc (next_frame = %p)\n", next_frame); | |
964 | ||
3e8c568d | 965 | frame_unwind_register (next_frame, gdbarch_pc_regnum (current_gdbarch), buf); |
ca3bf3bd DJ |
966 | |
967 | DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) | |
968 | extract_typed_address (buf, builtin_type_void_func_ptr)); | |
969 | ||
970 | return extract_typed_address (buf, builtin_type_void_func_ptr); | |
971 | } | |
972 | ||
973 | ||
974 | static struct frame_id | |
975 | xtensa_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
976 | { | |
977 | CORE_ADDR pc, fp; | |
ca3bf3bd | 978 | |
bdb4c075 | 979 | /* next_frame->prev is a dummy frame. Return a frame ID of that frame. */ |
ca3bf3bd DJ |
980 | |
981 | DEBUGTRACE ("xtensa_unwind_dummy_id ()\n"); | |
982 | ||
983 | pc = frame_pc_unwind (next_frame); | |
bdb4c075 | 984 | fp = frame_unwind_register_unsigned (next_frame, A1_REGNUM); |
ca3bf3bd DJ |
985 | |
986 | /* Make dummy frame ID unique by adding a constant. */ | |
bdb4c075 | 987 | return frame_id_build (fp + SP_ALIGNMENT, pc); |
ca3bf3bd DJ |
988 | } |
989 | ||
bdb4c075 MG |
990 | /* The key values to identify the frame using "cache" are |
991 | ||
992 | cache->base = SP of this frame; | |
993 | cache->pc = entry-PC (entry point of the frame function); | |
994 | cache->prev_sp = SP of the previous frame. | |
995 | */ | |
996 | ||
997 | static void | |
998 | call0_frame_cache (struct frame_info *next_frame, | |
999 | xtensa_frame_cache_t *cache, | |
1000 | CORE_ADDR pc); | |
ca3bf3bd DJ |
1001 | |
1002 | static struct xtensa_frame_cache * | |
1003 | xtensa_frame_cache (struct frame_info *next_frame, void **this_cache) | |
1004 | { | |
1005 | xtensa_frame_cache_t *cache; | |
ca3bf3bd | 1006 | CORE_ADDR ra, wb, ws, pc, sp, ps; |
bdb4c075 | 1007 | unsigned int ps_regnum = gdbarch_ps_regnum (current_gdbarch); |
ca3bf3bd | 1008 | char op1; |
bdb4c075 | 1009 | int windowed; |
ca3bf3bd DJ |
1010 | |
1011 | DEBUGTRACE ("xtensa_frame_cache (next_frame %p, *this_cache %p)\n", | |
1012 | next_frame, this_cache ? *this_cache : (void*)0xdeadbeef); | |
1013 | ||
ca3bf3bd DJ |
1014 | if (*this_cache) |
1015 | return *this_cache; | |
1016 | ||
bdb4c075 MG |
1017 | windowed = windowing_enabled (xtensa_read_register (ps_regnum)); |
1018 | ||
ca3bf3bd | 1019 | /* Get pristine xtensa-frame. */ |
bdb4c075 | 1020 | cache = xtensa_alloc_frame_cache (windowed); |
ca3bf3bd DJ |
1021 | *this_cache = cache; |
1022 | ||
3e8c568d UW |
1023 | pc = frame_unwind_register_unsigned (next_frame, |
1024 | gdbarch_pc_regnum (current_gdbarch)); | |
ca3bf3bd | 1025 | |
bdb4c075 | 1026 | if (windowed) |
ca3bf3bd | 1027 | { |
bdb4c075 MG |
1028 | /* Get WINDOWBASE, WINDOWSTART, and PS registers. */ |
1029 | wb = frame_unwind_register_unsigned (next_frame, WB_REGNUM); | |
1030 | ws = frame_unwind_register_unsigned (next_frame, WS_REGNUM); | |
1031 | ps = frame_unwind_register_unsigned (next_frame, ps_regnum); | |
ca3bf3bd | 1032 | |
bdb4c075 MG |
1033 | op1 = read_memory_integer (pc, 1); |
1034 | if (XTENSA_IS_ENTRY (op1)) | |
ca3bf3bd | 1035 | { |
bdb4c075 MG |
1036 | int callinc = CALLINC (ps); |
1037 | ra = frame_unwind_register_unsigned (next_frame, | |
1038 | A0_REGNUM + callinc * 4); | |
1039 | ||
1040 | DEBUGINFO("[xtensa_frame_cache] 'entry' at 0x%08x\n (callinc = %d)", | |
1041 | (int)pc, callinc); | |
1042 | ||
1043 | /* ENTRY hasn't been executed yet, therefore callsize is still 0. */ | |
1044 | cache->wd.callsize = 0; | |
1045 | cache->wd.wb = wb; | |
1046 | cache->wd.ws = ws; | |
1047 | cache->prev_sp = frame_unwind_register_unsigned (next_frame, | |
1048 | A1_REGNUM); | |
1049 | } | |
1050 | else | |
1051 | { | |
1052 | ra = frame_unwind_register_unsigned (next_frame, A0_REGNUM); | |
1053 | cache->wd.callsize = WINSIZE (ra); | |
1054 | cache->wd.wb = (wb - cache->wd.callsize / 4) & (NUM_AREGS / 4 - 1); | |
1055 | cache->wd.ws = ws & ~(1 << wb); | |
ca3bf3bd DJ |
1056 | } |
1057 | ||
bdb4c075 MG |
1058 | cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME); |
1059 | cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff); | |
1060 | cache->ps = (ps & ~PS_CALLINC_MASK) | |
1061 | | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT); | |
1062 | ||
1063 | if (cache->wd.ws == 0) | |
ca3bf3bd | 1064 | { |
bdb4c075 | 1065 | int i; |
ca3bf3bd | 1066 | |
bdb4c075 MG |
1067 | /* Set A0...A3. */ |
1068 | sp = frame_unwind_register_unsigned (next_frame, A1_REGNUM) - 16; | |
1069 | ||
1070 | for (i = 0; i < 4; i++, sp += 4) | |
1071 | { | |
1072 | cache->wd.aregs[i] = sp; | |
1073 | } | |
ca3bf3bd | 1074 | |
bdb4c075 | 1075 | if (cache->wd.callsize > 4) |
ca3bf3bd | 1076 | { |
bdb4c075 MG |
1077 | /* Set A4...A7/A11. */ |
1078 | /* Read an SP of the previous frame. */ | |
1079 | sp = (CORE_ADDR) read_memory_integer (sp - 12, 4); | |
1080 | sp -= cache->wd.callsize * 4; | |
1081 | ||
1082 | for ( /* i=4 */ ; i < cache->wd.callsize; i++, sp += 4) | |
1083 | { | |
1084 | cache->wd.aregs[i] = sp; | |
1085 | } | |
ca3bf3bd DJ |
1086 | } |
1087 | } | |
ca3bf3bd | 1088 | |
bdb4c075 MG |
1089 | if ((cache->prev_sp == 0) && ( ra != 0 )) |
1090 | /* If RA is equal to 0 this frame is an outermost frame. Leave | |
1091 | cache->prev_sp unchanged marking the boundary of the frame stack. */ | |
ca3bf3bd | 1092 | { |
bdb4c075 MG |
1093 | if (cache->wd.ws == 0) |
1094 | { | |
1095 | /* Register window overflow already happened. | |
1096 | We can read caller's SP from the proper spill loction. */ | |
1097 | cache->prev_sp = | |
1098 | read_memory_integer (cache->wd.aregs[1], | |
1099 | register_size (current_gdbarch, | |
1100 | A1_REGNUM)); | |
1101 | } | |
1102 | else | |
1103 | { | |
1104 | /* Read caller's frame SP directly from the previous window. */ | |
1105 | int regnum = AREG_NUMBER (A1_REGNUM, cache->wd.wb); | |
ca3bf3bd | 1106 | |
bdb4c075 MG |
1107 | cache->prev_sp = xtensa_read_register (regnum); |
1108 | } | |
ca3bf3bd DJ |
1109 | } |
1110 | } | |
bdb4c075 MG |
1111 | else /* Call0 framework. */ |
1112 | { | |
1113 | call0_frame_cache (next_frame, cache, pc); | |
1114 | } | |
ca3bf3bd DJ |
1115 | |
1116 | cache->base = frame_unwind_register_unsigned (next_frame,A1_REGNUM); | |
1117 | ||
ca3bf3bd DJ |
1118 | return cache; |
1119 | } | |
1120 | ||
ca3bf3bd DJ |
1121 | static void |
1122 | xtensa_frame_this_id (struct frame_info *next_frame, | |
1123 | void **this_cache, | |
1124 | struct frame_id *this_id) | |
1125 | { | |
1126 | struct xtensa_frame_cache *cache = | |
1127 | xtensa_frame_cache (next_frame, this_cache); | |
bdb4c075 | 1128 | struct frame_id id; |
ca3bf3bd | 1129 | |
bdb4c075 MG |
1130 | DEBUGTRACE ("xtensa_frame_this_id (next 0x%08x, *this 0x%08x)\n", |
1131 | (unsigned int) next_frame, (unsigned int) *this_cache); | |
ca3bf3bd DJ |
1132 | |
1133 | if (cache->prev_sp == 0) | |
1134 | return; | |
1135 | ||
bdb4c075 MG |
1136 | id = frame_id_build (cache->prev_sp, cache->pc); |
1137 | if (frame_id_eq (id, get_frame_id(next_frame))) | |
1138 | { | |
1139 | warning(_("\ | |
1140 | Frame stack is corrupted. That could happen because of \ | |
1141 | setting register(s) from GDB or stopping execution \ | |
1142 | inside exception handler. Frame backtracing has stopped. \ | |
1143 | It can make some GDB commands work inappropriately.\n")); | |
1144 | cache->prev_sp = 0; | |
1145 | return; | |
1146 | } | |
1147 | (*this_id) = id; | |
ca3bf3bd DJ |
1148 | } |
1149 | ||
bdb4c075 MG |
1150 | static int |
1151 | call0_frame_get_reg_at_entry (struct frame_info *next_frame, | |
1152 | struct xtensa_frame_cache *cache, | |
1153 | int regnum, | |
1154 | CORE_ADDR *addrp, | |
1155 | enum lval_type *lval, | |
1156 | gdb_byte *valuep) | |
1157 | { | |
1158 | CORE_ADDR fp, spe; | |
1159 | int stkofs; | |
1160 | int reg = (regnum >= AR_BASE && regnum <= (AR_BASE + C0_NREGS)) | |
1161 | ? regnum - AR_BASE : regnum; | |
1162 | ||
1163 | /* Determine stack pointer on entry to this function, based on FP. */ | |
1164 | spe = cache->c0.c0_fp - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs; | |
1165 | ||
1166 | /* If register was saved to the stack frame in the prologue, retrieve it. */ | |
1167 | stkofs = cache->c0.c0_rt[reg].to_stk; | |
1168 | if (stkofs != C0_NOSTK) | |
1169 | { | |
1170 | *lval = lval_memory; | |
1171 | *addrp = spe + stkofs; | |
1172 | ||
1173 | if (valuep) | |
1174 | read_memory (*addrp, valuep, register_size (current_gdbarch, regnum)); | |
1175 | ||
1176 | return 1; | |
1177 | } | |
1178 | ||
1179 | /* If not callee-saved or if known to have been overwritten, give up. */ | |
1180 | if (reg < C0_CLESV | |
1181 | || cache->c0.c0_rt[reg].fr_reg != reg | |
1182 | || cache->c0.c0_rt[reg].fr_ofs != 0) | |
1183 | return 0; | |
1184 | ||
1185 | if (get_frame_type (next_frame) != NORMAL_FRAME) | |
1186 | /* TODO: Do we need a special case for DUMMY_FRAME here? */ | |
1187 | return 0; | |
1188 | ||
1189 | return call0_frame_get_reg_at_entry (get_next_frame(next_frame), | |
1190 | cache, regnum, addrp, lval, valuep); | |
1191 | } | |
ca3bf3bd DJ |
1192 | |
1193 | static void | |
1194 | xtensa_frame_prev_register (struct frame_info *next_frame, | |
1195 | void **this_cache, | |
1196 | int regnum, | |
1197 | int *optimizedp, | |
1198 | enum lval_type *lvalp, | |
1199 | CORE_ADDR *addrp, | |
1200 | int *realnump, | |
1201 | gdb_byte *valuep) | |
1202 | { | |
1203 | struct xtensa_frame_cache *cache = | |
1204 | xtensa_frame_cache (next_frame, this_cache); | |
1205 | CORE_ADDR saved_reg = 0; | |
1206 | int done = 1; | |
1207 | ||
bdb4c075 MG |
1208 | DEBUGTRACE ("xtensa_frame_prev_register (next 0x%08x, " |
1209 | "*this 0x%08x, regnum %d (%s), ...)\n", | |
1210 | (unsigned int) next_frame, | |
1211 | *this_cache ? (unsigned int) *this_cache : 0, regnum, | |
ca3bf3bd DJ |
1212 | xtensa_register_name (regnum)); |
1213 | ||
bdb4c075 MG |
1214 | if (regnum ==gdbarch_pc_regnum (current_gdbarch)) |
1215 | saved_reg = cache->ra; | |
1216 | else if (regnum == A1_REGNUM) | |
1217 | saved_reg = cache->prev_sp; | |
1218 | else if (!cache->call0) | |
ca3bf3bd | 1219 | { |
bdb4c075 MG |
1220 | if (regnum == WS_REGNUM) |
1221 | { | |
1222 | if (cache->wd.ws != 0) | |
1223 | saved_reg = cache->wd.ws; | |
1224 | else | |
1225 | saved_reg = 1 << cache->wd.wb; | |
1226 | } | |
1227 | else if (regnum == WB_REGNUM) | |
1228 | saved_reg = cache->wd.wb; | |
1229 | else if (regnum == gdbarch_ps_regnum (current_gdbarch)) | |
1230 | saved_reg = cache->ps; | |
ca3bf3bd | 1231 | else |
bdb4c075 | 1232 | done = 0; |
ca3bf3bd | 1233 | } |
ca3bf3bd DJ |
1234 | else |
1235 | done = 0; | |
1236 | ||
1237 | if (done) | |
1238 | { | |
1239 | *optimizedp = 0; | |
1240 | *lvalp = not_lval; | |
1241 | *addrp = 0; | |
1242 | *realnump = -1; | |
1243 | if (valuep) | |
1244 | store_unsigned_integer (valuep, 4, saved_reg); | |
1245 | ||
1246 | return; | |
1247 | } | |
1248 | ||
bdb4c075 | 1249 | if (!cache->call0) /* Windowed ABI. */ |
ca3bf3bd | 1250 | { |
bdb4c075 MG |
1251 | /* Convert A-register numbers to AR-register numbers. */ |
1252 | if (regnum >= A0_REGNUM && regnum <= A15_REGNUM) | |
1253 | regnum = AREG_NUMBER (regnum, cache->wd.wb); | |
ca3bf3bd | 1254 | |
bdb4c075 MG |
1255 | /* Check if AR-register has been saved to stack. */ |
1256 | if (regnum >= AR_BASE && regnum <= (AR_BASE + NUM_AREGS)) | |
1257 | { | |
1258 | int areg = regnum - AR_BASE - (cache->wd.wb * 4); | |
ca3bf3bd | 1259 | |
bdb4c075 MG |
1260 | if (areg >= 0 |
1261 | && areg < XTENSA_NUM_SAVED_AREGS | |
1262 | && cache->wd.aregs[areg] != -1) | |
1263 | { | |
1264 | *optimizedp = 0; | |
1265 | *lvalp = lval_memory; | |
1266 | *addrp = cache->wd.aregs[areg]; | |
1267 | *realnump = -1; | |
ca3bf3bd | 1268 | |
bdb4c075 MG |
1269 | if (valuep) |
1270 | read_memory (*addrp, valuep, | |
1271 | register_size (current_gdbarch, regnum)); | |
1272 | ||
1273 | DEBUGINFO ("[xtensa_frame_prev_register] register on stack\n"); | |
1274 | return; | |
1275 | } | |
ca3bf3bd DJ |
1276 | } |
1277 | } | |
bdb4c075 MG |
1278 | else /* Call0 ABI. */ |
1279 | { | |
1280 | int reg = (regnum >= AR_BASE && regnum <= (AR_BASE + C0_NREGS)) | |
1281 | ? regnum - AR_BASE : regnum; | |
ca3bf3bd | 1282 | |
bdb4c075 MG |
1283 | if (reg < C0_NREGS) |
1284 | { | |
1285 | CORE_ADDR spe; | |
1286 | int stkofs; | |
1287 | ||
1288 | /* If register was saved in the prologue, retrieve it. */ | |
1289 | stkofs = cache->c0.c0_rt[reg].to_stk; | |
1290 | if (stkofs != C0_NOSTK) | |
1291 | { | |
1292 | /* Determine SP on entry based on FP. */ | |
1293 | spe = cache->c0.c0_fp | |
1294 | - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs; | |
1295 | *optimizedp = 0; | |
1296 | *lvalp = lval_memory; | |
1297 | *addrp = spe + stkofs; | |
1298 | *realnump = -1; | |
1299 | ||
1300 | if (valuep) | |
1301 | read_memory (*addrp, valuep, | |
1302 | register_size (current_gdbarch, regnum)); | |
1303 | ||
1304 | DEBUGINFO ("[xtensa_frame_prev_register] register on stack\n"); | |
1305 | return; | |
1306 | } | |
1307 | } | |
1308 | } | |
1309 | ||
1310 | /* All other registers have been either saved to | |
1311 | the stack or are still alive in the processor. */ | |
ca3bf3bd DJ |
1312 | |
1313 | *optimizedp = 0; | |
1314 | *lvalp = lval_register; | |
1315 | *addrp = 0; | |
1316 | *realnump = regnum; | |
1317 | if (valuep) | |
1318 | frame_unwind_register (next_frame, (*realnump), valuep); | |
1319 | } | |
1320 | ||
1321 | ||
1322 | static const struct frame_unwind | |
1323 | xtensa_frame_unwind = | |
1324 | { | |
1325 | NORMAL_FRAME, | |
1326 | xtensa_frame_this_id, | |
1327 | xtensa_frame_prev_register | |
1328 | }; | |
1329 | ||
1330 | static const struct frame_unwind * | |
1331 | xtensa_frame_sniffer (struct frame_info *next_frame) | |
1332 | { | |
1333 | return &xtensa_frame_unwind; | |
1334 | } | |
1335 | ||
1336 | static CORE_ADDR | |
1337 | xtensa_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
1338 | { | |
1339 | struct xtensa_frame_cache *cache = | |
1340 | xtensa_frame_cache (next_frame, this_cache); | |
1341 | ||
1342 | return cache->base; | |
1343 | } | |
1344 | ||
1345 | static const struct frame_base | |
1346 | xtensa_frame_base = | |
1347 | { | |
1348 | &xtensa_frame_unwind, | |
1349 | xtensa_frame_base_address, | |
1350 | xtensa_frame_base_address, | |
1351 | xtensa_frame_base_address | |
1352 | }; | |
1353 | ||
1354 | ||
1355 | static void | |
1356 | xtensa_extract_return_value (struct type *type, | |
1357 | struct regcache *regcache, | |
1358 | void *dst) | |
1359 | { | |
1360 | bfd_byte *valbuf = dst; | |
1361 | int len = TYPE_LENGTH (type); | |
1362 | ULONGEST pc, wb; | |
1363 | int callsize, areg; | |
1364 | int offset = 0; | |
1365 | ||
1366 | DEBUGTRACE ("xtensa_extract_return_value (...)\n"); | |
1367 | ||
1368 | gdb_assert(len > 0); | |
1369 | ||
bdb4c075 MG |
1370 | if (CALL_ABI != CallAbiCall0Only) |
1371 | { | |
1372 | /* First, we have to find the caller window in the register file. */ | |
1373 | regcache_raw_read_unsigned (regcache, | |
3e8c568d | 1374 | gdbarch_pc_regnum (current_gdbarch), &pc); |
bdb4c075 | 1375 | callsize = extract_call_winsize (pc); |
ca3bf3bd | 1376 | |
bdb4c075 MG |
1377 | /* On Xtensa, we can return up to 4 words (or 2 for call12). */ |
1378 | if (len > (callsize > 8 ? 8 : 16)) | |
1379 | internal_error (__FILE__, __LINE__, | |
1380 | _("cannot extract return value of %d bytes long"), len); | |
ca3bf3bd | 1381 | |
bdb4c075 MG |
1382 | /* Get the register offset of the return |
1383 | register (A2) in the caller window. */ | |
1384 | regcache_raw_read_unsigned (regcache, WB_REGNUM, &wb); | |
1385 | areg = AREG_NUMBER(A2_REGNUM + callsize, wb); | |
1386 | } | |
1387 | else | |
1388 | { | |
1389 | /* No windowing hardware - Call0 ABI. */ | |
1390 | areg = A0_REGNUM + C0_ARGS; | |
1391 | } | |
ca3bf3bd DJ |
1392 | |
1393 | DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len); | |
1394 | ||
4c6b5505 | 1395 | if (len < 4 && gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1396 | offset = 4 - len; |
1397 | ||
1398 | for (; len > 0; len -= 4, areg++, valbuf += 4) | |
1399 | { | |
1400 | if (len < 4) | |
1401 | regcache_raw_read_part (regcache, areg, offset, len, valbuf); | |
1402 | else | |
1403 | regcache_raw_read (regcache, areg, valbuf); | |
1404 | } | |
1405 | } | |
1406 | ||
1407 | ||
1408 | static void | |
1409 | xtensa_store_return_value (struct type *type, | |
1410 | struct regcache *regcache, | |
1411 | const void *dst) | |
1412 | { | |
1413 | const bfd_byte *valbuf = dst; | |
1414 | unsigned int areg; | |
1415 | ULONGEST pc, wb; | |
1416 | int callsize; | |
1417 | int len = TYPE_LENGTH (type); | |
1418 | int offset = 0; | |
1419 | ||
1420 | DEBUGTRACE ("xtensa_store_return_value (...)\n"); | |
1421 | ||
bdb4c075 MG |
1422 | if (CALL_ABI != CallAbiCall0Only) |
1423 | { | |
1424 | regcache_raw_read_unsigned (regcache, WB_REGNUM, &wb); | |
3e8c568d UW |
1425 | regcache_raw_read_unsigned (regcache, |
1426 | gdbarch_pc_regnum (current_gdbarch), &pc); | |
bdb4c075 | 1427 | callsize = extract_call_winsize (pc); |
ca3bf3bd | 1428 | |
bdb4c075 MG |
1429 | if (len > (callsize > 8 ? 8 : 16)) |
1430 | internal_error (__FILE__, __LINE__, | |
1431 | _("unimplemented for this length: %d"), | |
1432 | TYPE_LENGTH (type)); | |
1433 | areg = AREG_NUMBER (A2_REGNUM + callsize, wb); | |
ca3bf3bd | 1434 | |
bdb4c075 | 1435 | DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n", |
ca3bf3bd | 1436 | callsize, (int) wb); |
bdb4c075 MG |
1437 | } |
1438 | else | |
1439 | { | |
1440 | areg = A0_REGNUM + C0_ARGS; | |
1441 | } | |
ca3bf3bd | 1442 | |
4c6b5505 | 1443 | if (len < 4 && gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1444 | offset = 4 - len; |
1445 | ||
ca3bf3bd DJ |
1446 | for (; len > 0; len -= 4, areg++, valbuf += 4) |
1447 | { | |
1448 | if (len < 4) | |
1449 | regcache_raw_write_part (regcache, areg, offset, len, valbuf); | |
1450 | else | |
1451 | regcache_raw_write (regcache, areg, valbuf); | |
1452 | } | |
1453 | } | |
1454 | ||
1455 | ||
bdb4c075 | 1456 | static enum return_value_convention |
ca3bf3bd DJ |
1457 | xtensa_return_value (struct gdbarch *gdbarch, |
1458 | struct type *valtype, | |
1459 | struct regcache *regcache, | |
1460 | gdb_byte *readbuf, | |
1461 | const gdb_byte *writebuf) | |
1462 | { | |
bdb4c075 | 1463 | /* Structures up to 16 bytes are returned in registers. */ |
ca3bf3bd DJ |
1464 | |
1465 | int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT | |
1466 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
1467 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
1468 | && TYPE_LENGTH (valtype) > 16); | |
1469 | ||
1470 | if (struct_return) | |
1471 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1472 | ||
1473 | DEBUGTRACE ("xtensa_return_value(...)\n"); | |
1474 | ||
1475 | if (writebuf != NULL) | |
1476 | { | |
1477 | xtensa_store_return_value (valtype, regcache, writebuf); | |
1478 | } | |
1479 | ||
1480 | if (readbuf != NULL) | |
1481 | { | |
1482 | gdb_assert (!struct_return); | |
1483 | xtensa_extract_return_value (valtype, regcache, readbuf); | |
1484 | } | |
1485 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1486 | } | |
1487 | ||
1488 | ||
1489 | /* DUMMY FRAME */ | |
1490 | ||
1491 | static CORE_ADDR | |
1492 | xtensa_push_dummy_call (struct gdbarch *gdbarch, | |
1493 | struct value *function, | |
1494 | struct regcache *regcache, | |
1495 | CORE_ADDR bp_addr, | |
1496 | int nargs, | |
1497 | struct value **args, | |
1498 | CORE_ADDR sp, | |
1499 | int struct_return, | |
1500 | CORE_ADDR struct_addr) | |
1501 | { | |
1502 | int i; | |
1503 | int size, onstack_size; | |
ff7a4c00 | 1504 | gdb_byte *buf = (gdb_byte *) alloca (16); |
ca3bf3bd DJ |
1505 | CORE_ADDR ra, ps; |
1506 | struct argument_info | |
1507 | { | |
1508 | const bfd_byte *contents; | |
1509 | int length; | |
1510 | int onstack; /* onstack == 0 => in reg */ | |
1511 | int align; /* alignment */ | |
1512 | union | |
1513 | { | |
1514 | int offset; /* stack offset if on stack */ | |
1515 | int regno; /* regno if in register */ | |
1516 | } u; | |
1517 | }; | |
1518 | ||
1519 | struct argument_info *arg_info = | |
1520 | (struct argument_info *) alloca (nargs * sizeof (struct argument_info)); | |
1521 | ||
1522 | CORE_ADDR osp = sp; | |
1523 | ||
1524 | DEBUGTRACE ("xtensa_push_dummy_call (...)\n"); | |
1525 | ||
1526 | if (xtensa_debug_level > 3) | |
1527 | { | |
1528 | int i; | |
1529 | DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs); | |
1530 | DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, " | |
1531 | "struct_addr=0x%x\n", | |
1532 | (int) sp, (int) struct_return, (int) struct_addr); | |
1533 | ||
1534 | for (i = 0; i < nargs; i++) | |
1535 | { | |
1536 | struct value *arg = args[i]; | |
1537 | struct type *arg_type = check_typedef (value_type (arg)); | |
bdb4c075 MG |
1538 | fprintf_unfiltered (gdb_stdlog, "%2d: 0x%08x %3d ", |
1539 | i, (int) arg, TYPE_LENGTH (arg_type)); | |
ca3bf3bd DJ |
1540 | switch (TYPE_CODE (arg_type)) |
1541 | { | |
1542 | case TYPE_CODE_INT: | |
1543 | fprintf_unfiltered (gdb_stdlog, "int"); | |
1544 | break; | |
1545 | case TYPE_CODE_STRUCT: | |
1546 | fprintf_unfiltered (gdb_stdlog, "struct"); | |
1547 | break; | |
1548 | default: | |
1549 | fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type)); | |
1550 | break; | |
1551 | } | |
bdb4c075 MG |
1552 | fprintf_unfiltered (gdb_stdlog, " 0x%08x\n", |
1553 | (unsigned int) value_contents (arg)); | |
ca3bf3bd DJ |
1554 | } |
1555 | } | |
1556 | ||
1557 | /* First loop: collect information. | |
1558 | Cast into type_long. (This shouldn't happen often for C because | |
1559 | GDB already does this earlier.) It's possible that GDB could | |
1560 | do it all the time but it's harmless to leave this code here. */ | |
1561 | ||
1562 | size = 0; | |
1563 | onstack_size = 0; | |
1564 | i = 0; | |
1565 | ||
1566 | if (struct_return) | |
1567 | size = REGISTER_SIZE; | |
1568 | ||
1569 | for (i = 0; i < nargs; i++) | |
1570 | { | |
1571 | struct argument_info *info = &arg_info[i]; | |
1572 | struct value *arg = args[i]; | |
1573 | struct type *arg_type = check_typedef (value_type (arg)); | |
1574 | ||
1575 | switch (TYPE_CODE (arg_type)) | |
1576 | { | |
1577 | case TYPE_CODE_INT: | |
1578 | case TYPE_CODE_BOOL: | |
1579 | case TYPE_CODE_CHAR: | |
1580 | case TYPE_CODE_RANGE: | |
1581 | case TYPE_CODE_ENUM: | |
1582 | ||
1583 | /* Cast argument to long if necessary as the mask does it too. */ | |
1584 | if (TYPE_LENGTH (arg_type) < TYPE_LENGTH (builtin_type_long)) | |
1585 | { | |
1586 | arg_type = builtin_type_long; | |
1587 | arg = value_cast (arg_type, arg); | |
1588 | } | |
bdb4c075 MG |
1589 | /* Aligment is equal to the type length for the basic types. */ |
1590 | info->align = TYPE_LENGTH (arg_type); | |
ca3bf3bd DJ |
1591 | break; |
1592 | ||
1593 | case TYPE_CODE_FLT: | |
1594 | ||
1595 | /* Align doubles correctly. */ | |
1596 | if (TYPE_LENGTH (arg_type) == TYPE_LENGTH (builtin_type_double)) | |
1597 | info->align = TYPE_LENGTH (builtin_type_double); | |
1598 | else | |
1599 | info->align = TYPE_LENGTH (builtin_type_long); | |
1600 | break; | |
1601 | ||
1602 | case TYPE_CODE_STRUCT: | |
1603 | default: | |
1604 | info->align = TYPE_LENGTH (builtin_type_long); | |
1605 | break; | |
1606 | } | |
1607 | info->length = TYPE_LENGTH (arg_type); | |
1608 | info->contents = value_contents (arg); | |
1609 | ||
1610 | /* Align size and onstack_size. */ | |
1611 | size = (size + info->align - 1) & ~(info->align - 1); | |
1612 | onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1); | |
1613 | ||
bdb4c075 | 1614 | if (size + info->length > REGISTER_SIZE * ARG_NOF) |
ca3bf3bd DJ |
1615 | { |
1616 | info->onstack = 1; | |
1617 | info->u.offset = onstack_size; | |
1618 | onstack_size += info->length; | |
1619 | } | |
1620 | else | |
1621 | { | |
1622 | info->onstack = 0; | |
bdb4c075 | 1623 | info->u.regno = ARG_1ST + size / REGISTER_SIZE; |
ca3bf3bd DJ |
1624 | } |
1625 | size += info->length; | |
1626 | } | |
1627 | ||
1628 | /* Adjust the stack pointer and align it. */ | |
1629 | sp = align_down (sp - onstack_size, SP_ALIGNMENT); | |
1630 | ||
bdb4c075 MG |
1631 | /* Simulate MOVSP, if Windowed ABI. */ |
1632 | if ((CALL_ABI != CallAbiCall0Only) && (sp != osp)) | |
ca3bf3bd DJ |
1633 | { |
1634 | read_memory (osp - 16, buf, 16); | |
1635 | write_memory (sp - 16, buf, 16); | |
1636 | } | |
1637 | ||
1638 | /* Second Loop: Load arguments. */ | |
1639 | ||
1640 | if (struct_return) | |
1641 | { | |
1642 | store_unsigned_integer (buf, REGISTER_SIZE, struct_addr); | |
bdb4c075 | 1643 | regcache_cooked_write (regcache, ARG_1ST, buf); |
ca3bf3bd DJ |
1644 | } |
1645 | ||
1646 | for (i = 0; i < nargs; i++) | |
1647 | { | |
1648 | struct argument_info *info = &arg_info[i]; | |
1649 | ||
1650 | if (info->onstack) | |
1651 | { | |
1652 | int n = info->length; | |
1653 | CORE_ADDR offset = sp + info->u.offset; | |
1654 | ||
1655 | /* Odd-sized structs are aligned to the lower side of a memory | |
1656 | word in big-endian mode and require a shift. This only | |
1657 | applies for structures smaller than one word. */ | |
1658 | ||
4c6b5505 UW |
1659 | if (n < REGISTER_SIZE |
1660 | && gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) | |
ca3bf3bd DJ |
1661 | offset += (REGISTER_SIZE - n); |
1662 | ||
1663 | write_memory (offset, info->contents, info->length); | |
1664 | ||
1665 | } | |
1666 | else | |
1667 | { | |
1668 | int n = info->length; | |
1669 | const bfd_byte *cp = info->contents; | |
1670 | int r = info->u.regno; | |
1671 | ||
1672 | /* Odd-sized structs are aligned to the lower side of registers in | |
1673 | big-endian mode and require a shift. The odd-sized leftover will | |
1674 | be at the end. Note that this is only true for structures smaller | |
1675 | than REGISTER_SIZE; for larger odd-sized structures the excess | |
1676 | will be left-aligned in the register on both endiannesses. */ | |
1677 | ||
4c6b5505 UW |
1678 | if (n < REGISTER_SIZE |
1679 | && gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) | |
ca3bf3bd DJ |
1680 | { |
1681 | ULONGEST v = extract_unsigned_integer (cp, REGISTER_SIZE); | |
1682 | v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT); | |
1683 | ||
1684 | store_unsigned_integer (buf, REGISTER_SIZE, v); | |
1685 | regcache_cooked_write (regcache, r, buf); | |
1686 | ||
1687 | cp += REGISTER_SIZE; | |
1688 | n -= REGISTER_SIZE; | |
1689 | r++; | |
1690 | } | |
1691 | else | |
1692 | while (n > 0) | |
1693 | { | |
ca3bf3bd DJ |
1694 | regcache_cooked_write (regcache, r, cp); |
1695 | ||
ca3bf3bd DJ |
1696 | cp += REGISTER_SIZE; |
1697 | n -= REGISTER_SIZE; | |
1698 | r++; | |
1699 | } | |
1700 | } | |
1701 | } | |
1702 | ||
ca3bf3bd | 1703 | /* Set the return address of dummy frame to the dummy address. |
bdb4c075 | 1704 | The return address for the current function (in A0) is |
ca3bf3bd DJ |
1705 | saved in the dummy frame, so we can savely overwrite A0 here. */ |
1706 | ||
bdb4c075 MG |
1707 | if (CALL_ABI != CallAbiCall0Only) |
1708 | { | |
1709 | ra = (bp_addr & 0x3fffffff) | 0x40000000; | |
1710 | regcache_raw_read (regcache, gdbarch_ps_regnum (current_gdbarch), buf); | |
1711 | ps = extract_unsigned_integer (buf, 4) & ~0x00030000; | |
1712 | regcache_cooked_write_unsigned (regcache, A4_REGNUM, ra); | |
1713 | regcache_cooked_write_unsigned (regcache, | |
1714 | gdbarch_ps_regnum (current_gdbarch), | |
1715 | ps | 0x00010000); | |
1716 | } | |
1717 | else | |
1718 | { | |
1719 | /* Simulate CALL0: write RA into A0 register. */ | |
1720 | regcache_cooked_write_unsigned (regcache, A0_REGNUM, bp_addr); | |
1721 | } | |
ca3bf3bd DJ |
1722 | |
1723 | /* Set new stack pointer and return it. */ | |
1724 | regcache_cooked_write_unsigned (regcache, A1_REGNUM, sp); | |
1725 | /* Make dummy frame ID unique by adding a constant. */ | |
1726 | return sp + SP_ALIGNMENT; | |
1727 | } | |
1728 | ||
1729 | ||
1730 | /* Return a breakpoint for the current location of PC. We always use | |
1731 | the density version if we have density instructions (regardless of the | |
1732 | current instruction at PC), and use regular instructions otherwise. */ | |
1733 | ||
1734 | #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 } | |
1735 | #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 } | |
1736 | #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f } | |
1737 | #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 } | |
1738 | ||
bdb4c075 | 1739 | static const unsigned char * |
ca3bf3bd DJ |
1740 | xtensa_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
1741 | { | |
ff7a4c00 MG |
1742 | static unsigned char big_breakpoint[] = BIG_BREAKPOINT; |
1743 | static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT; | |
1744 | static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT; | |
1745 | static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT; | |
ca3bf3bd DJ |
1746 | |
1747 | DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr); | |
1748 | ||
1749 | if (ISA_USE_DENSITY_INSTRUCTIONS) | |
1750 | { | |
4c6b5505 | 1751 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1752 | { |
1753 | *lenptr = sizeof (density_big_breakpoint); | |
1754 | return density_big_breakpoint; | |
1755 | } | |
1756 | else | |
1757 | { | |
1758 | *lenptr = sizeof (density_little_breakpoint); | |
1759 | return density_little_breakpoint; | |
1760 | } | |
1761 | } | |
1762 | else | |
1763 | { | |
4c6b5505 | 1764 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1765 | { |
1766 | *lenptr = sizeof (big_breakpoint); | |
1767 | return big_breakpoint; | |
1768 | } | |
1769 | else | |
1770 | { | |
1771 | *lenptr = sizeof (little_breakpoint); | |
1772 | return little_breakpoint; | |
1773 | } | |
1774 | } | |
1775 | } | |
1776 | ||
bdb4c075 MG |
1777 | /* Call0 ABI support routines. */ |
1778 | ||
1779 | /* Call0 opcode class. Opcodes are preclassified according to what they | |
1780 | mean for Call0 prologue analysis, and their number of significant operands. | |
1781 | The purpose of this is to simplify prologue analysis by separating | |
1782 | instruction decoding (libisa) from the semantics of prologue analysis. */ | |
1783 | ||
1784 | typedef enum { | |
1785 | c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */ | |
1786 | c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */ | |
1787 | c0opc_flow, /* Flow control insn. */ | |
1788 | c0opc_entry, /* ENTRY indicates non-Call0 prologue. */ | |
1789 | c0opc_break, /* Debugger software breakpoints. */ | |
1790 | c0opc_add, /* Adding two registers. */ | |
1791 | c0opc_addi, /* Adding a register and an immediate. */ | |
1792 | c0opc_sub, /* Subtracting a register from a register. */ | |
1793 | c0opc_mov, /* Moving a register to a register. */ | |
1794 | c0opc_movi, /* Moving an immediate to a register. */ | |
1795 | c0opc_l32r, /* Loading a literal. */ | |
1796 | c0opc_s32i, /* Storing word at fixed offset from a base register. */ | |
1797 | c0opc_NrOf /* Number of opcode classifications. */ | |
1798 | } xtensa_insn_kind; | |
1799 | ||
1800 | ||
1801 | /* Classify an opcode based on what it means for Call0 prologue analysis. */ | |
1802 | ||
1803 | static xtensa_insn_kind | |
1804 | call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc) | |
1805 | { | |
1806 | const char *opcname; | |
1807 | xtensa_insn_kind opclass = c0opc_uninteresting; | |
1808 | ||
1809 | DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc); | |
1810 | ||
1811 | /* Get opcode name and handle special classifications. */ | |
1812 | ||
1813 | opcname = xtensa_opcode_name (isa, opc); | |
1814 | ||
1815 | if (opcname == NULL | |
1816 | || strcasecmp (opcname, "ill") == 0 | |
1817 | || strcasecmp (opcname, "ill.n") == 0) | |
1818 | opclass = c0opc_illegal; | |
1819 | else if (strcasecmp (opcname, "break") == 0 | |
1820 | || strcasecmp (opcname, "break.n") == 0) | |
1821 | opclass = c0opc_break; | |
1822 | else if (strcasecmp (opcname, "entry") == 0) | |
1823 | opclass = c0opc_entry; | |
1824 | else if (xtensa_opcode_is_branch (isa, opc) > 0 | |
1825 | || xtensa_opcode_is_jump (isa, opc) > 0 | |
1826 | || xtensa_opcode_is_loop (isa, opc) > 0 | |
1827 | || xtensa_opcode_is_call (isa, opc) > 0 | |
1828 | || strcasecmp (opcname, "simcall") == 0 | |
1829 | || strcasecmp (opcname, "syscall") == 0) | |
1830 | opclass = c0opc_flow; | |
1831 | ||
1832 | /* Also, classify specific opcodes that need to be tracked. */ | |
1833 | else if (strcasecmp (opcname, "add") == 0 | |
1834 | || strcasecmp (opcname, "add.n") == 0) | |
1835 | opclass = c0opc_add; | |
1836 | else if (strcasecmp (opcname, "addi") == 0 | |
1837 | || strcasecmp (opcname, "addi.n") == 0 | |
1838 | || strcasecmp (opcname, "addmi") == 0) | |
1839 | opclass = c0opc_addi; | |
1840 | else if (strcasecmp (opcname, "sub") == 0) | |
1841 | opclass = c0opc_sub; | |
1842 | else if (strcasecmp (opcname, "mov.n") == 0 | |
1843 | || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */ | |
1844 | opclass = c0opc_mov; | |
1845 | else if (strcasecmp (opcname, "movi") == 0 | |
1846 | || strcasecmp (opcname, "movi.n") == 0) | |
1847 | opclass = c0opc_movi; | |
1848 | else if (strcasecmp (opcname, "l32r") == 0) | |
1849 | opclass = c0opc_l32r; | |
1850 | else if (strcasecmp (opcname, "s32i") == 0 | |
1851 | || strcasecmp (opcname, "s32i.n") == 0) | |
1852 | opclass = c0opc_s32i; | |
1853 | ||
1854 | return opclass; | |
1855 | } | |
1856 | ||
1857 | /* Tracks register movement/mutation for a given operation, which may | |
1858 | be within a bundle. Updates the destination register tracking info | |
1859 | accordingly. The pc is needed only for pc-relative load instructions | |
1860 | (eg. l32r). The SP register number is needed to identify stores to | |
1861 | the stack frame. */ | |
1862 | ||
1863 | static void | |
1864 | call0_track_op (xtensa_c0reg_t dst[], xtensa_c0reg_t src[], | |
1865 | xtensa_insn_kind opclass, int nods, unsigned odv[], | |
1866 | CORE_ADDR pc, int spreg) | |
1867 | { | |
1868 | unsigned litbase, litaddr, litval; | |
1869 | ||
1870 | switch (opclass) | |
1871 | { | |
1872 | case c0opc_addi: | |
1873 | /* 3 operands: dst, src, imm. */ | |
1874 | gdb_assert (nods == 3); | |
1875 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
1876 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2]; | |
1877 | break; | |
1878 | case c0opc_add: | |
1879 | /* 3 operands: dst, src1, src2. */ | |
1880 | gdb_assert (nods == 3); | |
1881 | if (src[odv[1]].fr_reg == C0_CONST) | |
1882 | { | |
1883 | dst[odv[0]].fr_reg = src[odv[2]].fr_reg; | |
1884 | dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs; | |
1885 | } | |
1886 | else if (src[odv[2]].fr_reg == C0_CONST) | |
1887 | { | |
1888 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
1889 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs; | |
1890 | } | |
1891 | else dst[odv[0]].fr_reg = C0_INEXP; | |
1892 | break; | |
1893 | case c0opc_sub: | |
1894 | /* 3 operands: dst, src1, src2. */ | |
1895 | gdb_assert (nods == 3); | |
1896 | if (src[odv[2]].fr_reg == C0_CONST) | |
1897 | { | |
1898 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
1899 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs; | |
1900 | } | |
1901 | else dst[odv[0]].fr_reg = C0_INEXP; | |
1902 | break; | |
1903 | case c0opc_mov: | |
1904 | /* 2 operands: dst, src [, src]. */ | |
1905 | gdb_assert (nods == 2); | |
1906 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
1907 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs; | |
1908 | break; | |
1909 | case c0opc_movi: | |
1910 | /* 2 operands: dst, imm. */ | |
1911 | gdb_assert (nods == 2); | |
1912 | dst[odv[0]].fr_reg = C0_CONST; | |
1913 | dst[odv[0]].fr_ofs = odv[1]; | |
1914 | break; | |
1915 | case c0opc_l32r: | |
1916 | /* 2 operands: dst, literal offset. */ | |
1917 | gdb_assert (nods == 2); | |
1918 | /* litbase = xtensa_get_litbase (pc); can be also used. */ | |
1919 | litbase = (LITBASE_REGNUM == -1) | |
1920 | ? 0 : xtensa_read_register (LITBASE_REGNUM); | |
1921 | litaddr = litbase & 1 | |
1922 | ? (litbase & ~1) + (signed)odv[1] | |
1923 | : (pc + 3 + (signed)odv[1]) & ~3; | |
1924 | litval = read_memory_integer(litaddr, 4); | |
1925 | dst[odv[0]].fr_reg = C0_CONST; | |
1926 | dst[odv[0]].fr_ofs = litval; | |
1927 | break; | |
1928 | case c0opc_s32i: | |
1929 | /* 3 operands: value, base, offset. */ | |
1930 | gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS); | |
1931 | if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */ | |
1932 | && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */ | |
1933 | && src[odv[0]].fr_reg >= 0 /* Value is from a register. */ | |
1934 | && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */ | |
1935 | && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */ | |
1936 | { | |
1937 | /* ISA encoding guarantees alignment. But, check it anyway. */ | |
1938 | gdb_assert ((odv[2] & 3) == 0); | |
1939 | dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2]; | |
1940 | } | |
1941 | break; | |
1942 | default: | |
1943 | gdb_assert (0); | |
1944 | } | |
1945 | } | |
1946 | ||
1947 | /* Analyze prologue of the function at start address to determine if it uses | |
1948 | the Call0 ABI, and if so track register moves and linear modifications | |
1949 | in the prologue up to the PC or just beyond the prologue, whichever is first. | |
1950 | An 'entry' instruction indicates non-Call0 ABI and the end of the prologue. | |
1951 | The prologue may overlap non-prologue instructions but is guaranteed to end | |
1952 | by the first flow-control instruction (jump, branch, call or return). | |
1953 | Since an optimized function may move information around and change the | |
1954 | stack frame arbitrarily during the prologue, the information is guaranteed | |
1955 | valid only at the point in the function indicated by the PC. | |
1956 | May be used to skip the prologue or identify the ABI, w/o tracking. | |
1957 | ||
1958 | Returns: Address of first instruction after prologue, or PC (whichever | |
1959 | is first), or 0, if decoding failed (in libisa). | |
1960 | Input args: | |
1961 | start Start address of function/prologue. | |
1962 | pc Program counter to stop at. Use 0 to continue to end of prologue. | |
1963 | If 0, avoids infinite run-on in corrupt code memory by bounding | |
1964 | the scan to the end of the function if that can be determined. | |
1965 | nregs Number of general registers to track (size of rt[] array). | |
1966 | InOut args: | |
1967 | rt[] Array[nregs] of xtensa_c0reg structures for register tracking info. | |
1968 | If NULL, registers are not tracked. | |
1969 | Output args: | |
1970 | call0 If != NULL, *call0 is set non-zero if Call0 ABI used, else 0 | |
1971 | (more accurately, non-zero until 'entry' insn is encountered). | |
1972 | ||
1973 | Note that these may produce useful results even if decoding fails | |
1974 | because they begin with default assumptions that analysis may change. */ | |
1975 | ||
1976 | static CORE_ADDR | |
1977 | call0_analyze_prologue (CORE_ADDR start, CORE_ADDR pc, | |
1978 | int nregs, xtensa_c0reg_t rt[], int *call0) | |
1979 | { | |
1980 | CORE_ADDR ia; /* Current insn address in prologue. */ | |
1981 | CORE_ADDR ba = 0; /* Current address at base of insn buffer. */ | |
1982 | CORE_ADDR bt; /* Current address at top+1 of insn buffer. */ | |
1983 | #define BSZ 32 /* Instruction buffer size. */ | |
1984 | char ibuf[BSZ]; /* Instruction buffer for decoding prologue. */ | |
1985 | xtensa_isa isa; /* libisa ISA handle. */ | |
1986 | xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */ | |
1987 | xtensa_format ifmt; /* libisa instruction format. */ | |
1988 | int ilen, islots, is; /* Instruction length, nbr slots, current slot. */ | |
1989 | xtensa_opcode opc; /* Opcode in current slot. */ | |
1990 | xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */ | |
1991 | int nods; /* Opcode number of operands. */ | |
1992 | unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */ | |
1993 | xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */ | |
1994 | int j; /* General loop counter. */ | |
1995 | int fail = 0; /* Set non-zero and exit, if decoding fails. */ | |
1996 | CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */ | |
1997 | CORE_ADDR end_pc; /* The PC for the lust function insn. */ | |
1998 | ||
1999 | struct symtab_and_line prologue_sal; | |
2000 | ||
2001 | DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n", | |
2002 | (int)start, (int)pc); | |
2003 | ||
2004 | /* Try to limit the scan to the end of the function if a non-zero pc | |
2005 | arg was not supplied to avoid probing beyond the end of valid memory. | |
2006 | If memory is full of garbage that classifies as c0opc_uninteresting. | |
2007 | If this fails (eg. if no symbols) pc ends up 0 as it was. | |
2008 | Intialize the Call0 frame and register tracking info. | |
2009 | Assume it's Call0 until an 'entry' instruction is encountered. | |
2010 | Assume we may be in the prologue until we hit a flow control instr. */ | |
2011 | ||
2012 | rtmp = NULL; | |
2013 | body_pc = INT_MAX; | |
2014 | end_pc = 0; | |
2015 | ||
2016 | /* Find out, if we have an information about the prologue from DWARF. */ | |
2017 | prologue_sal = find_pc_line (start, 0); | |
2018 | if (prologue_sal.line != 0) /* Found debug info. */ | |
2019 | body_pc = prologue_sal.end; | |
2020 | ||
2021 | /* If we are going to analyze the prologue in general without knowing about | |
2022 | the current PC, make the best assumtion for the end of the prologue. */ | |
2023 | if (pc == 0) | |
2024 | { | |
2025 | find_pc_partial_function (start, 0, NULL, &end_pc); | |
2026 | body_pc = min (end_pc, body_pc); | |
2027 | } | |
2028 | else | |
2029 | body_pc = min (pc, body_pc); | |
2030 | ||
2031 | if (call0 != NULL) | |
2032 | *call0 = 1; | |
2033 | ||
2034 | if (rt != NULL) | |
2035 | { | |
2036 | rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t)); | |
2037 | /* rt is already initialized in xtensa_alloc_frame_cache(). */ | |
2038 | } | |
2039 | else nregs = 0; | |
2040 | ||
2041 | isa = xtensa_default_isa; | |
2042 | gdb_assert (BSZ >= xtensa_isa_maxlength (isa)); | |
2043 | ins = xtensa_insnbuf_alloc (isa); | |
2044 | slot = xtensa_insnbuf_alloc (isa); | |
2045 | ||
2046 | for (ia = start, bt = ia; ia < body_pc ; ia += ilen) | |
2047 | { | |
2048 | /* (Re)fill instruction buffer from memory if necessary, but do not | |
2049 | read memory beyond PC to be sure we stay within text section | |
2050 | (this protection only works if a non-zero pc is supplied). */ | |
2051 | ||
2052 | if (ia + xtensa_isa_maxlength (isa) > bt) | |
2053 | { | |
2054 | ba = ia; | |
2055 | bt = (ba + BSZ) < body_pc ? ba + BSZ : body_pc; | |
2056 | read_memory (ba, ibuf, bt - ba); | |
2057 | } | |
2058 | ||
2059 | /* Decode format information. */ | |
2060 | ||
2061 | xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); | |
2062 | ifmt = xtensa_format_decode (isa, ins); | |
2063 | if (ifmt == XTENSA_UNDEFINED) | |
2064 | { | |
2065 | fail = 1; | |
2066 | goto done; | |
2067 | } | |
2068 | ilen = xtensa_format_length (isa, ifmt); | |
2069 | if (ilen == XTENSA_UNDEFINED) | |
2070 | { | |
2071 | fail = 1; | |
2072 | goto done; | |
2073 | } | |
2074 | islots = xtensa_format_num_slots (isa, ifmt); | |
2075 | if (islots == XTENSA_UNDEFINED) | |
2076 | { | |
2077 | fail = 1; | |
2078 | goto done; | |
2079 | } | |
2080 | ||
2081 | /* Analyze a bundle or a single instruction, using a snapshot of | |
2082 | the register tracking info as input for the entire bundle so that | |
2083 | register changes do not take effect within this bundle. */ | |
ca3bf3bd | 2084 | |
bdb4c075 MG |
2085 | for (j = 0; j < nregs; ++j) |
2086 | rtmp[j] = rt[j]; | |
2087 | ||
2088 | for (is = 0; is < islots; ++is) | |
2089 | { | |
2090 | /* Decode a slot and classify the opcode. */ | |
2091 | ||
2092 | fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot); | |
2093 | if (fail) | |
2094 | goto done; | |
2095 | ||
2096 | opc = xtensa_opcode_decode (isa, ifmt, is, slot); | |
2097 | DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n", | |
2098 | (unsigned)ia, opc); | |
2099 | if (opc == XTENSA_UNDEFINED) | |
2100 | opclass = c0opc_illegal; | |
2101 | else | |
2102 | opclass = call0_classify_opcode (isa, opc); | |
2103 | ||
2104 | /* Decide whether to track this opcode, ignore it, or bail out. */ | |
2105 | ||
2106 | switch (opclass) | |
2107 | { | |
2108 | case c0opc_illegal: | |
2109 | case c0opc_break: | |
2110 | fail = 1; | |
2111 | goto done; | |
2112 | ||
2113 | case c0opc_uninteresting: | |
2114 | continue; | |
2115 | ||
2116 | case c0opc_flow: | |
2117 | goto done; | |
2118 | ||
2119 | case c0opc_entry: | |
2120 | if (call0 != NULL) | |
2121 | *call0 = 0; | |
2122 | ia += ilen; /* Skip over 'entry' insn. */ | |
2123 | goto done; | |
2124 | ||
2125 | default: | |
2126 | if (call0 != NULL) | |
2127 | *call0 = 1; | |
2128 | } | |
2129 | ||
2130 | /* Only expected opcodes should get this far. */ | |
2131 | if (rt == NULL) | |
2132 | continue; | |
2133 | ||
2134 | /* Extract and decode the operands. */ | |
2135 | nods = xtensa_opcode_num_operands (isa, opc); | |
2136 | if (nods == XTENSA_UNDEFINED) | |
2137 | { | |
2138 | fail = 1; | |
2139 | goto done; | |
2140 | } | |
2141 | ||
2142 | for (j = 0; j < nods && j < C0_MAXOPDS; ++j) | |
2143 | { | |
2144 | fail = xtensa_operand_get_field (isa, opc, j, ifmt, | |
2145 | is, slot, &odv[j]); | |
2146 | if (fail) | |
2147 | goto done; | |
2148 | ||
2149 | fail = xtensa_operand_decode (isa, opc, j, &odv[j]); | |
2150 | if (fail) | |
2151 | goto done; | |
2152 | } | |
2153 | ||
2154 | /* Check operands to verify use of 'mov' assembler macro. */ | |
2155 | if (opclass == c0opc_mov && nods == 3) | |
2156 | { | |
2157 | if (odv[2] == odv[1]) | |
2158 | nods = 2; | |
2159 | else | |
2160 | { | |
2161 | opclass = c0opc_uninteresting; | |
2162 | continue; | |
2163 | } | |
2164 | } | |
2165 | ||
2166 | /* Track register movement and modification for this operation. */ | |
2167 | call0_track_op (rt, rtmp, opclass, nods, odv, ia, 1); | |
2168 | } | |
2169 | } | |
2170 | done: | |
2171 | DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n", | |
2172 | (unsigned)ia, fail ? "failed" : "succeeded"); | |
2173 | xtensa_insnbuf_free(isa, slot); | |
2174 | xtensa_insnbuf_free(isa, ins); | |
2175 | return fail ? 0 : ia; | |
2176 | } | |
2177 | ||
2178 | /* Initialize frame cache for the current frame. The "next_frame" is the next | |
2179 | one relative to current frame. "cache" is the pointer to the data structure | |
2180 | we have to initialize. "pc" is curretnt PC. */ | |
2181 | ||
2182 | static void | |
2183 | call0_frame_cache (struct frame_info *next_frame, | |
2184 | xtensa_frame_cache_t *cache, CORE_ADDR pc) | |
2185 | { | |
2186 | CORE_ADDR start_pc; /* The beginning of the function. */ | |
2187 | CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */ | |
2188 | CORE_ADDR sp, fp, ra; | |
2189 | int fp_regnum, c0_hasfp, c0_frmsz, prev_sp, to_stk; | |
2190 | ||
2191 | /* Find the beginning of the prologue of the function containing the PC | |
2192 | and analyze it up to the PC or the end of the prologue. */ | |
2193 | ||
2194 | if (find_pc_partial_function (pc, NULL, &start_pc, NULL)) | |
2195 | { | |
2196 | body_pc = call0_analyze_prologue (start_pc, pc, C0_NREGS, | |
2197 | &cache->c0.c0_rt[0], | |
2198 | &cache->call0); | |
2199 | } | |
2200 | ||
2201 | sp = frame_unwind_register_unsigned (next_frame, A1_REGNUM); | |
2202 | fp = sp; /* Assume FP == SP until proven otherwise. */ | |
2203 | ||
2204 | /* Get the frame information and FP (if used) at the current PC. | |
2205 | If PC is in the prologue, the prologue analysis is more reliable | |
2206 | than DWARF info. We don't not know for sure if PC is in the prologue, | |
2207 | but we know no calls have yet taken place, so we can almost | |
2208 | certainly rely on the prologue analysis. */ | |
2209 | ||
2210 | if (body_pc <= pc) | |
2211 | { | |
2212 | /* Prologue analysis was successful up to the PC. | |
2213 | It includes the cases when PC == START_PC. */ | |
2214 | c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP; | |
2215 | /* c0_hasfp == true means there is a frame pointer because | |
2216 | we analyzed the prologue and found that cache->c0.c0_rt[C0_FP] | |
2217 | was derived from SP. Otherwise, it would be C0_FP. */ | |
2218 | fp_regnum = c0_hasfp ? C0_FP : C0_SP; | |
2219 | c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs; | |
2220 | fp_regnum += A0_BASE; | |
2221 | } | |
2222 | else /* No data from the prologue analysis. */ | |
2223 | { | |
2224 | c0_hasfp = 0; | |
2225 | fp_regnum = A0_BASE + C0_SP; | |
2226 | c0_frmsz = 0; | |
2227 | start_pc = pc; | |
2228 | } | |
2229 | ||
2230 | prev_sp = fp + c0_frmsz; | |
2231 | ||
2232 | /* Frame size from debug info or prologue tracking does not account for | |
2233 | alloca() and other dynamic allocations. Adjust frame size by FP - SP. */ | |
2234 | if (c0_hasfp) | |
2235 | { | |
2236 | fp = frame_unwind_register_unsigned (next_frame, fp_regnum); | |
2237 | ||
2238 | /* Recalculate previous SP. */ | |
2239 | prev_sp = fp + c0_frmsz; | |
2240 | /* Update the stack frame size. */ | |
2241 | c0_frmsz += fp - sp; | |
2242 | } | |
2243 | ||
2244 | /* Get the return address (RA) from the stack if saved, | |
2245 | or try to get it from a register. */ | |
2246 | ||
2247 | to_stk = cache->c0.c0_rt[C0_RA].to_stk; | |
2248 | if (to_stk != C0_NOSTK) | |
2249 | ra = (CORE_ADDR) | |
2250 | read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk, 4); | |
2251 | ||
2252 | else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST | |
2253 | && cache->c0.c0_rt[C0_RA].fr_ofs == 0) | |
2254 | { | |
2255 | /* Special case for terminating backtrace at a function that wants to | |
2256 | be seen as the outermost. Such a function will clear it's RA (A0) | |
2257 | register to 0 in the prologue instead of saving its original value. */ | |
2258 | ra = 0; | |
2259 | } | |
2260 | else | |
2261 | { | |
2262 | /* RA was copied to another register or (before any function call) may | |
2263 | still be in the original RA register. This is not always reliable: | |
2264 | even in a leaf function, register tracking stops after prologue, and | |
2265 | even in prologue, non-prologue instructions (not tracked) may overwrite | |
2266 | RA or any register it was copied to. If likely in prologue or before | |
2267 | any call, use retracking info and hope for the best (compiler should | |
2268 | have saved RA in stack if not in a leaf function). If not in prologue, | |
2269 | too bad. */ | |
2270 | ||
2271 | int i; | |
2272 | for (i = 0; | |
2273 | (i < C0_NREGS) && | |
2274 | (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA); | |
2275 | ++i); | |
2276 | if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA) | |
2277 | i = C0_RA; | |
2278 | if (i < C0_NREGS) /* Read from the next_frame. */ | |
2279 | { | |
2280 | ra = frame_unwind_register_unsigned (next_frame, | |
2281 | A0_REGNUM + cache->c0.c0_rt[i].fr_reg); | |
2282 | } | |
2283 | else ra = 0; | |
2284 | } | |
2285 | ||
2286 | cache->pc = start_pc; | |
2287 | cache->ra = ra; | |
2288 | /* RA == 0 marks the outermost frame. Do not go past it. */ | |
2289 | cache->prev_sp = (ra != 0) ? prev_sp : 0; | |
2290 | cache->c0.fp_regnum = fp_regnum; | |
2291 | cache->c0.c0_frmsz = c0_frmsz; | |
2292 | cache->c0.c0_hasfp = c0_hasfp; | |
2293 | cache->c0.c0_fp = fp; | |
2294 | } | |
2295 | ||
2296 | ||
2297 | /* Skip function prologue. | |
2298 | ||
2299 | Return the pc of the first instruction after prologue. GDB calls this to | |
2300 | find the address of the first line of the function or (if there is no line | |
2301 | number information) to skip the prologue for planting breakpoints on | |
2302 | function entries. Use debug info (if present) or prologue analysis to skip | |
2303 | the prologue to achieve reliable debugging behavior. For windowed ABI, | |
2304 | only the 'entry' instruction is skipped. It is not strictly necessary to | |
2305 | skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to | |
2306 | backtrace at any point in the prologue, however certain potential hazards | |
2307 | are avoided and a more "normal" debugging experience is ensured by | |
2308 | skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG). | |
2309 | For example, if we don't skip the prologue: | |
2310 | - Some args may not yet have been saved to the stack where the debug | |
2311 | info expects to find them (true anyway when only 'entry' is skipped); | |
2312 | - Software breakpoints ('break' instrs) may not have been unplanted | |
2313 | when the prologue analysis is done on initializing the frame cache, | |
2314 | and breaks in the prologue will throw off the analysis. | |
ca3bf3bd DJ |
2315 | |
2316 | If we have debug info ( line-number info, in particular ) we simply skip | |
2317 | the code associated with the first function line effectively skipping | |
bdb4c075 | 2318 | the prologue code. It works even in cases like |
ca3bf3bd DJ |
2319 | |
2320 | int main() | |
2321 | { int local_var = 1; | |
2322 | .... | |
2323 | } | |
2324 | ||
2325 | because, for this source code, both Xtensa compilers will generate two | |
2326 | separate entries ( with the same line number ) in dwarf line-number | |
2327 | section to make sure there is a boundary between the prologue code and | |
2328 | the rest of the function. | |
2329 | ||
bdb4c075 MG |
2330 | If there is no debug info, we need to analyze the code. */ |
2331 | ||
2332 | /* #define DONT_SKIP_PROLOGUE */ | |
ca3bf3bd DJ |
2333 | |
2334 | CORE_ADDR | |
2335 | xtensa_skip_prologue (CORE_ADDR start_pc) | |
2336 | { | |
bdb4c075 MG |
2337 | struct symtab_and_line prologue_sal; |
2338 | CORE_ADDR body_pc; | |
2339 | ||
ca3bf3bd DJ |
2340 | DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc); |
2341 | ||
bdb4c075 MG |
2342 | #if DONT_SKIP_PROLOGUE |
2343 | return start_pc; | |
2344 | #endif | |
2345 | ||
2346 | /* Try to find first body line from debug info. */ | |
2347 | ||
2348 | prologue_sal = find_pc_line (start_pc, 0); | |
2349 | if (prologue_sal.line != 0) /* Found debug info. */ | |
ca3bf3bd | 2350 | { |
bdb4c075 MG |
2351 | /* In Call0, it is possible to have a function with only one instruction |
2352 | ('ret') resulting from a 1-line optimized function that does nothing. | |
2353 | In that case, prologue_sal.end may actually point to the start of the | |
2354 | next function in the text section, causing a breakpoint to be set at | |
2355 | the wrong place. Check if the end address is in a different function, | |
2356 | and if so return the start PC. We know we have symbol info. */ | |
ca3bf3bd | 2357 | |
bdb4c075 MG |
2358 | CORE_ADDR end_func; |
2359 | ||
2360 | find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL); | |
2361 | if (end_func != start_pc) | |
ca3bf3bd DJ |
2362 | return start_pc; |
2363 | ||
bdb4c075 | 2364 | return prologue_sal.end; |
ca3bf3bd | 2365 | } |
ca3bf3bd | 2366 | |
bdb4c075 MG |
2367 | /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */ |
2368 | body_pc = call0_analyze_prologue(start_pc, 0, 0, NULL, NULL); | |
2369 | return body_pc != 0 ? body_pc : start_pc; | |
2370 | } | |
ca3bf3bd DJ |
2371 | |
2372 | /* Verify the current configuration. */ | |
ca3bf3bd DJ |
2373 | static void |
2374 | xtensa_verify_config (struct gdbarch *gdbarch) | |
2375 | { | |
2376 | struct ui_file *log; | |
2377 | struct cleanup *cleanups; | |
2378 | struct gdbarch_tdep *tdep; | |
2379 | long dummy; | |
2380 | char *buf; | |
2381 | ||
2382 | tdep = gdbarch_tdep (gdbarch); | |
2383 | log = mem_fileopen (); | |
2384 | cleanups = make_cleanup_ui_file_delete (log); | |
2385 | ||
2386 | /* Verify that we got a reasonable number of AREGS. */ | |
2387 | if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs) | |
bdb4c075 MG |
2388 | fprintf_unfiltered (log, _("\ |
2389 | \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"), | |
2390 | tdep->num_aregs); | |
ca3bf3bd DJ |
2391 | |
2392 | /* Verify that certain registers exist. */ | |
bdb4c075 | 2393 | |
ca3bf3bd | 2394 | if (tdep->pc_regnum == -1) |
bdb4c075 MG |
2395 | fprintf_unfiltered (log, _("\n\tpc_regnum: No PC register")); |
2396 | if (tdep->isa_use_exceptions && tdep->ps_regnum == -1) | |
2397 | fprintf_unfiltered (log, _("\n\tps_regnum: No PS register")); | |
2398 | ||
2399 | if (tdep->isa_use_windowed_registers) | |
2400 | { | |
2401 | if (tdep->wb_regnum == -1) | |
2402 | fprintf_unfiltered (log, _("\n\twb_regnum: No WB register")); | |
2403 | if (tdep->ws_regnum == -1) | |
2404 | fprintf_unfiltered (log, _("\n\tws_regnum: No WS register")); | |
2405 | if (tdep->ar_base == -1) | |
2406 | fprintf_unfiltered (log, _("\n\tar_base: No AR registers")); | |
2407 | } | |
2408 | ||
ca3bf3bd | 2409 | if (tdep->a0_base == -1) |
bdb4c075 | 2410 | fprintf_unfiltered (log, _("\n\ta0_base: No Ax registers")); |
ca3bf3bd DJ |
2411 | |
2412 | buf = ui_file_xstrdup (log, &dummy); | |
2413 | make_cleanup (xfree, buf); | |
2414 | if (strlen (buf) > 0) | |
2415 | internal_error (__FILE__, __LINE__, | |
2416 | _("the following are invalid: %s"), buf); | |
2417 | do_cleanups (cleanups); | |
2418 | } | |
2419 | ||
ca3bf3bd DJ |
2420 | /* Module "constructor" function. */ |
2421 | ||
2422 | static struct gdbarch * | |
2423 | xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2424 | { | |
2425 | struct gdbarch_tdep *tdep; | |
2426 | struct gdbarch *gdbarch; | |
2427 | struct xtensa_abi_handler *abi_handler; | |
2428 | ||
2429 | DEBUGTRACE ("gdbarch_init()\n"); | |
2430 | ||
2431 | /* We have to set the byte order before we call gdbarch_alloc. */ | |
2432 | info.byte_order = xtensa_config_byte_order (&info); | |
2433 | ||
2434 | tdep = xtensa_config_tdep (&info); | |
2435 | gdbarch = gdbarch_alloc (&info, tdep); | |
2436 | ||
2437 | /* Verify our configuration. */ | |
2438 | xtensa_verify_config (gdbarch); | |
2439 | ||
bdb4c075 | 2440 | /* Pseudo-Register read/write. */ |
ca3bf3bd DJ |
2441 | set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read); |
2442 | set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write); | |
2443 | ||
2444 | /* Set target information. */ | |
2445 | set_gdbarch_num_regs (gdbarch, tdep->num_regs); | |
2446 | set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs); | |
2447 | set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1); | |
2448 | set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum); | |
2449 | set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum); | |
2450 | ||
2451 | /* Renumber registers for known formats (stab, dwarf, and dwarf2). */ | |
2452 | set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); | |
2453 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); | |
2454 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); | |
2455 | ||
2456 | /* We provide our own function to get register information. */ | |
2457 | set_gdbarch_register_name (gdbarch, xtensa_register_name); | |
2458 | set_gdbarch_register_type (gdbarch, xtensa_register_type); | |
2459 | ||
2460 | /* To call functions from GDB using dummy frame */ | |
2461 | set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call); | |
2462 | ||
2463 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); | |
2464 | ||
2465 | set_gdbarch_return_value (gdbarch, xtensa_return_value); | |
2466 | ||
2467 | /* Advance PC across any prologue instructions to reach "real" code. */ | |
2468 | set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue); | |
2469 | ||
2470 | /* Stack grows downward. */ | |
2471 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2472 | ||
2473 | /* Set breakpoints. */ | |
2474 | set_gdbarch_breakpoint_from_pc (gdbarch, xtensa_breakpoint_from_pc); | |
2475 | ||
2476 | /* After breakpoint instruction or illegal instruction, pc still | |
2477 | points at break instruction, so don't decrement. */ | |
2478 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
2479 | ||
2480 | /* We don't skip args. */ | |
2481 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
2482 | ||
2483 | set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc); | |
2484 | ||
2485 | set_gdbarch_frame_align (gdbarch, xtensa_frame_align); | |
2486 | ||
2487 | set_gdbarch_unwind_dummy_id (gdbarch, xtensa_unwind_dummy_id); | |
2488 | ||
2489 | /* Frame handling. */ | |
2490 | frame_base_set_default (gdbarch, &xtensa_frame_base); | |
2491 | frame_unwind_append_sniffer (gdbarch, xtensa_frame_sniffer); | |
2492 | ||
2493 | set_gdbarch_print_insn (gdbarch, print_insn_xtensa); | |
2494 | ||
2495 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
2496 | ||
2497 | xtensa_add_reggroups (gdbarch); | |
2498 | set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p); | |
2499 | ||
2500 | set_gdbarch_regset_from_core_section (gdbarch, | |
2501 | xtensa_regset_from_core_section); | |
2502 | ||
2503 | return gdbarch; | |
2504 | } | |
2505 | ||
ca3bf3bd DJ |
2506 | static void |
2507 | xtensa_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
2508 | { | |
2509 | error (_("xtensa_dump_tdep(): not implemented")); | |
2510 | } | |
2511 | ||
ca3bf3bd DJ |
2512 | void |
2513 | _initialize_xtensa_tdep (void) | |
2514 | { | |
2515 | struct cmd_list_element *c; | |
2516 | ||
2517 | gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep); | |
2518 | xtensa_init_reggroups (); | |
2519 | ||
2520 | add_setshow_zinteger_cmd ("xtensa", | |
2521 | class_maintenance, | |
2522 | &xtensa_debug_level, _("\ | |
2523 | Set Xtensa debugging."), _("\ | |
2524 | Show Xtensa debugging."), _("\ | |
2525 | When non-zero, Xtensa-specific debugging is enabled. \ | |
2526 | Can be 1, 2, 3, or 4 indicating the level of debugging."), | |
2527 | NULL, | |
2528 | NULL, | |
2529 | &setdebuglist, &showdebuglist); | |
2530 | } |