Commit | Line | Data |
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ca3bf3bd DJ |
1 | /* Target-dependent code for the Xtensa port of GDB, the GNU debugger. |
2 | ||
61baf725 | 3 | Copyright (C) 2003-2017 Free Software Foundation, Inc. |
ca3bf3bd DJ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
ca3bf3bd DJ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
ca3bf3bd DJ |
19 | |
20 | #include "defs.h" | |
21 | #include "frame.h" | |
ee967b5f | 22 | #include "solib-svr4.h" |
ca3bf3bd DJ |
23 | #include "symtab.h" |
24 | #include "symfile.h" | |
25 | #include "objfiles.h" | |
26 | #include "gdbtypes.h" | |
27 | #include "gdbcore.h" | |
28 | #include "value.h" | |
29 | #include "dis-asm.h" | |
30 | #include "inferior.h" | |
40045d91 | 31 | #include "osabi.h" |
ca3bf3bd DJ |
32 | #include "regcache.h" |
33 | #include "reggroups.h" | |
34 | #include "regset.h" | |
35 | ||
36 | #include "dummy-frame.h" | |
fa8f86ff | 37 | #include "dwarf2.h" |
ca3bf3bd DJ |
38 | #include "dwarf2-frame.h" |
39 | #include "dwarf2loc.h" | |
ca3bf3bd DJ |
40 | #include "frame-base.h" |
41 | #include "frame-unwind.h" | |
42 | ||
43 | #include "arch-utils.h" | |
44 | #include "gdbarch.h" | |
45 | #include "remote.h" | |
46 | #include "serial.h" | |
47 | ||
48 | #include "command.h" | |
49 | #include "gdbcmd.h" | |
ca3bf3bd | 50 | |
bdb4c075 | 51 | #include "xtensa-isa.h" |
ca3bf3bd | 52 | #include "xtensa-tdep.h" |
94a0e877 | 53 | #include "xtensa-config.h" |
325fac50 | 54 | #include <algorithm> |
ca3bf3bd DJ |
55 | |
56 | ||
ccce17b0 | 57 | static unsigned int xtensa_debug_level = 0; |
ca3bf3bd DJ |
58 | |
59 | #define DEBUGWARN(args...) \ | |
60 | if (xtensa_debug_level > 0) \ | |
61 | fprintf_unfiltered (gdb_stdlog, "(warn ) " args) | |
62 | ||
63 | #define DEBUGINFO(args...) \ | |
64 | if (xtensa_debug_level > 1) \ | |
65 | fprintf_unfiltered (gdb_stdlog, "(info ) " args) | |
66 | ||
67 | #define DEBUGTRACE(args...) \ | |
68 | if (xtensa_debug_level > 2) \ | |
69 | fprintf_unfiltered (gdb_stdlog, "(trace) " args) | |
70 | ||
71 | #define DEBUGVERB(args...) \ | |
72 | if (xtensa_debug_level > 3) \ | |
73 | fprintf_unfiltered (gdb_stdlog, "(verb ) " args) | |
74 | ||
75 | ||
76 | /* According to the ABI, the SP must be aligned to 16-byte boundaries. */ | |
ca3bf3bd DJ |
77 | #define SP_ALIGNMENT 16 |
78 | ||
79 | ||
bdb4c075 MG |
80 | /* On Windowed ABI, we use a6 through a11 for passing arguments |
81 | to a function called by GDB because CALL4 is used. */ | |
bdb4c075 MG |
82 | #define ARGS_NUM_REGS 6 |
83 | #define REGISTER_SIZE 4 | |
ca3bf3bd | 84 | |
ca3bf3bd | 85 | |
bdb4c075 MG |
86 | /* Extract the call size from the return address or PS register. */ |
87 | #define PS_CALLINC_SHIFT 16 | |
88 | #define PS_CALLINC_MASK 0x00030000 | |
89 | #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT) | |
90 | #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3)) | |
ca3bf3bd | 91 | |
98689b25 MG |
92 | /* On TX, hardware can be configured without Exception Option. |
93 | There is no PS register in this case. Inside XT-GDB, let us treat | |
94 | it as a virtual read-only register always holding the same value. */ | |
95 | #define TX_PS 0x20 | |
96 | ||
bdb4c075 | 97 | /* ABI-independent macros. */ |
91d8eb23 MD |
98 | #define ARG_NOF(gdbarch) \ |
99 | (gdbarch_tdep (gdbarch)->call_abi \ | |
100 | == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS)) | |
101 | #define ARG_1ST(gdbarch) \ | |
102 | (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \ | |
94a0e877 | 103 | ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \ |
91d8eb23 | 104 | : (gdbarch_tdep (gdbarch)->a0_base + 6)) |
ca3bf3bd | 105 | |
ca3bf3bd DJ |
106 | /* XTENSA_IS_ENTRY tests whether the first byte of an instruction |
107 | indicates that the instruction is an ENTRY instruction. */ | |
108 | ||
91d8eb23 MD |
109 | #define XTENSA_IS_ENTRY(gdbarch, op1) \ |
110 | ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \ | |
4c6b5505 | 111 | ? ((op1) == 0x6c) : ((op1) == 0x36)) |
ca3bf3bd | 112 | |
bdb4c075 | 113 | #define XTENSA_ENTRY_LENGTH 3 |
ca3bf3bd DJ |
114 | |
115 | /* windowing_enabled() returns true, if windowing is enabled. | |
116 | WOE must be set to 1; EXCM to 0. | |
117 | Note: We assume that EXCM is always 0 for XEA1. */ | |
118 | ||
bdb4c075 MG |
119 | #define PS_WOE (1<<18) |
120 | #define PS_EXC (1<<4) | |
121 | ||
0dd5cbc5 AH |
122 | /* Big enough to hold the size of the largest register in bytes. */ |
123 | #define XTENSA_MAX_REGISTER_SIZE 64 | |
124 | ||
b801de47 | 125 | static int |
98689b25 MG |
126 | windowing_enabled (struct gdbarch *gdbarch, unsigned int ps) |
127 | { | |
128 | /* If we know CALL0 ABI is set explicitly, say it is Call0. */ | |
129 | if (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only) | |
130 | return 0; | |
131 | ||
132 | return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0); | |
133 | } | |
134 | ||
581e13c1 MS |
135 | /* Convert a live A-register number to the corresponding AR-register |
136 | number. */ | |
91d8eb23 | 137 | static int |
ee967b5f | 138 | arreg_number (struct gdbarch *gdbarch, int a_regnum, ULONGEST wb) |
91d8eb23 MD |
139 | { |
140 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
ee967b5f | 141 | int arreg; |
91d8eb23 | 142 | |
ee967b5f MG |
143 | arreg = a_regnum - tdep->a0_base; |
144 | arreg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT; | |
145 | arreg &= tdep->num_aregs - 1; | |
91d8eb23 | 146 | |
ee967b5f MG |
147 | return arreg + tdep->ar_base; |
148 | } | |
149 | ||
150 | /* Convert a live AR-register number to the corresponding A-register order | |
151 | number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */ | |
152 | static int | |
153 | areg_number (struct gdbarch *gdbarch, int ar_regnum, unsigned int wb) | |
154 | { | |
155 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
156 | int areg; | |
157 | ||
158 | areg = ar_regnum - tdep->ar_base; | |
159 | if (areg < 0 || areg >= tdep->num_aregs) | |
160 | return -1; | |
161 | areg = (areg - wb * 4) & (tdep->num_aregs - 1); | |
162 | return (areg > 15) ? -1 : areg; | |
91d8eb23 MD |
163 | } |
164 | ||
68d6df83 | 165 | /* Read Xtensa register directly from the hardware. */ |
b801de47 | 166 | static unsigned long |
08b9c608 MG |
167 | xtensa_read_register (int regnum) |
168 | { | |
169 | ULONGEST value; | |
170 | ||
171 | regcache_raw_read_unsigned (get_current_regcache (), regnum, &value); | |
172 | return (unsigned long) value; | |
173 | } | |
174 | ||
68d6df83 | 175 | /* Write Xtensa register directly to the hardware. */ |
b801de47 | 176 | static void |
08b9c608 MG |
177 | xtensa_write_register (int regnum, ULONGEST value) |
178 | { | |
179 | regcache_raw_write_unsigned (get_current_regcache (), regnum, value); | |
180 | } | |
181 | ||
ca3bf3bd DJ |
182 | /* Return the window size of the previous call to the function from which we |
183 | have just returned. | |
184 | ||
185 | This function is used to extract the return value after a called function | |
bdb4c075 | 186 | has returned to the caller. On Xtensa, the register that holds the return |
ca3bf3bd DJ |
187 | value (from the perspective of the caller) depends on what call |
188 | instruction was used. For now, we are assuming that the call instruction | |
189 | precedes the current address, so we simply analyze the call instruction. | |
190 | If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4' | |
191 | method to call the inferior function. */ | |
192 | ||
193 | static int | |
91d8eb23 | 194 | extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc) |
ca3bf3bd | 195 | { |
e17a4113 | 196 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
bdb4c075 | 197 | int winsize = 4; |
ca3bf3bd | 198 | int insn; |
ff7a4c00 | 199 | gdb_byte buf[4]; |
ca3bf3bd DJ |
200 | |
201 | DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc); | |
202 | ||
203 | /* Read the previous instruction (should be a call[x]{4|8|12}. */ | |
204 | read_memory (pc-3, buf, 3); | |
e17a4113 | 205 | insn = extract_unsigned_integer (buf, 3, byte_order); |
ca3bf3bd DJ |
206 | |
207 | /* Decode call instruction: | |
208 | Little Endian | |
209 | call{0,4,8,12} OFFSET || {00,01,10,11} || 0101 | |
210 | callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000 | |
211 | Big Endian | |
212 | call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET | |
213 | callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */ | |
214 | ||
e17a4113 | 215 | if (byte_order == BFD_ENDIAN_LITTLE) |
ca3bf3bd DJ |
216 | { |
217 | if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0)) | |
bdb4c075 | 218 | winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */ |
ca3bf3bd DJ |
219 | } |
220 | else | |
221 | { | |
222 | if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03)) | |
bdb4c075 | 223 | winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */ |
ca3bf3bd DJ |
224 | } |
225 | return winsize; | |
226 | } | |
227 | ||
228 | ||
229 | /* REGISTER INFORMATION */ | |
230 | ||
08b9c608 MG |
231 | /* Find register by name. */ |
232 | static int | |
a121b7c1 | 233 | xtensa_find_register_by_name (struct gdbarch *gdbarch, const char *name) |
08b9c608 MG |
234 | { |
235 | int i; | |
236 | ||
237 | for (i = 0; i < gdbarch_num_regs (gdbarch) | |
238 | + gdbarch_num_pseudo_regs (gdbarch); | |
239 | i++) | |
240 | ||
241 | if (strcasecmp (gdbarch_tdep (gdbarch)->regmap[i].name, name) == 0) | |
242 | return i; | |
243 | ||
244 | return -1; | |
245 | } | |
246 | ||
ca3bf3bd | 247 | /* Returns the name of a register. */ |
ca3bf3bd | 248 | static const char * |
d93859e2 | 249 | xtensa_register_name (struct gdbarch *gdbarch, int regnum) |
ca3bf3bd DJ |
250 | { |
251 | /* Return the name stored in the register map. */ | |
d93859e2 UW |
252 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch) |
253 | + gdbarch_num_pseudo_regs (gdbarch)) | |
254 | return gdbarch_tdep (gdbarch)->regmap[regnum].name; | |
ca3bf3bd | 255 | |
ca3bf3bd DJ |
256 | internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum); |
257 | return 0; | |
258 | } | |
259 | ||
ca3bf3bd DJ |
260 | /* Return the type of a register. Create a new type, if necessary. */ |
261 | ||
ca3bf3bd DJ |
262 | static struct type * |
263 | xtensa_register_type (struct gdbarch *gdbarch, int regnum) | |
264 | { | |
df4df182 UW |
265 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
266 | ||
ca3bf3bd | 267 | /* Return signed integer for ARx and Ax registers. */ |
df4df182 UW |
268 | if ((regnum >= tdep->ar_base |
269 | && regnum < tdep->ar_base + tdep->num_aregs) | |
270 | || (regnum >= tdep->a0_base | |
271 | && regnum < tdep->a0_base + 16)) | |
0dfff4cb | 272 | return builtin_type (gdbarch)->builtin_int; |
ca3bf3bd | 273 | |
6b50c0b0 | 274 | if (regnum == gdbarch_pc_regnum (gdbarch) |
df4df182 | 275 | || regnum == tdep->a0_base + 1) |
fde6c819 | 276 | return builtin_type (gdbarch)->builtin_data_ptr; |
ca3bf3bd DJ |
277 | |
278 | /* Return the stored type for all other registers. */ | |
6b50c0b0 UW |
279 | else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch) |
280 | + gdbarch_num_pseudo_regs (gdbarch)) | |
ca3bf3bd | 281 | { |
df4df182 | 282 | xtensa_register_t* reg = &tdep->regmap[regnum]; |
ca3bf3bd | 283 | |
bdb4c075 | 284 | /* Set ctype for this register (only the first time). */ |
ca3bf3bd DJ |
285 | |
286 | if (reg->ctype == 0) | |
287 | { | |
288 | struct ctype_cache *tp; | |
289 | int size = reg->byte_size; | |
290 | ||
bdb4c075 MG |
291 | /* We always use the memory representation, |
292 | even if the register width is smaller. */ | |
ca3bf3bd DJ |
293 | switch (size) |
294 | { | |
295 | case 1: | |
df4df182 | 296 | reg->ctype = builtin_type (gdbarch)->builtin_uint8; |
ca3bf3bd DJ |
297 | break; |
298 | ||
299 | case 2: | |
df4df182 | 300 | reg->ctype = builtin_type (gdbarch)->builtin_uint16; |
ca3bf3bd DJ |
301 | break; |
302 | ||
303 | case 4: | |
df4df182 | 304 | reg->ctype = builtin_type (gdbarch)->builtin_uint32; |
ca3bf3bd DJ |
305 | break; |
306 | ||
307 | case 8: | |
df4df182 | 308 | reg->ctype = builtin_type (gdbarch)->builtin_uint64; |
ca3bf3bd DJ |
309 | break; |
310 | ||
311 | case 16: | |
df4df182 | 312 | reg->ctype = builtin_type (gdbarch)->builtin_uint128; |
ca3bf3bd DJ |
313 | break; |
314 | ||
315 | default: | |
df4df182 | 316 | for (tp = tdep->type_entries; tp != NULL; tp = tp->next) |
ca3bf3bd DJ |
317 | if (tp->size == size) |
318 | break; | |
319 | ||
320 | if (tp == NULL) | |
321 | { | |
1448a0a2 | 322 | char *name = xstrprintf ("int%d", size * 8); |
8d749320 SM |
323 | |
324 | tp = XNEW (struct ctype_cache); | |
df4df182 UW |
325 | tp->next = tdep->type_entries; |
326 | tdep->type_entries = tp; | |
ca3bf3bd | 327 | tp->size = size; |
e9bb382b | 328 | tp->virtual_type |
1448a0a2 PM |
329 | = arch_integer_type (gdbarch, size * 8, 1, name); |
330 | xfree (name); | |
ca3bf3bd DJ |
331 | } |
332 | ||
333 | reg->ctype = tp->virtual_type; | |
334 | } | |
335 | } | |
336 | return reg->ctype; | |
337 | } | |
338 | ||
ca3bf3bd DJ |
339 | internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum); |
340 | return 0; | |
341 | } | |
342 | ||
343 | ||
bdb4c075 | 344 | /* Return the 'local' register number for stubs, dwarf2, etc. |
ca3bf3bd DJ |
345 | The debugging information enumerates registers starting from 0 for A0 |
346 | to n for An. So, we only have to add the base number for A0. */ | |
347 | ||
348 | static int | |
d3f73121 | 349 | xtensa_reg_to_regnum (struct gdbarch *gdbarch, int regnum) |
ca3bf3bd DJ |
350 | { |
351 | int i; | |
352 | ||
353 | if (regnum >= 0 && regnum < 16) | |
d3f73121 | 354 | return gdbarch_tdep (gdbarch)->a0_base + regnum; |
ca3bf3bd | 355 | |
f57d151a | 356 | for (i = 0; |
d3f73121 | 357 | i < gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
f57d151a | 358 | i++) |
d3f73121 | 359 | if (regnum == gdbarch_tdep (gdbarch)->regmap[i].target_number) |
ca3bf3bd DJ |
360 | return i; |
361 | ||
0fde2c53 | 362 | return -1; |
ca3bf3bd DJ |
363 | } |
364 | ||
365 | ||
bdb4c075 MG |
366 | /* Write the bits of a masked register to the various registers. |
367 | Only the masked areas of these registers are modified; the other | |
368 | fields are untouched. The size of masked registers is always less | |
369 | than or equal to 32 bits. */ | |
ca3bf3bd DJ |
370 | |
371 | static void | |
9c9acae0 UW |
372 | xtensa_register_write_masked (struct regcache *regcache, |
373 | xtensa_register_t *reg, const gdb_byte *buffer) | |
ca3bf3bd | 374 | { |
0dd5cbc5 | 375 | unsigned int value[(XTENSA_MAX_REGISTER_SIZE + 3) / 4]; |
ca3bf3bd DJ |
376 | const xtensa_mask_t *mask = reg->mask; |
377 | ||
378 | int shift = 0; /* Shift for next mask (mod 32). */ | |
379 | int start, size; /* Start bit and size of current mask. */ | |
380 | ||
381 | unsigned int *ptr = value; | |
382 | unsigned int regval, m, mem = 0; | |
383 | ||
384 | int bytesize = reg->byte_size; | |
385 | int bitsize = bytesize * 8; | |
386 | int i, r; | |
387 | ||
388 | DEBUGTRACE ("xtensa_register_write_masked ()\n"); | |
389 | ||
390 | /* Copy the masked register to host byte-order. */ | |
6b50c0b0 | 391 | if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
392 | for (i = 0; i < bytesize; i++) |
393 | { | |
394 | mem >>= 8; | |
395 | mem |= (buffer[bytesize - i - 1] << 24); | |
396 | if ((i & 3) == 3) | |
397 | *ptr++ = mem; | |
398 | } | |
399 | else | |
400 | for (i = 0; i < bytesize; i++) | |
401 | { | |
402 | mem >>= 8; | |
403 | mem |= (buffer[i] << 24); | |
404 | if ((i & 3) == 3) | |
405 | *ptr++ = mem; | |
406 | } | |
407 | ||
408 | /* We might have to shift the final value: | |
409 | bytesize & 3 == 0 -> nothing to do, we use the full 32 bits, | |
410 | bytesize & 3 == x -> shift (4-x) * 8. */ | |
411 | ||
412 | *ptr = mem >> (((0 - bytesize) & 3) * 8); | |
413 | ptr = value; | |
414 | mem = *ptr; | |
415 | ||
416 | /* Write the bits to the masked areas of the other registers. */ | |
417 | for (i = 0; i < mask->count; i++) | |
418 | { | |
419 | start = mask->mask[i].bit_start; | |
420 | size = mask->mask[i].bit_size; | |
421 | regval = mem >> shift; | |
422 | ||
423 | if ((shift += size) > bitsize) | |
424 | error (_("size of all masks is larger than the register")); | |
425 | ||
426 | if (shift >= 32) | |
427 | { | |
428 | mem = *(++ptr); | |
429 | shift -= 32; | |
430 | bitsize -= 32; | |
431 | ||
432 | if (shift > 0) | |
433 | regval |= mem << (size - shift); | |
434 | } | |
435 | ||
436 | /* Make sure we have a valid register. */ | |
437 | r = mask->mask[i].reg_num; | |
438 | if (r >= 0 && size > 0) | |
439 | { | |
440 | /* Don't overwrite the unmasked areas. */ | |
9c9acae0 UW |
441 | ULONGEST old_val; |
442 | regcache_cooked_read_unsigned (regcache, r, &old_val); | |
ca3bf3bd DJ |
443 | m = 0xffffffff >> (32 - size) << start; |
444 | regval <<= start; | |
9c9acae0 UW |
445 | regval = (regval & m) | (old_val & ~m); |
446 | regcache_cooked_write_unsigned (regcache, r, regval); | |
ca3bf3bd DJ |
447 | } |
448 | } | |
449 | } | |
450 | ||
451 | ||
bdb4c075 MG |
452 | /* Read a tie state or mapped registers. Read the masked areas |
453 | of the registers and assemble them into a single value. */ | |
ca3bf3bd | 454 | |
05d1431c | 455 | static enum register_status |
9c9acae0 UW |
456 | xtensa_register_read_masked (struct regcache *regcache, |
457 | xtensa_register_t *reg, gdb_byte *buffer) | |
ca3bf3bd | 458 | { |
0dd5cbc5 | 459 | unsigned int value[(XTENSA_MAX_REGISTER_SIZE + 3) / 4]; |
ca3bf3bd DJ |
460 | const xtensa_mask_t *mask = reg->mask; |
461 | ||
462 | int shift = 0; | |
463 | int start, size; | |
464 | ||
465 | unsigned int *ptr = value; | |
466 | unsigned int regval, mem = 0; | |
467 | ||
468 | int bytesize = reg->byte_size; | |
469 | int bitsize = bytesize * 8; | |
470 | int i; | |
471 | ||
472 | DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n", | |
473 | reg->name == 0 ? "" : reg->name); | |
474 | ||
475 | /* Assemble the register from the masked areas of other registers. */ | |
476 | for (i = 0; i < mask->count; i++) | |
477 | { | |
478 | int r = mask->mask[i].reg_num; | |
9c9acae0 UW |
479 | if (r >= 0) |
480 | { | |
05d1431c | 481 | enum register_status status; |
9c9acae0 | 482 | ULONGEST val; |
05d1431c PA |
483 | |
484 | status = regcache_cooked_read_unsigned (regcache, r, &val); | |
485 | if (status != REG_VALID) | |
486 | return status; | |
9c9acae0 UW |
487 | regval = (unsigned int) val; |
488 | } | |
489 | else | |
490 | regval = 0; | |
491 | ||
ca3bf3bd DJ |
492 | start = mask->mask[i].bit_start; |
493 | size = mask->mask[i].bit_size; | |
494 | ||
495 | regval >>= start; | |
496 | ||
497 | if (size < 32) | |
498 | regval &= (0xffffffff >> (32 - size)); | |
499 | ||
500 | mem |= regval << shift; | |
501 | ||
502 | if ((shift += size) > bitsize) | |
503 | error (_("size of all masks is larger than the register")); | |
504 | ||
505 | if (shift >= 32) | |
506 | { | |
507 | *ptr++ = mem; | |
508 | bitsize -= 32; | |
509 | shift -= 32; | |
510 | ||
511 | if (shift == 0) | |
512 | mem = 0; | |
513 | else | |
514 | mem = regval >> (size - shift); | |
515 | } | |
516 | } | |
517 | ||
518 | if (shift > 0) | |
519 | *ptr = mem; | |
520 | ||
521 | /* Copy value to target byte order. */ | |
522 | ptr = value; | |
523 | mem = *ptr; | |
524 | ||
6b50c0b0 | 525 | if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
526 | for (i = 0; i < bytesize; i++) |
527 | { | |
528 | if ((i & 3) == 0) | |
529 | mem = *ptr++; | |
530 | buffer[bytesize - i - 1] = mem & 0xff; | |
531 | mem >>= 8; | |
532 | } | |
533 | else | |
534 | for (i = 0; i < bytesize; i++) | |
535 | { | |
536 | if ((i & 3) == 0) | |
537 | mem = *ptr++; | |
538 | buffer[i] = mem & 0xff; | |
539 | mem >>= 8; | |
540 | } | |
05d1431c PA |
541 | |
542 | return REG_VALID; | |
ca3bf3bd DJ |
543 | } |
544 | ||
545 | ||
546 | /* Read pseudo registers. */ | |
547 | ||
05d1431c | 548 | static enum register_status |
ca3bf3bd DJ |
549 | xtensa_pseudo_register_read (struct gdbarch *gdbarch, |
550 | struct regcache *regcache, | |
551 | int regnum, | |
552 | gdb_byte *buffer) | |
553 | { | |
e17a4113 UW |
554 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
555 | ||
ca3bf3bd | 556 | DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n", |
d93859e2 | 557 | regnum, xtensa_register_name (gdbarch, regnum)); |
ca3bf3bd | 558 | |
bdb4c075 | 559 | /* Read aliases a0..a15, if this is a Windowed ABI. */ |
6b50c0b0 | 560 | if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers |
94a0e877 | 561 | && (regnum >= gdbarch_tdep (gdbarch)->a0_base) |
6b50c0b0 | 562 | && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)) |
ca3bf3bd | 563 | { |
c185f580 | 564 | ULONGEST value; |
05d1431c | 565 | enum register_status status; |
ca3bf3bd | 566 | |
c185f580 AH |
567 | status = regcache_raw_read_unsigned (regcache, |
568 | gdbarch_tdep (gdbarch)->wb_regnum, | |
569 | &value); | |
05d1431c PA |
570 | if (status != REG_VALID) |
571 | return status; | |
c185f580 | 572 | regnum = arreg_number (gdbarch, regnum, value); |
ca3bf3bd DJ |
573 | } |
574 | ||
bdb4c075 | 575 | /* We can always read non-pseudo registers. */ |
6b50c0b0 | 576 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) |
05d1431c | 577 | return regcache_raw_read (regcache, regnum, buffer); |
94a0e877 MG |
578 | |
579 | /* We have to find out how to deal with priveleged registers. | |
580 | Let's treat them as pseudo-registers, but we cannot read/write them. */ | |
581 | ||
0d0bf81a MF |
582 | else if (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only |
583 | || regnum < gdbarch_tdep (gdbarch)->a0_base) | |
94a0e877 MG |
584 | { |
585 | buffer[0] = (gdb_byte)0; | |
586 | buffer[1] = (gdb_byte)0; | |
587 | buffer[2] = (gdb_byte)0; | |
588 | buffer[3] = (gdb_byte)0; | |
05d1431c | 589 | return REG_VALID; |
94a0e877 | 590 | } |
ca3bf3bd | 591 | /* Pseudo registers. */ |
f57d151a | 592 | else if (regnum >= 0 |
6b50c0b0 UW |
593 | && regnum < gdbarch_num_regs (gdbarch) |
594 | + gdbarch_num_pseudo_regs (gdbarch)) | |
ca3bf3bd | 595 | { |
6b50c0b0 | 596 | xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; |
ca3bf3bd | 597 | xtensa_register_type_t type = reg->type; |
6b50c0b0 | 598 | int flags = gdbarch_tdep (gdbarch)->target_flags; |
ca3bf3bd | 599 | |
bdb4c075 | 600 | /* We cannot read Unknown or Unmapped registers. */ |
ca3bf3bd DJ |
601 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) |
602 | { | |
603 | if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
604 | { | |
605 | warning (_("cannot read register %s"), | |
d93859e2 | 606 | xtensa_register_name (gdbarch, regnum)); |
05d1431c | 607 | return REG_VALID; |
ca3bf3bd DJ |
608 | } |
609 | } | |
610 | ||
611 | /* Some targets cannot read TIE register files. */ | |
612 | else if (type == xtRegisterTypeTieRegfile) | |
613 | { | |
614 | /* Use 'fetch' to get register? */ | |
615 | if (flags & xtTargetFlagsUseFetchStore) | |
616 | { | |
617 | warning (_("cannot read register")); | |
05d1431c | 618 | return REG_VALID; |
ca3bf3bd DJ |
619 | } |
620 | ||
621 | /* On some targets (esp. simulators), we can always read the reg. */ | |
622 | else if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
623 | { | |
624 | warning (_("cannot read register")); | |
05d1431c | 625 | return REG_VALID; |
ca3bf3bd DJ |
626 | } |
627 | } | |
628 | ||
629 | /* We can always read mapped registers. */ | |
630 | else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState) | |
05d1431c | 631 | return xtensa_register_read_masked (regcache, reg, buffer); |
ca3bf3bd DJ |
632 | |
633 | /* Assume that we can read the register. */ | |
05d1431c | 634 | return regcache_raw_read (regcache, regnum, buffer); |
ca3bf3bd | 635 | } |
ca3bf3bd DJ |
636 | else |
637 | internal_error (__FILE__, __LINE__, | |
638 | _("invalid register number %d"), regnum); | |
639 | } | |
640 | ||
641 | ||
642 | /* Write pseudo registers. */ | |
643 | ||
644 | static void | |
645 | xtensa_pseudo_register_write (struct gdbarch *gdbarch, | |
646 | struct regcache *regcache, | |
647 | int regnum, | |
648 | const gdb_byte *buffer) | |
649 | { | |
e17a4113 UW |
650 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
651 | ||
ca3bf3bd | 652 | DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n", |
d93859e2 | 653 | regnum, xtensa_register_name (gdbarch, regnum)); |
ca3bf3bd | 654 | |
bdb4c075 | 655 | /* Renumber register, if aliase a0..a15 on Windowed ABI. */ |
6b50c0b0 | 656 | if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers |
94a0e877 | 657 | && (regnum >= gdbarch_tdep (gdbarch)->a0_base) |
6b50c0b0 | 658 | && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)) |
ca3bf3bd | 659 | { |
c185f580 AH |
660 | ULONGEST value; |
661 | regcache_raw_read_unsigned (regcache, | |
662 | gdbarch_tdep (gdbarch)->wb_regnum, &value); | |
663 | regnum = arreg_number (gdbarch, regnum, value); | |
ca3bf3bd DJ |
664 | } |
665 | ||
666 | /* We can always write 'core' registers. | |
667 | Note: We might have converted Ax->ARy. */ | |
6b50c0b0 | 668 | if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) |
ca3bf3bd DJ |
669 | regcache_raw_write (regcache, regnum, buffer); |
670 | ||
94a0e877 MG |
671 | /* We have to find out how to deal with priveleged registers. |
672 | Let's treat them as pseudo-registers, but we cannot read/write them. */ | |
673 | ||
674 | else if (regnum < gdbarch_tdep (gdbarch)->a0_base) | |
675 | { | |
676 | return; | |
677 | } | |
ca3bf3bd | 678 | /* Pseudo registers. */ |
f57d151a | 679 | else if (regnum >= 0 |
6b50c0b0 UW |
680 | && regnum < gdbarch_num_regs (gdbarch) |
681 | + gdbarch_num_pseudo_regs (gdbarch)) | |
ca3bf3bd | 682 | { |
6b50c0b0 | 683 | xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; |
ca3bf3bd | 684 | xtensa_register_type_t type = reg->type; |
6b50c0b0 | 685 | int flags = gdbarch_tdep (gdbarch)->target_flags; |
ca3bf3bd | 686 | |
bdb4c075 MG |
687 | /* On most targets, we cannot write registers |
688 | of type "Unknown" or "Unmapped". */ | |
ca3bf3bd DJ |
689 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) |
690 | { | |
691 | if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
692 | { | |
693 | warning (_("cannot write register %s"), | |
d93859e2 | 694 | xtensa_register_name (gdbarch, regnum)); |
ca3bf3bd DJ |
695 | return; |
696 | } | |
697 | } | |
698 | ||
699 | /* Some targets cannot read TIE register files. */ | |
700 | else if (type == xtRegisterTypeTieRegfile) | |
701 | { | |
702 | /* Use 'store' to get register? */ | |
703 | if (flags & xtTargetFlagsUseFetchStore) | |
704 | { | |
705 | warning (_("cannot write register")); | |
706 | return; | |
707 | } | |
708 | ||
709 | /* On some targets (esp. simulators), we can always write | |
710 | the register. */ | |
ca3bf3bd DJ |
711 | else if ((flags & xtTargetFlagsNonVisibleRegs) == 0) |
712 | { | |
713 | warning (_("cannot write register")); | |
714 | return; | |
715 | } | |
716 | } | |
717 | ||
718 | /* We can always write mapped registers. */ | |
719 | else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState) | |
720 | { | |
9c9acae0 | 721 | xtensa_register_write_masked (regcache, reg, buffer); |
ca3bf3bd DJ |
722 | return; |
723 | } | |
724 | ||
725 | /* Assume that we can write the register. */ | |
726 | regcache_raw_write (regcache, regnum, buffer); | |
727 | } | |
ca3bf3bd DJ |
728 | else |
729 | internal_error (__FILE__, __LINE__, | |
730 | _("invalid register number %d"), regnum); | |
731 | } | |
732 | ||
ca3bf3bd DJ |
733 | static struct reggroup *xtensa_ar_reggroup; |
734 | static struct reggroup *xtensa_user_reggroup; | |
735 | static struct reggroup *xtensa_vectra_reggroup; | |
7b871568 | 736 | static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR]; |
ca3bf3bd DJ |
737 | |
738 | static void | |
739 | xtensa_init_reggroups (void) | |
740 | { | |
98689b25 | 741 | int i; |
98689b25 | 742 | |
ca3bf3bd DJ |
743 | xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP); |
744 | xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP); | |
745 | xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP); | |
ca3bf3bd | 746 | |
98689b25 | 747 | for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++) |
9c3cc999 | 748 | xtensa_cp[i] = reggroup_new (xstrprintf ("cp%d", i), USER_REGGROUP); |
7b871568 | 749 | } |
ca3bf3bd DJ |
750 | |
751 | static void | |
752 | xtensa_add_reggroups (struct gdbarch *gdbarch) | |
753 | { | |
7b871568 MG |
754 | int i; |
755 | ||
756 | /* Predefined groups. */ | |
ca3bf3bd DJ |
757 | reggroup_add (gdbarch, all_reggroup); |
758 | reggroup_add (gdbarch, save_reggroup); | |
759 | reggroup_add (gdbarch, restore_reggroup); | |
760 | reggroup_add (gdbarch, system_reggroup); | |
7b871568 MG |
761 | reggroup_add (gdbarch, vector_reggroup); |
762 | reggroup_add (gdbarch, general_reggroup); | |
763 | reggroup_add (gdbarch, float_reggroup); | |
764 | ||
765 | /* Xtensa-specific groups. */ | |
766 | reggroup_add (gdbarch, xtensa_ar_reggroup); | |
767 | reggroup_add (gdbarch, xtensa_user_reggroup); | |
768 | reggroup_add (gdbarch, xtensa_vectra_reggroup); | |
ca3bf3bd | 769 | |
7b871568 MG |
770 | for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++) |
771 | reggroup_add (gdbarch, xtensa_cp[i]); | |
ca3bf3bd DJ |
772 | } |
773 | ||
7b871568 MG |
774 | static int |
775 | xtensa_coprocessor_register_group (struct reggroup *group) | |
776 | { | |
777 | int i; | |
778 | ||
779 | for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++) | |
780 | if (group == xtensa_cp[i]) | |
781 | return i; | |
782 | ||
783 | return -1; | |
784 | } | |
ca3bf3bd DJ |
785 | |
786 | #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \ | |
787 | | XTENSA_REGISTER_FLAGS_WRITABLE \ | |
788 | | XTENSA_REGISTER_FLAGS_VOLATILE) | |
789 | ||
790 | #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \ | |
791 | | XTENSA_REGISTER_FLAGS_WRITABLE) | |
792 | ||
793 | static int | |
794 | xtensa_register_reggroup_p (struct gdbarch *gdbarch, | |
795 | int regnum, | |
796 | struct reggroup *group) | |
797 | { | |
6b50c0b0 | 798 | xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum]; |
ca3bf3bd DJ |
799 | xtensa_register_type_t type = reg->type; |
800 | xtensa_register_group_t rg = reg->group; | |
7b871568 | 801 | int cp_number; |
ca3bf3bd | 802 | |
57041825 MG |
803 | if (group == save_reggroup) |
804 | /* Every single register should be included into the list of registers | |
805 | to be watched for changes while using -data-list-changed-registers. */ | |
806 | return 1; | |
807 | ||
ca3bf3bd DJ |
808 | /* First, skip registers that are not visible to this target |
809 | (unknown and unmapped registers when not using ISS). */ | |
810 | ||
811 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) | |
812 | return 0; | |
813 | if (group == all_reggroup) | |
814 | return 1; | |
815 | if (group == xtensa_ar_reggroup) | |
816 | return rg & xtRegisterGroupAddrReg; | |
817 | if (group == xtensa_user_reggroup) | |
818 | return rg & xtRegisterGroupUser; | |
819 | if (group == float_reggroup) | |
820 | return rg & xtRegisterGroupFloat; | |
821 | if (group == general_reggroup) | |
822 | return rg & xtRegisterGroupGeneral; | |
ca3bf3bd DJ |
823 | if (group == system_reggroup) |
824 | return rg & xtRegisterGroupState; | |
825 | if (group == vector_reggroup || group == xtensa_vectra_reggroup) | |
826 | return rg & xtRegisterGroupVectra; | |
57041825 | 827 | if (group == restore_reggroup) |
6b50c0b0 | 828 | return (regnum < gdbarch_num_regs (gdbarch) |
ca3bf3bd | 829 | && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID); |
1448a0a2 PM |
830 | cp_number = xtensa_coprocessor_register_group (group); |
831 | if (cp_number >= 0) | |
7b871568 | 832 | return rg & (xtRegisterGroupCP0 << cp_number); |
ca3bf3bd DJ |
833 | else |
834 | return 1; | |
835 | } | |
836 | ||
837 | ||
ca3bf3bd DJ |
838 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
839 | in the general-purpose register set REGSET to register cache | |
bdb4c075 | 840 | REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */ |
ca3bf3bd DJ |
841 | |
842 | static void | |
843 | xtensa_supply_gregset (const struct regset *regset, | |
844 | struct regcache *rc, | |
845 | int regnum, | |
846 | const void *gregs, | |
847 | size_t len) | |
848 | { | |
19ba03f4 | 849 | const xtensa_elf_gregset_t *regs = (const xtensa_elf_gregset_t *) gregs; |
6b50c0b0 | 850 | struct gdbarch *gdbarch = get_regcache_arch (rc); |
ca3bf3bd DJ |
851 | int i; |
852 | ||
cce7e648 | 853 | DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum); |
ca3bf3bd | 854 | |
6b50c0b0 UW |
855 | if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1) |
856 | regcache_raw_supply (rc, gdbarch_pc_regnum (gdbarch), (char *) ®s->pc); | |
857 | if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1) | |
858 | regcache_raw_supply (rc, gdbarch_ps_regnum (gdbarch), (char *) ®s->ps); | |
859 | if (regnum == gdbarch_tdep (gdbarch)->wb_regnum || regnum == -1) | |
860 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->wb_regnum, | |
304fe255 | 861 | (char *) ®s->windowbase); |
6b50c0b0 UW |
862 | if (regnum == gdbarch_tdep (gdbarch)->ws_regnum || regnum == -1) |
863 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ws_regnum, | |
304fe255 | 864 | (char *) ®s->windowstart); |
6b50c0b0 UW |
865 | if (regnum == gdbarch_tdep (gdbarch)->lbeg_regnum || regnum == -1) |
866 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lbeg_regnum, | |
304fe255 | 867 | (char *) ®s->lbeg); |
6b50c0b0 UW |
868 | if (regnum == gdbarch_tdep (gdbarch)->lend_regnum || regnum == -1) |
869 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lend_regnum, | |
304fe255 | 870 | (char *) ®s->lend); |
6b50c0b0 UW |
871 | if (regnum == gdbarch_tdep (gdbarch)->lcount_regnum || regnum == -1) |
872 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lcount_regnum, | |
304fe255 | 873 | (char *) ®s->lcount); |
6b50c0b0 UW |
874 | if (regnum == gdbarch_tdep (gdbarch)->sar_regnum || regnum == -1) |
875 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->sar_regnum, | |
304fe255 | 876 | (char *) ®s->sar); |
6b50c0b0 UW |
877 | if (regnum >=gdbarch_tdep (gdbarch)->ar_base |
878 | && regnum < gdbarch_tdep (gdbarch)->ar_base | |
879 | + gdbarch_tdep (gdbarch)->num_aregs) | |
304fe255 UW |
880 | regcache_raw_supply (rc, regnum, |
881 | (char *) ®s->ar[regnum - gdbarch_tdep | |
6b50c0b0 | 882 | (gdbarch)->ar_base]); |
ca3bf3bd DJ |
883 | else if (regnum == -1) |
884 | { | |
6b50c0b0 UW |
885 | for (i = 0; i < gdbarch_tdep (gdbarch)->num_aregs; ++i) |
886 | regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ar_base + i, | |
304fe255 | 887 | (char *) ®s->ar[i]); |
ca3bf3bd DJ |
888 | } |
889 | } | |
890 | ||
891 | ||
892 | /* Xtensa register set. */ | |
893 | ||
894 | static struct regset | |
895 | xtensa_gregset = | |
896 | { | |
897 | NULL, | |
898 | xtensa_supply_gregset | |
899 | }; | |
900 | ||
901 | ||
97094034 | 902 | /* Iterate over supported core file register note sections. */ |
ca3bf3bd | 903 | |
97094034 AA |
904 | static void |
905 | xtensa_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
906 | iterate_over_regset_sections_cb *cb, | |
907 | void *cb_data, | |
908 | const struct regcache *regcache) | |
ca3bf3bd | 909 | { |
97094034 | 910 | DEBUGTRACE ("xtensa_iterate_over_regset_sections\n"); |
ca3bf3bd | 911 | |
97094034 AA |
912 | cb (".reg", sizeof (xtensa_elf_gregset_t), &xtensa_gregset, |
913 | NULL, cb_data); | |
ca3bf3bd DJ |
914 | } |
915 | ||
916 | ||
bdb4c075 | 917 | /* Handling frames. */ |
ca3bf3bd | 918 | |
bdb4c075 MG |
919 | /* Number of registers to save in case of Windowed ABI. */ |
920 | #define XTENSA_NUM_SAVED_AREGS 12 | |
ca3bf3bd | 921 | |
bdb4c075 MG |
922 | /* Frame cache part for Windowed ABI. */ |
923 | typedef struct xtensa_windowed_frame_cache | |
ca3bf3bd | 924 | { |
ee967b5f MG |
925 | int wb; /* WINDOWBASE of the previous frame. */ |
926 | int callsize; /* Call size of this frame. */ | |
08b9c608 MG |
927 | int ws; /* WINDOWSTART of the previous frame. It keeps track of |
928 | life windows only. If there is no bit set for the | |
929 | window, that means it had been already spilled | |
930 | because of window overflow. */ | |
931 | ||
932 | /* Addresses of spilled A-registers. | |
933 | AREGS[i] == -1, if corresponding AR is alive. */ | |
ca3bf3bd | 934 | CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS]; |
bdb4c075 MG |
935 | } xtensa_windowed_frame_cache_t; |
936 | ||
937 | /* Call0 ABI Definitions. */ | |
938 | ||
581e13c1 MS |
939 | #define C0_MAXOPDS 3 /* Maximum number of operands for prologue |
940 | analysis. */ | |
bdb4c075 MG |
941 | #define C0_CLESV 12 /* Callee-saved registers are here and up. */ |
942 | #define C0_SP 1 /* Register used as SP. */ | |
943 | #define C0_FP 15 /* Register used as FP. */ | |
944 | #define C0_RA 0 /* Register used as return address. */ | |
945 | #define C0_ARGS 2 /* Register used as first arg/retval. */ | |
946 | #define C0_NARGS 6 /* Number of A-regs for args/retvals. */ | |
947 | ||
948 | /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each | |
949 | A-register where the current content of the reg came from (in terms | |
950 | of an original reg and a constant). Negative values of c0_rt[n].fp_reg | |
951 | mean that the orignal content of the register was saved to the stack. | |
952 | c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't | |
953 | know where SP will end up until the entire prologue has been analyzed. */ | |
954 | ||
955 | #define C0_CONST -1 /* fr_reg value if register contains a constant. */ | |
956 | #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */ | |
957 | #define C0_NOSTK -1 /* to_stk value if register has not been stored. */ | |
958 | ||
959 | extern xtensa_isa xtensa_default_isa; | |
960 | ||
961 | typedef struct xtensa_c0reg | |
962 | { | |
dbab50de MG |
963 | int fr_reg; /* original register from which register content |
964 | is derived, or C0_CONST, or C0_INEXP. */ | |
965 | int fr_ofs; /* constant offset from reg, or immediate value. */ | |
966 | int to_stk; /* offset from original SP to register (4-byte aligned), | |
967 | or C0_NOSTK if register has not been saved. */ | |
bdb4c075 MG |
968 | } xtensa_c0reg_t; |
969 | ||
bdb4c075 MG |
970 | /* Frame cache part for Call0 ABI. */ |
971 | typedef struct xtensa_call0_frame_cache | |
972 | { | |
dbab50de MG |
973 | int c0_frmsz; /* Stack frame size. */ |
974 | int c0_hasfp; /* Current frame uses frame pointer. */ | |
975 | int fp_regnum; /* A-register used as FP. */ | |
976 | int c0_fp; /* Actual value of frame pointer. */ | |
977 | int c0_fpalign; /* Dinamic adjustment for the stack | |
978 | pointer. It's an AND mask. Zero, | |
979 | if alignment was not adjusted. */ | |
980 | int c0_old_sp; /* In case of dynamic adjustment, it is | |
981 | a register holding unaligned sp. | |
982 | C0_INEXP, when undefined. */ | |
983 | int c0_sp_ofs; /* If "c0_old_sp" was spilled it's a | |
984 | stack offset. C0_NOSTK otherwise. */ | |
985 | ||
986 | xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */ | |
bdb4c075 MG |
987 | } xtensa_call0_frame_cache_t; |
988 | ||
989 | typedef struct xtensa_frame_cache | |
990 | { | |
ee967b5f | 991 | CORE_ADDR base; /* Stack pointer of this frame. */ |
08b9c608 MG |
992 | CORE_ADDR pc; /* PC of this frame at the function entry point. */ |
993 | CORE_ADDR ra; /* The raw return address of this frame. */ | |
994 | CORE_ADDR ps; /* The PS register of the previous (older) frame. */ | |
995 | CORE_ADDR prev_sp; /* Stack Pointer of the previous (older) frame. */ | |
bdb4c075 MG |
996 | int call0; /* It's a call0 framework (else windowed). */ |
997 | union | |
998 | { | |
999 | xtensa_windowed_frame_cache_t wd; /* call0 == false. */ | |
1000 | xtensa_call0_frame_cache_t c0; /* call0 == true. */ | |
1001 | }; | |
ca3bf3bd DJ |
1002 | } xtensa_frame_cache_t; |
1003 | ||
1004 | ||
1005 | static struct xtensa_frame_cache * | |
bdb4c075 | 1006 | xtensa_alloc_frame_cache (int windowed) |
ca3bf3bd DJ |
1007 | { |
1008 | xtensa_frame_cache_t *cache; | |
1009 | int i; | |
1010 | ||
1011 | DEBUGTRACE ("xtensa_alloc_frame_cache ()\n"); | |
1012 | ||
1013 | cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t); | |
1014 | ||
1015 | cache->base = 0; | |
1016 | cache->pc = 0; | |
1017 | cache->ra = 0; | |
ca3bf3bd | 1018 | cache->ps = 0; |
ca3bf3bd | 1019 | cache->prev_sp = 0; |
bdb4c075 MG |
1020 | cache->call0 = !windowed; |
1021 | if (cache->call0) | |
1022 | { | |
1023 | cache->c0.c0_frmsz = -1; | |
1024 | cache->c0.c0_hasfp = 0; | |
1025 | cache->c0.fp_regnum = -1; | |
1026 | cache->c0.c0_fp = -1; | |
dbab50de MG |
1027 | cache->c0.c0_fpalign = 0; |
1028 | cache->c0.c0_old_sp = C0_INEXP; | |
1029 | cache->c0.c0_sp_ofs = C0_NOSTK; | |
ca3bf3bd | 1030 | |
bdb4c075 MG |
1031 | for (i = 0; i < C0_NREGS; i++) |
1032 | { | |
1033 | cache->c0.c0_rt[i].fr_reg = i; | |
1034 | cache->c0.c0_rt[i].fr_ofs = 0; | |
1035 | cache->c0.c0_rt[i].to_stk = C0_NOSTK; | |
1036 | } | |
1037 | } | |
1038 | else | |
1039 | { | |
1040 | cache->wd.wb = 0; | |
ee967b5f | 1041 | cache->wd.ws = 0; |
bdb4c075 | 1042 | cache->wd.callsize = -1; |
ca3bf3bd | 1043 | |
bdb4c075 MG |
1044 | for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++) |
1045 | cache->wd.aregs[i] = -1; | |
1046 | } | |
ca3bf3bd DJ |
1047 | return cache; |
1048 | } | |
1049 | ||
1050 | ||
1051 | static CORE_ADDR | |
1052 | xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) | |
1053 | { | |
1054 | return address & ~15; | |
1055 | } | |
1056 | ||
1057 | ||
1058 | static CORE_ADDR | |
1059 | xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1060 | { | |
ff7a4c00 | 1061 | gdb_byte buf[8]; |
0dfff4cb | 1062 | CORE_ADDR pc; |
ca3bf3bd | 1063 | |
a74ce742 PM |
1064 | DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n", |
1065 | host_address_to_string (next_frame)); | |
ca3bf3bd | 1066 | |
6b50c0b0 | 1067 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1068 | pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
ca3bf3bd | 1069 | |
0dfff4cb | 1070 | DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc); |
ca3bf3bd | 1071 | |
0dfff4cb | 1072 | return pc; |
ca3bf3bd DJ |
1073 | } |
1074 | ||
1075 | ||
1076 | static struct frame_id | |
5142f611 | 1077 | xtensa_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
ca3bf3bd DJ |
1078 | { |
1079 | CORE_ADDR pc, fp; | |
ca3bf3bd | 1080 | |
5142f611 | 1081 | /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */ |
ca3bf3bd | 1082 | |
5142f611 MG |
1083 | pc = get_frame_pc (this_frame); |
1084 | fp = get_frame_register_unsigned | |
1085 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1); | |
ca3bf3bd DJ |
1086 | |
1087 | /* Make dummy frame ID unique by adding a constant. */ | |
bdb4c075 | 1088 | return frame_id_build (fp + SP_ALIGNMENT, pc); |
ca3bf3bd DJ |
1089 | } |
1090 | ||
08b9c608 MG |
1091 | /* Returns true, if instruction to execute next is unique to Xtensa Window |
1092 | Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */ | |
1093 | ||
1094 | static int | |
1095 | xtensa_window_interrupt_insn (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1096 | { | |
1097 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1098 | unsigned int insn = read_memory_integer (pc, 4, byte_order); | |
1099 | unsigned int code; | |
1100 | ||
1101 | if (byte_order == BFD_ENDIAN_BIG) | |
1102 | { | |
1103 | /* Check, if this is L32E or S32E. */ | |
1104 | code = insn & 0xf000ff00; | |
1105 | if ((code == 0x00009000) || (code == 0x00009400)) | |
1106 | return 1; | |
1107 | /* Check, if this is RFWU or RFWO. */ | |
1108 | code = insn & 0xffffff00; | |
1109 | return ((code == 0x00430000) || (code == 0x00530000)); | |
1110 | } | |
1111 | else | |
1112 | { | |
1113 | /* Check, if this is L32E or S32E. */ | |
1114 | code = insn & 0x00ff000f; | |
1115 | if ((code == 0x090000) || (code == 0x490000)) | |
1116 | return 1; | |
1117 | /* Check, if this is RFWU or RFWO. */ | |
1118 | code = insn & 0x00ffffff; | |
1119 | return ((code == 0x00003400) || (code == 0x00003500)); | |
1120 | } | |
1121 | } | |
1122 | ||
ee967b5f MG |
1123 | /* Returns the best guess about which register is a frame pointer |
1124 | for the function containing CURRENT_PC. */ | |
1125 | ||
d4709618 MG |
1126 | #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */ |
1127 | #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */ | |
ee967b5f MG |
1128 | |
1129 | static unsigned int | |
1130 | xtensa_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR current_pc) | |
1131 | { | |
1132 | #define RETURN_FP goto done | |
1133 | ||
1134 | unsigned int fp_regnum = gdbarch_tdep (gdbarch)->a0_base + 1; | |
1135 | CORE_ADDR start_addr; | |
1136 | xtensa_isa isa; | |
1137 | xtensa_insnbuf ins, slot; | |
948f8e3d | 1138 | gdb_byte ibuf[XTENSA_ISA_BSZ]; |
ee967b5f MG |
1139 | CORE_ADDR ia, bt, ba; |
1140 | xtensa_format ifmt; | |
1141 | int ilen, islots, is; | |
1142 | xtensa_opcode opc; | |
1143 | const char *opcname; | |
1144 | ||
1145 | find_pc_partial_function (current_pc, NULL, &start_addr, NULL); | |
1146 | if (start_addr == 0) | |
1147 | return fp_regnum; | |
1148 | ||
ee967b5f MG |
1149 | isa = xtensa_default_isa; |
1150 | gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); | |
1151 | ins = xtensa_insnbuf_alloc (isa); | |
1152 | slot = xtensa_insnbuf_alloc (isa); | |
1153 | ba = 0; | |
1154 | ||
1155 | for (ia = start_addr, bt = ia; ia < current_pc ; ia += ilen) | |
1156 | { | |
1157 | if (ia + xtensa_isa_maxlength (isa) > bt) | |
1158 | { | |
1159 | ba = ia; | |
1160 | bt = (ba + XTENSA_ISA_BSZ) < current_pc | |
1161 | ? ba + XTENSA_ISA_BSZ : current_pc; | |
d4709618 MG |
1162 | if (target_read_memory (ba, ibuf, bt - ba) != 0) |
1163 | RETURN_FP; | |
ee967b5f MG |
1164 | } |
1165 | ||
1166 | xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); | |
1167 | ifmt = xtensa_format_decode (isa, ins); | |
1168 | if (ifmt == XTENSA_UNDEFINED) | |
1169 | RETURN_FP; | |
1170 | ilen = xtensa_format_length (isa, ifmt); | |
1171 | if (ilen == XTENSA_UNDEFINED) | |
1172 | RETURN_FP; | |
1173 | islots = xtensa_format_num_slots (isa, ifmt); | |
1174 | if (islots == XTENSA_UNDEFINED) | |
1175 | RETURN_FP; | |
1176 | ||
1177 | for (is = 0; is < islots; ++is) | |
1178 | { | |
1179 | if (xtensa_format_get_slot (isa, ifmt, is, ins, slot)) | |
1180 | RETURN_FP; | |
1181 | ||
1182 | opc = xtensa_opcode_decode (isa, ifmt, is, slot); | |
1183 | if (opc == XTENSA_UNDEFINED) | |
1184 | RETURN_FP; | |
1185 | ||
1186 | opcname = xtensa_opcode_name (isa, opc); | |
1187 | ||
1188 | if (strcasecmp (opcname, "mov.n") == 0 | |
1189 | || strcasecmp (opcname, "or") == 0) | |
1190 | { | |
1191 | unsigned int register_operand; | |
1192 | ||
1193 | /* Possible candidate for setting frame pointer | |
581e13c1 | 1194 | from A1. This is what we are looking for. */ |
ee967b5f MG |
1195 | |
1196 | if (xtensa_operand_get_field (isa, opc, 1, ifmt, | |
1197 | is, slot, ®ister_operand) != 0) | |
1198 | RETURN_FP; | |
1199 | if (xtensa_operand_decode (isa, opc, 1, ®ister_operand) != 0) | |
1200 | RETURN_FP; | |
1201 | if (register_operand == 1) /* Mov{.n} FP A1. */ | |
1202 | { | |
1203 | if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, | |
1204 | ®ister_operand) != 0) | |
1205 | RETURN_FP; | |
1206 | if (xtensa_operand_decode (isa, opc, 0, | |
1207 | ®ister_operand) != 0) | |
1208 | RETURN_FP; | |
1209 | ||
581e13c1 MS |
1210 | fp_regnum |
1211 | = gdbarch_tdep (gdbarch)->a0_base + register_operand; | |
ee967b5f MG |
1212 | RETURN_FP; |
1213 | } | |
1214 | } | |
1215 | ||
1216 | if ( | |
1217 | /* We have problems decoding the memory. */ | |
1218 | opcname == NULL | |
1219 | || strcasecmp (opcname, "ill") == 0 | |
1220 | || strcasecmp (opcname, "ill.n") == 0 | |
1221 | /* Hit planted breakpoint. */ | |
1222 | || strcasecmp (opcname, "break") == 0 | |
1223 | || strcasecmp (opcname, "break.n") == 0 | |
1224 | /* Flow control instructions finish prologue. */ | |
1225 | || xtensa_opcode_is_branch (isa, opc) > 0 | |
1226 | || xtensa_opcode_is_jump (isa, opc) > 0 | |
1227 | || xtensa_opcode_is_loop (isa, opc) > 0 | |
1228 | || xtensa_opcode_is_call (isa, opc) > 0 | |
1229 | || strcasecmp (opcname, "simcall") == 0 | |
1230 | || strcasecmp (opcname, "syscall") == 0) | |
1231 | /* Can not continue analysis. */ | |
1232 | RETURN_FP; | |
1233 | } | |
1234 | } | |
1235 | done: | |
1236 | xtensa_insnbuf_free(isa, slot); | |
1237 | xtensa_insnbuf_free(isa, ins); | |
1238 | return fp_regnum; | |
1239 | } | |
1240 | ||
bdb4c075 MG |
1241 | /* The key values to identify the frame using "cache" are |
1242 | ||
ee967b5f | 1243 | cache->base = SP (or best guess about FP) of this frame; |
bdb4c075 | 1244 | cache->pc = entry-PC (entry point of the frame function); |
581e13c1 | 1245 | cache->prev_sp = SP of the previous frame. */ |
bdb4c075 MG |
1246 | |
1247 | static void | |
5142f611 | 1248 | call0_frame_cache (struct frame_info *this_frame, |
dbab50de | 1249 | xtensa_frame_cache_t *cache, CORE_ADDR pc); |
ca3bf3bd | 1250 | |
08b9c608 MG |
1251 | static void |
1252 | xtensa_window_interrupt_frame_cache (struct frame_info *this_frame, | |
1253 | xtensa_frame_cache_t *cache, | |
1254 | CORE_ADDR pc); | |
1255 | ||
ca3bf3bd | 1256 | static struct xtensa_frame_cache * |
5142f611 | 1257 | xtensa_frame_cache (struct frame_info *this_frame, void **this_cache) |
ca3bf3bd DJ |
1258 | { |
1259 | xtensa_frame_cache_t *cache; | |
ca3bf3bd | 1260 | CORE_ADDR ra, wb, ws, pc, sp, ps; |
5142f611 | 1261 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
e17a4113 | 1262 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
ee967b5f | 1263 | unsigned int fp_regnum; |
98689b25 | 1264 | int windowed, ps_regnum; |
ca3bf3bd | 1265 | |
ca3bf3bd | 1266 | if (*this_cache) |
19ba03f4 | 1267 | return (struct xtensa_frame_cache *) *this_cache; |
ca3bf3bd | 1268 | |
98689b25 MG |
1269 | pc = get_frame_register_unsigned (this_frame, gdbarch_pc_regnum (gdbarch)); |
1270 | ps_regnum = gdbarch_ps_regnum (gdbarch); | |
68d6df83 MG |
1271 | ps = (ps_regnum >= 0 |
1272 | ? get_frame_register_unsigned (this_frame, ps_regnum) : TX_PS); | |
98689b25 MG |
1273 | |
1274 | windowed = windowing_enabled (gdbarch, ps); | |
bdb4c075 | 1275 | |
ca3bf3bd | 1276 | /* Get pristine xtensa-frame. */ |
bdb4c075 | 1277 | cache = xtensa_alloc_frame_cache (windowed); |
ca3bf3bd DJ |
1278 | *this_cache = cache; |
1279 | ||
bdb4c075 | 1280 | if (windowed) |
ca3bf3bd | 1281 | { |
a08b52b5 | 1282 | LONGEST op1; |
98689b25 | 1283 | |
bdb4c075 | 1284 | /* Get WINDOWBASE, WINDOWSTART, and PS registers. */ |
5142f611 MG |
1285 | wb = get_frame_register_unsigned (this_frame, |
1286 | gdbarch_tdep (gdbarch)->wb_regnum); | |
1287 | ws = get_frame_register_unsigned (this_frame, | |
1288 | gdbarch_tdep (gdbarch)->ws_regnum); | |
ca3bf3bd | 1289 | |
a08b52b5 MF |
1290 | if (safe_read_memory_integer (pc, 1, byte_order, &op1) |
1291 | && XTENSA_IS_ENTRY (gdbarch, op1)) | |
ca3bf3bd | 1292 | { |
bdb4c075 | 1293 | int callinc = CALLINC (ps); |
5142f611 MG |
1294 | ra = get_frame_register_unsigned |
1295 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + callinc * 4); | |
bdb4c075 MG |
1296 | |
1297 | /* ENTRY hasn't been executed yet, therefore callsize is still 0. */ | |
1298 | cache->wd.callsize = 0; | |
1299 | cache->wd.wb = wb; | |
1300 | cache->wd.ws = ws; | |
5142f611 MG |
1301 | cache->prev_sp = get_frame_register_unsigned |
1302 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1); | |
ee967b5f MG |
1303 | |
1304 | /* This only can be the outermost frame since we are | |
1305 | just about to execute ENTRY. SP hasn't been set yet. | |
1306 | We can assume any frame size, because it does not | |
1307 | matter, and, let's fake frame base in cache. */ | |
98689b25 | 1308 | cache->base = cache->prev_sp - 16; |
ee967b5f MG |
1309 | |
1310 | cache->pc = pc; | |
1311 | cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff); | |
1312 | cache->ps = (ps & ~PS_CALLINC_MASK) | |
1313 | | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT); | |
1314 | ||
1315 | return cache; | |
bdb4c075 MG |
1316 | } |
1317 | else | |
1318 | { | |
ee967b5f | 1319 | fp_regnum = xtensa_scan_prologue (gdbarch, pc); |
5142f611 MG |
1320 | ra = get_frame_register_unsigned (this_frame, |
1321 | gdbarch_tdep (gdbarch)->a0_base); | |
bdb4c075 | 1322 | cache->wd.callsize = WINSIZE (ra); |
304fe255 | 1323 | cache->wd.wb = (wb - cache->wd.callsize / 4) |
6b50c0b0 | 1324 | & (gdbarch_tdep (gdbarch)->num_aregs / 4 - 1); |
bdb4c075 | 1325 | cache->wd.ws = ws & ~(1 << wb); |
ca3bf3bd | 1326 | |
5142f611 | 1327 | cache->pc = get_frame_func (this_frame); |
f6402f18 | 1328 | cache->ra = (pc & 0xc0000000) | (ra & 0x3fffffff); |
ee967b5f MG |
1329 | cache->ps = (ps & ~PS_CALLINC_MASK) |
1330 | | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT); | |
1331 | } | |
bdb4c075 MG |
1332 | |
1333 | if (cache->wd.ws == 0) | |
ca3bf3bd | 1334 | { |
bdb4c075 | 1335 | int i; |
ca3bf3bd | 1336 | |
bdb4c075 | 1337 | /* Set A0...A3. */ |
5142f611 MG |
1338 | sp = get_frame_register_unsigned |
1339 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1) - 16; | |
bdb4c075 MG |
1340 | |
1341 | for (i = 0; i < 4; i++, sp += 4) | |
1342 | { | |
1343 | cache->wd.aregs[i] = sp; | |
1344 | } | |
ca3bf3bd | 1345 | |
bdb4c075 | 1346 | if (cache->wd.callsize > 4) |
ca3bf3bd | 1347 | { |
bdb4c075 | 1348 | /* Set A4...A7/A11. */ |
ee967b5f MG |
1349 | /* Get the SP of the frame previous to the previous one. |
1350 | To achieve this, we have to dereference SP twice. */ | |
e17a4113 UW |
1351 | sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order); |
1352 | sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order); | |
bdb4c075 MG |
1353 | sp -= cache->wd.callsize * 4; |
1354 | ||
ee967b5f | 1355 | for ( i = 4; i < cache->wd.callsize; i++, sp += 4) |
bdb4c075 MG |
1356 | { |
1357 | cache->wd.aregs[i] = sp; | |
1358 | } | |
ca3bf3bd DJ |
1359 | } |
1360 | } | |
ca3bf3bd | 1361 | |
bdb4c075 | 1362 | if ((cache->prev_sp == 0) && ( ra != 0 )) |
08b9c608 MG |
1363 | /* If RA is equal to 0 this frame is an outermost frame. Leave |
1364 | cache->prev_sp unchanged marking the boundary of the frame stack. */ | |
ca3bf3bd | 1365 | { |
ee967b5f | 1366 | if ((cache->wd.ws & (1 << cache->wd.wb)) == 0) |
bdb4c075 MG |
1367 | { |
1368 | /* Register window overflow already happened. | |
1369 | We can read caller's SP from the proper spill loction. */ | |
5142f611 MG |
1370 | sp = get_frame_register_unsigned |
1371 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1); | |
e17a4113 | 1372 | cache->prev_sp = read_memory_integer (sp - 12, 4, byte_order); |
bdb4c075 MG |
1373 | } |
1374 | else | |
1375 | { | |
1376 | /* Read caller's frame SP directly from the previous window. */ | |
ee967b5f | 1377 | int regnum = arreg_number |
91d8eb23 | 1378 | (gdbarch, gdbarch_tdep (gdbarch)->a0_base + 1, |
304fe255 | 1379 | cache->wd.wb); |
ca3bf3bd | 1380 | |
08b9c608 | 1381 | cache->prev_sp = xtensa_read_register (regnum); |
bdb4c075 | 1382 | } |
ca3bf3bd DJ |
1383 | } |
1384 | } | |
08b9c608 MG |
1385 | else if (xtensa_window_interrupt_insn (gdbarch, pc)) |
1386 | { | |
1387 | /* Execution stopped inside Xtensa Window Interrupt Handler. */ | |
1388 | ||
1389 | xtensa_window_interrupt_frame_cache (this_frame, cache, pc); | |
1390 | /* Everything was set already, including cache->base. */ | |
1391 | return cache; | |
1392 | } | |
bdb4c075 MG |
1393 | else /* Call0 framework. */ |
1394 | { | |
dbab50de | 1395 | call0_frame_cache (this_frame, cache, pc); |
ee967b5f | 1396 | fp_regnum = cache->c0.fp_regnum; |
bdb4c075 | 1397 | } |
ca3bf3bd | 1398 | |
5142f611 | 1399 | cache->base = get_frame_register_unsigned (this_frame, fp_regnum); |
ca3bf3bd | 1400 | |
ca3bf3bd DJ |
1401 | return cache; |
1402 | } | |
1403 | ||
dbab50de MG |
1404 | static int xtensa_session_once_reported = 1; |
1405 | ||
1406 | /* Report a problem with prologue analysis while doing backtracing. | |
1407 | But, do it only once to avoid annoyng repeated messages. */ | |
1408 | ||
4e6ca6d5 MG |
1409 | static void |
1410 | warning_once (void) | |
dbab50de MG |
1411 | { |
1412 | if (xtensa_session_once_reported == 0) | |
1413 | warning (_("\ | |
1414 | \nUnrecognised function prologue. Stack trace cannot be resolved. \ | |
1415 | This message will not be repeated in this session.\n")); | |
1416 | ||
1417 | xtensa_session_once_reported = 1; | |
1418 | } | |
1419 | ||
1420 | ||
ca3bf3bd | 1421 | static void |
5142f611 | 1422 | xtensa_frame_this_id (struct frame_info *this_frame, |
ca3bf3bd DJ |
1423 | void **this_cache, |
1424 | struct frame_id *this_id) | |
1425 | { | |
1426 | struct xtensa_frame_cache *cache = | |
5142f611 | 1427 | xtensa_frame_cache (this_frame, this_cache); |
ca3bf3bd DJ |
1428 | |
1429 | if (cache->prev_sp == 0) | |
1430 | return; | |
1431 | ||
5142f611 | 1432 | (*this_id) = frame_id_build (cache->prev_sp, cache->pc); |
bdb4c075 | 1433 | } |
ca3bf3bd | 1434 | |
5142f611 MG |
1435 | static struct value * |
1436 | xtensa_frame_prev_register (struct frame_info *this_frame, | |
ca3bf3bd | 1437 | void **this_cache, |
5142f611 | 1438 | int regnum) |
ca3bf3bd | 1439 | { |
5142f611 MG |
1440 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1441 | struct xtensa_frame_cache *cache; | |
1442 | ULONGEST saved_reg = 0; | |
ca3bf3bd DJ |
1443 | int done = 1; |
1444 | ||
5142f611 MG |
1445 | if (*this_cache == NULL) |
1446 | *this_cache = xtensa_frame_cache (this_frame, this_cache); | |
19ba03f4 | 1447 | cache = (struct xtensa_frame_cache *) *this_cache; |
ca3bf3bd | 1448 | |
6b50c0b0 | 1449 | if (regnum ==gdbarch_pc_regnum (gdbarch)) |
bdb4c075 | 1450 | saved_reg = cache->ra; |
6b50c0b0 | 1451 | else if (regnum == gdbarch_tdep (gdbarch)->a0_base + 1) |
bdb4c075 MG |
1452 | saved_reg = cache->prev_sp; |
1453 | else if (!cache->call0) | |
ca3bf3bd | 1454 | { |
6b50c0b0 | 1455 | if (regnum == gdbarch_tdep (gdbarch)->ws_regnum) |
ee967b5f | 1456 | saved_reg = cache->wd.ws; |
6b50c0b0 | 1457 | else if (regnum == gdbarch_tdep (gdbarch)->wb_regnum) |
bdb4c075 | 1458 | saved_reg = cache->wd.wb; |
6b50c0b0 | 1459 | else if (regnum == gdbarch_ps_regnum (gdbarch)) |
bdb4c075 | 1460 | saved_reg = cache->ps; |
ca3bf3bd | 1461 | else |
bdb4c075 | 1462 | done = 0; |
ca3bf3bd | 1463 | } |
ca3bf3bd DJ |
1464 | else |
1465 | done = 0; | |
1466 | ||
1467 | if (done) | |
5142f611 | 1468 | return frame_unwind_got_constant (this_frame, regnum, saved_reg); |
ca3bf3bd | 1469 | |
bdb4c075 | 1470 | if (!cache->call0) /* Windowed ABI. */ |
ca3bf3bd | 1471 | { |
ee967b5f MG |
1472 | /* Convert A-register numbers to AR-register numbers, |
1473 | if we deal with A-register. */ | |
94a0e877 | 1474 | if (regnum >= gdbarch_tdep (gdbarch)->a0_base |
6b50c0b0 | 1475 | && regnum <= gdbarch_tdep (gdbarch)->a0_base + 15) |
ee967b5f | 1476 | regnum = arreg_number (gdbarch, regnum, cache->wd.wb); |
ca3bf3bd | 1477 | |
ee967b5f | 1478 | /* Check, if we deal with AR-register saved on stack. */ |
6b50c0b0 UW |
1479 | if (regnum >= gdbarch_tdep (gdbarch)->ar_base |
1480 | && regnum <= (gdbarch_tdep (gdbarch)->ar_base | |
1481 | + gdbarch_tdep (gdbarch)->num_aregs)) | |
bdb4c075 | 1482 | { |
ee967b5f | 1483 | int areg = areg_number (gdbarch, regnum, cache->wd.wb); |
ca3bf3bd | 1484 | |
bdb4c075 MG |
1485 | if (areg >= 0 |
1486 | && areg < XTENSA_NUM_SAVED_AREGS | |
1487 | && cache->wd.aregs[areg] != -1) | |
5142f611 MG |
1488 | return frame_unwind_got_memory (this_frame, regnum, |
1489 | cache->wd.aregs[areg]); | |
ca3bf3bd DJ |
1490 | } |
1491 | } | |
bdb4c075 MG |
1492 | else /* Call0 ABI. */ |
1493 | { | |
6b50c0b0 UW |
1494 | int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base |
1495 | && regnum <= (gdbarch_tdep (gdbarch)->ar_base | |
304fe255 | 1496 | + C0_NREGS)) |
6b50c0b0 | 1497 | ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum; |
ca3bf3bd | 1498 | |
bdb4c075 MG |
1499 | if (reg < C0_NREGS) |
1500 | { | |
1501 | CORE_ADDR spe; | |
1502 | int stkofs; | |
1503 | ||
1504 | /* If register was saved in the prologue, retrieve it. */ | |
1505 | stkofs = cache->c0.c0_rt[reg].to_stk; | |
1506 | if (stkofs != C0_NOSTK) | |
1507 | { | |
1508 | /* Determine SP on entry based on FP. */ | |
1509 | spe = cache->c0.c0_fp | |
1510 | - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs; | |
5142f611 | 1511 | |
581e13c1 MS |
1512 | return frame_unwind_got_memory (this_frame, regnum, |
1513 | spe + stkofs); | |
bdb4c075 MG |
1514 | } |
1515 | } | |
1516 | } | |
1517 | ||
1518 | /* All other registers have been either saved to | |
1519 | the stack or are still alive in the processor. */ | |
ca3bf3bd | 1520 | |
5142f611 | 1521 | return frame_unwind_got_register (this_frame, regnum, regnum); |
ca3bf3bd DJ |
1522 | } |
1523 | ||
1524 | ||
1525 | static const struct frame_unwind | |
5142f611 | 1526 | xtensa_unwind = |
ca3bf3bd DJ |
1527 | { |
1528 | NORMAL_FRAME, | |
8fbca658 | 1529 | default_frame_unwind_stop_reason, |
ca3bf3bd | 1530 | xtensa_frame_this_id, |
5142f611 MG |
1531 | xtensa_frame_prev_register, |
1532 | NULL, | |
1533 | default_frame_sniffer | |
ca3bf3bd DJ |
1534 | }; |
1535 | ||
ca3bf3bd | 1536 | static CORE_ADDR |
5142f611 | 1537 | xtensa_frame_base_address (struct frame_info *this_frame, void **this_cache) |
ca3bf3bd DJ |
1538 | { |
1539 | struct xtensa_frame_cache *cache = | |
5142f611 | 1540 | xtensa_frame_cache (this_frame, this_cache); |
ca3bf3bd DJ |
1541 | |
1542 | return cache->base; | |
1543 | } | |
1544 | ||
1545 | static const struct frame_base | |
1546 | xtensa_frame_base = | |
1547 | { | |
5142f611 | 1548 | &xtensa_unwind, |
ca3bf3bd DJ |
1549 | xtensa_frame_base_address, |
1550 | xtensa_frame_base_address, | |
1551 | xtensa_frame_base_address | |
1552 | }; | |
1553 | ||
1554 | ||
1555 | static void | |
1556 | xtensa_extract_return_value (struct type *type, | |
1557 | struct regcache *regcache, | |
1558 | void *dst) | |
1559 | { | |
6b50c0b0 | 1560 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
19ba03f4 | 1561 | bfd_byte *valbuf = (bfd_byte *) dst; |
ca3bf3bd DJ |
1562 | int len = TYPE_LENGTH (type); |
1563 | ULONGEST pc, wb; | |
1564 | int callsize, areg; | |
1565 | int offset = 0; | |
1566 | ||
1567 | DEBUGTRACE ("xtensa_extract_return_value (...)\n"); | |
1568 | ||
1569 | gdb_assert(len > 0); | |
1570 | ||
6b50c0b0 | 1571 | if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
bdb4c075 MG |
1572 | { |
1573 | /* First, we have to find the caller window in the register file. */ | |
6b50c0b0 | 1574 | regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc); |
91d8eb23 | 1575 | callsize = extract_call_winsize (gdbarch, pc); |
ca3bf3bd | 1576 | |
bdb4c075 MG |
1577 | /* On Xtensa, we can return up to 4 words (or 2 for call12). */ |
1578 | if (len > (callsize > 8 ? 8 : 16)) | |
1579 | internal_error (__FILE__, __LINE__, | |
581e13c1 MS |
1580 | _("cannot extract return value of %d bytes long"), |
1581 | len); | |
ca3bf3bd | 1582 | |
bdb4c075 MG |
1583 | /* Get the register offset of the return |
1584 | register (A2) in the caller window. */ | |
304fe255 | 1585 | regcache_raw_read_unsigned |
6b50c0b0 | 1586 | (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb); |
ee967b5f | 1587 | areg = arreg_number (gdbarch, |
91d8eb23 | 1588 | gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb); |
bdb4c075 MG |
1589 | } |
1590 | else | |
1591 | { | |
1592 | /* No windowing hardware - Call0 ABI. */ | |
94a0e877 | 1593 | areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS; |
bdb4c075 | 1594 | } |
ca3bf3bd DJ |
1595 | |
1596 | DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len); | |
1597 | ||
6b50c0b0 | 1598 | if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1599 | offset = 4 - len; |
1600 | ||
1601 | for (; len > 0; len -= 4, areg++, valbuf += 4) | |
1602 | { | |
1603 | if (len < 4) | |
1604 | regcache_raw_read_part (regcache, areg, offset, len, valbuf); | |
1605 | else | |
1606 | regcache_raw_read (regcache, areg, valbuf); | |
1607 | } | |
1608 | } | |
1609 | ||
1610 | ||
1611 | static void | |
1612 | xtensa_store_return_value (struct type *type, | |
1613 | struct regcache *regcache, | |
1614 | const void *dst) | |
1615 | { | |
6b50c0b0 | 1616 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
19ba03f4 | 1617 | const bfd_byte *valbuf = (const bfd_byte *) dst; |
ca3bf3bd DJ |
1618 | unsigned int areg; |
1619 | ULONGEST pc, wb; | |
1620 | int callsize; | |
1621 | int len = TYPE_LENGTH (type); | |
1622 | int offset = 0; | |
1623 | ||
1624 | DEBUGTRACE ("xtensa_store_return_value (...)\n"); | |
1625 | ||
6b50c0b0 | 1626 | if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
bdb4c075 | 1627 | { |
6b50c0b0 UW |
1628 | regcache_raw_read_unsigned |
1629 | (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb); | |
1630 | regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc); | |
91d8eb23 | 1631 | callsize = extract_call_winsize (gdbarch, pc); |
ca3bf3bd | 1632 | |
bdb4c075 MG |
1633 | if (len > (callsize > 8 ? 8 : 16)) |
1634 | internal_error (__FILE__, __LINE__, | |
1635 | _("unimplemented for this length: %d"), | |
1636 | TYPE_LENGTH (type)); | |
ee967b5f MG |
1637 | areg = arreg_number (gdbarch, |
1638 | gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb); | |
ca3bf3bd | 1639 | |
bdb4c075 | 1640 | DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n", |
ca3bf3bd | 1641 | callsize, (int) wb); |
bdb4c075 MG |
1642 | } |
1643 | else | |
1644 | { | |
94a0e877 | 1645 | areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS; |
bdb4c075 | 1646 | } |
ca3bf3bd | 1647 | |
6b50c0b0 | 1648 | if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1649 | offset = 4 - len; |
1650 | ||
ca3bf3bd DJ |
1651 | for (; len > 0; len -= 4, areg++, valbuf += 4) |
1652 | { | |
1653 | if (len < 4) | |
1654 | regcache_raw_write_part (regcache, areg, offset, len, valbuf); | |
1655 | else | |
1656 | regcache_raw_write (regcache, areg, valbuf); | |
1657 | } | |
1658 | } | |
1659 | ||
1660 | ||
bdb4c075 | 1661 | static enum return_value_convention |
ca3bf3bd | 1662 | xtensa_return_value (struct gdbarch *gdbarch, |
6a3a010b | 1663 | struct value *function, |
ca3bf3bd DJ |
1664 | struct type *valtype, |
1665 | struct regcache *regcache, | |
1666 | gdb_byte *readbuf, | |
1667 | const gdb_byte *writebuf) | |
1668 | { | |
bdb4c075 | 1669 | /* Structures up to 16 bytes are returned in registers. */ |
ca3bf3bd DJ |
1670 | |
1671 | int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT | |
1672 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
1673 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
1674 | && TYPE_LENGTH (valtype) > 16); | |
1675 | ||
1676 | if (struct_return) | |
1677 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1678 | ||
1679 | DEBUGTRACE ("xtensa_return_value(...)\n"); | |
1680 | ||
1681 | if (writebuf != NULL) | |
1682 | { | |
1683 | xtensa_store_return_value (valtype, regcache, writebuf); | |
1684 | } | |
1685 | ||
1686 | if (readbuf != NULL) | |
1687 | { | |
1688 | gdb_assert (!struct_return); | |
1689 | xtensa_extract_return_value (valtype, regcache, readbuf); | |
1690 | } | |
1691 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1692 | } | |
1693 | ||
1694 | ||
1695 | /* DUMMY FRAME */ | |
1696 | ||
1697 | static CORE_ADDR | |
1698 | xtensa_push_dummy_call (struct gdbarch *gdbarch, | |
1699 | struct value *function, | |
1700 | struct regcache *regcache, | |
1701 | CORE_ADDR bp_addr, | |
1702 | int nargs, | |
1703 | struct value **args, | |
1704 | CORE_ADDR sp, | |
1705 | int struct_return, | |
1706 | CORE_ADDR struct_addr) | |
1707 | { | |
e17a4113 | 1708 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
ca3bf3bd DJ |
1709 | int i; |
1710 | int size, onstack_size; | |
ff7a4c00 | 1711 | gdb_byte *buf = (gdb_byte *) alloca (16); |
ca3bf3bd DJ |
1712 | CORE_ADDR ra, ps; |
1713 | struct argument_info | |
1714 | { | |
1715 | const bfd_byte *contents; | |
1716 | int length; | |
1717 | int onstack; /* onstack == 0 => in reg */ | |
1718 | int align; /* alignment */ | |
1719 | union | |
1720 | { | |
581e13c1 MS |
1721 | int offset; /* stack offset if on stack. */ |
1722 | int regno; /* regno if in register. */ | |
ca3bf3bd DJ |
1723 | } u; |
1724 | }; | |
1725 | ||
1726 | struct argument_info *arg_info = | |
1727 | (struct argument_info *) alloca (nargs * sizeof (struct argument_info)); | |
1728 | ||
1729 | CORE_ADDR osp = sp; | |
1730 | ||
1731 | DEBUGTRACE ("xtensa_push_dummy_call (...)\n"); | |
1732 | ||
1733 | if (xtensa_debug_level > 3) | |
1734 | { | |
1735 | int i; | |
1736 | DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs); | |
1737 | DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, " | |
1738 | "struct_addr=0x%x\n", | |
1739 | (int) sp, (int) struct_return, (int) struct_addr); | |
1740 | ||
1741 | for (i = 0; i < nargs; i++) | |
1742 | { | |
1743 | struct value *arg = args[i]; | |
1744 | struct type *arg_type = check_typedef (value_type (arg)); | |
3329c4b5 PM |
1745 | fprintf_unfiltered (gdb_stdlog, "%2d: %s %3d ", i, |
1746 | host_address_to_string (arg), | |
1747 | TYPE_LENGTH (arg_type)); | |
ca3bf3bd DJ |
1748 | switch (TYPE_CODE (arg_type)) |
1749 | { | |
1750 | case TYPE_CODE_INT: | |
1751 | fprintf_unfiltered (gdb_stdlog, "int"); | |
1752 | break; | |
1753 | case TYPE_CODE_STRUCT: | |
1754 | fprintf_unfiltered (gdb_stdlog, "struct"); | |
1755 | break; | |
1756 | default: | |
1757 | fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type)); | |
1758 | break; | |
1759 | } | |
3329c4b5 PM |
1760 | fprintf_unfiltered (gdb_stdlog, " %s\n", |
1761 | host_address_to_string (value_contents (arg))); | |
ca3bf3bd DJ |
1762 | } |
1763 | } | |
1764 | ||
1765 | /* First loop: collect information. | |
1766 | Cast into type_long. (This shouldn't happen often for C because | |
1767 | GDB already does this earlier.) It's possible that GDB could | |
1768 | do it all the time but it's harmless to leave this code here. */ | |
1769 | ||
1770 | size = 0; | |
1771 | onstack_size = 0; | |
1772 | i = 0; | |
1773 | ||
1774 | if (struct_return) | |
1775 | size = REGISTER_SIZE; | |
1776 | ||
1777 | for (i = 0; i < nargs; i++) | |
1778 | { | |
1779 | struct argument_info *info = &arg_info[i]; | |
1780 | struct value *arg = args[i]; | |
1781 | struct type *arg_type = check_typedef (value_type (arg)); | |
1782 | ||
1783 | switch (TYPE_CODE (arg_type)) | |
1784 | { | |
1785 | case TYPE_CODE_INT: | |
1786 | case TYPE_CODE_BOOL: | |
1787 | case TYPE_CODE_CHAR: | |
1788 | case TYPE_CODE_RANGE: | |
1789 | case TYPE_CODE_ENUM: | |
1790 | ||
1791 | /* Cast argument to long if necessary as the mask does it too. */ | |
0dfff4cb UW |
1792 | if (TYPE_LENGTH (arg_type) |
1793 | < TYPE_LENGTH (builtin_type (gdbarch)->builtin_long)) | |
ca3bf3bd | 1794 | { |
0dfff4cb | 1795 | arg_type = builtin_type (gdbarch)->builtin_long; |
ca3bf3bd DJ |
1796 | arg = value_cast (arg_type, arg); |
1797 | } | |
bdb4c075 MG |
1798 | /* Aligment is equal to the type length for the basic types. */ |
1799 | info->align = TYPE_LENGTH (arg_type); | |
ca3bf3bd DJ |
1800 | break; |
1801 | ||
1802 | case TYPE_CODE_FLT: | |
1803 | ||
1804 | /* Align doubles correctly. */ | |
0dfff4cb UW |
1805 | if (TYPE_LENGTH (arg_type) |
1806 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_double)) | |
1807 | info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_double); | |
ca3bf3bd | 1808 | else |
0dfff4cb | 1809 | info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long); |
ca3bf3bd DJ |
1810 | break; |
1811 | ||
1812 | case TYPE_CODE_STRUCT: | |
1813 | default: | |
0dfff4cb | 1814 | info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long); |
ca3bf3bd DJ |
1815 | break; |
1816 | } | |
1817 | info->length = TYPE_LENGTH (arg_type); | |
1818 | info->contents = value_contents (arg); | |
1819 | ||
1820 | /* Align size and onstack_size. */ | |
1821 | size = (size + info->align - 1) & ~(info->align - 1); | |
1822 | onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1); | |
1823 | ||
91d8eb23 | 1824 | if (size + info->length > REGISTER_SIZE * ARG_NOF (gdbarch)) |
ca3bf3bd DJ |
1825 | { |
1826 | info->onstack = 1; | |
1827 | info->u.offset = onstack_size; | |
1828 | onstack_size += info->length; | |
1829 | } | |
1830 | else | |
1831 | { | |
1832 | info->onstack = 0; | |
91d8eb23 | 1833 | info->u.regno = ARG_1ST (gdbarch) + size / REGISTER_SIZE; |
ca3bf3bd DJ |
1834 | } |
1835 | size += info->length; | |
1836 | } | |
1837 | ||
1838 | /* Adjust the stack pointer and align it. */ | |
1839 | sp = align_down (sp - onstack_size, SP_ALIGNMENT); | |
1840 | ||
bdb4c075 | 1841 | /* Simulate MOVSP, if Windowed ABI. */ |
6b50c0b0 | 1842 | if ((gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
304fe255 | 1843 | && (sp != osp)) |
ca3bf3bd DJ |
1844 | { |
1845 | read_memory (osp - 16, buf, 16); | |
1846 | write_memory (sp - 16, buf, 16); | |
1847 | } | |
1848 | ||
1849 | /* Second Loop: Load arguments. */ | |
1850 | ||
1851 | if (struct_return) | |
1852 | { | |
e17a4113 | 1853 | store_unsigned_integer (buf, REGISTER_SIZE, byte_order, struct_addr); |
91d8eb23 | 1854 | regcache_cooked_write (regcache, ARG_1ST (gdbarch), buf); |
ca3bf3bd DJ |
1855 | } |
1856 | ||
1857 | for (i = 0; i < nargs; i++) | |
1858 | { | |
1859 | struct argument_info *info = &arg_info[i]; | |
1860 | ||
1861 | if (info->onstack) | |
1862 | { | |
1863 | int n = info->length; | |
1864 | CORE_ADDR offset = sp + info->u.offset; | |
1865 | ||
1866 | /* Odd-sized structs are aligned to the lower side of a memory | |
1867 | word in big-endian mode and require a shift. This only | |
1868 | applies for structures smaller than one word. */ | |
1869 | ||
4c6b5505 | 1870 | if (n < REGISTER_SIZE |
6b50c0b0 | 1871 | && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1872 | offset += (REGISTER_SIZE - n); |
1873 | ||
1874 | write_memory (offset, info->contents, info->length); | |
1875 | ||
1876 | } | |
1877 | else | |
1878 | { | |
1879 | int n = info->length; | |
1880 | const bfd_byte *cp = info->contents; | |
1881 | int r = info->u.regno; | |
1882 | ||
1883 | /* Odd-sized structs are aligned to the lower side of registers in | |
1884 | big-endian mode and require a shift. The odd-sized leftover will | |
1885 | be at the end. Note that this is only true for structures smaller | |
1886 | than REGISTER_SIZE; for larger odd-sized structures the excess | |
1887 | will be left-aligned in the register on both endiannesses. */ | |
1888 | ||
e17a4113 | 1889 | if (n < REGISTER_SIZE && byte_order == BFD_ENDIAN_BIG) |
ca3bf3bd | 1890 | { |
e17a4113 UW |
1891 | ULONGEST v; |
1892 | v = extract_unsigned_integer (cp, REGISTER_SIZE, byte_order); | |
ca3bf3bd DJ |
1893 | v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT); |
1894 | ||
e17a4113 | 1895 | store_unsigned_integer (buf, REGISTER_SIZE, byte_order, v); |
ca3bf3bd DJ |
1896 | regcache_cooked_write (regcache, r, buf); |
1897 | ||
1898 | cp += REGISTER_SIZE; | |
1899 | n -= REGISTER_SIZE; | |
1900 | r++; | |
1901 | } | |
1902 | else | |
1903 | while (n > 0) | |
1904 | { | |
ca3bf3bd DJ |
1905 | regcache_cooked_write (regcache, r, cp); |
1906 | ||
ca3bf3bd DJ |
1907 | cp += REGISTER_SIZE; |
1908 | n -= REGISTER_SIZE; | |
1909 | r++; | |
1910 | } | |
1911 | } | |
1912 | } | |
1913 | ||
ca3bf3bd | 1914 | /* Set the return address of dummy frame to the dummy address. |
bdb4c075 | 1915 | The return address for the current function (in A0) is |
ca3bf3bd DJ |
1916 | saved in the dummy frame, so we can savely overwrite A0 here. */ |
1917 | ||
6b50c0b0 | 1918 | if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only) |
bdb4c075 | 1919 | { |
98689b25 | 1920 | ULONGEST val; |
68d6df83 | 1921 | |
bdb4c075 | 1922 | ra = (bp_addr & 0x3fffffff) | 0x40000000; |
98689b25 MG |
1923 | regcache_raw_read_unsigned (regcache, gdbarch_ps_regnum (gdbarch), &val); |
1924 | ps = (unsigned long) val & ~0x00030000; | |
304fe255 | 1925 | regcache_cooked_write_unsigned |
6b50c0b0 | 1926 | (regcache, gdbarch_tdep (gdbarch)->a0_base + 4, ra); |
bdb4c075 | 1927 | regcache_cooked_write_unsigned (regcache, |
6b50c0b0 | 1928 | gdbarch_ps_regnum (gdbarch), |
bdb4c075 | 1929 | ps | 0x00010000); |
94a0e877 MG |
1930 | |
1931 | /* All the registers have been saved. After executing | |
1932 | dummy call, they all will be restored. So it's safe | |
1933 | to modify WINDOWSTART register to make it look like there | |
1934 | is only one register window corresponding to WINDOWEBASE. */ | |
1935 | ||
1936 | regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf); | |
e17a4113 UW |
1937 | regcache_cooked_write_unsigned |
1938 | (regcache, gdbarch_tdep (gdbarch)->ws_regnum, | |
1939 | 1 << extract_unsigned_integer (buf, 4, byte_order)); | |
bdb4c075 MG |
1940 | } |
1941 | else | |
1942 | { | |
1943 | /* Simulate CALL0: write RA into A0 register. */ | |
304fe255 | 1944 | regcache_cooked_write_unsigned |
94a0e877 | 1945 | (regcache, gdbarch_tdep (gdbarch)->a0_base, bp_addr); |
bdb4c075 | 1946 | } |
ca3bf3bd DJ |
1947 | |
1948 | /* Set new stack pointer and return it. */ | |
304fe255 | 1949 | regcache_cooked_write_unsigned (regcache, |
6b50c0b0 | 1950 | gdbarch_tdep (gdbarch)->a0_base + 1, sp); |
ca3bf3bd DJ |
1951 | /* Make dummy frame ID unique by adding a constant. */ |
1952 | return sp + SP_ALIGNMENT; | |
1953 | } | |
1954 | ||
cd6c3b4f YQ |
1955 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
1956 | ||
d19280ad YQ |
1957 | static int |
1958 | xtensa_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
1959 | { | |
1960 | if (gdbarch_tdep (gdbarch)->isa_use_density_instructions) | |
1961 | return 2; | |
1962 | else | |
1963 | return 4; | |
1964 | } | |
ca3bf3bd DJ |
1965 | |
1966 | /* Return a breakpoint for the current location of PC. We always use | |
1967 | the density version if we have density instructions (regardless of the | |
1968 | current instruction at PC), and use regular instructions otherwise. */ | |
1969 | ||
1970 | #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 } | |
1971 | #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 } | |
1972 | #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f } | |
1973 | #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 } | |
1974 | ||
cd6c3b4f YQ |
1975 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
1976 | ||
d19280ad YQ |
1977 | static const gdb_byte * |
1978 | xtensa_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
ca3bf3bd | 1979 | { |
d19280ad | 1980 | *size = kind; |
ca3bf3bd | 1981 | |
d19280ad | 1982 | if (kind == 4) |
ca3bf3bd | 1983 | { |
d19280ad YQ |
1984 | static unsigned char big_breakpoint[] = BIG_BREAKPOINT; |
1985 | static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT; | |
1986 | ||
67d57894 | 1987 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d19280ad | 1988 | return big_breakpoint; |
ca3bf3bd | 1989 | else |
d19280ad | 1990 | return little_breakpoint; |
ca3bf3bd DJ |
1991 | } |
1992 | else | |
1993 | { | |
d19280ad YQ |
1994 | static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT; |
1995 | static unsigned char density_little_breakpoint[] | |
1996 | = DENSITY_LITTLE_BREAKPOINT; | |
1997 | ||
67d57894 | 1998 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d19280ad | 1999 | return density_big_breakpoint; |
ca3bf3bd | 2000 | else |
d19280ad | 2001 | return density_little_breakpoint; |
ca3bf3bd DJ |
2002 | } |
2003 | } | |
2004 | ||
bdb4c075 MG |
2005 | /* Call0 ABI support routines. */ |
2006 | ||
f976a05d MG |
2007 | /* Return true, if PC points to "ret" or "ret.n". */ |
2008 | ||
2009 | static int | |
2010 | call0_ret (CORE_ADDR start_pc, CORE_ADDR finish_pc) | |
2011 | { | |
2012 | #define RETURN_RET goto done | |
2013 | xtensa_isa isa; | |
2014 | xtensa_insnbuf ins, slot; | |
948f8e3d | 2015 | gdb_byte ibuf[XTENSA_ISA_BSZ]; |
f976a05d MG |
2016 | CORE_ADDR ia, bt, ba; |
2017 | xtensa_format ifmt; | |
2018 | int ilen, islots, is; | |
2019 | xtensa_opcode opc; | |
2020 | const char *opcname; | |
2021 | int found_ret = 0; | |
2022 | ||
2023 | isa = xtensa_default_isa; | |
2024 | gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); | |
2025 | ins = xtensa_insnbuf_alloc (isa); | |
2026 | slot = xtensa_insnbuf_alloc (isa); | |
2027 | ba = 0; | |
2028 | ||
2029 | for (ia = start_pc, bt = ia; ia < finish_pc ; ia += ilen) | |
2030 | { | |
2031 | if (ia + xtensa_isa_maxlength (isa) > bt) | |
2032 | { | |
2033 | ba = ia; | |
2034 | bt = (ba + XTENSA_ISA_BSZ) < finish_pc | |
2035 | ? ba + XTENSA_ISA_BSZ : finish_pc; | |
2036 | if (target_read_memory (ba, ibuf, bt - ba) != 0 ) | |
2037 | RETURN_RET; | |
2038 | } | |
2039 | ||
2040 | xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); | |
2041 | ifmt = xtensa_format_decode (isa, ins); | |
2042 | if (ifmt == XTENSA_UNDEFINED) | |
2043 | RETURN_RET; | |
2044 | ilen = xtensa_format_length (isa, ifmt); | |
2045 | if (ilen == XTENSA_UNDEFINED) | |
2046 | RETURN_RET; | |
2047 | islots = xtensa_format_num_slots (isa, ifmt); | |
2048 | if (islots == XTENSA_UNDEFINED) | |
2049 | RETURN_RET; | |
2050 | ||
2051 | for (is = 0; is < islots; ++is) | |
2052 | { | |
2053 | if (xtensa_format_get_slot (isa, ifmt, is, ins, slot)) | |
2054 | RETURN_RET; | |
2055 | ||
2056 | opc = xtensa_opcode_decode (isa, ifmt, is, slot); | |
2057 | if (opc == XTENSA_UNDEFINED) | |
2058 | RETURN_RET; | |
2059 | ||
2060 | opcname = xtensa_opcode_name (isa, opc); | |
2061 | ||
2062 | if ((strcasecmp (opcname, "ret.n") == 0) | |
2063 | || (strcasecmp (opcname, "ret") == 0)) | |
2064 | { | |
2065 | found_ret = 1; | |
2066 | RETURN_RET; | |
2067 | } | |
2068 | } | |
2069 | } | |
2070 | done: | |
2071 | xtensa_insnbuf_free(isa, slot); | |
2072 | xtensa_insnbuf_free(isa, ins); | |
2073 | return found_ret; | |
2074 | } | |
2075 | ||
bdb4c075 MG |
2076 | /* Call0 opcode class. Opcodes are preclassified according to what they |
2077 | mean for Call0 prologue analysis, and their number of significant operands. | |
2078 | The purpose of this is to simplify prologue analysis by separating | |
2079 | instruction decoding (libisa) from the semantics of prologue analysis. */ | |
2080 | ||
68d6df83 MG |
2081 | typedef enum |
2082 | { | |
bdb4c075 MG |
2083 | c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */ |
2084 | c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */ | |
2085 | c0opc_flow, /* Flow control insn. */ | |
2086 | c0opc_entry, /* ENTRY indicates non-Call0 prologue. */ | |
2087 | c0opc_break, /* Debugger software breakpoints. */ | |
2088 | c0opc_add, /* Adding two registers. */ | |
2089 | c0opc_addi, /* Adding a register and an immediate. */ | |
dbab50de | 2090 | c0opc_and, /* Bitwise "and"-ing two registers. */ |
bdb4c075 MG |
2091 | c0opc_sub, /* Subtracting a register from a register. */ |
2092 | c0opc_mov, /* Moving a register to a register. */ | |
2093 | c0opc_movi, /* Moving an immediate to a register. */ | |
2094 | c0opc_l32r, /* Loading a literal. */ | |
08b9c608 MG |
2095 | c0opc_s32i, /* Storing word at fixed offset from a base register. */ |
2096 | c0opc_rwxsr, /* RSR, WRS, or XSR instructions. */ | |
2097 | c0opc_l32e, /* L32E instruction. */ | |
2098 | c0opc_s32e, /* S32E instruction. */ | |
2099 | c0opc_rfwo, /* RFWO instruction. */ | |
2100 | c0opc_rfwu, /* RFWU instruction. */ | |
bdb4c075 MG |
2101 | c0opc_NrOf /* Number of opcode classifications. */ |
2102 | } xtensa_insn_kind; | |
2103 | ||
08b9c608 MG |
2104 | /* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */ |
2105 | ||
2106 | static int | |
2107 | rwx_special_register (const char *opcname) | |
2108 | { | |
2109 | char ch = *opcname++; | |
2110 | ||
2111 | if ((ch != 'r') && (ch != 'w') && (ch != 'x')) | |
2112 | return 0; | |
2113 | if (*opcname++ != 's') | |
2114 | return 0; | |
2115 | if (*opcname++ != 'r') | |
2116 | return 0; | |
2117 | if (*opcname++ != '.') | |
2118 | return 0; | |
2119 | ||
2120 | return 1; | |
2121 | } | |
bdb4c075 MG |
2122 | |
2123 | /* Classify an opcode based on what it means for Call0 prologue analysis. */ | |
2124 | ||
2125 | static xtensa_insn_kind | |
2126 | call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc) | |
2127 | { | |
2128 | const char *opcname; | |
2129 | xtensa_insn_kind opclass = c0opc_uninteresting; | |
2130 | ||
2131 | DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc); | |
2132 | ||
2133 | /* Get opcode name and handle special classifications. */ | |
2134 | ||
2135 | opcname = xtensa_opcode_name (isa, opc); | |
2136 | ||
2137 | if (opcname == NULL | |
2138 | || strcasecmp (opcname, "ill") == 0 | |
2139 | || strcasecmp (opcname, "ill.n") == 0) | |
2140 | opclass = c0opc_illegal; | |
2141 | else if (strcasecmp (opcname, "break") == 0 | |
2142 | || strcasecmp (opcname, "break.n") == 0) | |
2143 | opclass = c0opc_break; | |
2144 | else if (strcasecmp (opcname, "entry") == 0) | |
2145 | opclass = c0opc_entry; | |
08b9c608 MG |
2146 | else if (strcasecmp (opcname, "rfwo") == 0) |
2147 | opclass = c0opc_rfwo; | |
2148 | else if (strcasecmp (opcname, "rfwu") == 0) | |
2149 | opclass = c0opc_rfwu; | |
bdb4c075 MG |
2150 | else if (xtensa_opcode_is_branch (isa, opc) > 0 |
2151 | || xtensa_opcode_is_jump (isa, opc) > 0 | |
2152 | || xtensa_opcode_is_loop (isa, opc) > 0 | |
2153 | || xtensa_opcode_is_call (isa, opc) > 0 | |
2154 | || strcasecmp (opcname, "simcall") == 0 | |
2155 | || strcasecmp (opcname, "syscall") == 0) | |
2156 | opclass = c0opc_flow; | |
2157 | ||
2158 | /* Also, classify specific opcodes that need to be tracked. */ | |
2159 | else if (strcasecmp (opcname, "add") == 0 | |
2160 | || strcasecmp (opcname, "add.n") == 0) | |
2161 | opclass = c0opc_add; | |
dbab50de MG |
2162 | else if (strcasecmp (opcname, "and") == 0) |
2163 | opclass = c0opc_and; | |
bdb4c075 MG |
2164 | else if (strcasecmp (opcname, "addi") == 0 |
2165 | || strcasecmp (opcname, "addi.n") == 0 | |
2166 | || strcasecmp (opcname, "addmi") == 0) | |
2167 | opclass = c0opc_addi; | |
2168 | else if (strcasecmp (opcname, "sub") == 0) | |
2169 | opclass = c0opc_sub; | |
2170 | else if (strcasecmp (opcname, "mov.n") == 0 | |
2171 | || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */ | |
2172 | opclass = c0opc_mov; | |
2173 | else if (strcasecmp (opcname, "movi") == 0 | |
2174 | || strcasecmp (opcname, "movi.n") == 0) | |
2175 | opclass = c0opc_movi; | |
2176 | else if (strcasecmp (opcname, "l32r") == 0) | |
2177 | opclass = c0opc_l32r; | |
2178 | else if (strcasecmp (opcname, "s32i") == 0 | |
2179 | || strcasecmp (opcname, "s32i.n") == 0) | |
2180 | opclass = c0opc_s32i; | |
08b9c608 MG |
2181 | else if (strcasecmp (opcname, "l32e") == 0) |
2182 | opclass = c0opc_l32e; | |
2183 | else if (strcasecmp (opcname, "s32e") == 0) | |
2184 | opclass = c0opc_s32e; | |
2185 | else if (rwx_special_register (opcname)) | |
2186 | opclass = c0opc_rwxsr; | |
bdb4c075 MG |
2187 | |
2188 | return opclass; | |
2189 | } | |
2190 | ||
2191 | /* Tracks register movement/mutation for a given operation, which may | |
2192 | be within a bundle. Updates the destination register tracking info | |
2193 | accordingly. The pc is needed only for pc-relative load instructions | |
2194 | (eg. l32r). The SP register number is needed to identify stores to | |
dbab50de MG |
2195 | the stack frame. Returns 0, if analysis was succesfull, non-zero |
2196 | otherwise. */ | |
bdb4c075 | 2197 | |
dbab50de MG |
2198 | static int |
2199 | call0_track_op (struct gdbarch *gdbarch, xtensa_c0reg_t dst[], xtensa_c0reg_t src[], | |
bdb4c075 | 2200 | xtensa_insn_kind opclass, int nods, unsigned odv[], |
dbab50de | 2201 | CORE_ADDR pc, int spreg, xtensa_frame_cache_t *cache) |
bdb4c075 | 2202 | { |
e17a4113 | 2203 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
dbab50de | 2204 | unsigned litbase, litaddr, litval; |
bdb4c075 MG |
2205 | |
2206 | switch (opclass) | |
2207 | { | |
2208 | case c0opc_addi: | |
2209 | /* 3 operands: dst, src, imm. */ | |
2210 | gdb_assert (nods == 3); | |
2211 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
2212 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2]; | |
2213 | break; | |
2214 | case c0opc_add: | |
2215 | /* 3 operands: dst, src1, src2. */ | |
08b9c608 | 2216 | gdb_assert (nods == 3); |
bdb4c075 MG |
2217 | if (src[odv[1]].fr_reg == C0_CONST) |
2218 | { | |
2219 | dst[odv[0]].fr_reg = src[odv[2]].fr_reg; | |
2220 | dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs; | |
2221 | } | |
2222 | else if (src[odv[2]].fr_reg == C0_CONST) | |
2223 | { | |
2224 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
2225 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs; | |
2226 | } | |
2227 | else dst[odv[0]].fr_reg = C0_INEXP; | |
2228 | break; | |
dbab50de MG |
2229 | case c0opc_and: |
2230 | /* 3 operands: dst, src1, src2. */ | |
2231 | gdb_assert (nods == 3); | |
2232 | if (cache->c0.c0_fpalign == 0) | |
2233 | { | |
2234 | /* Handle dynamic stack alignment. */ | |
2235 | if ((src[odv[0]].fr_reg == spreg) && (src[odv[1]].fr_reg == spreg)) | |
2236 | { | |
2237 | if (src[odv[2]].fr_reg == C0_CONST) | |
2238 | cache->c0.c0_fpalign = src[odv[2]].fr_ofs; | |
2239 | break; | |
2240 | } | |
2241 | else if ((src[odv[0]].fr_reg == spreg) | |
2242 | && (src[odv[2]].fr_reg == spreg)) | |
2243 | { | |
2244 | if (src[odv[1]].fr_reg == C0_CONST) | |
2245 | cache->c0.c0_fpalign = src[odv[1]].fr_ofs; | |
2246 | break; | |
2247 | } | |
2248 | /* else fall through. */ | |
2249 | } | |
2250 | if (src[odv[1]].fr_reg == C0_CONST) | |
2251 | { | |
2252 | dst[odv[0]].fr_reg = src[odv[2]].fr_reg; | |
2253 | dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs & src[odv[1]].fr_ofs; | |
2254 | } | |
2255 | else if (src[odv[2]].fr_reg == C0_CONST) | |
2256 | { | |
2257 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
2258 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs & src[odv[2]].fr_ofs; | |
2259 | } | |
2260 | else dst[odv[0]].fr_reg = C0_INEXP; | |
2261 | break; | |
bdb4c075 MG |
2262 | case c0opc_sub: |
2263 | /* 3 operands: dst, src1, src2. */ | |
2264 | gdb_assert (nods == 3); | |
2265 | if (src[odv[2]].fr_reg == C0_CONST) | |
2266 | { | |
2267 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; | |
2268 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs; | |
2269 | } | |
2270 | else dst[odv[0]].fr_reg = C0_INEXP; | |
2271 | break; | |
2272 | case c0opc_mov: | |
2273 | /* 2 operands: dst, src [, src]. */ | |
2274 | gdb_assert (nods == 2); | |
dbab50de MG |
2275 | /* First, check if it's a special case of saving unaligned SP |
2276 | to a spare register in case of dynamic stack adjustment. | |
2277 | But, only do it one time. The second time could be initializing | |
2278 | frame pointer. We don't want to overwrite the first one. */ | |
2279 | if ((odv[1] == spreg) && (cache->c0.c0_old_sp == C0_INEXP)) | |
2280 | cache->c0.c0_old_sp = odv[0]; | |
2281 | ||
bdb4c075 MG |
2282 | dst[odv[0]].fr_reg = src[odv[1]].fr_reg; |
2283 | dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs; | |
2284 | break; | |
2285 | case c0opc_movi: | |
2286 | /* 2 operands: dst, imm. */ | |
2287 | gdb_assert (nods == 2); | |
2288 | dst[odv[0]].fr_reg = C0_CONST; | |
2289 | dst[odv[0]].fr_ofs = odv[1]; | |
2290 | break; | |
2291 | case c0opc_l32r: | |
2292 | /* 2 operands: dst, literal offset. */ | |
2293 | gdb_assert (nods == 2); | |
dbab50de MG |
2294 | /* litbase = xtensa_get_litbase (pc); can be also used. */ |
2295 | litbase = (gdbarch_tdep (gdbarch)->litbase_regnum == -1) | |
2296 | ? 0 : xtensa_read_register | |
2297 | (gdbarch_tdep (gdbarch)->litbase_regnum); | |
bdb4c075 MG |
2298 | litaddr = litbase & 1 |
2299 | ? (litbase & ~1) + (signed)odv[1] | |
2300 | : (pc + 3 + (signed)odv[1]) & ~3; | |
e17a4113 | 2301 | litval = read_memory_integer (litaddr, 4, byte_order); |
bdb4c075 MG |
2302 | dst[odv[0]].fr_reg = C0_CONST; |
2303 | dst[odv[0]].fr_ofs = litval; | |
2304 | break; | |
2305 | case c0opc_s32i: | |
2306 | /* 3 operands: value, base, offset. */ | |
2307 | gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS); | |
dbab50de MG |
2308 | /* First, check if it's a spill for saved unaligned SP, |
2309 | when dynamic stack adjustment was applied to this frame. */ | |
2310 | if ((cache->c0.c0_fpalign != 0) /* Dynamic stack adjustment. */ | |
2311 | && (odv[1] == spreg) /* SP usage indicates spill. */ | |
2312 | && (odv[0] == cache->c0.c0_old_sp)) /* Old SP register spilled. */ | |
2313 | cache->c0.c0_sp_ofs = odv[2]; | |
2314 | ||
bdb4c075 MG |
2315 | if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */ |
2316 | && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */ | |
2317 | && src[odv[0]].fr_reg >= 0 /* Value is from a register. */ | |
2318 | && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */ | |
2319 | && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */ | |
2320 | { | |
2321 | /* ISA encoding guarantees alignment. But, check it anyway. */ | |
2322 | gdb_assert ((odv[2] & 3) == 0); | |
2323 | dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2]; | |
2324 | } | |
2325 | break; | |
dbab50de MG |
2326 | /* If we end up inside Window Overflow / Underflow interrupt handler |
2327 | report an error because these handlers should have been handled | |
2328 | already in a different way. */ | |
2329 | case c0opc_l32e: | |
2330 | case c0opc_s32e: | |
2331 | case c0opc_rfwo: | |
2332 | case c0opc_rfwu: | |
2333 | return 1; | |
bdb4c075 | 2334 | default: |
dbab50de | 2335 | return 1; |
bdb4c075 | 2336 | } |
dbab50de | 2337 | return 0; |
bdb4c075 MG |
2338 | } |
2339 | ||
dbab50de | 2340 | /* Analyze prologue of the function at start address to determine if it uses |
bdb4c075 | 2341 | the Call0 ABI, and if so track register moves and linear modifications |
dbab50de MG |
2342 | in the prologue up to the PC or just beyond the prologue, whichever is |
2343 | first. An 'entry' instruction indicates non-Call0 ABI and the end of the | |
2344 | prologue. The prologue may overlap non-prologue instructions but is | |
2345 | guaranteed to end by the first flow-control instruction (jump, branch, | |
2346 | call or return). Since an optimized function may move information around | |
2347 | and change the stack frame arbitrarily during the prologue, the information | |
2348 | is guaranteed valid only at the point in the function indicated by the PC. | |
bdb4c075 MG |
2349 | May be used to skip the prologue or identify the ABI, w/o tracking. |
2350 | ||
2351 | Returns: Address of first instruction after prologue, or PC (whichever | |
2352 | is first), or 0, if decoding failed (in libisa). | |
2353 | Input args: | |
2354 | start Start address of function/prologue. | |
2355 | pc Program counter to stop at. Use 0 to continue to end of prologue. | |
2356 | If 0, avoids infinite run-on in corrupt code memory by bounding | |
2357 | the scan to the end of the function if that can be determined. | |
dbab50de | 2358 | nregs Number of general registers to track. |
bdb4c075 | 2359 | InOut args: |
dbab50de | 2360 | cache Xtensa frame cache. |
bdb4c075 MG |
2361 | |
2362 | Note that these may produce useful results even if decoding fails | |
2363 | because they begin with default assumptions that analysis may change. */ | |
2364 | ||
2365 | static CORE_ADDR | |
e17a4113 | 2366 | call0_analyze_prologue (struct gdbarch *gdbarch, |
dbab50de MG |
2367 | CORE_ADDR start, CORE_ADDR pc, |
2368 | int nregs, xtensa_frame_cache_t *cache) | |
bdb4c075 MG |
2369 | { |
2370 | CORE_ADDR ia; /* Current insn address in prologue. */ | |
2371 | CORE_ADDR ba = 0; /* Current address at base of insn buffer. */ | |
2372 | CORE_ADDR bt; /* Current address at top+1 of insn buffer. */ | |
948f8e3d | 2373 | gdb_byte ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue. */ |
bdb4c075 MG |
2374 | xtensa_isa isa; /* libisa ISA handle. */ |
2375 | xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */ | |
2376 | xtensa_format ifmt; /* libisa instruction format. */ | |
2377 | int ilen, islots, is; /* Instruction length, nbr slots, current slot. */ | |
2378 | xtensa_opcode opc; /* Opcode in current slot. */ | |
2379 | xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */ | |
2380 | int nods; /* Opcode number of operands. */ | |
2381 | unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */ | |
2382 | xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */ | |
2383 | int j; /* General loop counter. */ | |
2384 | int fail = 0; /* Set non-zero and exit, if decoding fails. */ | |
2385 | CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */ | |
2386 | CORE_ADDR end_pc; /* The PC for the lust function insn. */ | |
2387 | ||
2388 | struct symtab_and_line prologue_sal; | |
2389 | ||
2390 | DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n", | |
2391 | (int)start, (int)pc); | |
2392 | ||
2393 | /* Try to limit the scan to the end of the function if a non-zero pc | |
2394 | arg was not supplied to avoid probing beyond the end of valid memory. | |
2395 | If memory is full of garbage that classifies as c0opc_uninteresting. | |
2396 | If this fails (eg. if no symbols) pc ends up 0 as it was. | |
26c4b26f | 2397 | Initialize the Call0 frame and register tracking info. |
bdb4c075 MG |
2398 | Assume it's Call0 until an 'entry' instruction is encountered. |
2399 | Assume we may be in the prologue until we hit a flow control instr. */ | |
2400 | ||
2401 | rtmp = NULL; | |
8179e739 | 2402 | body_pc = UINT_MAX; |
bdb4c075 MG |
2403 | end_pc = 0; |
2404 | ||
2405 | /* Find out, if we have an information about the prologue from DWARF. */ | |
2406 | prologue_sal = find_pc_line (start, 0); | |
2407 | if (prologue_sal.line != 0) /* Found debug info. */ | |
2408 | body_pc = prologue_sal.end; | |
2409 | ||
2410 | /* If we are going to analyze the prologue in general without knowing about | |
2411 | the current PC, make the best assumtion for the end of the prologue. */ | |
2412 | if (pc == 0) | |
2413 | { | |
2414 | find_pc_partial_function (start, 0, NULL, &end_pc); | |
325fac50 | 2415 | body_pc = std::min (end_pc, body_pc); |
bdb4c075 MG |
2416 | } |
2417 | else | |
325fac50 | 2418 | body_pc = std::min (pc, body_pc); |
bdb4c075 | 2419 | |
dbab50de MG |
2420 | cache->call0 = 1; |
2421 | rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t)); | |
bdb4c075 MG |
2422 | |
2423 | isa = xtensa_default_isa; | |
2ff5e605 | 2424 | gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); |
bdb4c075 MG |
2425 | ins = xtensa_insnbuf_alloc (isa); |
2426 | slot = xtensa_insnbuf_alloc (isa); | |
2427 | ||
2428 | for (ia = start, bt = ia; ia < body_pc ; ia += ilen) | |
2429 | { | |
2430 | /* (Re)fill instruction buffer from memory if necessary, but do not | |
2431 | read memory beyond PC to be sure we stay within text section | |
2432 | (this protection only works if a non-zero pc is supplied). */ | |
2433 | ||
2434 | if (ia + xtensa_isa_maxlength (isa) > bt) | |
2435 | { | |
2436 | ba = ia; | |
2ff5e605 | 2437 | bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ : body_pc; |
dbab50de MG |
2438 | if (target_read_memory (ba, ibuf, bt - ba) != 0 ) |
2439 | error (_("Unable to read target memory ...")); | |
bdb4c075 MG |
2440 | } |
2441 | ||
2442 | /* Decode format information. */ | |
2443 | ||
2444 | xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); | |
2445 | ifmt = xtensa_format_decode (isa, ins); | |
2446 | if (ifmt == XTENSA_UNDEFINED) | |
2447 | { | |
2448 | fail = 1; | |
2449 | goto done; | |
2450 | } | |
2451 | ilen = xtensa_format_length (isa, ifmt); | |
2452 | if (ilen == XTENSA_UNDEFINED) | |
2453 | { | |
2454 | fail = 1; | |
2455 | goto done; | |
2456 | } | |
2457 | islots = xtensa_format_num_slots (isa, ifmt); | |
2458 | if (islots == XTENSA_UNDEFINED) | |
2459 | { | |
2460 | fail = 1; | |
2461 | goto done; | |
2462 | } | |
2463 | ||
2464 | /* Analyze a bundle or a single instruction, using a snapshot of | |
2465 | the register tracking info as input for the entire bundle so that | |
2466 | register changes do not take effect within this bundle. */ | |
ca3bf3bd | 2467 | |
bdb4c075 | 2468 | for (j = 0; j < nregs; ++j) |
dbab50de | 2469 | rtmp[j] = cache->c0.c0_rt[j]; |
bdb4c075 MG |
2470 | |
2471 | for (is = 0; is < islots; ++is) | |
2472 | { | |
2473 | /* Decode a slot and classify the opcode. */ | |
2474 | ||
2475 | fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot); | |
2476 | if (fail) | |
2477 | goto done; | |
2478 | ||
2479 | opc = xtensa_opcode_decode (isa, ifmt, is, slot); | |
dbab50de | 2480 | DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n", |
bdb4c075 MG |
2481 | (unsigned)ia, opc); |
2482 | if (opc == XTENSA_UNDEFINED) | |
2483 | opclass = c0opc_illegal; | |
2484 | else | |
2485 | opclass = call0_classify_opcode (isa, opc); | |
2486 | ||
2487 | /* Decide whether to track this opcode, ignore it, or bail out. */ | |
2488 | ||
2489 | switch (opclass) | |
2490 | { | |
2491 | case c0opc_illegal: | |
2492 | case c0opc_break: | |
2493 | fail = 1; | |
2494 | goto done; | |
2495 | ||
2496 | case c0opc_uninteresting: | |
2497 | continue; | |
2498 | ||
dbab50de MG |
2499 | case c0opc_flow: /* Flow control instructions stop analysis. */ |
2500 | case c0opc_rwxsr: /* RSR, WSR, XSR instructions stop analysis. */ | |
bdb4c075 MG |
2501 | goto done; |
2502 | ||
2503 | case c0opc_entry: | |
dbab50de | 2504 | cache->call0 = 0; |
bdb4c075 MG |
2505 | ia += ilen; /* Skip over 'entry' insn. */ |
2506 | goto done; | |
2507 | ||
2508 | default: | |
dbab50de | 2509 | cache->call0 = 1; |
bdb4c075 MG |
2510 | } |
2511 | ||
2512 | /* Only expected opcodes should get this far. */ | |
bdb4c075 MG |
2513 | |
2514 | /* Extract and decode the operands. */ | |
2515 | nods = xtensa_opcode_num_operands (isa, opc); | |
2516 | if (nods == XTENSA_UNDEFINED) | |
2517 | { | |
2518 | fail = 1; | |
2519 | goto done; | |
2520 | } | |
2521 | ||
2522 | for (j = 0; j < nods && j < C0_MAXOPDS; ++j) | |
2523 | { | |
2524 | fail = xtensa_operand_get_field (isa, opc, j, ifmt, | |
2525 | is, slot, &odv[j]); | |
2526 | if (fail) | |
2527 | goto done; | |
2528 | ||
2529 | fail = xtensa_operand_decode (isa, opc, j, &odv[j]); | |
2530 | if (fail) | |
2531 | goto done; | |
2532 | } | |
2533 | ||
2534 | /* Check operands to verify use of 'mov' assembler macro. */ | |
2535 | if (opclass == c0opc_mov && nods == 3) | |
2536 | { | |
2537 | if (odv[2] == odv[1]) | |
dbab50de MG |
2538 | { |
2539 | nods = 2; | |
2540 | if ((odv[0] == 1) && (odv[1] != 1)) | |
2541 | /* OR A1, An, An , where n != 1. | |
2542 | This means we are inside epilogue already. */ | |
2543 | goto done; | |
2544 | } | |
bdb4c075 MG |
2545 | else |
2546 | { | |
2547 | opclass = c0opc_uninteresting; | |
2548 | continue; | |
2549 | } | |
2550 | } | |
2551 | ||
2552 | /* Track register movement and modification for this operation. */ | |
dbab50de MG |
2553 | fail = call0_track_op (gdbarch, cache->c0.c0_rt, rtmp, |
2554 | opclass, nods, odv, ia, 1, cache); | |
2555 | if (fail) | |
2556 | goto done; | |
bdb4c075 MG |
2557 | } |
2558 | } | |
2559 | done: | |
2560 | DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n", | |
2561 | (unsigned)ia, fail ? "failed" : "succeeded"); | |
2562 | xtensa_insnbuf_free(isa, slot); | |
2563 | xtensa_insnbuf_free(isa, ins); | |
d4709618 | 2564 | return fail ? XTENSA_ISA_BADPC : ia; |
bdb4c075 MG |
2565 | } |
2566 | ||
5142f611 | 2567 | /* Initialize frame cache for the current frame in CALL0 ABI. */ |
bdb4c075 MG |
2568 | |
2569 | static void | |
5142f611 | 2570 | call0_frame_cache (struct frame_info *this_frame, |
dbab50de | 2571 | xtensa_frame_cache_t *cache, CORE_ADDR pc) |
bdb4c075 | 2572 | { |
5142f611 | 2573 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
e17a4113 | 2574 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
bdb4c075 MG |
2575 | CORE_ADDR start_pc; /* The beginning of the function. */ |
2576 | CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */ | |
2577 | CORE_ADDR sp, fp, ra; | |
dbab50de | 2578 | int fp_regnum = C0_SP, c0_hasfp = 0, c0_frmsz = 0, prev_sp = 0, to_stk; |
bdb4c075 | 2579 | |
dbab50de MG |
2580 | sp = get_frame_register_unsigned |
2581 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1); | |
2582 | fp = sp; /* Assume FP == SP until proven otherwise. */ | |
2583 | ||
bdb4c075 MG |
2584 | /* Find the beginning of the prologue of the function containing the PC |
2585 | and analyze it up to the PC or the end of the prologue. */ | |
2586 | ||
2587 | if (find_pc_partial_function (pc, NULL, &start_pc, NULL)) | |
2588 | { | |
dbab50de | 2589 | body_pc = call0_analyze_prologue (gdbarch, start_pc, pc, C0_NREGS, cache); |
d4709618 MG |
2590 | |
2591 | if (body_pc == XTENSA_ISA_BADPC) | |
dbab50de MG |
2592 | { |
2593 | warning_once (); | |
2594 | ra = 0; | |
2595 | goto finish_frame_analysis; | |
2596 | } | |
bdb4c075 MG |
2597 | } |
2598 | ||
bdb4c075 MG |
2599 | /* Get the frame information and FP (if used) at the current PC. |
2600 | If PC is in the prologue, the prologue analysis is more reliable | |
dbab50de MG |
2601 | than DWARF info. We don't not know for sure, if PC is in the prologue, |
2602 | but we do know no calls have yet taken place, so we can almost | |
bdb4c075 MG |
2603 | certainly rely on the prologue analysis. */ |
2604 | ||
2605 | if (body_pc <= pc) | |
2606 | { | |
2607 | /* Prologue analysis was successful up to the PC. | |
2608 | It includes the cases when PC == START_PC. */ | |
2609 | c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP; | |
2610 | /* c0_hasfp == true means there is a frame pointer because | |
2611 | we analyzed the prologue and found that cache->c0.c0_rt[C0_FP] | |
2612 | was derived from SP. Otherwise, it would be C0_FP. */ | |
2613 | fp_regnum = c0_hasfp ? C0_FP : C0_SP; | |
2614 | c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs; | |
6b50c0b0 | 2615 | fp_regnum += gdbarch_tdep (gdbarch)->a0_base; |
bdb4c075 MG |
2616 | } |
2617 | else /* No data from the prologue analysis. */ | |
2618 | { | |
2619 | c0_hasfp = 0; | |
6b50c0b0 | 2620 | fp_regnum = gdbarch_tdep (gdbarch)->a0_base + C0_SP; |
bdb4c075 MG |
2621 | c0_frmsz = 0; |
2622 | start_pc = pc; | |
2623 | } | |
2624 | ||
dbab50de MG |
2625 | if (cache->c0.c0_fpalign) |
2626 | { | |
2627 | /* This frame has a special prologue with a dynamic stack adjustment | |
2628 | to force an alignment, which is bigger than standard 16 bytes. */ | |
2629 | ||
2630 | CORE_ADDR unaligned_sp; | |
2631 | ||
2632 | if (cache->c0.c0_old_sp == C0_INEXP) | |
2633 | /* This can't be. Prologue code should be consistent. | |
2634 | Unaligned stack pointer should be saved in a spare register. */ | |
2635 | { | |
2636 | warning_once (); | |
2637 | ra = 0; | |
2638 | goto finish_frame_analysis; | |
2639 | } | |
2640 | ||
2641 | if (cache->c0.c0_sp_ofs == C0_NOSTK) | |
2642 | /* Saved unaligned value of SP is kept in a register. */ | |
2643 | unaligned_sp = get_frame_register_unsigned | |
2644 | (this_frame, gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_old_sp); | |
2645 | else | |
2646 | /* Get the value from stack. */ | |
2647 | unaligned_sp = (CORE_ADDR) | |
2648 | read_memory_integer (fp + cache->c0.c0_sp_ofs, 4, byte_order); | |
2649 | ||
2650 | prev_sp = unaligned_sp + c0_frmsz; | |
2651 | } | |
2652 | else | |
2653 | prev_sp = fp + c0_frmsz; | |
bdb4c075 MG |
2654 | |
2655 | /* Frame size from debug info or prologue tracking does not account for | |
2656 | alloca() and other dynamic allocations. Adjust frame size by FP - SP. */ | |
2657 | if (c0_hasfp) | |
2658 | { | |
5142f611 | 2659 | fp = get_frame_register_unsigned (this_frame, fp_regnum); |
bdb4c075 | 2660 | |
bdb4c075 MG |
2661 | /* Update the stack frame size. */ |
2662 | c0_frmsz += fp - sp; | |
2663 | } | |
2664 | ||
2665 | /* Get the return address (RA) from the stack if saved, | |
2666 | or try to get it from a register. */ | |
2667 | ||
2668 | to_stk = cache->c0.c0_rt[C0_RA].to_stk; | |
2669 | if (to_stk != C0_NOSTK) | |
2670 | ra = (CORE_ADDR) | |
e17a4113 UW |
2671 | read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk, |
2672 | 4, byte_order); | |
bdb4c075 MG |
2673 | |
2674 | else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST | |
2675 | && cache->c0.c0_rt[C0_RA].fr_ofs == 0) | |
2676 | { | |
dbab50de MG |
2677 | /* Special case for terminating backtrace at a function that wants to |
2678 | be seen as the outermost one. Such a function will clear it's RA (A0) | |
2679 | register to 0 in the prologue instead of saving its original value. */ | |
bdb4c075 MG |
2680 | ra = 0; |
2681 | } | |
2682 | else | |
2683 | { | |
dbab50de MG |
2684 | /* RA was copied to another register or (before any function call) may |
2685 | still be in the original RA register. This is not always reliable: | |
2686 | even in a leaf function, register tracking stops after prologue, and | |
2687 | even in prologue, non-prologue instructions (not tracked) may overwrite | |
2688 | RA or any register it was copied to. If likely in prologue or before | |
2689 | any call, use retracking info and hope for the best (compiler should | |
2690 | have saved RA in stack if not in a leaf function). If not in prologue, | |
2691 | too bad. */ | |
bdb4c075 MG |
2692 | |
2693 | int i; | |
1448a0a2 PM |
2694 | for (i = 0; |
2695 | (i < C0_NREGS) | |
2696 | && (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA); | |
bdb4c075 MG |
2697 | ++i); |
2698 | if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA) | |
2699 | i = C0_RA; | |
5142f611 | 2700 | if (i < C0_NREGS) |
bdb4c075 | 2701 | { |
5142f611 MG |
2702 | ra = get_frame_register_unsigned |
2703 | (this_frame, | |
2704 | gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_rt[i].fr_reg); | |
bdb4c075 MG |
2705 | } |
2706 | else ra = 0; | |
2707 | } | |
2708 | ||
dbab50de | 2709 | finish_frame_analysis: |
bdb4c075 MG |
2710 | cache->pc = start_pc; |
2711 | cache->ra = ra; | |
2712 | /* RA == 0 marks the outermost frame. Do not go past it. */ | |
2713 | cache->prev_sp = (ra != 0) ? prev_sp : 0; | |
2714 | cache->c0.fp_regnum = fp_regnum; | |
2715 | cache->c0.c0_frmsz = c0_frmsz; | |
2716 | cache->c0.c0_hasfp = c0_hasfp; | |
2717 | cache->c0.c0_fp = fp; | |
2718 | } | |
2719 | ||
08b9c608 MG |
2720 | static CORE_ADDR a0_saved; |
2721 | static CORE_ADDR a7_saved; | |
2722 | static CORE_ADDR a11_saved; | |
2723 | static int a0_was_saved; | |
2724 | static int a7_was_saved; | |
2725 | static int a11_was_saved; | |
2726 | ||
68d6df83 | 2727 | /* Simulate L32E instruction: AT <-- ref (AS + offset). */ |
08b9c608 MG |
2728 | static void |
2729 | execute_l32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb) | |
2730 | { | |
2731 | int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb); | |
2732 | int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb); | |
2733 | CORE_ADDR addr = xtensa_read_register (asreg) + offset; | |
2734 | unsigned int spilled_value | |
2735 | = read_memory_unsigned_integer (addr, 4, gdbarch_byte_order (gdbarch)); | |
2736 | ||
2737 | if ((at == 0) && !a0_was_saved) | |
2738 | { | |
2739 | a0_saved = xtensa_read_register (atreg); | |
2740 | a0_was_saved = 1; | |
2741 | } | |
2742 | else if ((at == 7) && !a7_was_saved) | |
2743 | { | |
2744 | a7_saved = xtensa_read_register (atreg); | |
2745 | a7_was_saved = 1; | |
2746 | } | |
2747 | else if ((at == 11) && !a11_was_saved) | |
2748 | { | |
2749 | a11_saved = xtensa_read_register (atreg); | |
2750 | a11_was_saved = 1; | |
2751 | } | |
2752 | ||
2753 | xtensa_write_register (atreg, spilled_value); | |
2754 | } | |
2755 | ||
68d6df83 | 2756 | /* Simulate S32E instruction: AT --> ref (AS + offset). */ |
08b9c608 MG |
2757 | static void |
2758 | execute_s32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb) | |
2759 | { | |
2760 | int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb); | |
2761 | int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb); | |
2762 | CORE_ADDR addr = xtensa_read_register (asreg) + offset; | |
2763 | ULONGEST spilled_value = xtensa_read_register (atreg); | |
2764 | ||
2765 | write_memory_unsigned_integer (addr, 4, | |
2766 | gdbarch_byte_order (gdbarch), | |
2767 | spilled_value); | |
2768 | } | |
2769 | ||
2770 | #define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200 | |
2771 | ||
68d6df83 MG |
2772 | typedef enum |
2773 | { | |
08b9c608 MG |
2774 | xtWindowOverflow, |
2775 | xtWindowUnderflow, | |
2776 | xtNoExceptionHandler | |
2777 | } xtensa_exception_handler_t; | |
2778 | ||
68d6df83 | 2779 | /* Execute instruction stream from current PC until hitting RFWU or RFWO. |
08b9c608 MG |
2780 | Return type of Xtensa Window Interrupt Handler on success. */ |
2781 | static xtensa_exception_handler_t | |
2782 | execute_code (struct gdbarch *gdbarch, CORE_ADDR current_pc, CORE_ADDR wb) | |
2783 | { | |
2784 | xtensa_isa isa; | |
2785 | xtensa_insnbuf ins, slot; | |
948f8e3d | 2786 | gdb_byte ibuf[XTENSA_ISA_BSZ]; |
08b9c608 MG |
2787 | CORE_ADDR ia, bt, ba; |
2788 | xtensa_format ifmt; | |
2789 | int ilen, islots, is; | |
2790 | xtensa_opcode opc; | |
2791 | int insn_num = 0; | |
08b9c608 MG |
2792 | void (*func) (struct gdbarch *, int, int, int, CORE_ADDR); |
2793 | ||
19afdd07 | 2794 | uint32_t at, as, offset; |
08b9c608 MG |
2795 | |
2796 | /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */ | |
2797 | int WindowUnderflow12 = (current_pc & 0x1ff) >= 0x140; | |
2798 | ||
2799 | isa = xtensa_default_isa; | |
2800 | gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa)); | |
2801 | ins = xtensa_insnbuf_alloc (isa); | |
2802 | slot = xtensa_insnbuf_alloc (isa); | |
2803 | ba = 0; | |
2804 | ia = current_pc; | |
2805 | bt = ia; | |
2806 | ||
2807 | a0_was_saved = 0; | |
2808 | a7_was_saved = 0; | |
2809 | a11_was_saved = 0; | |
2810 | ||
2811 | while (insn_num++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN) | |
2812 | { | |
2813 | if (ia + xtensa_isa_maxlength (isa) > bt) | |
2814 | { | |
2815 | ba = ia; | |
2816 | bt = (ba + XTENSA_ISA_BSZ); | |
2817 | if (target_read_memory (ba, ibuf, bt - ba) != 0) | |
2818 | return xtNoExceptionHandler; | |
2819 | } | |
2820 | xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0); | |
2821 | ifmt = xtensa_format_decode (isa, ins); | |
2822 | if (ifmt == XTENSA_UNDEFINED) | |
2823 | return xtNoExceptionHandler; | |
2824 | ilen = xtensa_format_length (isa, ifmt); | |
2825 | if (ilen == XTENSA_UNDEFINED) | |
2826 | return xtNoExceptionHandler; | |
2827 | islots = xtensa_format_num_slots (isa, ifmt); | |
2828 | if (islots == XTENSA_UNDEFINED) | |
2829 | return xtNoExceptionHandler; | |
2830 | for (is = 0; is < islots; ++is) | |
2831 | { | |
2832 | if (xtensa_format_get_slot (isa, ifmt, is, ins, slot)) | |
2833 | return xtNoExceptionHandler; | |
2834 | opc = xtensa_opcode_decode (isa, ifmt, is, slot); | |
2835 | if (opc == XTENSA_UNDEFINED) | |
2836 | return xtNoExceptionHandler; | |
2837 | switch (call0_classify_opcode (isa, opc)) | |
2838 | { | |
2839 | case c0opc_illegal: | |
2840 | case c0opc_flow: | |
2841 | case c0opc_entry: | |
2842 | case c0opc_break: | |
2843 | /* We expect none of them here. */ | |
2844 | return xtNoExceptionHandler; | |
2845 | case c0opc_l32e: | |
2846 | func = execute_l32e; | |
2847 | break; | |
2848 | case c0opc_s32e: | |
2849 | func = execute_s32e; | |
2850 | break; | |
2851 | case c0opc_rfwo: /* RFWO. */ | |
2852 | /* Here, we return from WindowOverflow handler and, | |
2853 | if we stopped at the very beginning, which means | |
2854 | A0 was saved, we have to restore it now. */ | |
2855 | if (a0_was_saved) | |
2856 | { | |
2857 | int arreg = arreg_number (gdbarch, | |
2858 | gdbarch_tdep (gdbarch)->a0_base, | |
2859 | wb); | |
2860 | xtensa_write_register (arreg, a0_saved); | |
2861 | } | |
2862 | return xtWindowOverflow; | |
2863 | case c0opc_rfwu: /* RFWU. */ | |
2864 | /* Here, we return from WindowUnderflow handler. | |
2865 | Let's see if either A7 or A11 has to be restored. */ | |
2866 | if (WindowUnderflow12) | |
2867 | { | |
2868 | if (a11_was_saved) | |
2869 | { | |
2870 | int arreg = arreg_number (gdbarch, | |
2871 | gdbarch_tdep (gdbarch)->a0_base + 11, | |
2872 | wb); | |
2873 | xtensa_write_register (arreg, a11_saved); | |
2874 | } | |
2875 | } | |
2876 | else if (a7_was_saved) | |
2877 | { | |
2878 | int arreg = arreg_number (gdbarch, | |
2879 | gdbarch_tdep (gdbarch)->a0_base + 7, | |
2880 | wb); | |
2881 | xtensa_write_register (arreg, a7_saved); | |
2882 | } | |
2883 | return xtWindowUnderflow; | |
2884 | default: /* Simply skip this insns. */ | |
2885 | continue; | |
2886 | } | |
2887 | ||
2888 | /* Decode arguments for L32E / S32E and simulate their execution. */ | |
2889 | if ( xtensa_opcode_num_operands (isa, opc) != 3 ) | |
2890 | return xtNoExceptionHandler; | |
2891 | if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, &at)) | |
2892 | return xtNoExceptionHandler; | |
2893 | if (xtensa_operand_decode (isa, opc, 0, &at)) | |
2894 | return xtNoExceptionHandler; | |
2895 | if (xtensa_operand_get_field (isa, opc, 1, ifmt, is, slot, &as)) | |
2896 | return xtNoExceptionHandler; | |
2897 | if (xtensa_operand_decode (isa, opc, 1, &as)) | |
2898 | return xtNoExceptionHandler; | |
2899 | if (xtensa_operand_get_field (isa, opc, 2, ifmt, is, slot, &offset)) | |
2900 | return xtNoExceptionHandler; | |
2901 | if (xtensa_operand_decode (isa, opc, 2, &offset)) | |
2902 | return xtNoExceptionHandler; | |
2903 | ||
2904 | (*func) (gdbarch, at, as, offset, wb); | |
2905 | } | |
2906 | ||
2907 | ia += ilen; | |
2908 | } | |
2909 | return xtNoExceptionHandler; | |
2910 | } | |
2911 | ||
2912 | /* Handle Window Overflow / Underflow exception frames. */ | |
2913 | ||
2914 | static void | |
2915 | xtensa_window_interrupt_frame_cache (struct frame_info *this_frame, | |
2916 | xtensa_frame_cache_t *cache, | |
2917 | CORE_ADDR pc) | |
2918 | { | |
2919 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2920 | CORE_ADDR ps, wb, ws, ra; | |
2921 | int epc1_regnum, i, regnum; | |
2922 | xtensa_exception_handler_t eh_type; | |
2923 | ||
2924 | /* Read PS, WB, and WS from the hardware. Note that PS register | |
2925 | must be present, if Windowed ABI is supported. */ | |
2926 | ps = xtensa_read_register (gdbarch_ps_regnum (gdbarch)); | |
2927 | wb = xtensa_read_register (gdbarch_tdep (gdbarch)->wb_regnum); | |
2928 | ws = xtensa_read_register (gdbarch_tdep (gdbarch)->ws_regnum); | |
2929 | ||
2930 | /* Execute all the remaining instructions from Window Interrupt Handler | |
2931 | by simulating them on the remote protocol level. On return, set the | |
2932 | type of Xtensa Window Interrupt Handler, or report an error. */ | |
2933 | eh_type = execute_code (gdbarch, pc, wb); | |
2934 | if (eh_type == xtNoExceptionHandler) | |
2935 | error (_("\ | |
2936 | Unable to decode Xtensa Window Interrupt Handler's code.")); | |
2937 | ||
2938 | cache->ps = ps ^ PS_EXC; /* Clear the exception bit in PS. */ | |
2939 | cache->call0 = 0; /* It's Windowed ABI. */ | |
2940 | ||
2941 | /* All registers for the cached frame will be alive. */ | |
2942 | for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++) | |
2943 | cache->wd.aregs[i] = -1; | |
2944 | ||
2945 | if (eh_type == xtWindowOverflow) | |
2946 | cache->wd.ws = ws ^ (1 << wb); | |
2947 | else /* eh_type == xtWindowUnderflow. */ | |
2948 | cache->wd.ws = ws | (1 << wb); | |
2949 | ||
2950 | cache->wd.wb = (ps & 0xf00) >> 8; /* Set WB to OWB. */ | |
2951 | regnum = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base, | |
2952 | cache->wd.wb); | |
2953 | ra = xtensa_read_register (regnum); | |
2954 | cache->wd.callsize = WINSIZE (ra); | |
2955 | cache->prev_sp = xtensa_read_register (regnum + 1); | |
2956 | /* Set regnum to a frame pointer of the frame being cached. */ | |
2957 | regnum = xtensa_scan_prologue (gdbarch, pc); | |
2958 | regnum = arreg_number (gdbarch, | |
2959 | gdbarch_tdep (gdbarch)->a0_base + regnum, | |
2960 | cache->wd.wb); | |
2961 | cache->base = get_frame_register_unsigned (this_frame, regnum); | |
2962 | ||
2963 | /* Read PC of interrupted function from EPC1 register. */ | |
2964 | epc1_regnum = xtensa_find_register_by_name (gdbarch,"epc1"); | |
2965 | if (epc1_regnum < 0) | |
2966 | error(_("Unable to read Xtensa register EPC1")); | |
2967 | cache->ra = xtensa_read_register (epc1_regnum); | |
2968 | cache->pc = get_frame_func (this_frame); | |
2969 | } | |
2970 | ||
bdb4c075 MG |
2971 | |
2972 | /* Skip function prologue. | |
2973 | ||
2974 | Return the pc of the first instruction after prologue. GDB calls this to | |
2975 | find the address of the first line of the function or (if there is no line | |
2976 | number information) to skip the prologue for planting breakpoints on | |
2977 | function entries. Use debug info (if present) or prologue analysis to skip | |
2978 | the prologue to achieve reliable debugging behavior. For windowed ABI, | |
2979 | only the 'entry' instruction is skipped. It is not strictly necessary to | |
2980 | skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to | |
2981 | backtrace at any point in the prologue, however certain potential hazards | |
2982 | are avoided and a more "normal" debugging experience is ensured by | |
2983 | skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG). | |
2984 | For example, if we don't skip the prologue: | |
2985 | - Some args may not yet have been saved to the stack where the debug | |
2986 | info expects to find them (true anyway when only 'entry' is skipped); | |
2987 | - Software breakpoints ('break' instrs) may not have been unplanted | |
2988 | when the prologue analysis is done on initializing the frame cache, | |
2989 | and breaks in the prologue will throw off the analysis. | |
ca3bf3bd DJ |
2990 | |
2991 | If we have debug info ( line-number info, in particular ) we simply skip | |
2992 | the code associated with the first function line effectively skipping | |
bdb4c075 | 2993 | the prologue code. It works even in cases like |
ca3bf3bd DJ |
2994 | |
2995 | int main() | |
2996 | { int local_var = 1; | |
2997 | .... | |
2998 | } | |
2999 | ||
3000 | because, for this source code, both Xtensa compilers will generate two | |
3001 | separate entries ( with the same line number ) in dwarf line-number | |
3002 | section to make sure there is a boundary between the prologue code and | |
3003 | the rest of the function. | |
3004 | ||
bdb4c075 MG |
3005 | If there is no debug info, we need to analyze the code. */ |
3006 | ||
3007 | /* #define DONT_SKIP_PROLOGUE */ | |
ca3bf3bd | 3008 | |
63807e1d | 3009 | static CORE_ADDR |
6093d2eb | 3010 | xtensa_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
ca3bf3bd | 3011 | { |
bdb4c075 MG |
3012 | struct symtab_and_line prologue_sal; |
3013 | CORE_ADDR body_pc; | |
3014 | ||
ca3bf3bd DJ |
3015 | DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc); |
3016 | ||
bdb4c075 MG |
3017 | #if DONT_SKIP_PROLOGUE |
3018 | return start_pc; | |
3019 | #endif | |
3020 | ||
3021 | /* Try to find first body line from debug info. */ | |
3022 | ||
3023 | prologue_sal = find_pc_line (start_pc, 0); | |
3024 | if (prologue_sal.line != 0) /* Found debug info. */ | |
ca3bf3bd | 3025 | { |
f976a05d MG |
3026 | /* In Call0, it is possible to have a function with only one instruction |
3027 | ('ret') resulting from a one-line optimized function that does nothing. | |
3028 | In that case, prologue_sal.end may actually point to the start of the | |
3029 | next function in the text section, causing a breakpoint to be set at | |
3030 | the wrong place. Check, if the end address is within a different | |
3031 | function, and if so return the start PC. We know we have symbol | |
3032 | information. */ | |
ca3bf3bd | 3033 | |
bdb4c075 MG |
3034 | CORE_ADDR end_func; |
3035 | ||
f976a05d MG |
3036 | if ((gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only) |
3037 | && call0_ret (start_pc, prologue_sal.end)) | |
3038 | return start_pc; | |
3039 | ||
bdb4c075 MG |
3040 | find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL); |
3041 | if (end_func != start_pc) | |
ca3bf3bd DJ |
3042 | return start_pc; |
3043 | ||
bdb4c075 | 3044 | return prologue_sal.end; |
ca3bf3bd | 3045 | } |
ca3bf3bd | 3046 | |
bdb4c075 | 3047 | /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */ |
dbab50de MG |
3048 | body_pc = call0_analyze_prologue (gdbarch, start_pc, 0, 0, |
3049 | xtensa_alloc_frame_cache (0)); | |
bdb4c075 MG |
3050 | return body_pc != 0 ? body_pc : start_pc; |
3051 | } | |
ca3bf3bd DJ |
3052 | |
3053 | /* Verify the current configuration. */ | |
ca3bf3bd DJ |
3054 | static void |
3055 | xtensa_verify_config (struct gdbarch *gdbarch) | |
3056 | { | |
d7e74731 PA |
3057 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3058 | string_file log; | |
ca3bf3bd DJ |
3059 | |
3060 | /* Verify that we got a reasonable number of AREGS. */ | |
3061 | if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs) | |
d7e74731 | 3062 | log.printf (_("\ |
bdb4c075 | 3063 | \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"), |
d7e74731 | 3064 | tdep->num_aregs); |
ca3bf3bd DJ |
3065 | |
3066 | /* Verify that certain registers exist. */ | |
bdb4c075 | 3067 | |
ca3bf3bd | 3068 | if (tdep->pc_regnum == -1) |
d7e74731 | 3069 | log.printf (_("\n\tpc_regnum: No PC register")); |
bdb4c075 | 3070 | if (tdep->isa_use_exceptions && tdep->ps_regnum == -1) |
d7e74731 | 3071 | log.printf (_("\n\tps_regnum: No PS register")); |
bdb4c075 MG |
3072 | |
3073 | if (tdep->isa_use_windowed_registers) | |
3074 | { | |
3075 | if (tdep->wb_regnum == -1) | |
d7e74731 | 3076 | log.printf (_("\n\twb_regnum: No WB register")); |
bdb4c075 | 3077 | if (tdep->ws_regnum == -1) |
d7e74731 | 3078 | log.printf (_("\n\tws_regnum: No WS register")); |
bdb4c075 | 3079 | if (tdep->ar_base == -1) |
d7e74731 | 3080 | log.printf (_("\n\tar_base: No AR registers")); |
bdb4c075 MG |
3081 | } |
3082 | ||
ca3bf3bd | 3083 | if (tdep->a0_base == -1) |
d7e74731 | 3084 | log.printf (_("\n\ta0_base: No Ax registers")); |
ca3bf3bd | 3085 | |
d7e74731 | 3086 | if (!log.empty ()) |
ca3bf3bd | 3087 | internal_error (__FILE__, __LINE__, |
d7e74731 | 3088 | _("the following are invalid: %s"), log.c_str ()); |
ca3bf3bd DJ |
3089 | } |
3090 | ||
94a0e877 MG |
3091 | |
3092 | /* Derive specific register numbers from the array of registers. */ | |
3093 | ||
63807e1d | 3094 | static void |
94a0e877 MG |
3095 | xtensa_derive_tdep (struct gdbarch_tdep *tdep) |
3096 | { | |
3097 | xtensa_register_t* rmap; | |
3098 | int n, max_size = 4; | |
3099 | ||
3100 | tdep->num_regs = 0; | |
3101 | tdep->num_nopriv_regs = 0; | |
3102 | ||
3103 | /* Special registers 0..255 (core). */ | |
3104 | #define XTENSA_DBREGN_SREG(n) (0x0200+(n)) | |
f74f865e MF |
3105 | /* User registers 0..255. */ |
3106 | #define XTENSA_DBREGN_UREG(n) (0x0300+(n)) | |
94a0e877 MG |
3107 | |
3108 | for (rmap = tdep->regmap, n = 0; rmap->target_number != -1; n++, rmap++) | |
3109 | { | |
3110 | if (rmap->target_number == 0x0020) | |
3111 | tdep->pc_regnum = n; | |
3112 | else if (rmap->target_number == 0x0100) | |
3113 | tdep->ar_base = n; | |
3114 | else if (rmap->target_number == 0x0000) | |
3115 | tdep->a0_base = n; | |
3116 | else if (rmap->target_number == XTENSA_DBREGN_SREG(72)) | |
3117 | tdep->wb_regnum = n; | |
3118 | else if (rmap->target_number == XTENSA_DBREGN_SREG(73)) | |
3119 | tdep->ws_regnum = n; | |
3120 | else if (rmap->target_number == XTENSA_DBREGN_SREG(233)) | |
3121 | tdep->debugcause_regnum = n; | |
3122 | else if (rmap->target_number == XTENSA_DBREGN_SREG(232)) | |
3123 | tdep->exccause_regnum = n; | |
3124 | else if (rmap->target_number == XTENSA_DBREGN_SREG(238)) | |
3125 | tdep->excvaddr_regnum = n; | |
3126 | else if (rmap->target_number == XTENSA_DBREGN_SREG(0)) | |
3127 | tdep->lbeg_regnum = n; | |
3128 | else if (rmap->target_number == XTENSA_DBREGN_SREG(1)) | |
3129 | tdep->lend_regnum = n; | |
3130 | else if (rmap->target_number == XTENSA_DBREGN_SREG(2)) | |
3131 | tdep->lcount_regnum = n; | |
3132 | else if (rmap->target_number == XTENSA_DBREGN_SREG(3)) | |
3133 | tdep->sar_regnum = n; | |
3134 | else if (rmap->target_number == XTENSA_DBREGN_SREG(5)) | |
3135 | tdep->litbase_regnum = n; | |
3136 | else if (rmap->target_number == XTENSA_DBREGN_SREG(230)) | |
3137 | tdep->ps_regnum = n; | |
f74f865e MF |
3138 | else if (rmap->target_number == XTENSA_DBREGN_UREG(231)) |
3139 | tdep->threadptr_regnum = n; | |
94a0e877 MG |
3140 | #if 0 |
3141 | else if (rmap->target_number == XTENSA_DBREGN_SREG(226)) | |
3142 | tdep->interrupt_regnum = n; | |
3143 | else if (rmap->target_number == XTENSA_DBREGN_SREG(227)) | |
3144 | tdep->interrupt2_regnum = n; | |
3145 | else if (rmap->target_number == XTENSA_DBREGN_SREG(224)) | |
3146 | tdep->cpenable_regnum = n; | |
3147 | #endif | |
3148 | ||
3149 | if (rmap->byte_size > max_size) | |
3150 | max_size = rmap->byte_size; | |
3151 | if (rmap->mask != 0 && tdep->num_regs == 0) | |
3152 | tdep->num_regs = n; | |
3153 | /* Find out out how to deal with priveleged registers. | |
3154 | ||
3155 | if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0 | |
3156 | && tdep->num_nopriv_regs == 0) | |
3157 | tdep->num_nopriv_regs = n; | |
3158 | */ | |
3159 | if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0 | |
3160 | && tdep->num_regs == 0) | |
3161 | tdep->num_regs = n; | |
3162 | } | |
3163 | ||
3164 | /* Number of pseudo registers. */ | |
3165 | tdep->num_pseudo_regs = n - tdep->num_regs; | |
3166 | ||
3167 | /* Empirically determined maximum sizes. */ | |
3168 | tdep->max_register_raw_size = max_size; | |
3169 | tdep->max_register_virtual_size = max_size; | |
3170 | } | |
3171 | ||
ca3bf3bd DJ |
3172 | /* Module "constructor" function. */ |
3173 | ||
94a0e877 MG |
3174 | extern struct gdbarch_tdep xtensa_tdep; |
3175 | ||
ca3bf3bd DJ |
3176 | static struct gdbarch * |
3177 | xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
3178 | { | |
3179 | struct gdbarch_tdep *tdep; | |
3180 | struct gdbarch *gdbarch; | |
ca3bf3bd DJ |
3181 | |
3182 | DEBUGTRACE ("gdbarch_init()\n"); | |
3183 | ||
a4398628 MF |
3184 | if (!xtensa_default_isa) |
3185 | xtensa_default_isa = xtensa_isa_init (0, 0); | |
3186 | ||
ca3bf3bd | 3187 | /* We have to set the byte order before we call gdbarch_alloc. */ |
94a0e877 | 3188 | info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE; |
ca3bf3bd | 3189 | |
94a0e877 | 3190 | tdep = &xtensa_tdep; |
ca3bf3bd | 3191 | gdbarch = gdbarch_alloc (&info, tdep); |
94a0e877 | 3192 | xtensa_derive_tdep (tdep); |
ca3bf3bd DJ |
3193 | |
3194 | /* Verify our configuration. */ | |
3195 | xtensa_verify_config (gdbarch); | |
dbab50de | 3196 | xtensa_session_once_reported = 0; |
ca3bf3bd | 3197 | |
53375380 PA |
3198 | set_gdbarch_wchar_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
3199 | set_gdbarch_wchar_signed (gdbarch, 0); | |
3200 | ||
bdb4c075 | 3201 | /* Pseudo-Register read/write. */ |
ca3bf3bd DJ |
3202 | set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read); |
3203 | set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write); | |
3204 | ||
3205 | /* Set target information. */ | |
3206 | set_gdbarch_num_regs (gdbarch, tdep->num_regs); | |
3207 | set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs); | |
3208 | set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1); | |
3209 | set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum); | |
3210 | set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum); | |
3211 | ||
ba2b1c56 | 3212 | /* Renumber registers for known formats (stabs and dwarf2). */ |
ca3bf3bd | 3213 | set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); |
ca3bf3bd DJ |
3214 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); |
3215 | ||
3216 | /* We provide our own function to get register information. */ | |
3217 | set_gdbarch_register_name (gdbarch, xtensa_register_name); | |
3218 | set_gdbarch_register_type (gdbarch, xtensa_register_type); | |
3219 | ||
581e13c1 | 3220 | /* To call functions from GDB using dummy frame. */ |
ca3bf3bd DJ |
3221 | set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call); |
3222 | ||
3223 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); | |
3224 | ||
3225 | set_gdbarch_return_value (gdbarch, xtensa_return_value); | |
3226 | ||
3227 | /* Advance PC across any prologue instructions to reach "real" code. */ | |
3228 | set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue); | |
3229 | ||
3230 | /* Stack grows downward. */ | |
3231 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
3232 | ||
3233 | /* Set breakpoints. */ | |
04180708 YQ |
3234 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
3235 | xtensa_breakpoint_kind_from_pc); | |
3236 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
3237 | xtensa_sw_breakpoint_from_kind); | |
ca3bf3bd DJ |
3238 | |
3239 | /* After breakpoint instruction or illegal instruction, pc still | |
3240 | points at break instruction, so don't decrement. */ | |
3241 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
3242 | ||
3243 | /* We don't skip args. */ | |
3244 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
3245 | ||
3246 | set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc); | |
3247 | ||
3248 | set_gdbarch_frame_align (gdbarch, xtensa_frame_align); | |
3249 | ||
5142f611 | 3250 | set_gdbarch_dummy_id (gdbarch, xtensa_dummy_id); |
ca3bf3bd DJ |
3251 | |
3252 | /* Frame handling. */ | |
3253 | frame_base_set_default (gdbarch, &xtensa_frame_base); | |
5142f611 MG |
3254 | frame_unwind_append_unwinder (gdbarch, &xtensa_unwind); |
3255 | dwarf2_append_unwinders (gdbarch); | |
ca3bf3bd | 3256 | |
ca3bf3bd DJ |
3257 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
3258 | ||
3259 | xtensa_add_reggroups (gdbarch); | |
3260 | set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p); | |
3261 | ||
97094034 AA |
3262 | set_gdbarch_iterate_over_regset_sections |
3263 | (gdbarch, xtensa_iterate_over_regset_sections); | |
ca3bf3bd | 3264 | |
ee967b5f MG |
3265 | set_solib_svr4_fetch_link_map_offsets |
3266 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); | |
3267 | ||
40045d91 MF |
3268 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
3269 | gdbarch_init_osabi (info, gdbarch); | |
3270 | ||
ca3bf3bd DJ |
3271 | return gdbarch; |
3272 | } | |
3273 | ||
ca3bf3bd | 3274 | static void |
6b50c0b0 | 3275 | xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
ca3bf3bd DJ |
3276 | { |
3277 | error (_("xtensa_dump_tdep(): not implemented")); | |
3278 | } | |
3279 | ||
ca3bf3bd DJ |
3280 | void |
3281 | _initialize_xtensa_tdep (void) | |
3282 | { | |
ca3bf3bd DJ |
3283 | gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep); |
3284 | xtensa_init_reggroups (); | |
3285 | ||
ccce17b0 YQ |
3286 | add_setshow_zuinteger_cmd ("xtensa", |
3287 | class_maintenance, | |
3288 | &xtensa_debug_level, | |
581e13c1 MS |
3289 | _("Set Xtensa debugging."), |
3290 | _("Show Xtensa debugging."), _("\ | |
ca3bf3bd DJ |
3291 | When non-zero, Xtensa-specific debugging is enabled. \ |
3292 | Can be 1, 2, 3, or 4 indicating the level of debugging."), | |
ccce17b0 YQ |
3293 | NULL, |
3294 | NULL, | |
3295 | &setdebuglist, &showdebuglist); | |
ca3bf3bd | 3296 | } |