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ca3bf3bd DJ |
1 | /* Target-dependent code for the Xtensa port of GDB, the GNU debugger. |
2 | ||
6aba47ca | 3 | Copyright (C) 2003, 2005, 2006, 2007 Free Software Foundation, Inc. |
ca3bf3bd DJ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 51 Franklin Street, Fifth Floor, | |
20 | Boston, MA 02110-1301, USA. */ | |
21 | ||
22 | #include "defs.h" | |
23 | #include "frame.h" | |
24 | #include "symtab.h" | |
25 | #include "symfile.h" | |
26 | #include "objfiles.h" | |
27 | #include "gdbtypes.h" | |
28 | #include "gdbcore.h" | |
29 | #include "value.h" | |
30 | #include "dis-asm.h" | |
31 | #include "inferior.h" | |
32 | #include "floatformat.h" | |
33 | #include "regcache.h" | |
34 | #include "reggroups.h" | |
35 | #include "regset.h" | |
36 | ||
37 | #include "dummy-frame.h" | |
38 | #include "elf/dwarf2.h" | |
39 | #include "dwarf2-frame.h" | |
40 | #include "dwarf2loc.h" | |
41 | #include "frame.h" | |
42 | #include "frame-base.h" | |
43 | #include "frame-unwind.h" | |
44 | ||
45 | #include "arch-utils.h" | |
46 | #include "gdbarch.h" | |
47 | #include "remote.h" | |
48 | #include "serial.h" | |
49 | ||
50 | #include "command.h" | |
51 | #include "gdbcmd.h" | |
52 | #include "gdb_assert.h" | |
53 | ||
54 | #include "xtensa-tdep.h" | |
55 | ||
56 | ||
57 | static int xtensa_debug_level = 0; | |
58 | ||
59 | #define DEBUGWARN(args...) \ | |
60 | if (xtensa_debug_level > 0) \ | |
61 | fprintf_unfiltered (gdb_stdlog, "(warn ) " args) | |
62 | ||
63 | #define DEBUGINFO(args...) \ | |
64 | if (xtensa_debug_level > 1) \ | |
65 | fprintf_unfiltered (gdb_stdlog, "(info ) " args) | |
66 | ||
67 | #define DEBUGTRACE(args...) \ | |
68 | if (xtensa_debug_level > 2) \ | |
69 | fprintf_unfiltered (gdb_stdlog, "(trace) " args) | |
70 | ||
71 | #define DEBUGVERB(args...) \ | |
72 | if (xtensa_debug_level > 3) \ | |
73 | fprintf_unfiltered (gdb_stdlog, "(verb ) " args) | |
74 | ||
75 | ||
76 | /* According to the ABI, the SP must be aligned to 16-byte boundaries. */ | |
77 | ||
78 | #define SP_ALIGNMENT 16 | |
79 | ||
80 | ||
81 | /* We use a6 through a11 for passing arguments to a function called by GDB. */ | |
82 | ||
83 | #define ARGS_FIRST_REG A6_REGNUM | |
84 | #define ARGS_NUM_REGS 6 | |
85 | #define REGISTER_SIZE 4 | |
86 | ||
87 | ||
88 | /* Extract the call size from the return address or ps register. */ | |
89 | ||
90 | #define PS_CALLINC_SHIFT 16 | |
91 | #define PS_CALLINC_MASK 0x00030000 | |
92 | #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT) | |
93 | #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3)) | |
94 | ||
95 | ||
96 | /* Convert a live Ax register number to the corresponding Areg number. */ | |
97 | ||
98 | #define AREG_NUMBER(r, wb) \ | |
99 | ((((r) - A0_REGNUM + (((wb) & WB_MASK)<<WB_SHIFT)) & AREGS_MASK) + AR_BASE) | |
100 | ||
101 | ||
102 | /* Define prototypes. */ | |
103 | ||
104 | extern struct gdbarch_tdep *xtensa_config_tdep (struct gdbarch_info *); | |
105 | extern int xtensa_config_byte_order (struct gdbarch_info *); | |
106 | ||
107 | ||
108 | /* XTENSA_IS_ENTRY tests whether the first byte of an instruction | |
109 | indicates that the instruction is an ENTRY instruction. */ | |
110 | ||
111 | #define XTENSA_IS_ENTRY(op1) \ | |
4c6b5505 UW |
112 | ((gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) \ |
113 | ? ((op1) == 0x6c) : ((op1) == 0x36)) | |
ca3bf3bd DJ |
114 | |
115 | #define XTENSA_ENTRY_LENGTH 3 | |
116 | ||
117 | ||
118 | /* windowing_enabled() returns true, if windowing is enabled. | |
119 | WOE must be set to 1; EXCM to 0. | |
120 | Note: We assume that EXCM is always 0 for XEA1. */ | |
121 | ||
122 | static inline int | |
123 | windowing_enabled (CORE_ADDR ps) | |
124 | { | |
125 | return ((ps & (1 << 4)) == 0 && (ps & (1 << 18)) != 0); | |
126 | } | |
127 | ||
128 | /* Return the window size of the previous call to the function from which we | |
129 | have just returned. | |
130 | ||
131 | This function is used to extract the return value after a called function | |
132 | has returned to the callee. On Xtensa, the register that holds the return | |
133 | value (from the perspective of the caller) depends on what call | |
134 | instruction was used. For now, we are assuming that the call instruction | |
135 | precedes the current address, so we simply analyze the call instruction. | |
136 | If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4' | |
137 | method to call the inferior function. */ | |
138 | ||
139 | static int | |
140 | extract_call_winsize (CORE_ADDR pc) | |
141 | { | |
142 | int winsize = 4; /* Default: No call, e.g. dummy frame. */ | |
143 | int insn; | |
ff7a4c00 | 144 | gdb_byte buf[4]; |
ca3bf3bd DJ |
145 | |
146 | DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc); | |
147 | ||
148 | /* Read the previous instruction (should be a call[x]{4|8|12}. */ | |
149 | read_memory (pc-3, buf, 3); | |
150 | insn = extract_unsigned_integer (buf, 3); | |
151 | ||
152 | /* Decode call instruction: | |
153 | Little Endian | |
154 | call{0,4,8,12} OFFSET || {00,01,10,11} || 0101 | |
155 | callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000 | |
156 | Big Endian | |
157 | call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET | |
158 | callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */ | |
159 | ||
160 | /* Lookup call insn. | |
161 | (Return the default value (4) if we can't find a valid call insn. */ | |
162 | ||
4c6b5505 | 163 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) |
ca3bf3bd DJ |
164 | { |
165 | if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0)) | |
166 | winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12 */ | |
167 | } | |
168 | else | |
169 | { | |
170 | if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03)) | |
171 | winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12 */ | |
172 | } | |
173 | return winsize; | |
174 | } | |
175 | ||
176 | ||
177 | /* REGISTER INFORMATION */ | |
178 | ||
179 | /* Returns the name of a register. */ | |
180 | ||
181 | static const char * | |
182 | xtensa_register_name (int regnum) | |
183 | { | |
184 | /* Return the name stored in the register map. */ | |
f57d151a UW |
185 | if (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch) |
186 | + gdbarch_num_pseudo_regs (current_gdbarch)) | |
ca3bf3bd DJ |
187 | return REGMAP[regnum].name; |
188 | ||
189 | /* Invalid register number. */ | |
190 | internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum); | |
191 | return 0; | |
192 | } | |
193 | ||
194 | ||
195 | /* Return the type of a register. Create a new type, if necessary. */ | |
196 | ||
197 | static struct ctype_cache | |
198 | { | |
199 | struct ctype_cache *next; | |
200 | int size; | |
201 | struct type *virtual_type; | |
202 | } *type_entries = NULL; | |
203 | ||
204 | static struct type * | |
205 | xtensa_register_type (struct gdbarch *gdbarch, int regnum) | |
206 | { | |
207 | /* Return signed integer for ARx and Ax registers. */ | |
208 | if ((regnum >= AR_BASE && regnum < AR_BASE + NUM_AREGS) | |
209 | || (regnum >= A0_BASE && regnum < A0_BASE + 16)) | |
210 | return builtin_type_int; | |
211 | ||
3e8c568d | 212 | if (regnum == gdbarch_pc_regnum (current_gdbarch) || regnum == A1_REGNUM) |
ca3bf3bd DJ |
213 | return lookup_pointer_type (builtin_type_void); |
214 | ||
215 | /* Return the stored type for all other registers. */ | |
f57d151a UW |
216 | else if (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch) |
217 | + gdbarch_num_pseudo_regs (current_gdbarch)) | |
ca3bf3bd DJ |
218 | { |
219 | xtensa_register_t* reg = ®MAP[regnum]; | |
220 | ||
221 | /* Set ctype for this register (only the first time we ask for it). */ | |
222 | ||
223 | if (reg->ctype == 0) | |
224 | { | |
225 | struct ctype_cache *tp; | |
226 | int size = reg->byte_size; | |
227 | ||
228 | /* We always use the memory representation, even if the register | |
229 | width is smaller. */ | |
230 | switch (size) | |
231 | { | |
232 | case 1: | |
233 | reg->ctype = builtin_type_uint8; | |
234 | break; | |
235 | ||
236 | case 2: | |
237 | reg->ctype = builtin_type_uint16; | |
238 | break; | |
239 | ||
240 | case 4: | |
241 | reg->ctype = builtin_type_uint32; | |
242 | break; | |
243 | ||
244 | case 8: | |
245 | reg->ctype = builtin_type_uint64; | |
246 | break; | |
247 | ||
248 | case 16: | |
249 | reg->ctype = builtin_type_uint128; | |
250 | break; | |
251 | ||
252 | default: | |
253 | for (tp = type_entries; tp != NULL; tp = tp->next) | |
254 | if (tp->size == size) | |
255 | break; | |
256 | ||
257 | if (tp == NULL) | |
258 | { | |
259 | char *name = xmalloc (16); | |
260 | tp = xmalloc (sizeof (struct ctype_cache)); | |
261 | tp->next = type_entries; | |
262 | type_entries = tp; | |
263 | tp->size = size; | |
264 | ||
265 | sprintf (name, "int%d", size * 8); | |
266 | tp->virtual_type = init_type (TYPE_CODE_INT, size, | |
267 | TYPE_FLAG_UNSIGNED, name, | |
268 | NULL); | |
269 | } | |
270 | ||
271 | reg->ctype = tp->virtual_type; | |
272 | } | |
273 | } | |
274 | return reg->ctype; | |
275 | } | |
276 | ||
277 | /* Invalid register number. */ | |
278 | internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum); | |
279 | return 0; | |
280 | } | |
281 | ||
282 | ||
283 | /* Returns the 'local' register number for stubs, dwarf2, etc. | |
284 | The debugging information enumerates registers starting from 0 for A0 | |
285 | to n for An. So, we only have to add the base number for A0. */ | |
286 | ||
287 | static int | |
288 | xtensa_reg_to_regnum (int regnum) | |
289 | { | |
290 | int i; | |
291 | ||
292 | if (regnum >= 0 && regnum < 16) | |
293 | return A0_BASE + regnum; | |
294 | ||
f57d151a UW |
295 | for (i = 0; |
296 | i < gdbarch_num_regs (current_gdbarch) | |
297 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
298 | i++) | |
ca3bf3bd DJ |
299 | if (regnum == REGMAP[i].target_number) |
300 | return i; | |
301 | ||
302 | /* Invalid register number. */ | |
303 | internal_error (__FILE__, __LINE__, | |
304 | _("invalid dwarf/stabs register number %d"), regnum); | |
305 | return 0; | |
306 | } | |
307 | ||
308 | ||
309 | /* Handle the special case of masked registers. */ | |
310 | ||
311 | /* Write the bits of a masked register to the various registers that | |
312 | are combined into this register. Only the masked areas of these | |
313 | registers are modified; the other fields are untouched. | |
314 | (Note: The size of masked registers is always less or equal 32 bits.) */ | |
315 | ||
316 | static void | |
9c9acae0 UW |
317 | xtensa_register_write_masked (struct regcache *regcache, |
318 | xtensa_register_t *reg, const gdb_byte *buffer) | |
ca3bf3bd DJ |
319 | { |
320 | unsigned int value[(MAX_REGISTER_SIZE + 3) / 4]; | |
321 | ||
322 | const xtensa_mask_t *mask = reg->mask; | |
323 | ||
324 | int shift = 0; /* Shift for next mask (mod 32). */ | |
325 | int start, size; /* Start bit and size of current mask. */ | |
326 | ||
327 | unsigned int *ptr = value; | |
328 | unsigned int regval, m, mem = 0; | |
329 | ||
330 | int bytesize = reg->byte_size; | |
331 | int bitsize = bytesize * 8; | |
332 | int i, r; | |
333 | ||
334 | DEBUGTRACE ("xtensa_register_write_masked ()\n"); | |
335 | ||
336 | /* Copy the masked register to host byte-order. */ | |
4c6b5505 | 337 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
338 | for (i = 0; i < bytesize; i++) |
339 | { | |
340 | mem >>= 8; | |
341 | mem |= (buffer[bytesize - i - 1] << 24); | |
342 | if ((i & 3) == 3) | |
343 | *ptr++ = mem; | |
344 | } | |
345 | else | |
346 | for (i = 0; i < bytesize; i++) | |
347 | { | |
348 | mem >>= 8; | |
349 | mem |= (buffer[i] << 24); | |
350 | if ((i & 3) == 3) | |
351 | *ptr++ = mem; | |
352 | } | |
353 | ||
354 | /* We might have to shift the final value: | |
355 | bytesize & 3 == 0 -> nothing to do, we use the full 32 bits, | |
356 | bytesize & 3 == x -> shift (4-x) * 8. */ | |
357 | ||
358 | *ptr = mem >> (((0 - bytesize) & 3) * 8); | |
359 | ptr = value; | |
360 | mem = *ptr; | |
361 | ||
362 | /* Write the bits to the masked areas of the other registers. */ | |
363 | for (i = 0; i < mask->count; i++) | |
364 | { | |
365 | start = mask->mask[i].bit_start; | |
366 | size = mask->mask[i].bit_size; | |
367 | regval = mem >> shift; | |
368 | ||
369 | if ((shift += size) > bitsize) | |
370 | error (_("size of all masks is larger than the register")); | |
371 | ||
372 | if (shift >= 32) | |
373 | { | |
374 | mem = *(++ptr); | |
375 | shift -= 32; | |
376 | bitsize -= 32; | |
377 | ||
378 | if (shift > 0) | |
379 | regval |= mem << (size - shift); | |
380 | } | |
381 | ||
382 | /* Make sure we have a valid register. */ | |
383 | r = mask->mask[i].reg_num; | |
384 | if (r >= 0 && size > 0) | |
385 | { | |
386 | /* Don't overwrite the unmasked areas. */ | |
9c9acae0 UW |
387 | ULONGEST old_val; |
388 | regcache_cooked_read_unsigned (regcache, r, &old_val); | |
ca3bf3bd DJ |
389 | m = 0xffffffff >> (32 - size) << start; |
390 | regval <<= start; | |
9c9acae0 UW |
391 | regval = (regval & m) | (old_val & ~m); |
392 | regcache_cooked_write_unsigned (regcache, r, regval); | |
ca3bf3bd DJ |
393 | } |
394 | } | |
395 | } | |
396 | ||
397 | ||
398 | /* Read the masked areas of the registers and assemble it into a single | |
399 | register. */ | |
400 | ||
401 | static void | |
9c9acae0 UW |
402 | xtensa_register_read_masked (struct regcache *regcache, |
403 | xtensa_register_t *reg, gdb_byte *buffer) | |
ca3bf3bd DJ |
404 | { |
405 | unsigned int value[(MAX_REGISTER_SIZE + 3) / 4]; | |
406 | ||
407 | const xtensa_mask_t *mask = reg->mask; | |
408 | ||
409 | int shift = 0; | |
410 | int start, size; | |
411 | ||
412 | unsigned int *ptr = value; | |
413 | unsigned int regval, mem = 0; | |
414 | ||
415 | int bytesize = reg->byte_size; | |
416 | int bitsize = bytesize * 8; | |
417 | int i; | |
418 | ||
419 | DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n", | |
420 | reg->name == 0 ? "" : reg->name); | |
421 | ||
422 | /* Assemble the register from the masked areas of other registers. */ | |
423 | for (i = 0; i < mask->count; i++) | |
424 | { | |
425 | int r = mask->mask[i].reg_num; | |
9c9acae0 UW |
426 | if (r >= 0) |
427 | { | |
428 | ULONGEST val; | |
429 | regcache_cooked_read_unsigned (regcache, r, &val); | |
430 | regval = (unsigned int) val; | |
431 | } | |
432 | else | |
433 | regval = 0; | |
434 | ||
ca3bf3bd DJ |
435 | start = mask->mask[i].bit_start; |
436 | size = mask->mask[i].bit_size; | |
437 | ||
438 | regval >>= start; | |
439 | ||
440 | if (size < 32) | |
441 | regval &= (0xffffffff >> (32 - size)); | |
442 | ||
443 | mem |= regval << shift; | |
444 | ||
445 | if ((shift += size) > bitsize) | |
446 | error (_("size of all masks is larger than the register")); | |
447 | ||
448 | if (shift >= 32) | |
449 | { | |
450 | *ptr++ = mem; | |
451 | bitsize -= 32; | |
452 | shift -= 32; | |
453 | ||
454 | if (shift == 0) | |
455 | mem = 0; | |
456 | else | |
457 | mem = regval >> (size - shift); | |
458 | } | |
459 | } | |
460 | ||
461 | if (shift > 0) | |
462 | *ptr = mem; | |
463 | ||
464 | /* Copy value to target byte order. */ | |
465 | ptr = value; | |
466 | mem = *ptr; | |
467 | ||
4c6b5505 | 468 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
469 | for (i = 0; i < bytesize; i++) |
470 | { | |
471 | if ((i & 3) == 0) | |
472 | mem = *ptr++; | |
473 | buffer[bytesize - i - 1] = mem & 0xff; | |
474 | mem >>= 8; | |
475 | } | |
476 | else | |
477 | for (i = 0; i < bytesize; i++) | |
478 | { | |
479 | if ((i & 3) == 0) | |
480 | mem = *ptr++; | |
481 | buffer[i] = mem & 0xff; | |
482 | mem >>= 8; | |
483 | } | |
484 | } | |
485 | ||
486 | ||
487 | /* Read pseudo registers. */ | |
488 | ||
489 | static void | |
490 | xtensa_pseudo_register_read (struct gdbarch *gdbarch, | |
491 | struct regcache *regcache, | |
492 | int regnum, | |
493 | gdb_byte *buffer) | |
494 | { | |
495 | DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n", | |
496 | regnum, xtensa_register_name (regnum)); | |
497 | ||
498 | /* Check if it is FP (renumber it in this case -> A0...A15). */ | |
499 | if (regnum == FP_ALIAS) | |
500 | error (_("trying to read FP")); | |
501 | ||
502 | /* Read aliases a0..a15. */ | |
503 | if (regnum >= A0_REGNUM && regnum <= A15_REGNUM) | |
504 | { | |
ff7a4c00 | 505 | gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE); |
ca3bf3bd DJ |
506 | |
507 | regcache_raw_read (regcache, WB_REGNUM, buf); | |
508 | regnum = AREG_NUMBER (regnum, extract_unsigned_integer (buf, 4)); | |
509 | } | |
510 | ||
511 | /* We can always read 'regular' registers. */ | |
f57d151a | 512 | if (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch)) |
ca3bf3bd DJ |
513 | regcache_raw_read (regcache, regnum, buffer); |
514 | ||
515 | /* Pseudo registers. */ | |
f57d151a UW |
516 | else if (regnum >= 0 |
517 | && regnum < gdbarch_num_regs (current_gdbarch) | |
518 | + gdbarch_num_pseudo_regs (current_gdbarch)) | |
ca3bf3bd DJ |
519 | { |
520 | xtensa_register_t *reg = ®MAP[regnum]; | |
521 | xtensa_register_type_t type = reg->type; | |
522 | int flags = XTENSA_TARGET_FLAGS; | |
523 | ||
524 | /* Can we read Unknown or Unmapped registers? */ | |
525 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) | |
526 | { | |
527 | if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
528 | { | |
529 | warning (_("cannot read register %s"), | |
530 | xtensa_register_name (regnum)); | |
531 | return; | |
532 | } | |
533 | } | |
534 | ||
535 | /* Some targets cannot read TIE register files. */ | |
536 | else if (type == xtRegisterTypeTieRegfile) | |
537 | { | |
538 | /* Use 'fetch' to get register? */ | |
539 | if (flags & xtTargetFlagsUseFetchStore) | |
540 | { | |
541 | warning (_("cannot read register")); | |
542 | return; | |
543 | } | |
544 | ||
545 | /* On some targets (esp. simulators), we can always read the reg. */ | |
546 | else if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
547 | { | |
548 | warning (_("cannot read register")); | |
549 | return; | |
550 | } | |
551 | } | |
552 | ||
553 | /* We can always read mapped registers. */ | |
554 | else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState) | |
555 | { | |
9c9acae0 | 556 | xtensa_register_read_masked (regcache, reg, buffer); |
ca3bf3bd DJ |
557 | return; |
558 | } | |
559 | ||
560 | /* Assume that we can read the register. */ | |
561 | regcache_raw_read (regcache, regnum, buffer); | |
562 | } | |
563 | ||
564 | else | |
565 | internal_error (__FILE__, __LINE__, | |
566 | _("invalid register number %d"), regnum); | |
567 | } | |
568 | ||
569 | ||
570 | /* Write pseudo registers. */ | |
571 | ||
572 | static void | |
573 | xtensa_pseudo_register_write (struct gdbarch *gdbarch, | |
574 | struct regcache *regcache, | |
575 | int regnum, | |
576 | const gdb_byte *buffer) | |
577 | { | |
578 | DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n", | |
579 | regnum, xtensa_register_name (regnum)); | |
580 | ||
581 | /* Check if this is FP. */ | |
582 | if (regnum == FP_ALIAS) | |
583 | error (_("trying to write FP")); | |
584 | ||
585 | /* Renumber register, if aliase a0..a15. */ | |
586 | if (regnum >= A0_REGNUM && regnum <= A15_REGNUM) | |
587 | { | |
ff7a4c00 | 588 | gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE); |
ca3bf3bd DJ |
589 | unsigned int wb; |
590 | ||
591 | regcache_raw_read (regcache, WB_REGNUM, buf); | |
592 | regnum = AREG_NUMBER (regnum, extract_unsigned_integer (buf, 4)); | |
593 | } | |
594 | ||
595 | /* We can always write 'core' registers. | |
596 | Note: We might have converted Ax->ARy. */ | |
f57d151a | 597 | if (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch)) |
ca3bf3bd DJ |
598 | regcache_raw_write (regcache, regnum, buffer); |
599 | ||
600 | /* Pseudo registers. */ | |
f57d151a UW |
601 | else if (regnum >= 0 |
602 | && regnum < gdbarch_num_regs (current_gdbarch) | |
603 | + gdbarch_num_pseudo_regs (current_gdbarch)) | |
ca3bf3bd DJ |
604 | { |
605 | xtensa_register_t *reg = ®MAP[regnum]; | |
606 | xtensa_register_type_t type = reg->type; | |
607 | int flags = XTENSA_TARGET_FLAGS; | |
608 | ||
609 | /* On most targets, we can't write registers of type "Unknown" | |
610 | or "Unmapped". */ | |
611 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) | |
612 | { | |
613 | if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
614 | { | |
615 | warning (_("cannot write register %s"), | |
616 | xtensa_register_name (regnum)); | |
617 | return; | |
618 | } | |
619 | } | |
620 | ||
621 | /* Some targets cannot read TIE register files. */ | |
622 | else if (type == xtRegisterTypeTieRegfile) | |
623 | { | |
624 | /* Use 'store' to get register? */ | |
625 | if (flags & xtTargetFlagsUseFetchStore) | |
626 | { | |
627 | warning (_("cannot write register")); | |
628 | return; | |
629 | } | |
630 | ||
631 | /* On some targets (esp. simulators), we can always write | |
632 | the register. */ | |
633 | ||
634 | else if ((flags & xtTargetFlagsNonVisibleRegs) == 0) | |
635 | { | |
636 | warning (_("cannot write register")); | |
637 | return; | |
638 | } | |
639 | } | |
640 | ||
641 | /* We can always write mapped registers. */ | |
642 | else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState) | |
643 | { | |
9c9acae0 | 644 | xtensa_register_write_masked (regcache, reg, buffer); |
ca3bf3bd DJ |
645 | return; |
646 | } | |
647 | ||
648 | /* Assume that we can write the register. */ | |
649 | regcache_raw_write (regcache, regnum, buffer); | |
650 | } | |
651 | ||
652 | else | |
653 | internal_error (__FILE__, __LINE__, | |
654 | _("invalid register number %d"), regnum); | |
655 | } | |
656 | ||
657 | ||
658 | static struct reggroup *xtensa_ar_reggroup; | |
659 | static struct reggroup *xtensa_user_reggroup; | |
660 | static struct reggroup *xtensa_vectra_reggroup; | |
661 | ||
662 | static void | |
663 | xtensa_init_reggroups (void) | |
664 | { | |
665 | xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP); | |
666 | xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP); | |
667 | xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP); | |
668 | } | |
669 | ||
670 | ||
671 | static void | |
672 | xtensa_add_reggroups (struct gdbarch *gdbarch) | |
673 | { | |
674 | reggroup_add (gdbarch, all_reggroup); | |
675 | reggroup_add (gdbarch, save_reggroup); | |
676 | reggroup_add (gdbarch, restore_reggroup); | |
677 | reggroup_add (gdbarch, system_reggroup); | |
678 | reggroup_add (gdbarch, vector_reggroup); /* vectra */ | |
679 | reggroup_add (gdbarch, general_reggroup); /* core */ | |
680 | reggroup_add (gdbarch, float_reggroup); /* float */ | |
681 | ||
682 | reggroup_add (gdbarch, xtensa_ar_reggroup); /* ar */ | |
683 | reggroup_add (gdbarch, xtensa_user_reggroup); /* user */ | |
684 | reggroup_add (gdbarch, xtensa_vectra_reggroup); /* vectra */ | |
685 | } | |
686 | ||
687 | ||
688 | #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \ | |
689 | | XTENSA_REGISTER_FLAGS_WRITABLE \ | |
690 | | XTENSA_REGISTER_FLAGS_VOLATILE) | |
691 | ||
692 | #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \ | |
693 | | XTENSA_REGISTER_FLAGS_WRITABLE) | |
694 | ||
695 | static int | |
696 | xtensa_register_reggroup_p (struct gdbarch *gdbarch, | |
697 | int regnum, | |
698 | struct reggroup *group) | |
699 | { | |
700 | xtensa_register_t* reg = ®MAP[regnum]; | |
701 | xtensa_register_type_t type = reg->type; | |
702 | xtensa_register_group_t rg = reg->group; | |
703 | ||
704 | /* First, skip registers that are not visible to this target | |
705 | (unknown and unmapped registers when not using ISS). */ | |
706 | ||
707 | if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown) | |
708 | return 0; | |
709 | if (group == all_reggroup) | |
710 | return 1; | |
711 | if (group == xtensa_ar_reggroup) | |
712 | return rg & xtRegisterGroupAddrReg; | |
713 | if (group == xtensa_user_reggroup) | |
714 | return rg & xtRegisterGroupUser; | |
715 | if (group == float_reggroup) | |
716 | return rg & xtRegisterGroupFloat; | |
717 | if (group == general_reggroup) | |
718 | return rg & xtRegisterGroupGeneral; | |
719 | if (group == float_reggroup) | |
720 | return rg & xtRegisterGroupFloat; | |
721 | if (group == system_reggroup) | |
722 | return rg & xtRegisterGroupState; | |
723 | if (group == vector_reggroup || group == xtensa_vectra_reggroup) | |
724 | return rg & xtRegisterGroupVectra; | |
725 | if (group == save_reggroup || group == restore_reggroup) | |
f57d151a | 726 | return (regnum < gdbarch_num_regs (current_gdbarch) |
ca3bf3bd DJ |
727 | && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID); |
728 | else | |
729 | return 1; | |
730 | } | |
731 | ||
732 | ||
733 | /* CORE FILE SUPPORT */ | |
734 | ||
735 | /* Supply register REGNUM from the buffer specified by GREGS and LEN | |
736 | in the general-purpose register set REGSET to register cache | |
737 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
738 | ||
739 | static void | |
740 | xtensa_supply_gregset (const struct regset *regset, | |
741 | struct regcache *rc, | |
742 | int regnum, | |
743 | const void *gregs, | |
744 | size_t len) | |
745 | { | |
746 | const xtensa_elf_gregset_t *regs = gregs; | |
747 | int i; | |
748 | ||
749 | DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...) \n", regnum); | |
750 | ||
3e8c568d UW |
751 | if (regnum == gdbarch_pc_regnum (current_gdbarch) || regnum == -1) |
752 | regcache_raw_supply (rc, | |
753 | gdbarch_pc_regnum (current_gdbarch), | |
754 | (char *) ®s->pc); | |
755 | if (regnum == gdbarch_ps_regnum (current_gdbarch) || regnum == -1) | |
756 | regcache_raw_supply (rc, gdbarch_ps_regnum (current_gdbarch), | |
757 | (char *) ®s->ps); | |
ca3bf3bd DJ |
758 | if (regnum == WB_REGNUM || regnum == -1) |
759 | regcache_raw_supply (rc, WB_REGNUM, (char *) ®s->windowbase); | |
760 | if (regnum == WS_REGNUM || regnum == -1) | |
761 | regcache_raw_supply (rc, WS_REGNUM, (char *) ®s->windowstart); | |
762 | if (regnum == LBEG_REGNUM || regnum == -1) | |
763 | regcache_raw_supply (rc, LBEG_REGNUM, (char *) ®s->lbeg); | |
764 | if (regnum == LEND_REGNUM || regnum == -1) | |
765 | regcache_raw_supply (rc, LEND_REGNUM, (char *) ®s->lend); | |
766 | if (regnum == LCOUNT_REGNUM || regnum == -1) | |
767 | regcache_raw_supply (rc, LCOUNT_REGNUM, (char *) ®s->lcount); | |
768 | if (regnum == SAR_REGNUM || regnum == -1) | |
769 | regcache_raw_supply (rc, SAR_REGNUM, (char *) ®s->sar); | |
770 | if (regnum == EXCCAUSE_REGNUM || regnum == -1) | |
771 | regcache_raw_supply (rc, EXCCAUSE_REGNUM, (char *) ®s->exccause); | |
772 | if (regnum == EXCVADDR_REGNUM || regnum == -1) | |
773 | regcache_raw_supply (rc, EXCVADDR_REGNUM, (char *) ®s->excvaddr); | |
774 | if (regnum >= AR_BASE && regnum < AR_BASE + NUM_AREGS) | |
775 | regcache_raw_supply (rc, regnum, (char *) ®s->ar[regnum - AR_BASE]); | |
776 | else if (regnum == -1) | |
777 | { | |
778 | for (i = 0; i < NUM_AREGS; ++i) | |
779 | regcache_raw_supply (rc, AR_BASE + i, (char *) ®s->ar[i]); | |
780 | } | |
781 | } | |
782 | ||
783 | ||
784 | /* Xtensa register set. */ | |
785 | ||
786 | static struct regset | |
787 | xtensa_gregset = | |
788 | { | |
789 | NULL, | |
790 | xtensa_supply_gregset | |
791 | }; | |
792 | ||
793 | ||
794 | /* Return the appropriate register set for the core section identified | |
795 | by SECT_NAME and SECT_SIZE. */ | |
796 | ||
797 | static const struct regset * | |
798 | xtensa_regset_from_core_section (struct gdbarch *core_arch, | |
799 | const char *sect_name, | |
800 | size_t sect_size) | |
801 | { | |
802 | DEBUGTRACE ("xtensa_regset_from_core_section " | |
803 | "(..., sect_name==\"%s\", sect_size==%x) \n", | |
cb5c8c39 | 804 | sect_name, (int) sect_size); |
ca3bf3bd DJ |
805 | |
806 | if (strcmp (sect_name, ".reg") == 0 | |
807 | && sect_size >= sizeof(xtensa_elf_gregset_t)) | |
808 | return &xtensa_gregset; | |
809 | ||
810 | return NULL; | |
811 | } | |
812 | ||
813 | ||
814 | /* F R A M E */ | |
815 | ||
816 | /* We currently don't support the call0-abi, so we have at max. 12 registers | |
817 | saved on the stack. */ | |
818 | ||
819 | #define XTENSA_NUM_SAVED_AREGS 12 | |
820 | ||
821 | typedef struct xtensa_frame_cache | |
822 | { | |
823 | CORE_ADDR base; | |
824 | CORE_ADDR pc; | |
825 | CORE_ADDR ra; /* The raw return address; use to compute call_inc. */ | |
826 | CORE_ADDR ps; | |
827 | int wb; /* Base for this frame; -1 if not in regfile. */ | |
828 | int callsize; /* Call size to next frame. */ | |
829 | int ws; | |
830 | CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS]; | |
831 | CORE_ADDR prev_sp; | |
832 | } xtensa_frame_cache_t; | |
833 | ||
834 | ||
835 | static struct xtensa_frame_cache * | |
836 | xtensa_alloc_frame_cache (void) | |
837 | { | |
838 | xtensa_frame_cache_t *cache; | |
839 | int i; | |
840 | ||
841 | DEBUGTRACE ("xtensa_alloc_frame_cache ()\n"); | |
842 | ||
843 | cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t); | |
844 | ||
845 | cache->base = 0; | |
846 | cache->pc = 0; | |
847 | cache->ra = 0; | |
848 | cache->wb = 0; | |
849 | cache->ps = 0; | |
850 | cache->callsize = -1; | |
851 | cache->prev_sp = 0; | |
852 | ||
853 | for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++) | |
854 | cache->aregs[i] = -1; | |
855 | ||
856 | return cache; | |
857 | } | |
858 | ||
859 | ||
860 | static CORE_ADDR | |
861 | xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) | |
862 | { | |
863 | return address & ~15; | |
864 | } | |
865 | ||
866 | ||
867 | static CORE_ADDR | |
868 | xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
869 | { | |
ff7a4c00 | 870 | gdb_byte buf[8]; |
ca3bf3bd DJ |
871 | |
872 | DEBUGTRACE ("xtensa_unwind_pc (next_frame = %p)\n", next_frame); | |
873 | ||
3e8c568d | 874 | frame_unwind_register (next_frame, gdbarch_pc_regnum (current_gdbarch), buf); |
ca3bf3bd DJ |
875 | |
876 | DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) | |
877 | extract_typed_address (buf, builtin_type_void_func_ptr)); | |
878 | ||
879 | return extract_typed_address (buf, builtin_type_void_func_ptr); | |
880 | } | |
881 | ||
882 | ||
883 | static struct frame_id | |
884 | xtensa_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
885 | { | |
886 | CORE_ADDR pc, fp; | |
ff7a4c00 | 887 | gdb_byte buf[4]; |
ca3bf3bd DJ |
888 | |
889 | /* next_frame->prev is a dummy frame. Return a frame ID of that frame. */ | |
890 | ||
891 | DEBUGTRACE ("xtensa_unwind_dummy_id ()\n"); | |
892 | ||
893 | pc = frame_pc_unwind (next_frame); | |
894 | frame_unwind_register (next_frame, A1_REGNUM, buf); | |
895 | fp = extract_unsigned_integer (buf, 4); | |
896 | ||
897 | /* Make dummy frame ID unique by adding a constant. */ | |
898 | return frame_id_build (fp+SP_ALIGNMENT, pc); | |
899 | } | |
900 | ||
901 | ||
902 | static struct xtensa_frame_cache * | |
903 | xtensa_frame_cache (struct frame_info *next_frame, void **this_cache) | |
904 | { | |
905 | xtensa_frame_cache_t *cache; | |
906 | char buf[4]; | |
907 | CORE_ADDR ra, wb, ws, pc, sp, ps; | |
908 | char op1; | |
909 | ||
910 | DEBUGTRACE ("xtensa_frame_cache (next_frame %p, *this_cache %p)\n", | |
911 | next_frame, this_cache ? *this_cache : (void*)0xdeadbeef); | |
912 | ||
913 | /* Already cached? */ | |
914 | if (*this_cache) | |
915 | return *this_cache; | |
916 | ||
917 | /* Get pristine xtensa-frame. */ | |
918 | cache = xtensa_alloc_frame_cache (); | |
919 | *this_cache = cache; | |
920 | ||
921 | /* Get windowbase, windowstart, ps, and pc. */ | |
922 | wb = frame_unwind_register_unsigned (next_frame, WB_REGNUM); | |
923 | ws = frame_unwind_register_unsigned (next_frame, WS_REGNUM); | |
3e8c568d UW |
924 | ps = frame_unwind_register_unsigned (next_frame, |
925 | gdbarch_ps_regnum (current_gdbarch)); | |
926 | pc = frame_unwind_register_unsigned (next_frame, | |
927 | gdbarch_pc_regnum (current_gdbarch)); | |
ca3bf3bd DJ |
928 | |
929 | op1 = read_memory_integer (pc, 1); | |
9c9acae0 | 930 | if (XTENSA_IS_ENTRY (op1) || !windowing_enabled (ps)) |
ca3bf3bd | 931 | { |
9c9acae0 | 932 | int callinc = CALLINC (ps); |
ca3bf3bd DJ |
933 | ra = frame_unwind_register_unsigned (next_frame, |
934 | A0_REGNUM + callinc * 4); | |
935 | ||
936 | DEBUGINFO("[xtensa_frame_cache] 'entry' at 0x%08x\n (callinc = %d)", | |
937 | (int)pc, callinc); | |
938 | ||
939 | /* ENTRY hasn't been executed yet, therefore callsize is still 0. */ | |
940 | cache->callsize = 0; | |
941 | cache->wb = wb; | |
942 | cache->ws = ws; | |
9c9acae0 | 943 | cache->prev_sp = frame_unwind_register_unsigned (next_frame, A1_REGNUM); |
ca3bf3bd DJ |
944 | } |
945 | else | |
946 | { | |
947 | ra = frame_unwind_register_unsigned (next_frame, A0_REGNUM); | |
948 | cache->callsize = WINSIZE (ra); | |
949 | cache->wb = (wb - (cache->callsize / 4)) & ((NUM_AREGS / 4) - 1); | |
950 | cache->ws = ws & ~(1 << wb); | |
951 | } | |
952 | ||
93d42b30 | 953 | cache->pc = ((frame_func_unwind (next_frame, NORMAL_FRAME) & 0xc0000000) |
ca3bf3bd DJ |
954 | | (ra & 0x3fffffff)); |
955 | cache->ps = (ps & ~PS_CALLINC_MASK) | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT); | |
956 | ||
957 | ||
958 | /* Note: We could also calculate the location on stack when we actually | |
959 | access the register. However, this approach, saving the location | |
960 | in the cache frame, is probably easier to support the call0 ABI. */ | |
961 | ||
962 | if (cache->ws == 0) | |
963 | { | |
964 | int i; | |
965 | ||
966 | /* Set A0...A3. */ | |
967 | sp = frame_unwind_register_unsigned (next_frame, A1_REGNUM) - 16; | |
968 | ||
969 | for (i = 0; i < 4; i++, sp += 4) | |
970 | { | |
971 | cache->aregs[i] = sp; | |
972 | } | |
973 | ||
974 | if (cache->callsize > 4) | |
975 | { | |
976 | /* Set A4...A7/A11. */ | |
977 | ||
978 | sp = (CORE_ADDR) read_memory_integer (sp - 12, 4); | |
979 | sp = (CORE_ADDR) read_memory_integer (sp - 12, 4); | |
980 | sp -= cache->callsize * 4; | |
981 | ||
982 | for ( /* i=4 */ ; i < cache->callsize; i++, sp += 4) | |
983 | { | |
984 | cache->aregs[i] = sp; | |
985 | } | |
986 | } | |
987 | } | |
988 | ||
989 | if (cache->prev_sp == 0) | |
990 | { | |
991 | if (cache->ws == 0) | |
992 | { | |
993 | /* Register window overflow already happened. | |
994 | We can read caller's frame SP from the proper spill loction. */ | |
995 | cache->prev_sp = | |
996 | read_memory_integer (cache->aregs[1], | |
997 | register_size (current_gdbarch, | |
998 | A1_REGNUM)); | |
999 | } | |
1000 | else | |
1001 | { | |
1002 | /* Read caller's frame SP directly from the previous window. */ | |
1003 | ||
1004 | int regnum = AREG_NUMBER (A1_REGNUM, cache->wb); | |
1005 | ||
9c9acae0 | 1006 | cache->prev_sp = frame_unwind_register_unsigned (next_frame, regnum); |
ca3bf3bd DJ |
1007 | } |
1008 | } | |
1009 | ||
1010 | cache->base = frame_unwind_register_unsigned (next_frame,A1_REGNUM); | |
1011 | ||
1012 | DEBUGINFO ("[xtensa_frame_cache] base 0x%08x, wb %d, " | |
1013 | "ws 0x%08x, callsize %d, pc 0x%08x, ps 0x%08x, prev_sp 0x%08x\n", | |
1014 | (unsigned int) cache->base, (unsigned int) cache->wb, | |
1015 | cache->ws, cache->callsize, (unsigned int) cache->pc, | |
1016 | (unsigned int) cache->ps, (unsigned int) cache->prev_sp); | |
1017 | ||
1018 | return cache; | |
1019 | } | |
1020 | ||
1021 | ||
1022 | static void | |
1023 | xtensa_frame_this_id (struct frame_info *next_frame, | |
1024 | void **this_cache, | |
1025 | struct frame_id *this_id) | |
1026 | { | |
1027 | struct xtensa_frame_cache *cache = | |
1028 | xtensa_frame_cache (next_frame, this_cache); | |
1029 | ||
cb5c8c39 DJ |
1030 | DEBUGTRACE ("xtensa_frame_this_id (next %p, *this %p)\n", |
1031 | next_frame, *this_cache); | |
ca3bf3bd DJ |
1032 | |
1033 | if (cache->prev_sp == 0) | |
1034 | return; | |
1035 | ||
1036 | (*this_id) = frame_id_build (cache->prev_sp, cache->pc); | |
1037 | } | |
1038 | ||
1039 | ||
1040 | static void | |
1041 | xtensa_frame_prev_register (struct frame_info *next_frame, | |
1042 | void **this_cache, | |
1043 | int regnum, | |
1044 | int *optimizedp, | |
1045 | enum lval_type *lvalp, | |
1046 | CORE_ADDR *addrp, | |
1047 | int *realnump, | |
1048 | gdb_byte *valuep) | |
1049 | { | |
1050 | struct xtensa_frame_cache *cache = | |
1051 | xtensa_frame_cache (next_frame, this_cache); | |
1052 | CORE_ADDR saved_reg = 0; | |
1053 | int done = 1; | |
1054 | ||
cb5c8c39 DJ |
1055 | DEBUGTRACE ("xtensa_frame_prev_register (next %p, " |
1056 | "*this %p, regnum %d (%s), ...)\n", | |
1057 | next_frame, | |
1058 | *this_cache ? *this_cache : 0, regnum, | |
ca3bf3bd DJ |
1059 | xtensa_register_name (regnum)); |
1060 | ||
1061 | if (regnum == WS_REGNUM) | |
1062 | { | |
1063 | if (cache->ws != 0) | |
1064 | saved_reg = cache->ws; | |
1065 | else | |
1066 | saved_reg = 1 << cache->wb; | |
1067 | } | |
1068 | else if (regnum == WB_REGNUM) | |
1069 | saved_reg = cache->wb; | |
3e8c568d | 1070 | else if (regnum == gdbarch_pc_regnum (current_gdbarch)) |
ca3bf3bd | 1071 | saved_reg = cache->pc; |
3e8c568d | 1072 | else if (regnum == gdbarch_ps_regnum (current_gdbarch)) |
ca3bf3bd DJ |
1073 | saved_reg = cache->ps; |
1074 | else | |
1075 | done = 0; | |
1076 | ||
1077 | if (done) | |
1078 | { | |
1079 | *optimizedp = 0; | |
1080 | *lvalp = not_lval; | |
1081 | *addrp = 0; | |
1082 | *realnump = -1; | |
1083 | if (valuep) | |
1084 | store_unsigned_integer (valuep, 4, saved_reg); | |
1085 | ||
1086 | return; | |
1087 | } | |
1088 | ||
1089 | /* Convert Ax register numbers to ARx register numbers. */ | |
1090 | if (regnum >= A0_REGNUM && regnum <= A15_REGNUM) | |
1091 | regnum = AREG_NUMBER (regnum, cache->wb); | |
1092 | ||
1093 | /* Check if ARx register has been saved to stack. */ | |
1094 | if (regnum >= AR_BASE && regnum <= (AR_BASE + NUM_AREGS)) | |
1095 | { | |
1096 | int areg = regnum - AR_BASE - (cache->wb * 4); | |
1097 | ||
1098 | if (areg >= 0 | |
1099 | && areg < XTENSA_NUM_SAVED_AREGS | |
1100 | && cache->aregs[areg] != -1) | |
1101 | { | |
1102 | *optimizedp = 0; | |
1103 | *lvalp = lval_memory; | |
1104 | *addrp = cache->aregs[areg]; | |
1105 | *realnump = -1; | |
1106 | ||
1107 | if (valuep) | |
1108 | read_memory (*addrp, valuep, | |
1109 | register_size (current_gdbarch, regnum)); | |
1110 | ||
1111 | DEBUGINFO ("[xtensa_frame_prev_register] register on stack\n"); | |
1112 | return; | |
1113 | } | |
1114 | } | |
1115 | ||
1116 | /* Note: All other registers have been either saved to the dummy stack | |
1117 | or are still alive in the processor. */ | |
1118 | ||
1119 | *optimizedp = 0; | |
1120 | *lvalp = lval_register; | |
1121 | *addrp = 0; | |
1122 | *realnump = regnum; | |
1123 | if (valuep) | |
1124 | frame_unwind_register (next_frame, (*realnump), valuep); | |
1125 | } | |
1126 | ||
1127 | ||
1128 | static const struct frame_unwind | |
1129 | xtensa_frame_unwind = | |
1130 | { | |
1131 | NORMAL_FRAME, | |
1132 | xtensa_frame_this_id, | |
1133 | xtensa_frame_prev_register | |
1134 | }; | |
1135 | ||
1136 | static const struct frame_unwind * | |
1137 | xtensa_frame_sniffer (struct frame_info *next_frame) | |
1138 | { | |
1139 | return &xtensa_frame_unwind; | |
1140 | } | |
1141 | ||
1142 | static CORE_ADDR | |
1143 | xtensa_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
1144 | { | |
1145 | struct xtensa_frame_cache *cache = | |
1146 | xtensa_frame_cache (next_frame, this_cache); | |
1147 | ||
1148 | return cache->base; | |
1149 | } | |
1150 | ||
1151 | static const struct frame_base | |
1152 | xtensa_frame_base = | |
1153 | { | |
1154 | &xtensa_frame_unwind, | |
1155 | xtensa_frame_base_address, | |
1156 | xtensa_frame_base_address, | |
1157 | xtensa_frame_base_address | |
1158 | }; | |
1159 | ||
1160 | ||
1161 | static void | |
1162 | xtensa_extract_return_value (struct type *type, | |
1163 | struct regcache *regcache, | |
1164 | void *dst) | |
1165 | { | |
1166 | bfd_byte *valbuf = dst; | |
1167 | int len = TYPE_LENGTH (type); | |
1168 | ULONGEST pc, wb; | |
1169 | int callsize, areg; | |
1170 | int offset = 0; | |
1171 | ||
1172 | DEBUGTRACE ("xtensa_extract_return_value (...)\n"); | |
1173 | ||
1174 | gdb_assert(len > 0); | |
1175 | ||
1176 | /* First, we have to find the caller window in the register file. */ | |
3e8c568d UW |
1177 | regcache_raw_read_unsigned (regcache, |
1178 | gdbarch_pc_regnum (current_gdbarch), &pc); | |
ca3bf3bd DJ |
1179 | callsize = extract_call_winsize (pc); |
1180 | ||
1181 | /* On Xtensa, we can return up to 4 words (or 2 when called by call12). */ | |
1182 | if (len > (callsize > 8 ? 8 : 16)) | |
1183 | internal_error (__FILE__, __LINE__, | |
1184 | _("cannot extract return value of %d bytes long"), len); | |
1185 | ||
1186 | /* Get the register offset of the return register (A2) in the caller | |
1187 | window. */ | |
1188 | regcache_raw_read_unsigned (regcache, WB_REGNUM, &wb); | |
1189 | areg = AREG_NUMBER(A2_REGNUM + callsize, wb); | |
1190 | ||
1191 | DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len); | |
1192 | ||
4c6b5505 | 1193 | if (len < 4 && gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1194 | offset = 4 - len; |
1195 | ||
1196 | for (; len > 0; len -= 4, areg++, valbuf += 4) | |
1197 | { | |
1198 | if (len < 4) | |
1199 | regcache_raw_read_part (regcache, areg, offset, len, valbuf); | |
1200 | else | |
1201 | regcache_raw_read (regcache, areg, valbuf); | |
1202 | } | |
1203 | } | |
1204 | ||
1205 | ||
1206 | static void | |
1207 | xtensa_store_return_value (struct type *type, | |
1208 | struct regcache *regcache, | |
1209 | const void *dst) | |
1210 | { | |
1211 | const bfd_byte *valbuf = dst; | |
1212 | unsigned int areg; | |
1213 | ULONGEST pc, wb; | |
1214 | int callsize; | |
1215 | int len = TYPE_LENGTH (type); | |
1216 | int offset = 0; | |
1217 | ||
1218 | DEBUGTRACE ("xtensa_store_return_value (...)\n"); | |
1219 | ||
1220 | regcache_raw_read_unsigned (regcache, WB_REGNUM, &wb); | |
3e8c568d UW |
1221 | regcache_raw_read_unsigned (regcache, |
1222 | gdbarch_pc_regnum (current_gdbarch), &pc); | |
ca3bf3bd DJ |
1223 | callsize = extract_call_winsize (pc); |
1224 | ||
1225 | if (len > (callsize > 8 ? 8 : 16)) | |
1226 | internal_error (__FILE__, __LINE__, | |
1227 | _("unimplemented for this length: %d"), | |
1228 | TYPE_LENGTH (type)); | |
1229 | ||
1230 | DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n", | |
1231 | callsize, (int) wb); | |
1232 | ||
4c6b5505 | 1233 | if (len < 4 && gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1234 | offset = 4 - len; |
1235 | ||
1236 | areg = AREG_NUMBER (A2_REGNUM + callsize, wb); | |
1237 | ||
1238 | for (; len > 0; len -= 4, areg++, valbuf += 4) | |
1239 | { | |
1240 | if (len < 4) | |
1241 | regcache_raw_write_part (regcache, areg, offset, len, valbuf); | |
1242 | else | |
1243 | regcache_raw_write (regcache, areg, valbuf); | |
1244 | } | |
1245 | } | |
1246 | ||
1247 | ||
1248 | enum return_value_convention | |
1249 | xtensa_return_value (struct gdbarch *gdbarch, | |
1250 | struct type *valtype, | |
1251 | struct regcache *regcache, | |
1252 | gdb_byte *readbuf, | |
1253 | const gdb_byte *writebuf) | |
1254 | { | |
1255 | /* Note: Structures up to 16 bytes are returned in registers. */ | |
1256 | ||
1257 | int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT | |
1258 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
1259 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
1260 | && TYPE_LENGTH (valtype) > 16); | |
1261 | ||
1262 | if (struct_return) | |
1263 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1264 | ||
1265 | DEBUGTRACE ("xtensa_return_value(...)\n"); | |
1266 | ||
1267 | if (writebuf != NULL) | |
1268 | { | |
1269 | xtensa_store_return_value (valtype, regcache, writebuf); | |
1270 | } | |
1271 | ||
1272 | if (readbuf != NULL) | |
1273 | { | |
1274 | gdb_assert (!struct_return); | |
1275 | xtensa_extract_return_value (valtype, regcache, readbuf); | |
1276 | } | |
1277 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1278 | } | |
1279 | ||
1280 | ||
1281 | /* DUMMY FRAME */ | |
1282 | ||
1283 | static CORE_ADDR | |
1284 | xtensa_push_dummy_call (struct gdbarch *gdbarch, | |
1285 | struct value *function, | |
1286 | struct regcache *regcache, | |
1287 | CORE_ADDR bp_addr, | |
1288 | int nargs, | |
1289 | struct value **args, | |
1290 | CORE_ADDR sp, | |
1291 | int struct_return, | |
1292 | CORE_ADDR struct_addr) | |
1293 | { | |
1294 | int i; | |
1295 | int size, onstack_size; | |
ff7a4c00 | 1296 | gdb_byte *buf = (gdb_byte *) alloca (16); |
ca3bf3bd DJ |
1297 | CORE_ADDR ra, ps; |
1298 | struct argument_info | |
1299 | { | |
1300 | const bfd_byte *contents; | |
1301 | int length; | |
1302 | int onstack; /* onstack == 0 => in reg */ | |
1303 | int align; /* alignment */ | |
1304 | union | |
1305 | { | |
1306 | int offset; /* stack offset if on stack */ | |
1307 | int regno; /* regno if in register */ | |
1308 | } u; | |
1309 | }; | |
1310 | ||
1311 | struct argument_info *arg_info = | |
1312 | (struct argument_info *) alloca (nargs * sizeof (struct argument_info)); | |
1313 | ||
1314 | CORE_ADDR osp = sp; | |
1315 | ||
1316 | DEBUGTRACE ("xtensa_push_dummy_call (...)\n"); | |
1317 | ||
1318 | if (xtensa_debug_level > 3) | |
1319 | { | |
1320 | int i; | |
1321 | DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs); | |
1322 | DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, " | |
1323 | "struct_addr=0x%x\n", | |
1324 | (int) sp, (int) struct_return, (int) struct_addr); | |
1325 | ||
1326 | for (i = 0; i < nargs; i++) | |
1327 | { | |
1328 | struct value *arg = args[i]; | |
1329 | struct type *arg_type = check_typedef (value_type (arg)); | |
cb5c8c39 DJ |
1330 | fprintf_unfiltered (gdb_stdlog, "%2d: %p %3d ", |
1331 | i, arg, TYPE_LENGTH (arg_type)); | |
ca3bf3bd DJ |
1332 | switch (TYPE_CODE (arg_type)) |
1333 | { | |
1334 | case TYPE_CODE_INT: | |
1335 | fprintf_unfiltered (gdb_stdlog, "int"); | |
1336 | break; | |
1337 | case TYPE_CODE_STRUCT: | |
1338 | fprintf_unfiltered (gdb_stdlog, "struct"); | |
1339 | break; | |
1340 | default: | |
1341 | fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type)); | |
1342 | break; | |
1343 | } | |
cb5c8c39 DJ |
1344 | fprintf_unfiltered (gdb_stdlog, " %p\n", |
1345 | value_contents (arg)); | |
ca3bf3bd DJ |
1346 | } |
1347 | } | |
1348 | ||
1349 | /* First loop: collect information. | |
1350 | Cast into type_long. (This shouldn't happen often for C because | |
1351 | GDB already does this earlier.) It's possible that GDB could | |
1352 | do it all the time but it's harmless to leave this code here. */ | |
1353 | ||
1354 | size = 0; | |
1355 | onstack_size = 0; | |
1356 | i = 0; | |
1357 | ||
1358 | if (struct_return) | |
1359 | size = REGISTER_SIZE; | |
1360 | ||
1361 | for (i = 0; i < nargs; i++) | |
1362 | { | |
1363 | struct argument_info *info = &arg_info[i]; | |
1364 | struct value *arg = args[i]; | |
1365 | struct type *arg_type = check_typedef (value_type (arg)); | |
1366 | ||
1367 | switch (TYPE_CODE (arg_type)) | |
1368 | { | |
1369 | case TYPE_CODE_INT: | |
1370 | case TYPE_CODE_BOOL: | |
1371 | case TYPE_CODE_CHAR: | |
1372 | case TYPE_CODE_RANGE: | |
1373 | case TYPE_CODE_ENUM: | |
1374 | ||
1375 | /* Cast argument to long if necessary as the mask does it too. */ | |
1376 | if (TYPE_LENGTH (arg_type) < TYPE_LENGTH (builtin_type_long)) | |
1377 | { | |
1378 | arg_type = builtin_type_long; | |
1379 | arg = value_cast (arg_type, arg); | |
1380 | } | |
1381 | info->align = TYPE_LENGTH (builtin_type_long); | |
1382 | break; | |
1383 | ||
1384 | case TYPE_CODE_FLT: | |
1385 | ||
1386 | /* Align doubles correctly. */ | |
1387 | if (TYPE_LENGTH (arg_type) == TYPE_LENGTH (builtin_type_double)) | |
1388 | info->align = TYPE_LENGTH (builtin_type_double); | |
1389 | else | |
1390 | info->align = TYPE_LENGTH (builtin_type_long); | |
1391 | break; | |
1392 | ||
1393 | case TYPE_CODE_STRUCT: | |
1394 | default: | |
1395 | info->align = TYPE_LENGTH (builtin_type_long); | |
1396 | break; | |
1397 | } | |
1398 | info->length = TYPE_LENGTH (arg_type); | |
1399 | info->contents = value_contents (arg); | |
1400 | ||
1401 | /* Align size and onstack_size. */ | |
1402 | size = (size + info->align - 1) & ~(info->align - 1); | |
1403 | onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1); | |
1404 | ||
1405 | if (size + info->length > REGISTER_SIZE * ARGS_NUM_REGS) | |
1406 | { | |
1407 | info->onstack = 1; | |
1408 | info->u.offset = onstack_size; | |
1409 | onstack_size += info->length; | |
1410 | } | |
1411 | else | |
1412 | { | |
1413 | info->onstack = 0; | |
1414 | info->u.regno = ARGS_FIRST_REG + size / REGISTER_SIZE; | |
1415 | } | |
1416 | size += info->length; | |
1417 | } | |
1418 | ||
1419 | /* Adjust the stack pointer and align it. */ | |
1420 | sp = align_down (sp - onstack_size, SP_ALIGNMENT); | |
1421 | ||
1422 | /* Simulate MOVSP. */ | |
1423 | if (sp != osp) | |
1424 | { | |
1425 | read_memory (osp - 16, buf, 16); | |
1426 | write_memory (sp - 16, buf, 16); | |
1427 | } | |
1428 | ||
1429 | /* Second Loop: Load arguments. */ | |
1430 | ||
1431 | if (struct_return) | |
1432 | { | |
1433 | store_unsigned_integer (buf, REGISTER_SIZE, struct_addr); | |
1434 | regcache_cooked_write (regcache, ARGS_FIRST_REG, buf); | |
1435 | } | |
1436 | ||
1437 | for (i = 0; i < nargs; i++) | |
1438 | { | |
1439 | struct argument_info *info = &arg_info[i]; | |
1440 | ||
1441 | if (info->onstack) | |
1442 | { | |
1443 | int n = info->length; | |
1444 | CORE_ADDR offset = sp + info->u.offset; | |
1445 | ||
1446 | /* Odd-sized structs are aligned to the lower side of a memory | |
1447 | word in big-endian mode and require a shift. This only | |
1448 | applies for structures smaller than one word. */ | |
1449 | ||
4c6b5505 UW |
1450 | if (n < REGISTER_SIZE |
1451 | && gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) | |
ca3bf3bd DJ |
1452 | offset += (REGISTER_SIZE - n); |
1453 | ||
1454 | write_memory (offset, info->contents, info->length); | |
1455 | ||
1456 | } | |
1457 | else | |
1458 | { | |
1459 | int n = info->length; | |
1460 | const bfd_byte *cp = info->contents; | |
1461 | int r = info->u.regno; | |
1462 | ||
1463 | /* Odd-sized structs are aligned to the lower side of registers in | |
1464 | big-endian mode and require a shift. The odd-sized leftover will | |
1465 | be at the end. Note that this is only true for structures smaller | |
1466 | than REGISTER_SIZE; for larger odd-sized structures the excess | |
1467 | will be left-aligned in the register on both endiannesses. */ | |
1468 | ||
4c6b5505 UW |
1469 | if (n < REGISTER_SIZE |
1470 | && gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) | |
ca3bf3bd DJ |
1471 | { |
1472 | ULONGEST v = extract_unsigned_integer (cp, REGISTER_SIZE); | |
1473 | v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT); | |
1474 | ||
1475 | store_unsigned_integer (buf, REGISTER_SIZE, v); | |
1476 | regcache_cooked_write (regcache, r, buf); | |
1477 | ||
1478 | cp += REGISTER_SIZE; | |
1479 | n -= REGISTER_SIZE; | |
1480 | r++; | |
1481 | } | |
1482 | else | |
1483 | while (n > 0) | |
1484 | { | |
1485 | /* ULONGEST v = extract_unsigned_integer (cp, REGISTER_SIZE);*/ | |
1486 | regcache_cooked_write (regcache, r, cp); | |
1487 | ||
9c9acae0 | 1488 | /* regcache_cooked_write_unsigned (regcache, r, v); */ |
ca3bf3bd DJ |
1489 | cp += REGISTER_SIZE; |
1490 | n -= REGISTER_SIZE; | |
1491 | r++; | |
1492 | } | |
1493 | } | |
1494 | } | |
1495 | ||
1496 | ||
1497 | /* Set the return address of dummy frame to the dummy address. | |
1498 | Note: The return address for the current function (in A0) is | |
1499 | saved in the dummy frame, so we can savely overwrite A0 here. */ | |
1500 | ||
1501 | ra = (bp_addr & 0x3fffffff) | 0x40000000; | |
3e8c568d | 1502 | regcache_raw_read (regcache, gdbarch_ps_regnum (current_gdbarch), buf); |
ca3bf3bd DJ |
1503 | ps = extract_unsigned_integer (buf, 4) & ~0x00030000; |
1504 | regcache_cooked_write_unsigned (regcache, A4_REGNUM, ra); | |
3e8c568d UW |
1505 | regcache_cooked_write_unsigned (regcache, |
1506 | gdbarch_ps_regnum (current_gdbarch), | |
1507 | ps | 0x00010000); | |
ca3bf3bd DJ |
1508 | |
1509 | /* Set new stack pointer and return it. */ | |
1510 | regcache_cooked_write_unsigned (regcache, A1_REGNUM, sp); | |
1511 | /* Make dummy frame ID unique by adding a constant. */ | |
1512 | return sp + SP_ALIGNMENT; | |
1513 | } | |
1514 | ||
1515 | ||
1516 | /* Return a breakpoint for the current location of PC. We always use | |
1517 | the density version if we have density instructions (regardless of the | |
1518 | current instruction at PC), and use regular instructions otherwise. */ | |
1519 | ||
1520 | #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 } | |
1521 | #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 } | |
1522 | #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f } | |
1523 | #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 } | |
1524 | ||
1525 | const unsigned char * | |
1526 | xtensa_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) | |
1527 | { | |
ff7a4c00 MG |
1528 | static unsigned char big_breakpoint[] = BIG_BREAKPOINT; |
1529 | static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT; | |
1530 | static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT; | |
1531 | static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT; | |
ca3bf3bd DJ |
1532 | |
1533 | DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr); | |
1534 | ||
1535 | if (ISA_USE_DENSITY_INSTRUCTIONS) | |
1536 | { | |
4c6b5505 | 1537 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1538 | { |
1539 | *lenptr = sizeof (density_big_breakpoint); | |
1540 | return density_big_breakpoint; | |
1541 | } | |
1542 | else | |
1543 | { | |
1544 | *lenptr = sizeof (density_little_breakpoint); | |
1545 | return density_little_breakpoint; | |
1546 | } | |
1547 | } | |
1548 | else | |
1549 | { | |
4c6b5505 | 1550 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
ca3bf3bd DJ |
1551 | { |
1552 | *lenptr = sizeof (big_breakpoint); | |
1553 | return big_breakpoint; | |
1554 | } | |
1555 | else | |
1556 | { | |
1557 | *lenptr = sizeof (little_breakpoint); | |
1558 | return little_breakpoint; | |
1559 | } | |
1560 | } | |
1561 | } | |
1562 | ||
1563 | ||
1564 | /* Return the pc of the first real instruction. We assume that this | |
1565 | machine uses register windows. | |
1566 | ||
1567 | If we have debug info ( line-number info, in particular ) we simply skip | |
1568 | the code associated with the first function line effectively skipping | |
1569 | the prologue code. It works even in cases like | |
1570 | ||
1571 | int main() | |
1572 | { int local_var = 1; | |
1573 | .... | |
1574 | } | |
1575 | ||
1576 | because, for this source code, both Xtensa compilers will generate two | |
1577 | separate entries ( with the same line number ) in dwarf line-number | |
1578 | section to make sure there is a boundary between the prologue code and | |
1579 | the rest of the function. | |
1580 | ||
1581 | If there is no debug info, we need to analyze the code. */ | |
1582 | ||
1583 | CORE_ADDR | |
1584 | xtensa_skip_prologue (CORE_ADDR start_pc) | |
1585 | { | |
1586 | DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc); | |
1587 | ||
1588 | if (ISA_USE_WINDOWED_REGISTERS) | |
1589 | { | |
1590 | unsigned char op1; | |
1591 | struct symtab_and_line prologue_sal; | |
1592 | ||
1593 | op1 = read_memory_integer (start_pc, 1); | |
1594 | if (!XTENSA_IS_ENTRY (op1)) | |
1595 | return start_pc; | |
1596 | ||
1597 | prologue_sal = find_pc_line (start_pc, 0); | |
1598 | if (prologue_sal.line != 0) | |
1599 | return prologue_sal.end; | |
1600 | else | |
1601 | return start_pc + XTENSA_ENTRY_LENGTH; | |
1602 | } | |
1603 | else | |
1604 | { | |
1605 | internal_error (__FILE__, __LINE__, | |
1606 | _("non-windowed configurations are not supported")); | |
1607 | return start_pc; | |
1608 | } | |
1609 | } | |
1610 | ||
1611 | ||
1612 | /* CONFIGURATION CHECK */ | |
1613 | ||
1614 | /* Verify the current configuration. */ | |
1615 | ||
1616 | static void | |
1617 | xtensa_verify_config (struct gdbarch *gdbarch) | |
1618 | { | |
1619 | struct ui_file *log; | |
1620 | struct cleanup *cleanups; | |
1621 | struct gdbarch_tdep *tdep; | |
1622 | long dummy; | |
1623 | char *buf; | |
1624 | ||
1625 | tdep = gdbarch_tdep (gdbarch); | |
1626 | log = mem_fileopen (); | |
1627 | cleanups = make_cleanup_ui_file_delete (log); | |
1628 | ||
1629 | /* Verify that we got a reasonable number of AREGS. */ | |
1630 | if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs) | |
1631 | fprintf_unfiltered (log, "\n\tnum_aregs: Number of AR registers (%d) " | |
1632 | "is not a power of two!", tdep->num_aregs); | |
1633 | ||
1634 | /* Verify that certain registers exist. */ | |
1635 | if (tdep->pc_regnum == -1) | |
1636 | fprintf_unfiltered (log, "\n\tpc_regnum: No PC register"); | |
1637 | if (tdep->ps_regnum == -1) | |
1638 | fprintf_unfiltered (log, "\n\tps_regnum: No PS register"); | |
1639 | if (tdep->wb_regnum == -1) | |
1640 | fprintf_unfiltered (log, "\n\twb_regnum: No WB register"); | |
1641 | if (tdep->ws_regnum == -1) | |
1642 | fprintf_unfiltered (log, "\n\tws_regnum: No WS register"); | |
1643 | if (tdep->ar_base == -1) | |
1644 | fprintf_unfiltered (log, "\n\tar_base: No AR registers"); | |
1645 | if (tdep->a0_base == -1) | |
1646 | fprintf_unfiltered (log, "\n\ta0_base: No Ax registers"); | |
1647 | ||
1648 | buf = ui_file_xstrdup (log, &dummy); | |
1649 | make_cleanup (xfree, buf); | |
1650 | if (strlen (buf) > 0) | |
1651 | internal_error (__FILE__, __LINE__, | |
1652 | _("the following are invalid: %s"), buf); | |
1653 | do_cleanups (cleanups); | |
1654 | } | |
1655 | ||
1656 | ||
1657 | /* Module "constructor" function. */ | |
1658 | ||
1659 | static struct gdbarch * | |
1660 | xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1661 | { | |
1662 | struct gdbarch_tdep *tdep; | |
1663 | struct gdbarch *gdbarch; | |
1664 | struct xtensa_abi_handler *abi_handler; | |
1665 | ||
1666 | DEBUGTRACE ("gdbarch_init()\n"); | |
1667 | ||
1668 | /* We have to set the byte order before we call gdbarch_alloc. */ | |
1669 | info.byte_order = xtensa_config_byte_order (&info); | |
1670 | ||
1671 | tdep = xtensa_config_tdep (&info); | |
1672 | gdbarch = gdbarch_alloc (&info, tdep); | |
1673 | ||
1674 | /* Verify our configuration. */ | |
1675 | xtensa_verify_config (gdbarch); | |
1676 | ||
1677 | /* Pseudo-Register read/write */ | |
1678 | set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read); | |
1679 | set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write); | |
1680 | ||
1681 | /* Set target information. */ | |
1682 | set_gdbarch_num_regs (gdbarch, tdep->num_regs); | |
1683 | set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs); | |
1684 | set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1); | |
1685 | set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum); | |
1686 | set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum); | |
1687 | ||
1688 | /* Renumber registers for known formats (stab, dwarf, and dwarf2). */ | |
1689 | set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); | |
1690 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); | |
1691 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum); | |
1692 | ||
1693 | /* We provide our own function to get register information. */ | |
1694 | set_gdbarch_register_name (gdbarch, xtensa_register_name); | |
1695 | set_gdbarch_register_type (gdbarch, xtensa_register_type); | |
1696 | ||
1697 | /* To call functions from GDB using dummy frame */ | |
1698 | set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call); | |
1699 | ||
1700 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); | |
1701 | ||
1702 | set_gdbarch_return_value (gdbarch, xtensa_return_value); | |
1703 | ||
1704 | /* Advance PC across any prologue instructions to reach "real" code. */ | |
1705 | set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue); | |
1706 | ||
1707 | /* Stack grows downward. */ | |
1708 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1709 | ||
1710 | /* Set breakpoints. */ | |
1711 | set_gdbarch_breakpoint_from_pc (gdbarch, xtensa_breakpoint_from_pc); | |
1712 | ||
1713 | /* After breakpoint instruction or illegal instruction, pc still | |
1714 | points at break instruction, so don't decrement. */ | |
1715 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
1716 | ||
1717 | /* We don't skip args. */ | |
1718 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
1719 | ||
1720 | set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc); | |
1721 | ||
1722 | set_gdbarch_frame_align (gdbarch, xtensa_frame_align); | |
1723 | ||
1724 | set_gdbarch_unwind_dummy_id (gdbarch, xtensa_unwind_dummy_id); | |
1725 | ||
1726 | /* Frame handling. */ | |
1727 | frame_base_set_default (gdbarch, &xtensa_frame_base); | |
1728 | frame_unwind_append_sniffer (gdbarch, xtensa_frame_sniffer); | |
1729 | ||
1730 | set_gdbarch_print_insn (gdbarch, print_insn_xtensa); | |
1731 | ||
1732 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
1733 | ||
1734 | xtensa_add_reggroups (gdbarch); | |
1735 | set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p); | |
1736 | ||
1737 | set_gdbarch_regset_from_core_section (gdbarch, | |
1738 | xtensa_regset_from_core_section); | |
1739 | ||
1740 | return gdbarch; | |
1741 | } | |
1742 | ||
1743 | ||
1744 | /* Dump xtensa tdep structure. */ | |
1745 | ||
1746 | static void | |
1747 | xtensa_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
1748 | { | |
1749 | error (_("xtensa_dump_tdep(): not implemented")); | |
1750 | } | |
1751 | ||
1752 | ||
1753 | void | |
1754 | _initialize_xtensa_tdep (void) | |
1755 | { | |
1756 | struct cmd_list_element *c; | |
1757 | ||
1758 | gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep); | |
1759 | xtensa_init_reggroups (); | |
1760 | ||
1761 | add_setshow_zinteger_cmd ("xtensa", | |
1762 | class_maintenance, | |
1763 | &xtensa_debug_level, _("\ | |
1764 | Set Xtensa debugging."), _("\ | |
1765 | Show Xtensa debugging."), _("\ | |
1766 | When non-zero, Xtensa-specific debugging is enabled. \ | |
1767 | Can be 1, 2, 3, or 4 indicating the level of debugging."), | |
1768 | NULL, | |
1769 | NULL, | |
1770 | &setdebuglist, &showdebuglist); | |
1771 | } |