Commit | Line | Data |
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0a30fbc4 | 1 | /* GNU/Linux/ARM specific low level interface, for the remote server for GDB. |
b811d2c2 | 2 | Copyright (C) 1995-2020 Free Software Foundation, Inc. |
0a30fbc4 DJ |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
0a30fbc4 DJ |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
0a30fbc4 DJ |
18 | |
19 | #include "server.h" | |
58caa3dc | 20 | #include "linux-low.h" |
deca266c | 21 | #include "arch/arm.h" |
d9311bfa AT |
22 | #include "arch/arm-linux.h" |
23 | #include "arch/arm-get-next-pcs.h" | |
bd9e6534 | 24 | #include "linux-aarch32-low.h" |
7cc17433 AH |
25 | #include "linux-aarch32-tdesc.h" |
26 | #include "linux-arm-tdesc.h" | |
0a30fbc4 | 27 | |
bd9e6534 | 28 | #include <sys/uio.h> |
3743bb4f DE |
29 | /* Don't include elf.h if linux/elf.h got included by gdb_proc_service.h. |
30 | On Bionic elf.h and linux/elf.h have conflicting definitions. */ | |
31 | #ifndef ELFMAG0 | |
58d6951d | 32 | #include <elf.h> |
3743bb4f | 33 | #endif |
5826e159 | 34 | #include "nat/gdb_ptrace.h" |
09b4ad9f | 35 | #include <signal.h> |
d9311bfa | 36 | #include <sys/syscall.h> |
9308fc88 | 37 | |
9308fc88 DJ |
38 | #ifndef PTRACE_GET_THREAD_AREA |
39 | #define PTRACE_GET_THREAD_AREA 22 | |
40 | #endif | |
41 | ||
fb1e4ffc DJ |
42 | #ifndef PTRACE_GETWMMXREGS |
43 | # define PTRACE_GETWMMXREGS 18 | |
44 | # define PTRACE_SETWMMXREGS 19 | |
45 | #endif | |
46 | ||
58d6951d DJ |
47 | #ifndef PTRACE_GETVFPREGS |
48 | # define PTRACE_GETVFPREGS 27 | |
49 | # define PTRACE_SETVFPREGS 28 | |
50 | #endif | |
51 | ||
09b4ad9f UW |
52 | #ifndef PTRACE_GETHBPREGS |
53 | #define PTRACE_GETHBPREGS 29 | |
54 | #define PTRACE_SETHBPREGS 30 | |
55 | #endif | |
56 | ||
ef0478f6 TBA |
57 | /* Linux target op definitions for the ARM architecture. */ |
58 | ||
59 | class arm_target : public linux_process_target | |
60 | { | |
61 | public: | |
62 | ||
797bcff5 TBA |
63 | protected: |
64 | ||
65 | void low_arch_setup () override; | |
ef0478f6 TBA |
66 | }; |
67 | ||
68 | /* The singleton target ops object. */ | |
69 | ||
70 | static arm_target the_arm_target; | |
71 | ||
09b4ad9f | 72 | /* Information describing the hardware breakpoint capabilities. */ |
71487fd7 | 73 | static struct |
09b4ad9f UW |
74 | { |
75 | unsigned char arch; | |
76 | unsigned char max_wp_length; | |
77 | unsigned char wp_count; | |
78 | unsigned char bp_count; | |
71487fd7 | 79 | } arm_linux_hwbp_cap; |
09b4ad9f UW |
80 | |
81 | /* Enum describing the different types of ARM hardware break-/watch-points. */ | |
82 | typedef enum | |
83 | { | |
84 | arm_hwbp_break = 0, | |
85 | arm_hwbp_load = 1, | |
86 | arm_hwbp_store = 2, | |
87 | arm_hwbp_access = 3 | |
88 | } arm_hwbp_type; | |
89 | ||
90 | /* Type describing an ARM Hardware Breakpoint Control register value. */ | |
91 | typedef unsigned int arm_hwbp_control_t; | |
92 | ||
93 | /* Structure used to keep track of hardware break-/watch-points. */ | |
94 | struct arm_linux_hw_breakpoint | |
95 | { | |
96 | /* Address to break on, or being watched. */ | |
97 | unsigned int address; | |
98 | /* Control register for break-/watch- point. */ | |
99 | arm_hwbp_control_t control; | |
100 | }; | |
101 | ||
102 | /* Since we cannot dynamically allocate subfields of arch_process_info, | |
103 | assume a maximum number of supported break-/watchpoints. */ | |
104 | #define MAX_BPTS 32 | |
105 | #define MAX_WPTS 32 | |
106 | ||
107 | /* Per-process arch-specific data we want to keep. */ | |
108 | struct arch_process_info | |
109 | { | |
110 | /* Hardware breakpoints for this process. */ | |
111 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; | |
112 | /* Hardware watchpoints for this process. */ | |
113 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; | |
114 | }; | |
115 | ||
116 | /* Per-thread arch-specific data we want to keep. */ | |
117 | struct arch_lwp_info | |
118 | { | |
119 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
120 | char bpts_changed[MAX_BPTS]; | |
121 | char wpts_changed[MAX_WPTS]; | |
122 | /* Cached stopped data address. */ | |
123 | CORE_ADDR stopped_data_address; | |
124 | }; | |
125 | ||
58d6951d DJ |
126 | /* These are in <asm/elf.h> in current kernels. */ |
127 | #define HWCAP_VFP 64 | |
128 | #define HWCAP_IWMMXT 512 | |
129 | #define HWCAP_NEON 4096 | |
130 | #define HWCAP_VFPv3 8192 | |
131 | #define HWCAP_VFPv3D16 16384 | |
132 | ||
0a30fbc4 DJ |
133 | #ifdef HAVE_SYS_REG_H |
134 | #include <sys/reg.h> | |
135 | #endif | |
136 | ||
23ce3b1c | 137 | #define arm_num_regs 26 |
0a30fbc4 | 138 | |
2ec06d2e | 139 | static int arm_regmap[] = { |
0a30fbc4 DJ |
140 | 0, 4, 8, 12, 16, 20, 24, 28, |
141 | 32, 36, 40, 44, 48, 52, 56, 60, | |
23ce3b1c DJ |
142 | -1, -1, -1, -1, -1, -1, -1, -1, -1, |
143 | 64 | |
0a30fbc4 DJ |
144 | }; |
145 | ||
d9311bfa AT |
146 | /* Forward declarations needed for get_next_pcs ops. */ |
147 | static ULONGEST get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, | |
148 | int len, | |
149 | int byte_order); | |
150 | ||
151 | static CORE_ADDR get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, | |
152 | CORE_ADDR val); | |
153 | ||
553cb527 | 154 | static CORE_ADDR get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self); |
d9311bfa AT |
155 | |
156 | static int get_next_pcs_is_thumb (struct arm_get_next_pcs *self); | |
157 | ||
158 | /* get_next_pcs operations. */ | |
159 | static struct arm_get_next_pcs_ops get_next_pcs_ops = { | |
160 | get_next_pcs_read_memory_unsigned_integer, | |
161 | get_next_pcs_syscall_next_pc, | |
162 | get_next_pcs_addr_bits_remove, | |
ed443b61 YQ |
163 | get_next_pcs_is_thumb, |
164 | arm_linux_get_next_pcs_fixup, | |
d9311bfa AT |
165 | }; |
166 | ||
2ec06d2e DJ |
167 | static int |
168 | arm_cannot_store_register (int regno) | |
0a30fbc4 | 169 | { |
2ec06d2e | 170 | return (regno >= arm_num_regs); |
0a30fbc4 DJ |
171 | } |
172 | ||
2ec06d2e DJ |
173 | static int |
174 | arm_cannot_fetch_register (int regno) | |
0a30fbc4 | 175 | { |
2ec06d2e | 176 | return (regno >= arm_num_regs); |
0a30fbc4 DJ |
177 | } |
178 | ||
fb1e4ffc | 179 | static void |
442ea881 | 180 | arm_fill_wmmxregset (struct regcache *regcache, void *buf) |
fb1e4ffc | 181 | { |
7cc17433 | 182 | if (arm_linux_get_tdesc_fp_type (regcache->tdesc) != ARM_FP_TYPE_IWMMXT) |
58d6951d DJ |
183 | return; |
184 | ||
166a82be | 185 | for (int i = 0; i < 16; i++) |
442ea881 | 186 | collect_register (regcache, arm_num_regs + i, (char *) buf + i * 8); |
fb1e4ffc DJ |
187 | |
188 | /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */ | |
166a82be | 189 | for (int i = 0; i < 6; i++) |
442ea881 PA |
190 | collect_register (regcache, arm_num_regs + i + 16, |
191 | (char *) buf + 16 * 8 + i * 4); | |
fb1e4ffc DJ |
192 | } |
193 | ||
194 | static void | |
442ea881 | 195 | arm_store_wmmxregset (struct regcache *regcache, const void *buf) |
fb1e4ffc | 196 | { |
7cc17433 | 197 | if (arm_linux_get_tdesc_fp_type (regcache->tdesc) != ARM_FP_TYPE_IWMMXT) |
58d6951d DJ |
198 | return; |
199 | ||
166a82be | 200 | for (int i = 0; i < 16; i++) |
442ea881 | 201 | supply_register (regcache, arm_num_regs + i, (char *) buf + i * 8); |
fb1e4ffc DJ |
202 | |
203 | /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */ | |
166a82be | 204 | for (int i = 0; i < 6; i++) |
442ea881 PA |
205 | supply_register (regcache, arm_num_regs + i + 16, |
206 | (char *) buf + 16 * 8 + i * 4); | |
fb1e4ffc DJ |
207 | } |
208 | ||
58d6951d | 209 | static void |
442ea881 | 210 | arm_fill_vfpregset (struct regcache *regcache, void *buf) |
58d6951d | 211 | { |
bd9e6534 | 212 | int num; |
58d6951d | 213 | |
7cc17433 | 214 | if (is_aarch32_linux_description (regcache->tdesc)) |
58d6951d | 215 | num = 32; |
89abb039 | 216 | else |
7cc17433 AH |
217 | { |
218 | arm_fp_type fp_type = arm_linux_get_tdesc_fp_type (regcache->tdesc); | |
219 | ||
220 | if (fp_type == ARM_FP_TYPE_VFPV3) | |
221 | num = 32; | |
222 | else if (fp_type == ARM_FP_TYPE_VFPV2) | |
223 | num = 16; | |
224 | else | |
225 | return; | |
226 | } | |
58d6951d | 227 | |
bd9e6534 | 228 | arm_fill_vfpregset_num (regcache, buf, num); |
58d6951d DJ |
229 | } |
230 | ||
d9311bfa AT |
231 | /* Wrapper of UNMAKE_THUMB_ADDR for get_next_pcs. */ |
232 | static CORE_ADDR | |
233 | get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, CORE_ADDR val) | |
234 | { | |
235 | return UNMAKE_THUMB_ADDR (val); | |
236 | } | |
237 | ||
58d6951d | 238 | static void |
442ea881 | 239 | arm_store_vfpregset (struct regcache *regcache, const void *buf) |
58d6951d | 240 | { |
bd9e6534 | 241 | int num; |
58d6951d | 242 | |
7cc17433 | 243 | if (is_aarch32_linux_description (regcache->tdesc)) |
58d6951d | 244 | num = 32; |
89abb039 | 245 | else |
7cc17433 AH |
246 | { |
247 | arm_fp_type fp_type = arm_linux_get_tdesc_fp_type (regcache->tdesc); | |
248 | ||
249 | if (fp_type == ARM_FP_TYPE_VFPV3) | |
250 | num = 32; | |
251 | else if (fp_type == ARM_FP_TYPE_VFPV2) | |
252 | num = 16; | |
253 | else | |
254 | return; | |
255 | } | |
58d6951d | 256 | |
bd9e6534 | 257 | arm_store_vfpregset_num (regcache, buf, num); |
58d6951d | 258 | } |
fb1e4ffc | 259 | |
d9311bfa AT |
260 | /* Wrapper of arm_is_thumb_mode for get_next_pcs. */ |
261 | static int | |
262 | get_next_pcs_is_thumb (struct arm_get_next_pcs *self) | |
263 | { | |
264 | return arm_is_thumb_mode (); | |
265 | } | |
266 | ||
30baf67b | 267 | /* Read memory from the inferior. |
d9311bfa AT |
268 | BYTE_ORDER is ignored and there to keep compatiblity with GDB's |
269 | read_memory_unsigned_integer. */ | |
270 | static ULONGEST | |
271 | get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, | |
272 | int len, | |
273 | int byte_order) | |
274 | { | |
275 | ULONGEST res; | |
276 | ||
9e784964 | 277 | res = 0; |
694b382c AT |
278 | target_read_memory (memaddr, (unsigned char *) &res, len); |
279 | ||
d9311bfa AT |
280 | return res; |
281 | } | |
282 | ||
9308fc88 DJ |
283 | /* Fetch the thread-local storage pointer for libthread_db. */ |
284 | ||
285 | ps_err_e | |
754653a7 | 286 | ps_get_thread_area (struct ps_prochandle *ph, |
1b3f6016 | 287 | lwpid_t lwpid, int idx, void **base) |
9308fc88 DJ |
288 | { |
289 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
290 | return PS_ERR; | |
291 | ||
292 | /* IDX is the bias from the thread pointer to the beginning of the | |
293 | thread descriptor. It has to be subtracted due to implementation | |
294 | quirks in libthread_db. */ | |
295 | *base = (void *) ((char *)*base - idx); | |
296 | ||
297 | return PS_OK; | |
298 | } | |
299 | ||
09b4ad9f | 300 | |
71487fd7 UW |
301 | /* Query Hardware Breakpoint information for the target we are attached to |
302 | (using PID as ptrace argument) and set up arm_linux_hwbp_cap. */ | |
303 | static void | |
304 | arm_linux_init_hwbp_cap (int pid) | |
09b4ad9f | 305 | { |
71487fd7 | 306 | unsigned int val; |
09b4ad9f | 307 | |
71487fd7 UW |
308 | if (ptrace (PTRACE_GETHBPREGS, pid, 0, &val) < 0) |
309 | return; | |
09b4ad9f | 310 | |
71487fd7 UW |
311 | arm_linux_hwbp_cap.arch = (unsigned char)((val >> 24) & 0xff); |
312 | if (arm_linux_hwbp_cap.arch == 0) | |
313 | return; | |
09b4ad9f | 314 | |
71487fd7 UW |
315 | arm_linux_hwbp_cap.max_wp_length = (unsigned char)((val >> 16) & 0xff); |
316 | arm_linux_hwbp_cap.wp_count = (unsigned char)((val >> 8) & 0xff); | |
317 | arm_linux_hwbp_cap.bp_count = (unsigned char)(val & 0xff); | |
09b4ad9f | 318 | |
71487fd7 UW |
319 | if (arm_linux_hwbp_cap.wp_count > MAX_WPTS) |
320 | internal_error (__FILE__, __LINE__, "Unsupported number of watchpoints"); | |
321 | if (arm_linux_hwbp_cap.bp_count > MAX_BPTS) | |
322 | internal_error (__FILE__, __LINE__, "Unsupported number of breakpoints"); | |
09b4ad9f UW |
323 | } |
324 | ||
325 | /* How many hardware breakpoints are available? */ | |
326 | static int | |
327 | arm_linux_get_hw_breakpoint_count (void) | |
328 | { | |
71487fd7 | 329 | return arm_linux_hwbp_cap.bp_count; |
09b4ad9f UW |
330 | } |
331 | ||
332 | /* How many hardware watchpoints are available? */ | |
333 | static int | |
334 | arm_linux_get_hw_watchpoint_count (void) | |
335 | { | |
71487fd7 | 336 | return arm_linux_hwbp_cap.wp_count; |
09b4ad9f UW |
337 | } |
338 | ||
339 | /* Maximum length of area watched by hardware watchpoint. */ | |
340 | static int | |
341 | arm_linux_get_hw_watchpoint_max_length (void) | |
342 | { | |
71487fd7 | 343 | return arm_linux_hwbp_cap.max_wp_length; |
09b4ad9f UW |
344 | } |
345 | ||
346 | /* Initialize an ARM hardware break-/watch-point control register value. | |
347 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the | |
348 | type of break-/watch-point; ENABLE indicates whether the point is enabled. | |
349 | */ | |
350 | static arm_hwbp_control_t | |
351 | arm_hwbp_control_initialize (unsigned byte_address_select, | |
352 | arm_hwbp_type hwbp_type, | |
353 | int enable) | |
354 | { | |
355 | gdb_assert ((byte_address_select & ~0xffU) == 0); | |
356 | gdb_assert (hwbp_type != arm_hwbp_break | |
357 | || ((byte_address_select & 0xfU) != 0)); | |
358 | ||
359 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; | |
360 | } | |
361 | ||
362 | /* Does the breakpoint control value CONTROL have the enable bit set? */ | |
363 | static int | |
364 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) | |
365 | { | |
366 | return control & 0x1; | |
367 | } | |
368 | ||
369 | /* Is the breakpoint control value CONTROL initialized? */ | |
370 | static int | |
371 | arm_hwbp_control_is_initialized (arm_hwbp_control_t control) | |
372 | { | |
373 | return control != 0; | |
374 | } | |
375 | ||
376 | /* Change a breakpoint control word so that it is in the disabled state. */ | |
377 | static arm_hwbp_control_t | |
378 | arm_hwbp_control_disable (arm_hwbp_control_t control) | |
379 | { | |
380 | return control & ~0x1; | |
381 | } | |
382 | ||
383 | /* Are two break-/watch-points equal? */ | |
384 | static int | |
385 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, | |
386 | const struct arm_linux_hw_breakpoint *p2) | |
387 | { | |
388 | return p1->address == p2->address && p1->control == p2->control; | |
389 | } | |
390 | ||
802e8e6d PA |
391 | /* Convert a raw breakpoint type to an enum arm_hwbp_type. */ |
392 | ||
171de4b8 | 393 | static arm_hwbp_type |
802e8e6d PA |
394 | raw_bkpt_type_to_arm_hwbp_type (enum raw_bkpt_type raw_type) |
395 | { | |
396 | switch (raw_type) | |
397 | { | |
398 | case raw_bkpt_type_hw: | |
399 | return arm_hwbp_break; | |
400 | case raw_bkpt_type_write_wp: | |
401 | return arm_hwbp_store; | |
402 | case raw_bkpt_type_read_wp: | |
403 | return arm_hwbp_load; | |
404 | case raw_bkpt_type_access_wp: | |
405 | return arm_hwbp_access; | |
406 | default: | |
407 | gdb_assert_not_reached ("unhandled raw type"); | |
408 | } | |
409 | } | |
410 | ||
09b4ad9f UW |
411 | /* Initialize the hardware breakpoint structure P for a breakpoint or |
412 | watchpoint at ADDR to LEN. The type of watchpoint is given in TYPE. | |
b62e2b27 UW |
413 | Returns -1 if TYPE is unsupported, or -2 if the particular combination |
414 | of ADDR and LEN cannot be implemented. Otherwise, returns 0 if TYPE | |
415 | represents a breakpoint and 1 if type represents a watchpoint. */ | |
09b4ad9f | 416 | static int |
802e8e6d PA |
417 | arm_linux_hw_point_initialize (enum raw_bkpt_type raw_type, CORE_ADDR addr, |
418 | int len, struct arm_linux_hw_breakpoint *p) | |
09b4ad9f UW |
419 | { |
420 | arm_hwbp_type hwbp_type; | |
421 | unsigned mask; | |
422 | ||
802e8e6d | 423 | hwbp_type = raw_bkpt_type_to_arm_hwbp_type (raw_type); |
09b4ad9f UW |
424 | |
425 | if (hwbp_type == arm_hwbp_break) | |
426 | { | |
427 | /* For breakpoints, the length field encodes the mode. */ | |
428 | switch (len) | |
429 | { | |
430 | case 2: /* 16-bit Thumb mode breakpoint */ | |
431 | case 3: /* 32-bit Thumb mode breakpoint */ | |
fcf303ab UW |
432 | mask = 0x3; |
433 | addr &= ~1; | |
09b4ad9f UW |
434 | break; |
435 | case 4: /* 32-bit ARM mode breakpoint */ | |
436 | mask = 0xf; | |
fcf303ab | 437 | addr &= ~3; |
09b4ad9f UW |
438 | break; |
439 | default: | |
440 | /* Unsupported. */ | |
b62e2b27 | 441 | return -2; |
09b4ad9f | 442 | } |
09b4ad9f UW |
443 | } |
444 | else | |
445 | { | |
446 | CORE_ADDR max_wp_length = arm_linux_get_hw_watchpoint_max_length (); | |
447 | CORE_ADDR aligned_addr; | |
448 | ||
449 | /* Can not set watchpoints for zero or negative lengths. */ | |
450 | if (len <= 0) | |
b62e2b27 | 451 | return -2; |
09b4ad9f UW |
452 | /* The current ptrace interface can only handle watchpoints that are a |
453 | power of 2. */ | |
454 | if ((len & (len - 1)) != 0) | |
b62e2b27 | 455 | return -2; |
09b4ad9f UW |
456 | |
457 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address | |
458 | range covered by a watchpoint. */ | |
459 | aligned_addr = addr & ~(max_wp_length - 1); | |
460 | if (aligned_addr + max_wp_length < addr + len) | |
b62e2b27 | 461 | return -2; |
09b4ad9f UW |
462 | |
463 | mask = (1 << len) - 1; | |
464 | } | |
465 | ||
466 | p->address = (unsigned int) addr; | |
467 | p->control = arm_hwbp_control_initialize (mask, hwbp_type, 1); | |
468 | ||
469 | return hwbp_type != arm_hwbp_break; | |
470 | } | |
471 | ||
472 | /* Callback to mark a watch-/breakpoint to be updated in all threads of | |
473 | the current process. */ | |
474 | ||
00192f77 SM |
475 | static void |
476 | update_registers_callback (thread_info *thread, int watch, int i) | |
09b4ad9f | 477 | { |
d86d4aaf | 478 | struct lwp_info *lwp = get_thread_lwp (thread); |
09b4ad9f | 479 | |
00192f77 SM |
480 | /* The actual update is done later just before resuming the lwp, |
481 | we just mark that the registers need updating. */ | |
482 | if (watch) | |
483 | lwp->arch_private->wpts_changed[i] = 1; | |
484 | else | |
485 | lwp->arch_private->bpts_changed[i] = 1; | |
09b4ad9f | 486 | |
00192f77 SM |
487 | /* If the lwp isn't stopped, force it to momentarily pause, so |
488 | we can update its breakpoint registers. */ | |
489 | if (!lwp->stopped) | |
490 | linux_stop_lwp (lwp); | |
09b4ad9f UW |
491 | } |
492 | ||
802e8e6d PA |
493 | static int |
494 | arm_supports_z_point_type (char z_type) | |
495 | { | |
496 | switch (z_type) | |
497 | { | |
abeead09 | 498 | case Z_PACKET_SW_BP: |
802e8e6d PA |
499 | case Z_PACKET_HW_BP: |
500 | case Z_PACKET_WRITE_WP: | |
501 | case Z_PACKET_READ_WP: | |
502 | case Z_PACKET_ACCESS_WP: | |
503 | return 1; | |
504 | default: | |
505 | /* Leave the handling of sw breakpoints with the gdb client. */ | |
506 | return 0; | |
507 | } | |
508 | } | |
509 | ||
09b4ad9f UW |
510 | /* Insert hardware break-/watchpoint. */ |
511 | static int | |
802e8e6d PA |
512 | arm_insert_point (enum raw_bkpt_type type, CORE_ADDR addr, |
513 | int len, struct raw_breakpoint *bp) | |
09b4ad9f UW |
514 | { |
515 | struct process_info *proc = current_process (); | |
516 | struct arm_linux_hw_breakpoint p, *pts; | |
517 | int watch, i, count; | |
518 | ||
519 | watch = arm_linux_hw_point_initialize (type, addr, len, &p); | |
520 | if (watch < 0) | |
521 | { | |
522 | /* Unsupported. */ | |
b62e2b27 | 523 | return watch == -1 ? 1 : -1; |
09b4ad9f UW |
524 | } |
525 | ||
526 | if (watch) | |
527 | { | |
528 | count = arm_linux_get_hw_watchpoint_count (); | |
fe978cb0 | 529 | pts = proc->priv->arch_private->wpts; |
09b4ad9f UW |
530 | } |
531 | else | |
532 | { | |
533 | count = arm_linux_get_hw_breakpoint_count (); | |
fe978cb0 | 534 | pts = proc->priv->arch_private->bpts; |
09b4ad9f UW |
535 | } |
536 | ||
537 | for (i = 0; i < count; i++) | |
538 | if (!arm_hwbp_control_is_enabled (pts[i].control)) | |
539 | { | |
09b4ad9f | 540 | pts[i] = p; |
00192f77 SM |
541 | |
542 | /* Only update the threads of the current process. */ | |
543 | for_each_thread (current_thread->id.pid (), [&] (thread_info *thread) | |
544 | { | |
545 | update_registers_callback (thread, watch, i); | |
546 | }); | |
547 | ||
09b4ad9f UW |
548 | return 0; |
549 | } | |
550 | ||
551 | /* We're out of watchpoints. */ | |
552 | return -1; | |
553 | } | |
554 | ||
555 | /* Remove hardware break-/watchpoint. */ | |
556 | static int | |
802e8e6d PA |
557 | arm_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, |
558 | int len, struct raw_breakpoint *bp) | |
09b4ad9f UW |
559 | { |
560 | struct process_info *proc = current_process (); | |
561 | struct arm_linux_hw_breakpoint p, *pts; | |
562 | int watch, i, count; | |
563 | ||
564 | watch = arm_linux_hw_point_initialize (type, addr, len, &p); | |
565 | if (watch < 0) | |
566 | { | |
567 | /* Unsupported. */ | |
568 | return -1; | |
569 | } | |
570 | ||
571 | if (watch) | |
572 | { | |
573 | count = arm_linux_get_hw_watchpoint_count (); | |
fe978cb0 | 574 | pts = proc->priv->arch_private->wpts; |
09b4ad9f UW |
575 | } |
576 | else | |
577 | { | |
578 | count = arm_linux_get_hw_breakpoint_count (); | |
fe978cb0 | 579 | pts = proc->priv->arch_private->bpts; |
09b4ad9f UW |
580 | } |
581 | ||
582 | for (i = 0; i < count; i++) | |
583 | if (arm_linux_hw_breakpoint_equal (&p, pts + i)) | |
584 | { | |
09b4ad9f | 585 | pts[i].control = arm_hwbp_control_disable (pts[i].control); |
00192f77 SM |
586 | |
587 | /* Only update the threads of the current process. */ | |
588 | for_each_thread (current_thread->id.pid (), [&] (thread_info *thread) | |
589 | { | |
590 | update_registers_callback (thread, watch, i); | |
591 | }); | |
592 | ||
09b4ad9f UW |
593 | return 0; |
594 | } | |
595 | ||
596 | /* No watchpoint matched. */ | |
597 | return -1; | |
598 | } | |
599 | ||
600 | /* Return whether current thread is stopped due to a watchpoint. */ | |
601 | static int | |
602 | arm_stopped_by_watchpoint (void) | |
603 | { | |
0bfdf32f | 604 | struct lwp_info *lwp = get_thread_lwp (current_thread); |
a5362b9a | 605 | siginfo_t siginfo; |
09b4ad9f UW |
606 | |
607 | /* We must be able to set hardware watchpoints. */ | |
608 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
609 | return 0; | |
610 | ||
611 | /* Retrieve siginfo. */ | |
612 | errno = 0; | |
0bfdf32f | 613 | ptrace (PTRACE_GETSIGINFO, lwpid_of (current_thread), 0, &siginfo); |
09b4ad9f UW |
614 | if (errno != 0) |
615 | return 0; | |
616 | ||
617 | /* This must be a hardware breakpoint. */ | |
618 | if (siginfo.si_signo != SIGTRAP | |
619 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
620 | return 0; | |
621 | ||
622 | /* If we are in a positive slot then we're looking at a breakpoint and not | |
623 | a watchpoint. */ | |
624 | if (siginfo.si_errno >= 0) | |
625 | return 0; | |
626 | ||
627 | /* Cache stopped data address for use by arm_stopped_data_address. */ | |
628 | lwp->arch_private->stopped_data_address | |
629 | = (CORE_ADDR) (uintptr_t) siginfo.si_addr; | |
630 | ||
631 | return 1; | |
632 | } | |
633 | ||
634 | /* Return data address that triggered watchpoint. Called only if | |
635 | arm_stopped_by_watchpoint returned true. */ | |
636 | static CORE_ADDR | |
637 | arm_stopped_data_address (void) | |
638 | { | |
0bfdf32f | 639 | struct lwp_info *lwp = get_thread_lwp (current_thread); |
09b4ad9f UW |
640 | return lwp->arch_private->stopped_data_address; |
641 | } | |
642 | ||
643 | /* Called when a new process is created. */ | |
644 | static struct arch_process_info * | |
645 | arm_new_process (void) | |
646 | { | |
8d749320 | 647 | struct arch_process_info *info = XCNEW (struct arch_process_info); |
09b4ad9f UW |
648 | return info; |
649 | } | |
650 | ||
04ec7890 SM |
651 | /* Called when a process is being deleted. */ |
652 | ||
653 | static void | |
654 | arm_delete_process (struct arch_process_info *info) | |
655 | { | |
656 | xfree (info); | |
657 | } | |
658 | ||
09b4ad9f | 659 | /* Called when a new thread is detected. */ |
34c703da GB |
660 | static void |
661 | arm_new_thread (struct lwp_info *lwp) | |
09b4ad9f | 662 | { |
8d749320 | 663 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); |
09b4ad9f UW |
664 | int i; |
665 | ||
666 | for (i = 0; i < MAX_BPTS; i++) | |
667 | info->bpts_changed[i] = 1; | |
668 | for (i = 0; i < MAX_WPTS; i++) | |
669 | info->wpts_changed[i] = 1; | |
670 | ||
34c703da | 671 | lwp->arch_private = info; |
09b4ad9f UW |
672 | } |
673 | ||
466eecee SM |
674 | /* Function to call when a thread is being deleted. */ |
675 | ||
676 | static void | |
677 | arm_delete_thread (struct arch_lwp_info *arch_lwp) | |
678 | { | |
679 | xfree (arch_lwp); | |
680 | } | |
681 | ||
3a8a0396 DB |
682 | static void |
683 | arm_new_fork (struct process_info *parent, struct process_info *child) | |
684 | { | |
69291610 HW |
685 | struct arch_process_info *parent_proc_info; |
686 | struct arch_process_info *child_proc_info; | |
3a8a0396 DB |
687 | struct lwp_info *child_lwp; |
688 | struct arch_lwp_info *child_lwp_info; | |
689 | int i; | |
690 | ||
691 | /* These are allocated by linux_add_process. */ | |
61a7418c DB |
692 | gdb_assert (parent->priv != NULL |
693 | && parent->priv->arch_private != NULL); | |
694 | gdb_assert (child->priv != NULL | |
695 | && child->priv->arch_private != NULL); | |
3a8a0396 | 696 | |
69291610 HW |
697 | parent_proc_info = parent->priv->arch_private; |
698 | child_proc_info = child->priv->arch_private; | |
699 | ||
3a8a0396 DB |
700 | /* Linux kernel before 2.6.33 commit |
701 | 72f674d203cd230426437cdcf7dd6f681dad8b0d | |
702 | will inherit hardware debug registers from parent | |
703 | on fork/vfork/clone. Newer Linux kernels create such tasks with | |
704 | zeroed debug registers. | |
705 | ||
706 | GDB core assumes the child inherits the watchpoints/hw | |
707 | breakpoints of the parent, and will remove them all from the | |
708 | forked off process. Copy the debug registers mirrors into the | |
709 | new process so that all breakpoints and watchpoints can be | |
710 | removed together. The debug registers mirror will become zeroed | |
711 | in the end before detaching the forked off process, thus making | |
712 | this compatible with older Linux kernels too. */ | |
713 | ||
714 | *child_proc_info = *parent_proc_info; | |
715 | ||
716 | /* Mark all the hardware breakpoints and watchpoints as changed to | |
717 | make sure that the registers will be updated. */ | |
9179355e | 718 | child_lwp = find_lwp_pid (ptid_t (child->pid)); |
3a8a0396 DB |
719 | child_lwp_info = child_lwp->arch_private; |
720 | for (i = 0; i < MAX_BPTS; i++) | |
721 | child_lwp_info->bpts_changed[i] = 1; | |
722 | for (i = 0; i < MAX_WPTS; i++) | |
723 | child_lwp_info->wpts_changed[i] = 1; | |
724 | } | |
725 | ||
09b4ad9f UW |
726 | /* Called when resuming a thread. |
727 | If the debug regs have changed, update the thread's copies. */ | |
728 | static void | |
729 | arm_prepare_to_resume (struct lwp_info *lwp) | |
730 | { | |
d86d4aaf DE |
731 | struct thread_info *thread = get_lwp_thread (lwp); |
732 | int pid = lwpid_of (thread); | |
733 | struct process_info *proc = find_process_pid (pid_of (thread)); | |
fe978cb0 | 734 | struct arch_process_info *proc_info = proc->priv->arch_private; |
09b4ad9f UW |
735 | struct arch_lwp_info *lwp_info = lwp->arch_private; |
736 | int i; | |
737 | ||
738 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) | |
739 | if (lwp_info->bpts_changed[i]) | |
740 | { | |
741 | errno = 0; | |
742 | ||
743 | if (arm_hwbp_control_is_enabled (proc_info->bpts[i].control)) | |
f15f9948 | 744 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 745 | (PTRACE_TYPE_ARG3) ((i << 1) + 1), |
f15f9948 | 746 | &proc_info->bpts[i].address) < 0) |
71487fd7 | 747 | perror_with_name ("Unexpected error setting breakpoint address"); |
09b4ad9f UW |
748 | |
749 | if (arm_hwbp_control_is_initialized (proc_info->bpts[i].control)) | |
f15f9948 | 750 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 751 | (PTRACE_TYPE_ARG3) ((i << 1) + 2), |
f15f9948 | 752 | &proc_info->bpts[i].control) < 0) |
71487fd7 | 753 | perror_with_name ("Unexpected error setting breakpoint"); |
09b4ad9f UW |
754 | |
755 | lwp_info->bpts_changed[i] = 0; | |
756 | } | |
757 | ||
758 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) | |
759 | if (lwp_info->wpts_changed[i]) | |
760 | { | |
761 | errno = 0; | |
762 | ||
763 | if (arm_hwbp_control_is_enabled (proc_info->wpts[i].control)) | |
f15f9948 | 764 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 765 | (PTRACE_TYPE_ARG3) -((i << 1) + 1), |
f15f9948 | 766 | &proc_info->wpts[i].address) < 0) |
71487fd7 | 767 | perror_with_name ("Unexpected error setting watchpoint address"); |
09b4ad9f UW |
768 | |
769 | if (arm_hwbp_control_is_initialized (proc_info->wpts[i].control)) | |
f15f9948 | 770 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 771 | (PTRACE_TYPE_ARG3) -((i << 1) + 2), |
f15f9948 | 772 | &proc_info->wpts[i].control) < 0) |
71487fd7 | 773 | perror_with_name ("Unexpected error setting watchpoint"); |
09b4ad9f UW |
774 | |
775 | lwp_info->wpts_changed[i] = 0; | |
776 | } | |
777 | } | |
778 | ||
f7a6a40d YQ |
779 | /* Find the next pc for a sigreturn or rt_sigreturn syscall. In |
780 | addition, set IS_THUMB depending on whether we will return to ARM | |
781 | or Thumb code. | |
d9311bfa AT |
782 | See arm-linux.h for stack layout details. */ |
783 | static CORE_ADDR | |
f7a6a40d YQ |
784 | arm_sigreturn_next_pc (struct regcache *regcache, int svc_number, |
785 | int *is_thumb) | |
d9311bfa AT |
786 | { |
787 | unsigned long sp; | |
788 | unsigned long sp_data; | |
789 | /* Offset of PC register. */ | |
790 | int pc_offset = 0; | |
791 | CORE_ADDR next_pc = 0; | |
cf2ebb6e | 792 | uint32_t cpsr; |
d9311bfa AT |
793 | |
794 | gdb_assert (svc_number == __NR_sigreturn || svc_number == __NR_rt_sigreturn); | |
795 | ||
796 | collect_register_by_name (regcache, "sp", &sp); | |
52405d85 | 797 | the_target->read_memory (sp, (unsigned char *) &sp_data, 4); |
d9311bfa AT |
798 | |
799 | pc_offset = arm_linux_sigreturn_next_pc_offset | |
800 | (sp, sp_data, svc_number, __NR_sigreturn == svc_number ? 1 : 0); | |
801 | ||
52405d85 | 802 | the_target->read_memory (sp + pc_offset, (unsigned char *) &next_pc, 4); |
d9311bfa | 803 | |
f7a6a40d | 804 | /* Set IS_THUMB according the CPSR saved on the stack. */ |
52405d85 | 805 | the_target->read_memory (sp + pc_offset + 4, (unsigned char *) &cpsr, 4); |
f7a6a40d YQ |
806 | *is_thumb = ((cpsr & CPSR_T) != 0); |
807 | ||
d9311bfa AT |
808 | return next_pc; |
809 | } | |
810 | ||
811 | /* When PC is at a syscall instruction, return the PC of the next | |
812 | instruction to be executed. */ | |
813 | static CORE_ADDR | |
553cb527 | 814 | get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self) |
d9311bfa AT |
815 | { |
816 | CORE_ADDR next_pc = 0; | |
553cb527 | 817 | CORE_ADDR pc = regcache_read_pc (self->regcache); |
d9311bfa AT |
818 | int is_thumb = arm_is_thumb_mode (); |
819 | ULONGEST svc_number = 0; | |
820 | struct regcache *regcache = self->regcache; | |
821 | ||
822 | if (is_thumb) | |
823 | { | |
824 | collect_register (regcache, 7, &svc_number); | |
825 | next_pc = pc + 2; | |
826 | } | |
827 | else | |
828 | { | |
829 | unsigned long this_instr; | |
830 | unsigned long svc_operand; | |
831 | ||
694b382c | 832 | target_read_memory (pc, (unsigned char *) &this_instr, 4); |
d9311bfa AT |
833 | svc_operand = (0x00ffffff & this_instr); |
834 | ||
835 | if (svc_operand) /* OABI. */ | |
836 | { | |
837 | svc_number = svc_operand - 0x900000; | |
838 | } | |
839 | else /* EABI. */ | |
840 | { | |
841 | collect_register (regcache, 7, &svc_number); | |
842 | } | |
843 | ||
844 | next_pc = pc + 4; | |
845 | } | |
846 | ||
847 | /* This is a sigreturn or sigreturn_rt syscall. */ | |
848 | if (svc_number == __NR_sigreturn || svc_number == __NR_rt_sigreturn) | |
849 | { | |
f7a6a40d YQ |
850 | /* SIGRETURN or RT_SIGRETURN may affect the arm thumb mode, so |
851 | update IS_THUMB. */ | |
852 | next_pc = arm_sigreturn_next_pc (regcache, svc_number, &is_thumb); | |
d9311bfa AT |
853 | } |
854 | ||
855 | /* Addresses for calling Thumb functions have the bit 0 set. */ | |
856 | if (is_thumb) | |
857 | next_pc = MAKE_THUMB_ADDR (next_pc); | |
858 | ||
859 | return next_pc; | |
860 | } | |
09b4ad9f | 861 | |
3aee8918 PA |
862 | static const struct target_desc * |
863 | arm_read_description (void) | |
58d6951d | 864 | { |
974c89e0 | 865 | unsigned long arm_hwcap = linux_get_hwcap (4); |
71487fd7 | 866 | |
58d6951d | 867 | if (arm_hwcap & HWCAP_IWMMXT) |
7cc17433 | 868 | return arm_linux_read_description (ARM_FP_TYPE_IWMMXT); |
58d6951d DJ |
869 | |
870 | if (arm_hwcap & HWCAP_VFP) | |
871 | { | |
166a82be AH |
872 | /* Make sure that the kernel supports reading VFP registers. Support was |
873 | added in 2.6.30. */ | |
874 | int pid = lwpid_of (current_thread); | |
875 | errno = 0; | |
876 | char *buf = (char *) alloca (ARM_VFP3_REGS_SIZE); | |
877 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 && errno == EIO) | |
7cc17433 | 878 | return arm_linux_read_description (ARM_FP_TYPE_NONE); |
58d6951d DJ |
879 | |
880 | /* NEON implies either no VFP, or VFPv3-D32. We only support | |
881 | it with VFP. */ | |
882 | if (arm_hwcap & HWCAP_NEON) | |
7cc17433 | 883 | return aarch32_linux_read_description (); |
58d6951d | 884 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) |
7cc17433 | 885 | return arm_linux_read_description (ARM_FP_TYPE_VFPV3); |
58d6951d | 886 | else |
7cc17433 | 887 | return arm_linux_read_description (ARM_FP_TYPE_VFPV2); |
58d6951d DJ |
888 | } |
889 | ||
890 | /* The default configuration uses legacy FPA registers, probably | |
891 | simulated. */ | |
7cc17433 | 892 | return arm_linux_read_description (ARM_FP_TYPE_NONE); |
58d6951d DJ |
893 | } |
894 | ||
797bcff5 TBA |
895 | void |
896 | arm_target::low_arch_setup () | |
3aee8918 | 897 | { |
bd9e6534 YQ |
898 | int tid = lwpid_of (current_thread); |
899 | int gpregs[18]; | |
900 | struct iovec iov; | |
901 | ||
166a82be AH |
902 | /* Query hardware watchpoint/breakpoint capabilities. */ |
903 | arm_linux_init_hwbp_cap (tid); | |
904 | ||
3aee8918 | 905 | current_process ()->tdesc = arm_read_description (); |
bd9e6534 YQ |
906 | |
907 | iov.iov_base = gpregs; | |
908 | iov.iov_len = sizeof (gpregs); | |
909 | ||
910 | /* Check if PTRACE_GETREGSET works. */ | |
911 | if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) == 0) | |
912 | have_ptrace_getregset = 1; | |
913 | else | |
914 | have_ptrace_getregset = 0; | |
3aee8918 PA |
915 | } |
916 | ||
d9311bfa AT |
917 | /* Fetch the next possible PCs after the current instruction executes. */ |
918 | ||
a0ff9e1a | 919 | static std::vector<CORE_ADDR> |
4d18591b | 920 | arm_gdbserver_get_next_pcs (struct regcache *regcache) |
d9311bfa AT |
921 | { |
922 | struct arm_get_next_pcs next_pcs_ctx; | |
d9311bfa AT |
923 | |
924 | arm_get_next_pcs_ctor (&next_pcs_ctx, | |
925 | &get_next_pcs_ops, | |
926 | /* Byte order is ignored assumed as host. */ | |
927 | 0, | |
928 | 0, | |
1b451dda | 929 | 1, |
d9311bfa AT |
930 | regcache); |
931 | ||
a0ff9e1a | 932 | return arm_get_next_pcs (&next_pcs_ctx); |
d9311bfa AT |
933 | } |
934 | ||
7d00775e AT |
935 | /* Support for hardware single step. */ |
936 | ||
937 | static int | |
938 | arm_supports_hardware_single_step (void) | |
939 | { | |
940 | return 0; | |
941 | } | |
942 | ||
79e7fd4f YQ |
943 | /* Implementation of linux_target_ops method "get_syscall_trapinfo". */ |
944 | ||
945 | static void | |
946 | arm_get_syscall_trapinfo (struct regcache *regcache, int *sysno) | |
947 | { | |
948 | if (arm_is_thumb_mode ()) | |
949 | collect_register_by_name (regcache, "r7", sysno); | |
950 | else | |
951 | { | |
952 | unsigned long pc; | |
953 | unsigned long insn; | |
954 | ||
955 | collect_register_by_name (regcache, "pc", &pc); | |
956 | ||
52405d85 | 957 | if (the_target->read_memory (pc - 4, (unsigned char *) &insn, 4)) |
79e7fd4f YQ |
958 | *sysno = UNKNOWN_SYSCALL; |
959 | else | |
960 | { | |
961 | unsigned long svc_operand = (0x00ffffff & insn); | |
962 | ||
963 | if (svc_operand) | |
964 | { | |
965 | /* OABI */ | |
966 | *sysno = svc_operand - 0x900000; | |
967 | } | |
968 | else | |
969 | { | |
970 | /* EABI */ | |
971 | collect_register_by_name (regcache, "r7", sysno); | |
972 | } | |
973 | } | |
974 | } | |
975 | } | |
976 | ||
bd9e6534 YQ |
977 | /* Register sets without using PTRACE_GETREGSET. */ |
978 | ||
3aee8918 | 979 | static struct regset_info arm_regsets[] = { |
350fab54 AH |
980 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, |
981 | ARM_CORE_REGS_SIZE + ARM_INT_REGISTER_SIZE, GENERAL_REGS, | |
fb1e4ffc | 982 | arm_fill_gregset, arm_store_gregset }, |
350fab54 | 983 | { PTRACE_GETWMMXREGS, PTRACE_SETWMMXREGS, 0, IWMMXT_REGS_SIZE, EXTENDED_REGS, |
fb1e4ffc | 984 | arm_fill_wmmxregset, arm_store_wmmxregset }, |
350fab54 | 985 | { PTRACE_GETVFPREGS, PTRACE_SETVFPREGS, 0, ARM_VFP3_REGS_SIZE, EXTENDED_REGS, |
58d6951d | 986 | arm_fill_vfpregset, arm_store_vfpregset }, |
50bc912a | 987 | NULL_REGSET |
fb1e4ffc DJ |
988 | }; |
989 | ||
3aee8918 PA |
990 | static struct regsets_info arm_regsets_info = |
991 | { | |
992 | arm_regsets, /* regsets */ | |
993 | 0, /* num_regsets */ | |
994 | NULL, /* disabled_regsets */ | |
995 | }; | |
996 | ||
997 | static struct usrregs_info arm_usrregs_info = | |
998 | { | |
999 | arm_num_regs, | |
1000 | arm_regmap, | |
1001 | }; | |
1002 | ||
bd9e6534 | 1003 | static struct regs_info regs_info_arm = |
3aee8918 PA |
1004 | { |
1005 | NULL, /* regset_bitmap */ | |
1006 | &arm_usrregs_info, | |
1007 | &arm_regsets_info | |
1008 | }; | |
1009 | ||
1010 | static const struct regs_info * | |
1011 | arm_regs_info (void) | |
1012 | { | |
bd9e6534 YQ |
1013 | const struct target_desc *tdesc = current_process ()->tdesc; |
1014 | ||
1015 | if (have_ptrace_getregset == 1 | |
7cc17433 AH |
1016 | && (is_aarch32_linux_description (tdesc) |
1017 | || arm_linux_get_tdesc_fp_type (tdesc) == ARM_FP_TYPE_VFPV3)) | |
bd9e6534 | 1018 | return ®s_info_aarch32; |
7cc17433 AH |
1019 | |
1020 | return ®s_info_arm; | |
3aee8918 PA |
1021 | } |
1022 | ||
dd373349 | 1023 | struct linux_target_ops the_low_target = { |
dd373349 AT |
1024 | arm_regs_info, |
1025 | arm_cannot_fetch_register, | |
1026 | arm_cannot_store_register, | |
1027 | NULL, /* fetch_register */ | |
276d4552 YQ |
1028 | linux_get_pc_32bit, |
1029 | linux_set_pc_32bit, | |
8689682c | 1030 | arm_breakpoint_kind_from_pc, |
dd373349 | 1031 | arm_sw_breakpoint_from_kind, |
d9311bfa | 1032 | arm_gdbserver_get_next_pcs, |
0d62e5e8 DJ |
1033 | 0, |
1034 | arm_breakpoint_at, | |
802e8e6d | 1035 | arm_supports_z_point_type, |
09b4ad9f UW |
1036 | arm_insert_point, |
1037 | arm_remove_point, | |
1038 | arm_stopped_by_watchpoint, | |
1039 | arm_stopped_data_address, | |
1040 | NULL, /* collect_ptrace_register */ | |
1041 | NULL, /* supply_ptrace_register */ | |
1042 | NULL, /* siginfo_fixup */ | |
1043 | arm_new_process, | |
04ec7890 | 1044 | arm_delete_process, |
09b4ad9f | 1045 | arm_new_thread, |
466eecee | 1046 | arm_delete_thread, |
3a8a0396 | 1047 | arm_new_fork, |
09b4ad9f | 1048 | arm_prepare_to_resume, |
769ef81f AT |
1049 | NULL, /* process_qsupported */ |
1050 | NULL, /* supports_tracepoints */ | |
1051 | NULL, /* get_thread_area */ | |
1052 | NULL, /* install_fast_tracepoint_jump_pad */ | |
1053 | NULL, /* emit_ops */ | |
1054 | NULL, /* get_min_fast_tracepoint_insn_len */ | |
1055 | NULL, /* supports_range_stepping */ | |
7d00775e | 1056 | arm_breakpoint_kind_from_current_state, |
79e7fd4f YQ |
1057 | arm_supports_hardware_single_step, |
1058 | arm_get_syscall_trapinfo, | |
2ec06d2e | 1059 | }; |
3aee8918 | 1060 | |
ef0478f6 TBA |
1061 | /* The linux target ops object. */ |
1062 | ||
1063 | linux_process_target *the_linux_target = &the_arm_target; | |
1064 | ||
3aee8918 PA |
1065 | void |
1066 | initialize_low_arch (void) | |
1067 | { | |
bd9e6534 | 1068 | initialize_low_arch_aarch32 (); |
3aee8918 PA |
1069 | initialize_regsets_info (&arm_regsets_info); |
1070 | } |