Commit | Line | Data |
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0a30fbc4 | 1 | /* GNU/Linux/ARM specific low level interface, for the remote server for GDB. |
b811d2c2 | 2 | Copyright (C) 1995-2020 Free Software Foundation, Inc. |
0a30fbc4 DJ |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
0a30fbc4 DJ |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
0a30fbc4 DJ |
18 | |
19 | #include "server.h" | |
58caa3dc | 20 | #include "linux-low.h" |
deca266c | 21 | #include "arch/arm.h" |
d9311bfa AT |
22 | #include "arch/arm-linux.h" |
23 | #include "arch/arm-get-next-pcs.h" | |
bd9e6534 | 24 | #include "linux-aarch32-low.h" |
7cc17433 AH |
25 | #include "linux-aarch32-tdesc.h" |
26 | #include "linux-arm-tdesc.h" | |
0a30fbc4 | 27 | |
bd9e6534 | 28 | #include <sys/uio.h> |
3743bb4f DE |
29 | /* Don't include elf.h if linux/elf.h got included by gdb_proc_service.h. |
30 | On Bionic elf.h and linux/elf.h have conflicting definitions. */ | |
31 | #ifndef ELFMAG0 | |
58d6951d | 32 | #include <elf.h> |
3743bb4f | 33 | #endif |
5826e159 | 34 | #include "nat/gdb_ptrace.h" |
09b4ad9f | 35 | #include <signal.h> |
d9311bfa | 36 | #include <sys/syscall.h> |
9308fc88 | 37 | |
9308fc88 DJ |
38 | #ifndef PTRACE_GET_THREAD_AREA |
39 | #define PTRACE_GET_THREAD_AREA 22 | |
40 | #endif | |
41 | ||
fb1e4ffc DJ |
42 | #ifndef PTRACE_GETWMMXREGS |
43 | # define PTRACE_GETWMMXREGS 18 | |
44 | # define PTRACE_SETWMMXREGS 19 | |
45 | #endif | |
46 | ||
58d6951d DJ |
47 | #ifndef PTRACE_GETVFPREGS |
48 | # define PTRACE_GETVFPREGS 27 | |
49 | # define PTRACE_SETVFPREGS 28 | |
50 | #endif | |
51 | ||
09b4ad9f UW |
52 | #ifndef PTRACE_GETHBPREGS |
53 | #define PTRACE_GETHBPREGS 29 | |
54 | #define PTRACE_SETHBPREGS 30 | |
55 | #endif | |
56 | ||
ef0478f6 TBA |
57 | /* Linux target op definitions for the ARM architecture. */ |
58 | ||
59 | class arm_target : public linux_process_target | |
60 | { | |
61 | public: | |
62 | ||
aa8d21c9 TBA |
63 | const regs_info *get_regs_info () override; |
64 | ||
06250e4e TBA |
65 | int breakpoint_kind_from_pc (CORE_ADDR *pcptr) override; |
66 | ||
67 | int breakpoint_kind_from_current_state (CORE_ADDR *pcptr) override; | |
68 | ||
3ca4edb6 TBA |
69 | const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override; |
70 | ||
7582c77c TBA |
71 | bool supports_software_single_step () override; |
72 | ||
007c9b97 TBA |
73 | bool supports_z_point_type (char z_type) override; |
74 | ||
b31cdfa6 TBA |
75 | bool supports_hardware_single_step () override; |
76 | ||
797bcff5 TBA |
77 | protected: |
78 | ||
79 | void low_arch_setup () override; | |
daca57a7 TBA |
80 | |
81 | bool low_cannot_fetch_register (int regno) override; | |
82 | ||
83 | bool low_cannot_store_register (int regno) override; | |
bf9ae9d8 TBA |
84 | |
85 | bool low_supports_breakpoints () override; | |
86 | ||
87 | CORE_ADDR low_get_pc (regcache *regcache) override; | |
88 | ||
89 | void low_set_pc (regcache *regcache, CORE_ADDR newpc) override; | |
7582c77c TBA |
90 | |
91 | std::vector<CORE_ADDR> low_get_next_pcs (regcache *regcache) override; | |
d7146cda TBA |
92 | |
93 | bool low_breakpoint_at (CORE_ADDR pc) override; | |
9db9aa23 TBA |
94 | |
95 | int low_insert_point (raw_bkpt_type type, CORE_ADDR addr, | |
96 | int size, raw_breakpoint *bp) override; | |
97 | ||
98 | int low_remove_point (raw_bkpt_type type, CORE_ADDR addr, | |
99 | int size, raw_breakpoint *bp) override; | |
ac1bbaca TBA |
100 | |
101 | bool low_stopped_by_watchpoint () override; | |
102 | ||
103 | CORE_ADDR low_stopped_data_address () override; | |
fd000fb3 TBA |
104 | |
105 | arch_process_info *low_new_process () override; | |
106 | ||
107 | void low_delete_process (arch_process_info *info) override; | |
108 | ||
109 | void low_new_thread (lwp_info *) override; | |
110 | ||
111 | void low_delete_thread (arch_lwp_info *) override; | |
112 | ||
113 | void low_new_fork (process_info *parent, process_info *child) override; | |
d7599cc0 TBA |
114 | |
115 | void low_prepare_to_resume (lwp_info *lwp) override; | |
9eedd27d TBA |
116 | |
117 | bool low_supports_catch_syscall () override; | |
118 | ||
119 | void low_get_syscall_trapinfo (regcache *regcache, int *sysno) override; | |
ef0478f6 TBA |
120 | }; |
121 | ||
122 | /* The singleton target ops object. */ | |
123 | ||
124 | static arm_target the_arm_target; | |
125 | ||
bf9ae9d8 TBA |
126 | bool |
127 | arm_target::low_supports_breakpoints () | |
128 | { | |
129 | return true; | |
130 | } | |
131 | ||
132 | CORE_ADDR | |
133 | arm_target::low_get_pc (regcache *regcache) | |
134 | { | |
135 | return linux_get_pc_32bit (regcache); | |
136 | } | |
137 | ||
138 | void | |
139 | arm_target::low_set_pc (regcache *regcache, CORE_ADDR pc) | |
140 | { | |
141 | linux_set_pc_32bit (regcache, pc); | |
142 | } | |
143 | ||
06250e4e TBA |
144 | int |
145 | arm_target::breakpoint_kind_from_pc (CORE_ADDR *pcptr) | |
146 | { | |
147 | return arm_breakpoint_kind_from_pc (pcptr); | |
148 | } | |
149 | ||
150 | int | |
151 | arm_target::breakpoint_kind_from_current_state (CORE_ADDR *pcptr) | |
152 | { | |
153 | return arm_breakpoint_kind_from_current_state (pcptr); | |
154 | } | |
155 | ||
3ca4edb6 TBA |
156 | const gdb_byte * |
157 | arm_target::sw_breakpoint_from_kind (int kind, int *size) | |
158 | { | |
159 | return arm_sw_breakpoint_from_kind (kind, size); | |
160 | } | |
161 | ||
d7146cda TBA |
162 | bool |
163 | arm_target::low_breakpoint_at (CORE_ADDR pc) | |
164 | { | |
165 | return arm_breakpoint_at (pc); | |
166 | } | |
167 | ||
09b4ad9f | 168 | /* Information describing the hardware breakpoint capabilities. */ |
71487fd7 | 169 | static struct |
09b4ad9f UW |
170 | { |
171 | unsigned char arch; | |
172 | unsigned char max_wp_length; | |
173 | unsigned char wp_count; | |
174 | unsigned char bp_count; | |
71487fd7 | 175 | } arm_linux_hwbp_cap; |
09b4ad9f UW |
176 | |
177 | /* Enum describing the different types of ARM hardware break-/watch-points. */ | |
178 | typedef enum | |
179 | { | |
180 | arm_hwbp_break = 0, | |
181 | arm_hwbp_load = 1, | |
182 | arm_hwbp_store = 2, | |
183 | arm_hwbp_access = 3 | |
184 | } arm_hwbp_type; | |
185 | ||
186 | /* Type describing an ARM Hardware Breakpoint Control register value. */ | |
187 | typedef unsigned int arm_hwbp_control_t; | |
188 | ||
189 | /* Structure used to keep track of hardware break-/watch-points. */ | |
190 | struct arm_linux_hw_breakpoint | |
191 | { | |
192 | /* Address to break on, or being watched. */ | |
193 | unsigned int address; | |
194 | /* Control register for break-/watch- point. */ | |
195 | arm_hwbp_control_t control; | |
196 | }; | |
197 | ||
198 | /* Since we cannot dynamically allocate subfields of arch_process_info, | |
199 | assume a maximum number of supported break-/watchpoints. */ | |
200 | #define MAX_BPTS 32 | |
201 | #define MAX_WPTS 32 | |
202 | ||
203 | /* Per-process arch-specific data we want to keep. */ | |
204 | struct arch_process_info | |
205 | { | |
206 | /* Hardware breakpoints for this process. */ | |
207 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; | |
208 | /* Hardware watchpoints for this process. */ | |
209 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; | |
210 | }; | |
211 | ||
212 | /* Per-thread arch-specific data we want to keep. */ | |
213 | struct arch_lwp_info | |
214 | { | |
215 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
216 | char bpts_changed[MAX_BPTS]; | |
217 | char wpts_changed[MAX_WPTS]; | |
218 | /* Cached stopped data address. */ | |
219 | CORE_ADDR stopped_data_address; | |
220 | }; | |
221 | ||
58d6951d DJ |
222 | /* These are in <asm/elf.h> in current kernels. */ |
223 | #define HWCAP_VFP 64 | |
224 | #define HWCAP_IWMMXT 512 | |
225 | #define HWCAP_NEON 4096 | |
226 | #define HWCAP_VFPv3 8192 | |
227 | #define HWCAP_VFPv3D16 16384 | |
228 | ||
0a30fbc4 DJ |
229 | #ifdef HAVE_SYS_REG_H |
230 | #include <sys/reg.h> | |
231 | #endif | |
232 | ||
23ce3b1c | 233 | #define arm_num_regs 26 |
0a30fbc4 | 234 | |
2ec06d2e | 235 | static int arm_regmap[] = { |
0a30fbc4 DJ |
236 | 0, 4, 8, 12, 16, 20, 24, 28, |
237 | 32, 36, 40, 44, 48, 52, 56, 60, | |
23ce3b1c DJ |
238 | -1, -1, -1, -1, -1, -1, -1, -1, -1, |
239 | 64 | |
0a30fbc4 DJ |
240 | }; |
241 | ||
d9311bfa AT |
242 | /* Forward declarations needed for get_next_pcs ops. */ |
243 | static ULONGEST get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, | |
244 | int len, | |
245 | int byte_order); | |
246 | ||
247 | static CORE_ADDR get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, | |
248 | CORE_ADDR val); | |
249 | ||
553cb527 | 250 | static CORE_ADDR get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self); |
d9311bfa AT |
251 | |
252 | static int get_next_pcs_is_thumb (struct arm_get_next_pcs *self); | |
253 | ||
254 | /* get_next_pcs operations. */ | |
255 | static struct arm_get_next_pcs_ops get_next_pcs_ops = { | |
256 | get_next_pcs_read_memory_unsigned_integer, | |
257 | get_next_pcs_syscall_next_pc, | |
258 | get_next_pcs_addr_bits_remove, | |
ed443b61 YQ |
259 | get_next_pcs_is_thumb, |
260 | arm_linux_get_next_pcs_fixup, | |
d9311bfa AT |
261 | }; |
262 | ||
daca57a7 TBA |
263 | bool |
264 | arm_target::low_cannot_store_register (int regno) | |
0a30fbc4 | 265 | { |
2ec06d2e | 266 | return (regno >= arm_num_regs); |
0a30fbc4 DJ |
267 | } |
268 | ||
daca57a7 TBA |
269 | bool |
270 | arm_target::low_cannot_fetch_register (int regno) | |
0a30fbc4 | 271 | { |
2ec06d2e | 272 | return (regno >= arm_num_regs); |
0a30fbc4 DJ |
273 | } |
274 | ||
fb1e4ffc | 275 | static void |
442ea881 | 276 | arm_fill_wmmxregset (struct regcache *regcache, void *buf) |
fb1e4ffc | 277 | { |
7cc17433 | 278 | if (arm_linux_get_tdesc_fp_type (regcache->tdesc) != ARM_FP_TYPE_IWMMXT) |
58d6951d DJ |
279 | return; |
280 | ||
166a82be | 281 | for (int i = 0; i < 16; i++) |
442ea881 | 282 | collect_register (regcache, arm_num_regs + i, (char *) buf + i * 8); |
fb1e4ffc DJ |
283 | |
284 | /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */ | |
166a82be | 285 | for (int i = 0; i < 6; i++) |
442ea881 PA |
286 | collect_register (regcache, arm_num_regs + i + 16, |
287 | (char *) buf + 16 * 8 + i * 4); | |
fb1e4ffc DJ |
288 | } |
289 | ||
290 | static void | |
442ea881 | 291 | arm_store_wmmxregset (struct regcache *regcache, const void *buf) |
fb1e4ffc | 292 | { |
7cc17433 | 293 | if (arm_linux_get_tdesc_fp_type (regcache->tdesc) != ARM_FP_TYPE_IWMMXT) |
58d6951d DJ |
294 | return; |
295 | ||
166a82be | 296 | for (int i = 0; i < 16; i++) |
442ea881 | 297 | supply_register (regcache, arm_num_regs + i, (char *) buf + i * 8); |
fb1e4ffc DJ |
298 | |
299 | /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */ | |
166a82be | 300 | for (int i = 0; i < 6; i++) |
442ea881 PA |
301 | supply_register (regcache, arm_num_regs + i + 16, |
302 | (char *) buf + 16 * 8 + i * 4); | |
fb1e4ffc DJ |
303 | } |
304 | ||
58d6951d | 305 | static void |
442ea881 | 306 | arm_fill_vfpregset (struct regcache *regcache, void *buf) |
58d6951d | 307 | { |
bd9e6534 | 308 | int num; |
58d6951d | 309 | |
7cc17433 | 310 | if (is_aarch32_linux_description (regcache->tdesc)) |
58d6951d | 311 | num = 32; |
89abb039 | 312 | else |
7cc17433 AH |
313 | { |
314 | arm_fp_type fp_type = arm_linux_get_tdesc_fp_type (regcache->tdesc); | |
315 | ||
316 | if (fp_type == ARM_FP_TYPE_VFPV3) | |
317 | num = 32; | |
318 | else if (fp_type == ARM_FP_TYPE_VFPV2) | |
319 | num = 16; | |
320 | else | |
321 | return; | |
322 | } | |
58d6951d | 323 | |
bd9e6534 | 324 | arm_fill_vfpregset_num (regcache, buf, num); |
58d6951d DJ |
325 | } |
326 | ||
d9311bfa AT |
327 | /* Wrapper of UNMAKE_THUMB_ADDR for get_next_pcs. */ |
328 | static CORE_ADDR | |
329 | get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, CORE_ADDR val) | |
330 | { | |
331 | return UNMAKE_THUMB_ADDR (val); | |
332 | } | |
333 | ||
58d6951d | 334 | static void |
442ea881 | 335 | arm_store_vfpregset (struct regcache *regcache, const void *buf) |
58d6951d | 336 | { |
bd9e6534 | 337 | int num; |
58d6951d | 338 | |
7cc17433 | 339 | if (is_aarch32_linux_description (regcache->tdesc)) |
58d6951d | 340 | num = 32; |
89abb039 | 341 | else |
7cc17433 AH |
342 | { |
343 | arm_fp_type fp_type = arm_linux_get_tdesc_fp_type (regcache->tdesc); | |
344 | ||
345 | if (fp_type == ARM_FP_TYPE_VFPV3) | |
346 | num = 32; | |
347 | else if (fp_type == ARM_FP_TYPE_VFPV2) | |
348 | num = 16; | |
349 | else | |
350 | return; | |
351 | } | |
58d6951d | 352 | |
bd9e6534 | 353 | arm_store_vfpregset_num (regcache, buf, num); |
58d6951d | 354 | } |
fb1e4ffc | 355 | |
d9311bfa AT |
356 | /* Wrapper of arm_is_thumb_mode for get_next_pcs. */ |
357 | static int | |
358 | get_next_pcs_is_thumb (struct arm_get_next_pcs *self) | |
359 | { | |
360 | return arm_is_thumb_mode (); | |
361 | } | |
362 | ||
30baf67b | 363 | /* Read memory from the inferior. |
d9311bfa AT |
364 | BYTE_ORDER is ignored and there to keep compatiblity with GDB's |
365 | read_memory_unsigned_integer. */ | |
366 | static ULONGEST | |
367 | get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, | |
368 | int len, | |
369 | int byte_order) | |
370 | { | |
371 | ULONGEST res; | |
372 | ||
9e784964 | 373 | res = 0; |
694b382c AT |
374 | target_read_memory (memaddr, (unsigned char *) &res, len); |
375 | ||
d9311bfa AT |
376 | return res; |
377 | } | |
378 | ||
9308fc88 DJ |
379 | /* Fetch the thread-local storage pointer for libthread_db. */ |
380 | ||
381 | ps_err_e | |
754653a7 | 382 | ps_get_thread_area (struct ps_prochandle *ph, |
1b3f6016 | 383 | lwpid_t lwpid, int idx, void **base) |
9308fc88 DJ |
384 | { |
385 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
386 | return PS_ERR; | |
387 | ||
388 | /* IDX is the bias from the thread pointer to the beginning of the | |
389 | thread descriptor. It has to be subtracted due to implementation | |
390 | quirks in libthread_db. */ | |
391 | *base = (void *) ((char *)*base - idx); | |
392 | ||
393 | return PS_OK; | |
394 | } | |
395 | ||
09b4ad9f | 396 | |
71487fd7 UW |
397 | /* Query Hardware Breakpoint information for the target we are attached to |
398 | (using PID as ptrace argument) and set up arm_linux_hwbp_cap. */ | |
399 | static void | |
400 | arm_linux_init_hwbp_cap (int pid) | |
09b4ad9f | 401 | { |
71487fd7 | 402 | unsigned int val; |
09b4ad9f | 403 | |
71487fd7 UW |
404 | if (ptrace (PTRACE_GETHBPREGS, pid, 0, &val) < 0) |
405 | return; | |
09b4ad9f | 406 | |
71487fd7 UW |
407 | arm_linux_hwbp_cap.arch = (unsigned char)((val >> 24) & 0xff); |
408 | if (arm_linux_hwbp_cap.arch == 0) | |
409 | return; | |
09b4ad9f | 410 | |
71487fd7 UW |
411 | arm_linux_hwbp_cap.max_wp_length = (unsigned char)((val >> 16) & 0xff); |
412 | arm_linux_hwbp_cap.wp_count = (unsigned char)((val >> 8) & 0xff); | |
413 | arm_linux_hwbp_cap.bp_count = (unsigned char)(val & 0xff); | |
09b4ad9f | 414 | |
71487fd7 UW |
415 | if (arm_linux_hwbp_cap.wp_count > MAX_WPTS) |
416 | internal_error (__FILE__, __LINE__, "Unsupported number of watchpoints"); | |
417 | if (arm_linux_hwbp_cap.bp_count > MAX_BPTS) | |
418 | internal_error (__FILE__, __LINE__, "Unsupported number of breakpoints"); | |
09b4ad9f UW |
419 | } |
420 | ||
421 | /* How many hardware breakpoints are available? */ | |
422 | static int | |
423 | arm_linux_get_hw_breakpoint_count (void) | |
424 | { | |
71487fd7 | 425 | return arm_linux_hwbp_cap.bp_count; |
09b4ad9f UW |
426 | } |
427 | ||
428 | /* How many hardware watchpoints are available? */ | |
429 | static int | |
430 | arm_linux_get_hw_watchpoint_count (void) | |
431 | { | |
71487fd7 | 432 | return arm_linux_hwbp_cap.wp_count; |
09b4ad9f UW |
433 | } |
434 | ||
435 | /* Maximum length of area watched by hardware watchpoint. */ | |
436 | static int | |
437 | arm_linux_get_hw_watchpoint_max_length (void) | |
438 | { | |
71487fd7 | 439 | return arm_linux_hwbp_cap.max_wp_length; |
09b4ad9f UW |
440 | } |
441 | ||
442 | /* Initialize an ARM hardware break-/watch-point control register value. | |
443 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the | |
444 | type of break-/watch-point; ENABLE indicates whether the point is enabled. | |
445 | */ | |
446 | static arm_hwbp_control_t | |
447 | arm_hwbp_control_initialize (unsigned byte_address_select, | |
448 | arm_hwbp_type hwbp_type, | |
449 | int enable) | |
450 | { | |
451 | gdb_assert ((byte_address_select & ~0xffU) == 0); | |
452 | gdb_assert (hwbp_type != arm_hwbp_break | |
453 | || ((byte_address_select & 0xfU) != 0)); | |
454 | ||
455 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; | |
456 | } | |
457 | ||
458 | /* Does the breakpoint control value CONTROL have the enable bit set? */ | |
459 | static int | |
460 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) | |
461 | { | |
462 | return control & 0x1; | |
463 | } | |
464 | ||
465 | /* Is the breakpoint control value CONTROL initialized? */ | |
466 | static int | |
467 | arm_hwbp_control_is_initialized (arm_hwbp_control_t control) | |
468 | { | |
469 | return control != 0; | |
470 | } | |
471 | ||
472 | /* Change a breakpoint control word so that it is in the disabled state. */ | |
473 | static arm_hwbp_control_t | |
474 | arm_hwbp_control_disable (arm_hwbp_control_t control) | |
475 | { | |
476 | return control & ~0x1; | |
477 | } | |
478 | ||
479 | /* Are two break-/watch-points equal? */ | |
480 | static int | |
481 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, | |
482 | const struct arm_linux_hw_breakpoint *p2) | |
483 | { | |
484 | return p1->address == p2->address && p1->control == p2->control; | |
485 | } | |
486 | ||
802e8e6d PA |
487 | /* Convert a raw breakpoint type to an enum arm_hwbp_type. */ |
488 | ||
171de4b8 | 489 | static arm_hwbp_type |
802e8e6d PA |
490 | raw_bkpt_type_to_arm_hwbp_type (enum raw_bkpt_type raw_type) |
491 | { | |
492 | switch (raw_type) | |
493 | { | |
494 | case raw_bkpt_type_hw: | |
495 | return arm_hwbp_break; | |
496 | case raw_bkpt_type_write_wp: | |
497 | return arm_hwbp_store; | |
498 | case raw_bkpt_type_read_wp: | |
499 | return arm_hwbp_load; | |
500 | case raw_bkpt_type_access_wp: | |
501 | return arm_hwbp_access; | |
502 | default: | |
503 | gdb_assert_not_reached ("unhandled raw type"); | |
504 | } | |
505 | } | |
506 | ||
09b4ad9f UW |
507 | /* Initialize the hardware breakpoint structure P for a breakpoint or |
508 | watchpoint at ADDR to LEN. The type of watchpoint is given in TYPE. | |
b62e2b27 UW |
509 | Returns -1 if TYPE is unsupported, or -2 if the particular combination |
510 | of ADDR and LEN cannot be implemented. Otherwise, returns 0 if TYPE | |
511 | represents a breakpoint and 1 if type represents a watchpoint. */ | |
09b4ad9f | 512 | static int |
802e8e6d PA |
513 | arm_linux_hw_point_initialize (enum raw_bkpt_type raw_type, CORE_ADDR addr, |
514 | int len, struct arm_linux_hw_breakpoint *p) | |
09b4ad9f UW |
515 | { |
516 | arm_hwbp_type hwbp_type; | |
517 | unsigned mask; | |
518 | ||
802e8e6d | 519 | hwbp_type = raw_bkpt_type_to_arm_hwbp_type (raw_type); |
09b4ad9f UW |
520 | |
521 | if (hwbp_type == arm_hwbp_break) | |
522 | { | |
523 | /* For breakpoints, the length field encodes the mode. */ | |
524 | switch (len) | |
525 | { | |
526 | case 2: /* 16-bit Thumb mode breakpoint */ | |
527 | case 3: /* 32-bit Thumb mode breakpoint */ | |
fcf303ab UW |
528 | mask = 0x3; |
529 | addr &= ~1; | |
09b4ad9f UW |
530 | break; |
531 | case 4: /* 32-bit ARM mode breakpoint */ | |
532 | mask = 0xf; | |
fcf303ab | 533 | addr &= ~3; |
09b4ad9f UW |
534 | break; |
535 | default: | |
536 | /* Unsupported. */ | |
b62e2b27 | 537 | return -2; |
09b4ad9f | 538 | } |
09b4ad9f UW |
539 | } |
540 | else | |
541 | { | |
542 | CORE_ADDR max_wp_length = arm_linux_get_hw_watchpoint_max_length (); | |
543 | CORE_ADDR aligned_addr; | |
544 | ||
545 | /* Can not set watchpoints for zero or negative lengths. */ | |
546 | if (len <= 0) | |
b62e2b27 | 547 | return -2; |
09b4ad9f UW |
548 | /* The current ptrace interface can only handle watchpoints that are a |
549 | power of 2. */ | |
550 | if ((len & (len - 1)) != 0) | |
b62e2b27 | 551 | return -2; |
09b4ad9f UW |
552 | |
553 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address | |
554 | range covered by a watchpoint. */ | |
555 | aligned_addr = addr & ~(max_wp_length - 1); | |
556 | if (aligned_addr + max_wp_length < addr + len) | |
b62e2b27 | 557 | return -2; |
09b4ad9f UW |
558 | |
559 | mask = (1 << len) - 1; | |
560 | } | |
561 | ||
562 | p->address = (unsigned int) addr; | |
563 | p->control = arm_hwbp_control_initialize (mask, hwbp_type, 1); | |
564 | ||
565 | return hwbp_type != arm_hwbp_break; | |
566 | } | |
567 | ||
568 | /* Callback to mark a watch-/breakpoint to be updated in all threads of | |
569 | the current process. */ | |
570 | ||
00192f77 SM |
571 | static void |
572 | update_registers_callback (thread_info *thread, int watch, int i) | |
09b4ad9f | 573 | { |
d86d4aaf | 574 | struct lwp_info *lwp = get_thread_lwp (thread); |
09b4ad9f | 575 | |
00192f77 SM |
576 | /* The actual update is done later just before resuming the lwp, |
577 | we just mark that the registers need updating. */ | |
578 | if (watch) | |
579 | lwp->arch_private->wpts_changed[i] = 1; | |
580 | else | |
581 | lwp->arch_private->bpts_changed[i] = 1; | |
09b4ad9f | 582 | |
00192f77 SM |
583 | /* If the lwp isn't stopped, force it to momentarily pause, so |
584 | we can update its breakpoint registers. */ | |
585 | if (!lwp->stopped) | |
586 | linux_stop_lwp (lwp); | |
09b4ad9f UW |
587 | } |
588 | ||
007c9b97 TBA |
589 | bool |
590 | arm_target::supports_z_point_type (char z_type) | |
802e8e6d PA |
591 | { |
592 | switch (z_type) | |
593 | { | |
abeead09 | 594 | case Z_PACKET_SW_BP: |
802e8e6d PA |
595 | case Z_PACKET_HW_BP: |
596 | case Z_PACKET_WRITE_WP: | |
597 | case Z_PACKET_READ_WP: | |
598 | case Z_PACKET_ACCESS_WP: | |
007c9b97 | 599 | return true; |
802e8e6d PA |
600 | default: |
601 | /* Leave the handling of sw breakpoints with the gdb client. */ | |
007c9b97 | 602 | return false; |
802e8e6d PA |
603 | } |
604 | } | |
605 | ||
09b4ad9f | 606 | /* Insert hardware break-/watchpoint. */ |
9db9aa23 TBA |
607 | int |
608 | arm_target::low_insert_point (raw_bkpt_type type, CORE_ADDR addr, | |
609 | int len, raw_breakpoint *bp) | |
09b4ad9f UW |
610 | { |
611 | struct process_info *proc = current_process (); | |
612 | struct arm_linux_hw_breakpoint p, *pts; | |
613 | int watch, i, count; | |
614 | ||
615 | watch = arm_linux_hw_point_initialize (type, addr, len, &p); | |
616 | if (watch < 0) | |
617 | { | |
618 | /* Unsupported. */ | |
b62e2b27 | 619 | return watch == -1 ? 1 : -1; |
09b4ad9f UW |
620 | } |
621 | ||
622 | if (watch) | |
623 | { | |
624 | count = arm_linux_get_hw_watchpoint_count (); | |
fe978cb0 | 625 | pts = proc->priv->arch_private->wpts; |
09b4ad9f UW |
626 | } |
627 | else | |
628 | { | |
629 | count = arm_linux_get_hw_breakpoint_count (); | |
fe978cb0 | 630 | pts = proc->priv->arch_private->bpts; |
09b4ad9f UW |
631 | } |
632 | ||
633 | for (i = 0; i < count; i++) | |
634 | if (!arm_hwbp_control_is_enabled (pts[i].control)) | |
635 | { | |
09b4ad9f | 636 | pts[i] = p; |
00192f77 SM |
637 | |
638 | /* Only update the threads of the current process. */ | |
639 | for_each_thread (current_thread->id.pid (), [&] (thread_info *thread) | |
640 | { | |
641 | update_registers_callback (thread, watch, i); | |
642 | }); | |
643 | ||
09b4ad9f UW |
644 | return 0; |
645 | } | |
646 | ||
647 | /* We're out of watchpoints. */ | |
648 | return -1; | |
649 | } | |
650 | ||
651 | /* Remove hardware break-/watchpoint. */ | |
9db9aa23 TBA |
652 | int |
653 | arm_target::low_remove_point (raw_bkpt_type type, CORE_ADDR addr, | |
654 | int len, raw_breakpoint *bp) | |
09b4ad9f UW |
655 | { |
656 | struct process_info *proc = current_process (); | |
657 | struct arm_linux_hw_breakpoint p, *pts; | |
658 | int watch, i, count; | |
659 | ||
660 | watch = arm_linux_hw_point_initialize (type, addr, len, &p); | |
661 | if (watch < 0) | |
662 | { | |
663 | /* Unsupported. */ | |
664 | return -1; | |
665 | } | |
666 | ||
667 | if (watch) | |
668 | { | |
669 | count = arm_linux_get_hw_watchpoint_count (); | |
fe978cb0 | 670 | pts = proc->priv->arch_private->wpts; |
09b4ad9f UW |
671 | } |
672 | else | |
673 | { | |
674 | count = arm_linux_get_hw_breakpoint_count (); | |
fe978cb0 | 675 | pts = proc->priv->arch_private->bpts; |
09b4ad9f UW |
676 | } |
677 | ||
678 | for (i = 0; i < count; i++) | |
679 | if (arm_linux_hw_breakpoint_equal (&p, pts + i)) | |
680 | { | |
09b4ad9f | 681 | pts[i].control = arm_hwbp_control_disable (pts[i].control); |
00192f77 SM |
682 | |
683 | /* Only update the threads of the current process. */ | |
684 | for_each_thread (current_thread->id.pid (), [&] (thread_info *thread) | |
685 | { | |
686 | update_registers_callback (thread, watch, i); | |
687 | }); | |
688 | ||
09b4ad9f UW |
689 | return 0; |
690 | } | |
691 | ||
692 | /* No watchpoint matched. */ | |
693 | return -1; | |
694 | } | |
695 | ||
696 | /* Return whether current thread is stopped due to a watchpoint. */ | |
ac1bbaca TBA |
697 | bool |
698 | arm_target::low_stopped_by_watchpoint () | |
09b4ad9f | 699 | { |
0bfdf32f | 700 | struct lwp_info *lwp = get_thread_lwp (current_thread); |
a5362b9a | 701 | siginfo_t siginfo; |
09b4ad9f UW |
702 | |
703 | /* We must be able to set hardware watchpoints. */ | |
704 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
ac1bbaca | 705 | return false; |
09b4ad9f UW |
706 | |
707 | /* Retrieve siginfo. */ | |
708 | errno = 0; | |
0bfdf32f | 709 | ptrace (PTRACE_GETSIGINFO, lwpid_of (current_thread), 0, &siginfo); |
09b4ad9f | 710 | if (errno != 0) |
ac1bbaca | 711 | return false; |
09b4ad9f UW |
712 | |
713 | /* This must be a hardware breakpoint. */ | |
714 | if (siginfo.si_signo != SIGTRAP | |
715 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
ac1bbaca | 716 | return false; |
09b4ad9f UW |
717 | |
718 | /* If we are in a positive slot then we're looking at a breakpoint and not | |
719 | a watchpoint. */ | |
720 | if (siginfo.si_errno >= 0) | |
ac1bbaca | 721 | return false; |
09b4ad9f UW |
722 | |
723 | /* Cache stopped data address for use by arm_stopped_data_address. */ | |
724 | lwp->arch_private->stopped_data_address | |
725 | = (CORE_ADDR) (uintptr_t) siginfo.si_addr; | |
726 | ||
ac1bbaca | 727 | return true; |
09b4ad9f UW |
728 | } |
729 | ||
730 | /* Return data address that triggered watchpoint. Called only if | |
ac1bbaca TBA |
731 | low_stopped_by_watchpoint returned true. */ |
732 | CORE_ADDR | |
733 | arm_target::low_stopped_data_address () | |
09b4ad9f | 734 | { |
0bfdf32f | 735 | struct lwp_info *lwp = get_thread_lwp (current_thread); |
09b4ad9f UW |
736 | return lwp->arch_private->stopped_data_address; |
737 | } | |
738 | ||
739 | /* Called when a new process is created. */ | |
fd000fb3 TBA |
740 | arch_process_info * |
741 | arm_target::low_new_process () | |
09b4ad9f | 742 | { |
8d749320 | 743 | struct arch_process_info *info = XCNEW (struct arch_process_info); |
09b4ad9f UW |
744 | return info; |
745 | } | |
746 | ||
04ec7890 SM |
747 | /* Called when a process is being deleted. */ |
748 | ||
fd000fb3 TBA |
749 | void |
750 | arm_target::low_delete_process (arch_process_info *info) | |
04ec7890 SM |
751 | { |
752 | xfree (info); | |
753 | } | |
754 | ||
09b4ad9f | 755 | /* Called when a new thread is detected. */ |
fd000fb3 TBA |
756 | void |
757 | arm_target::low_new_thread (lwp_info *lwp) | |
09b4ad9f | 758 | { |
8d749320 | 759 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); |
09b4ad9f UW |
760 | int i; |
761 | ||
762 | for (i = 0; i < MAX_BPTS; i++) | |
763 | info->bpts_changed[i] = 1; | |
764 | for (i = 0; i < MAX_WPTS; i++) | |
765 | info->wpts_changed[i] = 1; | |
766 | ||
34c703da | 767 | lwp->arch_private = info; |
09b4ad9f UW |
768 | } |
769 | ||
466eecee SM |
770 | /* Function to call when a thread is being deleted. */ |
771 | ||
fd000fb3 TBA |
772 | void |
773 | arm_target::low_delete_thread (arch_lwp_info *arch_lwp) | |
466eecee SM |
774 | { |
775 | xfree (arch_lwp); | |
776 | } | |
777 | ||
fd000fb3 TBA |
778 | void |
779 | arm_target::low_new_fork (process_info *parent, process_info *child) | |
3a8a0396 | 780 | { |
69291610 HW |
781 | struct arch_process_info *parent_proc_info; |
782 | struct arch_process_info *child_proc_info; | |
3a8a0396 DB |
783 | struct lwp_info *child_lwp; |
784 | struct arch_lwp_info *child_lwp_info; | |
785 | int i; | |
786 | ||
787 | /* These are allocated by linux_add_process. */ | |
61a7418c DB |
788 | gdb_assert (parent->priv != NULL |
789 | && parent->priv->arch_private != NULL); | |
790 | gdb_assert (child->priv != NULL | |
791 | && child->priv->arch_private != NULL); | |
3a8a0396 | 792 | |
69291610 HW |
793 | parent_proc_info = parent->priv->arch_private; |
794 | child_proc_info = child->priv->arch_private; | |
795 | ||
3a8a0396 DB |
796 | /* Linux kernel before 2.6.33 commit |
797 | 72f674d203cd230426437cdcf7dd6f681dad8b0d | |
798 | will inherit hardware debug registers from parent | |
799 | on fork/vfork/clone. Newer Linux kernels create such tasks with | |
800 | zeroed debug registers. | |
801 | ||
802 | GDB core assumes the child inherits the watchpoints/hw | |
803 | breakpoints of the parent, and will remove them all from the | |
804 | forked off process. Copy the debug registers mirrors into the | |
805 | new process so that all breakpoints and watchpoints can be | |
806 | removed together. The debug registers mirror will become zeroed | |
807 | in the end before detaching the forked off process, thus making | |
808 | this compatible with older Linux kernels too. */ | |
809 | ||
810 | *child_proc_info = *parent_proc_info; | |
811 | ||
812 | /* Mark all the hardware breakpoints and watchpoints as changed to | |
813 | make sure that the registers will be updated. */ | |
9179355e | 814 | child_lwp = find_lwp_pid (ptid_t (child->pid)); |
3a8a0396 DB |
815 | child_lwp_info = child_lwp->arch_private; |
816 | for (i = 0; i < MAX_BPTS; i++) | |
817 | child_lwp_info->bpts_changed[i] = 1; | |
818 | for (i = 0; i < MAX_WPTS; i++) | |
819 | child_lwp_info->wpts_changed[i] = 1; | |
820 | } | |
821 | ||
09b4ad9f UW |
822 | /* Called when resuming a thread. |
823 | If the debug regs have changed, update the thread's copies. */ | |
d7599cc0 TBA |
824 | void |
825 | arm_target::low_prepare_to_resume (lwp_info *lwp) | |
09b4ad9f | 826 | { |
d86d4aaf DE |
827 | struct thread_info *thread = get_lwp_thread (lwp); |
828 | int pid = lwpid_of (thread); | |
829 | struct process_info *proc = find_process_pid (pid_of (thread)); | |
fe978cb0 | 830 | struct arch_process_info *proc_info = proc->priv->arch_private; |
09b4ad9f UW |
831 | struct arch_lwp_info *lwp_info = lwp->arch_private; |
832 | int i; | |
833 | ||
834 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) | |
835 | if (lwp_info->bpts_changed[i]) | |
836 | { | |
837 | errno = 0; | |
838 | ||
839 | if (arm_hwbp_control_is_enabled (proc_info->bpts[i].control)) | |
f15f9948 | 840 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 841 | (PTRACE_TYPE_ARG3) ((i << 1) + 1), |
f15f9948 | 842 | &proc_info->bpts[i].address) < 0) |
71487fd7 | 843 | perror_with_name ("Unexpected error setting breakpoint address"); |
09b4ad9f UW |
844 | |
845 | if (arm_hwbp_control_is_initialized (proc_info->bpts[i].control)) | |
f15f9948 | 846 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 847 | (PTRACE_TYPE_ARG3) ((i << 1) + 2), |
f15f9948 | 848 | &proc_info->bpts[i].control) < 0) |
71487fd7 | 849 | perror_with_name ("Unexpected error setting breakpoint"); |
09b4ad9f UW |
850 | |
851 | lwp_info->bpts_changed[i] = 0; | |
852 | } | |
853 | ||
854 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) | |
855 | if (lwp_info->wpts_changed[i]) | |
856 | { | |
857 | errno = 0; | |
858 | ||
859 | if (arm_hwbp_control_is_enabled (proc_info->wpts[i].control)) | |
f15f9948 | 860 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 861 | (PTRACE_TYPE_ARG3) -((i << 1) + 1), |
f15f9948 | 862 | &proc_info->wpts[i].address) < 0) |
71487fd7 | 863 | perror_with_name ("Unexpected error setting watchpoint address"); |
09b4ad9f UW |
864 | |
865 | if (arm_hwbp_control_is_initialized (proc_info->wpts[i].control)) | |
f15f9948 | 866 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 867 | (PTRACE_TYPE_ARG3) -((i << 1) + 2), |
f15f9948 | 868 | &proc_info->wpts[i].control) < 0) |
71487fd7 | 869 | perror_with_name ("Unexpected error setting watchpoint"); |
09b4ad9f UW |
870 | |
871 | lwp_info->wpts_changed[i] = 0; | |
872 | } | |
873 | } | |
874 | ||
f7a6a40d YQ |
875 | /* Find the next pc for a sigreturn or rt_sigreturn syscall. In |
876 | addition, set IS_THUMB depending on whether we will return to ARM | |
877 | or Thumb code. | |
d9311bfa AT |
878 | See arm-linux.h for stack layout details. */ |
879 | static CORE_ADDR | |
f7a6a40d YQ |
880 | arm_sigreturn_next_pc (struct regcache *regcache, int svc_number, |
881 | int *is_thumb) | |
d9311bfa AT |
882 | { |
883 | unsigned long sp; | |
884 | unsigned long sp_data; | |
885 | /* Offset of PC register. */ | |
886 | int pc_offset = 0; | |
887 | CORE_ADDR next_pc = 0; | |
cf2ebb6e | 888 | uint32_t cpsr; |
d9311bfa AT |
889 | |
890 | gdb_assert (svc_number == __NR_sigreturn || svc_number == __NR_rt_sigreturn); | |
891 | ||
892 | collect_register_by_name (regcache, "sp", &sp); | |
52405d85 | 893 | the_target->read_memory (sp, (unsigned char *) &sp_data, 4); |
d9311bfa AT |
894 | |
895 | pc_offset = arm_linux_sigreturn_next_pc_offset | |
896 | (sp, sp_data, svc_number, __NR_sigreturn == svc_number ? 1 : 0); | |
897 | ||
52405d85 | 898 | the_target->read_memory (sp + pc_offset, (unsigned char *) &next_pc, 4); |
d9311bfa | 899 | |
f7a6a40d | 900 | /* Set IS_THUMB according the CPSR saved on the stack. */ |
52405d85 | 901 | the_target->read_memory (sp + pc_offset + 4, (unsigned char *) &cpsr, 4); |
f7a6a40d YQ |
902 | *is_thumb = ((cpsr & CPSR_T) != 0); |
903 | ||
d9311bfa AT |
904 | return next_pc; |
905 | } | |
906 | ||
907 | /* When PC is at a syscall instruction, return the PC of the next | |
908 | instruction to be executed. */ | |
909 | static CORE_ADDR | |
553cb527 | 910 | get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self) |
d9311bfa AT |
911 | { |
912 | CORE_ADDR next_pc = 0; | |
553cb527 | 913 | CORE_ADDR pc = regcache_read_pc (self->regcache); |
d9311bfa AT |
914 | int is_thumb = arm_is_thumb_mode (); |
915 | ULONGEST svc_number = 0; | |
916 | struct regcache *regcache = self->regcache; | |
917 | ||
918 | if (is_thumb) | |
919 | { | |
920 | collect_register (regcache, 7, &svc_number); | |
921 | next_pc = pc + 2; | |
922 | } | |
923 | else | |
924 | { | |
925 | unsigned long this_instr; | |
926 | unsigned long svc_operand; | |
927 | ||
694b382c | 928 | target_read_memory (pc, (unsigned char *) &this_instr, 4); |
d9311bfa AT |
929 | svc_operand = (0x00ffffff & this_instr); |
930 | ||
931 | if (svc_operand) /* OABI. */ | |
932 | { | |
933 | svc_number = svc_operand - 0x900000; | |
934 | } | |
935 | else /* EABI. */ | |
936 | { | |
937 | collect_register (regcache, 7, &svc_number); | |
938 | } | |
939 | ||
940 | next_pc = pc + 4; | |
941 | } | |
942 | ||
943 | /* This is a sigreturn or sigreturn_rt syscall. */ | |
944 | if (svc_number == __NR_sigreturn || svc_number == __NR_rt_sigreturn) | |
945 | { | |
f7a6a40d YQ |
946 | /* SIGRETURN or RT_SIGRETURN may affect the arm thumb mode, so |
947 | update IS_THUMB. */ | |
948 | next_pc = arm_sigreturn_next_pc (regcache, svc_number, &is_thumb); | |
d9311bfa AT |
949 | } |
950 | ||
951 | /* Addresses for calling Thumb functions have the bit 0 set. */ | |
952 | if (is_thumb) | |
953 | next_pc = MAKE_THUMB_ADDR (next_pc); | |
954 | ||
955 | return next_pc; | |
956 | } | |
09b4ad9f | 957 | |
3aee8918 PA |
958 | static const struct target_desc * |
959 | arm_read_description (void) | |
58d6951d | 960 | { |
974c89e0 | 961 | unsigned long arm_hwcap = linux_get_hwcap (4); |
71487fd7 | 962 | |
58d6951d | 963 | if (arm_hwcap & HWCAP_IWMMXT) |
7cc17433 | 964 | return arm_linux_read_description (ARM_FP_TYPE_IWMMXT); |
58d6951d DJ |
965 | |
966 | if (arm_hwcap & HWCAP_VFP) | |
967 | { | |
166a82be AH |
968 | /* Make sure that the kernel supports reading VFP registers. Support was |
969 | added in 2.6.30. */ | |
970 | int pid = lwpid_of (current_thread); | |
971 | errno = 0; | |
972 | char *buf = (char *) alloca (ARM_VFP3_REGS_SIZE); | |
973 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 && errno == EIO) | |
7cc17433 | 974 | return arm_linux_read_description (ARM_FP_TYPE_NONE); |
58d6951d DJ |
975 | |
976 | /* NEON implies either no VFP, or VFPv3-D32. We only support | |
977 | it with VFP. */ | |
978 | if (arm_hwcap & HWCAP_NEON) | |
7cc17433 | 979 | return aarch32_linux_read_description (); |
58d6951d | 980 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) |
7cc17433 | 981 | return arm_linux_read_description (ARM_FP_TYPE_VFPV3); |
58d6951d | 982 | else |
7cc17433 | 983 | return arm_linux_read_description (ARM_FP_TYPE_VFPV2); |
58d6951d DJ |
984 | } |
985 | ||
986 | /* The default configuration uses legacy FPA registers, probably | |
987 | simulated. */ | |
7cc17433 | 988 | return arm_linux_read_description (ARM_FP_TYPE_NONE); |
58d6951d DJ |
989 | } |
990 | ||
797bcff5 TBA |
991 | void |
992 | arm_target::low_arch_setup () | |
3aee8918 | 993 | { |
bd9e6534 YQ |
994 | int tid = lwpid_of (current_thread); |
995 | int gpregs[18]; | |
996 | struct iovec iov; | |
997 | ||
166a82be AH |
998 | /* Query hardware watchpoint/breakpoint capabilities. */ |
999 | arm_linux_init_hwbp_cap (tid); | |
1000 | ||
3aee8918 | 1001 | current_process ()->tdesc = arm_read_description (); |
bd9e6534 YQ |
1002 | |
1003 | iov.iov_base = gpregs; | |
1004 | iov.iov_len = sizeof (gpregs); | |
1005 | ||
1006 | /* Check if PTRACE_GETREGSET works. */ | |
1007 | if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) == 0) | |
1008 | have_ptrace_getregset = 1; | |
1009 | else | |
1010 | have_ptrace_getregset = 0; | |
3aee8918 PA |
1011 | } |
1012 | ||
7582c77c TBA |
1013 | bool |
1014 | arm_target::supports_software_single_step () | |
1015 | { | |
1016 | return true; | |
1017 | } | |
1018 | ||
d9311bfa AT |
1019 | /* Fetch the next possible PCs after the current instruction executes. */ |
1020 | ||
7582c77c TBA |
1021 | std::vector<CORE_ADDR> |
1022 | arm_target::low_get_next_pcs (regcache *regcache) | |
d9311bfa AT |
1023 | { |
1024 | struct arm_get_next_pcs next_pcs_ctx; | |
d9311bfa AT |
1025 | |
1026 | arm_get_next_pcs_ctor (&next_pcs_ctx, | |
1027 | &get_next_pcs_ops, | |
1028 | /* Byte order is ignored assumed as host. */ | |
1029 | 0, | |
1030 | 0, | |
1b451dda | 1031 | 1, |
d9311bfa AT |
1032 | regcache); |
1033 | ||
a0ff9e1a | 1034 | return arm_get_next_pcs (&next_pcs_ctx); |
d9311bfa AT |
1035 | } |
1036 | ||
7d00775e AT |
1037 | /* Support for hardware single step. */ |
1038 | ||
b31cdfa6 TBA |
1039 | bool |
1040 | arm_target::supports_hardware_single_step () | |
7d00775e | 1041 | { |
b31cdfa6 | 1042 | return false; |
7d00775e AT |
1043 | } |
1044 | ||
9eedd27d TBA |
1045 | bool |
1046 | arm_target::low_supports_catch_syscall () | |
1047 | { | |
1048 | return true; | |
1049 | } | |
79e7fd4f | 1050 | |
9eedd27d TBA |
1051 | /* Implementation of linux target ops method "low_get_syscall_trapinfo". */ |
1052 | ||
1053 | void | |
1054 | arm_target::low_get_syscall_trapinfo (regcache *regcache, int *sysno) | |
79e7fd4f YQ |
1055 | { |
1056 | if (arm_is_thumb_mode ()) | |
1057 | collect_register_by_name (regcache, "r7", sysno); | |
1058 | else | |
1059 | { | |
1060 | unsigned long pc; | |
1061 | unsigned long insn; | |
1062 | ||
1063 | collect_register_by_name (regcache, "pc", &pc); | |
1064 | ||
9eedd27d | 1065 | if (read_memory (pc - 4, (unsigned char *) &insn, 4)) |
79e7fd4f YQ |
1066 | *sysno = UNKNOWN_SYSCALL; |
1067 | else | |
1068 | { | |
1069 | unsigned long svc_operand = (0x00ffffff & insn); | |
1070 | ||
1071 | if (svc_operand) | |
1072 | { | |
1073 | /* OABI */ | |
1074 | *sysno = svc_operand - 0x900000; | |
1075 | } | |
1076 | else | |
1077 | { | |
1078 | /* EABI */ | |
1079 | collect_register_by_name (regcache, "r7", sysno); | |
1080 | } | |
1081 | } | |
1082 | } | |
1083 | } | |
1084 | ||
bd9e6534 YQ |
1085 | /* Register sets without using PTRACE_GETREGSET. */ |
1086 | ||
3aee8918 | 1087 | static struct regset_info arm_regsets[] = { |
350fab54 AH |
1088 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, |
1089 | ARM_CORE_REGS_SIZE + ARM_INT_REGISTER_SIZE, GENERAL_REGS, | |
fb1e4ffc | 1090 | arm_fill_gregset, arm_store_gregset }, |
350fab54 | 1091 | { PTRACE_GETWMMXREGS, PTRACE_SETWMMXREGS, 0, IWMMXT_REGS_SIZE, EXTENDED_REGS, |
fb1e4ffc | 1092 | arm_fill_wmmxregset, arm_store_wmmxregset }, |
350fab54 | 1093 | { PTRACE_GETVFPREGS, PTRACE_SETVFPREGS, 0, ARM_VFP3_REGS_SIZE, EXTENDED_REGS, |
58d6951d | 1094 | arm_fill_vfpregset, arm_store_vfpregset }, |
50bc912a | 1095 | NULL_REGSET |
fb1e4ffc DJ |
1096 | }; |
1097 | ||
3aee8918 PA |
1098 | static struct regsets_info arm_regsets_info = |
1099 | { | |
1100 | arm_regsets, /* regsets */ | |
1101 | 0, /* num_regsets */ | |
1102 | NULL, /* disabled_regsets */ | |
1103 | }; | |
1104 | ||
1105 | static struct usrregs_info arm_usrregs_info = | |
1106 | { | |
1107 | arm_num_regs, | |
1108 | arm_regmap, | |
1109 | }; | |
1110 | ||
bd9e6534 | 1111 | static struct regs_info regs_info_arm = |
3aee8918 PA |
1112 | { |
1113 | NULL, /* regset_bitmap */ | |
1114 | &arm_usrregs_info, | |
1115 | &arm_regsets_info | |
1116 | }; | |
1117 | ||
aa8d21c9 TBA |
1118 | const regs_info * |
1119 | arm_target::get_regs_info () | |
3aee8918 | 1120 | { |
bd9e6534 YQ |
1121 | const struct target_desc *tdesc = current_process ()->tdesc; |
1122 | ||
1123 | if (have_ptrace_getregset == 1 | |
7cc17433 AH |
1124 | && (is_aarch32_linux_description (tdesc) |
1125 | || arm_linux_get_tdesc_fp_type (tdesc) == ARM_FP_TYPE_VFPV3)) | |
bd9e6534 | 1126 | return ®s_info_aarch32; |
7cc17433 AH |
1127 | |
1128 | return ®s_info_arm; | |
3aee8918 PA |
1129 | } |
1130 | ||
ef0478f6 TBA |
1131 | /* The linux target ops object. */ |
1132 | ||
1133 | linux_process_target *the_linux_target = &the_arm_target; | |
1134 | ||
3aee8918 PA |
1135 | void |
1136 | initialize_low_arch (void) | |
1137 | { | |
bd9e6534 | 1138 | initialize_low_arch_aarch32 (); |
3aee8918 PA |
1139 | initialize_regsets_info (&arm_regsets_info); |
1140 | } |