Commit | Line | Data |
---|---|---|
45b134e5 | 1 | /* GNU/Linux/CRIS specific low level interface, for the remote server for GDB. |
b811d2c2 | 2 | Copyright (C) 1995-2020 Free Software Foundation, Inc. |
45b134e5 OF |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
45b134e5 OF |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
45b134e5 OF |
18 | |
19 | #include "server.h" | |
20 | #include "linux-low.h" | |
5826e159 | 21 | #include "nat/gdb_ptrace.h" |
45b134e5 | 22 | |
ef0478f6 TBA |
23 | /* Linux target op definitions for the CRIS architecture. */ |
24 | ||
25 | class crisv32_target : public linux_process_target | |
26 | { | |
27 | public: | |
28 | ||
aa8d21c9 TBA |
29 | const regs_info *get_regs_info () override; |
30 | ||
797bcff5 TBA |
31 | protected: |
32 | ||
33 | void low_arch_setup () override; | |
daca57a7 TBA |
34 | |
35 | bool low_cannot_fetch_register (int regno) override; | |
36 | ||
37 | bool low_cannot_store_register (int regno) override; | |
ef0478f6 TBA |
38 | }; |
39 | ||
40 | /* The singleton target ops object. */ | |
41 | ||
42 | static crisv32_target the_crisv32_target; | |
43 | ||
daca57a7 TBA |
44 | bool |
45 | crisv32_target::low_cannot_fetch_register (int regno) | |
46 | { | |
47 | gdb_assert_not_reached ("linux target op low_cannot_fetch_register " | |
48 | "is not implemented by the target"); | |
49 | } | |
50 | ||
51 | bool | |
52 | crisv32_target::low_cannot_store_register (int regno) | |
53 | { | |
54 | gdb_assert_not_reached ("linux target op low_cannot_store_register " | |
55 | "is not implemented by the target"); | |
56 | } | |
57 | ||
d05b4ac3 UW |
58 | /* Defined in auto-generated file reg-crisv32.c. */ |
59 | void init_registers_crisv32 (void); | |
3aee8918 | 60 | extern const struct target_desc *tdesc_crisv32; |
d05b4ac3 | 61 | |
45b134e5 OF |
62 | /* CRISv32 */ |
63 | #define cris_num_regs 49 | |
64 | ||
8eb3d7b6 RW |
65 | #ifndef PTRACE_GET_THREAD_AREA |
66 | #define PTRACE_GET_THREAD_AREA 25 | |
67 | #endif | |
68 | ||
45b134e5 OF |
69 | /* Note: Ignoring USP (having the stack pointer in two locations causes trouble |
70 | without any significant gain). */ | |
71 | ||
72 | /* Locations need to match <include/asm/arch/ptrace.h>. */ | |
73 | static int cris_regmap[] = { | |
74 | 1*4, 2*4, 3*4, 4*4, | |
75 | 5*4, 6*4, 7*4, 8*4, | |
76 | 9*4, 10*4, 11*4, 12*4, | |
77 | 13*4, 14*4, 24*4, 15*4, | |
78 | ||
79 | -1, -1, -1, 16*4, | |
80 | -1, 22*4, 23*4, 17*4, | |
81 | -1, -1, 21*4, 20*4, | |
82 | -1, 19*4, -1, 18*4, | |
83 | ||
84 | 25*4, | |
85 | ||
1b3f6016 | 86 | 26*4, -1, -1, 29*4, |
45b134e5 OF |
87 | 30*4, 31*4, 32*4, 33*4, |
88 | 34*4, 35*4, 36*4, 37*4, | |
89 | 38*4, 39*4, 40*4, -1 | |
1b3f6016 | 90 | |
45b134e5 OF |
91 | }; |
92 | ||
45b134e5 OF |
93 | static const unsigned short cris_breakpoint = 0xe938; |
94 | #define cris_breakpoint_len 2 | |
95 | ||
dd373349 AT |
96 | /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */ |
97 | ||
98 | static const gdb_byte * | |
99 | cris_sw_breakpoint_from_kind (int kind, int *size) | |
100 | { | |
101 | *size = cris_breakpoint_len; | |
102 | return (const gdb_byte *) &cris_breakpoint; | |
103 | } | |
104 | ||
45b134e5 OF |
105 | static int |
106 | cris_breakpoint_at (CORE_ADDR where) | |
107 | { | |
108 | unsigned short insn; | |
109 | ||
52405d85 TBA |
110 | the_target->read_memory (where, (unsigned char *) &insn, |
111 | cris_breakpoint_len); | |
45b134e5 OF |
112 | if (insn == cris_breakpoint) |
113 | return 1; | |
114 | ||
115 | /* If necessary, recognize more trap instructions here. GDB only uses the | |
116 | one. */ | |
117 | return 0; | |
118 | } | |
119 | ||
45b134e5 | 120 | static void |
442ea881 PA |
121 | cris_write_data_breakpoint (struct regcache *regcache, |
122 | int bp, unsigned long start, unsigned long end) | |
45b134e5 OF |
123 | { |
124 | switch (bp) | |
125 | { | |
126 | case 0: | |
442ea881 PA |
127 | supply_register_by_name (regcache, "s3", &start); |
128 | supply_register_by_name (regcache, "s4", &end); | |
45b134e5 OF |
129 | break; |
130 | case 1: | |
442ea881 PA |
131 | supply_register_by_name (regcache, "s5", &start); |
132 | supply_register_by_name (regcache, "s6", &end); | |
45b134e5 OF |
133 | break; |
134 | case 2: | |
442ea881 PA |
135 | supply_register_by_name (regcache, "s7", &start); |
136 | supply_register_by_name (regcache, "s8", &end); | |
45b134e5 OF |
137 | break; |
138 | case 3: | |
442ea881 PA |
139 | supply_register_by_name (regcache, "s9", &start); |
140 | supply_register_by_name (regcache, "s10", &end); | |
45b134e5 OF |
141 | break; |
142 | case 4: | |
442ea881 PA |
143 | supply_register_by_name (regcache, "s11", &start); |
144 | supply_register_by_name (regcache, "s12", &end); | |
45b134e5 OF |
145 | break; |
146 | case 5: | |
442ea881 PA |
147 | supply_register_by_name (regcache, "s13", &start); |
148 | supply_register_by_name (regcache, "s14", &end); | |
45b134e5 OF |
149 | break; |
150 | } | |
151 | } | |
152 | ||
153 | static int | |
802e8e6d PA |
154 | cris_supports_z_point_type (char z_type) |
155 | { | |
156 | switch (z_type) | |
157 | { | |
158 | case Z_PACKET_WRITE_WP: | |
159 | case Z_PACKET_READ_WP: | |
160 | case Z_PACKET_ACCESS_WP: | |
161 | return 1; | |
162 | default: | |
163 | return 0; | |
164 | } | |
165 | } | |
166 | ||
167 | static int | |
168 | cris_insert_point (enum raw_bkpt_type type, CORE_ADDR addr, | |
169 | int len, struct raw_breakpoint *bp) | |
45b134e5 OF |
170 | { |
171 | int bp; | |
172 | unsigned long bp_ctrl; | |
173 | unsigned long start, end; | |
174 | unsigned long ccs; | |
442ea881 | 175 | struct regcache *regcache; |
1b3f6016 | 176 | |
0bfdf32f | 177 | regcache = get_thread_regcache (current_thread, 1); |
442ea881 | 178 | |
45b134e5 OF |
179 | /* Read watchpoints are set as access watchpoints, because of GDB's |
180 | inability to deal with pure read watchpoints. */ | |
802e8e6d PA |
181 | if (type == raw_bkpt_type_read_wp) |
182 | type = raw_bkpt_type_access_wp; | |
45b134e5 OF |
183 | |
184 | /* Get the configuration register. */ | |
442ea881 | 185 | collect_register_by_name (regcache, "s0", &bp_ctrl); |
45b134e5 OF |
186 | |
187 | /* The watchpoint allocation scheme is the simplest possible. | |
188 | For example, if a region is watched for read and | |
189 | a write watch is requested, a new watchpoint will | |
190 | be used. Also, if a watch for a region that is already | |
191 | covered by one or more existing watchpoints, a new | |
192 | watchpoint will be used. */ | |
1b3f6016 | 193 | |
45b134e5 OF |
194 | /* First, find a free data watchpoint. */ |
195 | for (bp = 0; bp < 6; bp++) | |
196 | { | |
197 | /* Each data watchpoint's control registers occupy 2 bits | |
198 | (hence the 3), starting at bit 2 for D0 (hence the 2) | |
199 | with 4 bits between for each watchpoint (yes, the 4). */ | |
1b3f6016 | 200 | if (!(bp_ctrl & (0x3 << (2 + (bp * 4))))) |
45b134e5 OF |
201 | break; |
202 | } | |
1b3f6016 | 203 | |
45b134e5 OF |
204 | if (bp > 5) |
205 | { | |
206 | /* We're out of watchpoints. */ | |
207 | return -1; | |
208 | } | |
209 | ||
210 | /* Configure the control register first. */ | |
802e8e6d | 211 | if (type == raw_bkpt_type_read_wp || type == raw_bkpt_type_access_wp) |
45b134e5 OF |
212 | { |
213 | /* Trigger on read. */ | |
214 | bp_ctrl |= (1 << (2 + bp * 4)); | |
215 | } | |
802e8e6d | 216 | if (type == raw_bkpt_type_write_wp || type == raw_bkpt_type_access_wp) |
45b134e5 OF |
217 | { |
218 | /* Trigger on write. */ | |
219 | bp_ctrl |= (2 << (2 + bp * 4)); | |
220 | } | |
1b3f6016 | 221 | |
45b134e5 | 222 | /* Setup the configuration register. */ |
442ea881 | 223 | supply_register_by_name (regcache, "s0", &bp_ctrl); |
1b3f6016 | 224 | |
45b134e5 OF |
225 | /* Setup the range. */ |
226 | start = addr; | |
227 | end = addr + len - 1; | |
228 | ||
229 | /* Configure the watchpoint register. */ | |
442ea881 | 230 | cris_write_data_breakpoint (regcache, bp, start, end); |
45b134e5 | 231 | |
442ea881 | 232 | collect_register_by_name (regcache, "ccs", &ccs); |
45b134e5 OF |
233 | /* Set the S1 flag to enable watchpoints. */ |
234 | ccs |= (1 << 19); | |
442ea881 | 235 | supply_register_by_name (regcache, "ccs", &ccs); |
45b134e5 OF |
236 | |
237 | return 0; | |
238 | } | |
239 | ||
240 | static int | |
802e8e6d PA |
241 | cris_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, int len, |
242 | struct raw_breakpoint *bp) | |
45b134e5 OF |
243 | { |
244 | int bp; | |
245 | unsigned long bp_ctrl; | |
246 | unsigned long start, end; | |
442ea881 | 247 | struct regcache *regcache; |
07c04788 | 248 | unsigned long bp_d_regs[12]; |
1b3f6016 | 249 | |
0bfdf32f | 250 | regcache = get_thread_regcache (current_thread, 1); |
442ea881 | 251 | |
45b134e5 OF |
252 | /* Read watchpoints are set as access watchpoints, because of GDB's |
253 | inability to deal with pure read watchpoints. */ | |
802e8e6d PA |
254 | if (type == raw_bkpt_type_read_wp) |
255 | type = raw_bkpt_type_access_wp; | |
1b3f6016 | 256 | |
45b134e5 | 257 | /* Get the configuration register. */ |
442ea881 | 258 | collect_register_by_name (regcache, "s0", &bp_ctrl); |
45b134e5 OF |
259 | |
260 | /* Try to find a watchpoint that is configured for the | |
261 | specified range, then check that read/write also matches. */ | |
1b3f6016 | 262 | |
45b134e5 OF |
263 | /* Ugly pointer arithmetic, since I cannot rely on a |
264 | single switch (addr) as there may be several watchpoints with | |
265 | the same start address for example. */ | |
266 | ||
45b134e5 | 267 | /* Get all range registers to simplify search. */ |
442ea881 PA |
268 | collect_register_by_name (regcache, "s3", &bp_d_regs[0]); |
269 | collect_register_by_name (regcache, "s4", &bp_d_regs[1]); | |
270 | collect_register_by_name (regcache, "s5", &bp_d_regs[2]); | |
271 | collect_register_by_name (regcache, "s6", &bp_d_regs[3]); | |
272 | collect_register_by_name (regcache, "s7", &bp_d_regs[4]); | |
273 | collect_register_by_name (regcache, "s8", &bp_d_regs[5]); | |
274 | collect_register_by_name (regcache, "s9", &bp_d_regs[6]); | |
275 | collect_register_by_name (regcache, "s10", &bp_d_regs[7]); | |
276 | collect_register_by_name (regcache, "s11", &bp_d_regs[8]); | |
277 | collect_register_by_name (regcache, "s12", &bp_d_regs[9]); | |
278 | collect_register_by_name (regcache, "s13", &bp_d_regs[10]); | |
279 | collect_register_by_name (regcache, "s14", &bp_d_regs[11]); | |
45b134e5 | 280 | |
1b3f6016 | 281 | for (bp = 0; bp < 6; bp++) |
45b134e5 | 282 | { |
1b3f6016 | 283 | if (bp_d_regs[bp * 2] == addr |
45b134e5 OF |
284 | && bp_d_regs[bp * 2 + 1] == (addr + len - 1)) { |
285 | /* Matching range. */ | |
286 | int bitpos = 2 + bp * 4; | |
287 | int rw_bits; | |
1b3f6016 | 288 | |
45b134e5 OF |
289 | /* Read/write bits for this BP. */ |
290 | rw_bits = (bp_ctrl & (0x3 << bitpos)) >> bitpos; | |
1b3f6016 | 291 | |
802e8e6d PA |
292 | if ((type == raw_bkpt_type_read_wp && rw_bits == 0x1) |
293 | || (type == raw_bkpt_type_write_wp && rw_bits == 0x2) | |
294 | || (type == raw_bkpt_type_access_wp && rw_bits == 0x3)) | |
45b134e5 OF |
295 | { |
296 | /* Read/write matched. */ | |
297 | break; | |
298 | } | |
299 | } | |
300 | } | |
1b3f6016 | 301 | |
45b134e5 OF |
302 | if (bp > 5) |
303 | { | |
304 | /* No watchpoint matched. */ | |
305 | return -1; | |
306 | } | |
1b3f6016 | 307 | |
45b134e5 OF |
308 | /* Found a matching watchpoint. Now, deconfigure it by |
309 | both disabling read/write in bp_ctrl and zeroing its | |
310 | start/end addresses. */ | |
311 | bp_ctrl &= ~(3 << (2 + (bp * 4))); | |
312 | /* Setup the configuration register. */ | |
442ea881 | 313 | supply_register_by_name (regcache, "s0", &bp_ctrl); |
45b134e5 OF |
314 | |
315 | start = end = 0; | |
316 | /* Configure the watchpoint register. */ | |
442ea881 | 317 | cris_write_data_breakpoint (regcache, bp, start, end); |
45b134e5 OF |
318 | |
319 | /* Note that we don't clear the S1 flag here. It's done when continuing. */ | |
320 | return 0; | |
321 | } | |
322 | ||
323 | static int | |
324 | cris_stopped_by_watchpoint (void) | |
325 | { | |
326 | unsigned long exs; | |
0bfdf32f | 327 | struct regcache *regcache = get_thread_regcache (current_thread, 1); |
45b134e5 | 328 | |
07c04788 | 329 | collect_register_by_name (regcache, "exs", &exs); |
45b134e5 OF |
330 | |
331 | return (((exs & 0xff00) >> 8) == 0xc); | |
332 | } | |
333 | ||
334 | static CORE_ADDR | |
335 | cris_stopped_data_address (void) | |
336 | { | |
337 | unsigned long eda; | |
0bfdf32f | 338 | struct regcache *regcache = get_thread_regcache (current_thread, 1); |
45b134e5 | 339 | |
07c04788 | 340 | collect_register_by_name (regcache, "eda", &eda); |
45b134e5 OF |
341 | |
342 | /* FIXME: Possibly adjust to match watched range. */ | |
343 | return eda; | |
344 | } | |
345 | ||
8eb3d7b6 | 346 | ps_err_e |
754653a7 | 347 | ps_get_thread_area (struct ps_prochandle *ph, |
8eb3d7b6 RW |
348 | lwpid_t lwpid, int idx, void **base) |
349 | { | |
350 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
351 | return PS_ERR; | |
352 | ||
353 | /* IDX is the bias from the thread pointer to the beginning of the | |
354 | thread descriptor. It has to be subtracted due to implementation | |
355 | quirks in libthread_db. */ | |
356 | *base = (void *) ((char *) *base - idx); | |
357 | return PS_OK; | |
358 | } | |
359 | ||
45b134e5 | 360 | static void |
07c04788 | 361 | cris_fill_gregset (struct regcache *regcache, void *buf) |
45b134e5 OF |
362 | { |
363 | int i; | |
364 | ||
365 | for (i = 0; i < cris_num_regs; i++) | |
366 | { | |
367 | if (cris_regmap[i] != -1) | |
07c04788 | 368 | collect_register (regcache, i, ((char *) buf) + cris_regmap[i]); |
45b134e5 OF |
369 | } |
370 | } | |
371 | ||
372 | static void | |
07c04788 | 373 | cris_store_gregset (struct regcache *regcache, const void *buf) |
45b134e5 OF |
374 | { |
375 | int i; | |
376 | ||
377 | for (i = 0; i < cris_num_regs; i++) | |
378 | { | |
379 | if (cris_regmap[i] != -1) | |
07c04788 | 380 | supply_register (regcache, i, ((char *) buf) + cris_regmap[i]); |
45b134e5 OF |
381 | } |
382 | } | |
383 | ||
797bcff5 TBA |
384 | void |
385 | crisv32_target::low_arch_setup () | |
3aee8918 PA |
386 | { |
387 | current_process ()->tdesc = tdesc_crisv32; | |
388 | } | |
389 | ||
7d00775e AT |
390 | /* Support for hardware single step. */ |
391 | ||
392 | static int | |
393 | cris_supports_hardware_single_step (void) | |
394 | { | |
395 | return 1; | |
396 | } | |
397 | ||
3aee8918 | 398 | static struct regset_info cris_regsets[] = { |
07c04788 | 399 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, cris_num_regs * 4, |
45b134e5 | 400 | GENERAL_REGS, cris_fill_gregset, cris_store_gregset }, |
50bc912a | 401 | NULL_REGSET |
45b134e5 OF |
402 | }; |
403 | ||
3aee8918 PA |
404 | |
405 | static struct regsets_info cris_regsets_info = | |
406 | { | |
407 | cris_regsets, /* regsets */ | |
408 | 0, /* num_regsets */ | |
409 | NULL, /* disabled_regsets */ | |
410 | }; | |
411 | ||
412 | static struct usrregs_info cris_usrregs_info = | |
413 | { | |
414 | cris_num_regs, | |
415 | cris_regmap, | |
416 | }; | |
417 | ||
aa8d21c9 | 418 | static struct regs_info myregs_info = |
3aee8918 PA |
419 | { |
420 | NULL, /* regset_bitmap */ | |
421 | &cris_usrregs_info, | |
422 | &cris_regsets_info | |
423 | }; | |
424 | ||
aa8d21c9 TBA |
425 | const regs_info * |
426 | crisv32_target::get_regs_info () | |
3aee8918 | 427 | { |
aa8d21c9 | 428 | return &myregs_info; |
3aee8918 PA |
429 | } |
430 | ||
45b134e5 | 431 | struct linux_target_ops the_low_target = { |
276d4552 YQ |
432 | linux_get_pc_32bit, |
433 | linux_set_pc_32bit, | |
dd373349 AT |
434 | NULL, /* breakpoint_kind_from_pc */ |
435 | cris_sw_breakpoint_from_kind, | |
fa5308bd | 436 | NULL, /* get_next_pcs */ |
45b134e5 OF |
437 | 0, |
438 | cris_breakpoint_at, | |
802e8e6d | 439 | cris_supports_z_point_type, |
d993e290 PA |
440 | cris_insert_point, |
441 | cris_remove_point, | |
45b134e5 OF |
442 | cris_stopped_by_watchpoint, |
443 | cris_stopped_data_address, | |
7d00775e AT |
444 | NULL, /* collect_ptrace_register */ |
445 | NULL, /* supply_ptrace_register */ | |
446 | NULL, /* siginfo_fixup */ | |
447 | NULL, /* new_process */ | |
04ec7890 | 448 | NULL, /* delete_process */ |
7d00775e | 449 | NULL, /* new_thread */ |
466eecee | 450 | NULL, /* delete_thread */ |
7d00775e AT |
451 | NULL, /* new_fork */ |
452 | NULL, /* prepare_to_resume */ | |
453 | NULL, /* process_qsupported */ | |
454 | NULL, /* supports_tracepoints */ | |
455 | NULL, /* get_thread_area */ | |
456 | NULL, /* install_fast_tracepoint_jump_pad */ | |
457 | NULL, /* emit_ops */ | |
458 | NULL, /* get_min_fast_tracepoint_insn_len */ | |
459 | NULL, /* supports_range_stepping */ | |
460 | NULL, /* breakpoint_kind_from_current_state */ | |
461 | cris_supports_hardware_single_step, | |
45b134e5 | 462 | }; |
3aee8918 | 463 | |
ef0478f6 TBA |
464 | /* The linux target ops object. */ |
465 | ||
466 | linux_process_target *the_linux_target = &the_crisv32_target; | |
467 | ||
3aee8918 PA |
468 | void |
469 | initialize_low_arch (void) | |
470 | { | |
eddddb9d | 471 | init_registers_crisv32 (); |
3aee8918 PA |
472 | |
473 | initialize_regsets_info (&cris_regsets_info); | |
474 | } |