Commit | Line | Data |
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7cfbc4a0 | 1 | /* GNU/Linux/m32r specific low level interface, for the remote server for GDB. |
b811d2c2 | 2 | Copyright (C) 2005-2020 Free Software Foundation, Inc. |
7cfbc4a0 KI |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
7cfbc4a0 KI |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
7cfbc4a0 KI |
18 | |
19 | #include "server.h" | |
20 | #include "linux-low.h" | |
21 | ||
22 | #ifdef HAVE_SYS_REG_H | |
23 | #include <sys/reg.h> | |
24 | #endif | |
25 | ||
ef0478f6 TBA |
26 | /* Linux target op definitions for the m32r architecture. */ |
27 | ||
28 | class m32r_target : public linux_process_target | |
29 | { | |
30 | public: | |
31 | ||
32 | }; | |
33 | ||
34 | /* The singleton target ops object. */ | |
35 | ||
36 | static m32r_target the_m32r_target; | |
37 | ||
d05b4ac3 UW |
38 | /* Defined in auto-generated file reg-m32r.c. */ |
39 | void init_registers_m32r (void); | |
3aee8918 | 40 | extern const struct target_desc *tdesc_m32r; |
d05b4ac3 | 41 | |
7cfbc4a0 KI |
42 | #define m32r_num_regs 25 |
43 | ||
44 | static int m32r_regmap[] = { | |
45 | #ifdef PT_R0 | |
46 | PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7, | |
47 | PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_FP, PT_LR, PT_SPU, | |
48 | PT_PSW, PT_CBR, PT_SPI, PT_SPU, PT_BPC, PT_PC, PT_ACCL, PT_ACCH, PT_EVB | |
49 | #else | |
50 | 4 * 4, 4 * 5, 4 * 6, 4 * 7, 4 * 0, 4 * 1, 4 * 2, 4 * 8, | |
51 | 4 * 9, 4 * 10, 4 * 11, 4 * 12, 4 * 13, 4 * 24, 4 * 25, 4 * 23, | |
52 | 4 * 19, 4 * 31, 4 * 26, 4 * 23, 4 * 20, 4 * 30, 4 * 16, 4 * 15, 4 * 32 | |
53 | #endif | |
54 | }; | |
55 | ||
56 | static int | |
57 | m32r_cannot_store_register (int regno) | |
58 | { | |
59 | return (regno >= m32r_num_regs); | |
60 | } | |
61 | ||
62 | static int | |
63 | m32r_cannot_fetch_register (int regno) | |
64 | { | |
65 | return (regno >= m32r_num_regs); | |
66 | } | |
67 | ||
7cfbc4a0 KI |
68 | static const unsigned short m32r_breakpoint = 0x10f1; |
69 | #define m32r_breakpoint_len 2 | |
70 | ||
dd373349 AT |
71 | /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */ |
72 | ||
73 | static const gdb_byte * | |
74 | m32r_sw_breakpoint_from_kind (int kind, int *size) | |
75 | { | |
76 | *size = m32r_breakpoint_len; | |
77 | return (const gdb_byte *) &m32r_breakpoint; | |
78 | } | |
79 | ||
7cfbc4a0 KI |
80 | static int |
81 | m32r_breakpoint_at (CORE_ADDR where) | |
82 | { | |
83 | unsigned short insn; | |
84 | ||
52405d85 TBA |
85 | the_target->read_memory (where, (unsigned char *) &insn, |
86 | m32r_breakpoint_len); | |
7cfbc4a0 KI |
87 | if (insn == m32r_breakpoint) |
88 | return 1; | |
89 | ||
90 | /* If necessary, recognize more trap instructions here. GDB only uses the | |
91 | one. */ | |
92 | return 0; | |
93 | } | |
94 | ||
3aee8918 PA |
95 | static void |
96 | m32r_arch_setup (void) | |
97 | { | |
98 | current_process ()->tdesc = tdesc_m32r; | |
99 | } | |
100 | ||
7d00775e AT |
101 | /* Support for hardware single step. */ |
102 | ||
103 | static int | |
104 | m32r_supports_hardware_single_step (void) | |
105 | { | |
106 | return 1; | |
107 | } | |
108 | ||
3aee8918 PA |
109 | static struct usrregs_info m32r_usrregs_info = |
110 | { | |
111 | m32r_num_regs, | |
112 | m32r_regmap, | |
113 | }; | |
114 | ||
115 | static struct regs_info regs_info = | |
116 | { | |
117 | NULL, /* regset_bitmap */ | |
118 | &m32r_usrregs_info, | |
119 | }; | |
120 | ||
121 | static const struct regs_info * | |
122 | m32r_regs_info (void) | |
123 | { | |
124 | return ®s_info; | |
125 | } | |
126 | ||
7cfbc4a0 | 127 | struct linux_target_ops the_low_target = { |
3aee8918 PA |
128 | m32r_arch_setup, |
129 | m32r_regs_info, | |
7cfbc4a0 KI |
130 | m32r_cannot_fetch_register, |
131 | m32r_cannot_store_register, | |
c14dfd32 | 132 | NULL, /* fetch_register */ |
276d4552 YQ |
133 | linux_get_pc_32bit, |
134 | linux_set_pc_32bit, | |
dd373349 AT |
135 | NULL, /* breakpoint_from_pc */ |
136 | m32r_sw_breakpoint_from_kind, | |
7cfbc4a0 KI |
137 | NULL, |
138 | 0, | |
139 | m32r_breakpoint_at, | |
7d00775e AT |
140 | NULL, /* supports_z_point_type */ |
141 | NULL, /* insert_point */ | |
142 | NULL, /* remove_point */ | |
143 | NULL, /* stopped_by_watchpoint */ | |
144 | NULL, /* stopped_data_address */ | |
145 | NULL, /* collect_ptrace_register */ | |
146 | NULL, /* supply_ptrace_register */ | |
147 | NULL, /* siginfo_fixup */ | |
148 | NULL, /* new_process */ | |
04ec7890 | 149 | NULL, /* delete_process */ |
7d00775e | 150 | NULL, /* new_thread */ |
466eecee | 151 | NULL, /* delete_thread */ |
7d00775e AT |
152 | NULL, /* new_fork */ |
153 | NULL, /* prepare_to_resume */ | |
154 | NULL, /* process_qsupported */ | |
155 | NULL, /* supports_tracepoints */ | |
156 | NULL, /* get_thread_area */ | |
157 | NULL, /* install_fast_tracepoint_jump_pad */ | |
158 | NULL, /* emit_ops */ | |
159 | NULL, /* get_min_fast_tracepoint_insn_len */ | |
160 | NULL, /* supports_range_stepping */ | |
161 | NULL, /* breakpoint_kind_from_current_state */ | |
162 | m32r_supports_hardware_single_step, | |
7cfbc4a0 | 163 | }; |
3aee8918 | 164 | |
ef0478f6 TBA |
165 | /* The linux target ops object. */ |
166 | ||
167 | linux_process_target *the_linux_target = &the_m32r_target; | |
168 | ||
3aee8918 PA |
169 | void |
170 | initialize_low_arch (void) | |
171 | { | |
172 | init_registers_m32r (); | |
173 | } |