Commit | Line | Data |
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0a30fbc4 | 1 | /* GNU/Linux/MIPS specific low level interface, for the remote server for GDB. |
b811d2c2 | 2 | Copyright (C) 1995-2020 Free Software Foundation, Inc. |
0a30fbc4 DJ |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
0a30fbc4 DJ |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
0a30fbc4 DJ |
18 | |
19 | #include "server.h" | |
58caa3dc | 20 | #include "linux-low.h" |
0a30fbc4 | 21 | |
5826e159 | 22 | #include "nat/gdb_ptrace.h" |
186947f7 | 23 | #include <endian.h> |
21b0f40c | 24 | |
125f8a3d | 25 | #include "nat/mips-linux-watch.h" |
21b0f40c DJ |
26 | #include "gdb_proc_service.h" |
27 | ||
ef0478f6 TBA |
28 | /* Linux target op definitions for the MIPS architecture. */ |
29 | ||
30 | class mips_target : public linux_process_target | |
31 | { | |
32 | public: | |
33 | ||
aa8d21c9 TBA |
34 | const regs_info *get_regs_info () override; |
35 | ||
3ca4edb6 TBA |
36 | const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override; |
37 | ||
007c9b97 TBA |
38 | bool supports_z_point_type (char z_type) override; |
39 | ||
797bcff5 TBA |
40 | protected: |
41 | ||
42 | void low_arch_setup () override; | |
daca57a7 TBA |
43 | |
44 | bool low_cannot_fetch_register (int regno) override; | |
45 | ||
46 | bool low_cannot_store_register (int regno) override; | |
bd70b1f2 TBA |
47 | |
48 | bool low_fetch_register (regcache *regcache, int regno) override; | |
bf9ae9d8 TBA |
49 | |
50 | bool low_supports_breakpoints () override; | |
51 | ||
52 | CORE_ADDR low_get_pc (regcache *regcache) override; | |
53 | ||
54 | void low_set_pc (regcache *regcache, CORE_ADDR newpc) override; | |
d7146cda TBA |
55 | |
56 | bool low_breakpoint_at (CORE_ADDR pc) override; | |
9db9aa23 TBA |
57 | |
58 | int low_insert_point (raw_bkpt_type type, CORE_ADDR addr, | |
59 | int size, raw_breakpoint *bp) override; | |
60 | ||
61 | int low_remove_point (raw_bkpt_type type, CORE_ADDR addr, | |
62 | int size, raw_breakpoint *bp) override; | |
ac1bbaca TBA |
63 | |
64 | bool low_stopped_by_watchpoint () override; | |
65 | ||
66 | CORE_ADDR low_stopped_data_address () override; | |
b35db733 TBA |
67 | |
68 | void low_collect_ptrace_register (regcache *regcache, int regno, | |
69 | char *buf) override; | |
70 | ||
71 | void low_supply_ptrace_register (regcache *regcache, int regno, | |
72 | const char *buf) override; | |
fd000fb3 TBA |
73 | |
74 | arch_process_info *low_new_process () override; | |
75 | ||
76 | void low_delete_process (arch_process_info *info) override; | |
77 | ||
78 | void low_new_thread (lwp_info *) override; | |
79 | ||
80 | void low_delete_thread (arch_lwp_info *) override; | |
81 | ||
82 | void low_new_fork (process_info *parent, process_info *child) override; | |
d7599cc0 TBA |
83 | |
84 | void low_prepare_to_resume (lwp_info *lwp) override; | |
ef0478f6 TBA |
85 | }; |
86 | ||
87 | /* The singleton target ops object. */ | |
88 | ||
89 | static mips_target the_mips_target; | |
90 | ||
d05b4ac3 UW |
91 | /* Defined in auto-generated file mips-linux.c. */ |
92 | void init_registers_mips_linux (void); | |
3aee8918 PA |
93 | extern const struct target_desc *tdesc_mips_linux; |
94 | ||
1faeff08 MR |
95 | /* Defined in auto-generated file mips-dsp-linux.c. */ |
96 | void init_registers_mips_dsp_linux (void); | |
3aee8918 PA |
97 | extern const struct target_desc *tdesc_mips_dsp_linux; |
98 | ||
d05b4ac3 UW |
99 | /* Defined in auto-generated file mips64-linux.c. */ |
100 | void init_registers_mips64_linux (void); | |
3aee8918 PA |
101 | extern const struct target_desc *tdesc_mips64_linux; |
102 | ||
1faeff08 MR |
103 | /* Defined in auto-generated file mips64-dsp-linux.c. */ |
104 | void init_registers_mips64_dsp_linux (void); | |
3aee8918 | 105 | extern const struct target_desc *tdesc_mips64_dsp_linux; |
1faeff08 MR |
106 | |
107 | #ifdef __mips64 | |
3aee8918 PA |
108 | #define tdesc_mips_linux tdesc_mips64_linux |
109 | #define tdesc_mips_dsp_linux tdesc_mips64_dsp_linux | |
1faeff08 | 110 | #endif |
d05b4ac3 | 111 | |
21b0f40c DJ |
112 | #ifndef PTRACE_GET_THREAD_AREA |
113 | #define PTRACE_GET_THREAD_AREA 25 | |
114 | #endif | |
115 | ||
0a30fbc4 DJ |
116 | #ifdef HAVE_SYS_REG_H |
117 | #include <sys/reg.h> | |
118 | #endif | |
119 | ||
117ce543 | 120 | #define mips_num_regs 73 |
1faeff08 | 121 | #define mips_dsp_num_regs 80 |
0a30fbc4 DJ |
122 | |
123 | #include <asm/ptrace.h> | |
124 | ||
1faeff08 MR |
125 | #ifndef DSP_BASE |
126 | #define DSP_BASE 71 | |
127 | #define DSP_CONTROL 77 | |
128 | #endif | |
129 | ||
186947f7 DJ |
130 | union mips_register |
131 | { | |
132 | unsigned char buf[8]; | |
133 | ||
134 | /* Deliberately signed, for proper sign extension. */ | |
135 | int reg32; | |
136 | long long reg64; | |
137 | }; | |
138 | ||
0a30fbc4 DJ |
139 | /* Return the ptrace ``address'' of register REGNO. */ |
140 | ||
1faeff08 MR |
141 | #define mips_base_regs \ |
142 | -1, 1, 2, 3, 4, 5, 6, 7, \ | |
143 | 8, 9, 10, 11, 12, 13, 14, 15, \ | |
144 | 16, 17, 18, 19, 20, 21, 22, 23, \ | |
145 | 24, 25, 26, 27, 28, 29, 30, 31, \ | |
146 | \ | |
147 | -1, MMLO, MMHI, BADVADDR, CAUSE, PC, \ | |
148 | \ | |
149 | FPR_BASE, FPR_BASE + 1, FPR_BASE + 2, FPR_BASE + 3, \ | |
150 | FPR_BASE + 4, FPR_BASE + 5, FPR_BASE + 6, FPR_BASE + 7, \ | |
151 | FPR_BASE + 8, FPR_BASE + 9, FPR_BASE + 10, FPR_BASE + 11, \ | |
152 | FPR_BASE + 12, FPR_BASE + 13, FPR_BASE + 14, FPR_BASE + 15, \ | |
153 | FPR_BASE + 16, FPR_BASE + 17, FPR_BASE + 18, FPR_BASE + 19, \ | |
154 | FPR_BASE + 20, FPR_BASE + 21, FPR_BASE + 22, FPR_BASE + 23, \ | |
155 | FPR_BASE + 24, FPR_BASE + 25, FPR_BASE + 26, FPR_BASE + 27, \ | |
156 | FPR_BASE + 28, FPR_BASE + 29, FPR_BASE + 30, FPR_BASE + 31, \ | |
157 | FPC_CSR, FPC_EIR | |
158 | ||
159 | #define mips_dsp_regs \ | |
160 | DSP_BASE, DSP_BASE + 1, DSP_BASE + 2, DSP_BASE + 3, \ | |
161 | DSP_BASE + 4, DSP_BASE + 5, \ | |
162 | DSP_CONTROL | |
163 | ||
164 | static int mips_regmap[mips_num_regs] = { | |
165 | mips_base_regs, | |
166 | 0 | |
167 | }; | |
0a30fbc4 | 168 | |
1faeff08 MR |
169 | static int mips_dsp_regmap[mips_dsp_num_regs] = { |
170 | mips_base_regs, | |
171 | mips_dsp_regs, | |
172 | 0 | |
173 | }; | |
0a30fbc4 | 174 | |
1faeff08 MR |
175 | /* DSP registers are not in any regset and can only be accessed |
176 | individually. */ | |
0a30fbc4 | 177 | |
1faeff08 MR |
178 | static unsigned char mips_dsp_regset_bitmap[(mips_dsp_num_regs + 7) / 8] = { |
179 | 0xfe, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0x80 | |
0a30fbc4 DJ |
180 | }; |
181 | ||
3aee8918 PA |
182 | static int have_dsp = -1; |
183 | ||
1faeff08 MR |
184 | /* Try peeking at an arbitrarily chosen DSP register and pick the available |
185 | user register set accordingly. */ | |
186 | ||
3aee8918 PA |
187 | static const struct target_desc * |
188 | mips_read_description (void) | |
1faeff08 | 189 | { |
3aee8918 | 190 | if (have_dsp < 0) |
1faeff08 | 191 | { |
0bfdf32f | 192 | int pid = lwpid_of (current_thread); |
1faeff08 | 193 | |
ac740bc7 | 194 | errno = 0; |
1faeff08 MR |
195 | ptrace (PTRACE_PEEKUSER, pid, DSP_CONTROL, 0); |
196 | switch (errno) | |
197 | { | |
198 | case 0: | |
3aee8918 | 199 | have_dsp = 1; |
1faeff08 MR |
200 | break; |
201 | case EIO: | |
3aee8918 | 202 | have_dsp = 0; |
1faeff08 MR |
203 | break; |
204 | default: | |
205 | perror_with_name ("ptrace"); | |
206 | break; | |
207 | } | |
208 | } | |
3aee8918 PA |
209 | |
210 | return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux; | |
211 | } | |
212 | ||
797bcff5 TBA |
213 | void |
214 | mips_target::low_arch_setup () | |
3aee8918 PA |
215 | { |
216 | current_process ()->tdesc = mips_read_description (); | |
217 | } | |
218 | ||
7a60ad40 YQ |
219 | /* Per-process arch-specific data we want to keep. */ |
220 | ||
221 | struct arch_process_info | |
222 | { | |
223 | /* -1 if the kernel and/or CPU do not support watch registers. | |
224 | 1 if watch_readback is valid and we can read style, num_valid | |
225 | and the masks. | |
226 | 0 if we need to read the watch_readback. */ | |
227 | ||
228 | int watch_readback_valid; | |
229 | ||
230 | /* Cached watch register read values. */ | |
231 | ||
232 | struct pt_watch_regs watch_readback; | |
233 | ||
234 | /* Current watchpoint requests for this process. */ | |
235 | ||
236 | struct mips_watchpoint *current_watches; | |
237 | ||
238 | /* The current set of watch register values for writing the | |
239 | registers. */ | |
240 | ||
241 | struct pt_watch_regs watch_mirror; | |
242 | }; | |
243 | ||
244 | /* Per-thread arch-specific data we want to keep. */ | |
245 | ||
246 | struct arch_lwp_info | |
247 | { | |
248 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
249 | int watch_registers_changed; | |
250 | }; | |
251 | ||
0a30fbc4 DJ |
252 | /* From mips-linux-nat.c. */ |
253 | ||
254 | /* Pseudo registers can not be read. ptrace does not provide a way to | |
255 | read (or set) PS_REGNUM, and there's no point in reading or setting | |
e4439e43 MR |
256 | ZERO_REGNUM, it's always 0. We also can not set BADVADDR, CAUSE, |
257 | or FCRIR via ptrace(). */ | |
0a30fbc4 | 258 | |
daca57a7 TBA |
259 | bool |
260 | mips_target::low_cannot_fetch_register (int regno) | |
0a30fbc4 | 261 | { |
3aee8918 PA |
262 | const struct target_desc *tdesc; |
263 | ||
daca57a7 TBA |
264 | if (get_regs_info ()->usrregs->regmap[regno] == -1) |
265 | return true; | |
0a30fbc4 | 266 | |
3aee8918 PA |
267 | tdesc = current_process ()->tdesc; |
268 | ||
75d74cca MR |
269 | /* On n32 we can't access 64-bit registers via PTRACE_PEEKUSR. */ |
270 | if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE)) | |
daca57a7 | 271 | return true; |
75d74cca | 272 | |
3aee8918 | 273 | if (find_regno (tdesc, "r0") == regno) |
daca57a7 | 274 | return true; |
0a30fbc4 | 275 | |
daca57a7 | 276 | return false; |
0a30fbc4 DJ |
277 | } |
278 | ||
daca57a7 TBA |
279 | bool |
280 | mips_target::low_cannot_store_register (int regno) | |
0a30fbc4 | 281 | { |
3aee8918 PA |
282 | const struct target_desc *tdesc; |
283 | ||
daca57a7 TBA |
284 | if (get_regs_info ()->usrregs->regmap[regno] == -1) |
285 | return true; | |
0a30fbc4 | 286 | |
3aee8918 PA |
287 | tdesc = current_process ()->tdesc; |
288 | ||
75d74cca MR |
289 | /* On n32 we can't access 64-bit registers via PTRACE_POKEUSR. */ |
290 | if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE)) | |
daca57a7 | 291 | return true; |
75d74cca | 292 | |
3aee8918 | 293 | if (find_regno (tdesc, "r0") == regno) |
daca57a7 | 294 | return true; |
0a30fbc4 | 295 | |
3aee8918 | 296 | if (find_regno (tdesc, "cause") == regno) |
daca57a7 | 297 | return true; |
0a30fbc4 | 298 | |
3aee8918 | 299 | if (find_regno (tdesc, "badvaddr") == regno) |
daca57a7 | 300 | return true; |
0a30fbc4 | 301 | |
3aee8918 | 302 | if (find_regno (tdesc, "fir") == regno) |
daca57a7 | 303 | return true; |
0a30fbc4 | 304 | |
daca57a7 | 305 | return false; |
0a30fbc4 | 306 | } |
2ec06d2e | 307 | |
bd70b1f2 TBA |
308 | bool |
309 | mips_target::low_fetch_register (regcache *regcache, int regno) | |
e4439e43 MR |
310 | { |
311 | const struct target_desc *tdesc = current_process ()->tdesc; | |
312 | ||
313 | if (find_regno (tdesc, "r0") == regno) | |
314 | { | |
315 | supply_register_zeroed (regcache, regno); | |
bd70b1f2 | 316 | return true; |
e4439e43 MR |
317 | } |
318 | ||
bd70b1f2 | 319 | return false; |
e4439e43 MR |
320 | } |
321 | ||
bf9ae9d8 TBA |
322 | bool |
323 | mips_target::low_supports_breakpoints () | |
324 | { | |
325 | return true; | |
326 | } | |
327 | ||
328 | CORE_ADDR | |
329 | mips_target::low_get_pc (regcache *regcache) | |
0d62e5e8 | 330 | { |
186947f7 | 331 | union mips_register pc; |
442ea881 | 332 | collect_register_by_name (regcache, "pc", pc.buf); |
3aee8918 | 333 | return register_size (regcache->tdesc, 0) == 4 ? pc.reg32 : pc.reg64; |
0d62e5e8 DJ |
334 | } |
335 | ||
bf9ae9d8 TBA |
336 | void |
337 | mips_target::low_set_pc (regcache *regcache, CORE_ADDR pc) | |
0d62e5e8 | 338 | { |
186947f7 | 339 | union mips_register newpc; |
3aee8918 | 340 | if (register_size (regcache->tdesc, 0) == 4) |
186947f7 DJ |
341 | newpc.reg32 = pc; |
342 | else | |
343 | newpc.reg64 = pc; | |
344 | ||
442ea881 | 345 | supply_register_by_name (regcache, "pc", newpc.buf); |
0d62e5e8 DJ |
346 | } |
347 | ||
348 | /* Correct in either endianness. */ | |
186947f7 | 349 | static const unsigned int mips_breakpoint = 0x0005000d; |
0d62e5e8 DJ |
350 | #define mips_breakpoint_len 4 |
351 | ||
3ca4edb6 | 352 | /* Implementation of target ops method "sw_breakpoint_from_kind". */ |
dd373349 | 353 | |
3ca4edb6 TBA |
354 | const gdb_byte * |
355 | mips_target::sw_breakpoint_from_kind (int kind, int *size) | |
dd373349 AT |
356 | { |
357 | *size = mips_breakpoint_len; | |
358 | return (const gdb_byte *) &mips_breakpoint; | |
359 | } | |
360 | ||
d7146cda TBA |
361 | bool |
362 | mips_target::low_breakpoint_at (CORE_ADDR where) | |
0d62e5e8 | 363 | { |
186947f7 | 364 | unsigned int insn; |
0d62e5e8 | 365 | |
d7146cda | 366 | read_memory (where, (unsigned char *) &insn, 4); |
0d62e5e8 | 367 | if (insn == mips_breakpoint) |
d7146cda | 368 | return true; |
0d62e5e8 DJ |
369 | |
370 | /* If necessary, recognize more trap instructions here. GDB only uses the | |
371 | one. */ | |
d7146cda | 372 | return false; |
0d62e5e8 DJ |
373 | } |
374 | ||
da25033c | 375 | /* Mark the watch registers of lwp, represented by ENTRY, as changed. */ |
7a60ad40 | 376 | |
da25033c SM |
377 | static void |
378 | update_watch_registers_callback (thread_info *thread) | |
7a60ad40 | 379 | { |
d86d4aaf | 380 | struct lwp_info *lwp = get_thread_lwp (thread); |
7a60ad40 | 381 | |
da25033c SM |
382 | /* The actual update is done later just before resuming the lwp, |
383 | we just mark that the registers need updating. */ | |
384 | lwp->arch_private->watch_registers_changed = 1; | |
7a60ad40 | 385 | |
da25033c SM |
386 | /* If the lwp isn't stopped, force it to momentarily pause, so |
387 | we can update its watch registers. */ | |
388 | if (!lwp->stopped) | |
389 | linux_stop_lwp (lwp); | |
7a60ad40 YQ |
390 | } |
391 | ||
fd000fb3 TBA |
392 | /* This is the implementation of linux target ops method |
393 | low_new_process. */ | |
7a60ad40 | 394 | |
fd000fb3 TBA |
395 | arch_process_info * |
396 | mips_target::low_new_process () | |
7a60ad40 | 397 | { |
8d749320 | 398 | struct arch_process_info *info = XCNEW (struct arch_process_info); |
7a60ad40 YQ |
399 | |
400 | return info; | |
401 | } | |
402 | ||
fd000fb3 TBA |
403 | /* This is the implementation of linux target ops method |
404 | low_delete_process. */ | |
04ec7890 | 405 | |
fd000fb3 TBA |
406 | void |
407 | mips_target::low_delete_process (arch_process_info *info) | |
04ec7890 SM |
408 | { |
409 | xfree (info); | |
410 | } | |
411 | ||
fd000fb3 | 412 | /* This is the implementation of linux target ops method low_new_thread. |
7a60ad40 YQ |
413 | Mark the watch registers as changed, so the threads' copies will |
414 | be updated. */ | |
415 | ||
fd000fb3 TBA |
416 | void |
417 | mips_target::low_new_thread (lwp_info *lwp) | |
7a60ad40 | 418 | { |
8d749320 | 419 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); |
7a60ad40 YQ |
420 | |
421 | info->watch_registers_changed = 1; | |
422 | ||
34c703da | 423 | lwp->arch_private = info; |
7a60ad40 YQ |
424 | } |
425 | ||
466eecee SM |
426 | /* Function to call when a thread is being deleted. */ |
427 | ||
fd000fb3 TBA |
428 | void |
429 | mips_target::low_delete_thread (arch_lwp_info *arch_lwp) | |
466eecee SM |
430 | { |
431 | xfree (arch_lwp); | |
432 | } | |
433 | ||
3a8a0396 DB |
434 | /* Create a new mips_watchpoint and add it to the list. */ |
435 | ||
436 | static void | |
cbec665b | 437 | mips_add_watchpoint (struct arch_process_info *priv, CORE_ADDR addr, int len, |
eb3e3c67 | 438 | enum target_hw_bp_type watch_type) |
3a8a0396 DB |
439 | { |
440 | struct mips_watchpoint *new_watch; | |
441 | struct mips_watchpoint **pw; | |
442 | ||
8d749320 | 443 | new_watch = XNEW (struct mips_watchpoint); |
3a8a0396 DB |
444 | new_watch->addr = addr; |
445 | new_watch->len = len; | |
446 | new_watch->type = watch_type; | |
447 | new_watch->next = NULL; | |
448 | ||
cbec665b | 449 | pw = &priv->current_watches; |
3a8a0396 DB |
450 | while (*pw != NULL) |
451 | pw = &(*pw)->next; | |
452 | *pw = new_watch; | |
453 | } | |
454 | ||
455 | /* Hook to call when a new fork is attached. */ | |
456 | ||
fd000fb3 TBA |
457 | void |
458 | mips_target::low_new_fork (process_info *parent, | |
459 | process_info *child) | |
3a8a0396 DB |
460 | { |
461 | struct arch_process_info *parent_private; | |
462 | struct arch_process_info *child_private; | |
463 | struct mips_watchpoint *wp; | |
464 | ||
465 | /* These are allocated by linux_add_process. */ | |
61a7418c DB |
466 | gdb_assert (parent->priv != NULL |
467 | && parent->priv->arch_private != NULL); | |
468 | gdb_assert (child->priv != NULL | |
469 | && child->priv->arch_private != NULL); | |
3a8a0396 DB |
470 | |
471 | /* Linux kernel before 2.6.33 commit | |
472 | 72f674d203cd230426437cdcf7dd6f681dad8b0d | |
473 | will inherit hardware debug registers from parent | |
474 | on fork/vfork/clone. Newer Linux kernels create such tasks with | |
475 | zeroed debug registers. | |
476 | ||
477 | GDB core assumes the child inherits the watchpoints/hw | |
478 | breakpoints of the parent, and will remove them all from the | |
479 | forked off process. Copy the debug registers mirrors into the | |
480 | new process so that all breakpoints and watchpoints can be | |
481 | removed together. The debug registers mirror will become zeroed | |
482 | in the end before detaching the forked off process, thus making | |
483 | this compatible with older Linux kernels too. */ | |
484 | ||
61a7418c DB |
485 | parent_private = parent->priv->arch_private; |
486 | child_private = child->priv->arch_private; | |
3a8a0396 DB |
487 | |
488 | child_private->watch_readback_valid = parent_private->watch_readback_valid; | |
489 | child_private->watch_readback = parent_private->watch_readback; | |
490 | ||
491 | for (wp = parent_private->current_watches; wp != NULL; wp = wp->next) | |
492 | mips_add_watchpoint (child_private, wp->addr, wp->len, wp->type); | |
493 | ||
494 | child_private->watch_mirror = parent_private->watch_mirror; | |
495 | } | |
d7599cc0 TBA |
496 | /* This is the implementation of linux target ops method |
497 | low_prepare_to_resume. If the watch regs have changed, update the | |
7a60ad40 YQ |
498 | thread's copies. */ |
499 | ||
d7599cc0 TBA |
500 | void |
501 | mips_target::low_prepare_to_resume (lwp_info *lwp) | |
7a60ad40 | 502 | { |
d86d4aaf | 503 | ptid_t ptid = ptid_of (get_lwp_thread (lwp)); |
e99b03dc | 504 | struct process_info *proc = find_process_pid (ptid.pid ()); |
fe978cb0 | 505 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
506 | |
507 | if (lwp->arch_private->watch_registers_changed) | |
508 | { | |
509 | /* Only update the watch registers if we have set or unset a | |
510 | watchpoint already. */ | |
fe978cb0 | 511 | if (mips_linux_watch_get_num_valid (&priv->watch_mirror) > 0) |
7a60ad40 YQ |
512 | { |
513 | /* Write the mirrored watch register values. */ | |
e38504b3 | 514 | int tid = ptid.lwp (); |
7a60ad40 YQ |
515 | |
516 | if (-1 == ptrace (PTRACE_SET_WATCH_REGS, tid, | |
aa58a496 | 517 | &priv->watch_mirror, NULL)) |
7a60ad40 YQ |
518 | perror_with_name ("Couldn't write watch register"); |
519 | } | |
520 | ||
521 | lwp->arch_private->watch_registers_changed = 0; | |
522 | } | |
523 | } | |
524 | ||
007c9b97 TBA |
525 | bool |
526 | mips_target::supports_z_point_type (char z_type) | |
802e8e6d PA |
527 | { |
528 | switch (z_type) | |
529 | { | |
530 | case Z_PACKET_WRITE_WP: | |
531 | case Z_PACKET_READ_WP: | |
532 | case Z_PACKET_ACCESS_WP: | |
007c9b97 | 533 | return true; |
802e8e6d | 534 | default: |
007c9b97 | 535 | return false; |
802e8e6d PA |
536 | } |
537 | } | |
538 | ||
9db9aa23 TBA |
539 | /* This is the implementation of linux target ops method |
540 | low_insert_point. */ | |
7a60ad40 | 541 | |
9db9aa23 TBA |
542 | int |
543 | mips_target::low_insert_point (raw_bkpt_type type, CORE_ADDR addr, | |
544 | int len, raw_breakpoint *bp) | |
7a60ad40 YQ |
545 | { |
546 | struct process_info *proc = current_process (); | |
fe978cb0 | 547 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 | 548 | struct pt_watch_regs regs; |
7a60ad40 YQ |
549 | long lwpid; |
550 | enum target_hw_bp_type watch_type; | |
551 | uint32_t irw; | |
552 | ||
0bfdf32f | 553 | lwpid = lwpid_of (current_thread); |
7a60ad40 | 554 | if (!mips_linux_read_watch_registers (lwpid, |
fe978cb0 PA |
555 | &priv->watch_readback, |
556 | &priv->watch_readback_valid, | |
7a60ad40 YQ |
557 | 0)) |
558 | return -1; | |
559 | ||
560 | if (len <= 0) | |
561 | return -1; | |
562 | ||
fe978cb0 | 563 | regs = priv->watch_readback; |
7a60ad40 | 564 | /* Add the current watches. */ |
fe978cb0 | 565 | mips_linux_watch_populate_regs (priv->current_watches, ®s); |
7a60ad40 YQ |
566 | |
567 | /* Now try to add the new watch. */ | |
802e8e6d | 568 | watch_type = raw_bkpt_type_to_target_hw_bp_type (type); |
7a60ad40 YQ |
569 | irw = mips_linux_watch_type_to_irw (watch_type); |
570 | if (!mips_linux_watch_try_one_watch (®s, addr, len, irw)) | |
571 | return -1; | |
572 | ||
573 | /* It fit. Stick it on the end of the list. */ | |
3a8a0396 | 574 | mips_add_watchpoint (priv, addr, len, watch_type); |
7a60ad40 | 575 | |
fe978cb0 | 576 | priv->watch_mirror = regs; |
7a60ad40 YQ |
577 | |
578 | /* Only update the threads of this process. */ | |
da25033c | 579 | for_each_thread (proc->pid, update_watch_registers_callback); |
7a60ad40 YQ |
580 | |
581 | return 0; | |
582 | } | |
583 | ||
9db9aa23 TBA |
584 | /* This is the implementation of linux target ops method |
585 | low_remove_point. */ | |
7a60ad40 | 586 | |
9db9aa23 TBA |
587 | int |
588 | mips_target::low_remove_point (raw_bkpt_type type, CORE_ADDR addr, | |
589 | int len, raw_breakpoint *bp) | |
7a60ad40 YQ |
590 | { |
591 | struct process_info *proc = current_process (); | |
fe978cb0 | 592 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
593 | |
594 | int deleted_one; | |
7a60ad40 YQ |
595 | enum target_hw_bp_type watch_type; |
596 | ||
597 | struct mips_watchpoint **pw; | |
598 | struct mips_watchpoint *w; | |
599 | ||
7a60ad40 | 600 | /* Search for a known watch that matches. Then unlink and free it. */ |
802e8e6d | 601 | watch_type = raw_bkpt_type_to_target_hw_bp_type (type); |
7a60ad40 | 602 | deleted_one = 0; |
fe978cb0 | 603 | pw = &priv->current_watches; |
7a60ad40 YQ |
604 | while ((w = *pw)) |
605 | { | |
606 | if (w->addr == addr && w->len == len && w->type == watch_type) | |
607 | { | |
608 | *pw = w->next; | |
609 | free (w); | |
610 | deleted_one = 1; | |
611 | break; | |
612 | } | |
613 | pw = &(w->next); | |
614 | } | |
615 | ||
616 | if (!deleted_one) | |
617 | return -1; /* We don't know about it, fail doing nothing. */ | |
618 | ||
619 | /* At this point watch_readback is known to be valid because we | |
620 | could not have added the watch without reading it. */ | |
fe978cb0 | 621 | gdb_assert (priv->watch_readback_valid == 1); |
7a60ad40 | 622 | |
fe978cb0 PA |
623 | priv->watch_mirror = priv->watch_readback; |
624 | mips_linux_watch_populate_regs (priv->current_watches, | |
625 | &priv->watch_mirror); | |
7a60ad40 YQ |
626 | |
627 | /* Only update the threads of this process. */ | |
da25033c SM |
628 | for_each_thread (proc->pid, update_watch_registers_callback); |
629 | ||
7a60ad40 YQ |
630 | return 0; |
631 | } | |
632 | ||
ac1bbaca TBA |
633 | /* This is the implementation of linux target ops method |
634 | low_stopped_by_watchpoint. The watchhi R and W bits indicate | |
7a60ad40 YQ |
635 | the watch register triggered. */ |
636 | ||
ac1bbaca TBA |
637 | bool |
638 | mips_target::low_stopped_by_watchpoint () | |
7a60ad40 YQ |
639 | { |
640 | struct process_info *proc = current_process (); | |
fe978cb0 | 641 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
642 | int n; |
643 | int num_valid; | |
0bfdf32f | 644 | long lwpid = lwpid_of (current_thread); |
7a60ad40 YQ |
645 | |
646 | if (!mips_linux_read_watch_registers (lwpid, | |
fe978cb0 PA |
647 | &priv->watch_readback, |
648 | &priv->watch_readback_valid, | |
7a60ad40 YQ |
649 | 1)) |
650 | return 0; | |
651 | ||
fe978cb0 | 652 | num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback); |
7a60ad40 YQ |
653 | |
654 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
fe978cb0 | 655 | if (mips_linux_watch_get_watchhi (&priv->watch_readback, n) |
7a60ad40 | 656 | & (R_MASK | W_MASK)) |
ac1bbaca | 657 | return true; |
7a60ad40 | 658 | |
ac1bbaca | 659 | return false; |
7a60ad40 YQ |
660 | } |
661 | ||
ac1bbaca TBA |
662 | /* This is the implementation of linux target ops method |
663 | low_stopped_data_address. */ | |
7a60ad40 | 664 | |
ac1bbaca TBA |
665 | CORE_ADDR |
666 | mips_target::low_stopped_data_address () | |
7a60ad40 YQ |
667 | { |
668 | struct process_info *proc = current_process (); | |
fe978cb0 | 669 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
670 | int n; |
671 | int num_valid; | |
0bfdf32f | 672 | long lwpid = lwpid_of (current_thread); |
7a60ad40 YQ |
673 | |
674 | /* On MIPS we don't know the low order 3 bits of the data address. | |
675 | GDB does not support remote targets that can't report the | |
676 | watchpoint address. So, make our best guess; return the starting | |
677 | address of a watchpoint request which overlaps the one that | |
678 | triggered. */ | |
679 | ||
680 | if (!mips_linux_read_watch_registers (lwpid, | |
fe978cb0 PA |
681 | &priv->watch_readback, |
682 | &priv->watch_readback_valid, | |
7a60ad40 YQ |
683 | 0)) |
684 | return 0; | |
685 | ||
fe978cb0 | 686 | num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback); |
7a60ad40 YQ |
687 | |
688 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
fe978cb0 | 689 | if (mips_linux_watch_get_watchhi (&priv->watch_readback, n) |
7a60ad40 YQ |
690 | & (R_MASK | W_MASK)) |
691 | { | |
692 | CORE_ADDR t_low, t_hi; | |
693 | int t_irw; | |
694 | struct mips_watchpoint *watch; | |
695 | ||
fe978cb0 | 696 | t_low = mips_linux_watch_get_watchlo (&priv->watch_readback, n); |
7a60ad40 | 697 | t_irw = t_low & IRW_MASK; |
fe978cb0 | 698 | t_hi = (mips_linux_watch_get_watchhi (&priv->watch_readback, n) |
7a60ad40 YQ |
699 | | IRW_MASK); |
700 | t_low &= ~(CORE_ADDR)t_hi; | |
701 | ||
fe978cb0 | 702 | for (watch = priv->current_watches; |
7a60ad40 YQ |
703 | watch != NULL; |
704 | watch = watch->next) | |
705 | { | |
706 | CORE_ADDR addr = watch->addr; | |
707 | CORE_ADDR last_byte = addr + watch->len - 1; | |
708 | ||
709 | if ((t_irw & mips_linux_watch_type_to_irw (watch->type)) == 0) | |
710 | { | |
711 | /* Different type. */ | |
712 | continue; | |
713 | } | |
714 | /* Check for overlap of even a single byte. */ | |
715 | if (last_byte >= t_low && addr <= t_low + t_hi) | |
716 | return addr; | |
717 | } | |
718 | } | |
719 | ||
720 | /* Shouldn't happen. */ | |
721 | return 0; | |
722 | } | |
723 | ||
21b0f40c DJ |
724 | /* Fetch the thread-local storage pointer for libthread_db. */ |
725 | ||
726 | ps_err_e | |
754653a7 | 727 | ps_get_thread_area (struct ps_prochandle *ph, |
1b3f6016 | 728 | lwpid_t lwpid, int idx, void **base) |
21b0f40c DJ |
729 | { |
730 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
731 | return PS_ERR; | |
732 | ||
733 | /* IDX is the bias from the thread pointer to the beginning of the | |
734 | thread descriptor. It has to be subtracted due to implementation | |
735 | quirks in libthread_db. */ | |
736 | *base = (void *) ((char *)*base - idx); | |
737 | ||
738 | return PS_OK; | |
739 | } | |
740 | ||
186947f7 | 741 | static void |
442ea881 PA |
742 | mips_collect_register (struct regcache *regcache, |
743 | int use_64bit, int regno, union mips_register *reg) | |
186947f7 DJ |
744 | { |
745 | union mips_register tmp_reg; | |
746 | ||
747 | if (use_64bit) | |
748 | { | |
442ea881 | 749 | collect_register (regcache, regno, &tmp_reg.reg64); |
186947f7 DJ |
750 | *reg = tmp_reg; |
751 | } | |
752 | else | |
753 | { | |
442ea881 | 754 | collect_register (regcache, regno, &tmp_reg.reg32); |
186947f7 DJ |
755 | reg->reg64 = tmp_reg.reg32; |
756 | } | |
757 | } | |
758 | ||
759 | static void | |
442ea881 PA |
760 | mips_supply_register (struct regcache *regcache, |
761 | int use_64bit, int regno, const union mips_register *reg) | |
186947f7 DJ |
762 | { |
763 | int offset = 0; | |
764 | ||
765 | /* For big-endian 32-bit targets, ignore the high four bytes of each | |
766 | eight-byte slot. */ | |
767 | if (__BYTE_ORDER == __BIG_ENDIAN && !use_64bit) | |
768 | offset = 4; | |
769 | ||
442ea881 | 770 | supply_register (regcache, regno, reg->buf + offset); |
186947f7 DJ |
771 | } |
772 | ||
7e947ad3 MR |
773 | #ifdef HAVE_PTRACE_GETREGS |
774 | ||
186947f7 | 775 | static void |
442ea881 PA |
776 | mips_collect_register_32bit (struct regcache *regcache, |
777 | int use_64bit, int regno, unsigned char *buf) | |
186947f7 DJ |
778 | { |
779 | union mips_register tmp_reg; | |
780 | int reg32; | |
781 | ||
442ea881 | 782 | mips_collect_register (regcache, use_64bit, regno, &tmp_reg); |
186947f7 DJ |
783 | reg32 = tmp_reg.reg64; |
784 | memcpy (buf, ®32, 4); | |
785 | } | |
786 | ||
787 | static void | |
442ea881 PA |
788 | mips_supply_register_32bit (struct regcache *regcache, |
789 | int use_64bit, int regno, const unsigned char *buf) | |
186947f7 DJ |
790 | { |
791 | union mips_register tmp_reg; | |
792 | int reg32; | |
793 | ||
794 | memcpy (®32, buf, 4); | |
795 | tmp_reg.reg64 = reg32; | |
442ea881 | 796 | mips_supply_register (regcache, use_64bit, regno, &tmp_reg); |
186947f7 DJ |
797 | } |
798 | ||
799 | static void | |
442ea881 | 800 | mips_fill_gregset (struct regcache *regcache, void *buf) |
186947f7 | 801 | { |
1996e237 | 802 | union mips_register *regset = (union mips_register *) buf; |
186947f7 | 803 | int i, use_64bit; |
3aee8918 | 804 | const struct target_desc *tdesc = regcache->tdesc; |
186947f7 | 805 | |
3aee8918 | 806 | use_64bit = (register_size (tdesc, 0) == 8); |
186947f7 | 807 | |
117ce543 | 808 | for (i = 1; i < 32; i++) |
442ea881 PA |
809 | mips_collect_register (regcache, use_64bit, i, regset + i); |
810 | ||
811 | mips_collect_register (regcache, use_64bit, | |
3aee8918 | 812 | find_regno (tdesc, "lo"), regset + 32); |
442ea881 | 813 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 814 | find_regno (tdesc, "hi"), regset + 33); |
442ea881 | 815 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 816 | find_regno (tdesc, "pc"), regset + 34); |
442ea881 | 817 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 818 | find_regno (tdesc, "badvaddr"), regset + 35); |
442ea881 | 819 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 820 | find_regno (tdesc, "status"), regset + 36); |
442ea881 | 821 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 822 | find_regno (tdesc, "cause"), regset + 37); |
442ea881 PA |
823 | |
824 | mips_collect_register (regcache, use_64bit, | |
3aee8918 | 825 | find_regno (tdesc, "restart"), regset + 0); |
186947f7 DJ |
826 | } |
827 | ||
828 | static void | |
442ea881 | 829 | mips_store_gregset (struct regcache *regcache, const void *buf) |
186947f7 | 830 | { |
1996e237 | 831 | const union mips_register *regset = (const union mips_register *) buf; |
186947f7 DJ |
832 | int i, use_64bit; |
833 | ||
3aee8918 | 834 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
186947f7 | 835 | |
e4439e43 MR |
836 | supply_register_by_name_zeroed (regcache, "r0"); |
837 | ||
838 | for (i = 1; i < 32; i++) | |
442ea881 PA |
839 | mips_supply_register (regcache, use_64bit, i, regset + i); |
840 | ||
442ea881 | 841 | mips_supply_register (regcache, use_64bit, |
3aee8918 PA |
842 | find_regno (regcache->tdesc, "lo"), regset + 32); |
843 | mips_supply_register (regcache, use_64bit, | |
844 | find_regno (regcache->tdesc, "hi"), regset + 33); | |
442ea881 | 845 | mips_supply_register (regcache, use_64bit, |
3aee8918 | 846 | find_regno (regcache->tdesc, "pc"), regset + 34); |
442ea881 | 847 | mips_supply_register (regcache, use_64bit, |
3aee8918 PA |
848 | find_regno (regcache->tdesc, "badvaddr"), regset + 35); |
849 | mips_supply_register (regcache, use_64bit, | |
850 | find_regno (regcache->tdesc, "status"), regset + 36); | |
851 | mips_supply_register (regcache, use_64bit, | |
852 | find_regno (regcache->tdesc, "cause"), regset + 37); | |
442ea881 PA |
853 | |
854 | mips_supply_register (regcache, use_64bit, | |
3aee8918 | 855 | find_regno (regcache->tdesc, "restart"), regset + 0); |
186947f7 DJ |
856 | } |
857 | ||
858 | static void | |
442ea881 | 859 | mips_fill_fpregset (struct regcache *regcache, void *buf) |
186947f7 | 860 | { |
1996e237 | 861 | union mips_register *regset = (union mips_register *) buf; |
186947f7 DJ |
862 | int i, use_64bit, first_fp, big_endian; |
863 | ||
3aee8918 PA |
864 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
865 | first_fp = find_regno (regcache->tdesc, "f0"); | |
186947f7 DJ |
866 | big_endian = (__BYTE_ORDER == __BIG_ENDIAN); |
867 | ||
868 | /* See GDB for a discussion of this peculiar layout. */ | |
869 | for (i = 0; i < 32; i++) | |
870 | if (use_64bit) | |
442ea881 | 871 | collect_register (regcache, first_fp + i, regset[i].buf); |
186947f7 | 872 | else |
442ea881 | 873 | collect_register (regcache, first_fp + i, |
186947f7 DJ |
874 | regset[i & ~1].buf + 4 * (big_endian != (i & 1))); |
875 | ||
442ea881 | 876 | mips_collect_register_32bit (regcache, use_64bit, |
3aee8918 PA |
877 | find_regno (regcache->tdesc, "fcsr"), regset[32].buf); |
878 | mips_collect_register_32bit (regcache, use_64bit, | |
879 | find_regno (regcache->tdesc, "fir"), | |
186947f7 DJ |
880 | regset[32].buf + 4); |
881 | } | |
882 | ||
883 | static void | |
442ea881 | 884 | mips_store_fpregset (struct regcache *regcache, const void *buf) |
186947f7 | 885 | { |
1996e237 | 886 | const union mips_register *regset = (const union mips_register *) buf; |
186947f7 DJ |
887 | int i, use_64bit, first_fp, big_endian; |
888 | ||
3aee8918 PA |
889 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
890 | first_fp = find_regno (regcache->tdesc, "f0"); | |
186947f7 DJ |
891 | big_endian = (__BYTE_ORDER == __BIG_ENDIAN); |
892 | ||
893 | /* See GDB for a discussion of this peculiar layout. */ | |
894 | for (i = 0; i < 32; i++) | |
895 | if (use_64bit) | |
442ea881 | 896 | supply_register (regcache, first_fp + i, regset[i].buf); |
186947f7 | 897 | else |
442ea881 | 898 | supply_register (regcache, first_fp + i, |
186947f7 DJ |
899 | regset[i & ~1].buf + 4 * (big_endian != (i & 1))); |
900 | ||
442ea881 | 901 | mips_supply_register_32bit (regcache, use_64bit, |
3aee8918 PA |
902 | find_regno (regcache->tdesc, "fcsr"), |
903 | regset[32].buf); | |
904 | mips_supply_register_32bit (regcache, use_64bit, | |
905 | find_regno (regcache->tdesc, "fir"), | |
186947f7 DJ |
906 | regset[32].buf + 4); |
907 | } | |
908 | #endif /* HAVE_PTRACE_GETREGS */ | |
909 | ||
7e947ad3 MR |
910 | /* Take care of 32-bit registers with 64-bit ptrace, POKEUSER side. */ |
911 | ||
b35db733 TBA |
912 | void |
913 | mips_target::low_collect_ptrace_register (regcache *regcache, int regno, | |
914 | char *buf) | |
7e947ad3 | 915 | { |
7e947ad3 MR |
916 | int use_64bit = sizeof (PTRACE_XFER_TYPE) == 8; |
917 | ||
918 | if (use_64bit && register_size (regcache->tdesc, regno) == 4) | |
919 | { | |
920 | union mips_register reg; | |
921 | ||
922 | mips_collect_register (regcache, 0, regno, ®); | |
923 | memcpy (buf, ®, sizeof (reg)); | |
924 | } | |
925 | else | |
926 | collect_register (regcache, regno, buf); | |
927 | } | |
928 | ||
929 | /* Take care of 32-bit registers with 64-bit ptrace, PEEKUSER side. */ | |
930 | ||
b35db733 TBA |
931 | void |
932 | mips_target::low_supply_ptrace_register (regcache *regcache, int regno, | |
933 | const char *buf) | |
7e947ad3 | 934 | { |
7e947ad3 MR |
935 | int use_64bit = sizeof (PTRACE_XFER_TYPE) == 8; |
936 | ||
937 | if (use_64bit && register_size (regcache->tdesc, regno) == 4) | |
938 | { | |
939 | union mips_register reg; | |
940 | ||
941 | memcpy (®, buf, sizeof (reg)); | |
942 | mips_supply_register (regcache, 0, regno, ®); | |
943 | } | |
944 | else | |
945 | supply_register (regcache, regno, buf); | |
946 | } | |
947 | ||
3aee8918 | 948 | static struct regset_info mips_regsets[] = { |
186947f7 | 949 | #ifdef HAVE_PTRACE_GETREGS |
1570b33e | 950 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, 38 * 8, GENERAL_REGS, |
186947f7 | 951 | mips_fill_gregset, mips_store_gregset }, |
1570b33e | 952 | { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, 33 * 8, FP_REGS, |
186947f7 DJ |
953 | mips_fill_fpregset, mips_store_fpregset }, |
954 | #endif /* HAVE_PTRACE_GETREGS */ | |
50bc912a | 955 | NULL_REGSET |
186947f7 DJ |
956 | }; |
957 | ||
3aee8918 PA |
958 | static struct regsets_info mips_regsets_info = |
959 | { | |
960 | mips_regsets, /* regsets */ | |
961 | 0, /* num_regsets */ | |
962 | NULL, /* disabled_regsets */ | |
963 | }; | |
964 | ||
965 | static struct usrregs_info mips_dsp_usrregs_info = | |
966 | { | |
967 | mips_dsp_num_regs, | |
968 | mips_dsp_regmap, | |
969 | }; | |
970 | ||
971 | static struct usrregs_info mips_usrregs_info = | |
972 | { | |
973 | mips_num_regs, | |
974 | mips_regmap, | |
975 | }; | |
976 | ||
977 | static struct regs_info dsp_regs_info = | |
978 | { | |
979 | mips_dsp_regset_bitmap, | |
980 | &mips_dsp_usrregs_info, | |
981 | &mips_regsets_info | |
982 | }; | |
983 | ||
aa8d21c9 | 984 | static struct regs_info myregs_info = |
3aee8918 PA |
985 | { |
986 | NULL, /* regset_bitmap */ | |
987 | &mips_usrregs_info, | |
988 | &mips_regsets_info | |
989 | }; | |
990 | ||
aa8d21c9 TBA |
991 | const regs_info * |
992 | mips_target::get_regs_info () | |
3aee8918 PA |
993 | { |
994 | if (have_dsp) | |
995 | return &dsp_regs_info; | |
996 | else | |
aa8d21c9 | 997 | return &myregs_info; |
3aee8918 PA |
998 | } |
999 | ||
ef0478f6 TBA |
1000 | /* The linux target ops object. */ |
1001 | ||
1002 | linux_process_target *the_linux_target = &the_mips_target; | |
1003 | ||
3aee8918 PA |
1004 | void |
1005 | initialize_low_arch (void) | |
1006 | { | |
1007 | /* Initialize the Linux target descriptions. */ | |
1008 | init_registers_mips_linux (); | |
1009 | init_registers_mips_dsp_linux (); | |
1010 | init_registers_mips64_linux (); | |
1011 | init_registers_mips64_dsp_linux (); | |
1012 | ||
1013 | initialize_regsets_info (&mips_regsets_info); | |
1014 | } |