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Fix an integer overflow in RISC-V relocation handling
[deliverable/binutils-gdb.git] / include / ChangeLog
CommitLineData
45f76423
AW		 12016-12-20 Andrew Waterman <andrew@sifive.com>
2 Kuan-Lin Chen <kuanlinchentw@gmail.com>
3
4 * elf/riscv.h: Add R_RISCV_TPREL_I through R_RISCV_SET32.
5
22185505 62016-12-16 fincs <fincs.alt1@gmail.com>
7
8 * bfdlink.h (struct bfd_link_info): Add gc_keep_exported.
9
5e7fc731
MR		 102016-12-14 Maciej W. Rozycki <macro@imgtec.com>
11
12 * elf/mips.h (Elf_Internal_ABIFlags_v0): Also declare struct
13 typedef as `elf_internal_abiflags_v0'.
14
a6a51754
RL		 152016-12-13 Renlin Li <renlin.li@arm.com>
16
17 * opcode/aarch64.h (aarch64_operand_class): Remove
18 AARCH64_OPND_CLASS_CP_REG.
19 (enum aarch64_opnd): Change AARCH64_OPND_Cn to AARCH64_OPND_CRn,
20 AARCH64_OPND_Cm to AARCH64_OPND_CRm.
21 (aarch64_opnd_qualifier): Define AARCH64_OPND_QLF_CR qualifier.
22
64c11183
MR		 232016-12-09 Maciej W. Rozycki <macro@imgtec.com>
24
25 * opcode/mips.h: Remove references to `>' operand code.
26
4b078115
MR		 272016-12-07 Maciej W. Rozycki <macro@imgtec.com>
28
29 * opcode/mips.h (INSN_CHIP_MASK): Update according to bit use.
30
b8760d2c
MR		 312016-12-07 Maciej W. Rozycki <macro@imgtec.com>
32
33 * opcode/mips.h (ASE_DSPR3): Add a comment.
34
a12fd8e1
SN		 352016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
36
37 * opcode/arm.h (ARM_EXT2_V8_3A, ARM_AEXT2_V8_3A): New.
38 (ARM_ARCH_V8_3A): New.
39
abe7c33b
CZ		 402016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
41
42 * opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE
43 instruction classes.
44
6884417a
JM		 452016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
46
47 * opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
48 hwcaps2.
49
08dc996f
AM		 502016-11-22 Alan Modra <amodra@gmail.com>
51
52 PR 20744
53 * opcode/ppc.h: Define VLE insns using 16A and 16D relocs.
54
535aade6
DT		 552016-11-03 David Tolnay <dtolnay@gmail.com>
56 Mark Wielaard <mark@klomp.org>
57
58 * demangle.h (DMGL_RUST): New macro.
59 (DMGL_STYLE_MASK): Add DMGL_RUST.
60 (demangling_styles): Add dlang_rust.
61 (RUST_DEMANGLING_STYLE_STRING): New macro.
62 (RUST_DEMANGLING): New macro.
63 (rust_demangle): New prototype.
64 (rust_is_mangled): Likewise.
65 (rust_demangle_sym): Likewise.
66
a4ddf8dc
JM		 672016-11-07 Jason Merrill <jason@redhat.com>
68
69 * demangle.h (enum demangle_component_type): Add
70 DEMANGLE_COMPONENT_NOEXCEPT, DEMANGLE_COMPONENT_THROW_SPEC.
71
c2c4ff8d
SN		 722016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
73
74 * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1,
75 AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3.
76 (enum aarch64_op): Add OP_FCMLA_ELEM.
77
3f06e550
SN		 782016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
79
80 * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM10.
81 (enum aarch64_insn_class): Add ldst_imm10.
82
c84364ec
SN		 832016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
84
85 * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rm_SP.
86
1924ff75
SN		 872016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
88
89 * opcode/aarch64.h (AARCH64_FEATURE_V8_3): Define.
90 (AARCH64_ARCH_V8_3): Define.
91 (AARCH64_ARCH_V8_1, AARCH64_ARCH_V8_2): Simplify.
92
d46a2165
TP		 932016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
94
95 * opcode/arm.h (ARM_AEXT_V8M_MAIN_DSP): Define.
96 (ARM_AEXT2_V8M_MAIN_DSP): Likewise.
97 (ARM_ARCH_V8M_MAIN_DSP): Likewise.
98
5a736821
GM		 992016-11-03 Graham Markall <graham.markall@embecosm.com>
100
101 * opcode/arc.h: Add PROTOCOL_DECODE to insn_class_t.
102
bdfe53e3
AB		 1032016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
104
105 * opcode/arc.h (struct arc_opcode): Change type of opcode and mask
106 fields.
107 (struct arc_long_opcode): Delete.
108 (struct arc_operand): Change types for insert and extract
109 handlers.
110
2e272202
GM		 1112016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
112
113 * opcode/arc.h: Make macros 64-bit safe.
114
06fe285f
GM		 1152016-11-03 Graham Markall <graham.markall@embecosm.com>
116
117 * opcode/arc.h (arc_opcode_len): Declare.
118 (ARC_SHORT): Delete.
119
e23eba97
NC		 1202016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
121 Andrew Waterman <andrew@sifive.com>
122
123 Add support for RISC-V architecture.
124 * dis-asm.h: Add prototypes for print_insn_riscv and
125 print_riscv_disassembler_options.
126 * elf/riscv.h: New file.
127 * opcode/riscv-opc.h: New file.
128 * opcode/riscv.h: New file.
129
6d913794
NC		 1302016-10-17 Nick Clifton <nickc@redhat.com>
131
132 * elf/common.h (DT_SYMTAB_SHNDX): Define.
133 (EM_CLOUDSHIELD, EM_COREA_1ST, EM_COREA_2ND, EM_OPEN8): Define.
134 (EM_VIDEOCORE5, EM_56800EX, EM_BA1, EM_BA2, EM_XCORE): Define.
135 (EM_MCHP_PIC, EM_KM32, EM_KMX32, EM_KMX16, EM_KMX8): Define.
136 (EM_KVARC, EM_CDP, EM_COGE, EM_COOL, EM_NORC): Define.
137 (EM_CSR_KALIMBA, EM_Z80, EM_AMDGPU, EM_RISCV): Define.
138 (ELFOSABI_OPENVOS): Define.
139 (GRP_MASKOS, GRP_MASKPROC): Define.
140
b4f6af8e
PA		 1412016-10-14 Pedro Alves <palves@redhat.com>
142
143 * ansidecl.h [__cplusplus >= 201103 && GCC_VERSION < 4007] (FINAL,
144 OVERRIDE): Define as empty.
145 [__cplusplus < 201103 && GCC_VERSION < 4007] (FINAL): Define as
146 __final.
147 [__cplusplus < 201103 && GCC_VERSION >= 4007] (OVERRIDE): Define as
148 empty.
149
d118ee37
PA		 1502016-10-14 Pedro Alves <palves@redhat.com>
151
152 * ansidecl.h (GCC_FINAL): Delete.
153 (OVERRIDE, FINAL): New, moved from gcc/coretypes.h.
154
e5b06ef0
CZ		 1552016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
156
157 * opcode/arc.h (ARC_OPCODE_ARCV2): New define.
158
a5721ba2
AM		 1592016-09-29 Alan Modra <amodra@gmail.com>
160
161 * opcode/ppc.h (PPC_OPERAND_OPTIONAL32): Define.
162
2b848ebd
CZ		 1632016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
164
165 * opcode/arc.h (insn_class_t): Add two new classes.
166
005d79fd
AM		 1672016-09-26 Alan Modra <amodra@gmail.com>
168
169 * elf/ppc.h (Tag_GNU_Power_ABI_FP): Comment on new values.
170
bb7eff52
RS		 1712016-09-21 Richard Sandiford <richard.sandiford@arm.com>
172
173 * opcode/aarch64.h (aarch64_cond): Bump array size to 4.
174
c0890d26
RS		 1752016-09-21 Richard Sandiford <richard.sandiford@arm.com>
176
177 * opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro.
178 (OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi)
179 (OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P)
180 (OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops.
181
116b6019
RS		 1822016-09-21 Richard Sandiford <richard.sandiford@arm.com>
183
184 * opcode/aarch64.h (sve_cpy, sve_index, sve_limm, sve_misc)
185 (sve_movprfx, sve_pred_zm, sve_shift_pred, sve_shift_unpred)
186 (sve_size_bhs, sve_size_bhsd, sve_size_hsd, sve_size_sd): New
187 aarch64_insn_classes.
188
047cd301
RS		 1892016-09-21 Richard Sandiford <richard.sandiford@arm.com>
190
191 * opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd.
192 (AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd)
193 (AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise.
194
165d4950
RS		 1952016-09-21 Richard Sandiford <richard.sandiford@arm.com>
196
197 * opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd.
198 (AARCH64_OPND_SVE_I1_HALF_ONE, AARCH64_OPND_SVE_I1_HALF_TWO)
199 (AARCH64_OPND_SVE_I1_ZERO_ONE): Likewise.
200
e950b345
RS		 2012016-09-21 Richard Sandiford <richard.sandiford@arm.com>
202
203 * opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
204 (AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
205 (AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
206 (AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
207 (AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
208 (AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
209 (AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
210 (AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
211 (AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
212 (AARCH64_OPND_SVE_UIMM8_53): Likewise.
213 (aarch64_sve_dupm_mov_immediate_p): Declare.
214
98907a70
RS		 2152016-09-21 Richard Sandiford <richard.sandiford@arm.com>
216
217 * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd.
218 (AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL)
219 (AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL)
220 (AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise.
221 (AARCH64_MOD_MUL_VL): New aarch64_modifier_kind.
222
4df068de
RS		 2232016-09-21 Richard Sandiford <richard.sandiford@arm.com>
224
225 * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
226 (AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
227 (AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
228 (AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
229 (AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
230 (AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
231 (AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
232 (AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
233 (AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
234 (AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
235 (AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
236 (AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
237 (AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
238 (AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
239 (AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
240 (AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
241 Likewise.
242
2442d846
RS		 2432016-09-21 Richard Sandiford <richard.sandiford@arm.com>
244
245 * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New
246 aarch64_opnd.
247 (AARCH64_MOD_MUL): New aarch64_modifier_kind.
248 (aarch64_opnd_info): Make shifter.amount an int64_t and
249 rearrange the fields.
250
245d2e3f
RS		 2512016-09-21 Richard Sandiford <richard.sandiford@arm.com>
252
253 * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN): New aarch64_opnd.
254 (AARCH64_OPND_SVE_PRFOP): Likewise.
255 (aarch64_sve_pattern_array): Declare.
256 (aarch64_sve_prfop_array): Likewise.
257
d50c751e
RS		 2582016-09-21 Richard Sandiford <richard.sandiford@arm.com>
259
260 * opcode/aarch64.h (AARCH64_OPND_QLF_P_Z): New aarch64_opnd_qualifier.
261 (AARCH64_OPND_QLF_P_M): Likewise.
262
f11ad6bc
RS		 2632016-09-21 Richard Sandiford <richard.sandiford@arm.com>
264
265 * opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
266 aarch64_operand_class.
267 (AARCH64_OPND_CLASS_PRED_REG): Likewise.
268 (AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
269 (AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
270 (AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
271 (AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
272 (AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
273 (AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
274 (AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
275
0c608d6b
RS		 2762016-09-21 Richard Sandiford <richard.sandiford@arm.com>
277
278 * opcode/aarch64.h (aarch64_opcode): Add a tied_operand field.
279 (AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind.
280
4989adac
RS		 2812016-09-21 Richard Sandiford <richard.sandiford@arm.com>
282
283 * opcode/aarch64.h (F_STRICT): New flag.
284
27e5a270
RE		 2852016-09-07 Richard Earnshaw <rearnsha@arm.com>
286
287 * opcode/arm.h (ARM_ARCH_V8A_CRC): New architecture.
288
a87aa054
CM		 2892016-08-26 Cupertino Miranda <cmiranda@synopsys.com>
290 * elf/arc-reloc.def: Fixed relocation formula for N*, SDA, SDA_12,
291 SDA_16_LD*, S13_PCREL, N32_ME, SECTOFF_* relocations.
292 * opcode/arc-func.h (replace_disp12s): Added. Used for SDA_12
293 relocation.
294
4ba2ef8f
TP		 2952016-08-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
296
297 * arm.h (ARM_GET_SYM_CMSE_SPCL): Define macro.
298 (ARM_SET_SYM_CMSE_SPCL): Likewise.
299
dfdaec14
AJ		 3002016-08-01 Andrew Jenner <andrew@codesourcery.com>
301
302 * opcode/ppc.h (PPC_OPCODE_E200Z4): New define.
303
fa3fcee7
NC		 3042016-07-29 Aldy Hernandez <aldyh@redhat.com>
305
306 * libiberty.h (MAX_ALLOCA_SIZE): New macro.
307
db18dbab
GM		 3082016-07-27 Graham Markall <graham.markall@embecosm.com>
309
310 * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE,
311 ARC_OPERAND_COLON. Add the arc_nps_address_type enum and
312 ARC_NUM_ADDRTYPES.
313 * opcode/arc.h: Add BMU to insn_class_t enum.
314 * opcode/arc.h: Add PMU to insn_class_t enum.
315
37fd5ef3
CZ		 3162016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
317
318 * dis-asm.h: Declare print_arc_disassembler_options.
319
76359541
TP		 3202016-07-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
321
322 * bfdlink.h (struct bfd_link_info): Declare new ldscript_def and
323 out_implib_bfd fields.
324
fa1c0170
CZ		 3252016-07-14 Claudiu Zissulescu <claziss@synopsys.com>
326
327 * elf/arc-reloc.def (ARC_SDA32): Don't use ME transformation.
328
f0728ee3
AV		 3292016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com>
330
331 * include/elf/arm.h (SHF_ARM_NOREAD): Rename to ...
332 (SHF_ARM_PURECODE): ... this.
333
93d8990c
SN		 3342016-07-01 Szabolcs Nagy <szabolcs.nagy@arm.com>
335
336 * opcode/aarch64.h (AARCH64_CPU_HAS_ALL_FEATURES): New.
337 (AARCH64_CPU_HAS_ANY_FEATURES): New.
338 (AARCH64_CPU_HAS_FEATURE): Define as AARCH64_CPU_HAS_ALL_FEATURES.
339 (AARCH64_OPCODE_HAS_FEATURE): Remove.
340
534dbe46
MW		 3412016-06-30 Matthew Wahab <matthew.wahab@arm.com>
342
343 * opcode/arm.h (ARM_ARCH_V8_2a): Add FPU_NEON_EXT_RDMA to the set
344 of enabled FPU features.
345
042c94de
TS		 3462016-06-29 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
347
348 * opcode/sparc.h (enum sparc_opcode_arch_val): Move
349 SPARC_OPCODE_ARCH_MAX into the enum.
350
dab26bf4
RS		 3512016-06-28 Richard Sandiford <richard.sandiford@arm.com>
352
353 * opcode/aarch64.h (aarch64_opnd_info): Change index fields to int64_t.
354
c9775dde
MR		 3552016-06-28 Maciej W. Rozycki <macro@imgtec.com>
356
357 * elf/mips.h (R_MIPS16_PC16_S1): New relocation.
358
7c2c4aa1
TS		 3592016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
360
361 * elf/xtensa.h (xtensa_make_property_section): New prototype.
362
b00f86d0
JB		 3632016-06-24 John Baldwin <jhb@FreeBSD.org>
364
365 * elf/common.h (AT_FREEBSD_EXECPATH, AT_FREEBSD_CANARY)
366 (AT_FREEBSD_CANARYLEN, AT_FREEBSD_OSRELDATE, AT_FREEBSD_NCPUS)
367 (AT_FREEBSD_PAGESIZES, AT_FREEBSD_PAGESIZESLEN)
368 (AT_FREEBSD_TIMEKEEP, AT_FREEBSD_STACKPROT): Define.
369
ce440d63
GM		 3702016-06-23 Graham Markall <graham.markall@embecosm.com>
371
372 * opcode/arc.h: Make insn_class_t alphabetical again.
373
6b477896
TS		 3742016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
375
376 * elf/dlx.h: Wrap in extern C.
377 * elf/xtensa.h: Likewise.
378 * opcode/arc.h: Likewise.
379
6edaf4d7
TS		 3802016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
381
382 * opcode/tilegx.h: Move TILEGX_NUM_PIPELINE_ENCODINGS into
383 tilegx_pipeline.
384
bdd582db
GM		 3852016-06-21 Graham Markall <graham.markall@embecosm.com>
386
387 * opcode/arc.h: Add nps400 extension and instruction
388 subclass.
389 Remove ARC_OPCODE_NPS400
390 * elf/arc.h: Remove E_ARC_MACH_NPS400
391
4f26fb3a
JM		 3922016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
393
394 * opcode/sparc.h (enum sparc_opcode_arch_val): Add
395 SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
396 SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
397 SPARC_OPCODE_ARCH_V9M.
398
99a54ef6
JB		 3992016-06-14 John Baldwin <jhb@FreeBSD.org>
400
401 * opcode/msp430-decode.h (MSP430_Size): Remove.
402 (Msp430_Opcode_Decoded): Change type of size to int.
403
0eaf2e1b
AM		 4042016-06-11 Alan Modra <amodra@gmail.com>
405
406 * coff/sparc.h (COFF_ADJUST_SYM_OUT_POST): Define.
407
337c570c
JM		 4082016-06-08 Jose E. Marchesi <jose.marchesi@oracle.com>
409
410 * opcode/sparc.h: Add missing documentation for hyperprivileged
411 registers in rd (%) and rs1 ($).
412
14b57c7c
AM		 4132016-06-07 Alan Modra <amodra@gmail.com>
414
415 * elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
416 PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
417 PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
418 PPC_APUINFO_VLE: Define.
419
4d1464f2
MW		 4202016-06-07 Matthew Wahab <matthew.wahab@arm.com>
421
422 * opcode/arm.h (ARM_EXT2_RAS): New. Also align preceding
423 entries.
424 (ARM_AEXT_V8_2A): Add ARM_EXT2_RAS.
425
4eb6f892
AB		 4262016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
427
428 * opcode/arc.h (MAX_INSN_ARGS): Increase to 16.
429 (struct arc_long_opcode): New structure.
430 (arc_long_opcodes): Declare.
431 (arc_num_long_opcodes): Declare.
432
1fe0971e
TS		 4332016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
434
435 * elf/mips.h: Add extern "C".
436 * elf/sh.h: Likewise.
437 * opcode/d10v.h: Likewise.
438 * opcode/d30v.h: Likewise.
439 * opcode/ia64.h: Likewise.
440 * opcode/mips.h: Likewise.
441 * opcode/ppc.h: Likewise.
442 * opcode/sparc.h: Likewise.
443 * opcode/tic6x.h: Likewise.
444 * opcode/v850.h: Likewise.
445
1a72702b
AM		 4462016-05-28 Alan Modra <amodra@gmail.com>
447
448 * bfdlink.h (struct bfd_link_callbacks): Update comments.
449 Return void from multiple_definition, multiple_common,
450 add_to_set, constructor, warning, undefined_symbol,
451 reloc_overflow, reloc_dangerous and unattached_reloc.
452
94740f9c
TS		 4532016-05-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
454
455 * opcode/metag.h: wrap declarations in extern "C".
456
d9eca1df
CZ		 4572016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
458
459 * opcode/arc.h (insn_subclass_t): Add COND.
460 (flag_class_t): Add F_CLASS_EXTEND.
461
c810e0b8
CZ		 4622016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
463
464 * opcode/arc.h (struct arc_opcode): Renamed attribute class to
465 insn_class.
466 (struct arc_flag_class): Renamed attribute class to flag_class.
467
3d207518
TS		 4682016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
469
470 * opcode/tic54x.h (struct symbol_): typedef to tic54x_symbol instead of
471 plain symbol.
472
5ff087ac
TT		 4732016-04-29 Tom Tromey <tom@tromey.com>
474
475 * dwarf2.h (enum dwarf_source_language) <DW_LANG_Rust,
476 DW_LANG_Rust_old>: New constants.
477
8f4f9071
MF		 4782016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
479
480 * elf/mips.h (AFL_ASE_DSPR3): New macro.
481 (AFL_ASE_MASK): Update to include AFL_ASE_DSPR3.
482 * opcode/mips.h (ASE_DSPR3): New macro.
483
39d911fc
TP		 4842016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
485 Nick Clifton <nickc@redhat.com>
486
487 * arm.h (enum arm_st_branch_type): Add new ST_BRANCH_ENUM_SIZE
488 enumerator.
489 (NUM_ENUM_ARM_ST_BRANCH_TYPE_BITS): New macro.
490 (ENUM_ARM_ST_BRANCH_TYPE_BITMASK): Likewise.
491 (ARM_SYM_BRANCH_TYPE): Replace by ...
492 (ARM_GET_SYM_BRANCH_TYPE): This and ...
493 (ARM_SET_SYM_BRANCH_TYPE): This in two versions depending on whether
494 BFD_ASSERT is defined or not.
495
15afaa63
TP		 4962016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
497
498 * elf/arm.h (Tag_DSP_extension): Define.
499
d942732e
TP		 5002016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
501
502 * arm.h (ARM_FSET_CPU_SUBSET): Define macro.
503
16a1fa25
TP		 5042016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
505
506 * opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit.
507 (ARM_AEXT2_V8M_MAIN): New architecture extension feature set.
508 (ARM_ARCH_V8M_MAIN): Use ARM_AEXT2_V8M_MAIN instead of ARM_AEXT2_V8M
509 for the high core bits.
510
945e0f82
CZ		 5112016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
512
513 * opcode/arc.h (ARC_SYNTAX_1OP): Declare
514 (ARC_SYNTAX_NOP): Likewsie.
515 (ARC_OP1_MUST_BE_IMM): Update defined value.
516 (ARC_OP1_IMM_IMPLIED): Likewise.
517 (arg_32bit_rc, arg_32bit_u6, arg_32bit_limm): Declare.
518
4bd13cde
NC		 5192016-04-28 Nick Clifton <nickc@redhat.com>
520
521 PR target/19722
522 * opcode/aarch64.h (struct aarch64_opcode): Add verifier field.
523
a6a4679f
AM		 5242016-04-27 Alan Modra <amodra@gmail.com>
525
526 * bfdlink.h (struct bfd_link_hash_entry): Add "section" field to
527 undef. Formatting.
528
4f3b23b3
NC		 5292016-04-21 Nick Clifton <nickc@redhat.com>
530
531 * bfdlink.h: Add prototype for bfd_link_check_relocs.
532
d9689752
L		 5332016-04-20 H.J. Lu <hongjiu.lu@intel.com>
534
535 * bfdlink.h (bfd_link_info): Add check_relocs_after_open_input.
536
52176c67
AB		 5372016-04-20 Andrew Burgess <andrew.burgess@embecosm.com>
538
539 * elf/arc-reloc.def (ARC_NPS_CMEM16): Add ME modifier to formula.
540
537aefaf
AB		 5412016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
542
543 * opcode/arc.h (MAX_INSN_ARGS): Increase 6 to 8.
544
c8f785f2
AB		 5452016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
546
547 * opcode/arc.h (insn_class_t): Add NET and ACL class.
548
4b0c052e
AB		 5492016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
550
551 * elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc.
552 * opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define.
553
f36e33da
CZ		 5542016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
555
556 * opcode/arc.h (flag_class_t): Update.
557 (ARC_OPCODE_NONE): Define.
558 (ARC_OPCODE_ARCALL): Likewise.
559 (ARC_OPCODE_ARCFPX): Likewise.
560 (ARC_REGISTER_READONLY): Likewise.
561 (ARC_REGISTER_WRITEONLY): Likewise.
562 (ARC_REGISTER_NOSHORT_CUT): Likewise.
563 (arc_aux_reg): Add cpu.
564
b99747ae
CZ		 5652016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
566
567 * opcode/arc.h (arc_num_opcodes): Remove.
568 (ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
569 (ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
570 (ARC_SUFFIX_FLAG): Define.
571 (flags_none, flags_f, flags_cc, flags_ccf): Declare.
572 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
573 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
574 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
575 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
576 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
577 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
578 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
579 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
580 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
581
5822016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
583
584 * opcode/arc.h (DPA, DPX, SPX): New subclass enums.
585 (ARC_FPUDA): Define.
586 (arc_aux_reg): Add new field.
587
5882016-04-05 Cupertino Miranda <cmiranda@synopsys.com>
094fb063
CZ		 589
590 * opcode/arc-func.h (replace_bits24): Changed.
591 (replace_bits24_be): Created.
592
f2dd8838
CZ		 5932016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
594
b99747ae
CZ		 595 * opcode/arc.h (insn_subclass_t): Add QUARKSE subclass.
596 (FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP)
597 (INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL)
598 (INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU)
599 (INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS)
600 (INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL)
601 (INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC)
602 (MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC)
603 (MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU)
604 (MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS)
605 (MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL)
606 (MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C)
607 (INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL)
608 (MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
f2dd8838 609
b9bb4a93
TS		 6102016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
611
612 * opcode/i960.h: Add const qualifiers.
613 * opcode/tic4x.h (struct tic4x_inst): Likewise.
614
e23e8ebe
AB		 6152016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
616
617 * opcodes/arc.h (insn_class_t): Add BITOP type.
618
1ae8ab47
AB		 6192016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
620
621 * opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
622 new classes instead.
623
8699fc3e
AB		 6242016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
625
626 * elf/arc.h (E_ARC_MACH_NPS400): Define.
627 * opcode/arc.h (ARC_OPCODE_NPS400): Define.
628
a9522a21
AB		 6292016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
630
631 * elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related comment.
632
c0334580
AB		 6332016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
634
635 * elf/arc.h (EF_ARC_MACH): Delete.
636 (EF_ARC_MACH_MSK): Remove out of date comment.
637
24740d83
AB		 6382016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
639
640 * opcode/arc.h (ARC_OPCODE_BASE): Delete.
641
4c10bbaa
L		 6422016-03-15 H.J. Lu <hongjiu.lu@intel.com>
643
644 PR ld/19807
645 * bfdlink.h (bfd_link_info): Add no_reloc_overflow_check.
646
72f3b6aa
CZ		 6472016-03-08 Cupertino Miranda <Cupertino.Miranda@synopsys.com>
648 Andrew Burgess <andrew.burgess@embecosm.com>
649
650 * elf/arc-reloc.def: Add a call to ME within the formula for each
651 relocation that requires middle-endian correction.
652
f86f5863
TS		 6532016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
654
655 * opcode/dlx.h (struct dlx_opcode): Add const qualifiers.
656 * opcode/h8300.h (struct h8_opcode): Likewise.
657 * opcode/hppa.h (struct pa_opcode): Likewise.
658 * opcode/msp430.h: Likewise.
659 * opcode/spu.h (struct spu_opcode): Likewise.
660 * opcode/tic30.h (struct _register): Likewise.
661 * opcode/tic4x.h (struct tic4x_register): Likewise.
662 (struct tic4x_cond): Likewise.
663 (struct tic4x_indirect): Likewise.
664 (struct tic4x_inst): Likewise.
665 * opcode/visium.h (struct reg_entry): Likewise.
666
643afb90
MW		 6672016-03-04 Matthew Wahab <matthew.wahab@arm.com>
668
669 * arm.h (ARM_ARCH_V8_1A): Add FPU_NEON_EXT_RDMA.
670 (ARM_CPU_HAS_FEATURE): Add comment.
671
3f1f41f5
L		 6722016-03-03 Than McIntosh <thanm@google.com>
673
674 * plugin-api.h: Add new hooks to the plugin transfer vector to
675 to support querying section alignment and section size.
676 (ld_plugin_get_input_section_alignment): New hook.
677 (ld_plugin_get_input_section_size): New hook.
678 (ld_plugin_tag): Add LDPT_GET_INPUT_SECTION_ALIGNMENT
679 and LDPT_GET_INPUT_SECTION_SIZE.
680 (ld_plugin_tv): Add tv_get_input_section_alignment and
681 tv_get_input_section_size.
682
9b738e36 6832016-03-03 Evgenii Stepanov <eugenis@google.com>
95ecdfbf
ES		 684
685 * plugin-api.h (enum ld_plugin_tag): Add LDPT_GET_SYMBOLS_V3.
686
11e5f1ec
L		 6872016-02-26 H.J. Lu <hongjiu.lu@intel.com>
688
689 PR ld/19645
690 * bfdlink.h (bfd_link_elf_stt_common): New enum.
691 (bfd_link_info): Add elf_stt_common.
692
aec6b87e
L		 6932016-02-26 H.J. Lu <hongjiu.lu@intel.com>
694
695 PR ld/19636
696 PR ld/19704
697 PR ld/19719
698 * bfdlink.h (bfd_link_info): Add dynamic_undefined_weak.
699
b8ec4e87
JW		 7002016-02-19 Matthew Wahab <matthew.wahab@arm.com>
701 Jiong Wang <jiong.wang@arm.com>
702
703 * opcode/arm.h (ARM_EXT2_FP16_INSN): New.
704
4670103e
CZ		 7052016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
706 Janek van Oirschot <jvanoirs@synopsys.com>
707
b99747ae
CZ		 708 * opcode/arc.h (arc_opcode arc_relax_opcodes)
709 (arc_num_relax_opcodes): Declare.
4670103e 710
609332f1
NC		 7112016-02-09 Nick Clifton <nickc@redhat.com>
712
713 * opcode/metag.h (metag_scondtab): Mark as possibly unused.
714 * opcode/nds32.h (nds32_r45map): Likewise.
715 (nds32_r54map): Likewise.
716 * opcode/visium.h (gen_reg_table): Likewise.
717 (fp_reg_table, cc_table, opcode_table): Likewise.
718
24f5f69a
AM		 7192016-02-09 Alan Modra <amodra@gmail.com>
720
721 PR 16583
722 * elf/common.h (AT_SUN_HWCAP): Undef before defining.
723
c1d9289f
NC		 7242016-02-04 Nick Clifton <nickc@redhat.com>
725
726 PR target/19561
727 * opcode/msp430.h (IGNORE_CARRY_BIT): New define.
728 (RRUX): Synthesise using case 2 rather than 7.
729
f4ddf30f
JB		 7302016-01-19 John Baldwin <jhb@FreeBSD.org>
731
732 * elf/common.h (NT_FREEBSD_THRMISC): Define.
733 (NT_FREEBSD_PROCSTAT_PROC): Define.
734 (NT_FREEBSD_PROCSTAT_FILES): Define.
735 (NT_FREEBSD_PROCSTAT_VMMAP): Define.
736 (NT_FREEBSD_PROCSTAT_GROUPS): Define.
737 (NT_FREEBSD_PROCSTAT_UMASK): Define.
738 (NT_FREEBSD_PROCSTAT_RLIMIT): Define.
739 (NT_FREEBSD_PROCSTAT_OSREL): Define.
740 (NT_FREEBSD_PROCSTAT_PSSTRINGS): Define.
741 (NT_FREEBSD_PROCSTAT_AUXV): Define.
742
34e967a5
MC		 7432016-01-18 Miranda Cupertino <Cupertino.Miranda@synopsys.com>
744 Zissulescu Claudiu <Claudiu.Zissulescu@synopsys.com>
745
746 * elf/arc-reloc.def (ARC_32, ARC_GOTPC, ARC_TLS_GD_GOT)
747 (ARC_TLS_IE_GOT, ARC_TLS_DTPOFF, ARC_TLS_DTPOFF_S9, ARC_TLS_LE_S9)
748 (ARC_TLS_LE_32): Fixed formula.
749 (ARC_TLS_GD_LD): Use new special function.
750 * opcode/arc-func.h: Changed all the replacement
751 functions to clear the patching bits before doing an or it with the value
752 argument.
753
9ae678af
NC		 7542016-01-18 Nick Clifton <nickc@redhat.com>
755
756 PR ld/19440
757 * coff/internal.h (internal_syment): Use int to hold section
758 number.
759 (N_UNDEF): Cast to int not short.
760 (N_ABS): Likewise.
761 (N_DEBUG): Likewise.
762 (N_TV): Likewise.
763 (P_TV): Likewise.
764
4849dfd8
NC		 7652016-01-11 Nick Clifton <nickc@redhat.com>
766
767 Import this change from GCC mainline:
768
769 2016-01-07 Mike Frysinger <vapier@gentoo.org>
770
771 * longlong.h: Change !__SHMEDIA__ to
772 (!defined (__SHMEDIA__) || !__SHMEDIA__).
773 Change __SHMEDIA__ to defined (__SHMEDIA__) && __SHMEDIA__.
774
b31e4803
MR		 7752016-01-06 Maciej W. Rozycki <macro@imgtec.com>
776
777 * opcode/mips.h: Add a summary of MIPS16 operand codes.
778
b36c1ccb
MF		 7792016-01-05 Mike Frysinger <vapier@gentoo.org>
780
781 * libiberty.h (dupargv): Change arg to char * const *.
782 (writeargv, countargv): Likewise.
783
6f2750fe
AM		 7842016-01-01 Alan Modra <amodra@gmail.com>
785
786 Update year range in copyright notice of all files.
787
3499769a
AM		 788For older changes see ChangeLog-0415, aout/ChangeLog-9115,
789cgen/ChangeLog-0915, coff/ChangeLog-0415, elf/ChangeLog-0415,
790mach-o/ChangeLog-1115, nlm/ChangeLog-9315, opcode/ChangeLog-0415,
791som/ChangeLog-1015, and vms/ChangeLog-1015
792\f
793Copyright (C) 2016 Free Software Foundation, Inc.
794
795Copying and distribution of this file, with or without modification,
796are permitted in any medium without royalty provided the copyright
797notice and this notice are preserved.
798
799Local Variables:
800mode: change-log
801left-margin: 8
802fill-column: 74
803version-control: never
804End:
GDB Binutils - Deliverables
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