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MIPS16: Switch to 32-bit opcode table interpretation
[deliverable/binutils-gdb.git] / include / ChangeLog
CommitLineData
7fd53920
MR		 12016-12-20 Maciej W. Rozycki <macro@imgtec.com>
2
3 * opcode/mips.h (mips_opcode_32bit_p): New inline function.
4
2922d21d
AW		 52016-12-20 Andrew Waterman <andrew@sifive.com>
6
7 * elf/riscv.h (EF_RISCV_SOFT_FLOAT): Don't define.
8 (EF_RISCV_FLOAT_ABI, EF_RISCV_FLOAT_ABI_SOFT): Define.
9 (EF_RISCV_FLOAT_ABI_SINGLE, EF_RISCV_FLOAT_ABI_DOUBLE): Define.
10 (EF_RISCV_FLOAT_ABI_QUAD): Define.
11
45f76423
AW		 122016-12-20 Andrew Waterman <andrew@sifive.com>
13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
14
15 * elf/riscv.h: Add R_RISCV_TPREL_I through R_RISCV_SET32.
16
22185505 172016-12-16 fincs <fincs.alt1@gmail.com>
18
19 * bfdlink.h (struct bfd_link_info): Add gc_keep_exported.
20
5e7fc731
MR		 212016-12-14 Maciej W. Rozycki <macro@imgtec.com>
22
23 * elf/mips.h (Elf_Internal_ABIFlags_v0): Also declare struct
24 typedef as `elf_internal_abiflags_v0'.
25
a6a51754
RL		 262016-12-13 Renlin Li <renlin.li@arm.com>
27
28 * opcode/aarch64.h (aarch64_operand_class): Remove
29 AARCH64_OPND_CLASS_CP_REG.
30 (enum aarch64_opnd): Change AARCH64_OPND_Cn to AARCH64_OPND_CRn,
31 AARCH64_OPND_Cm to AARCH64_OPND_CRm.
32 (aarch64_opnd_qualifier): Define AARCH64_OPND_QLF_CR qualifier.
33
64c11183
MR		 342016-12-09 Maciej W. Rozycki <macro@imgtec.com>
35
36 * opcode/mips.h: Remove references to `>' operand code.
37
4b078115
MR		 382016-12-07 Maciej W. Rozycki <macro@imgtec.com>
39
40 * opcode/mips.h (INSN_CHIP_MASK): Update according to bit use.
41
b8760d2c
MR		 422016-12-07 Maciej W. Rozycki <macro@imgtec.com>
43
44 * opcode/mips.h (ASE_DSPR3): Add a comment.
45
a12fd8e1
SN		 462016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
47
48 * opcode/arm.h (ARM_EXT2_V8_3A, ARM_AEXT2_V8_3A): New.
49 (ARM_ARCH_V8_3A): New.
50
abe7c33b
CZ		 512016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
52
53 * opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE
54 instruction classes.
55
6884417a
JM		 562016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
57
58 * opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
59 hwcaps2.
60
08dc996f
AM		 612016-11-22 Alan Modra <amodra@gmail.com>
62
63 PR 20744
64 * opcode/ppc.h: Define VLE insns using 16A and 16D relocs.
65
535aade6
DT		 662016-11-03 David Tolnay <dtolnay@gmail.com>
67 Mark Wielaard <mark@klomp.org>
68
69 * demangle.h (DMGL_RUST): New macro.
70 (DMGL_STYLE_MASK): Add DMGL_RUST.
71 (demangling_styles): Add dlang_rust.
72 (RUST_DEMANGLING_STYLE_STRING): New macro.
73 (RUST_DEMANGLING): New macro.
74 (rust_demangle): New prototype.
75 (rust_is_mangled): Likewise.
76 (rust_demangle_sym): Likewise.
77
a4ddf8dc
JM		 782016-11-07 Jason Merrill <jason@redhat.com>
79
80 * demangle.h (enum demangle_component_type): Add
81 DEMANGLE_COMPONENT_NOEXCEPT, DEMANGLE_COMPONENT_THROW_SPEC.
82
c2c4ff8d
SN		 832016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
84
85 * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1,
86 AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3.
87 (enum aarch64_op): Add OP_FCMLA_ELEM.
88
3f06e550
SN		 892016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
90
91 * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM10.
92 (enum aarch64_insn_class): Add ldst_imm10.
93
c84364ec
SN		 942016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
95
96 * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rm_SP.
97
1924ff75
SN		 982016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
99
100 * opcode/aarch64.h (AARCH64_FEATURE_V8_3): Define.
101 (AARCH64_ARCH_V8_3): Define.
102 (AARCH64_ARCH_V8_1, AARCH64_ARCH_V8_2): Simplify.
103
d46a2165
TP		 1042016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
105
106 * opcode/arm.h (ARM_AEXT_V8M_MAIN_DSP): Define.
107 (ARM_AEXT2_V8M_MAIN_DSP): Likewise.
108 (ARM_ARCH_V8M_MAIN_DSP): Likewise.
109
5a736821
GM		 1102016-11-03 Graham Markall <graham.markall@embecosm.com>
111
112 * opcode/arc.h: Add PROTOCOL_DECODE to insn_class_t.
113
bdfe53e3
AB		 1142016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
115
116 * opcode/arc.h (struct arc_opcode): Change type of opcode and mask
117 fields.
118 (struct arc_long_opcode): Delete.
119 (struct arc_operand): Change types for insert and extract
120 handlers.
121
2e272202
GM		 1222016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
123
124 * opcode/arc.h: Make macros 64-bit safe.
125
06fe285f
GM		 1262016-11-03 Graham Markall <graham.markall@embecosm.com>
127
128 * opcode/arc.h (arc_opcode_len): Declare.
129 (ARC_SHORT): Delete.
130
e23eba97
NC		 1312016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
132 Andrew Waterman <andrew@sifive.com>
133
134 Add support for RISC-V architecture.
135 * dis-asm.h: Add prototypes for print_insn_riscv and
136 print_riscv_disassembler_options.
137 * elf/riscv.h: New file.
138 * opcode/riscv-opc.h: New file.
139 * opcode/riscv.h: New file.
140
6d913794
NC		 1412016-10-17 Nick Clifton <nickc@redhat.com>
142
143 * elf/common.h (DT_SYMTAB_SHNDX): Define.
144 (EM_CLOUDSHIELD, EM_COREA_1ST, EM_COREA_2ND, EM_OPEN8): Define.
145 (EM_VIDEOCORE5, EM_56800EX, EM_BA1, EM_BA2, EM_XCORE): Define.
146 (EM_MCHP_PIC, EM_KM32, EM_KMX32, EM_KMX16, EM_KMX8): Define.
147 (EM_KVARC, EM_CDP, EM_COGE, EM_COOL, EM_NORC): Define.
148 (EM_CSR_KALIMBA, EM_Z80, EM_AMDGPU, EM_RISCV): Define.
149 (ELFOSABI_OPENVOS): Define.
150 (GRP_MASKOS, GRP_MASKPROC): Define.
151
b4f6af8e
PA		 1522016-10-14 Pedro Alves <palves@redhat.com>
153
154 * ansidecl.h [__cplusplus >= 201103 && GCC_VERSION < 4007] (FINAL,
155 OVERRIDE): Define as empty.
156 [__cplusplus < 201103 && GCC_VERSION < 4007] (FINAL): Define as
157 __final.
158 [__cplusplus < 201103 && GCC_VERSION >= 4007] (OVERRIDE): Define as
159 empty.
160
d118ee37
PA		 1612016-10-14 Pedro Alves <palves@redhat.com>
162
163 * ansidecl.h (GCC_FINAL): Delete.
164 (OVERRIDE, FINAL): New, moved from gcc/coretypes.h.
165
e5b06ef0
CZ		 1662016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
167
168 * opcode/arc.h (ARC_OPCODE_ARCV2): New define.
169
a5721ba2
AM		 1702016-09-29 Alan Modra <amodra@gmail.com>
171
172 * opcode/ppc.h (PPC_OPERAND_OPTIONAL32): Define.
173
2b848ebd
CZ		 1742016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
175
176 * opcode/arc.h (insn_class_t): Add two new classes.
177
005d79fd
AM		 1782016-09-26 Alan Modra <amodra@gmail.com>
179
180 * elf/ppc.h (Tag_GNU_Power_ABI_FP): Comment on new values.
181
bb7eff52
RS		 1822016-09-21 Richard Sandiford <richard.sandiford@arm.com>
183
184 * opcode/aarch64.h (aarch64_cond): Bump array size to 4.
185
c0890d26
RS		 1862016-09-21 Richard Sandiford <richard.sandiford@arm.com>
187
188 * opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro.
189 (OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi)
190 (OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P)
191 (OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops.
192
116b6019
RS		 1932016-09-21 Richard Sandiford <richard.sandiford@arm.com>
194
195 * opcode/aarch64.h (sve_cpy, sve_index, sve_limm, sve_misc)
196 (sve_movprfx, sve_pred_zm, sve_shift_pred, sve_shift_unpred)
197 (sve_size_bhs, sve_size_bhsd, sve_size_hsd, sve_size_sd): New
198 aarch64_insn_classes.
199
047cd301
RS		 2002016-09-21 Richard Sandiford <richard.sandiford@arm.com>
201
202 * opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd.
203 (AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd)
204 (AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise.
205
165d4950
RS		 2062016-09-21 Richard Sandiford <richard.sandiford@arm.com>
207
208 * opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd.
209 (AARCH64_OPND_SVE_I1_HALF_ONE, AARCH64_OPND_SVE_I1_HALF_TWO)
210 (AARCH64_OPND_SVE_I1_ZERO_ONE): Likewise.
211
e950b345
RS		 2122016-09-21 Richard Sandiford <richard.sandiford@arm.com>
213
214 * opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
215 (AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
216 (AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
217 (AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
218 (AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
219 (AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
220 (AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
221 (AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
222 (AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
223 (AARCH64_OPND_SVE_UIMM8_53): Likewise.
224 (aarch64_sve_dupm_mov_immediate_p): Declare.
225
98907a70
RS		 2262016-09-21 Richard Sandiford <richard.sandiford@arm.com>
227
228 * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd.
229 (AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL)
230 (AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL)
231 (AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise.
232 (AARCH64_MOD_MUL_VL): New aarch64_modifier_kind.
233
4df068de
RS		 2342016-09-21 Richard Sandiford <richard.sandiford@arm.com>
235
236 * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
237 (AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
238 (AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
239 (AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
240 (AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
241 (AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
242 (AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
243 (AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
244 (AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
245 (AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
246 (AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
247 (AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
248 (AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
249 (AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
250 (AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
251 (AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
252 Likewise.
253
2442d846
RS		 2542016-09-21 Richard Sandiford <richard.sandiford@arm.com>
255
256 * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New
257 aarch64_opnd.
258 (AARCH64_MOD_MUL): New aarch64_modifier_kind.
259 (aarch64_opnd_info): Make shifter.amount an int64_t and
260 rearrange the fields.
261
245d2e3f
RS		 2622016-09-21 Richard Sandiford <richard.sandiford@arm.com>
263
264 * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN): New aarch64_opnd.
265 (AARCH64_OPND_SVE_PRFOP): Likewise.
266 (aarch64_sve_pattern_array): Declare.
267 (aarch64_sve_prfop_array): Likewise.
268
d50c751e
RS		 2692016-09-21 Richard Sandiford <richard.sandiford@arm.com>
270
271 * opcode/aarch64.h (AARCH64_OPND_QLF_P_Z): New aarch64_opnd_qualifier.
272 (AARCH64_OPND_QLF_P_M): Likewise.
273
f11ad6bc
RS		 2742016-09-21 Richard Sandiford <richard.sandiford@arm.com>
275
276 * opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
277 aarch64_operand_class.
278 (AARCH64_OPND_CLASS_PRED_REG): Likewise.
279 (AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
280 (AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
281 (AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
282 (AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
283 (AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
284 (AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
285 (AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
286
0c608d6b
RS		 2872016-09-21 Richard Sandiford <richard.sandiford@arm.com>
288
289 * opcode/aarch64.h (aarch64_opcode): Add a tied_operand field.
290 (AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind.
291
4989adac
RS		 2922016-09-21 Richard Sandiford <richard.sandiford@arm.com>
293
294 * opcode/aarch64.h (F_STRICT): New flag.
295
27e5a270
RE		 2962016-09-07 Richard Earnshaw <rearnsha@arm.com>
297
298 * opcode/arm.h (ARM_ARCH_V8A_CRC): New architecture.
299
a87aa054
CM		 3002016-08-26 Cupertino Miranda <cmiranda@synopsys.com>
301 * elf/arc-reloc.def: Fixed relocation formula for N*, SDA, SDA_12,
302 SDA_16_LD*, S13_PCREL, N32_ME, SECTOFF_* relocations.
303 * opcode/arc-func.h (replace_disp12s): Added. Used for SDA_12
304 relocation.
305
4ba2ef8f
TP		 3062016-08-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
307
308 * arm.h (ARM_GET_SYM_CMSE_SPCL): Define macro.
309 (ARM_SET_SYM_CMSE_SPCL): Likewise.
310
dfdaec14
AJ		 3112016-08-01 Andrew Jenner <andrew@codesourcery.com>
312
313 * opcode/ppc.h (PPC_OPCODE_E200Z4): New define.
314
fa3fcee7
NC		 3152016-07-29 Aldy Hernandez <aldyh@redhat.com>
316
317 * libiberty.h (MAX_ALLOCA_SIZE): New macro.
318
db18dbab
GM		 3192016-07-27 Graham Markall <graham.markall@embecosm.com>
320
321 * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE,
322 ARC_OPERAND_COLON. Add the arc_nps_address_type enum and
323 ARC_NUM_ADDRTYPES.
324 * opcode/arc.h: Add BMU to insn_class_t enum.
325 * opcode/arc.h: Add PMU to insn_class_t enum.
326
37fd5ef3
CZ		 3272016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
328
329 * dis-asm.h: Declare print_arc_disassembler_options.
330
76359541
TP		 3312016-07-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
332
333 * bfdlink.h (struct bfd_link_info): Declare new ldscript_def and
334 out_implib_bfd fields.
335
fa1c0170
CZ		 3362016-07-14 Claudiu Zissulescu <claziss@synopsys.com>
337
338 * elf/arc-reloc.def (ARC_SDA32): Don't use ME transformation.
339
f0728ee3
AV		 3402016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com>
341
342 * include/elf/arm.h (SHF_ARM_NOREAD): Rename to ...
343 (SHF_ARM_PURECODE): ... this.
344
93d8990c
SN		 3452016-07-01 Szabolcs Nagy <szabolcs.nagy@arm.com>
346
347 * opcode/aarch64.h (AARCH64_CPU_HAS_ALL_FEATURES): New.
348 (AARCH64_CPU_HAS_ANY_FEATURES): New.
349 (AARCH64_CPU_HAS_FEATURE): Define as AARCH64_CPU_HAS_ALL_FEATURES.
350 (AARCH64_OPCODE_HAS_FEATURE): Remove.
351
534dbe46
MW		 3522016-06-30 Matthew Wahab <matthew.wahab@arm.com>
353
354 * opcode/arm.h (ARM_ARCH_V8_2a): Add FPU_NEON_EXT_RDMA to the set
355 of enabled FPU features.
356
042c94de
TS		 3572016-06-29 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
358
359 * opcode/sparc.h (enum sparc_opcode_arch_val): Move
360 SPARC_OPCODE_ARCH_MAX into the enum.
361
dab26bf4
RS		 3622016-06-28 Richard Sandiford <richard.sandiford@arm.com>
363
364 * opcode/aarch64.h (aarch64_opnd_info): Change index fields to int64_t.
365
c9775dde
MR		 3662016-06-28 Maciej W. Rozycki <macro@imgtec.com>
367
368 * elf/mips.h (R_MIPS16_PC16_S1): New relocation.
369
7c2c4aa1
TS		 3702016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
371
372 * elf/xtensa.h (xtensa_make_property_section): New prototype.
373
b00f86d0
JB		 3742016-06-24 John Baldwin <jhb@FreeBSD.org>
375
376 * elf/common.h (AT_FREEBSD_EXECPATH, AT_FREEBSD_CANARY)
377 (AT_FREEBSD_CANARYLEN, AT_FREEBSD_OSRELDATE, AT_FREEBSD_NCPUS)
378 (AT_FREEBSD_PAGESIZES, AT_FREEBSD_PAGESIZESLEN)
379 (AT_FREEBSD_TIMEKEEP, AT_FREEBSD_STACKPROT): Define.
380
ce440d63
GM		 3812016-06-23 Graham Markall <graham.markall@embecosm.com>
382
383 * opcode/arc.h: Make insn_class_t alphabetical again.
384
6b477896
TS		 3852016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
386
387 * elf/dlx.h: Wrap in extern C.
388 * elf/xtensa.h: Likewise.
389 * opcode/arc.h: Likewise.
390
6edaf4d7
TS		 3912016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
392
393 * opcode/tilegx.h: Move TILEGX_NUM_PIPELINE_ENCODINGS into
394 tilegx_pipeline.
395
bdd582db
GM		 3962016-06-21 Graham Markall <graham.markall@embecosm.com>
397
398 * opcode/arc.h: Add nps400 extension and instruction
399 subclass.
400 Remove ARC_OPCODE_NPS400
401 * elf/arc.h: Remove E_ARC_MACH_NPS400
402
4f26fb3a
JM		 4032016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
404
405 * opcode/sparc.h (enum sparc_opcode_arch_val): Add
406 SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
407 SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
408 SPARC_OPCODE_ARCH_V9M.
409
99a54ef6
JB		 4102016-06-14 John Baldwin <jhb@FreeBSD.org>
411
412 * opcode/msp430-decode.h (MSP430_Size): Remove.
413 (Msp430_Opcode_Decoded): Change type of size to int.
414
0eaf2e1b
AM		 4152016-06-11 Alan Modra <amodra@gmail.com>
416
417 * coff/sparc.h (COFF_ADJUST_SYM_OUT_POST): Define.
418
337c570c
JM		 4192016-06-08 Jose E. Marchesi <jose.marchesi@oracle.com>
420
421 * opcode/sparc.h: Add missing documentation for hyperprivileged
422 registers in rd (%) and rs1 ($).
423
14b57c7c
AM		 4242016-06-07 Alan Modra <amodra@gmail.com>
425
426 * elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
427 PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
428 PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
429 PPC_APUINFO_VLE: Define.
430
4d1464f2
MW		 4312016-06-07 Matthew Wahab <matthew.wahab@arm.com>
432
433 * opcode/arm.h (ARM_EXT2_RAS): New. Also align preceding
434 entries.
435 (ARM_AEXT_V8_2A): Add ARM_EXT2_RAS.
436
4eb6f892
AB		 4372016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
438
439 * opcode/arc.h (MAX_INSN_ARGS): Increase to 16.
440 (struct arc_long_opcode): New structure.
441 (arc_long_opcodes): Declare.
442 (arc_num_long_opcodes): Declare.
443
1fe0971e
TS		 4442016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
445
446 * elf/mips.h: Add extern "C".
447 * elf/sh.h: Likewise.
448 * opcode/d10v.h: Likewise.
449 * opcode/d30v.h: Likewise.
450 * opcode/ia64.h: Likewise.
451 * opcode/mips.h: Likewise.
452 * opcode/ppc.h: Likewise.
453 * opcode/sparc.h: Likewise.
454 * opcode/tic6x.h: Likewise.
455 * opcode/v850.h: Likewise.
456
1a72702b
AM		 4572016-05-28 Alan Modra <amodra@gmail.com>
458
459 * bfdlink.h (struct bfd_link_callbacks): Update comments.
460 Return void from multiple_definition, multiple_common,
461 add_to_set, constructor, warning, undefined_symbol,
462 reloc_overflow, reloc_dangerous and unattached_reloc.
463
94740f9c
TS		 4642016-05-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
465
466 * opcode/metag.h: wrap declarations in extern "C".
467
d9eca1df
CZ		 4682016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
469
470 * opcode/arc.h (insn_subclass_t): Add COND.
471 (flag_class_t): Add F_CLASS_EXTEND.
472
c810e0b8
CZ		 4732016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
474
475 * opcode/arc.h (struct arc_opcode): Renamed attribute class to
476 insn_class.
477 (struct arc_flag_class): Renamed attribute class to flag_class.
478
3d207518
TS		 4792016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
480
481 * opcode/tic54x.h (struct symbol_): typedef to tic54x_symbol instead of
482 plain symbol.
483
5ff087ac
TT		 4842016-04-29 Tom Tromey <tom@tromey.com>
485
486 * dwarf2.h (enum dwarf_source_language) <DW_LANG_Rust,
487 DW_LANG_Rust_old>: New constants.
488
8f4f9071
MF		 4892016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
490
491 * elf/mips.h (AFL_ASE_DSPR3): New macro.
492 (AFL_ASE_MASK): Update to include AFL_ASE_DSPR3.
493 * opcode/mips.h (ASE_DSPR3): New macro.
494
39d911fc
TP		 4952016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
496 Nick Clifton <nickc@redhat.com>
497
498 * arm.h (enum arm_st_branch_type): Add new ST_BRANCH_ENUM_SIZE
499 enumerator.
500 (NUM_ENUM_ARM_ST_BRANCH_TYPE_BITS): New macro.
501 (ENUM_ARM_ST_BRANCH_TYPE_BITMASK): Likewise.
502 (ARM_SYM_BRANCH_TYPE): Replace by ...
503 (ARM_GET_SYM_BRANCH_TYPE): This and ...
504 (ARM_SET_SYM_BRANCH_TYPE): This in two versions depending on whether
505 BFD_ASSERT is defined or not.
506
15afaa63
TP		 5072016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
508
509 * elf/arm.h (Tag_DSP_extension): Define.
510
d942732e
TP		 5112016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
512
513 * arm.h (ARM_FSET_CPU_SUBSET): Define macro.
514
16a1fa25
TP		 5152016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
516
517 * opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit.
518 (ARM_AEXT2_V8M_MAIN): New architecture extension feature set.
519 (ARM_ARCH_V8M_MAIN): Use ARM_AEXT2_V8M_MAIN instead of ARM_AEXT2_V8M
520 for the high core bits.
521
945e0f82
CZ		 5222016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
523
524 * opcode/arc.h (ARC_SYNTAX_1OP): Declare
525 (ARC_SYNTAX_NOP): Likewsie.
526 (ARC_OP1_MUST_BE_IMM): Update defined value.
527 (ARC_OP1_IMM_IMPLIED): Likewise.
528 (arg_32bit_rc, arg_32bit_u6, arg_32bit_limm): Declare.
529
4bd13cde
NC		 5302016-04-28 Nick Clifton <nickc@redhat.com>
531
532 PR target/19722
533 * opcode/aarch64.h (struct aarch64_opcode): Add verifier field.
534
a6a4679f
AM		 5352016-04-27 Alan Modra <amodra@gmail.com>
536
537 * bfdlink.h (struct bfd_link_hash_entry): Add "section" field to
538 undef. Formatting.
539
4f3b23b3
NC		 5402016-04-21 Nick Clifton <nickc@redhat.com>
541
542 * bfdlink.h: Add prototype for bfd_link_check_relocs.
543
d9689752
L		 5442016-04-20 H.J. Lu <hongjiu.lu@intel.com>
545
546 * bfdlink.h (bfd_link_info): Add check_relocs_after_open_input.
547
52176c67
AB		 5482016-04-20 Andrew Burgess <andrew.burgess@embecosm.com>
549
550 * elf/arc-reloc.def (ARC_NPS_CMEM16): Add ME modifier to formula.
551
537aefaf
AB		 5522016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
553
554 * opcode/arc.h (MAX_INSN_ARGS): Increase 6 to 8.
555
c8f785f2
AB		 5562016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
557
558 * opcode/arc.h (insn_class_t): Add NET and ACL class.
559
4b0c052e
AB		 5602016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
561
562 * elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc.
563 * opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define.
564
f36e33da
CZ		 5652016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
566
567 * opcode/arc.h (flag_class_t): Update.
568 (ARC_OPCODE_NONE): Define.
569 (ARC_OPCODE_ARCALL): Likewise.
570 (ARC_OPCODE_ARCFPX): Likewise.
571 (ARC_REGISTER_READONLY): Likewise.
572 (ARC_REGISTER_WRITEONLY): Likewise.
573 (ARC_REGISTER_NOSHORT_CUT): Likewise.
574 (arc_aux_reg): Add cpu.
575
b99747ae
CZ		 5762016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
577
578 * opcode/arc.h (arc_num_opcodes): Remove.
579 (ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
580 (ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
581 (ARC_SUFFIX_FLAG): Define.
582 (flags_none, flags_f, flags_cc, flags_ccf): Declare.
583 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
584 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
585 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
586 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
587 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
588 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
589 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
590 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
591 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
592
5932016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
594
595 * opcode/arc.h (DPA, DPX, SPX): New subclass enums.
596 (ARC_FPUDA): Define.
597 (arc_aux_reg): Add new field.
598
5992016-04-05 Cupertino Miranda <cmiranda@synopsys.com>
094fb063
CZ		 600
601 * opcode/arc-func.h (replace_bits24): Changed.
602 (replace_bits24_be): Created.
603
f2dd8838
CZ		 6042016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
605
b99747ae
CZ		 606 * opcode/arc.h (insn_subclass_t): Add QUARKSE subclass.
607 (FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP)
608 (INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL)
609 (INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU)
610 (INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS)
611 (INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL)
612 (INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC)
613 (MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC)
614 (MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU)
615 (MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS)
616 (MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL)
617 (MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C)
618 (INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL)
619 (MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
f2dd8838 620
b9bb4a93
TS		 6212016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
622
623 * opcode/i960.h: Add const qualifiers.
624 * opcode/tic4x.h (struct tic4x_inst): Likewise.
625
e23e8ebe
AB		 6262016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
627
628 * opcodes/arc.h (insn_class_t): Add BITOP type.
629
1ae8ab47
AB		 6302016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
631
632 * opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
633 new classes instead.
634
8699fc3e
AB		 6352016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
636
637 * elf/arc.h (E_ARC_MACH_NPS400): Define.
638 * opcode/arc.h (ARC_OPCODE_NPS400): Define.
639
a9522a21
AB		 6402016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
641
642 * elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related comment.
643
c0334580
AB		 6442016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
645
646 * elf/arc.h (EF_ARC_MACH): Delete.
647 (EF_ARC_MACH_MSK): Remove out of date comment.
648
24740d83
AB		 6492016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
650
651 * opcode/arc.h (ARC_OPCODE_BASE): Delete.
652
4c10bbaa
L		 6532016-03-15 H.J. Lu <hongjiu.lu@intel.com>
654
655 PR ld/19807
656 * bfdlink.h (bfd_link_info): Add no_reloc_overflow_check.
657
72f3b6aa
CZ		 6582016-03-08 Cupertino Miranda <Cupertino.Miranda@synopsys.com>
659 Andrew Burgess <andrew.burgess@embecosm.com>
660
661 * elf/arc-reloc.def: Add a call to ME within the formula for each
662 relocation that requires middle-endian correction.
663
f86f5863
TS		 6642016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
665
666 * opcode/dlx.h (struct dlx_opcode): Add const qualifiers.
667 * opcode/h8300.h (struct h8_opcode): Likewise.
668 * opcode/hppa.h (struct pa_opcode): Likewise.
669 * opcode/msp430.h: Likewise.
670 * opcode/spu.h (struct spu_opcode): Likewise.
671 * opcode/tic30.h (struct _register): Likewise.
672 * opcode/tic4x.h (struct tic4x_register): Likewise.
673 (struct tic4x_cond): Likewise.
674 (struct tic4x_indirect): Likewise.
675 (struct tic4x_inst): Likewise.
676 * opcode/visium.h (struct reg_entry): Likewise.
677
643afb90
MW		 6782016-03-04 Matthew Wahab <matthew.wahab@arm.com>
679
680 * arm.h (ARM_ARCH_V8_1A): Add FPU_NEON_EXT_RDMA.
681 (ARM_CPU_HAS_FEATURE): Add comment.
682
3f1f41f5
L		 6832016-03-03 Than McIntosh <thanm@google.com>
684
685 * plugin-api.h: Add new hooks to the plugin transfer vector to
686 to support querying section alignment and section size.
687 (ld_plugin_get_input_section_alignment): New hook.
688 (ld_plugin_get_input_section_size): New hook.
689 (ld_plugin_tag): Add LDPT_GET_INPUT_SECTION_ALIGNMENT
690 and LDPT_GET_INPUT_SECTION_SIZE.
691 (ld_plugin_tv): Add tv_get_input_section_alignment and
692 tv_get_input_section_size.
693
9b738e36 6942016-03-03 Evgenii Stepanov <eugenis@google.com>
95ecdfbf
ES		 695
696 * plugin-api.h (enum ld_plugin_tag): Add LDPT_GET_SYMBOLS_V3.
697
11e5f1ec
L		 6982016-02-26 H.J. Lu <hongjiu.lu@intel.com>
699
700 PR ld/19645
701 * bfdlink.h (bfd_link_elf_stt_common): New enum.
702 (bfd_link_info): Add elf_stt_common.
703
aec6b87e
L		 7042016-02-26 H.J. Lu <hongjiu.lu@intel.com>
705
706 PR ld/19636
707 PR ld/19704
708 PR ld/19719
709 * bfdlink.h (bfd_link_info): Add dynamic_undefined_weak.
710
b8ec4e87
JW		 7112016-02-19 Matthew Wahab <matthew.wahab@arm.com>
712 Jiong Wang <jiong.wang@arm.com>
713
714 * opcode/arm.h (ARM_EXT2_FP16_INSN): New.
715
4670103e
CZ		 7162016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
717 Janek van Oirschot <jvanoirs@synopsys.com>
718
b99747ae
CZ		 719 * opcode/arc.h (arc_opcode arc_relax_opcodes)
720 (arc_num_relax_opcodes): Declare.
4670103e 721
609332f1
NC		 7222016-02-09 Nick Clifton <nickc@redhat.com>
723
724 * opcode/metag.h (metag_scondtab): Mark as possibly unused.
725 * opcode/nds32.h (nds32_r45map): Likewise.
726 (nds32_r54map): Likewise.
727 * opcode/visium.h (gen_reg_table): Likewise.
728 (fp_reg_table, cc_table, opcode_table): Likewise.
729
24f5f69a
AM		 7302016-02-09 Alan Modra <amodra@gmail.com>
731
732 PR 16583
733 * elf/common.h (AT_SUN_HWCAP): Undef before defining.
734
c1d9289f
NC		 7352016-02-04 Nick Clifton <nickc@redhat.com>
736
737 PR target/19561
738 * opcode/msp430.h (IGNORE_CARRY_BIT): New define.
739 (RRUX): Synthesise using case 2 rather than 7.
740
f4ddf30f
JB		 7412016-01-19 John Baldwin <jhb@FreeBSD.org>
742
743 * elf/common.h (NT_FREEBSD_THRMISC): Define.
744 (NT_FREEBSD_PROCSTAT_PROC): Define.
745 (NT_FREEBSD_PROCSTAT_FILES): Define.
746 (NT_FREEBSD_PROCSTAT_VMMAP): Define.
747 (NT_FREEBSD_PROCSTAT_GROUPS): Define.
748 (NT_FREEBSD_PROCSTAT_UMASK): Define.
749 (NT_FREEBSD_PROCSTAT_RLIMIT): Define.
750 (NT_FREEBSD_PROCSTAT_OSREL): Define.
751 (NT_FREEBSD_PROCSTAT_PSSTRINGS): Define.
752 (NT_FREEBSD_PROCSTAT_AUXV): Define.
753
34e967a5
MC		 7542016-01-18 Miranda Cupertino <Cupertino.Miranda@synopsys.com>
755 Zissulescu Claudiu <Claudiu.Zissulescu@synopsys.com>
756
757 * elf/arc-reloc.def (ARC_32, ARC_GOTPC, ARC_TLS_GD_GOT)
758 (ARC_TLS_IE_GOT, ARC_TLS_DTPOFF, ARC_TLS_DTPOFF_S9, ARC_TLS_LE_S9)
759 (ARC_TLS_LE_32): Fixed formula.
760 (ARC_TLS_GD_LD): Use new special function.
761 * opcode/arc-func.h: Changed all the replacement
762 functions to clear the patching bits before doing an or it with the value
763 argument.
764
9ae678af
NC		 7652016-01-18 Nick Clifton <nickc@redhat.com>
766
767 PR ld/19440
768 * coff/internal.h (internal_syment): Use int to hold section
769 number.
770 (N_UNDEF): Cast to int not short.
771 (N_ABS): Likewise.
772 (N_DEBUG): Likewise.
773 (N_TV): Likewise.
774 (P_TV): Likewise.
775
4849dfd8
NC		 7762016-01-11 Nick Clifton <nickc@redhat.com>
777
778 Import this change from GCC mainline:
779
780 2016-01-07 Mike Frysinger <vapier@gentoo.org>
781
782 * longlong.h: Change !__SHMEDIA__ to
783 (!defined (__SHMEDIA__) || !__SHMEDIA__).
784 Change __SHMEDIA__ to defined (__SHMEDIA__) && __SHMEDIA__.
785
b31e4803
MR		 7862016-01-06 Maciej W. Rozycki <macro@imgtec.com>
787
788 * opcode/mips.h: Add a summary of MIPS16 operand codes.
789
b36c1ccb
MF		 7902016-01-05 Mike Frysinger <vapier@gentoo.org>
791
792 * libiberty.h (dupargv): Change arg to char * const *.
793 (writeargv, countargv): Likewise.
794
6f2750fe
AM		 7952016-01-01 Alan Modra <amodra@gmail.com>
796
797 Update year range in copyright notice of all files.
798
3499769a
AM		 799For older changes see ChangeLog-0415, aout/ChangeLog-9115,
800cgen/ChangeLog-0915, coff/ChangeLog-0415, elf/ChangeLog-0415,
801mach-o/ChangeLog-1115, nlm/ChangeLog-9315, opcode/ChangeLog-0415,
802som/ChangeLog-1015, and vms/ChangeLog-1015
803\f
804Copyright (C) 2016 Free Software Foundation, Inc.
805
806Copying and distribution of this file, with or without modification,
807are permitted in any medium without royalty provided the copyright
808notice and this notice are preserved.
809
810Local Variables:
811mode: change-log
812left-margin: 8
813fill-column: 74
814version-control: never
815End:
GDB Binutils - Deliverables
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