[deliverable/linux.git] / include / asm-alpha / core_mcpcia.h

#ifndef __ALPHA_MCPCIA__H__
#define __ALPHA_MCPCIA__H__

/* Define to experiment with fitting everything into one 128MB HAE window.
   One window per bus, that is.  */
#define MCPCIA_ONE_HAE_WINDOW 1

#include <linux/types.h>
#include <linux/pci.h>
#include <asm/compiler.h>

/*
 * MCPCIA is the internal name for a core logic chipset which provides
 * PCI access for the RAWHIDE family of systems.
 *
 * This file is based on:
 *
 * RAWHIDE System Programmer's Manual
 * 16-May-96
 * Rev. 1.4
 *
 */

/*------------------------------------------------------------------------**
**                                                                        **
**  I/O procedures                                                        **
**                                                                        **
**      inport[b|w|t|l], outport[b|w|t|l] 8:16:24:32 IO xfers             **
**	inportbxt: 8 bits only                                            **
**      inport:    alias of inportw                                       **
**      outport:   alias of outportw                                      **
**                                                                        **
**      inmem[b|w|t|l], outmem[b|w|t|l] 8:16:24:32 ISA memory xfers       **
**	inmembxt: 8 bits only                                             **
**      inmem:    alias of inmemw                                         **
**      outmem:   alias of outmemw                                        **
**                                                                        **
**------------------------------------------------------------------------*/


/* MCPCIA ADDRESS BIT DEFINITIONS
 *
 *  3333 3333 3322 2222 2222 1111 1111 11
 *  9876 5432 1098 7654 3210 9876 5432 1098 7654 3210
 *  ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
 *  1                                             000
 *  ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
 *  |                                             |\|
 *  |                               Byte Enable --+ |
 *  |                             Transfer Length --+
 *  +-- IO space, not cached
 *
 *   Byte      Transfer
 *   Enable    Length    Transfer  Byte    Address
 *   adr<6:5>  adr<4:3>  Length    Enable  Adder
 *   ---------------------------------------------
 *      00        00      Byte      1110   0x000
 *      01        00      Byte      1101   0x020
 *      10        00      Byte      1011   0x040
 *      11        00      Byte      0111   0x060
 *
 *      00        01      Word      1100   0x008
 *      01        01      Word      1001   0x028 <= Not supported in this code.
 *      10        01      Word      0011   0x048
 *
 *      00        10      Tribyte   1000   0x010
 *      01        10      Tribyte   0001   0x030
 *
 *      10        11      Longword  0000   0x058
 *
 *      Note that byte enables are asserted low.
 *
 */

#define MCPCIA_MAX_HOSES 4

#define MCPCIA_MID(m)		((unsigned long)(m) << 33)

/* Dodge has PCI0 and PCI1 at MID 4 and 5 respectively. 
   Durango adds PCI2 and PCI3 at MID 6 and 7 respectively.  */
#define MCPCIA_HOSE2MID(h)	((h) + 4)

#define MCPCIA_MEM_MASK 0x07ffffff /* SPARSE Mem region mask is 27 bits */

/*
 * Memory spaces:
 */
#define MCPCIA_SPARSE(m)	(IDENT_ADDR + 0xf000000000UL + MCPCIA_MID(m))
#define MCPCIA_DENSE(m)		(IDENT_ADDR + 0xf100000000UL + MCPCIA_MID(m))
#define MCPCIA_IO(m)		(IDENT_ADDR + 0xf180000000UL + MCPCIA_MID(m))
#define MCPCIA_CONF(m)		(IDENT_ADDR + 0xf1c0000000UL + MCPCIA_MID(m))
#define MCPCIA_CSR(m)		(IDENT_ADDR + 0xf1e0000000UL + MCPCIA_MID(m))
#define MCPCIA_IO_IACK(m)	(IDENT_ADDR + 0xf1f0000000UL + MCPCIA_MID(m))
#define MCPCIA_DENSE_IO(m)	(IDENT_ADDR + 0xe1fc000000UL + MCPCIA_MID(m))
#define MCPCIA_DENSE_CONF(m)	(IDENT_ADDR + 0xe1fe000000UL + MCPCIA_MID(m))

/*
 *  General Registers
 */
#define MCPCIA_REV(m)		(MCPCIA_CSR(m) + 0x000)
#define MCPCIA_WHOAMI(m)	(MCPCIA_CSR(m) + 0x040)
#define MCPCIA_PCI_LAT(m)	(MCPCIA_CSR(m) + 0x080)
#define MCPCIA_CAP_CTRL(m)	(MCPCIA_CSR(m) + 0x100)
#define MCPCIA_HAE_MEM(m)	(MCPCIA_CSR(m) + 0x400)
#define MCPCIA_HAE_IO(m)	(MCPCIA_CSR(m) + 0x440)
#define _MCPCIA_IACK_SC(m)	(MCPCIA_CSR(m) + 0x480)
#define MCPCIA_HAE_DENSE(m)	(MCPCIA_CSR(m) + 0x4C0)

/*
 * Interrupt Control registers
 */
#define MCPCIA_INT_CTL(m)	(MCPCIA_CSR(m) + 0x500)
#define MCPCIA_INT_REQ(m)	(MCPCIA_CSR(m) + 0x540)
#define MCPCIA_INT_TARG(m)	(MCPCIA_CSR(m) + 0x580)
#define MCPCIA_INT_ADR(m)	(MCPCIA_CSR(m) + 0x5C0)
#define MCPCIA_INT_ADR_EXT(m)	(MCPCIA_CSR(m) + 0x600)
#define MCPCIA_INT_MASK0(m)	(MCPCIA_CSR(m) + 0x640)
#define MCPCIA_INT_MASK1(m)	(MCPCIA_CSR(m) + 0x680)
#define MCPCIA_INT_ACK0(m)	(MCPCIA_CSR(m) + 0x10003f00)
#define MCPCIA_INT_ACK1(m)	(MCPCIA_CSR(m) + 0x10003f40)

/*
 * Performance Monitor registers
 */
#define MCPCIA_PERF_MON(m)	(MCPCIA_CSR(m) + 0x300)
#define MCPCIA_PERF_CONT(m)	(MCPCIA_CSR(m) + 0x340)

/*
 * Diagnostic Registers
 */
#define MCPCIA_CAP_DIAG(m)	(MCPCIA_CSR(m) + 0x700)
#define MCPCIA_TOP_OF_MEM(m)	(MCPCIA_CSR(m) + 0x7C0)

/*
 * Error registers
 */
#define MCPCIA_MC_ERR0(m)	(MCPCIA_CSR(m) + 0x800)
#define MCPCIA_MC_ERR1(m)	(MCPCIA_CSR(m) + 0x840)
#define MCPCIA_CAP_ERR(m)	(MCPCIA_CSR(m) + 0x880)
#define MCPCIA_PCI_ERR1(m)	(MCPCIA_CSR(m) + 0x1040)
#define MCPCIA_MDPA_STAT(m)	(MCPCIA_CSR(m) + 0x4000)
#define MCPCIA_MDPA_SYN(m)	(MCPCIA_CSR(m) + 0x4040)
#define MCPCIA_MDPA_DIAG(m)	(MCPCIA_CSR(m) + 0x4080)
#define MCPCIA_MDPB_STAT(m)	(MCPCIA_CSR(m) + 0x8000)
#define MCPCIA_MDPB_SYN(m)	(MCPCIA_CSR(m) + 0x8040)
#define MCPCIA_MDPB_DIAG(m)	(MCPCIA_CSR(m) + 0x8080)

/*
 * PCI Address Translation Registers.
 */
#define MCPCIA_SG_TBIA(m)	(MCPCIA_CSR(m) + 0x1300)
#define MCPCIA_HBASE(m)		(MCPCIA_CSR(m) + 0x1340)

#define MCPCIA_W0_BASE(m)	(MCPCIA_CSR(m) + 0x1400)
#define MCPCIA_W0_MASK(m)	(MCPCIA_CSR(m) + 0x1440)
#define MCPCIA_T0_BASE(m)	(MCPCIA_CSR(m) + 0x1480)

#define MCPCIA_W1_BASE(m)	(MCPCIA_CSR(m) + 0x1500)
#define MCPCIA_W1_MASK(m)	(MCPCIA_CSR(m) + 0x1540)
#define MCPCIA_T1_BASE(m)	(MCPCIA_CSR(m) + 0x1580)

#define MCPCIA_W2_BASE(m)	(MCPCIA_CSR(m) + 0x1600)
#define MCPCIA_W2_MASK(m)	(MCPCIA_CSR(m) + 0x1640)
#define MCPCIA_T2_BASE(m)	(MCPCIA_CSR(m) + 0x1680)

#define MCPCIA_W3_BASE(m)	(MCPCIA_CSR(m) + 0x1700)
#define MCPCIA_W3_MASK(m)	(MCPCIA_CSR(m) + 0x1740)
#define MCPCIA_T3_BASE(m)	(MCPCIA_CSR(m) + 0x1780)

/* Hack!  Only words for bus 0.  */

#ifndef MCPCIA_ONE_HAE_WINDOW
#define MCPCIA_HAE_ADDRESS	MCPCIA_HAE_MEM(4)
#endif
#define MCPCIA_IACK_SC		_MCPCIA_IACK_SC(4)

/* 
 * The canonical non-remaped I/O and MEM addresses have these values
 * subtracted out.  This is arranged so that folks manipulating ISA
 * devices can use their familiar numbers and have them map to bus 0.
 */

#define MCPCIA_IO_BIAS		MCPCIA_IO(4)
#define MCPCIA_MEM_BIAS		MCPCIA_DENSE(4)

/* Offset between ram physical addresses and pci64 DAC bus addresses.  */
#define MCPCIA_DAC_OFFSET	(1UL << 40)

/*
 * Data structure for handling MCPCIA machine checks:
 */
struct el_MCPCIA_uncorrected_frame_mcheck {
	struct el_common header;
	struct el_common_EV5_uncorrectable_mcheck procdata;
};


#ifdef __KERNEL__

#ifndef __EXTERN_INLINE
#define __EXTERN_INLINE extern inline
#define __IO_EXTERN_INLINE
#endif

/*
 * I/O functions:
 *
 * MCPCIA, the RAWHIDE family PCI/memory support chipset for the EV5 (21164)
 * and EV56 (21164a) processors, can use either a sparse address mapping
 * scheme, or the so-called byte-word PCI address space, to get at PCI memory
 * and I/O.
 *
 * Unfortunately, we can't use BWIO with EV5, so for now, we always use SPARSE.
 */

/*
 * Memory functions.  64-bit and 32-bit accesses are done through
 * dense memory space, everything else through sparse space.
 *
 * For reading and writing 8 and 16 bit quantities we need to
 * go through one of the three sparse address mapping regions
 * and use the HAE_MEM CSR to provide some bits of the address.
 * The following few routines use only sparse address region 1
 * which gives 1Gbyte of accessible space which relates exactly
 * to the amount of PCI memory mapping *into* system address space.
 * See p 6-17 of the specification but it looks something like this:
 *
 * 21164 Address:
 *
 *          3         2         1
 * 9876543210987654321098765432109876543210
 * 1ZZZZ0.PCI.QW.Address............BBLL
 *
 * ZZ = SBZ
 * BB = Byte offset
 * LL = Transfer length
 *
 * PCI Address:
 *
 * 3         2         1
 * 10987654321098765432109876543210
 * HHH....PCI.QW.Address........ 00
 *
 * HHH = 31:29 HAE_MEM CSR
 *
 */

#define vip	volatile int __force *
#define vuip	volatile unsigned int __force *

#ifdef MCPCIA_ONE_HAE_WINDOW
#define MCPCIA_FROB_MMIO						\
	if (__mcpcia_is_mmio(hose)) {					\
		set_hae(hose & 0xffffffff);				\
		hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4);	\
	}
#else
#define MCPCIA_FROB_MMIO						\
	if (__mcpcia_is_mmio(hose)) {					\
		hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4);	\
	}
#endif

extern inline int __mcpcia_is_mmio(unsigned long addr)
{
	return (addr & 0x80000000UL) == 0;
}

__EXTERN_INLINE unsigned int mcpcia_ioread8(void __iomem *xaddr)
{
	unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
	unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
	unsigned long result;

	MCPCIA_FROB_MMIO;

	result = *(vip) ((addr << 5) + hose + 0x00);
	return __kernel_extbl(result, addr & 3);
}

__EXTERN_INLINE void mcpcia_iowrite8(u8 b, void __iomem *xaddr)
{
	unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
	unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
	unsigned long w;

	MCPCIA_FROB_MMIO;

	w = __kernel_insbl(b, addr & 3);
	*(vuip) ((addr << 5) + hose + 0x00) = w;
}

__EXTERN_INLINE unsigned int mcpcia_ioread16(void __iomem *xaddr)
{
	unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
	unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
	unsigned long result;

	MCPCIA_FROB_MMIO;

	result = *(vip) ((addr << 5) + hose + 0x08);
	return __kernel_extwl(result, addr & 3);
}

__EXTERN_INLINE void mcpcia_iowrite16(u16 b, void __iomem *xaddr)
{
	unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
	unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
	unsigned long w;

	MCPCIA_FROB_MMIO;

	w = __kernel_inswl(b, addr & 3);
	*(vuip) ((addr << 5) + hose + 0x08) = w;
}

__EXTERN_INLINE unsigned int mcpcia_ioread32(void __iomem *xaddr)
{
	unsigned long addr = (unsigned long)xaddr;

	if (!__mcpcia_is_mmio(addr))
		addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18;

	return *(vuip)addr;
}

__EXTERN_INLINE void mcpcia_iowrite32(u32 b, void __iomem *xaddr)
{
	unsigned long addr = (unsigned long)xaddr;

	if (!__mcpcia_is_mmio(addr))
		addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18;

	*(vuip)addr = b;
}


__EXTERN_INLINE void __iomem *mcpcia_ioportmap(unsigned long addr)
{
	return (void __iomem *)(addr + MCPCIA_IO_BIAS);
}

__EXTERN_INLINE void __iomem *mcpcia_ioremap(unsigned long addr,
					     unsigned long size)
{
	return (void __iomem *)(addr + MCPCIA_MEM_BIAS);
}

__EXTERN_INLINE int mcpcia_is_ioaddr(unsigned long addr)
{
	return addr >= MCPCIA_SPARSE(0);
}

__EXTERN_INLINE int mcpcia_is_mmio(const volatile void __iomem *xaddr)
{
	unsigned long addr = (unsigned long) xaddr;
	return __mcpcia_is_mmio(addr);
}

#undef MCPCIA_FROB_MMIO

#undef vip
#undef vuip

#undef __IO_PREFIX
#define __IO_PREFIX		mcpcia
#define mcpcia_trivial_rw_bw	2
#define mcpcia_trivial_rw_lq	1
#define mcpcia_trivial_io_bw	0
#define mcpcia_trivial_io_lq	0
#define mcpcia_trivial_iounmap	1
#include <asm/io_trivial.h>

#ifdef __IO_EXTERN_INLINE
#undef __EXTERN_INLINE
#undef __IO_EXTERN_INLINE
#endif

#endif /* __KERNEL__ */

#endif /* __ALPHA_MCPCIA__H__ */
Commit	Line	Data
1da177e4 LT	1	#ifndef __ALPHA_MCPCIA__H__
	2	#define __ALPHA_MCPCIA__H__
	3
	4	/* Define to experiment with fitting everything into one 128MB HAE window.
	5	One window per bus, that is. */
	6	#define MCPCIA_ONE_HAE_WINDOW 1
	7
	8	#include <linux/types.h>
	9	#include <linux/pci.h>
	10	#include <asm/compiler.h>
	11
	12	/*
	13	* MCPCIA is the internal name for a core logic chipset which provides
	14	* PCI access for the RAWHIDE family of systems.
	15	*
	16	* This file is based on:
	17	*
	18	* RAWHIDE System Programmer's Manual
	19	* 16-May-96
	20	* Rev. 1.4
	21	*
	22	*/
	23
	24	/------------------------------------------------------------------------*
	25
	26	I/O procedures
	27
	28	inport[b\|w\|t\|l], outport[b\|w\|t\|l] 8:16:24:32 IO xfers
	29	inportbxt: 8 bits only
	30	inport: alias of inportw
	31	outport: alias of outportw
	32
	33	inmem[b\|w\|t\|l], outmem[b\|w\|t\|l] 8:16:24:32 ISA memory xfers
	34	inmembxt: 8 bits only
	35	inmem: alias of inmemw
	36	outmem: alias of outmemw
	37
	38	*------------------------------------------------------------------------/
	39
	40
	41	/* MCPCIA ADDRESS BIT DEFINITIONS
	42	*
	43	* 3333 3333 3322 2222 2222 1111 1111 11
	44	* 9876 5432 1098 7654 3210 9876 5432 1098 7654 3210
	45	* ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
	46	* 1 000
	47	* ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
	48	* \| \|\\|
	49	* \| Byte Enable --+ \|
	50	* \| Transfer Length --+
	51	* +-- IO space, not cached
	52	*
	53	* Byte Transfer
	54	* Enable Length Transfer Byte Address
	55	* adr<6:5> adr<4:3> Length Enable Adder
	56	* ---------------------------------------------
	57	* 00 00 Byte 1110 0x000
	58	* 01 00 Byte 1101 0x020
	59	* 10 00 Byte 1011 0x040
	60	* 11 00 Byte 0111 0x060
	61	*
	62	* 00 01 Word 1100 0x008
	63	* 01 01 Word 1001 0x028 <= Not supported in this code.
	64	* 10 01 Word 0011 0x048
65	*
66	* 00 10 Tribyte 1000 0x010
67	* 01 10 Tribyte 0001 0x030
68	*
69	* 10 11 Longword 0000 0x058
70	*
71	* Note that byte enables are asserted low.
72	*
73	*/
74
1b75b05b IK	75	#define MCPCIA_MAX_HOSES 4
1b75b05b IK	76
1da177e4 LT	77	#define MCPCIA_MID(m) ((unsigned long)(m) << 33)
	78
	79	/* Dodge has PCI0 and PCI1 at MID 4 and 5 respectively.
	80	Durango adds PCI2 and PCI3 at MID 6 and 7 respectively. */
	81	#define MCPCIA_HOSE2MID(h) ((h) + 4)
	82
	83	#define MCPCIA_MEM_MASK 0x07ffffff /* SPARSE Mem region mask is 27 bits */
	84
	85	/*
	86	* Memory spaces:
	87	*/
	88	#define MCPCIA_SPARSE(m) (IDENT_ADDR + 0xf000000000UL + MCPCIA_MID(m))
	89	#define MCPCIA_DENSE(m) (IDENT_ADDR + 0xf100000000UL + MCPCIA_MID(m))
	90	#define MCPCIA_IO(m) (IDENT_ADDR + 0xf180000000UL + MCPCIA_MID(m))
	91	#define MCPCIA_CONF(m) (IDENT_ADDR + 0xf1c0000000UL + MCPCIA_MID(m))
	92	#define MCPCIA_CSR(m) (IDENT_ADDR + 0xf1e0000000UL + MCPCIA_MID(m))
	93	#define MCPCIA_IO_IACK(m) (IDENT_ADDR + 0xf1f0000000UL + MCPCIA_MID(m))
	94	#define MCPCIA_DENSE_IO(m) (IDENT_ADDR + 0xe1fc000000UL + MCPCIA_MID(m))
	95	#define MCPCIA_DENSE_CONF(m) (IDENT_ADDR + 0xe1fe000000UL + MCPCIA_MID(m))
	96
	97	/*
	98	* General Registers
	99	*/
	100	#define MCPCIA_REV(m) (MCPCIA_CSR(m) + 0x000)
	101	#define MCPCIA_WHOAMI(m) (MCPCIA_CSR(m) + 0x040)
	102	#define MCPCIA_PCI_LAT(m) (MCPCIA_CSR(m) + 0x080)
	103	#define MCPCIA_CAP_CTRL(m) (MCPCIA_CSR(m) + 0x100)
	104	#define MCPCIA_HAE_MEM(m) (MCPCIA_CSR(m) + 0x400)
	105	#define MCPCIA_HAE_IO(m) (MCPCIA_CSR(m) + 0x440)
	106	#define _MCPCIA_IACK_SC(m) (MCPCIA_CSR(m) + 0x480)
	107	#define MCPCIA_HAE_DENSE(m) (MCPCIA_CSR(m) + 0x4C0)
	108
	109	/*
	110	* Interrupt Control registers
	111	*/
	112	#define MCPCIA_INT_CTL(m) (MCPCIA_CSR(m) + 0x500)
	113	#define MCPCIA_INT_REQ(m) (MCPCIA_CSR(m) + 0x540)
	114	#define MCPCIA_INT_TARG(m) (MCPCIA_CSR(m) + 0x580)
	115	#define MCPCIA_INT_ADR(m) (MCPCIA_CSR(m) + 0x5C0)
	116	#define MCPCIA_INT_ADR_EXT(m) (MCPCIA_CSR(m) + 0x600)
	117	#define MCPCIA_INT_MASK0(m) (MCPCIA_CSR(m) + 0x640)
	118	#define MCPCIA_INT_MASK1(m) (MCPCIA_CSR(m) + 0x680)
	119	#define MCPCIA_INT_ACK0(m) (MCPCIA_CSR(m) + 0x10003f00)
	120	#define MCPCIA_INT_ACK1(m) (MCPCIA_CSR(m) + 0x10003f40)
	121
	122	/*
	123	* Performance Monitor registers
	124	*/
	125	#define MCPCIA_PERF_MON(m) (MCPCIA_CSR(m) + 0x300)
	126	#define MCPCIA_PERF_CONT(m) (MCPCIA_CSR(m) + 0x340)
	127
	128	/*
	129	* Diagnostic Registers
	130	*/
	131	#define MCPCIA_CAP_DIAG(m) (MCPCIA_CSR(m) + 0x700)
	132	#define MCPCIA_TOP_OF_MEM(m) (MCPCIA_CSR(m) + 0x7C0)
	133
	134	/*
	135	* Error registers
	136	*/
	137	#define MCPCIA_MC_ERR0(m) (MCPCIA_CSR(m) + 0x800)
	138	#define MCPCIA_MC_ERR1(m) (MCPCIA_CSR(m) + 0x840)
	139	#define MCPCIA_CAP_ERR(m) (MCPCIA_CSR(m) + 0x880)
	140	#define MCPCIA_PCI_ERR1(m) (MCPCIA_CSR(m) + 0x1040)
141	#define MCPCIA_MDPA_STAT(m) (MCPCIA_CSR(m) + 0x4000)
142	#define MCPCIA_MDPA_SYN(m) (MCPCIA_CSR(m) + 0x4040)
143	#define MCPCIA_MDPA_DIAG(m) (MCPCIA_CSR(m) + 0x4080)
144	#define MCPCIA_MDPB_STAT(m) (MCPCIA_CSR(m) + 0x8000)
145	#define MCPCIA_MDPB_SYN(m) (MCPCIA_CSR(m) + 0x8040)
146	#define MCPCIA_MDPB_DIAG(m) (MCPCIA_CSR(m) + 0x8080)
147
148	/*
149	* PCI Address Translation Registers.
150	*/
151	#define MCPCIA_SG_TBIA(m) (MCPCIA_CSR(m) + 0x1300)
152	#define MCPCIA_HBASE(m) (MCPCIA_CSR(m) + 0x1340)
153
154	#define MCPCIA_W0_BASE(m) (MCPCIA_CSR(m) + 0x1400)
155	#define MCPCIA_W0_MASK(m) (MCPCIA_CSR(m) + 0x1440)
156	#define MCPCIA_T0_BASE(m) (MCPCIA_CSR(m) + 0x1480)
157
158	#define MCPCIA_W1_BASE(m) (MCPCIA_CSR(m) + 0x1500)
159	#define MCPCIA_W1_MASK(m) (MCPCIA_CSR(m) + 0x1540)
160	#define MCPCIA_T1_BASE(m) (MCPCIA_CSR(m) + 0x1580)
161
162	#define MCPCIA_W2_BASE(m) (MCPCIA_CSR(m) + 0x1600)
163	#define MCPCIA_W2_MASK(m) (MCPCIA_CSR(m) + 0x1640)
164	#define MCPCIA_T2_BASE(m) (MCPCIA_CSR(m) + 0x1680)
165
166	#define MCPCIA_W3_BASE(m) (MCPCIA_CSR(m) + 0x1700)
167	#define MCPCIA_W3_MASK(m) (MCPCIA_CSR(m) + 0x1740)
168	#define MCPCIA_T3_BASE(m) (MCPCIA_CSR(m) + 0x1780)
169
170	/* Hack! Only words for bus 0. */
171
172	#ifndef MCPCIA_ONE_HAE_WINDOW
173	#define MCPCIA_HAE_ADDRESS MCPCIA_HAE_MEM(4)
174	#endif
175	#define MCPCIA_IACK_SC _MCPCIA_IACK_SC(4)
176
177	/*
178	* The canonical non-remaped I/O and MEM addresses have these values
179	* subtracted out. This is arranged so that folks manipulating ISA
180	* devices can use their familiar numbers and have them map to bus 0.
181	*/
182
183	#define MCPCIA_IO_BIAS MCPCIA_IO(4)
184	#define MCPCIA_MEM_BIAS MCPCIA_DENSE(4)
185
186	/* Offset between ram physical addresses and pci64 DAC bus addresses. */
187	#define MCPCIA_DAC_OFFSET (1UL << 40)
188
189	/*
190	* Data structure for handling MCPCIA machine checks:
191	*/
192	struct el_MCPCIA_uncorrected_frame_mcheck {
193	struct el_common header;
194	struct el_common_EV5_uncorrectable_mcheck procdata;
195	};
196
197
198	#ifdef __KERNEL__
199
200	#ifndef __EXTERN_INLINE
201	#define __EXTERN_INLINE extern inline
202	#define __IO_EXTERN_INLINE
203	#endif
204
205	/*
206	* I/O functions:
207	*
208	* MCPCIA, the RAWHIDE family PCI/memory support chipset for the EV5 (21164)
209	* and EV56 (21164a) processors, can use either a sparse address mapping
210	* scheme, or the so-called byte-word PCI address space, to get at PCI memory
211	* and I/O.
212	*
213	* Unfortunately, we can't use BWIO with EV5, so for now, we always use SPARSE.
214	*/
215
216	/*
217	* Memory functions. 64-bit and 32-bit accesses are done through
218	* dense memory space, everything else through sparse space.
219	*
220	* For reading and writing 8 and 16 bit quantities we need to
221	* go through one of the three sparse address mapping regions
222	* and use the HAE_MEM CSR to provide some bits of the address.
223	* The following few routines use only sparse address region 1
224	* which gives 1Gbyte of accessible space which relates exactly
225	* to the amount of PCI memory mapping into system address space.
226	* See p 6-17 of the specification but it looks something like this:
227	*
228	* 21164 Address:
229	*
230	* 3 2 1
231	* 9876543210987654321098765432109876543210
232	* 1ZZZZ0.PCI.QW.Address............BBLL
233	*
234	* ZZ = SBZ
235	* BB = Byte offset
236	* LL = Transfer length
237	*
238	* PCI Address:
239	*
240	* 3 2 1
241	* 10987654321098765432109876543210
242	* HHH....PCI.QW.Address........ 00
243	*
244	* HHH = 31:29 HAE_MEM CSR
245	*
246	*/
247
248	#define vip volatile int __force *
249	#define vuip volatile unsigned int __force *
250
251	#ifdef MCPCIA_ONE_HAE_WINDOW
252	#define MCPCIA_FROB_MMIO \
253	if (__mcpcia_is_mmio(hose)) { \
254	set_hae(hose & 0xffffffff); \
255	hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4); \
256	}
257	#else
258	#define MCPCIA_FROB_MMIO \
259	if (__mcpcia_is_mmio(hose)) { \
260	hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4); \
261	}
262	#endif
263
d559d4a2	264	extern inline int __mcpcia_is_mmio(unsigned long addr)
1da177e4 LT	265	{
	266	return (addr & 0x80000000UL) == 0;
	267	}
	268
	269	__EXTERN_INLINE unsigned int mcpcia_ioread8(void __iomem *xaddr)
	270	{
	271	unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
	272	unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
	273	unsigned long result;
	274
	275	MCPCIA_FROB_MMIO;
	276
	277	result = *(vip) ((addr << 5) + hose + 0x00);
	278	return __kernel_extbl(result, addr & 3);
	279	}
	280
	281	__EXTERN_INLINE void mcpcia_iowrite8(u8 b, void __iomem *xaddr)
	282	{
	283	unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
	284	unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
	285	unsigned long w;
	286
	287	MCPCIA_FROB_MMIO;
	288
	289	w = __kernel_insbl(b, addr & 3);
	290	*(vuip) ((addr << 5) + hose + 0x00) = w;
	291	}
	292
	293	__EXTERN_INLINE unsigned int mcpcia_ioread16(void __iomem *xaddr)
	294	{
	295	unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
	296	unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
	297	unsigned long result;
	298
	299	MCPCIA_FROB_MMIO;
	300
	301	result = *(vip) ((addr << 5) + hose + 0x08);
	302	return __kernel_extwl(result, addr & 3);
	303	}
	304
	305	__EXTERN_INLINE void mcpcia_iowrite16(u16 b, void __iomem *xaddr)
	306	{
	307	unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
	308	unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
	309	unsigned long w;
	310
	311	MCPCIA_FROB_MMIO;
	312
	313	w = __kernel_inswl(b, addr & 3);
	314	*(vuip) ((addr << 5) + hose + 0x08) = w;
	315	}
	316
	317	__EXTERN_INLINE unsigned int mcpcia_ioread32(void __iomem *xaddr)
	318	{
	319	unsigned long addr = (unsigned long)xaddr;
	320
	321	if (!__mcpcia_is_mmio(addr))
	322	addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18;
	323
	324	return *(vuip)addr;
	325	}
	326
	327	__EXTERN_INLINE void mcpcia_iowrite32(u32 b, void __iomem *xaddr)
	328	{
329	unsigned long addr = (unsigned long)xaddr;
330
331	if (!__mcpcia_is_mmio(addr))
332	addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18;
333
334	*(vuip)addr = b;
335	}
336
337
338	__EXTERN_INLINE void __iomem *mcpcia_ioportmap(unsigned long addr)
339	{
340	return (void __iomem *)(addr + MCPCIA_IO_BIAS);
341	}
342
343	__EXTERN_INLINE void __iomem *mcpcia_ioremap(unsigned long addr,
344	unsigned long size)
345	{
346	return (void __iomem *)(addr + MCPCIA_MEM_BIAS);
347	}
348
349	__EXTERN_INLINE int mcpcia_is_ioaddr(unsigned long addr)
350	{
351	return addr >= MCPCIA_SPARSE(0);
352	}
353
354	__EXTERN_INLINE int mcpcia_is_mmio(const volatile void __iomem *xaddr)
355	{
356	unsigned long addr = (unsigned long) xaddr;
357	return __mcpcia_is_mmio(addr);
358	}
359
360	#undef MCPCIA_FROB_MMIO
361
362	#undef vip
363	#undef vuip
364
365	#undef __IO_PREFIX
366	#define __IO_PREFIX mcpcia
367	#define mcpcia_trivial_rw_bw 2
368	#define mcpcia_trivial_rw_lq 1
369	#define mcpcia_trivial_io_bw 0
370	#define mcpcia_trivial_io_lq 0
371	#define mcpcia_trivial_iounmap 1
372	#include <asm/io_trivial.h>
373
374	#ifdef __IO_EXTERN_INLINE
375	#undef __EXTERN_INLINE
376	#undef __IO_EXTERN_INLINE
377	#endif
378
379	#endif /* __KERNEL__ */
380
381	#endif /* __ALPHA_MCPCIA__H__ */