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1da177e4 LT |
1 | #ifndef __ALPHA_TITAN__H__ |
2 | #define __ALPHA_TITAN__H__ | |
3 | ||
4 | #include <linux/types.h> | |
5 | #include <linux/pci.h> | |
6 | #include <asm/compiler.h> | |
7 | ||
8 | /* | |
9 | * TITAN is the internal names for a core logic chipset which provides | |
10 | * memory controller and PCI/AGP access for 21264 based systems. | |
11 | * | |
12 | * This file is based on: | |
13 | * | |
14 | * Titan Chipset Engineering Specification | |
15 | * Revision 0.12 | |
16 | * 13 July 1999 | |
17 | * | |
18 | */ | |
19 | ||
20 | /* XXX: Do we need to conditionalize on this? */ | |
21 | #ifdef USE_48_BIT_KSEG | |
22 | #define TI_BIAS 0x80000000000UL | |
23 | #else | |
24 | #define TI_BIAS 0x10000000000UL | |
25 | #endif | |
26 | ||
27 | /* | |
28 | * CChip, DChip, and PChip registers | |
29 | */ | |
30 | ||
31 | typedef struct { | |
32 | volatile unsigned long csr __attribute__((aligned(64))); | |
33 | } titan_64; | |
34 | ||
35 | typedef struct { | |
36 | titan_64 csc; | |
37 | titan_64 mtr; | |
38 | titan_64 misc; | |
39 | titan_64 mpd; | |
40 | titan_64 aar0; | |
41 | titan_64 aar1; | |
42 | titan_64 aar2; | |
43 | titan_64 aar3; | |
44 | titan_64 dim0; | |
45 | titan_64 dim1; | |
46 | titan_64 dir0; | |
47 | titan_64 dir1; | |
48 | titan_64 drir; | |
49 | titan_64 prben; | |
50 | titan_64 iic0; | |
51 | titan_64 iic1; | |
52 | titan_64 mpr0; | |
53 | titan_64 mpr1; | |
54 | titan_64 mpr2; | |
55 | titan_64 mpr3; | |
56 | titan_64 rsvd[2]; | |
57 | titan_64 ttr; | |
58 | titan_64 tdr; | |
59 | titan_64 dim2; | |
60 | titan_64 dim3; | |
61 | titan_64 dir2; | |
62 | titan_64 dir3; | |
63 | titan_64 iic2; | |
64 | titan_64 iic3; | |
65 | titan_64 pwr; | |
66 | titan_64 reserved[17]; | |
67 | titan_64 cmonctla; | |
68 | titan_64 cmonctlb; | |
69 | titan_64 cmoncnt01; | |
70 | titan_64 cmoncnt23; | |
71 | titan_64 cpen; | |
72 | } titan_cchip; | |
73 | ||
74 | typedef struct { | |
75 | titan_64 dsc; | |
76 | titan_64 str; | |
77 | titan_64 drev; | |
78 | titan_64 dsc2; | |
79 | } titan_dchip; | |
80 | ||
81 | typedef struct { | |
82 | titan_64 wsba[4]; | |
83 | titan_64 wsm[4]; | |
84 | titan_64 tba[4]; | |
85 | titan_64 pctl; | |
86 | titan_64 plat; | |
87 | titan_64 reserved0[2]; | |
88 | union { | |
89 | struct { | |
90 | titan_64 serror; | |
91 | titan_64 serren; | |
92 | titan_64 serrset; | |
93 | titan_64 reserved0; | |
94 | titan_64 gperror; | |
95 | titan_64 gperren; | |
96 | titan_64 gperrset; | |
97 | titan_64 reserved1; | |
98 | titan_64 gtlbiv; | |
99 | titan_64 gtlbia; | |
100 | titan_64 reserved2[2]; | |
101 | titan_64 sctl; | |
102 | titan_64 reserved3[3]; | |
103 | } g; | |
104 | struct { | |
105 | titan_64 agperror; | |
106 | titan_64 agperren; | |
107 | titan_64 agperrset; | |
108 | titan_64 agplastwr; | |
109 | titan_64 aperror; | |
110 | titan_64 aperren; | |
111 | titan_64 aperrset; | |
112 | titan_64 reserved0; | |
113 | titan_64 atlbiv; | |
114 | titan_64 atlbia; | |
115 | titan_64 reserved1[6]; | |
116 | } a; | |
117 | } port_specific; | |
118 | titan_64 sprst; | |
119 | titan_64 reserved1[31]; | |
120 | } titan_pachip_port; | |
121 | ||
122 | typedef struct { | |
123 | titan_pachip_port g_port; | |
124 | titan_pachip_port a_port; | |
125 | } titan_pachip; | |
126 | ||
127 | #define TITAN_cchip ((titan_cchip *)(IDENT_ADDR+TI_BIAS+0x1A0000000UL)) | |
128 | #define TITAN_dchip ((titan_dchip *)(IDENT_ADDR+TI_BIAS+0x1B0000800UL)) | |
129 | #define TITAN_pachip0 ((titan_pachip *)(IDENT_ADDR+TI_BIAS+0x180000000UL)) | |
130 | #define TITAN_pachip1 ((titan_pachip *)(IDENT_ADDR+TI_BIAS+0x380000000UL)) | |
131 | extern unsigned TITAN_agp; | |
132 | extern int TITAN_bootcpu; | |
133 | ||
134 | /* | |
135 | * TITAN PA-chip Window Space Base Address register. | |
136 | * (WSBA[0-2]) | |
137 | */ | |
138 | #define wsba_m_ena 0x1 | |
139 | #define wsba_m_sg 0x2 | |
140 | #define wsba_m_addr 0xFFF00000 | |
141 | #define wmask_k_sz1gb 0x3FF00000 | |
142 | union TPAchipWSBA { | |
143 | struct { | |
144 | unsigned wsba_v_ena : 1; | |
145 | unsigned wsba_v_sg : 1; | |
146 | unsigned wsba_v_rsvd1 : 18; | |
147 | unsigned wsba_v_addr : 12; | |
148 | unsigned wsba_v_rsvd2 : 32; | |
149 | } wsba_r_bits; | |
150 | int wsba_q_whole [2]; | |
151 | }; | |
152 | ||
153 | /* | |
154 | * TITAN PA-chip Control Register | |
155 | * This definition covers both the G-Port GPCTL and the A-PORT APCTL. | |
156 | * Bits <51:0> are the same in both cases. APCTL<63:52> are only | |
157 | * applicable to AGP. | |
158 | */ | |
159 | #define pctl_m_fbtb 0x00000001 | |
160 | #define pctl_m_thdis 0x00000002 | |
161 | #define pctl_m_chaindis 0x00000004 | |
162 | #define pctl_m_tgtlat 0x00000018 | |
163 | #define pctl_m_hole 0x00000020 | |
164 | #define pctl_m_mwin 0x00000040 | |
165 | #define pctl_m_arbena 0x00000080 | |
166 | #define pctl_m_prigrp 0x0000FF00 | |
167 | #define pctl_m_ppri 0x00010000 | |
168 | #define pctl_m_pcispd66 0x00020000 | |
169 | #define pctl_m_cngstlt 0x003C0000 | |
170 | #define pctl_m_ptpdesten 0x3FC00000 | |
171 | #define pctl_m_dpcen 0x40000000 | |
172 | #define pctl_m_apcen 0x0000000080000000UL | |
173 | #define pctl_m_dcrtv 0x0000000300000000UL | |
174 | #define pctl_m_en_stepping 0x0000000400000000UL | |
175 | #define apctl_m_rsvd1 0x000FFFF800000000UL | |
176 | #define apctl_m_agp_rate 0x0030000000000000UL | |
177 | #define apctl_m_agp_sba_en 0x0040000000000000UL | |
178 | #define apctl_m_agp_en 0x0080000000000000UL | |
179 | #define apctl_m_rsvd2 0x0100000000000000UL | |
180 | #define apctl_m_agp_present 0x0200000000000000UL | |
181 | #define apctl_agp_hp_rd 0x1C00000000000000UL | |
182 | #define apctl_agp_lp_rd 0xE000000000000000UL | |
183 | #define gpctl_m_rsvd 0xFFFFFFF800000000UL | |
184 | union TPAchipPCTL { | |
185 | struct { | |
186 | unsigned pctl_v_fbtb : 1; /* A/G [0] */ | |
187 | unsigned pctl_v_thdis : 1; /* A/G [1] */ | |
188 | unsigned pctl_v_chaindis : 1; /* A/G [2] */ | |
189 | unsigned pctl_v_tgtlat : 2; /* A/G [4:3] */ | |
190 | unsigned pctl_v_hole : 1; /* A/G [5] */ | |
191 | unsigned pctl_v_mwin : 1; /* A/G [6] */ | |
192 | unsigned pctl_v_arbena : 1; /* A/G [7] */ | |
193 | unsigned pctl_v_prigrp : 8; /* A/G [15:8] */ | |
194 | unsigned pctl_v_ppri : 1; /* A/G [16] */ | |
195 | unsigned pctl_v_pcispd66 : 1; /* A/G [17] */ | |
196 | unsigned pctl_v_cngstlt : 4; /* A/G [21:18] */ | |
197 | unsigned pctl_v_ptpdesten : 8; /* A/G [29:22] */ | |
198 | unsigned pctl_v_dpcen : 1; /* A/G [30] */ | |
199 | unsigned pctl_v_apcen : 1; /* A/G [31] */ | |
200 | unsigned pctl_v_dcrtv : 2; /* A/G [33:32] */ | |
201 | unsigned pctl_v_en_stepping :1; /* A/G [34] */ | |
202 | unsigned apctl_v_rsvd1 : 17; /* A [51:35] */ | |
203 | unsigned apctl_v_agp_rate : 2; /* A [53:52] */ | |
204 | unsigned apctl_v_agp_sba_en : 1; /* A [54] */ | |
205 | unsigned apctl_v_agp_en : 1; /* A [55] */ | |
206 | unsigned apctl_v_rsvd2 : 1; /* A [56] */ | |
207 | unsigned apctl_v_agp_present : 1; /* A [57] */ | |
208 | unsigned apctl_v_agp_hp_rd : 3; /* A [60:58] */ | |
209 | unsigned apctl_v_agp_lp_rd : 3; /* A [63:61] */ | |
210 | } pctl_r_bits; | |
211 | unsigned int pctl_l_whole [2]; | |
212 | unsigned long pctl_q_whole; | |
213 | }; | |
214 | ||
215 | /* | |
216 | * SERROR / SERREN / SERRSET | |
217 | */ | |
218 | union TPAchipSERR { | |
219 | struct { | |
220 | unsigned serr_v_lost_uecc : 1; /* [0] */ | |
221 | unsigned serr_v_uecc : 1; /* [1] */ | |
222 | unsigned serr_v_cre : 1; /* [2] */ | |
223 | unsigned serr_v_nxio : 1; /* [3] */ | |
224 | unsigned serr_v_lost_cre : 1; /* [4] */ | |
225 | unsigned serr_v_rsvd0 : 10; /* [14:5] */ | |
226 | unsigned serr_v_addr : 32; /* [46:15] */ | |
227 | unsigned serr_v_rsvd1 : 5; /* [51:47] */ | |
228 | unsigned serr_v_source : 2; /* [53:52] */ | |
229 | unsigned serr_v_cmd : 2; /* [55:54] */ | |
230 | unsigned serr_v_syn : 8; /* [63:56] */ | |
231 | } serr_r_bits; | |
232 | unsigned int serr_l_whole[2]; | |
233 | unsigned long serr_q_whole; | |
234 | }; | |
235 | ||
236 | /* | |
237 | * GPERROR / APERROR / GPERREN / APERREN / GPERRSET / APERRSET | |
238 | */ | |
239 | union TPAchipPERR { | |
240 | struct { | |
241 | unsigned long perr_v_lost : 1; /* [0] */ | |
242 | unsigned long perr_v_serr : 1; /* [1] */ | |
243 | unsigned long perr_v_perr : 1; /* [2] */ | |
244 | unsigned long perr_v_dcrto : 1; /* [3] */ | |
245 | unsigned long perr_v_sge : 1; /* [4] */ | |
246 | unsigned long perr_v_ape : 1; /* [5] */ | |
247 | unsigned long perr_v_ta : 1; /* [6] */ | |
248 | unsigned long perr_v_dpe : 1; /* [7] */ | |
249 | unsigned long perr_v_nds : 1; /* [8] */ | |
250 | unsigned long perr_v_iptpr : 1; /* [9] */ | |
251 | unsigned long perr_v_iptpw : 1; /* [10] */ | |
252 | unsigned long perr_v_rsvd0 : 3; /* [13:11] */ | |
253 | unsigned long perr_v_addr : 33; /* [46:14] */ | |
254 | unsigned long perr_v_dac : 1; /* [47] */ | |
255 | unsigned long perr_v_mwin : 1; /* [48] */ | |
256 | unsigned long perr_v_rsvd1 : 3; /* [51:49] */ | |
257 | unsigned long perr_v_cmd : 4; /* [55:52] */ | |
258 | unsigned long perr_v_rsvd2 : 8; /* [63:56] */ | |
259 | } perr_r_bits; | |
260 | unsigned int perr_l_whole[2]; | |
261 | unsigned long perr_q_whole; | |
262 | }; | |
263 | ||
264 | /* | |
265 | * AGPERROR / AGPERREN / AGPERRSET | |
266 | */ | |
267 | union TPAchipAGPERR { | |
268 | struct { | |
269 | unsigned agperr_v_lost : 1; /* [0] */ | |
270 | unsigned agperr_v_lpqfull : 1; /* [1] */ | |
271 | unsigned apgerr_v_hpqfull : 1; /* [2] */ | |
272 | unsigned agperr_v_rescmd : 1; /* [3] */ | |
273 | unsigned agperr_v_ipte : 1; /* [4] */ | |
274 | unsigned agperr_v_ptp : 1; /* [5] */ | |
275 | unsigned agperr_v_nowindow : 1; /* [6] */ | |
276 | unsigned agperr_v_rsvd0 : 8; /* [14:7] */ | |
277 | unsigned agperr_v_addr : 32; /* [46:15] */ | |
278 | unsigned agperr_v_rsvd1 : 1; /* [47] */ | |
279 | unsigned agperr_v_dac : 1; /* [48] */ | |
280 | unsigned agperr_v_mwin : 1; /* [49] */ | |
281 | unsigned agperr_v_cmd : 3; /* [52:50] */ | |
282 | unsigned agperr_v_length : 6; /* [58:53] */ | |
283 | unsigned agperr_v_fence : 1; /* [59] */ | |
284 | unsigned agperr_v_rsvd2 : 4; /* [63:60] */ | |
285 | } agperr_r_bits; | |
286 | unsigned int agperr_l_whole[2]; | |
287 | unsigned long agperr_q_whole; | |
288 | }; | |
289 | /* | |
290 | * Memory spaces: | |
291 | * Hose numbers are assigned as follows: | |
292 | * 0 - pachip 0 / G Port | |
293 | * 1 - pachip 1 / G Port | |
294 | * 2 - pachip 0 / A Port | |
295 | * 3 - pachip 1 / A Port | |
296 | */ | |
297 | #define TITAN_HOSE_SHIFT (33) | |
298 | #define TITAN_HOSE(h) (((unsigned long)(h)) << TITAN_HOSE_SHIFT) | |
299 | #define TITAN_BASE (IDENT_ADDR + TI_BIAS) | |
300 | #define TITAN_MEM(h) (TITAN_BASE+TITAN_HOSE(h)+0x000000000UL) | |
301 | #define _TITAN_IACK_SC(h) (TITAN_BASE+TITAN_HOSE(h)+0x1F8000000UL) | |
302 | #define TITAN_IO(h) (TITAN_BASE+TITAN_HOSE(h)+0x1FC000000UL) | |
303 | #define TITAN_CONF(h) (TITAN_BASE+TITAN_HOSE(h)+0x1FE000000UL) | |
304 | ||
305 | #define TITAN_HOSE_MASK TITAN_HOSE(3) | |
306 | #define TITAN_IACK_SC _TITAN_IACK_SC(0) /* hack! */ | |
307 | ||
308 | /* | |
309 | * The canonical non-remaped I/O and MEM addresses have these values | |
310 | * subtracted out. This is arranged so that folks manipulating ISA | |
311 | * devices can use their familiar numbers and have them map to bus 0. | |
312 | */ | |
313 | ||
314 | #define TITAN_IO_BIAS TITAN_IO(0) | |
315 | #define TITAN_MEM_BIAS TITAN_MEM(0) | |
316 | ||
317 | /* The IO address space is larger than 0xffff */ | |
318 | #define TITAN_IO_SPACE (TITAN_CONF(0) - TITAN_IO(0)) | |
319 | ||
320 | /* TIG Space */ | |
321 | #define TITAN_TIG_SPACE (TITAN_BASE + 0x100000000UL) | |
322 | ||
323 | /* Offset between ram physical addresses and pci64 DAC bus addresses. */ | |
324 | /* ??? Just a guess. Ought to confirm it hasn't been moved. */ | |
325 | #define TITAN_DAC_OFFSET (1UL << 40) | |
326 | ||
327 | /* | |
328 | * Data structure for handling TITAN machine checks: | |
329 | */ | |
330 | #define SCB_Q_SYSERR 0x620 | |
331 | #define SCB_Q_PROCERR 0x630 | |
332 | #define SCB_Q_SYSMCHK 0x660 | |
333 | #define SCB_Q_PROCMCHK 0x670 | |
334 | #define SCB_Q_SYSEVENT 0x680 /* environmental / system management */ | |
335 | struct el_TITAN_sysdata_mcheck { | |
336 | u64 summary; /* 0x00 */ | |
337 | u64 c_dirx; /* 0x08 */ | |
338 | u64 c_misc; /* 0x10 */ | |
339 | u64 p0_serror; /* 0x18 */ | |
340 | u64 p0_gperror; /* 0x20 */ | |
341 | u64 p0_aperror; /* 0x28 */ | |
342 | u64 p0_agperror;/* 0x30 */ | |
343 | u64 p1_serror; /* 0x38 */ | |
344 | u64 p1_gperror; /* 0x40 */ | |
345 | u64 p1_aperror; /* 0x48 */ | |
346 | u64 p1_agperror;/* 0x50 */ | |
347 | }; | |
348 | ||
349 | /* | |
350 | * System area for a privateer 680 environmental/system management mcheck | |
351 | */ | |
352 | struct el_PRIVATEER_envdata_mcheck { | |
353 | u64 summary; /* 0x00 */ | |
354 | u64 c_dirx; /* 0x08 */ | |
355 | u64 smir; /* 0x10 */ | |
356 | u64 cpuir; /* 0x18 */ | |
357 | u64 psir; /* 0x20 */ | |
358 | u64 fault; /* 0x28 */ | |
359 | u64 sys_doors; /* 0x30 */ | |
360 | u64 temp_warn; /* 0x38 */ | |
361 | u64 fan_ctrl; /* 0x40 */ | |
362 | u64 code; /* 0x48 */ | |
363 | u64 reserved; /* 0x50 */ | |
364 | }; | |
365 | ||
366 | #ifdef __KERNEL__ | |
367 | ||
368 | #ifndef __EXTERN_INLINE | |
369 | #define __EXTERN_INLINE extern inline | |
370 | #define __IO_EXTERN_INLINE | |
371 | #endif | |
372 | ||
373 | /* | |
374 | * I/O functions: | |
375 | * | |
376 | * TITAN, a 21??? PCI/memory support chipset for the EV6 (21264) | |
377 | * can only use linear accesses to get at PCI/AGP memory and I/O spaces. | |
378 | */ | |
379 | ||
380 | /* | |
381 | * Memory functions. all accesses are done through linear space. | |
382 | */ | |
025a2215 | 383 | extern void __iomem *titan_ioportmap(unsigned long addr); |
1da177e4 LT |
384 | extern void __iomem *titan_ioremap(unsigned long addr, unsigned long size); |
385 | extern void titan_iounmap(volatile void __iomem *addr); | |
386 | ||
387 | __EXTERN_INLINE int titan_is_ioaddr(unsigned long addr) | |
388 | { | |
389 | return addr >= TITAN_BASE; | |
390 | } | |
391 | ||
392 | extern int titan_is_mmio(const volatile void __iomem *addr); | |
393 | ||
394 | #undef __IO_PREFIX | |
395 | #define __IO_PREFIX titan | |
396 | #define titan_trivial_rw_bw 1 | |
397 | #define titan_trivial_rw_lq 1 | |
398 | #define titan_trivial_io_bw 1 | |
399 | #define titan_trivial_io_lq 1 | |
400 | #define titan_trivial_iounmap 0 | |
401 | #include <asm/io_trivial.h> | |
402 | ||
403 | #ifdef __IO_EXTERN_INLINE | |
404 | #undef __EXTERN_INLINE | |
405 | #undef __IO_EXTERN_INLINE | |
406 | #endif | |
407 | ||
408 | #endif /* __KERNEL__ */ | |
409 | ||
410 | #endif /* __ALPHA_TITAN__H__ */ |